Browse Source

Add a bunch of stuff for RX, but broke TX :O :/ :)

curiousmuch 4 years ago
parent
commit
b56fd06dcf
10 changed files with 1054 additions and 68 deletions
  1. 28 4
      main/board.c
  2. 3 2
      main/board.h
  3. 13 3
      main/bt_spp.c
  4. 60 31
      main/cc1200.c
  5. 2 2
      main/cc1200.h
  6. 31 4
      main/cc1200_protocol.h
  7. 4 6
      main/kiss.c
  8. 9 5
      main/kiss.h
  9. 32 11
      main/main.c
  10. 872 0
      sdkconfig\\

+ 28 - 4
main/board.c

@@ -11,14 +11,21 @@
 #include "driver/adc.h"
 #include "board.h"
 
-void enable_red_led(void)
+// Debugging IO Functions
+void enable_debug_IO(uint32_t io_num)
 {
-	gpio_set_level(RED_LED, 1);
+	gpio_set_level(io_num, 1);
 }
 
-void enable_green_led(void)
+void disable_debug_IO(uint32_t io_num)
 {
-	gpio_set_level(GREEN_LED, 1);
+	gpio_set_level(io_num, 0);
+}
+
+// Red LED Functions
+void enable_red_led(void)
+{
+	gpio_set_level(RED_LED, 1);
 }
 
 void disable_red_led(void)
@@ -26,6 +33,12 @@ void disable_red_led(void)
 	gpio_set_level(RED_LED, 0);
 }
 
+// Green LED Functions
+void enable_green_led(void)
+{
+	gpio_set_level(GREEN_LED, 1);
+}
+
 void disable_green_led(void)
 {
 	gpio_set_level(GREEN_LED, 0);
@@ -51,4 +64,15 @@ void board_init(void)
 			.intr_type = GPIO_INTR_DISABLE
 	};
 	gpio_config(&led_pin_config);
+
+	// setup debugging IO
+	gpio_config_t debug_pin_config =
+	{
+			.pin_bit_mask = (uint64_t) (BIT64(DEBUG_0)|BIT64(DEBUG_1)),
+			.mode = GPIO_MODE_OUTPUT,
+			.pull_up_en = GPIO_PULLUP_DISABLE,
+			.pull_down_en = GPIO_PULLDOWN_DISABLE,
+			.intr_type = GPIO_INTR_DISABLE
+	};
+	gpio_config(&debug_pin_config);
 }

+ 3 - 2
main/board.h

@@ -21,7 +21,6 @@
 #define CC1200		1
 #define CC1120		1
 
-
 #if CC1120
 // CC1120 - ESP32 I/O
 // NOTE: Logic Probe is connecting to RESET - Pin1
@@ -55,13 +54,15 @@
 #endif
 
 
-#define DEBUG_0 			2
+#define DEBUG_0 			16
 #define DEBUG_1				4
 
 void enable_red_led(void);
 void enable_green_led(void);
 void disable_red_led(void);
 void disable_green_led(void);
+void enable_debug_IO(uint32_t io_num);
+void disable_debug_IO(uint32_t io_num);
 void board_init(void);
 int32_t battery_measure(void);
 

+ 13 - 3
main/bt_spp.c

@@ -19,7 +19,7 @@
 #include "esp_spp_api.h"
 
 // TODO: Remove and add call back functions to tie to main
-#include "tnc_kiss.c"
+#include "kiss.c"
 
 
 // Why are these global? Should I move this to a .h settings file?
@@ -31,6 +31,15 @@ static const esp_spp_mode_t esp_spp_mode = ESP_SPP_MODE_CB;
 static const esp_spp_sec_t sec_mask = ESP_SPP_SEC_AUTHENTICATE;//ESP_SPP_SEC_AUTHENTICATE;
 static const esp_spp_role_t role_slave = ESP_SPP_ROLE_SLAVE;
 
+typedef void (* receive_cb_t)(uint8_t *p, uint16_t p_len);
+
+receive_cb_t receive_cb;
+
+void esp_set_rx_cb(void (*rx_cb)(uint8_t *p, uint16_t p_len) )
+{
+	receive_cb = rx_cb;
+}
+
 // SPP Callback
 static void esp_spp_cb(esp_spp_cb_event_t event, esp_spp_cb_param_t *param)
 {
@@ -62,8 +71,9 @@ static void esp_spp_cb(esp_spp_cb_event_t event, esp_spp_cb_param_t *param)
 		// called when SPP connection receives data
 		ESP_LOGI(SPP_TAG, "ESP_SPP_DATA_IND_EVT len=%d handle=%d", param->data_ind.len, param->data_ind.handle);
 		//esp_log_buffer_hex("", param->data_ind.data, param->data_ind.len);
-		tnc_receive(param->data_ind.data, param->data_ind.len);
-		// send data to Arrow State-Machine
+		kiss_receive(param->data_ind.data, param->data_ind.len);
+
+		// [DEBUGING] echo received data
 		// esp_spp_write(param->data_ind.handle, param->data_ind.len, param->data_ind.data);
 		break;
 	case ESP_SPP_CONG_EVT:

+ 60 - 31
main/cc1200.c

@@ -6,6 +6,8 @@
 #include <math.h>
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
+#include "freertos/semphr.h"
+#include "freertos/portmacro.h"
 #include "driver/gpio.h"
 #include "sdkconfig.h"
 #include "driver/spi_master.h"
@@ -15,6 +17,9 @@
 #include "board.h"
 #include "esp_task_wdt.h"
 #include "freertos/ringbuf.h"
+#include "esp_log.h"
+
+#define CC_TAG "CC1200_Driver"
 
 #define CC1200_WRITE_BIT 	0
 #define CC1200_READ_BIT 	BIT(1)
@@ -41,7 +46,7 @@ spi_device_interface_config_t interface_config =
 	.dummy_bits = 0,
 	.mode = 0,
 	.spics_io_num = CC1120_CS,
-	.clock_speed_hz = (APB_CLK_FREQ/20),
+	.clock_speed_hz = (APB_CLK_FREQ/8),
 	.flags = 0,
 	.queue_size = 20
 
@@ -69,19 +74,9 @@ void cc1200_gpio_init(void)
 			.pull_down_en = GPIO_PULLDOWN_DISABLE,
 			.intr_type = GPIO_INTR_DISABLE
 	};
-//	gpio_config_t debug_pin_config =
-//	{
-//			.pin_bit_mask = (uint64_t) (BIT64(DEBUG_0)|BIT64(DEBUG_1)),
-//			.mode = GPIO_MODE_OUTPUT,
-//			.pull_up_en = GPIO_PULLUP_DISABLE,
-//			.pull_down_en = GPIO_PULLDOWN_DISABLE,
-//			.intr_type = GPIO_INTR_DISABLE
-//	};
 
 	gpio_config(&reset_pin_config);
 	gpio_config(&gpio_pin_config);
-	//gpio_config(&debug_pin_config);
-
 
 	gpio_set_level(CC1120_RESET, 1);
 
@@ -232,7 +227,7 @@ rf_status_t IRAM_ATTR cc1200_spi_strobe(uint8_t cmd)
 			.command_bits = 0,
 			.address_bits = 0
 	};
-	ret = spi_device_transmit(spi, (spi_transaction_t*)&rx_trans_ext);
+	ret = spi_device_polling_transmit(spi, (spi_transaction_t*)&rx_trans_ext); // switched to spi poll as test
 	ESP_ERROR_CHECK(ret);
 	return (temp & 0xF0);
 }
@@ -293,6 +288,14 @@ esp_err_t cc1200_radio_power(uint8_t txPower)
 	return ESP_OK;
 }
 
+void cc1200_radio_write(const cc1200_reg_settings_t* rf_settings, uint8_t len)
+{
+	uint8_t i;
+	for (i=0;i<len;i++)
+	{
+		cc1200_spi_write_byte(rf_settings[i].addr, rf_settings[i].data);
+	}
+}
 
 #define HDLC_FLAG 0x7E
 #define HDLC_FLAG_LEN 10
@@ -369,7 +372,7 @@ static void IRAM_ATTR cc1200_aprs_tx_isr(void* arg)
     new_sample = 1;
 
 	toggle = toggle ^ 1;
-	//gpio_set_level(DEBUG_1, toggle);
+	gpio_set_level(DEBUG_1, toggle);
 }
 
 void cc1200_lut_init(void)
@@ -387,6 +390,14 @@ void cc1200_lut_init(void)
 
 void IRAM_ATTR cc1200_radio_APRSTXPacket(uint8_t  *f, uint16_t f_len, uint8_t tx_delay, uint8_t tx_tail)
 {
+	// acquire SPI bus for fastest possible SPI transactions
+	spi_device_acquire_bus(spi, portMAX_DELAY);
+
+	vTaskSuspendAll();
+
+	// setup data rate for CFM TX
+	cc1200_radio_write(APRS_TX_RATE, sizeof(APRS_TX_RATE)/sizeof(cc1200_reg_settings_t));
+
 	// start CW transmission
 	cc1200_spi_write_byte(CC120X_FIFO, 0x12);
 	cc1200_spi_strobe(CC120X_STX);
@@ -397,8 +408,6 @@ void IRAM_ATTR cc1200_radio_APRSTXPacket(uint8_t  *f, uint16_t f_len, uint8_t tx
 	gpio_isr_handler_add(CC1120_GPIO3, cc1200_aprs_tx_isr, NULL);
 	gpio_set_intr_type(CC1120_GPIO3, GPIO_INTR_POSEDGE);
 
-	// acquire SPI bus for fastest possible SPI transactions
-	spi_device_acquire_bus(spi, portMAX_DELAY);
 
 
 	int16_t i,j;
@@ -549,45 +558,65 @@ void IRAM_ATTR cc1200_radio_APRSTXPacket(uint8_t  *f, uint16_t f_len, uint8_t tx
 			}
 		}
 		cc1200_spi_strobe(CC120X_SIDLE);
+		//cc1200_spi_strobe(CC120X_SFTX);
+		xTaskResumeAll();
 		spi_device_release_bus(spi);
 		gpio_uninstall_isr_service();
-
 }
 
-RingbufHandle_t cfm_buf_handle;
+extern SemaphoreHandle_t xRadioRXSemaphore;
 
 static void IRAM_ATTR cc1200_aprs_rx_isr(void* arg)
 {
+
 	//uint8_t data = 0;
+    //cc1200_spi_read_byte(CC120X_CFM_RX_DATA_OUT, &data);
+	static BaseType_t xHigherPriorityTaskWoken;
 
-	cc1200_spi_read_byte(CC120X_CFM_RX_DATA_OUT, &data);
 
-	toggle = toggle ^ 1;
-	//gpio_set_level(DEBUG_1, toggle);
-	xRingbufferSendFromISR(cfm_buf_handle, &data, sizeof(data), NULL);
+	gpio_set_intr_type(CC1120_GPIO2, GPIO_INTR_DISABLE);
+
+	xSemaphoreGiveFromISR(xRadioRXSemaphore, &xHigherPriorityTaskWoken);
+	if (xHigherPriorityTaskWoken == pdTRUE)
+	{
+		portYIELD_FROM_ISR( );
+	}
+
+	//cc1200_spi_read_byte(CC120X_RSSI1, &data);
+
+	//toggle = toggle ^ 1;
+	//	gpio_set_level(DEBUG_0, toggle);
+	//xRingbufferSendFromISR(cfm_buf_handle, &data, sizeof(data), NULL);
 	//ets_write_char_uart(data);
     //new_sample = 1;
 
+
 }
 
-void IRAM_ATTR cc1200_radio_APRSRXPacket(void)
+void IRAM_ATTR cc1200_radio_start_APRSRX(void)
 {
-	printf("Starting Continuous RX\n");
-	// start RX transmission
-	//cc1120_spi_write_byte(CC112X_FIFO, 0x12);
-	cc1200_spi_strobe(CC120X_SRX);
-	vTaskDelay(20/portTICK_PERIOD_MS);
-	cc1200_spi_strobe(CC120X_SRX);
-
 	// acquire SPI bus for fastest possible SPI transactions
 	spi_device_acquire_bus(spi, portMAX_DELAY);
 
+	//vTaskSuspendAll();
+
+	// start RX transmission
+	cc1200_radio_write(APRS_RX_RATE, sizeof(APRS_RX_RATE)/sizeof(cc1200_reg_settings_t));
+	while(cc1200_spi_strobe(CC120X_SRX) != CC120X_STATE_RX);
+
+
 	// enable interrupt pin for CC1120 for timing packets
 	gpio_install_isr_service(ESP_INTR_FLAG_IRAM);
 
-	gpio_isr_handler_add(CC1120_GPIO3, cc1200_aprs_rx_isr, NULL);
-	gpio_set_intr_type(CC1120_GPIO3, GPIO_INTR_POSEDGE);
+	gpio_isr_handler_add(CC1120_GPIO2, cc1200_aprs_rx_isr, NULL);
+	gpio_set_intr_type(CC1120_GPIO2, GPIO_INTR_POSEDGE);
+}
 
+void cc1200_radio_stop_APRSRX(void)
+{
+	gpio_uninstall_isr_service();
+	cc1200_spi_strobe(CC120X_SIDLE);
+	spi_device_release_bus(spi);
 }
 
 void cc1200_radio_init(const cc1200_reg_settings_t* rf_settings, uint8_t len)

+ 2 - 2
main/cc1200.h

@@ -290,8 +290,8 @@ esp_err_t cc1200_radio_frequency(uint32_t);
 rf_status_t cc1200_radio_reset(void);
 esp_err_t cc1200_radio_sleep(void);
 void cc1200_radio_APRSTXPacket(uint8_t  *f, uint16_t f_len, uint8_t tx_delay, uint8_t tx_tail);
-void cc1200_radio_APRSRXPacket(void);
-
+void cc1200_radio_start_APRSRX(void);
+void cc1200_radio_stop_APRSRX(void);
 
 #endif// CC120X_SPI_H
 

+ 31 - 4
main/cc1200_protocol.h

@@ -5,6 +5,14 @@
  *      Author: curiousmuch
  */
 
+//*********************************//
+// IMPORTANT GPIO SIGNALS
+// REG		DESCRIPTION
+// 0x1e		TX CLK
+// 0x1d		RX_CLK
+// 0x10		Carrier Sense Valid
+// 0x11		Carrier Sense
+//********************************//
 
 // Address Config = No address check
 // Bit Rate = 0.825
@@ -24,18 +32,37 @@
 #include <stdint.h>
 #include "cc1200.h"
 
+// Bit Rate = 0.825kHz
+static const cc1200_reg_settings_t APRS_TX_RATE[]=
+{
+		{CC120X_SYMBOL_RATE2, 0x35},
+		{CC120X_SYMBOL_RATE1, 0xA0},
+		{CC120X_SYMBOL_RATE0, 0x7B}
+};
+
+// Bit Rate = 13.2kHz
+static const cc1200_reg_settings_t APRS_RX_RATE[]=
+{
+		{CC120X_SYMBOL_RATE2, 0x75},
+		{CC120X_SYMBOL_RATE1, 0xA0},
+		{CC120X_SYMBOL_RATE0, 0x7B}
+};
+
 static const cc1200_reg_settings_t APRS_SETTINGS[]=
 {
-  {CC120X_IOCFG3,            0x1e},	// 0x1e for TX 0x1D for RX
+  {CC120X_IOCFG3,            0x1e},	// TX Clock
+  {CC120X_IOCFG2,			 0x1d},	// RX Clock
   {CC120X_IOCFG0,            0x09},
-  {CC120X_SYNC_CFG1,         0xAB},
+  {CC120X_SYNC_CFG1,         0xAB},	// Disable Sync Word [0x00]
+  //{CC120X_SYNC_CFG0,		 0x03}, // Disable RX_CONFIG_LIMITATION 0x13
   {CC120X_DEVIATION_M,       0x9D},
   {CC120X_MODCFG_DEV_E,      0x00},
   {CC120X_DCFILT_CFG,        0x5D},
   {CC120X_PREAMBLE_CFG1,     0x00},
-  {CC120X_PREAMBLE_CFG0,     0x8A},
+  {CC120X_PREAMBLE_CFG0,     0x8A},	// Disable Preamble [0x00]
   {CC120X_IQIC,              0xCB},
   {CC120X_CHAN_BW,           0x9C},
+  //{CC120X_MDMCFG1, 			 0x00},	// Random guess
   {CC120X_MDMCFG0,           0x05},
   {CC120X_SYMBOL_RATE2,      0x35},
   {CC120X_SYMBOL_RATE1,      0xA0},
@@ -53,7 +80,7 @@ static const cc1200_reg_settings_t APRS_SETTINGS[]=
   {CC120X_PKT_LEN,           0x3F},
   {CC120X_IF_MIX_CFG,        0x1C},
   {CC120X_FREQOFF_CFG,       0x22},
-  {CC120X_MDMCFG2,           0x0D},		// need to set CFM_DATA_EN bit for CFM mode
+  {CC120X_MDMCFG2,           0x0D},		// need to set CFM_DATA_EN bit for CFM mode and reduce upsampler rate
   {CC120X_FREQ2,             0x56},
   {CC120X_FREQ1,             0x81},
   {CC120X_FREQ0,             0x47},

+ 4 - 6
main/kiss.c

@@ -12,11 +12,9 @@
 #include "freertos/ringbuf.h"
 #include "esp_log.h"
 #include <stdio.h>
-#include "tnc_kiss.h"
-
-// TODO: remove and use call back function for TNC
 #include "cc1200.h"
 #include "fcs_calc.h"
+#include "kiss.h"
 
 buffer_handle_t buffer_handle;
 tnc_settings_t tnc_settings;
@@ -103,7 +101,7 @@ void kiss_process_frame(void)
 	return;
 }
 
-void tnc_set_paramters(tnc_settings_t s)
+void kiss_set_tnc_paramters(tnc_settings_t s)
 {
 		tnc_settings.tx_delay = s.tx_delay;
 		tnc_settings.persistence = s.persistence;
@@ -117,7 +115,7 @@ void tnc_set_paramters(tnc_settings_t s)
 // TNC needs the ability to RX KISS frame, decode it, schedule it, and then send out via APRS or Arrow-Net
 // TNC needs the ability to switch to RX mode,
 
-void tnc_init(void)
+void kiss_init(void)
 {
 	buffer_handle.max_len = FRAME_BUFFER_SIZE;			// TODO: make frame buffer dynamic
 //	tnc_settings.max_frame_size = FRAME_BUFFER_SIZE;
@@ -143,7 +141,7 @@ void tnc_init(void)
 // If the frame is not completed, the state machine will wait until more data is provided by the SPP interface.
 // If the frame is corrupted or the buffer fills, the frame will be dumped and the error must be logged.
 KISS_STATE_t kiss_state = FRAME_END;
-void tnc_receive(uint8_t* data, uint16_t len)
+void kiss_receive(uint8_t* data, uint16_t len)
 {
 	uint32_t i;
 	uint8_t chr;

+ 9 - 5
main/kiss.h

@@ -5,11 +5,11 @@
  *      Author: curiousmuch
  */
 
-#ifndef MAIN_TNC_KISS_H_
-#define MAIN_TNC_KISS_H_
+#ifndef MAIN_KISS_H_
+#define MAIN_KISS_H_
 
 // Logging Tag
-#define TNC_TAG "KISS TNC"
+#define TNC_TAG "KISS"
 
 // Frame Buffer
 #define FRAME_BUFFER_SIZE 512
@@ -32,8 +32,6 @@
 #define KISS_CMD_SETHARDWARE	0x06
 #define KISS_CMD_RETURN			0xFF
 
-
-
 // TXDELAY: TX keyup delay in 10 ms units. Default = 50 (500ms)
 // P: Persistence scaled 0 - 255. P = p *256 -1. Default = 63 (p = 0.25)
 // SlotTime: Slot interval in 10ms units. Default = 10 (100ms)
@@ -50,6 +48,7 @@
 	uint8_t full_duplex;
 } tnc_settings_t;
 
+
 typedef enum {
 	ESC_MODE = 0,
 	FRAME_ASS,
@@ -79,6 +78,11 @@ typedef struct {
 	uint16_t len;
 } raw_ax25_frame_t;
 
+/* Public Functions */
+void kiss_receive(uint8_t *data, uint16_t len);
+void kiss_init(void);
+void kiss_configure(void);
+
 
 
 #endif /* MAIN_TNC_KISS_H_ */

+ 32 - 11
main/main.c

@@ -5,6 +5,7 @@
 #include <stdio.h>
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
+#include "freertos/semphr.h"
 #include "driver/gpio.h"
 #include "sdkconfig.h"
 #include "esp_task_wdt.h"
@@ -13,10 +14,6 @@
 #include "cc1200_protocol.h"
 #include "board.h"
 
-#include "ax25_pad2.h"
-#include "ax25_pad.h"
-#include "fcs_calc.h"
-
 #include "nvs.h"
 #include "nvs_flash.h"
 #include "esp_log.h"
@@ -27,6 +24,9 @@
 #include "esp_spp_api.h"
 #include "bt_spp.c"
 
+#include "ax25_pad2.h"
+#include "ax25_pad.h"
+#include "fcs_calc.h"
 
 uint8_t APRS_TEST_PACKET[] = { 0x82, 0x98, 0x98, 0x40, 0x40, 0x40, 0xe0, 0x96, 0x84, 0x66, 0xaa, 0x96, 0xac, 0xe0, 0xae, 0x92,
 									 0x88, 0x8a, 0x62, 0x40, 0x62, 0xae, 0x92, 0x88, 0x8a, 0x64, 0x40, 0x65, 0x03, 0xf0, 0x3a, 0x4b,
@@ -34,19 +34,23 @@ uint8_t APRS_TEST_PACKET[] = { 0x82, 0x98, 0x98, 0x40, 0x40, 0x40, 0xe0, 0x96, 0
 									 0x20, 0x69, 0x73, 0x20, 0x61, 0x20, 0x54, 0x65, 0x73, 0x74, 0x7b, 0x31, 0xad, 0xa1 };
 
 RingbufHandle_t radio_tx_buf;
+SemaphoreHandle_t xRadioRXSemaphore;
 //RingbufHandle_t radio_rx_buf;
 
 void Radio_Task(void *pvParameters)
 {
 	size_t p_size;
 
+	// create sempahore
+	xRadioRXSemaphore = xSemaphoreCreateBinary();
+
 	// Setup Radio
 	cc1200_radio_init(APRS_SETTINGS, sizeof(APRS_SETTINGS)/sizeof(cc1200_reg_settings_t));
 	cc1200_radio_frequency(144390000-6000);
 
-	vTaskDelay(500/portTICK_PERIOD_MS);
-
+	cc1200_radio_start_APRSRX();
 
+	uint8_t toggle=0;
 
 	while(1)
 	{
@@ -54,27 +58,44 @@ void Radio_Task(void *pvParameters)
 		enable_green_led();
 		disable_red_led();
 
+		//cc1200_radio_start_APRSRX();
+		if (xSemaphoreTake(xRadioRXSemaphore, 0) == pdTRUE)
+		{
+			toggle = toggle ^ 1;
+			gpio_set_level(DEBUG_0, toggle);
+			gpio_set_intr_type(CC1120_GPIO2, GPIO_INTR_POSEDGE);
+		}
 
-		// Transmit Queued Packet
-		uint8_t *p = (uint8_t *)xRingbufferReceive(radio_tx_buf, &p_size, portMAX_DELAY);	// TODO: Modify to something which will check CC1200 status
+		//esp_task_wdt_reset();
 
+
+		// Transmit Queued Packet
+		uint8_t *p = (uint8_t *)xRingbufferReceive(radio_tx_buf, &p_size, 0);	// TODO: Modify to something which will check CC1200 status
 		if (p != NULL)
 		{
+			// disable RX mode
+			cc1200_radio_stop_APRSRX();
+
 			// setup LEDs for TX mode
 			enable_red_led();
 			disable_green_led();
 
-			//vTaskSuspendAll();
 
 			cc1200_radio_APRSTXPacket(p, p_size, 2, 0);
 
-			//xTaskResumeAll();
 			vRingbufferReturnItem(radio_tx_buf, (void *)p);
 
+			cc1200_radio_start_APRSRX();
 		}
     }
 }
 
+//void UART_Task(void *pvParameters)
+//{
+//
+//}
+//
+
 
 void radio_task_init()
 {
@@ -99,7 +120,7 @@ void IRAM_ATTR app_main()
 	radio_task_init();
 
 	// Setup Kiss Decoder and Encoder
-	tnc_init();
+	kiss_init();
 
 	// Initalize BLE
 	bt_spp_init();

+ 872 - 0
sdkconfig\\

@@ -0,0 +1,872 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Espressif IoT Development Framework Configuration
+#
+
+#
+# SDK tool configuration
+#
+CONFIG_TOOLPREFIX="xtensa-esp32-elf-"
+CONFIG_PYTHON="python2"
+CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y
+
+#
+# Bootloader config
+#
+CONFIG_LOG_BOOTLOADER_LEVEL_NONE=
+CONFIG_LOG_BOOTLOADER_LEVEL_ERROR=
+CONFIG_LOG_BOOTLOADER_LEVEL_WARN=
+CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y
+CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG=
+CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE=
+CONFIG_LOG_BOOTLOADER_LEVEL=3
+CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V=
+CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y
+CONFIG_BOOTLOADER_FACTORY_RESET=
+CONFIG_BOOTLOADER_APP_TEST=
+CONFIG_BOOTLOADER_WDT_ENABLE=y
+CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE=
+CONFIG_BOOTLOADER_WDT_TIME_MS=9000
+
+#
+# Security features
+#
+CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT=
+CONFIG_SECURE_BOOT_ENABLED=
+CONFIG_FLASH_ENCRYPTION_ENABLED=
+
+#
+# Serial flasher config
+#
+CONFIG_ESPTOOLPY_PORT="/dev/ttyUSB1"
+CONFIG_ESPTOOLPY_BAUD_115200B=y
+CONFIG_ESPTOOLPY_BAUD_230400B=
+CONFIG_ESPTOOLPY_BAUD_921600B=
+CONFIG_ESPTOOLPY_BAUD_2MB=
+CONFIG_ESPTOOLPY_BAUD_OTHER=
+CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
+CONFIG_ESPTOOLPY_BAUD=115200
+CONFIG_ESPTOOLPY_COMPRESSED=y
+CONFIG_FLASHMODE_QIO=
+CONFIG_FLASHMODE_QOUT=
+CONFIG_FLASHMODE_DIO=y
+CONFIG_FLASHMODE_DOUT=
+CONFIG_ESPTOOLPY_FLASHMODE="dio"
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=
+CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
+CONFIG_ESPTOOLPY_FLASHFREQ_26M=
+CONFIG_ESPTOOLPY_FLASHFREQ_20M=
+CONFIG_ESPTOOLPY_FLASHFREQ="40m"
+CONFIG_ESPTOOLPY_FLASHSIZE_1MB=
+CONFIG_ESPTOOLPY_FLASHSIZE_2MB=
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESPTOOLPY_FLASHSIZE_8MB=
+CONFIG_ESPTOOLPY_FLASHSIZE_16MB=
+CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
+CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
+CONFIG_ESPTOOLPY_BEFORE_RESET=y
+CONFIG_ESPTOOLPY_BEFORE_NORESET=
+CONFIG_ESPTOOLPY_BEFORE="default_reset"
+CONFIG_ESPTOOLPY_AFTER_RESET=y
+CONFIG_ESPTOOLPY_AFTER_NORESET=
+CONFIG_ESPTOOLPY_AFTER="hard_reset"
+CONFIG_MONITOR_BAUD_9600B=
+CONFIG_MONITOR_BAUD_57600B=
+CONFIG_MONITOR_BAUD_115200B=y
+CONFIG_MONITOR_BAUD_230400B=
+CONFIG_MONITOR_BAUD_921600B=
+CONFIG_MONITOR_BAUD_2MB=
+CONFIG_MONITOR_BAUD_OTHER=
+CONFIG_MONITOR_BAUD_OTHER_VAL=115200
+CONFIG_MONITOR_BAUD=115200
+
+#
+# Example Configuration
+#
+CONFIG_BLINK_GPIO=5
+
+#
+# Partition Table
+#
+CONFIG_PARTITION_TABLE_SINGLE_APP=y
+CONFIG_PARTITION_TABLE_TWO_OTA=
+CONFIG_PARTITION_TABLE_CUSTOM=
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
+CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv"
+CONFIG_PARTITION_TABLE_OFFSET=0x8000
+CONFIG_PARTITION_TABLE_MD5=y
+
+#
+# Compiler options
+#
+CONFIG_OPTIMIZATION_LEVEL_DEBUG=y
+CONFIG_OPTIMIZATION_LEVEL_RELEASE=
+CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
+CONFIG_OPTIMIZATION_ASSERTIONS_SILENT=
+CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED=
+CONFIG_CXX_EXCEPTIONS=
+CONFIG_STACK_CHECK_NONE=y
+CONFIG_STACK_CHECK_NORM=
+CONFIG_STACK_CHECK_STRONG=
+CONFIG_STACK_CHECK_ALL=
+CONFIG_STACK_CHECK=
+CONFIG_WARN_WRITE_STRINGS=
+CONFIG_DISABLE_GCC8_WARNINGS=
+
+#
+# Component config
+#
+
+#
+# Application Level Tracing
+#
+CONFIG_ESP32_APPTRACE_DEST_TRAX=
+CONFIG_ESP32_APPTRACE_DEST_NONE=y
+CONFIG_ESP32_APPTRACE_ENABLE=
+CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
+CONFIG_AWS_IOT_SDK=
+
+#
+# Bluetooth
+#
+CONFIG_BT_ENABLED=y
+
+#
+# Bluetooth controller
+#
+CONFIG_BTDM_CONTROLLER_MODE_BLE_ONLY=
+CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY=y
+CONFIG_BTDM_CONTROLLER_MODE_BTDM=
+CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN=2
+CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN=0
+CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0
+CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=2
+CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0
+CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_0=y
+CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_1=
+CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0
+CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI=y
+CONFIG_BTDM_CONTROLLER_HCI_MODE_UART_H4=
+
+#
+# MODEM SLEEP Options
+#
+CONFIG_BTDM_CONTROLLER_MODEM_SLEEP=y
+CONFIG_BTDM_MODEM_SLEEP_MODE_ORIG=y
+CONFIG_BTDM_MODEM_SLEEP_MODE_EVED=
+CONFIG_BTDM_LPCLK_SEL_MAIN_XTAL=y
+CONFIG_BLUEDROID_ENABLED=y
+CONFIG_BLUEDROID_PINNED_TO_CORE_0=y
+CONFIG_BLUEDROID_PINNED_TO_CORE_1=
+CONFIG_BLUEDROID_PINNED_TO_CORE=0
+CONFIG_BTC_TASK_STACK_SIZE=3072
+CONFIG_BLUEDROID_MEM_DEBUG=
+CONFIG_CLASSIC_BT_ENABLED=y
+CONFIG_A2DP_ENABLE=
+CONFIG_BT_SPP_ENABLED=y
+CONFIG_HFP_ENABLE=
+CONFIG_BT_STACK_NO_LOG=
+
+#
+# BT DEBUG LOG LEVEL
+#
+CONFIG_HCI_TRACE_LEVEL_NONE=
+CONFIG_HCI_TRACE_LEVEL_ERROR=
+CONFIG_HCI_TRACE_LEVEL_WARNING=y
+CONFIG_HCI_TRACE_LEVEL_API=
+CONFIG_HCI_TRACE_LEVEL_EVENT=
+CONFIG_HCI_TRACE_LEVEL_DEBUG=
+CONFIG_HCI_TRACE_LEVEL_VERBOSE=
+CONFIG_HCI_INITIAL_TRACE_LEVEL=2
+CONFIG_BTM_TRACE_LEVEL_NONE=
+CONFIG_BTM_TRACE_LEVEL_ERROR=
+CONFIG_BTM_TRACE_LEVEL_WARNING=y
+CONFIG_BTM_TRACE_LEVEL_API=
+CONFIG_BTM_TRACE_LEVEL_EVENT=
+CONFIG_BTM_TRACE_LEVEL_DEBUG=
+CONFIG_BTM_TRACE_LEVEL_VERBOSE=
+CONFIG_BTM_INITIAL_TRACE_LEVEL=2
+CONFIG_L2CAP_TRACE_LEVEL_NONE=
+CONFIG_L2CAP_TRACE_LEVEL_ERROR=
+CONFIG_L2CAP_TRACE_LEVEL_WARNING=y
+CONFIG_L2CAP_TRACE_LEVEL_API=
+CONFIG_L2CAP_TRACE_LEVEL_EVENT=
+CONFIG_L2CAP_TRACE_LEVEL_DEBUG=
+CONFIG_L2CAP_TRACE_LEVEL_VERBOSE=
+CONFIG_L2CAP_INITIAL_TRACE_LEVEL=2
+CONFIG_RFCOMM_TRACE_LEVEL_NONE=
+CONFIG_RFCOMM_TRACE_LEVEL_ERROR=
+CONFIG_RFCOMM_TRACE_LEVEL_WARNING=y
+CONFIG_RFCOMM_TRACE_LEVEL_API=
+CONFIG_RFCOMM_TRACE_LEVEL_EVENT=
+CONFIG_RFCOMM_TRACE_LEVEL_DEBUG=
+CONFIG_RFCOMM_TRACE_LEVEL_VERBOSE=
+CONFIG_RFCOMM_INITIAL_TRACE_LEVEL=2
+CONFIG_SDP_TRACE_LEVEL_NONE=
+CONFIG_SDP_TRACE_LEVEL_ERROR=
+CONFIG_SDP_TRACE_LEVEL_WARNING=y
+CONFIG_SDP_TRACE_LEVEL_API=
+CONFIG_SDP_TRACE_LEVEL_EVENT=
+CONFIG_SDP_TRACE_LEVEL_DEBUG=
+CONFIG_SDP_TRACE_LEVEL_VERBOSE=
+CONFIG_SDP_INITIAL_TRACE_LEVEL=2
+CONFIG_GAP_TRACE_LEVEL_NONE=
+CONFIG_GAP_TRACE_LEVEL_ERROR=
+CONFIG_GAP_TRACE_LEVEL_WARNING=y
+CONFIG_GAP_TRACE_LEVEL_API=
+CONFIG_GAP_TRACE_LEVEL_EVENT=
+CONFIG_GAP_TRACE_LEVEL_DEBUG=
+CONFIG_GAP_TRACE_LEVEL_VERBOSE=
+CONFIG_GAP_INITIAL_TRACE_LEVEL=2
+CONFIG_BNEP_TRACE_LEVEL_NONE=
+CONFIG_BNEP_TRACE_LEVEL_ERROR=
+CONFIG_BNEP_TRACE_LEVEL_WARNING=y
+CONFIG_BNEP_TRACE_LEVEL_API=
+CONFIG_BNEP_TRACE_LEVEL_EVENT=
+CONFIG_BNEP_TRACE_LEVEL_DEBUG=
+CONFIG_BNEP_TRACE_LEVEL_VERBOSE=
+CONFIG_BNEP_INITIAL_TRACE_LEVEL=2
+CONFIG_PAN_TRACE_LEVEL_NONE=
+CONFIG_PAN_TRACE_LEVEL_ERROR=
+CONFIG_PAN_TRACE_LEVEL_WARNING=y
+CONFIG_PAN_TRACE_LEVEL_API=
+CONFIG_PAN_TRACE_LEVEL_EVENT=
+CONFIG_PAN_TRACE_LEVEL_DEBUG=
+CONFIG_PAN_TRACE_LEVEL_VERBOSE=
+CONFIG_PAN_INITIAL_TRACE_LEVEL=2
+CONFIG_A2D_TRACE_LEVEL_NONE=
+CONFIG_A2D_TRACE_LEVEL_ERROR=
+CONFIG_A2D_TRACE_LEVEL_WARNING=y
+CONFIG_A2D_TRACE_LEVEL_API=
+CONFIG_A2D_TRACE_LEVEL_EVENT=
+CONFIG_A2D_TRACE_LEVEL_DEBUG=
+CONFIG_A2D_TRACE_LEVEL_VERBOSE=
+CONFIG_A2D_INITIAL_TRACE_LEVEL=2
+CONFIG_AVDT_TRACE_LEVEL_NONE=
+CONFIG_AVDT_TRACE_LEVEL_ERROR=
+CONFIG_AVDT_TRACE_LEVEL_WARNING=y
+CONFIG_AVDT_TRACE_LEVEL_API=
+CONFIG_AVDT_TRACE_LEVEL_EVENT=
+CONFIG_AVDT_TRACE_LEVEL_DEBUG=
+CONFIG_AVDT_TRACE_LEVEL_VERBOSE=
+CONFIG_AVDT_INITIAL_TRACE_LEVEL=2
+CONFIG_AVCT_TRACE_LEVEL_NONE=
+CONFIG_AVCT_TRACE_LEVEL_ERROR=
+CONFIG_AVCT_TRACE_LEVEL_WARNING=y
+CONFIG_AVCT_TRACE_LEVEL_API=
+CONFIG_AVCT_TRACE_LEVEL_EVENT=
+CONFIG_AVCT_TRACE_LEVEL_DEBUG=
+CONFIG_AVCT_TRACE_LEVEL_VERBOSE=
+CONFIG_AVCT_INITIAL_TRACE_LEVEL=2
+CONFIG_AVRC_TRACE_LEVEL_NONE=
+CONFIG_AVRC_TRACE_LEVEL_ERROR=
+CONFIG_AVRC_TRACE_LEVEL_WARNING=y
+CONFIG_AVRC_TRACE_LEVEL_API=
+CONFIG_AVRC_TRACE_LEVEL_EVENT=
+CONFIG_AVRC_TRACE_LEVEL_DEBUG=
+CONFIG_AVRC_TRACE_LEVEL_VERBOSE=
+CONFIG_AVRC_INITIAL_TRACE_LEVEL=2
+CONFIG_MCA_TRACE_LEVEL_NONE=
+CONFIG_MCA_TRACE_LEVEL_ERROR=
+CONFIG_MCA_TRACE_LEVEL_WARNING=y
+CONFIG_MCA_TRACE_LEVEL_API=
+CONFIG_MCA_TRACE_LEVEL_EVENT=
+CONFIG_MCA_TRACE_LEVEL_DEBUG=
+CONFIG_MCA_TRACE_LEVEL_VERBOSE=
+CONFIG_MCA_INITIAL_TRACE_LEVEL=2
+CONFIG_HID_TRACE_LEVEL_NONE=
+CONFIG_HID_TRACE_LEVEL_ERROR=
+CONFIG_HID_TRACE_LEVEL_WARNING=y
+CONFIG_HID_TRACE_LEVEL_API=
+CONFIG_HID_TRACE_LEVEL_EVENT=
+CONFIG_HID_TRACE_LEVEL_DEBUG=
+CONFIG_HID_TRACE_LEVEL_VERBOSE=
+CONFIG_HID_INITIAL_TRACE_LEVEL=2
+CONFIG_APPL_TRACE_LEVEL_NONE=
+CONFIG_APPL_TRACE_LEVEL_ERROR=
+CONFIG_APPL_TRACE_LEVEL_WARNING=y
+CONFIG_APPL_TRACE_LEVEL_API=
+CONFIG_APPL_TRACE_LEVEL_EVENT=
+CONFIG_APPL_TRACE_LEVEL_DEBUG=
+CONFIG_APPL_TRACE_LEVEL_VERBOSE=
+CONFIG_APPL_INITIAL_TRACE_LEVEL=2
+CONFIG_GATT_TRACE_LEVEL_NONE=
+CONFIG_GATT_TRACE_LEVEL_ERROR=
+CONFIG_GATT_TRACE_LEVEL_WARNING=y
+CONFIG_GATT_TRACE_LEVEL_API=
+CONFIG_GATT_TRACE_LEVEL_EVENT=
+CONFIG_GATT_TRACE_LEVEL_DEBUG=
+CONFIG_GATT_TRACE_LEVEL_VERBOSE=
+CONFIG_GATT_INITIAL_TRACE_LEVEL=2
+CONFIG_SMP_TRACE_LEVEL_NONE=
+CONFIG_SMP_TRACE_LEVEL_ERROR=
+CONFIG_SMP_TRACE_LEVEL_WARNING=y
+CONFIG_SMP_TRACE_LEVEL_API=
+CONFIG_SMP_TRACE_LEVEL_EVENT=
+CONFIG_SMP_TRACE_LEVEL_DEBUG=
+CONFIG_SMP_TRACE_LEVEL_VERBOSE=
+CONFIG_SMP_INITIAL_TRACE_LEVEL=2
+CONFIG_BTIF_TRACE_LEVEL_NONE=
+CONFIG_BTIF_TRACE_LEVEL_ERROR=
+CONFIG_BTIF_TRACE_LEVEL_WARNING=y
+CONFIG_BTIF_TRACE_LEVEL_API=
+CONFIG_BTIF_TRACE_LEVEL_EVENT=
+CONFIG_BTIF_TRACE_LEVEL_DEBUG=
+CONFIG_BTIF_TRACE_LEVEL_VERBOSE=
+CONFIG_BTIF_INITIAL_TRACE_LEVEL=2
+CONFIG_BTC_TRACE_LEVEL_NONE=
+CONFIG_BTC_TRACE_LEVEL_ERROR=
+CONFIG_BTC_TRACE_LEVEL_WARNING=y
+CONFIG_BTC_TRACE_LEVEL_API=
+CONFIG_BTC_TRACE_LEVEL_EVENT=
+CONFIG_BTC_TRACE_LEVEL_DEBUG=
+CONFIG_BTC_TRACE_LEVEL_VERBOSE=
+CONFIG_BTC_INITIAL_TRACE_LEVEL=2
+CONFIG_OSI_TRACE_LEVEL_NONE=
+CONFIG_OSI_TRACE_LEVEL_ERROR=
+CONFIG_OSI_TRACE_LEVEL_WARNING=y
+CONFIG_OSI_TRACE_LEVEL_API=
+CONFIG_OSI_TRACE_LEVEL_EVENT=
+CONFIG_OSI_TRACE_LEVEL_DEBUG=
+CONFIG_OSI_TRACE_LEVEL_VERBOSE=
+CONFIG_OSI_INITIAL_TRACE_LEVEL=2
+CONFIG_BLUFI_TRACE_LEVEL_NONE=
+CONFIG_BLUFI_TRACE_LEVEL_ERROR=
+CONFIG_BLUFI_TRACE_LEVEL_WARNING=y
+CONFIG_BLUFI_TRACE_LEVEL_API=
+CONFIG_BLUFI_TRACE_LEVEL_EVENT=
+CONFIG_BLUFI_TRACE_LEVEL_DEBUG=
+CONFIG_BLUFI_TRACE_LEVEL_VERBOSE=
+CONFIG_BLUFI_INITIAL_TRACE_LEVEL=2
+CONFIG_BT_ACL_CONNECTIONS=4
+CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST=
+CONFIG_BT_BLE_DYNAMIC_ENV_MEMORY=
+CONFIG_BLE_HOST_QUEUE_CONGESTION_CHECK=
+CONFIG_SMP_ENABLE=y
+CONFIG_BLE_ESTABLISH_LINK_CONNECTION_TIMEOUT=60
+CONFIG_BT_RESERVE_DRAM=0xdb5c
+
+#
+# Driver configurations
+#
+
+#
+# ADC configuration
+#
+CONFIG_ADC_FORCE_XPD_FSM=
+CONFIG_ADC2_DISABLE_DAC=y
+
+#
+# SPI configuration
+#
+CONFIG_SPI_MASTER_IN_IRAM=y
+CONFIG_SPI_MASTER_ISR_IN_IRAM=y
+CONFIG_SPI_SLAVE_IN_IRAM=
+CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
+
+#
+# ESP32-specific
+#
+CONFIG_ESP32_DEFAULT_CPU_FREQ_80=
+CONFIG_ESP32_DEFAULT_CPU_FREQ_160=y
+CONFIG_ESP32_DEFAULT_CPU_FREQ_240=
+CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=160
+CONFIG_SPIRAM_SUPPORT=
+CONFIG_MEMMAP_TRACEMEM=
+CONFIG_MEMMAP_TRACEMEM_TWOBANKS=
+CONFIG_ESP32_TRAX=
+CONFIG_TRACEMEM_RESERVE_DRAM=0x0
+CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=
+CONFIG_ESP32_ENABLE_COREDUMP_TO_UART=
+CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
+CONFIG_ESP32_ENABLE_COREDUMP=
+CONFIG_TWO_UNIVERSAL_MAC_ADDRESS=
+CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y
+CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4
+CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
+CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
+CONFIG_MAIN_TASK_STACK_SIZE=3584
+CONFIG_IPC_TASK_STACK_SIZE=1024
+CONFIG_TIMER_TASK_STACK_SIZE=3584
+CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
+CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF=
+CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR=
+CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF=
+CONFIG_NEWLIB_STDIN_LINE_ENDING_LF=
+CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
+CONFIG_NEWLIB_NANO_FORMAT=
+CONFIG_CONSOLE_UART_DEFAULT=y
+CONFIG_CONSOLE_UART_CUSTOM=
+CONFIG_CONSOLE_UART_NONE=
+CONFIG_CONSOLE_UART_NUM=0
+CONFIG_CONSOLE_UART_BAUDRATE=115200
+CONFIG_ULP_COPROC_ENABLED=
+CONFIG_ULP_COPROC_RESERVE_MEM=0
+CONFIG_ESP32_PANIC_PRINT_HALT=
+CONFIG_ESP32_PANIC_PRINT_REBOOT=y
+CONFIG_ESP32_PANIC_SILENT_REBOOT=
+CONFIG_ESP32_PANIC_GDBSTUB=
+CONFIG_ESP32_DEBUG_OCDAWARE=y
+CONFIG_ESP32_DEBUG_STUBS_ENABLE=y
+CONFIG_INT_WDT=y
+CONFIG_INT_WDT_TIMEOUT_MS=300
+CONFIG_INT_WDT_CHECK_CPU1=y
+CONFIG_TASK_WDT=y
+CONFIG_TASK_WDT_PANIC=
+CONFIG_TASK_WDT_TIMEOUT_S=5
+CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
+CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
+CONFIG_BROWNOUT_DET=y
+CONFIG_BROWNOUT_DET_LVL_SEL_0=y
+CONFIG_BROWNOUT_DET_LVL_SEL_1=
+CONFIG_BROWNOUT_DET_LVL_SEL_2=
+CONFIG_BROWNOUT_DET_LVL_SEL_3=
+CONFIG_BROWNOUT_DET_LVL_SEL_4=
+CONFIG_BROWNOUT_DET_LVL_SEL_5=
+CONFIG_BROWNOUT_DET_LVL_SEL_6=
+CONFIG_BROWNOUT_DET_LVL_SEL_7=
+CONFIG_BROWNOUT_DET_LVL=0
+CONFIG_REDUCE_PHY_TX_POWER=y
+CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y
+CONFIG_ESP32_TIME_SYSCALL_USE_RTC=
+CONFIG_ESP32_TIME_SYSCALL_USE_FRC1=
+CONFIG_ESP32_TIME_SYSCALL_USE_NONE=
+CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
+CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL=
+CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC=
+CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256=
+CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024
+CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
+CONFIG_ESP32_XTAL_FREQ_40=y
+CONFIG_ESP32_XTAL_FREQ_26=
+CONFIG_ESP32_XTAL_FREQ_AUTO=
+CONFIG_ESP32_XTAL_FREQ=40
+CONFIG_DISABLE_BASIC_ROM_CONSOLE=
+CONFIG_ESP_TIMER_PROFILING=
+CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS=
+CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
+
+#
+# Wi-Fi
+#
+CONFIG_SW_COEXIST_ENABLE=y
+CONFIG_SW_COEXIST_PREFERENCE_WIFI=
+CONFIG_SW_COEXIST_PREFERENCE_BT=
+CONFIG_SW_COEXIST_PREFERENCE_BALANCE=y
+CONFIG_SW_COEXIST_PREFERENCE_VALUE=2
+CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=
+CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y
+CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1
+CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32
+CONFIG_ESP32_WIFI_CSI_ENABLED=
+CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP32_WIFI_TX_BA_WIN=6
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+CONFIG_ESP32_WIFI_NVS_ENABLED=y
+CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
+CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1=
+CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP32_WIFI_IRAM_OPT=y
+CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
+
+#
+# PHY
+#
+CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
+CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION=
+CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
+CONFIG_ESP32_PHY_MAX_TX_POWER=20
+
+#
+# Power Management
+#
+CONFIG_PM_ENABLE=
+
+#
+# ADC-Calibration
+#
+CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y
+CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y
+CONFIG_ADC_CAL_LUT_ENABLE=y
+
+#
+# Event Loop Library
+#
+CONFIG_EVENT_LOOP_PROFILING=
+
+#
+# ESP HTTP client
+#
+CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y
+
+#
+# HTTP Server
+#
+CONFIG_HTTPD_MAX_REQ_HDR_LEN=512
+CONFIG_HTTPD_MAX_URI_LEN=512
+
+#
+# Ethernet
+#
+CONFIG_DMA_RX_BUF_NUM=10
+CONFIG_DMA_TX_BUF_NUM=10
+CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y
+CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000
+CONFIG_EMAC_TASK_PRIORITY=20
+CONFIG_EMAC_TASK_STACK_SIZE=3072
+
+#
+# FAT Filesystem support
+#
+CONFIG_FATFS_CODEPAGE_DYNAMIC=
+CONFIG_FATFS_CODEPAGE_437=y
+CONFIG_FATFS_CODEPAGE_720=
+CONFIG_FATFS_CODEPAGE_737=
+CONFIG_FATFS_CODEPAGE_771=
+CONFIG_FATFS_CODEPAGE_775=
+CONFIG_FATFS_CODEPAGE_850=
+CONFIG_FATFS_CODEPAGE_852=
+CONFIG_FATFS_CODEPAGE_855=
+CONFIG_FATFS_CODEPAGE_857=
+CONFIG_FATFS_CODEPAGE_860=
+CONFIG_FATFS_CODEPAGE_861=
+CONFIG_FATFS_CODEPAGE_862=
+CONFIG_FATFS_CODEPAGE_863=
+CONFIG_FATFS_CODEPAGE_864=
+CONFIG_FATFS_CODEPAGE_865=
+CONFIG_FATFS_CODEPAGE_866=
+CONFIG_FATFS_CODEPAGE_869=
+CONFIG_FATFS_CODEPAGE_932=
+CONFIG_FATFS_CODEPAGE_936=
+CONFIG_FATFS_CODEPAGE_949=
+CONFIG_FATFS_CODEPAGE_950=
+CONFIG_FATFS_CODEPAGE=437
+CONFIG_FATFS_LFN_NONE=y
+CONFIG_FATFS_LFN_HEAP=
+CONFIG_FATFS_LFN_STACK=
+CONFIG_FATFS_FS_LOCK=0
+CONFIG_FATFS_TIMEOUT_MS=10000
+CONFIG_FATFS_PER_FILE_CACHE=y
+
+#
+# Modbus configuration
+#
+CONFIG_MB_QUEUE_LENGTH=20
+CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048
+CONFIG_MB_SERIAL_BUF_SIZE=256
+CONFIG_MB_SERIAL_TASK_PRIO=10
+CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=
+CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
+CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
+CONFIG_MB_CONTROLLER_STACK_SIZE=4096
+CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
+CONFIG_MB_TIMER_PORT_ENABLED=y
+CONFIG_MB_TIMER_GROUP=0
+CONFIG_MB_TIMER_INDEX=0
+
+#
+# FreeRTOS
+#
+CONFIG_FREERTOS_UNICORE=
+CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
+CONFIG_FREERTOS_CORETIMER_0=y
+CONFIG_FREERTOS_CORETIMER_1=
+CONFIG_FREERTOS_HZ=100
+CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
+CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE=
+CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL=
+CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
+CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=
+CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
+CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
+CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
+CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE=
+CONFIG_FREERTOS_ASSERT_DISABLE=
+CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536
+CONFIG_FREERTOS_ISR_STACKSIZE=1536
+CONFIG_FREERTOS_LEGACY_HOOKS=
+CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16
+CONFIG_SUPPORT_STATIC_ALLOCATION=
+CONFIG_TIMER_TASK_PRIORITY=1
+CONFIG_TIMER_TASK_STACK_DEPTH=2048
+CONFIG_TIMER_QUEUE_LENGTH=10
+CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
+CONFIG_FREERTOS_USE_TRACE_FACILITY=
+CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=
+CONFIG_FREERTOS_DEBUG_INTERNALS=
+CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y
+
+#
+# Heap memory debugging
+#
+CONFIG_HEAP_POISONING_DISABLED=y
+CONFIG_HEAP_POISONING_LIGHT=
+CONFIG_HEAP_POISONING_COMPREHENSIVE=
+CONFIG_HEAP_TRACING=
+
+#
+# libsodium
+#
+CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y
+
+#
+# Log output
+#
+CONFIG_LOG_DEFAULT_LEVEL_NONE=
+CONFIG_LOG_DEFAULT_LEVEL_ERROR=
+CONFIG_LOG_DEFAULT_LEVEL_WARN=
+CONFIG_LOG_DEFAULT_LEVEL_INFO=y
+CONFIG_LOG_DEFAULT_LEVEL_DEBUG=
+CONFIG_LOG_DEFAULT_LEVEL_VERBOSE=
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_LOG_COLORS=y
+
+#
+# LWIP
+#
+CONFIG_L2_TO_L3_COPY=
+CONFIG_LWIP_IRAM_OPTIMIZATION=
+CONFIG_LWIP_MAX_SOCKETS=10
+CONFIG_USE_ONLY_LWIP_SELECT=
+CONFIG_LWIP_SO_REUSE=y
+CONFIG_LWIP_SO_REUSE_RXTOALL=y
+CONFIG_LWIP_SO_RCVBUF=
+CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1
+CONFIG_LWIP_IP_FRAG=
+CONFIG_LWIP_IP_REASSEMBLY=
+CONFIG_LWIP_STATS=
+CONFIG_LWIP_ETHARP_TRUST_IP_MAC=
+CONFIG_ESP_GRATUITOUS_ARP=y
+CONFIG_GARP_TMR_INTERVAL=60
+CONFIG_TCPIP_RECVMBOX_SIZE=32
+CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
+CONFIG_LWIP_DHCP_RESTORE_LAST_IP=
+
+#
+# DHCP server
+#
+CONFIG_LWIP_DHCPS_LEASE_UNIT=60
+CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
+CONFIG_LWIP_AUTOIP=
+CONFIG_LWIP_NETIF_LOOPBACK=y
+CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8
+
+#
+# TCP
+#
+CONFIG_LWIP_MAX_ACTIVE_TCP=16
+CONFIG_LWIP_MAX_LISTENING_TCP=16
+CONFIG_TCP_MAXRTX=12
+CONFIG_TCP_SYNMAXRTX=6
+CONFIG_TCP_MSS=1436
+CONFIG_TCP_MSL=60000
+CONFIG_TCP_SND_BUF_DEFAULT=5744
+CONFIG_TCP_WND_DEFAULT=5744
+CONFIG_TCP_RECVMBOX_SIZE=6
+CONFIG_TCP_QUEUE_OOSEQ=y
+CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES=
+CONFIG_TCP_OVERSIZE_MSS=y
+CONFIG_TCP_OVERSIZE_QUARTER_MSS=
+CONFIG_TCP_OVERSIZE_DISABLE=
+
+#
+# UDP
+#
+CONFIG_LWIP_MAX_UDP_PCBS=16
+CONFIG_UDP_RECVMBOX_SIZE=6
+CONFIG_TCPIP_TASK_STACK_SIZE=3072
+CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
+CONFIG_TCPIP_TASK_AFFINITY_CPU0=
+CONFIG_TCPIP_TASK_AFFINITY_CPU1=
+CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
+CONFIG_PPP_SUPPORT=
+
+#
+# ICMP
+#
+CONFIG_LWIP_MULTICAST_PING=
+CONFIG_LWIP_BROADCAST_PING=
+
+#
+# LWIP RAW API
+#
+CONFIG_LWIP_MAX_RAW_PCBS=16
+
+#
+# mbedTLS
+#
+CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y
+CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC=
+CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC=
+CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384
+CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=
+CONFIG_MBEDTLS_DEBUG=
+CONFIG_MBEDTLS_HARDWARE_AES=y
+CONFIG_MBEDTLS_HARDWARE_MPI=
+CONFIG_MBEDTLS_HARDWARE_SHA=
+CONFIG_MBEDTLS_HAVE_TIME=y
+CONFIG_MBEDTLS_HAVE_TIME_DATE=
+CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y
+CONFIG_MBEDTLS_TLS_SERVER_ONLY=
+CONFIG_MBEDTLS_TLS_CLIENT_ONLY=
+CONFIG_MBEDTLS_TLS_DISABLED=
+CONFIG_MBEDTLS_TLS_SERVER=y
+CONFIG_MBEDTLS_TLS_CLIENT=y
+CONFIG_MBEDTLS_TLS_ENABLED=y
+
+#
+# TLS Key Exchange Methods
+#
+CONFIG_MBEDTLS_PSK_MODES=
+CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
+CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
+CONFIG_MBEDTLS_SSL_PROTO_SSL3=
+CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
+CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
+CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
+CONFIG_MBEDTLS_SSL_PROTO_DTLS=
+CONFIG_MBEDTLS_SSL_ALPN=y
+CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y
+
+#
+# Symmetric Ciphers
+#
+CONFIG_MBEDTLS_AES_C=y
+CONFIG_MBEDTLS_CAMELLIA_C=
+CONFIG_MBEDTLS_DES_C=
+CONFIG_MBEDTLS_RC4_DISABLED=y
+CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT=
+CONFIG_MBEDTLS_RC4_ENABLED=
+CONFIG_MBEDTLS_BLOWFISH_C=
+CONFIG_MBEDTLS_XTEA_C=
+CONFIG_MBEDTLS_CCM_C=y
+CONFIG_MBEDTLS_GCM_C=y
+CONFIG_MBEDTLS_RIPEMD160_C=
+
+#
+# Certificates
+#
+CONFIG_MBEDTLS_PEM_PARSE_C=y
+CONFIG_MBEDTLS_PEM_WRITE_C=y
+CONFIG_MBEDTLS_X509_CRL_PARSE_C=y
+CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
+CONFIG_MBEDTLS_ECP_C=y
+CONFIG_MBEDTLS_ECDH_C=y
+CONFIG_MBEDTLS_ECDSA_C=y
+CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y
+CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
+
+#
+# mDNS
+#
+CONFIG_MDNS_MAX_SERVICES=10
+
+#
+# ESP-MQTT Configurations
+#
+CONFIG_MQTT_PROTOCOL_311=y
+CONFIG_MQTT_TRANSPORT_SSL=y
+CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
+CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
+CONFIG_MQTT_USE_CUSTOM_CONFIG=
+CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED=
+CONFIG_MQTT_CUSTOM_OUTBOX=
+
+#
+# NVS
+#
+
+#
+# OpenSSL
+#
+CONFIG_OPENSSL_DEBUG=
+CONFIG_OPENSSL_ASSERT_DO_NOTHING=y
+CONFIG_OPENSSL_ASSERT_EXIT=
+
+#
+# PThreads
+#
+CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
+CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
+CONFIG_PTHREAD_STACK_MIN=768
+
+#
+# SPI Flash driver
+#
+CONFIG_SPI_FLASH_VERIFY_WRITE=
+CONFIG_SPI_FLASH_ENABLE_COUNTERS=
+CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
+CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
+CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS=
+CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED=
+CONFIG_SPI_FLASH_YIELD_DURING_ERASE=
+
+#
+# SPIFFS Configuration
+#
+CONFIG_SPIFFS_MAX_PARTITIONS=3
+
+#
+# SPIFFS Cache Configuration
+#
+CONFIG_SPIFFS_CACHE=y
+CONFIG_SPIFFS_CACHE_WR=y
+CONFIG_SPIFFS_CACHE_STATS=
+CONFIG_SPIFFS_PAGE_CHECK=y
+CONFIG_SPIFFS_GC_MAX_RUNS=10
+CONFIG_SPIFFS_GC_STATS=
+CONFIG_SPIFFS_PAGE_SIZE=256
+CONFIG_SPIFFS_OBJ_NAME_LEN=32
+CONFIG_SPIFFS_USE_MAGIC=y
+CONFIG_SPIFFS_USE_MAGIC_LENGTH=y
+CONFIG_SPIFFS_META_LENGTH=4
+CONFIG_SPIFFS_USE_MTIME=y
+
+#
+# Debug Configuration
+#
+CONFIG_SPIFFS_DBG=
+CONFIG_SPIFFS_API_DBG=
+CONFIG_SPIFFS_GC_DBG=
+CONFIG_SPIFFS_CACHE_DBG=
+CONFIG_SPIFFS_CHECK_DBG=
+CONFIG_SPIFFS_TEST_VISUALISATION=
+
+#
+# TCP/IP Adapter
+#
+CONFIG_IP_LOST_TIMER_INTERVAL=120
+CONFIG_TCPIP_LWIP=y
+
+#
+# Virtual file system
+#
+CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
+CONFIG_SUPPORT_TERMIOS=y
+
+#
+# Wear Levelling
+#
+CONFIG_WL_SECTOR_SIZE_512=
+CONFIG_WL_SECTOR_SIZE_4096=y
+CONFIG_WL_SECTOR_SIZE=4096