Inital Commit

CMakeLists.txt

@@ -0,0 +1,6 @@
+# The following five lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.5)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(blink)

Makefile

@@ -0,0 +1,9 @@
+#
+# This is a project Makefile. It is assumed the directory this Makefile resides in is a
+# project subdirectory.
+#
+
+PROJECT_NAME := Arrow
+
+include $(IDF_PATH)/make/project.mk
+

main/CMakeLists.txt

@@ -0,0 +1,4 @@
+set(COMPONENT_SRCS "blink.c")
+set(COMPONENT_ADD_INCLUDEDIRS ".")
+
+register_component()

main/Kconfig.projbuild

@@ -0,0 +1,14 @@
+menu "Example Configuration"
+
+config BLINK_GPIO
+    int "Blink GPIO number"
+	range 0 34
+	default 5
+	help
+		GPIO number (IOxx) to blink on and off.
+
+		Some GPIOs are used for other purposes (flash connections, etc.) and cannot be used to blink.
+
+		GPIOs 35-39 are input-only so cannot be used as outputs.
+
+endmenu

main/board.h

@@ -0,0 +1,14 @@
+/*
+ * board.h
+ *
+ *  Created on: Jan 11, 2019
+ *      Author: curiousmuch
+ */
+
+#ifndef MAIN_BOARD_H_
+#define MAIN_BOARD_H_
+
+
+
+
+#endif /* MAIN_BOARD_H_ */

main/cc1120.h

@@ -0,0 +1,225 @@
+/*
+ * cc1120.h
+ *
+ *  Created on: Jan 11, 2019
+ *      Author: curiousmuch
+ */
+
+#ifndef MAIN_CC1120_H_
+#define MAIN_CC1120_H_
+
+#include <stdio.h>
+#include <stdint.h>
+
+/* CC1120 Configuration Registers */
+#define CC112X_IOCFG3                   0x0000
+#define CC112X_IOCFG2                   0x0001
+#define CC112X_IOCFG1                   0x0002
+#define CC112X_IOCFG0                   0x0003
+#define CC112X_SYNC3                    0x0004
+#define CC112X_SYNC2                    0x0005
+#define CC112X_SYNC1                    0x0006
+#define CC112X_SYNC0                    0x0007
+#define CC112X_SYNC_CFG1                0x0008
+#define CC112X_SYNC_CFG0                0x0009
+#define CC112X_DEVIATION_M              0x000A
+#define CC112X_MODCFG_DEV_E             0x000B
+#define CC112X_DCFILT_CFG               0x000C
+#define CC112X_PREAMBLE_CFG1            0x000D
+#define CC112X_PREAMBLE_CFG0            0x000E
+#define CC112X_FREQ_IF_CFG              0x000F
+#define CC112X_IQIC                     0x0010
+#define CC112X_CHAN_BW                  0x0011
+#define CC112X_MDMCFG1                  0x0012
+#define CC112X_MDMCFG0                  0x0013
+#define CC112X_SYMBOL_RATE2             0x0014
+#define CC112X_SYMBOL_RATE1             0x0015
+#define CC112X_SYMBOL_RATE0             0x0016
+#define CC112X_AGC_REF                  0x0017
+#define CC112X_AGC_CS_THR               0x0018
+#define CC112X_AGC_GAIN_ADJUST          0x0019
+#define CC112X_AGC_CFG3                 0x001A
+#define CC112X_AGC_CFG2                 0x001B
+#define CC112X_AGC_CFG1                 0x001C
+#define CC112X_AGC_CFG0                 0x001D
+#define CC112X_FIFO_CFG                 0x001E
+#define CC112X_DEV_ADDR                 0x001F
+#define CC112X_SETTLING_CFG             0x0020
+#define CC112X_FS_CFG                   0x0021
+#define CC112X_WOR_CFG1                 0x0022
+#define CC112X_WOR_CFG0                 0x0023
+#define CC112X_WOR_EVENT0_MSB           0x0024
+#define CC112X_WOR_EVENT0_LSB           0x0025
+#define CC112X_PKT_CFG2                 0x0026
+#define CC112X_PKT_CFG1                 0x0027
+#define CC112X_PKT_CFG0                 0x0028
+#define CC112X_RFEND_CFG1               0x0029
+#define CC112X_RFEND_CFG0               0x002A
+#define CC112X_PA_CFG2                  0x002B
+#define CC112X_PA_CFG1                  0x002C
+#define CC112X_PA_CFG0                  0x002D
+#define CC112X_PKT_LEN                  0x002E
+
+/* Extended Configuration Registers */
+#define CC112X_IF_MIX_CFG               0x2F00
+#define CC112X_FREQOFF_CFG              0x2F01
+#define CC112X_TOC_CFG                  0x2F02
+#define CC112X_MARC_SPARE               0x2F03
+#define CC112X_ECG_CFG                  0x2F04
+#define CC112X_CFM_DATA_CFG             0x2F05
+#define CC112X_EXT_CTRL                 0x2F06
+#define CC112X_RCCAL_FINE               0x2F07
+#define CC112X_RCCAL_COARSE             0x2F08
+#define CC112X_RCCAL_OFFSET             0x2F09
+#define CC112X_FREQOFF1                 0x2F0A
+#define CC112X_FREQOFF0                 0x2F0B
+#define CC112X_FREQ2                    0x2F0C
+#define CC112X_FREQ1                    0x2F0D
+#define CC112X_FREQ0                    0x2F0E
+#define CC112X_IF_ADC2                  0x2F0F
+#define CC112X_IF_ADC1                  0x2F10
+#define CC112X_IF_ADC0                  0x2F11
+#define CC112X_FS_DIG1                  0x2F12
+#define CC112X_FS_DIG0                  0x2F13
+#define CC112X_FS_CAL3                  0x2F14
+#define CC112X_FS_CAL2                  0x2F15
+#define CC112X_FS_CAL1                  0x2F16
+#define CC112X_FS_CAL0                  0x2F17
+#define CC112X_FS_CHP                   0x2F18
+#define CC112X_FS_DIVTWO                0x2F19
+#define CC112X_FS_DSM1                  0x2F1A
+#define CC112X_FS_DSM0                  0x2F1B
+#define CC112X_FS_DVC1                  0x2F1C
+#define CC112X_FS_DVC0                  0x2F1D
+#define CC112X_FS_LBI                   0x2F1E
+#define CC112X_FS_PFD                   0x2F1F
+#define CC112X_FS_PRE                   0x2F20
+#define CC112X_FS_REG_DIV_CML           0x2F21
+#define CC112X_FS_SPARE                 0x2F22
+#define CC112X_FS_VCO4                  0x2F23
+#define CC112X_FS_VCO3                  0x2F24
+#define CC112X_FS_VCO2                  0x2F25
+#define CC112X_FS_VCO1                  0x2F26
+#define CC112X_FS_VCO0                  0x2F27
+#define CC112X_GBIAS6                   0x2F28
+#define CC112X_GBIAS5                   0x2F29
+#define CC112X_GBIAS4                   0x2F2A
+#define CC112X_GBIAS3                   0x2F2B
+#define CC112X_GBIAS2                   0x2F2C
+#define CC112X_GBIAS1                   0x2F2D
+#define CC112X_GBIAS0                   0x2F2E
+#define CC112X_IFAMP                    0x2F2F
+#define CC112X_LNA                      0x2F30
+#define CC112X_RXMIX                    0x2F31
+#define CC112X_XOSC5                    0x2F32
+#define CC112X_XOSC4                    0x2F33
+#define CC112X_XOSC3                    0x2F34
+#define CC112X_XOSC2                    0x2F35
+#define CC112X_XOSC1                    0x2F36
+#define CC112X_XOSC0                    0x2F37
+#define CC112X_ANALOG_SPARE             0x2F38
+#define CC112X_PA_CFG3                  0x2F39
+#define CC112X_IRQ0M                    0x2F3F
+#define CC112X_IRQ0F                    0x2F40
+
+/* Status Registers */
+#define CC112X_WOR_TIME1                0x2F64
+#define CC112X_WOR_TIME0                0x2F65
+#define CC112X_WOR_CAPTURE1             0x2F66
+#define CC112X_WOR_CAPTURE0             0x2F67
+#define CC112X_BIST                     0x2F68
+#define CC112X_DCFILTOFFSET_I1          0x2F69
+#define CC112X_DCFILTOFFSET_I0          0x2F6A
+#define CC112X_DCFILTOFFSET_Q1          0x2F6B
+#define CC112X_DCFILTOFFSET_Q0          0x2F6C
+#define CC112X_IQIE_I1                  0x2F6D
+#define CC112X_IQIE_I0                  0x2F6E
+#define CC112X_IQIE_Q1                  0x2F6F
+#define CC112X_IQIE_Q0                  0x2F70
+#define CC112X_RSSI1                    0x2F71
+#define CC112X_RSSI0                    0x2F72
+#define CC112X_MARCSTATE                0x2F73
+#define CC112X_LQI_VAL                  0x2F74
+#define CC112X_PQT_SYNC_ERR             0x2F75
+#define CC112X_DEM_STATUS               0x2F76
+#define CC112X_FREQOFF_EST1             0x2F77
+#define CC112X_FREQOFF_EST0             0x2F78
+#define CC112X_AGC_GAIN3                0x2F79
+#define CC112X_AGC_GAIN2                0x2F7A
+#define CC112X_AGC_GAIN1                0x2F7B
+#define CC112X_AGC_GAIN0                0x2F7C
+#define CC112X_CFM_RX_DATA_OUT          0x2F7D
+#define CC112X_CFM_TX_DATA_IN           0x2F7E
+#define CC112X_ASK_SOFT_RX_DATA         0x2F7F
+#define CC112X_RNDGEN                   0x2F80
+#define CC112X_MAGN2                    0x2F81
+#define CC112X_MAGN1                    0x2F82
+#define CC112X_MAGN0                    0x2F83
+#define CC112X_ANG1                     0x2F84
+#define CC112X_ANG0                     0x2F85
+#define CC112X_CHFILT_I2                0x2F86
+#define CC112X_CHFILT_I1                0x2F87
+#define CC112X_CHFILT_I0                0x2F88
+#define CC112X_CHFILT_Q2                0x2F89
+#define CC112X_CHFILT_Q1                0x2F8A
+#define CC112X_CHFILT_Q0                0x2F8B
+#define CC112X_GPIO_STATUS              0x2F8C
+#define CC112X_FSCAL_CTRL               0x2F8D
+#define CC112X_PHASE_ADJUST             0x2F8E
+#define CC112X_PARTNUMBER               0x2F8F
+#define CC112X_PARTVERSION              0x2F90
+#define CC112X_SERIAL_STATUS            0x2F91
+#define CC112X_MODEM_STATUS1            0x2F92
+#define CC112X_MODEM_STATUS0            0x2F93
+#define CC112X_MARC_STATUS1             0x2F94
+#define CC112X_MARC_STATUS0             0x2F95
+#define CC112X_PA_IFAMP_TEST            0x2F96
+#define CC112X_FSRF_TEST                0x2F97
+#define CC112X_PRE_TEST                 0x2F98
+#define CC112X_PRE_OVR                  0x2F99
+#define CC112X_ADC_TEST                 0x2F9A
+#define CC112X_DVC_TEST                 0x2F9B
+#define CC112X_ATEST                    0x2F9C
+#define CC112X_ATEST_LVDS               0x2F9D
+#define CC112X_ATEST_MODE               0x2F9E
+#define CC112X_XOSC_TEST1               0x2F9F
+#define CC112X_XOSC_TEST0               0x2FA0
+
+#define CC112X_RXFIRST                  0x2FD2
+#define CC112X_TXFIRST                  0x2FD3
+#define CC112X_RXLAST                   0x2FD4
+#define CC112X_TXLAST                   0x2FD5
+#define CC112X_NUM_TXBYTES              0x2FD6
+
+/* Command strobe registers */
+#define CC112X_SRES                     0x30      /*  SRES    - Reset chip. */
+#define CC112X_SFSTXON                  0x31      /*  SFSTXON - Enable and calibrate frequency synthesizer. */
+#define CC112X_SXOFF                    0x32      /*  SXOFF   - Turn off crystal oscillator. */
+#define CC112X_SCAL                     0x33      /*  SCAL    - Calibrate frequency synthesizer and turn it off. */
+#define CC112X_SRX                      0x34      /*  SRX     - Enable RX. Perform calibration if enabled. */
+#define CC112X_STX                      0x35      /*  STX     - Enable TX. If in RX state, only enable TX if CCA passes. */
+#define CC112X_SIDLE                    0x36      /*  SIDLE   - Exit RX / TX, turn off frequency synthesizer. */
+#define CC112X_SWOR                     0x38      /*  SWOR    - Start automatic RX polling sequence (Wake-on-Radio) */
+#define CC112X_SPWD                     0x39      /*  SPWD    - Enter power down mode when CSn goes high. */
+#define CC112X_SFRX                     0x3A      /*  SFRX    - Flush the RX FIFO buffer. */
+#define CC112X_SFTX                     0x3B      /*  SFTX    - Flush the TX FIFO buffer. */
+#define CC112X_SWORRST                  0x3C      /*  SWORRST - Reset real time clock. */
+#define CC112X_SNOP                     0x3D      /*  SNOP    - No operation. Returns status byte. */
+#define CC112X_AFC                      0x37      /*  AFC     - Automatic Frequency Correction */
+
+/* Chip states returned in status byte */
+#define CC112X_STATE_IDLE               0x00
+#define CC112X_STATE_RX                 0x10
+#define CC112X_STATE_TX                 0x20
+#define CC112X_STATE_FSTXON             0x30
+#define CC112X_STATE_CALIBRATE          0x40
+#define CC112X_STATE_SETTLING           0x50
+#define CC112X_STATE_RXFIFO_ERROR       0x60
+#define CC112X_STATE_TXFIFO_ERROR       0x70
+
+/* FIFO Address */
+#define CC112X_FIFO						0x3F
+
+typedef uint8_t rf_status_t;
+
+#endif /* MAIN_CC1120_H_ */

main/cc1120_protocol.h

@@ -0,0 +1,83 @@
+/*
+ * cc1120_aprs.h
+ *
+ *  Created on: Jan 12, 2019
+ *      Author: curiousmuch
+ */
+
+#ifndef MAIN_CC1120_PROTOCOL_H_
+#define MAIN_CC1120_PROTOCOL_H_
+
+#include <stdio.h>
+#include <stdint.h>
+#include "cc1120.h"
+
+typedef struct {
+	uint16_t addr;
+	uint8_t data;
+} cc1120_reg_settings_t;
+
+/* APRS Radio Configuration */
+// Address Config = No address check
+// Bit Rate = 6
+// Carrier Frequency = 144.389999
+// Deviation = 5.004883
+// Device Address = 0
+// Manchester Enable = false
+// Modulation Format = 2-FSK
+// PA Ramping = true
+// Packet Bit Length = 0
+// Packet Length = 255
+// Packet Length Mode = Variable
+// Performance Mode = High Performance
+// RX Filter BW = 20.000000
+// Symbol rate = 6
+// TX Power = 15
+// Whitening = false
+static const cc1120_reg_settings_t ARPS_SETTINGS[]=
+{
+  {CC112X_IOCFG3,            0xB0},
+  {CC112X_IOCFG2,            0x06},
+  {CC112X_IOCFG1,            0xB0},
+  {CC112X_IOCFG0,            0x40},
+  {CC112X_SYNC_CFG1,         0x0B},
+  {CC112X_DEVIATION_M,       0x48},
+  {CC112X_DCFILT_CFG,        0x1C},
+  {CC112X_PREAMBLE_CFG1,     0x18},
+  {CC112X_IQIC,              0xC6},
+  {CC112X_CHAN_BW,           0x0A},
+  {CC112X_MDMCFG0,           0x05},
+  {CC112X_SYMBOL_RATE2,      0x68},
+  {CC112X_SYMBOL_RATE1,      0x93},
+  {CC112X_SYMBOL_RATE0,      0x75},
+  {CC112X_AGC_REF,           0x20},
+  {CC112X_AGC_CS_THR,        0x19},
+  {CC112X_AGC_CFG1,          0xA9},
+  {CC112X_AGC_CFG0,          0xCF},
+  {CC112X_FIFO_CFG,          0x00},
+  {CC112X_FS_CFG,            0x1B},
+  {CC112X_PKT_CFG0,          0x20},
+  {CC112X_PA_CFG0,           0x7E},
+  {CC112X_PKT_LEN,           0xFF},
+  {CC112X_IF_MIX_CFG,        0x00},
+  {CC112X_FREQOFF_CFG,       0x22},
+  {CC112X_FREQ2,             0x6C},
+  {CC112X_FREQ1,             0x4A},
+  {CC112X_FREQ0,             0xE1},
+  {CC112X_FS_DIG1,           0x00},
+  {CC112X_FS_DIG0,           0x5F},
+  {CC112X_FS_CAL1,           0x40},
+  {CC112X_FS_CAL0,           0x0E},
+  {CC112X_FS_DIVTWO,         0x03},
+  {CC112X_FS_DSM0,           0x33},
+  {CC112X_FS_DVC0,           0x17},
+  {CC112X_FS_PFD,            0x50},
+  {CC112X_FS_PRE,            0x6E},
+  {CC112X_FS_REG_DIV_CML,    0x14},
+  {CC112X_FS_SPARE,          0xAC},
+  {CC112X_FS_VCO0,           0xB4},
+  {CC112X_XOSC5,             0x0E},
+  {CC112X_XOSC1,             0x03},
+};
+
+#endif /* MAIN_CC1120_PROTOCOL_H_ */

main/component.mk

@@ -0,0 +1,4 @@
+#
+# "main" pseudo-component makefile.
+#
+# (Uses default behaviour of compiling all source files in directory, adding 'include' to include path.)

main/main.c

@@ -0,0 +1,286 @@
+/*
+ * Project: Arrow
+ * Author: 	curiousmuch
+ */
+#include <stdio.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "driver/gpio.h"
+#include "sdkconfig.h"
+
+// Includes for CC1120 Driver
+#include "driver/spi_master.h"
+#include "esp_err.h"
+#include "cc1120.h"
+#include "cc1120_protocol.h"
+
+// CC1120 - ESP32 I/O
+// NOTE: Logic Probe is connecting to RESET - Pin1
+#define CC1120_RESET		22
+#define CC1120_CS 			5
+#define CC1120_SCLK			18
+#define CC1120_MOSI			23
+#define CC1120_MISO			19
+#define CC1120_GPIO0		36
+#define CC1120_GPIO0_RTC	0
+#define CC1120_GPIO2		39
+#define CC1120_GPIO2_RTC	3
+#define CC1120_GPIO3 		34
+#define CC1120_GPIO3_RTC	4
+
+#define CC1120_WRITE_BIT 	0
+#define CC1120_READ_BIT 	BIT(1)
+#define CC1120_BURST_BIT 	BIT(0)
+
+// Public Configurations for CC1120 SPI Driver
+spi_bus_config_t bus_config =
+{
+	.miso_io_num = CC1120_MISO,
+	.mosi_io_num = CC1120_MOSI,
+	.sclk_io_num = CC1120_SCLK,
+	.quadwp_io_num = -1,
+	.quadhd_io_num = -1,
+	.max_transfer_sz = 150
+};
+
+spi_device_interface_config_t interface_config =
+{
+	.command_bits = 2,
+	.address_bits = 6,
+	.dummy_bits = 0,
+	.mode = 0,
+	.spics_io_num = CC1120_CS,
+	.clock_speed_hz = SPI_MASTER_FREQ_8M,
+	.flags = SPI_DEVICE_HALFDUPLEX,
+	.queue_size = 1
+
+};
+
+spi_device_handle_t spi;
+
+// Private CC1120 Driver Functions
+esp_err_t cc1120_gpio_init(void)
+{
+	gpio_config_t reset_pin_config =
+	{
+			.pin_bit_mask = (uint64_t)BIT64(CC1120_RESET),
+			.mode = GPIO_MODE_OUTPUT,
+			.pull_up_en = GPIO_PULLUP_DISABLE,
+			.pull_down_en = GPIO_PULLDOWN_DISABLE,
+			.intr_type = GPIO_INTR_DISABLE
+
+	};
+	gpio_config_t gpio_pin_config =
+	{
+			.pin_bit_mask = (uint64_t) (BIT64(CC1120_GPIO0)|BIT64(CC1120_GPIO2)|BIT64(CC1120_GPIO3)),
+			.mode = GPIO_MODE_INPUT,
+			.pull_up_en = GPIO_PULLUP_DISABLE,
+			.pull_down_en = GPIO_PULLDOWN_DISABLE,
+			.intr_type = GPIO_INTR_DISABLE
+	};
+	gpio_config(&reset_pin_config);
+	gpio_config(&gpio_pin_config);
+
+	gpio_set_level(CC1120_RESET, 1);
+
+	return ESP_OK;
+}
+
+esp_err_t cc1120_spi_init(void)
+{
+	esp_err_t ret;
+	ret = spi_bus_initialize(VSPI_HOST, &bus_config, 1);	// this uses DMA channel 1
+	ESP_ERROR_CHECK(ret);
+	ret = spi_bus_add_device(VSPI_HOST, &interface_config, &spi);
+	ESP_ERROR_CHECK(ret);
+	return ESP_OK;
+}
+
+esp_err_t cc1120_spi_write_byte(uint16_t addr, uint8_t data)
+{
+	esp_err_t ret;
+	spi_transaction_t tx_trans =
+	{
+		.flags = SPI_TRANS_USE_TXDATA,
+		.cmd = CC1120_WRITE_BIT,
+		.addr = addr,
+		.length = 8,
+		.rxlength = 0,
+		.tx_data[0] = data
+
+	};
+
+	if ((addr & 0xFF00) != 0) // send data with extended address in command field
+	{
+		tx_trans.flags |= (SPI_TRANS_VARIABLE_CMD | SPI_TRANS_VARIABLE_ADDR);
+		spi_transaction_ext_t tx_trans_ext =
+		{
+				.base = tx_trans,
+				.command_bits = 2,
+				.address_bits = 14
+		};
+		ret = spi_device_transmit(spi, (spi_transaction_t*)&tx_trans_ext);
+	}
+	else
+	{
+		ret = spi_device_transmit(spi, &tx_trans);
+	}
+	ESP_ERROR_CHECK(ret);
+	return ESP_OK;
+}
+
+esp_err_t cc1120_spi_write_bytes(uint16_t addr, uint8_t* data, uint8_t len)
+{
+	esp_err_t ret;
+	spi_transaction_t tx_trans =
+	{
+		.cmd = (CC1120_WRITE_BIT | CC1120_BURST_BIT),
+		.addr = addr,
+		.length = 8*len,
+		.tx_buffer = data
+	};
+	if ((addr & 0xFF00) != 0) // send data with extended address in command field
+	{
+		tx_trans.flags |= (SPI_TRANS_VARIABLE_CMD | SPI_TRANS_VARIABLE_ADDR);
+		spi_transaction_ext_t tx_trans_ext =
+		{
+				.base = tx_trans,
+				.command_bits = 2,
+				.address_bits = 14
+		};
+		ret = spi_device_transmit(spi, (spi_transaction_t*)&tx_trans_ext);
+	}
+	else
+	{
+		ret = spi_device_transmit(spi, &tx_trans);
+	}
+	ESP_ERROR_CHECK(ret);
+	return ESP_OK;
+}
+
+esp_err_t cc1120_spi_read_byte(uint16_t addr, uint8_t* data)
+{
+	esp_err_t ret;
+	spi_transaction_t rx_trans =
+	{
+		.flags = SPI_TRANS_USE_RXDATA,
+		.cmd = CC1120_READ_BIT,
+		.addr = addr,
+		.length = 8,
+		.rxlength = 8,
+	};
+	if ((addr & 0xFF00) != 0) // read data with extended address in command field
+	{
+		rx_trans.flags |= (SPI_TRANS_VARIABLE_CMD | SPI_TRANS_VARIABLE_ADDR);
+		spi_transaction_ext_t rx_trans_ext =
+		{
+				.base = rx_trans,
+				.command_bits = 2,
+				.address_bits = 14
+		};
+		ret = spi_device_transmit(spi, (spi_transaction_t*)&rx_trans_ext);
+	}
+	else
+	{
+		ret = spi_device_transmit(spi, &rx_trans);
+	}
+	ESP_ERROR_CHECK(ret);
+	*data = rx_trans.rx_data[0];
+	return ESP_OK;
+}
+
+esp_err_t cc1120_spi_read_bytes(uint16_t addr, uint8_t* data, uint8_t len)
+{
+	esp_err_t ret;
+	spi_transaction_t rx_trans =
+	{
+		.cmd = (CC1120_READ_BIT | CC1120_BURST_BIT),
+		.addr = addr,
+		.length = 8*len,
+		.rxlength = 8*len,
+		.rx_buffer = data
+	};
+	if ((addr & 0xFF00) != 0) // read data with extended address in command field
+	{
+		rx_trans.flags |= (SPI_TRANS_VARIABLE_CMD | SPI_TRANS_VARIABLE_ADDR);
+		spi_transaction_ext_t rx_trans_ext =
+		{
+				.base = rx_trans,
+				.command_bits = 2,
+				.address_bits = 14
+		};
+		ret = spi_device_transmit(spi, (spi_transaction_t*)&rx_trans_ext);
+	}
+	else
+	{
+		ret = spi_device_transmit(spi, &rx_trans);
+	}
+	ESP_ERROR_CHECK(ret);
+	return ESP_OK;
+}
+
+esp_err_t cc1120_spi_strobe(uint8_t cmd)
+{
+	esp_err_t ret;
+	spi_transaction_t strobe_trans =
+	{
+		.cmd = CC1120_WRITE_BIT,
+		.addr = cmd,
+		.length = 0,
+	};
+	ret = spi_device_transmit(spi, &strobe_trans);
+	ESP_ERROR_CHECK(ret);
+	return ESP_OK;
+
+}
+
+// Public CC1120 Driver Functions
+// These function should have there own error codes as they're dependent upon the radio and
+// not the ESP32 :)
+
+esp_err_t cc1120_radio_reset(void)
+{
+	return ESP_OK;
+}
+
+esp_err_t cc1120_radio_frequency(uint32_t freq)
+{
+	return ESP_OK;
+}
+
+esp_err_t cc1120_radio_sleep(void)
+{
+	return ESP_OK;
+}
+
+esp_err_t cc1120_radio_power(uint8_t txPower)
+{
+	return ESP_OK;
+}
+
+esp_err_t cc1120_radio_init(void)
+{
+	cc1120_gpio_init();
+	cc1120_spi_init();
+	return ESP_OK;
+}
+
+void app_main()
+{
+	cc1120_radio_init();
+	printf("Hello\n");
+	uint8_t data;
+	// function test loop
+	while(1)
+	{
+		//cc1120_spi_write_byte(CC112X_PKT_CFG2, 0x0F);
+		//cc1120_spi_write_byte(CC112X_FS_CAL0, 0x0F);
+		cc1120_spi_read_byte(CC112X_PARTNUMBER, &data);
+		cc1120_spi_strobe(CC112X_STX);
+		vTaskDelay(30/portTICK_RATE_MS);
+		cc1120_spi_strobe(CC112X_SRX);
+		printf("data: %x\n", data);
+		//esp_task_wdt_reset();
+		vTaskDelay(1000/portTICK_RATE_MS);
+	}
+}

sdkconfig.defaults

@@ -0,0 +1,2 @@
+#
+