arrow-firmware/main/cc1200_protocol.h

/*
 * CC120X_protocol.h
 *
 *  Created on: Apr 13, 2019
 *      Author: curiousmuch
 */

//*********************************//
// IMPORTANT GPIO SIGNALS
// REG		DESCRIPTION
// 0x1e		TX CLK
// 0x1d		RX_CLK
// 0x10		Carrier Sense Valid
// 0x11		Carrier Sense
//********************************//

// Address Config = No address check
// Bit Rate = 0.825
// Carrier Frequency = 144.174988
// Deviation = 2.994537
// Device Address = 0
// Manchester Enable = false
// Modulation Format = 2-FSK
// Packet Bit Length = 0
// Packet Length = 63
// Packet Length Mode = Not supported
// RX Filter BW = 14.880952
// Symbol rate = 0.825
// Whitening = false

#include <stdio.h>
#include <stdint.h>
#include "cc1200.h"

// Bit Rate = 0.825kHz
static const cc1200_reg_settings_t APRS_TX_RATE[]=
{
		{CC120X_SYMBOL_RATE2, 0x35},
		{CC120X_SYMBOL_RATE1, 0xA0},
		{CC120X_SYMBOL_RATE0, 0x7B}
};

// Bit Rate = 13.2kHz
static const cc1200_reg_settings_t APRS_RX_RATE[]=
{
		{CC120X_SYMBOL_RATE2, 0x75},
		{CC120X_SYMBOL_RATE1, 0xA0},
		{CC120X_SYMBOL_RATE0, 0x7B}
};

static const cc1200_reg_settings_t APRS_RX_SETTINGS[]=
{
  {CC120X_IOCFG3,            0x1e},	// TX Clock
  {CC120X_IOCFG2,			 0x1d},	// RX Clock
  {CC120X_IOCFG0,            0x09},
  {CC120X_SYNC_CFG1,         0x00},	// Disable Sync Word [0x00]
  {CC120X_SYNC_CFG0,		 0x13}, // Disable RX_CONFIG_LIMITATION 0x13
  {CC120X_DEVIATION_M,       0x9D},
  {CC120X_MODCFG_DEV_E,      0x00},
  {CC120X_DCFILT_CFG,        0x5D},
  {CC120X_PREAMBLE_CFG1,     0x00},
  {CC120X_PREAMBLE_CFG0,     0x00},	// Disable Preamble [0x00]
  {CC120X_IQIC,              0xCB},
  {CC120X_CHAN_BW,           0x9C},
  {CC120X_MDMCFG1, 			 0x00},	// Random guess
  {CC120X_MDMCFG0,           0x45},
  //{CC120X_MDMCFG0,           0x05},
  // 6 kHz
  {CC120X_SYMBOL_RATE2,      0x63},
  {CC120X_SYMBOL_RATE1,      0xA9},
  {CC120X_SYMBOL_RATE0,      0x2A},
  {CC120X_AGC_REF,           0x30},
  {CC120X_AGC_CS_THR,        0xEC},
  {CC120X_AGC_CFG3, 		 0x11}, // new
  {CC120X_AGC_CFG1,          0x51},
  {CC120X_AGC_CFG0,          0x87},
  {CC120X_FIFO_CFG,          0x00},
  {CC120X_FS_CFG,            0x1B},
  {CC120X_PKT_CFG2,          0x03},
  {CC120X_PKT_CFG1,          0x00},
  {CC120X_PKT_CFG0,          0x40},	// new
  {CC120X_RFEND_CFG1,        0x0F},	// new
  {CC120X_RFEND_CFG0,        0x00},
  {CC120X_PA_CFG1,           0x3F},
  {CC120X_PKT_LEN,           0xFF},
  {CC120X_IF_MIX_CFG,        0x1C},
  {CC120X_FREQOFF_CFG,       0x22},
  {CC120X_MDMCFG2,           0x0B},		// need to set CFM_DATA_EN bit for CFM mode and reduce upsampler rate
  {CC120X_FREQ2,             0x56},
  {CC120X_FREQ1,             0x81},
  {CC120X_FREQ0,             0x47},
  {CC120X_IF_ADC1,           0xEE},
  {CC120X_IF_ADC0,           0x10},
  {CC120X_FS_DIG1,           0x07},
  {CC120X_FS_DIG0,           0xAF},
  {CC120X_FS_CAL1,           0x40},
  {CC120X_FS_CAL0,           0x0E},
  {CC120X_FS_DIVTWO,         0x03},
  {CC120X_FS_DSM0,           0x33},
  {CC120X_FS_DVC0,           0x17},
  {CC120X_FS_PFD,            0x00},
  {CC120X_FS_PRE,            0x6E},
  {CC120X_FS_REG_DIV_CML,    0x1C},
  {CC120X_FS_SPARE,          0xAC},
  {CC120X_FS_VCO0,           0xB5},
  {CC120X_XOSC5,             0x0E},
  {CC120X_XOSC1,             0x03},
};

static const cc1200_reg_settings_t APRS_TX_SETTINGS[]=
{
  {CC120X_IOCFG3,            0x1e},	// 0x1e for TX 0x1D for RX
  {CC120X_IOCFG0,            0x1d},
  {CC120X_SYNC_CFG1,         0xAB},
  {CC120X_DEVIATION_M,       0x9D},
  {CC120X_MODCFG_DEV_E,      0x00},
  {CC120X_DCFILT_CFG,        0x5D},
  {CC120X_PREAMBLE_CFG1,     0x00},
  {CC120X_PREAMBLE_CFG0,     0x8A},
  {CC120X_IQIC,              0xCB},
  {CC120X_CHAN_BW,           0x9C},
  {CC120X_MDMCFG0,           0x05},
  {CC120X_SYMBOL_RATE2,      0x35},
  {CC120X_SYMBOL_RATE1,      0xA0},
  {CC120X_SYMBOL_RATE0,      0x7B},
  {CC120X_AGC_REF,           0x30},
  {CC120X_AGC_CS_THR,        0xEC},
  {CC120X_AGC_CFG1,          0x51},
  {CC120X_AGC_CFG0,          0x87},
  {CC120X_FIFO_CFG,          0x00},
  {CC120X_FS_CFG,            0x1B},
  {CC120X_PKT_CFG2,          0x02},
  {CC120X_PKT_CFG1,          0x00},
  {CC120X_PKT_CFG0,          0x40},
  {CC120X_PA_CFG1,           0x3F},
  {CC120X_PKT_LEN,           0x3F},
  {CC120X_IF_MIX_CFG,        0x1C},
  {CC120X_FREQOFF_CFG,       0x22},
  {CC120X_MDMCFG2,           0x0D},		// need to set CFM_DATA_EN bit for CFM mode
  {CC120X_FREQ2,             0x56},
  {CC120X_FREQ1,             0x81},
  {CC120X_FREQ0,             0x47},
  {CC120X_IF_ADC1,           0xEE},
  {CC120X_IF_ADC0,           0x10},
  {CC120X_FS_DIG1,           0x07},
  {CC120X_FS_DIG0,           0xAF},
  {CC120X_FS_CAL1,           0x40},
  {CC120X_FS_CAL0,           0x0E},
  {CC120X_FS_DIVTWO,         0x03},
  {CC120X_FS_DSM0,           0x33},
  {CC120X_FS_DVC0,           0x17},
  {CC120X_FS_PFD,            0x00},
  {CC120X_FS_PRE,            0x6E},
  {CC120X_FS_REG_DIV_CML,    0x1C},
  {CC120X_FS_SPARE,          0xAC},
  {CC120X_FS_VCO0,           0xB5},
  {CC120X_XOSC5,             0x0E},
  {CC120X_XOSC1,             0x03},
};

// Address Config = No address check
// Bit Rate = 1.2
// Carrier Frequency = 144.389954
// Deviation = 4.997253
// Device Address = 0
// Manchester Enable = false
// Modulation Format = 2-FSK
// Packet Bit Length = 0
// Packet Length = 255
// Packet Length Mode = Variable
// RX Filter BW = 14.880952
// Symbol rate = 1.2
// Whitening = false

static const cc1200_reg_settings_t APRS_RX2_SETTINGS[]=
{
  {CC120X_IOCFG2,            0x08},
  {CC120X_IOCFG0,            0x09},
  {CC120X_SYNC_CFG1,         0x3F},
  {CC120X_MODCFG_DEV_E,      0x01},
  {CC120X_DCFILT_CFG,        0x5D},
  {CC120X_PREAMBLE_CFG1,     0x00},
  {CC120X_PREAMBLE_CFG0,     0x8A},
  {CC120X_IQIC,              0xCB},
  {CC120X_CHAN_BW,           0x9C},
  {CC120X_MDMCFG1,           0x00},
  {CC120X_MDMCFG0,           0x45},
  {CC120X_SYMBOL_RATE2,      0x3F},
  {CC120X_SYMBOL_RATE1,      0x75},
  {CC120X_SYMBOL_RATE0,      0x10},
  {CC120X_AGC_REF,           0x30},
  {CC120X_AGC_CS_THR,        0xEC},
  {CC120X_AGC_CFG3,          0x11},
  {CC120X_AGC_CFG1,          0x51},
  {CC120X_AGC_CFG0,          0x87},
  {CC120X_FIFO_CFG,          0x00},
  {CC120X_FS_CFG,            0x1B},
  {CC120X_PKT_CFG2,          0x03},
  {CC120X_PKT_CFG1,          0x00},
  {CC120X_PKT_CFG0,          0x20},
  {CC120X_PA_CFG1,           0x3F},
  {CC120X_PKT_LEN,           0xFF},
  {CC120X_IF_MIX_CFG,        0x1C},
  {CC120X_FREQOFF_CFG,       0x22},
  {CC120X_MDMCFG2,           0x0D},
  {CC120X_FREQ2,             0x56},
  {CC120X_FREQ1,             0xA2},
  {CC120X_FREQ0,             0x4C},
  {CC120X_IF_ADC1,           0xEE},
  {CC120X_IF_ADC0,           0x10},
  {CC120X_FS_DIG1,           0x07},
  {CC120X_FS_DIG0,           0xAF},
  {CC120X_FS_CAL1,           0x40},
  {CC120X_FS_CAL0,           0x0E},
  {CC120X_FS_DIVTWO,         0x03},
  {CC120X_FS_DSM0,           0x33},
  {CC120X_FS_DVC0,           0x17},
  {CC120X_FS_PFD,            0x00},
  {CC120X_FS_PRE,            0x6E},
  {CC120X_FS_REG_DIV_CML,    0x1C},
  {CC120X_FS_SPARE,          0xAC},
  {CC120X_FS_VCO0,           0xB5},
  {CC120X_XOSC5,             0x0E},
  {CC120X_XOSC1,             0x03},
  {CC120X_SERIAL_STATUS,     0x08},
};

// Address Config = No address check
// Bit Rate = 1.2
// Carrier Frequency = 144.389954
// Deviation = 4.997253
// Device Address = 0
// Manchester Enable = false
// Modulation Format = 2-FSK
// Packet Bit Length = 0
// Packet Length = 255
// Packet Length Mode = Variable
// RX Filter BW = 14.880952
// Symbol rate = 1.2
// Whitening = false

static const cc1200_reg_settings_t APRS_TX2_SETTINGS[]=
{
  {CC120X_IOCFG2,            0x08},
  {CC120X_IOCFG0,            0x09},
  {CC120X_SYNC_CFG1,         0x0B},
  {CC120X_MODCFG_DEV_E,      0x01},
  {CC120X_DCFILT_CFG,        0x5D},
  {CC120X_PREAMBLE_CFG1,     0x00},
  {CC120X_PREAMBLE_CFG0,     0x8A},
  {CC120X_IQIC,              0xCB},
  {CC120X_CHAN_BW,           0x9C},
  {CC120X_MDMCFG1,           0x06},
  {CC120X_MDMCFG0,           0x45},
  {CC120X_SYMBOL_RATE2,      0x3F},
  {CC120X_SYMBOL_RATE1,      0x75},
  {CC120X_SYMBOL_RATE0,      0x10},
  {CC120X_AGC_REF,           0x30},
  {CC120X_AGC_CS_THR,        0xEC},
  {CC120X_AGC_CFG1,          0x51},
  {CC120X_AGC_CFG0,          0x87},
  {CC120X_FIFO_CFG,          0x00},
  {CC120X_FS_CFG,            0x1B},
  {CC120X_PKT_CFG2,          0x03},
  {CC120X_PKT_CFG1,          0x00},
  {CC120X_PKT_CFG0,          0x20},
  {CC120X_PA_CFG1,           0x3F},
  {CC120X_PKT_LEN,           0xFF},
  {CC120X_IF_MIX_CFG,        0x1C},
  {CC120X_FREQOFF_CFG,       0x22},
  {CC120X_MDMCFG2,           0x0D},
  {CC120X_FREQ2,             0x56},
  {CC120X_FREQ1,             0xA2},
  {CC120X_FREQ0,             0x4C},
  {CC120X_IF_ADC1,           0xEE},
  {CC120X_IF_ADC0,           0x10},
  {CC120X_FS_DIG1,           0x07},
  {CC120X_FS_DIG0,           0xAF},
  {CC120X_FS_CAL1,           0x40},
  {CC120X_FS_CAL0,           0x0E},
  {CC120X_FS_DIVTWO,         0x03},
  {CC120X_FS_DSM0,           0x33},
  {CC120X_FS_DVC0,           0x17},
  {CC120X_FS_PFD,            0x00},
  {CC120X_FS_PRE,            0x6E},
  {CC120X_FS_REG_DIV_CML,    0x1C},
  {CC120X_FS_SPARE,          0xAC},
  {CC120X_FS_VCO0,           0xB5},
  {CC120X_XOSC5,             0x0E},
  {CC120X_XOSC1,             0x03},
  {CC120X_SERIAL_STATUS,     0x08},
};