cc1200_spi_ripper.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000002cc 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000a544 080002d0 080002d0 000102d0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000228 0800a814 0800a814 0001a814 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .init_array 00000004 0800aa3c 0800aa3c 0001aa3c 2**2 CONTENTS, ALLOC, LOAD, DATA 4 .fini_array 00000004 0800aa40 0800aa40 0001aa40 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .data 000001e8 24000000 0800aa44 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 6 .bss 00001b8c 240001e8 0800ac2c 000201e8 2**2 ALLOC 7 ._user_heap_stack 00000604 24001d74 0800ac2c 00021d74 2**0 ALLOC 8 .ARM.attributes 0000002e 00000000 00000000 000201e8 2**0 CONTENTS, READONLY 9 .debug_info 0002d67a 00000000 00000000 00020216 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 10 .debug_abbrev 000052c9 00000000 00000000 0004d890 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_aranges 00001740 00000000 00000000 00052b60 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_ranges 00001578 00000000 00000000 000542a0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0003a87c 00000000 00000000 00055818 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 0001cba1 00000000 00000000 00090094 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 001622a6 00000000 00000000 000acc35 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000053 00000000 00000000 0020eedb 2**0 CONTENTS, READONLY 17 .debug_frame 00006a10 00000000 00000000 0020ef30 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002d0 <__do_global_dtors_aux>: 80002d0: b510 push {r4, lr} 80002d2: 4c05 ldr r4, [pc, #20] ; (80002e8 <__do_global_dtors_aux+0x18>) 80002d4: 7823 ldrb r3, [r4, #0] 80002d6: b933 cbnz r3, 80002e6 <__do_global_dtors_aux+0x16> 80002d8: 4b04 ldr r3, [pc, #16] ; (80002ec <__do_global_dtors_aux+0x1c>) 80002da: b113 cbz r3, 80002e2 <__do_global_dtors_aux+0x12> 80002dc: 4804 ldr r0, [pc, #16] ; (80002f0 <__do_global_dtors_aux+0x20>) 80002de: f3af 8000 nop.w 80002e2: 2301 movs r3, #1 80002e4: 7023 strb r3, [r4, #0] 80002e6: bd10 pop {r4, pc} 80002e8: 240001e8 .word 0x240001e8 80002ec: 00000000 .word 0x00000000 80002f0: 0800a7fc .word 0x0800a7fc 080002f4 : 80002f4: b508 push {r3, lr} 80002f6: 4b03 ldr r3, [pc, #12] ; (8000304 ) 80002f8: b11b cbz r3, 8000302 80002fa: 4903 ldr r1, [pc, #12] ; (8000308 ) 80002fc: 4803 ldr r0, [pc, #12] ; (800030c ) 80002fe: f3af 8000 nop.w 8000302: bd08 pop {r3, pc} 8000304: 00000000 .word 0x00000000 8000308: 240001ec .word 0x240001ec 800030c: 0800a7fc .word 0x0800a7fc 08000310 : 8000310: f001 01ff and.w r1, r1, #255 ; 0xff 8000314: 2a10 cmp r2, #16 8000316: db2b blt.n 8000370 8000318: f010 0f07 tst.w r0, #7 800031c: d008 beq.n 8000330 800031e: f810 3b01 ldrb.w r3, [r0], #1 8000322: 3a01 subs r2, #1 8000324: 428b cmp r3, r1 8000326: d02d beq.n 8000384 8000328: f010 0f07 tst.w r0, #7 800032c: b342 cbz r2, 8000380 800032e: d1f6 bne.n 800031e 8000330: b4f0 push {r4, r5, r6, r7} 8000332: ea41 2101 orr.w r1, r1, r1, lsl #8 8000336: ea41 4101 orr.w r1, r1, r1, lsl #16 800033a: f022 0407 bic.w r4, r2, #7 800033e: f07f 0700 mvns.w r7, #0 8000342: 2300 movs r3, #0 8000344: e8f0 5602 ldrd r5, r6, [r0], #8 8000348: 3c08 subs r4, #8 800034a: ea85 0501 eor.w r5, r5, r1 800034e: ea86 0601 eor.w r6, r6, r1 8000352: fa85 f547 uadd8 r5, r5, r7 8000356: faa3 f587 sel r5, r3, r7 800035a: fa86 f647 uadd8 r6, r6, r7 800035e: faa5 f687 sel r6, r5, r7 8000362: b98e cbnz r6, 8000388 8000364: d1ee bne.n 8000344 8000366: bcf0 pop {r4, r5, r6, r7} 8000368: f001 01ff and.w r1, r1, #255 ; 0xff 800036c: f002 0207 and.w r2, r2, #7 8000370: b132 cbz r2, 8000380 8000372: f810 3b01 ldrb.w r3, [r0], #1 8000376: 3a01 subs r2, #1 8000378: ea83 0301 eor.w r3, r3, r1 800037c: b113 cbz r3, 8000384 800037e: d1f8 bne.n 8000372 8000380: 2000 movs r0, #0 8000382: 4770 bx lr 8000384: 3801 subs r0, #1 8000386: 4770 bx lr 8000388: 2d00 cmp r5, #0 800038a: bf06 itte eq 800038c: 4635 moveq r5, r6 800038e: 3803 subeq r0, #3 8000390: 3807 subne r0, #7 8000392: f015 0f01 tst.w r5, #1 8000396: d107 bne.n 80003a8 8000398: 3001 adds r0, #1 800039a: f415 7f80 tst.w r5, #256 ; 0x100 800039e: bf02 ittt eq 80003a0: 3001 addeq r0, #1 80003a2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000 80003a6: 3001 addeq r0, #1 80003a8: bcf0 pop {r4, r5, r6, r7} 80003aa: 3801 subs r0, #1 80003ac: 4770 bx lr 80003ae: bf00 nop 080003b0 : * @rmtoll CR1 SPE LL_SPI_Enable * @param SPIx SPI Instance * @retval None */ __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) { 80003b0: b480 push {r7} 80003b2: b083 sub sp, #12 80003b4: af00 add r7, sp, #0 80003b6: 6078 str r0, [r7, #4] SET_BIT(SPIx->CR1, SPI_CR1_SPE); 80003b8: 687b ldr r3, [r7, #4] 80003ba: 681b ldr r3, [r3, #0] 80003bc: f043 0201 orr.w r2, r3, #1 80003c0: 687b ldr r3, [r7, #4] 80003c2: 601a str r2, [r3, #0] } 80003c4: bf00 nop 80003c6: 370c adds r7, #12 80003c8: 46bd mov sp, r7 80003ca: f85d 7b04 ldr.w r7, [sp], #4 80003ce: 4770 bx lr 080003d0 : * @rmtoll CR1 SPE LL_SPI_Disable * @param SPIx SPI Instance * @retval None */ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) { 80003d0: b480 push {r7} 80003d2: b083 sub sp, #12 80003d4: af00 add r7, sp, #0 80003d6: 6078 str r0, [r7, #4] CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 80003d8: 687b ldr r3, [r7, #4] 80003da: 681b ldr r3, [r3, #0] 80003dc: f023 0201 bic.w r2, r3, #1 80003e0: 687b ldr r3, [r7, #4] 80003e2: 601a str r2, [r3, #0] } 80003e4: bf00 nop 80003e6: 370c adds r7, #12 80003e8: 46bd mov sp, r7 80003ea: f85d 7b04 ldr.w r7, [sp], #4 80003ee: 4770 bx lr 080003f0 : * @param SPIx SPI Instance * @param Count 0..0xFFFF * @retval None */ __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count) { 80003f0: b480 push {r7} 80003f2: b083 sub sp, #12 80003f4: af00 add r7, sp, #0 80003f6: 6078 str r0, [r7, #4] 80003f8: 6039 str r1, [r7, #0] MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count); 80003fa: 687b ldr r3, [r7, #4] 80003fc: 685a ldr r2, [r3, #4] 80003fe: 4b06 ldr r3, [pc, #24] ; (8000418 ) 8000400: 4013 ands r3, r2 8000402: 683a ldr r2, [r7, #0] 8000404: 431a orrs r2, r3 8000406: 687b ldr r3, [r7, #4] 8000408: 605a str r2, [r3, #4] } 800040a: bf00 nop 800040c: 370c adds r7, #12 800040e: 46bd mov sp, r7 8000410: f85d 7b04 ldr.w r7, [sp], #4 8000414: 4770 bx lr 8000416: bf00 nop 8000418: ffff0000 .word 0xffff0000 0800041c : * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer * @param SPIx SPI Instance * @retval None */ __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx) { 800041c: b480 push {r7} 800041e: b083 sub sp, #12 8000420: af00 add r7, sp, #0 8000422: 6078 str r0, [r7, #4] SET_BIT(SPIx->CR1, SPI_CR1_CSTART); 8000424: 687b ldr r3, [r7, #4] 8000426: 681b ldr r3, [r3, #0] 8000428: f443 7200 orr.w r2, r3, #512 ; 0x200 800042c: 687b ldr r3, [r7, #4] 800042e: 601a str r2, [r3, #0] } 8000430: bf00 nop 8000432: 370c adds r7, #12 8000434: 46bd mov sp, r7 8000436: f85d 7b04 ldr.w r7, [sp], #4 800043a: 4770 bx lr 0800043c : * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx) { 800043c: b480 push {r7} 800043e: b083 sub sp, #12 8000440: af00 add r7, sp, #0 8000442: 6078 str r0, [r7, #4] return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL); 8000444: 687b ldr r3, [r7, #4] 8000446: 695b ldr r3, [r3, #20] 8000448: f003 0301 and.w r3, r3, #1 800044c: 2b01 cmp r3, #1 800044e: d101 bne.n 8000454 8000450: 2301 movs r3, #1 8000452: e000 b.n 8000456 8000454: 2300 movs r3, #0 } 8000456: 4618 mov r0, r3 8000458: 370c adds r7, #12 800045a: 46bd mov sp, r7 800045c: f85d 7b04 ldr.w r7, [sp], #4 8000460: 4770 bx lr 08000462 : * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx) { 8000462: b480 push {r7} 8000464: b083 sub sp, #12 8000466: af00 add r7, sp, #0 8000468: 6078 str r0, [r7, #4] return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL); 800046a: 687b ldr r3, [r7, #4] 800046c: 695b ldr r3, [r3, #20] 800046e: f003 0308 and.w r3, r3, #8 8000472: 2b08 cmp r3, #8 8000474: d101 bne.n 800047a 8000476: 2301 movs r3, #1 8000478: e000 b.n 800047c 800047a: 2300 movs r3, #0 } 800047c: 4618 mov r0, r3 800047e: 370c adds r7, #12 8000480: 46bd mov sp, r7 8000482: f85d 7b04 ldr.w r7, [sp], #4 8000486: 4770 bx lr 08000488 : * @rmtoll RXDR . LL_SPI_ReceiveData8 * @param SPIx SPI Instance * @retval 0..0xFF */ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) { 8000488: b480 push {r7} 800048a: b083 sub sp, #12 800048c: af00 add r7, sp, #0 800048e: 6078 str r0, [r7, #4] return (*((__IO uint8_t *)&SPIx->RXDR)); 8000490: 687b ldr r3, [r7, #4] 8000492: 3330 adds r3, #48 ; 0x30 8000494: 781b ldrb r3, [r3, #0] 8000496: b2db uxtb r3, r3 } 8000498: 4618 mov r0, r3 800049a: 370c adds r7, #12 800049c: 46bd mov sp, r7 800049e: f85d 7b04 ldr.w r7, [sp], #4 80004a2: 4770 bx lr 080004a4 : * @param SPIx SPI Instance * @param TxData 0..0xFF * @retval None */ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) { 80004a4: b480 push {r7} 80004a6: b083 sub sp, #12 80004a8: af00 add r7, sp, #0 80004aa: 6078 str r0, [r7, #4] 80004ac: 460b mov r3, r1 80004ae: 70fb strb r3, [r7, #3] *((__IO uint8_t *)&SPIx->TXDR) = TxData; 80004b0: 687b ldr r3, [r7, #4] 80004b2: 3320 adds r3, #32 80004b4: 78fa ldrb r2, [r7, #3] 80004b6: 701a strb r2, [r3, #0] } 80004b8: bf00 nop 80004ba: 370c adds r7, #12 80004bc: 46bd mov sp, r7 80004be: f85d 7b04 ldr.w r7, [sp], #4 80004c2: 4770 bx lr 080004c4 : * @param SPIx SPI Instance * @param TxData 0..0xFFFF * @retval None */ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) { 80004c4: b480 push {r7} 80004c6: b085 sub sp, #20 80004c8: af00 add r7, sp, #0 80004ca: 6078 str r0, [r7, #4] 80004cc: 460b mov r3, r1 80004ce: 807b strh r3, [r7, #2] #if defined (__GNUC__) __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR); 80004d0: 687b ldr r3, [r7, #4] 80004d2: 3320 adds r3, #32 80004d4: 60fb str r3, [r7, #12] *spitxdr = TxData; 80004d6: 68fb ldr r3, [r7, #12] 80004d8: 887a ldrh r2, [r7, #2] 80004da: 801a strh r2, [r3, #0] #else SPIx->TXDR = TxData; #endif /* __GNUC__ */ } 80004dc: bf00 nop 80004de: 3714 adds r7, #20 80004e0: 46bd mov sp, r7 80004e2: f85d 7b04 ldr.w r7, [sp], #4 80004e6: 4770 bx lr 080004e8 : * @param SPIx SPI Instance * @param TxData 0..0xFFFFFFFF * @retval None */ __STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) { 80004e8: b480 push {r7} 80004ea: b083 sub sp, #12 80004ec: af00 add r7, sp, #0 80004ee: 6078 str r0, [r7, #4] 80004f0: 6039 str r1, [r7, #0] *((__IO uint32_t *)&SPIx->TXDR) = TxData; 80004f2: 687b ldr r3, [r7, #4] 80004f4: 683a ldr r2, [r7, #0] 80004f6: 621a str r2, [r3, #32] } 80004f8: bf00 nop 80004fa: 370c adds r7, #12 80004fc: 46bd mov sp, r7 80004fe: f85d 7b04 ldr.w r7, [sp], #4 8000502: 4770 bx lr 08000504 : #define CC1200_READ_BIT 0b10000000 #define CC1200_BURST_BIT 0b01000000 void SPI1_TransmitBytes(uint8_t *p_buf, uint8_t len) { 8000504: b580 push {r7, lr} 8000506: b082 sub sp, #8 8000508: af00 add r7, sp, #0 800050a: 6078 str r0, [r7, #4] 800050c: 460b mov r3, r1 800050e: 70fb strb r3, [r7, #3] LL_SPI_SetTransferSize(SPI1, len); 8000510: 78fb ldrb r3, [r7, #3] 8000512: 4619 mov r1, r3 8000514: 481f ldr r0, [pc, #124] ; (8000594 ) 8000516: f7ff ff6b bl 80003f0 LL_SPI_Enable(SPI1); 800051a: 481e ldr r0, [pc, #120] ; (8000594 ) 800051c: f7ff ff48 bl 80003b0 LL_SPI_StartMasterTransfer(SPI1); 8000520: 481c ldr r0, [pc, #112] ; (8000594 ) 8000522: f7ff ff7b bl 800041c switch(len) 8000526: 78fb ldrb r3, [r7, #3] 8000528: 2b03 cmp r3, #3 800052a: d014 beq.n 8000556 800052c: 2b03 cmp r3, #3 800052e: dc19 bgt.n 8000564 8000530: 2b01 cmp r3, #1 8000532: d002 beq.n 800053a 8000534: 2b02 cmp r3, #2 8000536: d007 beq.n 8000548 8000538: e014 b.n 8000564 { case 1: LL_SPI_TransmitData8(SPI1, *p_buf); 800053a: 687b ldr r3, [r7, #4] 800053c: 781b ldrb r3, [r3, #0] 800053e: 4619 mov r1, r3 8000540: 4814 ldr r0, [pc, #80] ; (8000594 ) 8000542: f7ff ffaf bl 80004a4 break; 8000546: e013 b.n 8000570 case 2: LL_SPI_TransmitData16(SPI1, *(uint16_t *)p_buf); 8000548: 687b ldr r3, [r7, #4] 800054a: 881b ldrh r3, [r3, #0] 800054c: 4619 mov r1, r3 800054e: 4811 ldr r0, [pc, #68] ; (8000594 ) 8000550: f7ff ffb8 bl 80004c4 break; 8000554: e00c b.n 8000570 case 3: LL_SPI_TransmitData32(SPI1, *(uint32_t *)p_buf); 8000556: 687b ldr r3, [r7, #4] 8000558: 681b ldr r3, [r3, #0] 800055a: 4619 mov r1, r3 800055c: 480d ldr r0, [pc, #52] ; (8000594 ) 800055e: f7ff ffc3 bl 80004e8 break; 8000562: e005 b.n 8000570 default: assert(0); 8000564: 4b0c ldr r3, [pc, #48] ; (8000598 ) 8000566: 4a0d ldr r2, [pc, #52] ; (800059c ) 8000568: 212f movs r1, #47 ; 0x2f 800056a: 480d ldr r0, [pc, #52] ; (80005a0 ) 800056c: f009 f95a bl 8009824 <__assert_func> } // Wait until the transmission is complete while( LL_SPI_IsActiveFlag_EOT(SPI1) == 0); 8000570: bf00 nop 8000572: 4808 ldr r0, [pc, #32] ; (8000594 ) 8000574: f7ff ff75 bl 8000462 8000578: 4603 mov r3, r0 800057a: 2b00 cmp r3, #0 800057c: d0f9 beq.n 8000572 SPI1->IFCR = UINT32_MAX; 800057e: 4b05 ldr r3, [pc, #20] ; (8000594 ) 8000580: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8000584: 619a str r2, [r3, #24] LL_SPI_Disable(SPI1); 8000586: 4803 ldr r0, [pc, #12] ; (8000594 ) 8000588: f7ff ff22 bl 80003d0 } 800058c: bf00 nop 800058e: 3708 adds r7, #8 8000590: 46bd mov sp, r7 8000592: bd80 pop {r7, pc} 8000594: 40013000 .word 0x40013000 8000598: 0800a814 .word 0x0800a814 800059c: 0800a878 .word 0x0800a878 80005a0: 0800a818 .word 0x0800a818 080005a4 : uint8_t SPI1_ReceiveByte(void) { 80005a4: b580 push {r7, lr} 80005a6: b082 sub sp, #8 80005a8: af00 add r7, sp, #0 uint8_t rxByte; LL_SPI_SetTransferSize(SPI1, 1); 80005aa: 2101 movs r1, #1 80005ac: 4815 ldr r0, [pc, #84] ; (8000604 ) 80005ae: f7ff ff1f bl 80003f0 LL_SPI_Enable(SPI1); 80005b2: 4814 ldr r0, [pc, #80] ; (8000604 ) 80005b4: f7ff fefc bl 80003b0 LL_SPI_StartMasterTransfer(SPI1); 80005b8: 4812 ldr r0, [pc, #72] ; (8000604 ) 80005ba: f7ff ff2f bl 800041c LL_SPI_TransmitData8(SPI1, 0); 80005be: 2100 movs r1, #0 80005c0: 4810 ldr r0, [pc, #64] ; (8000604 ) 80005c2: f7ff ff6f bl 80004a4 while (LL_SPI_IsActiveFlag_RXP(SPI1) == 0); 80005c6: bf00 nop 80005c8: 480e ldr r0, [pc, #56] ; (8000604 ) 80005ca: f7ff ff37 bl 800043c 80005ce: 4603 mov r3, r0 80005d0: 2b00 cmp r3, #0 80005d2: d0f9 beq.n 80005c8 rxByte = LL_SPI_ReceiveData8(SPI1); 80005d4: 480b ldr r0, [pc, #44] ; (8000604 ) 80005d6: f7ff ff57 bl 8000488 80005da: 4603 mov r3, r0 80005dc: 71fb strb r3, [r7, #7] // Wait until the transmission is complete while( LL_SPI_IsActiveFlag_EOT(SPI1) == 0); 80005de: bf00 nop 80005e0: 4808 ldr r0, [pc, #32] ; (8000604 ) 80005e2: f7ff ff3e bl 8000462 80005e6: 4603 mov r3, r0 80005e8: 2b00 cmp r3, #0 80005ea: d0f9 beq.n 80005e0 SPI1->IFCR = UINT32_MAX; 80005ec: 4b05 ldr r3, [pc, #20] ; (8000604 ) 80005ee: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80005f2: 619a str r2, [r3, #24] LL_SPI_Disable(SPI1); 80005f4: 4803 ldr r0, [pc, #12] ; (8000604 ) 80005f6: f7ff feeb bl 80003d0 return rxByte; 80005fa: 79fb ldrb r3, [r7, #7] } 80005fc: 4618 mov r0, r3 80005fe: 3708 adds r7, #8 8000600: 46bd mov sp, r7 8000602: bd80 pop {r7, pc} 8000604: 40013000 .word 0x40013000 08000608 : uint8_t SPI1_TransmitReceive(uint8_t *p_buf, uint8_t len) { 8000608: b580 push {r7, lr} 800060a: b082 sub sp, #8 800060c: af00 add r7, sp, #0 800060e: 6078 str r0, [r7, #4] 8000610: 460b mov r3, r1 8000612: 70fb strb r3, [r7, #3] SPI1_TransmitBytes(p_buf, len); 8000614: 78fb ldrb r3, [r7, #3] 8000616: 4619 mov r1, r3 8000618: 6878 ldr r0, [r7, #4] 800061a: f7ff ff73 bl 8000504 return SPI1_ReceiveByte(); 800061e: f7ff ffc1 bl 80005a4 8000622: 4603 mov r3, r0 } 8000624: 4618 mov r0, r3 8000626: 3708 adds r7, #8 8000628: 46bd mov sp, r7 800062a: bd80 pop {r7, pc} 0800062c : // TODO: Fix to use HAL. static void cc1200_spi_write_byte(uint16_t addr, uint8_t data) { 800062c: b580 push {r7, lr} 800062e: b084 sub sp, #16 8000630: af00 add r7, sp, #0 8000632: 4603 mov r3, r0 8000634: 460a mov r2, r1 8000636: 80fb strh r3, [r7, #6] 8000638: 4613 mov r3, r2 800063a: 717b strb r3, [r7, #5] // set the data field HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 0); 800063c: 2200 movs r2, #0 800063e: 2140 movs r1, #64 ; 0x40 8000640: 4815 ldr r0, [pc, #84] ; (8000698 ) 8000642: f001 fa95 bl 8001b70 if ((addr & 0xFF00) != 0) // send data with extended address in command field 8000646: 88fb ldrh r3, [r7, #6] 8000648: f403 437f and.w r3, r3, #65280 ; 0xff00 800064c: 2b00 cmp r3, #0 800064e: d00f beq.n 8000670 { txBuf[0] = ((uint8_t *)&addr)[1]; 8000650: 79fb ldrb r3, [r7, #7] 8000652: 733b strb r3, [r7, #12] txBuf[1] = ((uint8_t *)&addr)[0]; 8000654: 1dbb adds r3, r7, #6 8000656: 781b ldrb r3, [r3, #0] 8000658: 737b strb r3, [r7, #13] txBuf[0] |= CC1200_WRITE_BIT; 800065a: 7b3b ldrb r3, [r7, #12] 800065c: 733b strb r3, [r7, #12] txBuf[2] = data; 800065e: 797b ldrb r3, [r7, #5] 8000660: 73bb strb r3, [r7, #14] SPI1_TransmitBytes(txBuf, 3); 8000662: f107 030c add.w r3, r7, #12 8000666: 2103 movs r1, #3 8000668: 4618 mov r0, r3 800066a: f7ff ff4b bl 8000504 800066e: e00a b.n 8000686 } else { // correctly configure the addr field. txBuf[0] = (uint8_t)addr | CC1200_WRITE_BIT; 8000670: 88fb ldrh r3, [r7, #6] 8000672: b2db uxtb r3, r3 8000674: 733b strb r3, [r7, #12] txBuf[1] = data; 8000676: 797b ldrb r3, [r7, #5] 8000678: 737b strb r3, [r7, #13] SPI1_TransmitBytes(txBuf, 2); 800067a: f107 030c add.w r3, r7, #12 800067e: 2102 movs r1, #2 8000680: 4618 mov r0, r3 8000682: f7ff ff3f bl 8000504 } HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 1); 8000686: 2201 movs r2, #1 8000688: 2140 movs r1, #64 ; 0x40 800068a: 4803 ldr r0, [pc, #12] ; (8000698 ) 800068c: f001 fa70 bl 8001b70 } 8000690: bf00 nop 8000692: 3710 adds r7, #16 8000694: 46bd mov sp, r7 8000696: bd80 pop {r7, pc} 8000698: 58020800 .word 0x58020800 0800069c : // ESP_ERROR_CHECK(ret); //} // TODO: Fix to use HAL. static void cc1200_spi_read_byte(uint16_t addr, uint8_t* data) { 800069c: b580 push {r7, lr} 800069e: b084 sub sp, #16 80006a0: af00 add r7, sp, #0 80006a2: 4603 mov r3, r0 80006a4: 6039 str r1, [r7, #0] 80006a6: 80fb strh r3, [r7, #6] uint8_t rxBuf[3]; uint8_t txBuf[3]; // correctly configure the addr field. txBuf[0] = (uint8_t)addr | CC1200_READ_BIT; 80006a8: 88fb ldrh r3, [r7, #6] 80006aa: b2db uxtb r3, r3 80006ac: f063 037f orn r3, r3, #127 ; 0x7f 80006b0: b2db uxtb r3, r3 80006b2: 723b strb r3, [r7, #8] HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 0); 80006b4: 2200 movs r2, #0 80006b6: 2140 movs r1, #64 ; 0x40 80006b8: 4817 ldr r0, [pc, #92] ; (8000718 ) 80006ba: f001 fa59 bl 8001b70 if ((addr & 0xFF00) != 0) // read data with extended address in command field 80006be: 88fb ldrh r3, [r7, #6] 80006c0: f403 437f and.w r3, r3, #65280 ; 0xff00 80006c4: 2b00 cmp r3, #0 80006c6: d014 beq.n 80006f2 { txBuf[0] = ((uint8_t *)&addr)[1]; 80006c8: 79fb ldrb r3, [r7, #7] 80006ca: 723b strb r3, [r7, #8] txBuf[1] = ((uint8_t *)&addr)[0]; 80006cc: 1dbb adds r3, r7, #6 80006ce: 781b ldrb r3, [r3, #0] 80006d0: 727b strb r3, [r7, #9] txBuf[0] |= CC1200_READ_BIT; 80006d2: 7a3b ldrb r3, [r7, #8] 80006d4: f063 037f orn r3, r3, #127 ; 0x7f 80006d8: b2db uxtb r3, r3 80006da: 723b strb r3, [r7, #8] *data = SPI1_TransmitReceive(txBuf, 2); 80006dc: f107 0308 add.w r3, r7, #8 80006e0: 2102 movs r1, #2 80006e2: 4618 mov r0, r3 80006e4: f7ff ff90 bl 8000608 80006e8: 4603 mov r3, r0 80006ea: 461a mov r2, r3 80006ec: 683b ldr r3, [r7, #0] 80006ee: 701a strb r2, [r3, #0] 80006f0: e009 b.n 8000706 } else { *data = SPI1_TransmitReceive(txBuf, 1); 80006f2: f107 0308 add.w r3, r7, #8 80006f6: 2101 movs r1, #1 80006f8: 4618 mov r0, r3 80006fa: f7ff ff85 bl 8000608 80006fe: 4603 mov r3, r0 8000700: 461a mov r2, r3 8000702: 683b ldr r3, [r7, #0] 8000704: 701a strb r2, [r3, #0] } HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 1); 8000706: 2201 movs r2, #1 8000708: 2140 movs r1, #64 ; 0x40 800070a: 4803 ldr r0, [pc, #12] ; (8000718 ) 800070c: f001 fa30 bl 8001b70 } 8000710: bf00 nop 8000712: 3710 adds r7, #16 8000714: 46bd mov sp, r7 8000716: bd80 pop {r7, pc} 8000718: 58020800 .word 0x58020800 0800071c : // ESP_ERROR_CHECK(ret); //} // TODO: Fix to use HAL. rf_status_t cc1200_spi_strobe(uint8_t cmd) { 800071c: b580 push {r7, lr} 800071e: b084 sub sp, #16 8000720: af00 add r7, sp, #0 8000722: 4603 mov r3, r0 8000724: 71fb strb r3, [r7, #7] uint8_t txBuf[2]; txBuf[0] = cmd; 8000726: 79fb ldrb r3, [r7, #7] 8000728: 733b strb r3, [r7, #12] HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 0); 800072a: 2200 movs r2, #0 800072c: 2140 movs r1, #64 ; 0x40 800072e: 481c ldr r0, [pc, #112] ; (80007a0 ) 8000730: f001 fa1e bl 8001b70 uint8_t rxByte; LL_SPI_SetTransferSize(SPI1, 1); 8000734: 2101 movs r1, #1 8000736: 481b ldr r0, [pc, #108] ; (80007a4 ) 8000738: f7ff fe5a bl 80003f0 LL_SPI_Enable(SPI1); 800073c: 4819 ldr r0, [pc, #100] ; (80007a4 ) 800073e: f7ff fe37 bl 80003b0 LL_SPI_StartMasterTransfer(SPI1); 8000742: 4818 ldr r0, [pc, #96] ; (80007a4 ) 8000744: f7ff fe6a bl 800041c LL_SPI_TransmitData8(SPI1, cmd); 8000748: 79fb ldrb r3, [r7, #7] 800074a: 4619 mov r1, r3 800074c: 4815 ldr r0, [pc, #84] ; (80007a4 ) 800074e: f7ff fea9 bl 80004a4 while (LL_SPI_IsActiveFlag_RXP(SPI1) == 0); 8000752: bf00 nop 8000754: 4813 ldr r0, [pc, #76] ; (80007a4 ) 8000756: f7ff fe71 bl 800043c 800075a: 4603 mov r3, r0 800075c: 2b00 cmp r3, #0 800075e: d0f9 beq.n 8000754 rxByte = LL_SPI_ReceiveData8(SPI1); 8000760: 4810 ldr r0, [pc, #64] ; (80007a4 ) 8000762: f7ff fe91 bl 8000488 8000766: 4603 mov r3, r0 8000768: 73fb strb r3, [r7, #15] // Wait until the transmission is complete while( LL_SPI_IsActiveFlag_EOT(SPI1) == 0); 800076a: bf00 nop 800076c: 480d ldr r0, [pc, #52] ; (80007a4 ) 800076e: f7ff fe78 bl 8000462 8000772: 4603 mov r3, r0 8000774: 2b00 cmp r3, #0 8000776: d0f9 beq.n 800076c SPI1->IFCR = UINT32_MAX; 8000778: 4b0a ldr r3, [pc, #40] ; (80007a4 ) 800077a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 800077e: 619a str r2, [r3, #24] LL_SPI_Disable(SPI1); 8000780: 4808 ldr r0, [pc, #32] ; (80007a4 ) 8000782: f7ff fe25 bl 80003d0 HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 1); 8000786: 2201 movs r2, #1 8000788: 2140 movs r1, #64 ; 0x40 800078a: 4805 ldr r0, [pc, #20] ; (80007a0 ) 800078c: f001 f9f0 bl 8001b70 return rxByte & 0xF0; 8000790: 7bfb ldrb r3, [r7, #15] 8000792: f023 030f bic.w r3, r3, #15 8000796: b2db uxtb r3, r3 } 8000798: 4618 mov r0, r3 800079a: 3710 adds r7, #16 800079c: 46bd mov sp, r7 800079e: bd80 pop {r7, pc} 80007a0: 58020800 .word 0x58020800 80007a4: 40013000 .word 0x40013000 080007a8 : cc1200_spi_read_byte(CC120X_RSSI1, &data); return data; } uint8_t cc1200_radio_read_CFM(void) { 80007a8: b580 push {r7, lr} 80007aa: b082 sub sp, #8 80007ac: af00 add r7, sp, #0 uint8_t data = 0; 80007ae: 2300 movs r3, #0 80007b0: 71fb strb r3, [r7, #7] cc1200_spi_read_byte(CC120X_CFM_RX_DATA_OUT, &data); 80007b2: 1dfb adds r3, r7, #7 80007b4: 4619 mov r1, r3 80007b6: f642 707d movw r0, #12157 ; 0x2f7d 80007ba: f7ff ff6f bl 800069c return data; 80007be: 79fb ldrb r3, [r7, #7] } 80007c0: 4618 mov r0, r3 80007c2: 3708 adds r7, #8 80007c4: 46bd mov sp, r7 80007c6: bd80 pop {r7, pc} 080007c8 : { cc1200_spi_write_byte(CC120X_CFM_TX_DATA_IN, data); } rf_status_t cc1200_radio_reset(void) { 80007c8: b580 push {r7, lr} 80007ca: b082 sub sp, #8 80007cc: af00 add r7, sp, #0 rf_status_t status; uint8_t retry_count = 0; 80007ce: 2300 movs r3, #0 80007d0: 71bb strb r3, [r7, #6] cc1200_spi_strobe(CC120X_SRES); // soft reset the chip 80007d2: 2030 movs r0, #48 ; 0x30 80007d4: f7ff ffa2 bl 800071c status = cc1200_spi_strobe(CC120X_SNOP); // get chip status 80007d8: 203d movs r0, #61 ; 0x3d 80007da: f7ff ff9f bl 800071c 80007de: 4603 mov r3, r0 80007e0: 71fb strb r3, [r7, #7] HAL_Delay(20); 80007e2: 2014 movs r0, #20 80007e4: f000 fee8 bl 80015b8 while((CC120X_RDYn_BIT & (status & 0x80))) // if chip isn't ready, wait 10ms 80007e8: e00d b.n 8000806 { HAL_Delay(10); 80007ea: 200a movs r0, #10 80007ec: f000 fee4 bl 80015b8 if (retry_count > 3) 80007f0: 79bb ldrb r3, [r7, #6] 80007f2: 2b03 cmp r3, #3 80007f4: d80c bhi.n 8000810 { break; } status = cc1200_spi_strobe(CC120X_SNOP); 80007f6: 203d movs r0, #61 ; 0x3d 80007f8: f7ff ff90 bl 800071c 80007fc: 4603 mov r3, r0 80007fe: 71fb strb r3, [r7, #7] retry_count++; 8000800: 79bb ldrb r3, [r7, #6] 8000802: 3301 adds r3, #1 8000804: 71bb strb r3, [r7, #6] while((CC120X_RDYn_BIT & (status & 0x80))) // if chip isn't ready, wait 10ms 8000806: f997 3007 ldrsb.w r3, [r7, #7] 800080a: 2b00 cmp r3, #0 800080c: dbed blt.n 80007ea 800080e: e000 b.n 8000812 break; 8000810: bf00 nop } return status; 8000812: 79fb ldrb r3, [r7, #7] } 8000814: 4618 mov r0, r3 8000816: 3708 adds r7, #8 8000818: 46bd mov sp, r7 800081a: bd80 pop {r7, pc} 800081c: 0000 movs r0, r0 ... 08000820 : #define CC1200_LO_DIVIDER 24 // 136.7 - 160 MHz Band #define CC1200_XOSC 40000000 // 40MHz void cc1200_radio_frequency(uint32_t freq) { 8000820: b580 push {r7, lr} 8000822: b084 sub sp, #16 8000824: af00 add r7, sp, #0 8000826: 6078 str r0, [r7, #4] // f_VCO = FREQ / 2^16 * f_XOSX + FREQOFF / 2^18 * F_XOSC double temp_freq; // calculate FREQ0, FREQ, FREQ2 registers temp_freq = ((double) freq * 65536 * CC1200_LO_DIVIDER) / CC1200_XOSC; 8000828: 687b ldr r3, [r7, #4] 800082a: ee07 3a90 vmov s15, r3 800082e: eeb8 7b67 vcvt.f64.u32 d7, s15 8000832: ed9f 6b19 vldr d6, [pc, #100] ; 8000898 8000836: ee27 7b06 vmul.f64 d7, d7, d6 800083a: eeb3 6b08 vmov.f64 d6, #56 ; 0x41c00000 24.0 800083e: ee27 6b06 vmul.f64 d6, d7, d6 8000842: ed9f 5b17 vldr d5, [pc, #92] ; 80008a0 8000846: ee86 7b05 vdiv.f64 d7, d6, d5 800084a: ed87 7b02 vstr d7, [r7, #8] freq = (uint32_t)temp_freq; 800084e: ed97 7b02 vldr d7, [r7, #8] 8000852: eefc 7bc7 vcvt.u32.f64 s15, d7 8000856: ee17 3a90 vmov r3, s15 800085a: 607b str r3, [r7, #4] cc1200_spi_write_byte(CC120X_FREQ0, ((uint8_t *)&freq)[0]); 800085c: 1d3b adds r3, r7, #4 800085e: 781b ldrb r3, [r3, #0] 8000860: 4619 mov r1, r3 8000862: f642 700e movw r0, #12046 ; 0x2f0e 8000866: f7ff fee1 bl 800062c cc1200_spi_write_byte(CC120X_FREQ1, ((uint8_t *)&freq)[1]); 800086a: 1d3b adds r3, r7, #4 800086c: 3301 adds r3, #1 800086e: 781b ldrb r3, [r3, #0] 8000870: 4619 mov r1, r3 8000872: f642 700d movw r0, #12045 ; 0x2f0d 8000876: f7ff fed9 bl 800062c cc1200_spi_write_byte(CC120X_FREQ2, ((uint8_t *)&freq)[2]); 800087a: 1d3b adds r3, r7, #4 800087c: 3302 adds r3, #2 800087e: 781b ldrb r3, [r3, #0] 8000880: 4619 mov r1, r3 8000882: f642 700c movw r0, #12044 ; 0x2f0c 8000886: f7ff fed1 bl 800062c return ; 800088a: bf00 nop } 800088c: 3710 adds r7, #16 800088e: 46bd mov sp, r7 8000890: bd80 pop {r7, pc} 8000892: bf00 nop 8000894: f3af 8000 nop.w 8000898: 00000000 .word 0x00000000 800089c: 40f00000 .word 0x40f00000 80008a0: 00000000 .word 0x00000000 80008a4: 418312d0 .word 0x418312d0 080008a8 : // TODO: Create exception for failure condition while (cc1200_spi_strobe(CC120X_STX) != CC120X_STATE_TX); } void cc1200_radio_rx(void) { 80008a8: b580 push {r7, lr} 80008aa: af00 add r7, sp, #0 // TODO: Create exception for failure condition while (cc1200_spi_strobe(CC120X_SRX) != CC120X_STATE_RX); 80008ac: bf00 nop 80008ae: 2034 movs r0, #52 ; 0x34 80008b0: f7ff ff34 bl 800071c 80008b4: 4603 mov r3, r0 80008b6: 2b10 cmp r3, #16 80008b8: d1f9 bne.n 80008ae } 80008ba: bf00 nop 80008bc: bf00 nop 80008be: bd80 pop {r7, pc} 080008c0 : // TODO: Fix to use HAL. void cc1200_radio_init(const cc1200_reg_settings_t* rf_settings, uint8_t len) { 80008c0: b580 push {r7, lr} 80008c2: b084 sub sp, #16 80008c4: af00 add r7, sp, #0 80008c6: 6078 str r0, [r7, #4] 80008c8: 460b mov r3, r1 80008ca: 70fb strb r3, [r7, #3] //cc1200_gpio_init(); //cc1200_spi_init(); cc1200_radio_reset(); //gpio_set_level(CC1200_RESET, 1); 80008cc: f7ff ff7c bl 80007c8 uint8_t i; for (i=0;i { cc1200_spi_write_byte(rf_settings[i].addr, rf_settings[i].data); 80008d6: 7bfb ldrb r3, [r7, #15] 80008d8: 009b lsls r3, r3, #2 80008da: 687a ldr r2, [r7, #4] 80008dc: 4413 add r3, r2 80008de: 8818 ldrh r0, [r3, #0] 80008e0: 7bfb ldrb r3, [r7, #15] 80008e2: 009b lsls r3, r3, #2 80008e4: 687a ldr r2, [r7, #4] 80008e6: 4413 add r3, r2 80008e8: 789b ldrb r3, [r3, #2] 80008ea: 4619 mov r1, r3 80008ec: f7ff fe9e bl 800062c for (i=0;i } while(cc1200_spi_strobe(CC120X_SIDLE) != CC120X_STATE_IDLE); 80008fe: bf00 nop 8000900: 2036 movs r0, #54 ; 0x36 8000902: f7ff ff0b bl 800071c 8000906: 4603 mov r3, r0 8000908: 2b00 cmp r3, #0 800090a: d1f9 bne.n 8000900 } 800090c: bf00 nop 800090e: bf00 nop 8000910: 3710 adds r7, #16 8000912: 46bd mov sp, r7 8000914: bd80 pop {r7, pc} 08000916 : { 8000916: b480 push {r7} 8000918: b083 sub sp, #12 800091a: af00 add r7, sp, #0 800091c: 6078 str r0, [r7, #4] 800091e: 6039 str r1, [r7, #0] MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard); 8000920: 687b ldr r3, [r7, #4] 8000922: 68db ldr r3, [r3, #12] 8000924: f423 1260 bic.w r2, r3, #3670016 ; 0x380000 8000928: 683b ldr r3, [r7, #0] 800092a: 431a orrs r2, r3 800092c: 687b ldr r3, [r7, #4] 800092e: 60da str r2, [r3, #12] } 8000930: bf00 nop 8000932: 370c adds r7, #12 8000934: 46bd mov sp, r7 8000936: f85d 7b04 ldr.w r7, [sp], #4 800093a: 4770 bx lr 0800093c : { 800093c: b480 push {r7} 800093e: b083 sub sp, #12 8000940: af00 add r7, sp, #0 8000942: 6078 str r0, [r7, #4] SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM); 8000944: 687b ldr r3, [r7, #4] 8000946: 68db ldr r3, [r3, #12] 8000948: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000 800094c: 687b ldr r3, [r7, #4] 800094e: 60da str r2, [r3, #12] } 8000950: bf00 nop 8000952: 370c adds r7, #12 8000954: 46bd mov sp, r7 8000956: f85d 7b04 ldr.w r7, [sp], #4 800095a: 4770 bx lr 0800095c : * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) { 800095c: b480 push {r7} 800095e: b085 sub sp, #20 8000960: af00 add r7, sp, #0 8000962: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, Periphs); 8000964: 4b0a ldr r3, [pc, #40] ; (8000990 ) 8000966: f8d3 20e0 ldr.w r2, [r3, #224] ; 0xe0 800096a: 4909 ldr r1, [pc, #36] ; (8000990 ) 800096c: 687b ldr r3, [r7, #4] 800096e: 4313 orrs r3, r2 8000970: f8c1 30e0 str.w r3, [r1, #224] ; 0xe0 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB4ENR, Periphs); 8000974: 4b06 ldr r3, [pc, #24] ; (8000990 ) 8000976: f8d3 20e0 ldr.w r2, [r3, #224] ; 0xe0 800097a: 687b ldr r3, [r7, #4] 800097c: 4013 ands r3, r2 800097e: 60fb str r3, [r7, #12] (void)tmpreg; 8000980: 68fb ldr r3, [r7, #12] } 8000982: bf00 nop 8000984: 3714 adds r7, #20 8000986: 46bd mov sp, r7 8000988: f85d 7b04 ldr.w r7, [sp], #4 800098c: 4770 bx lr 800098e: bf00 nop 8000990: 58024400 .word 0x58024400 08000994 : * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) { 8000994: b480 push {r7} 8000996: b085 sub sp, #20 8000998: af00 add r7, sp, #0 800099a: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, Periphs); 800099c: 4b0a ldr r3, [pc, #40] ; (80009c8 ) 800099e: f8d3 20f0 ldr.w r2, [r3, #240] ; 0xf0 80009a2: 4909 ldr r1, [pc, #36] ; (80009c8 ) 80009a4: 687b ldr r3, [r7, #4] 80009a6: 4313 orrs r3, r2 80009a8: f8c1 30f0 str.w r3, [r1, #240] ; 0xf0 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 80009ac: 4b06 ldr r3, [pc, #24] ; (80009c8 ) 80009ae: f8d3 20f0 ldr.w r2, [r3, #240] ; 0xf0 80009b2: 687b ldr r3, [r7, #4] 80009b4: 4013 ands r3, r2 80009b6: 60fb str r3, [r7, #12] (void)tmpreg; 80009b8: 68fb ldr r3, [r7, #12] } 80009ba: bf00 nop 80009bc: 3714 adds r7, #20 80009be: 46bd mov sp, r7 80009c0: f85d 7b04 ldr.w r7, [sp], #4 80009c4: 4770 bx lr 80009c6: bf00 nop 80009c8: 58024400 .word 0x58024400 080009cc : } static uint8_t txBuffer; void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim) { 80009cc: b580 push {r7, lr} 80009ce: b082 sub sp, #8 80009d0: af00 add r7, sp, #0 80009d2: 6078 str r0, [r7, #4] txBuffer = cc1200_radio_read_CFM(); 80009d4: f7ff fee8 bl 80007a8 80009d8: 4603 mov r3, r0 80009da: 461a mov r2, r3 80009dc: 4b0c ldr r3, [pc, #48] ; (8000a10 ) 80009de: 701a strb r2, [r3, #0] //cc1200_radio_write_CFM(0); CDC_Transmit_HS(&txBuffer, 1); 80009e0: 2101 movs r1, #1 80009e2: 480b ldr r0, [pc, #44] ; (8000a10 ) 80009e4: f008 fa9a bl 8008f1c // Toggle LED as heart beat. static uint32_t toggleCount = 0; if (toggleCount++ == 40000) 80009e8: 4b0a ldr r3, [pc, #40] ; (8000a14 ) 80009ea: 681b ldr r3, [r3, #0] 80009ec: 1c5a adds r2, r3, #1 80009ee: 4909 ldr r1, [pc, #36] ; (8000a14 ) 80009f0: 600a str r2, [r1, #0] 80009f2: f649 4240 movw r2, #40000 ; 0x9c40 80009f6: 4293 cmp r3, r2 80009f8: d106 bne.n 8000a08 { HAL_GPIO_TogglePin(LED_GREEN_GPIO_Port, LED_GREEN_Pin); 80009fa: 2101 movs r1, #1 80009fc: 4806 ldr r0, [pc, #24] ; (8000a18 ) 80009fe: f001 f8d0 bl 8001ba2 toggleCount = 0; 8000a02: 4b04 ldr r3, [pc, #16] ; (8000a14 ) 8000a04: 2200 movs r2, #0 8000a06: 601a str r2, [r3, #0] } } 8000a08: bf00 nop 8000a0a: 3708 adds r7, #8 8000a0c: 46bd mov sp, r7 8000a0e: bd80 pop {r7, pc} 8000a10: 24000204 .word 0x24000204 8000a14: 24000208 .word 0x24000208 8000a18: 58020400 .word 0x58020400 08000a1c
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000a1c: b580 push {r7, lr} 8000a1e: b084 sub sp, #16 8000a20: af00 add r7, sp, #0 \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 8000a22: 4b48 ldr r3, [pc, #288] ; (8000b44 ) 8000a24: 695b ldr r3, [r3, #20] 8000a26: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000a2a: 2b00 cmp r3, #0 8000a2c: d11b bne.n 8000a66 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 8000a2e: f3bf 8f4f dsb sy } 8000a32: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000a34: f3bf 8f6f isb sy } 8000a38: bf00 nop __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 8000a3a: 4b42 ldr r3, [pc, #264] ; (8000b44 ) 8000a3c: 2200 movs r2, #0 8000a3e: f8c3 2250 str.w r2, [r3, #592] ; 0x250 __ASM volatile ("dsb 0xF":::"memory"); 8000a42: f3bf 8f4f dsb sy } 8000a46: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000a48: f3bf 8f6f isb sy } 8000a4c: bf00 nop __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 8000a4e: 4b3d ldr r3, [pc, #244] ; (8000b44 ) 8000a50: 695b ldr r3, [r3, #20] 8000a52: 4a3c ldr r2, [pc, #240] ; (8000b44 ) 8000a54: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000a58: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000a5a: f3bf 8f4f dsb sy } 8000a5e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000a60: f3bf 8f6f isb sy } 8000a64: e000 b.n 8000a68 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 8000a66: bf00 nop #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000a68: 4b36 ldr r3, [pc, #216] ; (8000b44 ) 8000a6a: 695b ldr r3, [r3, #20] 8000a6c: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000a70: 2b00 cmp r3, #0 8000a72: d138 bne.n 8000ae6 SCB->CSSELR = 0U; /* select Level 1 data cache */ 8000a74: 4b33 ldr r3, [pc, #204] ; (8000b44 ) 8000a76: 2200 movs r2, #0 8000a78: f8c3 2084 str.w r2, [r3, #132] ; 0x84 __ASM volatile ("dsb 0xF":::"memory"); 8000a7c: f3bf 8f4f dsb sy } 8000a80: bf00 nop __DSB(); ccsidr = SCB->CCSIDR; 8000a82: 4b30 ldr r3, [pc, #192] ; (8000b44 ) 8000a84: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8000a88: 60bb str r3, [r7, #8] /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 8000a8a: 68bb ldr r3, [r7, #8] 8000a8c: 0b5b lsrs r3, r3, #13 8000a8e: f3c3 030e ubfx r3, r3, #0, #15 8000a92: 607b str r3, [r7, #4] do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 8000a94: 68bb ldr r3, [r7, #8] 8000a96: 08db lsrs r3, r3, #3 8000a98: f3c3 0309 ubfx r3, r3, #0, #10 8000a9c: 603b str r3, [r7, #0] do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 8000a9e: 687b ldr r3, [r7, #4] 8000aa0: 015a lsls r2, r3, #5 8000aa2: f643 73e0 movw r3, #16352 ; 0x3fe0 8000aa6: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 8000aa8: 683a ldr r2, [r7, #0] 8000aaa: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 8000aac: 4925 ldr r1, [pc, #148] ; (8000b44 ) 8000aae: 4313 orrs r3, r2 8000ab0: f8c1 3260 str.w r3, [r1, #608] ; 0x260 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); 8000ab4: 683b ldr r3, [r7, #0] 8000ab6: 1e5a subs r2, r3, #1 8000ab8: 603a str r2, [r7, #0] 8000aba: 2b00 cmp r3, #0 8000abc: d1ef bne.n 8000a9e } while(sets-- != 0U); 8000abe: 687b ldr r3, [r7, #4] 8000ac0: 1e5a subs r2, r3, #1 8000ac2: 607a str r2, [r7, #4] 8000ac4: 2b00 cmp r3, #0 8000ac6: d1e5 bne.n 8000a94 __ASM volatile ("dsb 0xF":::"memory"); 8000ac8: f3bf 8f4f dsb sy } 8000acc: bf00 nop __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 8000ace: 4b1d ldr r3, [pc, #116] ; (8000b44 ) 8000ad0: 695b ldr r3, [r3, #20] 8000ad2: 4a1c ldr r2, [pc, #112] ; (8000b44 ) 8000ad4: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000ad8: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000ada: f3bf 8f4f dsb sy } 8000ade: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000ae0: f3bf 8f6f isb sy } 8000ae4: e000 b.n 8000ae8 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000ae6: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000ae8: f000 fcd4 bl 8001494 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000aec: f000 f834 bl 8000b58 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000af0: f000 f98a bl 8000e08 MX_SPI1_Init(); 8000af4: f000 f8a0 bl 8000c38 MX_TIM3_Init(); 8000af8: f000 f938 bl 8000d6c MX_USB_DEVICE_Init(); 8000afc: f008 f94e bl 8008d9c /* USER CODE BEGIN 2 */ HAL_StatusTypeDef errCode; // Manually reset the CC1200. HAL_GPIO_WritePin(CC1200_RESET_GPIO_Port, CC1200_RESET_Pin, 0); 8000b00: 2200 movs r2, #0 8000b02: f44f 5180 mov.w r1, #4096 ; 0x1000 8000b06: 4810 ldr r0, [pc, #64] ; (8000b48 ) 8000b08: f001 f832 bl 8001b70 HAL_Delay(50); 8000b0c: 2032 movs r0, #50 ; 0x32 8000b0e: f000 fd53 bl 80015b8 HAL_GPIO_WritePin(CC1200_RESET_GPIO_Port, CC1200_RESET_Pin, 1); 8000b12: 2201 movs r2, #1 8000b14: f44f 5180 mov.w r1, #4096 ; 0x1000 8000b18: 480b ldr r0, [pc, #44] ; (8000b48 ) 8000b1a: f001 f829 bl 8001b70 HAL_Delay(50); 8000b1e: 2032 movs r0, #50 ; 0x32 8000b20: f000 fd4a bl 80015b8 // Setup up the 5million registers. cc1200_radio_init((cc1200_reg_settings_t *)AX25_SETTINGS, sizeof(AX25_SETTINGS)/sizeof(cc1200_reg_settings_t)); 8000b24: 2133 movs r1, #51 ; 0x33 8000b26: 4809 ldr r0, [pc, #36] ; (8000b4c ) 8000b28: f7ff feca bl 80008c0 // Set frequency cc1200_radio_frequency(144390000); 8000b2c: 4808 ldr r0, [pc, #32] ; (8000b50 ) 8000b2e: f7ff fe77 bl 8000820 // Enable TX/RX cc1200_radio_rx(); 8000b32: f7ff feb9 bl 80008a8 // Start Timer for SPI errCode = HAL_TIM_Base_Start_IT(&htim3); 8000b36: 4807 ldr r0, [pc, #28] ; (8000b54 ) 8000b38: f004 fa28 bl 8004f8c 8000b3c: 4603 mov r3, r0 8000b3e: 73fb strb r3, [r7, #15] /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000b40: e7fe b.n 8000b40 8000b42: bf00 nop 8000b44: e000ed00 .word 0xe000ed00 8000b48: 58020400 .word 0x58020400 8000b4c: 0800a88c .word 0x0800a88c 8000b50: 089b3770 .word 0x089b3770 8000b54: 2400043c .word 0x2400043c 08000b58 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000b58: b580 push {r7, lr} 8000b5a: b09c sub sp, #112 ; 0x70 8000b5c: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000b5e: f107 0324 add.w r3, r7, #36 ; 0x24 8000b62: 224c movs r2, #76 ; 0x4c 8000b64: 2100 movs r1, #0 8000b66: 4618 mov r0, r3 8000b68: f008 feb6 bl 80098d8 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000b6c: 1d3b adds r3, r7, #4 8000b6e: 2220 movs r2, #32 8000b70: 2100 movs r1, #0 8000b72: 4618 mov r0, r3 8000b74: f008 feb0 bl 80098d8 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 8000b78: 2002 movs r0, #2 8000b7a: f002 f9fb bl 8002f74 /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); 8000b7e: 2300 movs r3, #0 8000b80: 603b str r3, [r7, #0] 8000b82: 4b2c ldr r3, [pc, #176] ; (8000c34 ) 8000b84: 699b ldr r3, [r3, #24] 8000b86: 4a2b ldr r2, [pc, #172] ; (8000c34 ) 8000b88: f423 4340 bic.w r3, r3, #49152 ; 0xc000 8000b8c: 6193 str r3, [r2, #24] 8000b8e: 4b29 ldr r3, [pc, #164] ; (8000c34 ) 8000b90: 699b ldr r3, [r3, #24] 8000b92: f403 4340 and.w r3, r3, #49152 ; 0xc000 8000b96: 603b str r3, [r7, #0] 8000b98: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 8000b9a: bf00 nop 8000b9c: 4b25 ldr r3, [pc, #148] ; (8000c34 ) 8000b9e: 699b ldr r3, [r3, #24] 8000ba0: f403 5300 and.w r3, r3, #8192 ; 0x2000 8000ba4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8000ba8: d1f8 bne.n 8000b9c /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE; 8000baa: 2321 movs r3, #33 ; 0x21 8000bac: 627b str r3, [r7, #36] ; 0x24 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; 8000bae: f44f 23a0 mov.w r3, #327680 ; 0x50000 8000bb2: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 8000bb4: 2301 movs r3, #1 8000bb6: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000bb8: 2302 movs r3, #2 8000bba: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000bbc: 2302 movs r3, #2 8000bbe: 64fb str r3, [r7, #76] ; 0x4c RCC_OscInitStruct.PLL.PLLM = 4; 8000bc0: 2304 movs r3, #4 8000bc2: 653b str r3, [r7, #80] ; 0x50 RCC_OscInitStruct.PLL.PLLN = 275; 8000bc4: f240 1313 movw r3, #275 ; 0x113 8000bc8: 657b str r3, [r7, #84] ; 0x54 RCC_OscInitStruct.PLL.PLLP = 1; 8000bca: 2301 movs r3, #1 8000bcc: 65bb str r3, [r7, #88] ; 0x58 RCC_OscInitStruct.PLL.PLLQ = 4; 8000bce: 2304 movs r3, #4 8000bd0: 65fb str r3, [r7, #92] ; 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 8000bd2: 2302 movs r3, #2 8000bd4: 663b str r3, [r7, #96] ; 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; 8000bd6: 2304 movs r3, #4 8000bd8: 667b str r3, [r7, #100] ; 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 8000bda: 2300 movs r3, #0 8000bdc: 66bb str r3, [r7, #104] ; 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 8000bde: 2300 movs r3, #0 8000be0: 66fb str r3, [r7, #108] ; 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000be2: f107 0324 add.w r3, r7, #36 ; 0x24 8000be6: 4618 mov r0, r3 8000be8: f002 fa0e bl 8003008 8000bec: 4603 mov r3, r0 8000bee: 2b00 cmp r3, #0 8000bf0: d001 beq.n 8000bf6 { Error_Handler(); 8000bf2: f000 fa61 bl 80010b8 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000bf6: 233f movs r3, #63 ; 0x3f 8000bf8: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000bfa: 2303 movs r3, #3 8000bfc: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 8000bfe: 2300 movs r3, #0 8000c00: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 8000c02: 2308 movs r3, #8 8000c04: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 8000c06: 2340 movs r3, #64 ; 0x40 8000c08: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 8000c0a: 2340 movs r3, #64 ; 0x40 8000c0c: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000c0e: f44f 6380 mov.w r3, #1024 ; 0x400 8000c12: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000c14: 2340 movs r3, #64 ; 0x40 8000c16: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) 8000c18: 1d3b adds r3, r7, #4 8000c1a: 2103 movs r1, #3 8000c1c: 4618 mov r0, r3 8000c1e: f002 fd9f bl 8003760 8000c22: 4603 mov r3, r0 8000c24: 2b00 cmp r3, #0 8000c26: d001 beq.n 8000c2c { Error_Handler(); 8000c28: f000 fa46 bl 80010b8 } } 8000c2c: bf00 nop 8000c2e: 3770 adds r7, #112 ; 0x70 8000c30: 46bd mov sp, r7 8000c32: bd80 pop {r7, pc} 8000c34: 58024800 .word 0x58024800 08000c38 : * @brief SPI1 Initialization Function * @param None * @retval None */ static void MX_SPI1_Init(void) { 8000c38: b580 push {r7, lr} 8000c3a: b0be sub sp, #248 ; 0xf8 8000c3c: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_Init 0 */ /* USER CODE END SPI1_Init 0 */ LL_SPI_InitTypeDef SPI_InitStruct = {0}; 8000c3e: f107 03d0 add.w r3, r7, #208 ; 0xd0 8000c42: 2228 movs r2, #40 ; 0x28 8000c44: 2100 movs r1, #0 8000c46: 4618 mov r0, r3 8000c48: f008 fe46 bl 80098d8 LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000c4c: f107 03b8 add.w r3, r7, #184 ; 0xb8 8000c50: 2200 movs r2, #0 8000c52: 601a str r2, [r3, #0] 8000c54: 605a str r2, [r3, #4] 8000c56: 609a str r2, [r3, #8] 8000c58: 60da str r2, [r3, #12] 8000c5a: 611a str r2, [r3, #16] 8000c5c: 615a str r2, [r3, #20] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000c5e: 1d3b adds r3, r7, #4 8000c60: 22b4 movs r2, #180 ; 0xb4 8000c62: 2100 movs r1, #0 8000c64: 4618 mov r0, r3 8000c66: f008 fe37 bl 80098d8 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI1; 8000c6a: f44f 5380 mov.w r3, #4096 ; 0x1000 8000c6e: 607b str r3, [r7, #4] PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; 8000c70: 2300 movs r3, #0 8000c72: 65fb str r3, [r7, #92] ; 0x5c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000c74: 1d3b adds r3, r7, #4 8000c76: 4618 mov r0, r3 8000c78: f003 f8d2 bl 8003e20 8000c7c: 4603 mov r3, r0 8000c7e: 2b00 cmp r3, #0 8000c80: d001 beq.n 8000c86 { Error_Handler(); 8000c82: f000 fa19 bl 80010b8 } /* Peripheral clock enable */ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1); 8000c86: f44f 5080 mov.w r0, #4096 ; 0x1000 8000c8a: f7ff fe83 bl 8000994 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA); 8000c8e: 2001 movs r0, #1 8000c90: f7ff fe64 bl 800095c LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD); 8000c94: 2008 movs r0, #8 8000c96: f7ff fe61 bl 800095c /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO PD7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = LL_GPIO_PIN_5|LL_GPIO_PIN_6; 8000c9a: 2360 movs r3, #96 ; 0x60 8000c9c: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 8000ca0: 2302 movs r3, #2 8000ca2: f8c7 30bc str.w r3, [r7, #188] ; 0xbc GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 8000ca6: 2303 movs r3, #3 8000ca8: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 8000cac: 2300 movs r3, #0 8000cae: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 8000cb2: 2300 movs r3, #0 8000cb4: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 8000cb8: 2305 movs r3, #5 8000cba: f8c7 30cc str.w r3, [r7, #204] ; 0xcc LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000cbe: f107 03b8 add.w r3, r7, #184 ; 0xb8 8000cc2: 4619 mov r1, r3 8000cc4: 4826 ldr r0, [pc, #152] ; (8000d60 ) 8000cc6: f004 feff bl 8005ac8 GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 8000cca: 2380 movs r3, #128 ; 0x80 8000ccc: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 8000cd0: 2302 movs r3, #2 8000cd2: f8c7 30bc str.w r3, [r7, #188] ; 0xbc GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 8000cd6: 2303 movs r3, #3 8000cd8: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 8000cdc: 2300 movs r3, #0 8000cde: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 8000ce2: 2300 movs r3, #0 8000ce4: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 8000ce8: 2305 movs r3, #5 8000cea: f8c7 30cc str.w r3, [r7, #204] ; 0xcc LL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000cee: f107 03b8 add.w r3, r7, #184 ; 0xb8 8000cf2: 4619 mov r1, r3 8000cf4: 481b ldr r0, [pc, #108] ; (8000d64 ) 8000cf6: f004 fee7 bl 8005ac8 /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ /* SPI1 parameter configuration*/ SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; 8000cfa: 2300 movs r3, #0 8000cfc: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 8000d00: f44f 0380 mov.w r3, #4194304 ; 0x400000 8000d04: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_8BIT; 8000d08: 2307 movs r3, #7 8000d0a: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; 8000d0e: 2300 movs r3, #0 8000d10: f8c7 30dc str.w r3, [r7, #220] ; 0xdc SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 8000d14: 2300 movs r3, #0 8000d16: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 8000d1a: f04f 6380 mov.w r3, #67108864 ; 0x4000000 8000d1e: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV32; 8000d22: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 8000d26: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 8000d2a: 2300 movs r3, #0 8000d2c: f8c7 30ec str.w r3, [r7, #236] ; 0xec SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 8000d30: 2300 movs r3, #0 8000d32: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0 SPI_InitStruct.CRCPoly = 0x0; 8000d36: 2300 movs r3, #0 8000d38: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4 LL_SPI_Init(SPI1, &SPI_InitStruct); 8000d3c: f107 03d0 add.w r3, r7, #208 ; 0xd0 8000d40: 4619 mov r1, r3 8000d42: 4809 ldr r0, [pc, #36] ; (8000d68 ) 8000d44: f004 ff70 bl 8005c28 LL_SPI_SetStandard(SPI1, LL_SPI_PROTOCOL_MOTOROLA); 8000d48: 2100 movs r1, #0 8000d4a: 4807 ldr r0, [pc, #28] ; (8000d68 ) 8000d4c: f7ff fde3 bl 8000916 LL_SPI_EnableNSSPulseMgt(SPI1); 8000d50: 4805 ldr r0, [pc, #20] ; (8000d68 ) 8000d52: f7ff fdf3 bl 800093c /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } 8000d56: bf00 nop 8000d58: 37f8 adds r7, #248 ; 0xf8 8000d5a: 46bd mov sp, r7 8000d5c: bd80 pop {r7, pc} 8000d5e: bf00 nop 8000d60: 58020000 .word 0x58020000 8000d64: 58020c00 .word 0x58020c00 8000d68: 40013000 .word 0x40013000 08000d6c : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 8000d6c: b580 push {r7, lr} 8000d6e: b088 sub sp, #32 8000d70: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8000d72: f107 0310 add.w r3, r7, #16 8000d76: 2200 movs r2, #0 8000d78: 601a str r2, [r3, #0] 8000d7a: 605a str r2, [r3, #4] 8000d7c: 609a str r2, [r3, #8] 8000d7e: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000d80: 1d3b adds r3, r7, #4 8000d82: 2200 movs r2, #0 8000d84: 601a str r2, [r3, #0] 8000d86: 605a str r2, [r3, #4] 8000d88: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8000d8a: 4b1d ldr r3, [pc, #116] ; (8000e00 ) 8000d8c: 4a1d ldr r2, [pc, #116] ; (8000e04 ) 8000d8e: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 8000d90: 4b1b ldr r3, [pc, #108] ; (8000e00 ) 8000d92: 2200 movs r2, #0 8000d94: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8000d96: 4b1a ldr r3, [pc, #104] ; (8000e00 ) 8000d98: 2200 movs r2, #0 8000d9a: 609a str r2, [r3, #8] htim3.Init.Period = 6875; 8000d9c: 4b18 ldr r3, [pc, #96] ; (8000e00 ) 8000d9e: f641 22db movw r2, #6875 ; 0x1adb 8000da2: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000da4: 4b16 ldr r3, [pc, #88] ; (8000e00 ) 8000da6: 2200 movs r2, #0 8000da8: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8000daa: 4b15 ldr r3, [pc, #84] ; (8000e00 ) 8000dac: 2280 movs r2, #128 ; 0x80 8000dae: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 8000db0: 4813 ldr r0, [pc, #76] ; (8000e00 ) 8000db2: f004 f893 bl 8004edc 8000db6: 4603 mov r3, r0 8000db8: 2b00 cmp r3, #0 8000dba: d001 beq.n 8000dc0 { Error_Handler(); 8000dbc: f000 f97c bl 80010b8 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000dc0: f44f 5380 mov.w r3, #4096 ; 0x1000 8000dc4: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 8000dc6: f107 0310 add.w r3, r7, #16 8000dca: 4619 mov r1, r3 8000dcc: 480c ldr r0, [pc, #48] ; (8000e00 ) 8000dce: f004 fa83 bl 80052d8 8000dd2: 4603 mov r3, r0 8000dd4: 2b00 cmp r3, #0 8000dd6: d001 beq.n 8000ddc { Error_Handler(); 8000dd8: f000 f96e bl 80010b8 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000ddc: 2300 movs r3, #0 8000dde: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000de0: 2300 movs r3, #0 8000de2: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8000de4: 1d3b adds r3, r7, #4 8000de6: 4619 mov r1, r3 8000de8: 4805 ldr r0, [pc, #20] ; (8000e00 ) 8000dea: f004 fcd9 bl 80057a0 8000dee: 4603 mov r3, r0 8000df0: 2b00 cmp r3, #0 8000df2: d001 beq.n 8000df8 { Error_Handler(); 8000df4: f000 f960 bl 80010b8 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8000df8: bf00 nop 8000dfa: 3720 adds r7, #32 8000dfc: 46bd mov sp, r7 8000dfe: bd80 pop {r7, pc} 8000e00: 2400043c .word 0x2400043c 8000e04: 40000400 .word 0x40000400 08000e08 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000e08: b580 push {r7, lr} 8000e0a: b08c sub sp, #48 ; 0x30 8000e0c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000e0e: f107 031c add.w r3, r7, #28 8000e12: 2200 movs r2, #0 8000e14: 601a str r2, [r3, #0] 8000e16: 605a str r2, [r3, #4] 8000e18: 609a str r2, [r3, #8] 8000e1a: 60da str r2, [r3, #12] 8000e1c: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8000e1e: 4b9f ldr r3, [pc, #636] ; (800109c ) 8000e20: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000e24: 4a9d ldr r2, [pc, #628] ; (800109c ) 8000e26: f043 0304 orr.w r3, r3, #4 8000e2a: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000e2e: 4b9b ldr r3, [pc, #620] ; (800109c ) 8000e30: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000e34: f003 0304 and.w r3, r3, #4 8000e38: 61bb str r3, [r7, #24] 8000e3a: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOH_CLK_ENABLE(); 8000e3c: 4b97 ldr r3, [pc, #604] ; (800109c ) 8000e3e: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000e42: 4a96 ldr r2, [pc, #600] ; (800109c ) 8000e44: f043 0380 orr.w r3, r3, #128 ; 0x80 8000e48: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000e4c: 4b93 ldr r3, [pc, #588] ; (800109c ) 8000e4e: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000e52: f003 0380 and.w r3, r3, #128 ; 0x80 8000e56: 617b str r3, [r7, #20] 8000e58: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000e5a: 4b90 ldr r3, [pc, #576] ; (800109c ) 8000e5c: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000e60: 4a8e ldr r2, [pc, #568] ; (800109c ) 8000e62: f043 0301 orr.w r3, r3, #1 8000e66: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000e6a: 4b8c ldr r3, [pc, #560] ; (800109c ) 8000e6c: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000e70: f003 0301 and.w r3, r3, #1 8000e74: 613b str r3, [r7, #16] 8000e76: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000e78: 4b88 ldr r3, [pc, #544] ; (800109c ) 8000e7a: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000e7e: 4a87 ldr r2, [pc, #540] ; (800109c ) 8000e80: f043 0302 orr.w r3, r3, #2 8000e84: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000e88: 4b84 ldr r3, [pc, #528] ; (800109c ) 8000e8a: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000e8e: f003 0302 and.w r3, r3, #2 8000e92: 60fb str r3, [r7, #12] 8000e94: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000e96: 4b81 ldr r3, [pc, #516] ; (800109c ) 8000e98: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000e9c: 4a7f ldr r2, [pc, #508] ; (800109c ) 8000e9e: f043 0308 orr.w r3, r3, #8 8000ea2: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000ea6: 4b7d ldr r3, [pc, #500] ; (800109c ) 8000ea8: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000eac: f003 0308 and.w r3, r3, #8 8000eb0: 60bb str r3, [r7, #8] 8000eb2: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000eb4: 4b79 ldr r3, [pc, #484] ; (800109c ) 8000eb6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000eba: 4a78 ldr r2, [pc, #480] ; (800109c ) 8000ebc: f043 0340 orr.w r3, r3, #64 ; 0x40 8000ec0: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000ec4: 4b75 ldr r3, [pc, #468] ; (800109c ) 8000ec6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000eca: f003 0340 and.w r3, r3, #64 ; 0x40 8000ece: 607b str r3, [r7, #4] 8000ed0: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOE_CLK_ENABLE(); 8000ed2: 4b72 ldr r3, [pc, #456] ; (800109c ) 8000ed4: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000ed8: 4a70 ldr r2, [pc, #448] ; (800109c ) 8000eda: f043 0310 orr.w r3, r3, #16 8000ede: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000ee2: 4b6e ldr r3, [pc, #440] ; (800109c ) 8000ee4: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000ee8: f003 0310 and.w r3, r3, #16 8000eec: 603b str r3, [r7, #0] 8000eee: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LED_GREEN_Pin|CC1200_RESET_Pin|LED_RED_Pin, GPIO_PIN_RESET); 8000ef0: 2200 movs r2, #0 8000ef2: f245 0101 movw r1, #20481 ; 0x5001 8000ef6: 486a ldr r0, [pc, #424] ; (80010a0 ) 8000ef8: f000 fe3a bl 8001b70 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(CC1200_TCXO_ENABLE_GPIO_Port, CC1200_TCXO_ENABLE_Pin, GPIO_PIN_SET); 8000efc: 2201 movs r2, #1 8000efe: f44f 4100 mov.w r1, #32768 ; 0x8000 8000f02: 4867 ldr r0, [pc, #412] ; (80010a0 ) 8000f04: f000 fe34 bl 8001b70 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USB_FS_PWR_EN_GPIO_Port, USB_FS_PWR_EN_Pin, GPIO_PIN_RESET); 8000f08: 2200 movs r2, #0 8000f0a: f44f 6180 mov.w r1, #1024 ; 0x400 8000f0e: 4865 ldr r0, [pc, #404] ; (80010a4 ) 8000f10: f000 fe2e bl 8001b70 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, GPIO_PIN_SET); 8000f14: 2201 movs r2, #1 8000f16: 2140 movs r1, #64 ; 0x40 8000f18: 4863 ldr r0, [pc, #396] ; (80010a8 ) 8000f1a: f000 fe29 bl 8001b70 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LED_YELLOW_GPIO_Port, LED_YELLOW_Pin, GPIO_PIN_RESET); 8000f1e: 2200 movs r2, #0 8000f20: 2102 movs r1, #2 8000f22: 4862 ldr r0, [pc, #392] ; (80010ac ) 8000f24: f000 fe24 bl 8001b70 /*Configure GPIO pin : B1_Pin */ GPIO_InitStruct.Pin = B1_Pin; 8000f28: f44f 5300 mov.w r3, #8192 ; 0x2000 8000f2c: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000f2e: 2300 movs r3, #0 8000f30: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f32: 2300 movs r3, #0 8000f34: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); 8000f36: f107 031c add.w r3, r7, #28 8000f3a: 4619 mov r1, r3 8000f3c: 485a ldr r0, [pc, #360] ; (80010a8 ) 8000f3e: f000 fc6f bl 8001820 /*Configure GPIO pins : PC1 PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; 8000f42: 2332 movs r3, #50 ; 0x32 8000f44: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000f46: 2302 movs r3, #2 8000f48: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f4a: 2300 movs r3, #0 8000f4c: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000f4e: 2303 movs r3, #3 8000f50: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000f52: 230b movs r3, #11 8000f54: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000f56: f107 031c add.w r3, r7, #28 8000f5a: 4619 mov r1, r3 8000f5c: 4852 ldr r0, [pc, #328] ; (80010a8 ) 8000f5e: f000 fc5f bl 8001820 /*Configure GPIO pins : PA1 PA2 PA7 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; 8000f62: 2386 movs r3, #134 ; 0x86 8000f64: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000f66: 2302 movs r3, #2 8000f68: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f6a: 2300 movs r3, #0 8000f6c: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000f6e: 2303 movs r3, #3 8000f70: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000f72: 230b movs r3, #11 8000f74: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000f76: f107 031c add.w r3, r7, #28 8000f7a: 4619 mov r1, r3 8000f7c: 484c ldr r0, [pc, #304] ; (80010b0 ) 8000f7e: f000 fc4f bl 8001820 /*Configure GPIO pins : LED_GREEN_Pin LED_RED_Pin */ GPIO_InitStruct.Pin = LED_GREEN_Pin|LED_RED_Pin; 8000f82: f244 0301 movw r3, #16385 ; 0x4001 8000f86: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000f88: 2301 movs r3, #1 8000f8a: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f8c: 2300 movs r3, #0 8000f8e: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000f90: 2300 movs r3, #0 8000f92: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000f94: f107 031c add.w r3, r7, #28 8000f98: 4619 mov r1, r3 8000f9a: 4841 ldr r0, [pc, #260] ; (80010a0 ) 8000f9c: f000 fc40 bl 8001820 /*Configure GPIO pins : CC1200_RESET_Pin CC1200_TCXO_ENABLE_Pin */ GPIO_InitStruct.Pin = CC1200_RESET_Pin|CC1200_TCXO_ENABLE_Pin; 8000fa0: f44f 4310 mov.w r3, #36864 ; 0x9000 8000fa4: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000fa6: 2301 movs r3, #1 8000fa8: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000faa: 2300 movs r3, #0 8000fac: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000fae: 2303 movs r3, #3 8000fb0: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000fb2: f107 031c add.w r3, r7, #28 8000fb6: 4619 mov r1, r3 8000fb8: 4839 ldr r0, [pc, #228] ; (80010a0 ) 8000fba: f000 fc31 bl 8001820 /*Configure GPIO pin : PB13 */ GPIO_InitStruct.Pin = GPIO_PIN_13; 8000fbe: f44f 5300 mov.w r3, #8192 ; 0x2000 8000fc2: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000fc4: 2302 movs r3, #2 8000fc6: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000fc8: 2300 movs r3, #0 8000fca: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000fcc: 2303 movs r3, #3 8000fce: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000fd0: 230b movs r3, #11 8000fd2: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000fd4: f107 031c add.w r3, r7, #28 8000fd8: 4619 mov r1, r3 8000fda: 4831 ldr r0, [pc, #196] ; (80010a0 ) 8000fdc: f000 fc20 bl 8001820 /*Configure GPIO pins : STLK_VCP_RX_Pin STLK_VCP_TX_Pin */ GPIO_InitStruct.Pin = STLK_VCP_RX_Pin|STLK_VCP_TX_Pin; 8000fe0: f44f 7340 mov.w r3, #768 ; 0x300 8000fe4: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000fe6: 2302 movs r3, #2 8000fe8: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000fea: 2300 movs r3, #0 8000fec: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000fee: 2300 movs r3, #0 8000ff0: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF7_USART3; 8000ff2: 2307 movs r3, #7 8000ff4: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000ff6: f107 031c add.w r3, r7, #28 8000ffa: 4619 mov r1, r3 8000ffc: 4829 ldr r0, [pc, #164] ; (80010a4 ) 8000ffe: f000 fc0f bl 8001820 /*Configure GPIO pin : USB_FS_PWR_EN_Pin */ GPIO_InitStruct.Pin = USB_FS_PWR_EN_Pin; 8001002: f44f 6380 mov.w r3, #1024 ; 0x400 8001006: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001008: 2301 movs r3, #1 800100a: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800100c: 2300 movs r3, #0 800100e: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001010: 2300 movs r3, #0 8001012: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(USB_FS_PWR_EN_GPIO_Port, &GPIO_InitStruct); 8001014: f107 031c add.w r3, r7, #28 8001018: 4619 mov r1, r3 800101a: 4822 ldr r0, [pc, #136] ; (80010a4 ) 800101c: f000 fc00 bl 8001820 /*Configure GPIO pin : USB_FS_OVCR_Pin */ GPIO_InitStruct.Pin = USB_FS_OVCR_Pin; 8001020: 2380 movs r3, #128 ; 0x80 8001022: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8001024: f44f 1388 mov.w r3, #1114112 ; 0x110000 8001028: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800102a: 2300 movs r3, #0 800102c: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(USB_FS_OVCR_GPIO_Port, &GPIO_InitStruct); 800102e: f107 031c add.w r3, r7, #28 8001032: 4619 mov r1, r3 8001034: 481f ldr r0, [pc, #124] ; (80010b4 ) 8001036: f000 fbf3 bl 8001820 /*Configure GPIO pin : CC1200_CS_Pin */ GPIO_InitStruct.Pin = CC1200_CS_Pin; 800103a: 2340 movs r3, #64 ; 0x40 800103c: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800103e: 2301 movs r3, #1 8001040: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001042: 2300 movs r3, #0 8001044: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001046: 2303 movs r3, #3 8001048: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(CC1200_CS_GPIO_Port, &GPIO_InitStruct); 800104a: f107 031c add.w r3, r7, #28 800104e: 4619 mov r1, r3 8001050: 4815 ldr r0, [pc, #84] ; (80010a8 ) 8001052: f000 fbe5 bl 8001820 /*Configure GPIO pins : PG11 PG13 */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13; 8001056: f44f 5320 mov.w r3, #10240 ; 0x2800 800105a: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800105c: 2302 movs r3, #2 800105e: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001060: 2300 movs r3, #0 8001062: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001064: 2303 movs r3, #3 8001066: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8001068: 230b movs r3, #11 800106a: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 800106c: f107 031c add.w r3, r7, #28 8001070: 4619 mov r1, r3 8001072: 4810 ldr r0, [pc, #64] ; (80010b4 ) 8001074: f000 fbd4 bl 8001820 /*Configure GPIO pin : LED_YELLOW_Pin */ GPIO_InitStruct.Pin = LED_YELLOW_Pin; 8001078: 2302 movs r3, #2 800107a: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800107c: 2301 movs r3, #1 800107e: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001080: 2300 movs r3, #0 8001082: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001084: 2300 movs r3, #0 8001086: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(LED_YELLOW_GPIO_Port, &GPIO_InitStruct); 8001088: f107 031c add.w r3, r7, #28 800108c: 4619 mov r1, r3 800108e: 4807 ldr r0, [pc, #28] ; (80010ac ) 8001090: f000 fbc6 bl 8001820 } 8001094: bf00 nop 8001096: 3730 adds r7, #48 ; 0x30 8001098: 46bd mov sp, r7 800109a: bd80 pop {r7, pc} 800109c: 58024400 .word 0x58024400 80010a0: 58020400 .word 0x58020400 80010a4: 58020c00 .word 0x58020c00 80010a8: 58020800 .word 0x58020800 80010ac: 58021000 .word 0x58021000 80010b0: 58020000 .word 0x58020000 80010b4: 58021800 .word 0x58021800 080010b8 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80010b8: b480 push {r7} 80010ba: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 80010bc: b672 cpsid i } 80010be: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80010c0: e7fe b.n 80010c0 ... 080010c4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80010c4: b480 push {r7} 80010c6: b083 sub sp, #12 80010c8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80010ca: 4b0a ldr r3, [pc, #40] ; (80010f4 ) 80010cc: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 80010d0: 4a08 ldr r2, [pc, #32] ; (80010f4 ) 80010d2: f043 0302 orr.w r3, r3, #2 80010d6: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 80010da: 4b06 ldr r3, [pc, #24] ; (80010f4 ) 80010dc: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 80010e0: f003 0302 and.w r3, r3, #2 80010e4: 607b str r3, [r7, #4] 80010e6: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80010e8: bf00 nop 80010ea: 370c adds r7, #12 80010ec: 46bd mov sp, r7 80010ee: f85d 7b04 ldr.w r7, [sp], #4 80010f2: 4770 bx lr 80010f4: 58024400 .word 0x58024400 080010f8 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 80010f8: b580 push {r7, lr} 80010fa: b084 sub sp, #16 80010fc: af00 add r7, sp, #0 80010fe: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM3) 8001100: 687b ldr r3, [r7, #4] 8001102: 681b ldr r3, [r3, #0] 8001104: 4a0e ldr r2, [pc, #56] ; (8001140 ) 8001106: 4293 cmp r3, r2 8001108: d116 bne.n 8001138 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800110a: 4b0e ldr r3, [pc, #56] ; (8001144 ) 800110c: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001110: 4a0c ldr r2, [pc, #48] ; (8001144 ) 8001112: f043 0302 orr.w r3, r3, #2 8001116: f8c2 30e8 str.w r3, [r2, #232] ; 0xe8 800111a: 4b0a ldr r3, [pc, #40] ; (8001144 ) 800111c: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 8001120: f003 0302 and.w r3, r3, #2 8001124: 60fb str r3, [r7, #12] 8001126: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 8001128: 2200 movs r2, #0 800112a: 2100 movs r1, #0 800112c: 201d movs r0, #29 800112e: f000 fb42 bl 80017b6 HAL_NVIC_EnableIRQ(TIM3_IRQn); 8001132: 201d movs r0, #29 8001134: f000 fb59 bl 80017ea /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8001138: bf00 nop 800113a: 3710 adds r7, #16 800113c: 46bd mov sp, r7 800113e: bd80 pop {r7, pc} 8001140: 40000400 .word 0x40000400 8001144: 58024400 .word 0x58024400 08001148 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001148: b480 push {r7} 800114a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800114c: e7fe b.n 800114c 0800114e : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800114e: b480 push {r7} 8001150: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8001152: e7fe b.n 8001152 08001154 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001154: b480 push {r7} 8001156: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001158: e7fe b.n 8001158 0800115a : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 800115a: b480 push {r7} 800115c: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800115e: e7fe b.n 800115e 08001160 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001160: b480 push {r7} 8001162: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001164: e7fe b.n 8001164 08001166 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8001166: b480 push {r7} 8001168: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800116a: bf00 nop 800116c: 46bd mov sp, r7 800116e: f85d 7b04 ldr.w r7, [sp], #4 8001172: 4770 bx lr 08001174 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8001174: b480 push {r7} 8001176: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8001178: bf00 nop 800117a: 46bd mov sp, r7 800117c: f85d 7b04 ldr.w r7, [sp], #4 8001180: 4770 bx lr 08001182 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001182: b480 push {r7} 8001184: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8001186: bf00 nop 8001188: 46bd mov sp, r7 800118a: f85d 7b04 ldr.w r7, [sp], #4 800118e: 4770 bx lr 08001190 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8001190: b580 push {r7, lr} 8001192: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8001194: f000 f9f0 bl 8001578 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8001198: bf00 nop 800119a: bd80 pop {r7, pc} 0800119c : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800119c: b580 push {r7, lr} 800119e: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 80011a0: 4802 ldr r0, [pc, #8] ; (80011ac ) 80011a2: f003 ff79 bl 8005098 /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 80011a6: bf00 nop 80011a8: bd80 pop {r7, pc} 80011aa: bf00 nop 80011ac: 2400043c .word 0x2400043c 080011b0 : /** * @brief This function handles USB On The Go HS global interrupt. */ void OTG_HS_IRQHandler(void) { 80011b0: b580 push {r7, lr} 80011b2: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_HS_IRQn 0 */ /* USER CODE END OTG_HS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_HS); 80011b4: 4802 ldr r0, [pc, #8] ; (80011c0 ) 80011b6: f000 fe65 bl 8001e84 /* USER CODE BEGIN OTG_HS_IRQn 1 */ /* USER CODE END OTG_HS_IRQn 1 */ } 80011ba: bf00 nop 80011bc: bd80 pop {r7, pc} 80011be: bf00 nop 80011c0: 2400195c .word 0x2400195c 080011c4 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 80011c4: b480 push {r7} 80011c6: af00 add r7, sp, #0 return 1; 80011c8: 2301 movs r3, #1 } 80011ca: 4618 mov r0, r3 80011cc: 46bd mov sp, r7 80011ce: f85d 7b04 ldr.w r7, [sp], #4 80011d2: 4770 bx lr 080011d4 <_kill>: int _kill(int pid, int sig) { 80011d4: b580 push {r7, lr} 80011d6: b082 sub sp, #8 80011d8: af00 add r7, sp, #0 80011da: 6078 str r0, [r7, #4] 80011dc: 6039 str r1, [r7, #0] errno = EINVAL; 80011de: f008 fb3f bl 8009860 <__errno> 80011e2: 4603 mov r3, r0 80011e4: 2216 movs r2, #22 80011e6: 601a str r2, [r3, #0] return -1; 80011e8: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 80011ec: 4618 mov r0, r3 80011ee: 3708 adds r7, #8 80011f0: 46bd mov sp, r7 80011f2: bd80 pop {r7, pc} 080011f4 <_exit>: void _exit (int status) { 80011f4: b580 push {r7, lr} 80011f6: b082 sub sp, #8 80011f8: af00 add r7, sp, #0 80011fa: 6078 str r0, [r7, #4] _kill(status, -1); 80011fc: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001200: 6878 ldr r0, [r7, #4] 8001202: f7ff ffe7 bl 80011d4 <_kill> while (1) {} /* Make sure we hang here */ 8001206: e7fe b.n 8001206 <_exit+0x12> 08001208 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8001208: b580 push {r7, lr} 800120a: b086 sub sp, #24 800120c: af00 add r7, sp, #0 800120e: 60f8 str r0, [r7, #12] 8001210: 60b9 str r1, [r7, #8] 8001212: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8001214: 2300 movs r3, #0 8001216: 617b str r3, [r7, #20] 8001218: e00a b.n 8001230 <_read+0x28> { *ptr++ = __io_getchar(); 800121a: f3af 8000 nop.w 800121e: 4601 mov r1, r0 8001220: 68bb ldr r3, [r7, #8] 8001222: 1c5a adds r2, r3, #1 8001224: 60ba str r2, [r7, #8] 8001226: b2ca uxtb r2, r1 8001228: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800122a: 697b ldr r3, [r7, #20] 800122c: 3301 adds r3, #1 800122e: 617b str r3, [r7, #20] 8001230: 697a ldr r2, [r7, #20] 8001232: 687b ldr r3, [r7, #4] 8001234: 429a cmp r2, r3 8001236: dbf0 blt.n 800121a <_read+0x12> } return len; 8001238: 687b ldr r3, [r7, #4] } 800123a: 4618 mov r0, r3 800123c: 3718 adds r7, #24 800123e: 46bd mov sp, r7 8001240: bd80 pop {r7, pc} 08001242 <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 8001242: b580 push {r7, lr} 8001244: b086 sub sp, #24 8001246: af00 add r7, sp, #0 8001248: 60f8 str r0, [r7, #12] 800124a: 60b9 str r1, [r7, #8] 800124c: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800124e: 2300 movs r3, #0 8001250: 617b str r3, [r7, #20] 8001252: e009 b.n 8001268 <_write+0x26> { __io_putchar(*ptr++); 8001254: 68bb ldr r3, [r7, #8] 8001256: 1c5a adds r2, r3, #1 8001258: 60ba str r2, [r7, #8] 800125a: 781b ldrb r3, [r3, #0] 800125c: 4618 mov r0, r3 800125e: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) 8001262: 697b ldr r3, [r7, #20] 8001264: 3301 adds r3, #1 8001266: 617b str r3, [r7, #20] 8001268: 697a ldr r2, [r7, #20] 800126a: 687b ldr r3, [r7, #4] 800126c: 429a cmp r2, r3 800126e: dbf1 blt.n 8001254 <_write+0x12> } return len; 8001270: 687b ldr r3, [r7, #4] } 8001272: 4618 mov r0, r3 8001274: 3718 adds r7, #24 8001276: 46bd mov sp, r7 8001278: bd80 pop {r7, pc} 0800127a <_close>: int _close(int file) { 800127a: b480 push {r7} 800127c: b083 sub sp, #12 800127e: af00 add r7, sp, #0 8001280: 6078 str r0, [r7, #4] return -1; 8001282: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8001286: 4618 mov r0, r3 8001288: 370c adds r7, #12 800128a: 46bd mov sp, r7 800128c: f85d 7b04 ldr.w r7, [sp], #4 8001290: 4770 bx lr 08001292 <_fstat>: int _fstat(int file, struct stat *st) { 8001292: b480 push {r7} 8001294: b083 sub sp, #12 8001296: af00 add r7, sp, #0 8001298: 6078 str r0, [r7, #4] 800129a: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 800129c: 683b ldr r3, [r7, #0] 800129e: f44f 5200 mov.w r2, #8192 ; 0x2000 80012a2: 605a str r2, [r3, #4] return 0; 80012a4: 2300 movs r3, #0 } 80012a6: 4618 mov r0, r3 80012a8: 370c adds r7, #12 80012aa: 46bd mov sp, r7 80012ac: f85d 7b04 ldr.w r7, [sp], #4 80012b0: 4770 bx lr 080012b2 <_isatty>: int _isatty(int file) { 80012b2: b480 push {r7} 80012b4: b083 sub sp, #12 80012b6: af00 add r7, sp, #0 80012b8: 6078 str r0, [r7, #4] return 1; 80012ba: 2301 movs r3, #1 } 80012bc: 4618 mov r0, r3 80012be: 370c adds r7, #12 80012c0: 46bd mov sp, r7 80012c2: f85d 7b04 ldr.w r7, [sp], #4 80012c6: 4770 bx lr 080012c8 <_lseek>: int _lseek(int file, int ptr, int dir) { 80012c8: b480 push {r7} 80012ca: b085 sub sp, #20 80012cc: af00 add r7, sp, #0 80012ce: 60f8 str r0, [r7, #12] 80012d0: 60b9 str r1, [r7, #8] 80012d2: 607a str r2, [r7, #4] return 0; 80012d4: 2300 movs r3, #0 } 80012d6: 4618 mov r0, r3 80012d8: 3714 adds r7, #20 80012da: 46bd mov sp, r7 80012dc: f85d 7b04 ldr.w r7, [sp], #4 80012e0: 4770 bx lr ... 080012e4 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 80012e4: b580 push {r7, lr} 80012e6: b086 sub sp, #24 80012e8: af00 add r7, sp, #0 80012ea: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 80012ec: 4a14 ldr r2, [pc, #80] ; (8001340 <_sbrk+0x5c>) 80012ee: 4b15 ldr r3, [pc, #84] ; (8001344 <_sbrk+0x60>) 80012f0: 1ad3 subs r3, r2, r3 80012f2: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 80012f4: 697b ldr r3, [r7, #20] 80012f6: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 80012f8: 4b13 ldr r3, [pc, #76] ; (8001348 <_sbrk+0x64>) 80012fa: 681b ldr r3, [r3, #0] 80012fc: 2b00 cmp r3, #0 80012fe: d102 bne.n 8001306 <_sbrk+0x22> { __sbrk_heap_end = &_end; 8001300: 4b11 ldr r3, [pc, #68] ; (8001348 <_sbrk+0x64>) 8001302: 4a12 ldr r2, [pc, #72] ; (800134c <_sbrk+0x68>) 8001304: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8001306: 4b10 ldr r3, [pc, #64] ; (8001348 <_sbrk+0x64>) 8001308: 681a ldr r2, [r3, #0] 800130a: 687b ldr r3, [r7, #4] 800130c: 4413 add r3, r2 800130e: 693a ldr r2, [r7, #16] 8001310: 429a cmp r2, r3 8001312: d207 bcs.n 8001324 <_sbrk+0x40> { errno = ENOMEM; 8001314: f008 faa4 bl 8009860 <__errno> 8001318: 4603 mov r3, r0 800131a: 220c movs r2, #12 800131c: 601a str r2, [r3, #0] return (void *)-1; 800131e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 8001322: e009 b.n 8001338 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8001324: 4b08 ldr r3, [pc, #32] ; (8001348 <_sbrk+0x64>) 8001326: 681b ldr r3, [r3, #0] 8001328: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800132a: 4b07 ldr r3, [pc, #28] ; (8001348 <_sbrk+0x64>) 800132c: 681a ldr r2, [r3, #0] 800132e: 687b ldr r3, [r7, #4] 8001330: 4413 add r3, r2 8001332: 4a05 ldr r2, [pc, #20] ; (8001348 <_sbrk+0x64>) 8001334: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8001336: 68fb ldr r3, [r7, #12] } 8001338: 4618 mov r0, r3 800133a: 3718 adds r7, #24 800133c: 46bd mov sp, r7 800133e: bd80 pop {r7, pc} 8001340: 24050000 .word 0x24050000 8001344: 00000400 .word 0x00000400 8001348: 2400020c .word 0x2400020c 800134c: 24001d78 .word 0x24001d78 08001350 : * configuration. * @param None * @retval None */ void SystemInit (void) { 8001350: b480 push {r7} 8001352: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8001354: 4b32 ldr r3, [pc, #200] ; (8001420 ) 8001356: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 800135a: 4a31 ldr r2, [pc, #196] ; (8001420 ) 800135c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8001360: f8c2 3088 str.w r3, [r2, #136] ; 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8001364: 4b2f ldr r3, [pc, #188] ; (8001424 ) 8001366: 681b ldr r3, [r3, #0] 8001368: f003 030f and.w r3, r3, #15 800136c: 2b06 cmp r3, #6 800136e: d807 bhi.n 8001380 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8001370: 4b2c ldr r3, [pc, #176] ; (8001424 ) 8001372: 681b ldr r3, [r3, #0] 8001374: f023 030f bic.w r3, r3, #15 8001378: 4a2a ldr r2, [pc, #168] ; (8001424 ) 800137a: f043 0307 orr.w r3, r3, #7 800137e: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 8001380: 4b29 ldr r3, [pc, #164] ; (8001428 ) 8001382: 681b ldr r3, [r3, #0] 8001384: 4a28 ldr r2, [pc, #160] ; (8001428 ) 8001386: f043 0301 orr.w r3, r3, #1 800138a: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 800138c: 4b26 ldr r3, [pc, #152] ; (8001428 ) 800138e: 2200 movs r2, #0 8001390: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 8001392: 4b25 ldr r3, [pc, #148] ; (8001428 ) 8001394: 681a ldr r2, [r3, #0] 8001396: 4924 ldr r1, [pc, #144] ; (8001428 ) 8001398: 4b24 ldr r3, [pc, #144] ; (800142c ) 800139a: 4013 ands r3, r2 800139c: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 800139e: 4b21 ldr r3, [pc, #132] ; (8001424 ) 80013a0: 681b ldr r3, [r3, #0] 80013a2: f003 0308 and.w r3, r3, #8 80013a6: 2b00 cmp r3, #0 80013a8: d007 beq.n 80013ba { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 80013aa: 4b1e ldr r3, [pc, #120] ; (8001424 ) 80013ac: 681b ldr r3, [r3, #0] 80013ae: f023 030f bic.w r3, r3, #15 80013b2: 4a1c ldr r2, [pc, #112] ; (8001424 ) 80013b4: f043 0307 orr.w r3, r3, #7 80013b8: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 80013ba: 4b1b ldr r3, [pc, #108] ; (8001428 ) 80013bc: 2200 movs r2, #0 80013be: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 80013c0: 4b19 ldr r3, [pc, #100] ; (8001428 ) 80013c2: 2200 movs r2, #0 80013c4: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 80013c6: 4b18 ldr r3, [pc, #96] ; (8001428 ) 80013c8: 2200 movs r2, #0 80013ca: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 80013cc: 4b16 ldr r3, [pc, #88] ; (8001428 ) 80013ce: 4a18 ldr r2, [pc, #96] ; (8001430 ) 80013d0: 629a str r2, [r3, #40] ; 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 80013d2: 4b15 ldr r3, [pc, #84] ; (8001428 ) 80013d4: 4a17 ldr r2, [pc, #92] ; (8001434 ) 80013d6: 62da str r2, [r3, #44] ; 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 80013d8: 4b13 ldr r3, [pc, #76] ; (8001428 ) 80013da: 4a17 ldr r2, [pc, #92] ; (8001438 ) 80013dc: 631a str r2, [r3, #48] ; 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 80013de: 4b12 ldr r3, [pc, #72] ; (8001428 ) 80013e0: 2200 movs r2, #0 80013e2: 635a str r2, [r3, #52] ; 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 80013e4: 4b10 ldr r3, [pc, #64] ; (8001428 ) 80013e6: 4a14 ldr r2, [pc, #80] ; (8001438 ) 80013e8: 639a str r2, [r3, #56] ; 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 80013ea: 4b0f ldr r3, [pc, #60] ; (8001428 ) 80013ec: 2200 movs r2, #0 80013ee: 63da str r2, [r3, #60] ; 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 80013f0: 4b0d ldr r3, [pc, #52] ; (8001428 ) 80013f2: 4a11 ldr r2, [pc, #68] ; (8001438 ) 80013f4: 641a str r2, [r3, #64] ; 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 80013f6: 4b0c ldr r3, [pc, #48] ; (8001428 ) 80013f8: 2200 movs r2, #0 80013fa: 645a str r2, [r3, #68] ; 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 80013fc: 4b0a ldr r3, [pc, #40] ; (8001428 ) 80013fe: 681b ldr r3, [r3, #0] 8001400: 4a09 ldr r2, [pc, #36] ; (8001428 ) 8001402: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8001406: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8001408: 4b07 ldr r3, [pc, #28] ; (8001428 ) 800140a: 2200 movs r2, #0 800140c: 661a str r2, [r3, #96] ; 0x60 /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 800140e: 4b0b ldr r3, [pc, #44] ; (800143c ) 8001410: f243 02d2 movw r2, #12498 ; 0x30d2 8001414: 601a str r2, [r3, #0] SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 8001416: bf00 nop 8001418: 46bd mov sp, r7 800141a: f85d 7b04 ldr.w r7, [sp], #4 800141e: 4770 bx lr 8001420: e000ed00 .word 0xe000ed00 8001424: 52002000 .word 0x52002000 8001428: 58024400 .word 0x58024400 800142c: eaf6ed7f .word 0xeaf6ed7f 8001430: 02020200 .word 0x02020200 8001434: 01ff0000 .word 0x01ff0000 8001438: 01010280 .word 0x01010280 800143c: 52004000 .word 0x52004000 08001440 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001440: f8df d034 ldr.w sp, [pc, #52] ; 8001478 /* Call the clock system initialization function.*/ bl SystemInit 8001444: f7ff ff84 bl 8001350 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001448: 480c ldr r0, [pc, #48] ; (800147c ) ldr r1, =_edata 800144a: 490d ldr r1, [pc, #52] ; (8001480 ) ldr r2, =_sidata 800144c: 4a0d ldr r2, [pc, #52] ; (8001484 ) movs r3, #0 800144e: 2300 movs r3, #0 b LoopCopyDataInit 8001450: e002 b.n 8001458 08001452 : CopyDataInit: ldr r4, [r2, r3] 8001452: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001454: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001456: 3304 adds r3, #4 08001458 : LoopCopyDataInit: adds r4, r0, r3 8001458: 18c4 adds r4, r0, r3 cmp r4, r1 800145a: 428c cmp r4, r1 bcc CopyDataInit 800145c: d3f9 bcc.n 8001452 /* Zero fill the bss segment. */ ldr r2, =_sbss 800145e: 4a0a ldr r2, [pc, #40] ; (8001488 ) ldr r4, =_ebss 8001460: 4c0a ldr r4, [pc, #40] ; (800148c ) movs r3, #0 8001462: 2300 movs r3, #0 b LoopFillZerobss 8001464: e001 b.n 800146a 08001466 : FillZerobss: str r3, [r2] 8001466: 6013 str r3, [r2, #0] adds r2, r2, #4 8001468: 3204 adds r2, #4 0800146a : LoopFillZerobss: cmp r2, r4 800146a: 42a2 cmp r2, r4 bcc FillZerobss 800146c: d3fb bcc.n 8001466 /* Call static constructors */ bl __libc_init_array 800146e: f008 fa0f bl 8009890 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001472: f7ff fad3 bl 8000a1c
bx lr 8001476: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001478: 24050000 .word 0x24050000 ldr r0, =_sdata 800147c: 24000000 .word 0x24000000 ldr r1, =_edata 8001480: 240001e8 .word 0x240001e8 ldr r2, =_sidata 8001484: 0800aa44 .word 0x0800aa44 ldr r2, =_sbss 8001488: 240001e8 .word 0x240001e8 ldr r4, =_ebss 800148c: 24001d74 .word 0x24001d74 08001490 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001490: e7fe b.n 8001490 ... 08001494 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001494: b580 push {r7, lr} 8001496: b082 sub sp, #8 8001498: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800149a: 2003 movs r0, #3 800149c: f000 f980 bl 80017a0 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 80014a0: f002 fb14 bl 8003acc 80014a4: 4602 mov r2, r0 80014a6: 4b15 ldr r3, [pc, #84] ; (80014fc ) 80014a8: 699b ldr r3, [r3, #24] 80014aa: 0a1b lsrs r3, r3, #8 80014ac: f003 030f and.w r3, r3, #15 80014b0: 4913 ldr r1, [pc, #76] ; (8001500 ) 80014b2: 5ccb ldrb r3, [r1, r3] 80014b4: f003 031f and.w r3, r3, #31 80014b8: fa22 f303 lsr.w r3, r2, r3 80014bc: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 80014be: 4b0f ldr r3, [pc, #60] ; (80014fc ) 80014c0: 699b ldr r3, [r3, #24] 80014c2: f003 030f and.w r3, r3, #15 80014c6: 4a0e ldr r2, [pc, #56] ; (8001500 ) 80014c8: 5cd3 ldrb r3, [r2, r3] 80014ca: f003 031f and.w r3, r3, #31 80014ce: 687a ldr r2, [r7, #4] 80014d0: fa22 f303 lsr.w r3, r2, r3 80014d4: 4a0b ldr r2, [pc, #44] ; (8001504 ) 80014d6: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 80014d8: 4a0b ldr r2, [pc, #44] ; (8001508 ) 80014da: 687b ldr r3, [r7, #4] 80014dc: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 80014de: 2000 movs r0, #0 80014e0: f000 f814 bl 800150c 80014e4: 4603 mov r3, r0 80014e6: 2b00 cmp r3, #0 80014e8: d001 beq.n 80014ee { return HAL_ERROR; 80014ea: 2301 movs r3, #1 80014ec: e002 b.n 80014f4 } /* Init the low level hardware */ HAL_MspInit(); 80014ee: f7ff fde9 bl 80010c4 /* Return function status */ return HAL_OK; 80014f2: 2300 movs r3, #0 } 80014f4: 4618 mov r0, r3 80014f6: 3708 adds r7, #8 80014f8: 46bd mov sp, r7 80014fa: bd80 pop {r7, pc} 80014fc: 58024400 .word 0x58024400 8001500: 0800a958 .word 0x0800a958 8001504: 24000004 .word 0x24000004 8001508: 24000000 .word 0x24000000 0800150c : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800150c: b580 push {r7, lr} 800150e: b082 sub sp, #8 8001510: af00 add r7, sp, #0 8001512: 6078 str r0, [r7, #4] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if((uint32_t)uwTickFreq == 0UL) 8001514: 4b15 ldr r3, [pc, #84] ; (800156c ) 8001516: 781b ldrb r3, [r3, #0] 8001518: 2b00 cmp r3, #0 800151a: d101 bne.n 8001520 { return HAL_ERROR; 800151c: 2301 movs r3, #1 800151e: e021 b.n 8001564 } /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) 8001520: 4b13 ldr r3, [pc, #76] ; (8001570 ) 8001522: 681a ldr r2, [r3, #0] 8001524: 4b11 ldr r3, [pc, #68] ; (800156c ) 8001526: 781b ldrb r3, [r3, #0] 8001528: 4619 mov r1, r3 800152a: f44f 737a mov.w r3, #1000 ; 0x3e8 800152e: fbb3 f3f1 udiv r3, r3, r1 8001532: fbb2 f3f3 udiv r3, r2, r3 8001536: 4618 mov r0, r3 8001538: f000 f965 bl 8001806 800153c: 4603 mov r3, r0 800153e: 2b00 cmp r3, #0 8001540: d001 beq.n 8001546 { return HAL_ERROR; 8001542: 2301 movs r3, #1 8001544: e00e b.n 8001564 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001546: 687b ldr r3, [r7, #4] 8001548: 2b0f cmp r3, #15 800154a: d80a bhi.n 8001562 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800154c: 2200 movs r2, #0 800154e: 6879 ldr r1, [r7, #4] 8001550: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001554: f000 f92f bl 80017b6 uwTickPrio = TickPriority; 8001558: 4a06 ldr r2, [pc, #24] ; (8001574 ) 800155a: 687b ldr r3, [r7, #4] 800155c: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800155e: 2300 movs r3, #0 8001560: e000 b.n 8001564 return HAL_ERROR; 8001562: 2301 movs r3, #1 } 8001564: 4618 mov r0, r3 8001566: 3708 adds r7, #8 8001568: 46bd mov sp, r7 800156a: bd80 pop {r7, pc} 800156c: 2400000c .word 0x2400000c 8001570: 24000000 .word 0x24000000 8001574: 24000008 .word 0x24000008 08001578 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001578: b480 push {r7} 800157a: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 800157c: 4b06 ldr r3, [pc, #24] ; (8001598 ) 800157e: 781b ldrb r3, [r3, #0] 8001580: 461a mov r2, r3 8001582: 4b06 ldr r3, [pc, #24] ; (800159c ) 8001584: 681b ldr r3, [r3, #0] 8001586: 4413 add r3, r2 8001588: 4a04 ldr r2, [pc, #16] ; (800159c ) 800158a: 6013 str r3, [r2, #0] } 800158c: bf00 nop 800158e: 46bd mov sp, r7 8001590: f85d 7b04 ldr.w r7, [sp], #4 8001594: 4770 bx lr 8001596: bf00 nop 8001598: 2400000c .word 0x2400000c 800159c: 24000488 .word 0x24000488 080015a0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80015a0: b480 push {r7} 80015a2: af00 add r7, sp, #0 return uwTick; 80015a4: 4b03 ldr r3, [pc, #12] ; (80015b4 ) 80015a6: 681b ldr r3, [r3, #0] } 80015a8: 4618 mov r0, r3 80015aa: 46bd mov sp, r7 80015ac: f85d 7b04 ldr.w r7, [sp], #4 80015b0: 4770 bx lr 80015b2: bf00 nop 80015b4: 24000488 .word 0x24000488 080015b8 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80015b8: b580 push {r7, lr} 80015ba: b084 sub sp, #16 80015bc: af00 add r7, sp, #0 80015be: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80015c0: f7ff ffee bl 80015a0 80015c4: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80015c6: 687b ldr r3, [r7, #4] 80015c8: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80015ca: 68fb ldr r3, [r7, #12] 80015cc: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80015d0: d005 beq.n 80015de { wait += (uint32_t)(uwTickFreq); 80015d2: 4b0a ldr r3, [pc, #40] ; (80015fc ) 80015d4: 781b ldrb r3, [r3, #0] 80015d6: 461a mov r2, r3 80015d8: 68fb ldr r3, [r7, #12] 80015da: 4413 add r3, r2 80015dc: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80015de: bf00 nop 80015e0: f7ff ffde bl 80015a0 80015e4: 4602 mov r2, r0 80015e6: 68bb ldr r3, [r7, #8] 80015e8: 1ad3 subs r3, r2, r3 80015ea: 68fa ldr r2, [r7, #12] 80015ec: 429a cmp r2, r3 80015ee: d8f7 bhi.n 80015e0 { } } 80015f0: bf00 nop 80015f2: bf00 nop 80015f4: 3710 adds r7, #16 80015f6: 46bd mov sp, r7 80015f8: bd80 pop {r7, pc} 80015fa: bf00 nop 80015fc: 2400000c .word 0x2400000c 08001600 <__NVIC_SetPriorityGrouping>: { 8001600: b480 push {r7} 8001602: b085 sub sp, #20 8001604: af00 add r7, sp, #0 8001606: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001608: 687b ldr r3, [r7, #4] 800160a: f003 0307 and.w r3, r3, #7 800160e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001610: 4b0b ldr r3, [pc, #44] ; (8001640 <__NVIC_SetPriorityGrouping+0x40>) 8001612: 68db ldr r3, [r3, #12] 8001614: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001616: 68ba ldr r2, [r7, #8] 8001618: f64f 03ff movw r3, #63743 ; 0xf8ff 800161c: 4013 ands r3, r2 800161e: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001620: 68fb ldr r3, [r7, #12] 8001622: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001624: 68bb ldr r3, [r7, #8] 8001626: 431a orrs r2, r3 reg_value = (reg_value | 8001628: 4b06 ldr r3, [pc, #24] ; (8001644 <__NVIC_SetPriorityGrouping+0x44>) 800162a: 4313 orrs r3, r2 800162c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800162e: 4a04 ldr r2, [pc, #16] ; (8001640 <__NVIC_SetPriorityGrouping+0x40>) 8001630: 68bb ldr r3, [r7, #8] 8001632: 60d3 str r3, [r2, #12] } 8001634: bf00 nop 8001636: 3714 adds r7, #20 8001638: 46bd mov sp, r7 800163a: f85d 7b04 ldr.w r7, [sp], #4 800163e: 4770 bx lr 8001640: e000ed00 .word 0xe000ed00 8001644: 05fa0000 .word 0x05fa0000 08001648 <__NVIC_GetPriorityGrouping>: { 8001648: b480 push {r7} 800164a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800164c: 4b04 ldr r3, [pc, #16] ; (8001660 <__NVIC_GetPriorityGrouping+0x18>) 800164e: 68db ldr r3, [r3, #12] 8001650: 0a1b lsrs r3, r3, #8 8001652: f003 0307 and.w r3, r3, #7 } 8001656: 4618 mov r0, r3 8001658: 46bd mov sp, r7 800165a: f85d 7b04 ldr.w r7, [sp], #4 800165e: 4770 bx lr 8001660: e000ed00 .word 0xe000ed00 08001664 <__NVIC_EnableIRQ>: { 8001664: b480 push {r7} 8001666: b083 sub sp, #12 8001668: af00 add r7, sp, #0 800166a: 4603 mov r3, r0 800166c: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 800166e: f9b7 3006 ldrsh.w r3, [r7, #6] 8001672: 2b00 cmp r3, #0 8001674: db0b blt.n 800168e <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001676: 88fb ldrh r3, [r7, #6] 8001678: f003 021f and.w r2, r3, #31 800167c: 4907 ldr r1, [pc, #28] ; (800169c <__NVIC_EnableIRQ+0x38>) 800167e: f9b7 3006 ldrsh.w r3, [r7, #6] 8001682: 095b lsrs r3, r3, #5 8001684: 2001 movs r0, #1 8001686: fa00 f202 lsl.w r2, r0, r2 800168a: f841 2023 str.w r2, [r1, r3, lsl #2] } 800168e: bf00 nop 8001690: 370c adds r7, #12 8001692: 46bd mov sp, r7 8001694: f85d 7b04 ldr.w r7, [sp], #4 8001698: 4770 bx lr 800169a: bf00 nop 800169c: e000e100 .word 0xe000e100 080016a0 <__NVIC_SetPriority>: { 80016a0: b480 push {r7} 80016a2: b083 sub sp, #12 80016a4: af00 add r7, sp, #0 80016a6: 4603 mov r3, r0 80016a8: 6039 str r1, [r7, #0] 80016aa: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 80016ac: f9b7 3006 ldrsh.w r3, [r7, #6] 80016b0: 2b00 cmp r3, #0 80016b2: db0a blt.n 80016ca <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80016b4: 683b ldr r3, [r7, #0] 80016b6: b2da uxtb r2, r3 80016b8: 490c ldr r1, [pc, #48] ; (80016ec <__NVIC_SetPriority+0x4c>) 80016ba: f9b7 3006 ldrsh.w r3, [r7, #6] 80016be: 0112 lsls r2, r2, #4 80016c0: b2d2 uxtb r2, r2 80016c2: 440b add r3, r1 80016c4: f883 2300 strb.w r2, [r3, #768] ; 0x300 } 80016c8: e00a b.n 80016e0 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80016ca: 683b ldr r3, [r7, #0] 80016cc: b2da uxtb r2, r3 80016ce: 4908 ldr r1, [pc, #32] ; (80016f0 <__NVIC_SetPriority+0x50>) 80016d0: 88fb ldrh r3, [r7, #6] 80016d2: f003 030f and.w r3, r3, #15 80016d6: 3b04 subs r3, #4 80016d8: 0112 lsls r2, r2, #4 80016da: b2d2 uxtb r2, r2 80016dc: 440b add r3, r1 80016de: 761a strb r2, [r3, #24] } 80016e0: bf00 nop 80016e2: 370c adds r7, #12 80016e4: 46bd mov sp, r7 80016e6: f85d 7b04 ldr.w r7, [sp], #4 80016ea: 4770 bx lr 80016ec: e000e100 .word 0xe000e100 80016f0: e000ed00 .word 0xe000ed00 080016f4 : { 80016f4: b480 push {r7} 80016f6: b089 sub sp, #36 ; 0x24 80016f8: af00 add r7, sp, #0 80016fa: 60f8 str r0, [r7, #12] 80016fc: 60b9 str r1, [r7, #8] 80016fe: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001700: 68fb ldr r3, [r7, #12] 8001702: f003 0307 and.w r3, r3, #7 8001706: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001708: 69fb ldr r3, [r7, #28] 800170a: f1c3 0307 rsb r3, r3, #7 800170e: 2b04 cmp r3, #4 8001710: bf28 it cs 8001712: 2304 movcs r3, #4 8001714: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001716: 69fb ldr r3, [r7, #28] 8001718: 3304 adds r3, #4 800171a: 2b06 cmp r3, #6 800171c: d902 bls.n 8001724 800171e: 69fb ldr r3, [r7, #28] 8001720: 3b03 subs r3, #3 8001722: e000 b.n 8001726 8001724: 2300 movs r3, #0 8001726: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001728: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 800172c: 69bb ldr r3, [r7, #24] 800172e: fa02 f303 lsl.w r3, r2, r3 8001732: 43da mvns r2, r3 8001734: 68bb ldr r3, [r7, #8] 8001736: 401a ands r2, r3 8001738: 697b ldr r3, [r7, #20] 800173a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800173c: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001740: 697b ldr r3, [r7, #20] 8001742: fa01 f303 lsl.w r3, r1, r3 8001746: 43d9 mvns r1, r3 8001748: 687b ldr r3, [r7, #4] 800174a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800174c: 4313 orrs r3, r2 } 800174e: 4618 mov r0, r3 8001750: 3724 adds r7, #36 ; 0x24 8001752: 46bd mov sp, r7 8001754: f85d 7b04 ldr.w r7, [sp], #4 8001758: 4770 bx lr ... 0800175c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800175c: b580 push {r7, lr} 800175e: b082 sub sp, #8 8001760: af00 add r7, sp, #0 8001762: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001764: 687b ldr r3, [r7, #4] 8001766: 3b01 subs r3, #1 8001768: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 800176c: d301 bcc.n 8001772 { return (1UL); /* Reload value impossible */ 800176e: 2301 movs r3, #1 8001770: e00f b.n 8001792 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001772: 4a0a ldr r2, [pc, #40] ; (800179c ) 8001774: 687b ldr r3, [r7, #4] 8001776: 3b01 subs r3, #1 8001778: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800177a: 210f movs r1, #15 800177c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001780: f7ff ff8e bl 80016a0 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001784: 4b05 ldr r3, [pc, #20] ; (800179c ) 8001786: 2200 movs r2, #0 8001788: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800178a: 4b04 ldr r3, [pc, #16] ; (800179c ) 800178c: 2207 movs r2, #7 800178e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001790: 2300 movs r3, #0 } 8001792: 4618 mov r0, r3 8001794: 3708 adds r7, #8 8001796: 46bd mov sp, r7 8001798: bd80 pop {r7, pc} 800179a: bf00 nop 800179c: e000e010 .word 0xe000e010 080017a0 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80017a0: b580 push {r7, lr} 80017a2: b082 sub sp, #8 80017a4: af00 add r7, sp, #0 80017a6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80017a8: 6878 ldr r0, [r7, #4] 80017aa: f7ff ff29 bl 8001600 <__NVIC_SetPriorityGrouping> } 80017ae: bf00 nop 80017b0: 3708 adds r7, #8 80017b2: 46bd mov sp, r7 80017b4: bd80 pop {r7, pc} 080017b6 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80017b6: b580 push {r7, lr} 80017b8: b086 sub sp, #24 80017ba: af00 add r7, sp, #0 80017bc: 4603 mov r3, r0 80017be: 60b9 str r1, [r7, #8] 80017c0: 607a str r2, [r7, #4] 80017c2: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80017c4: f7ff ff40 bl 8001648 <__NVIC_GetPriorityGrouping> 80017c8: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80017ca: 687a ldr r2, [r7, #4] 80017cc: 68b9 ldr r1, [r7, #8] 80017ce: 6978 ldr r0, [r7, #20] 80017d0: f7ff ff90 bl 80016f4 80017d4: 4602 mov r2, r0 80017d6: f9b7 300e ldrsh.w r3, [r7, #14] 80017da: 4611 mov r1, r2 80017dc: 4618 mov r0, r3 80017de: f7ff ff5f bl 80016a0 <__NVIC_SetPriority> } 80017e2: bf00 nop 80017e4: 3718 adds r7, #24 80017e6: 46bd mov sp, r7 80017e8: bd80 pop {r7, pc} 080017ea : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80017ea: b580 push {r7, lr} 80017ec: b082 sub sp, #8 80017ee: af00 add r7, sp, #0 80017f0: 4603 mov r3, r0 80017f2: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80017f4: f9b7 3006 ldrsh.w r3, [r7, #6] 80017f8: 4618 mov r0, r3 80017fa: f7ff ff33 bl 8001664 <__NVIC_EnableIRQ> } 80017fe: bf00 nop 8001800: 3708 adds r7, #8 8001802: 46bd mov sp, r7 8001804: bd80 pop {r7, pc} 08001806 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001806: b580 push {r7, lr} 8001808: b082 sub sp, #8 800180a: af00 add r7, sp, #0 800180c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800180e: 6878 ldr r0, [r7, #4] 8001810: f7ff ffa4 bl 800175c 8001814: 4603 mov r3, r0 } 8001816: 4618 mov r0, r3 8001818: 3708 adds r7, #8 800181a: 46bd mov sp, r7 800181c: bd80 pop {r7, pc} ... 08001820 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001820: b480 push {r7} 8001822: b089 sub sp, #36 ; 0x24 8001824: af00 add r7, sp, #0 8001826: 6078 str r0, [r7, #4] 8001828: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 800182a: 2300 movs r3, #0 800182c: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 800182e: 4b86 ldr r3, [pc, #536] ; (8001a48 ) 8001830: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 8001832: e18c b.n 8001b4e { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 8001834: 683b ldr r3, [r7, #0] 8001836: 681a ldr r2, [r3, #0] 8001838: 2101 movs r1, #1 800183a: 69fb ldr r3, [r7, #28] 800183c: fa01 f303 lsl.w r3, r1, r3 8001840: 4013 ands r3, r2 8001842: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 8001844: 693b ldr r3, [r7, #16] 8001846: 2b00 cmp r3, #0 8001848: f000 817e beq.w 8001b48 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800184c: 683b ldr r3, [r7, #0] 800184e: 685b ldr r3, [r3, #4] 8001850: f003 0303 and.w r3, r3, #3 8001854: 2b01 cmp r3, #1 8001856: d005 beq.n 8001864 8001858: 683b ldr r3, [r7, #0] 800185a: 685b ldr r3, [r3, #4] 800185c: f003 0303 and.w r3, r3, #3 8001860: 2b02 cmp r3, #2 8001862: d130 bne.n 80018c6 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001864: 687b ldr r3, [r7, #4] 8001866: 689b ldr r3, [r3, #8] 8001868: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800186a: 69fb ldr r3, [r7, #28] 800186c: 005b lsls r3, r3, #1 800186e: 2203 movs r2, #3 8001870: fa02 f303 lsl.w r3, r2, r3 8001874: 43db mvns r3, r3 8001876: 69ba ldr r2, [r7, #24] 8001878: 4013 ands r3, r2 800187a: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800187c: 683b ldr r3, [r7, #0] 800187e: 68da ldr r2, [r3, #12] 8001880: 69fb ldr r3, [r7, #28] 8001882: 005b lsls r3, r3, #1 8001884: fa02 f303 lsl.w r3, r2, r3 8001888: 69ba ldr r2, [r7, #24] 800188a: 4313 orrs r3, r2 800188c: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800188e: 687b ldr r3, [r7, #4] 8001890: 69ba ldr r2, [r7, #24] 8001892: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8001894: 687b ldr r3, [r7, #4] 8001896: 685b ldr r3, [r3, #4] 8001898: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 800189a: 2201 movs r2, #1 800189c: 69fb ldr r3, [r7, #28] 800189e: fa02 f303 lsl.w r3, r2, r3 80018a2: 43db mvns r3, r3 80018a4: 69ba ldr r2, [r7, #24] 80018a6: 4013 ands r3, r2 80018a8: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80018aa: 683b ldr r3, [r7, #0] 80018ac: 685b ldr r3, [r3, #4] 80018ae: 091b lsrs r3, r3, #4 80018b0: f003 0201 and.w r2, r3, #1 80018b4: 69fb ldr r3, [r7, #28] 80018b6: fa02 f303 lsl.w r3, r2, r3 80018ba: 69ba ldr r2, [r7, #24] 80018bc: 4313 orrs r3, r2 80018be: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 80018c0: 687b ldr r3, [r7, #4] 80018c2: 69ba ldr r2, [r7, #24] 80018c4: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 80018c6: 683b ldr r3, [r7, #0] 80018c8: 685b ldr r3, [r3, #4] 80018ca: f003 0303 and.w r3, r3, #3 80018ce: 2b03 cmp r3, #3 80018d0: d017 beq.n 8001902 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 80018d2: 687b ldr r3, [r7, #4] 80018d4: 68db ldr r3, [r3, #12] 80018d6: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 80018d8: 69fb ldr r3, [r7, #28] 80018da: 005b lsls r3, r3, #1 80018dc: 2203 movs r2, #3 80018de: fa02 f303 lsl.w r3, r2, r3 80018e2: 43db mvns r3, r3 80018e4: 69ba ldr r2, [r7, #24] 80018e6: 4013 ands r3, r2 80018e8: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 80018ea: 683b ldr r3, [r7, #0] 80018ec: 689a ldr r2, [r3, #8] 80018ee: 69fb ldr r3, [r7, #28] 80018f0: 005b lsls r3, r3, #1 80018f2: fa02 f303 lsl.w r3, r2, r3 80018f6: 69ba ldr r2, [r7, #24] 80018f8: 4313 orrs r3, r2 80018fa: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 80018fc: 687b ldr r3, [r7, #4] 80018fe: 69ba ldr r2, [r7, #24] 8001900: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001902: 683b ldr r3, [r7, #0] 8001904: 685b ldr r3, [r3, #4] 8001906: f003 0303 and.w r3, r3, #3 800190a: 2b02 cmp r3, #2 800190c: d123 bne.n 8001956 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800190e: 69fb ldr r3, [r7, #28] 8001910: 08da lsrs r2, r3, #3 8001912: 687b ldr r3, [r7, #4] 8001914: 3208 adds r2, #8 8001916: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800191a: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 800191c: 69fb ldr r3, [r7, #28] 800191e: f003 0307 and.w r3, r3, #7 8001922: 009b lsls r3, r3, #2 8001924: 220f movs r2, #15 8001926: fa02 f303 lsl.w r3, r2, r3 800192a: 43db mvns r3, r3 800192c: 69ba ldr r2, [r7, #24] 800192e: 4013 ands r3, r2 8001930: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8001932: 683b ldr r3, [r7, #0] 8001934: 691a ldr r2, [r3, #16] 8001936: 69fb ldr r3, [r7, #28] 8001938: f003 0307 and.w r3, r3, #7 800193c: 009b lsls r3, r3, #2 800193e: fa02 f303 lsl.w r3, r2, r3 8001942: 69ba ldr r2, [r7, #24] 8001944: 4313 orrs r3, r2 8001946: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8001948: 69fb ldr r3, [r7, #28] 800194a: 08da lsrs r2, r3, #3 800194c: 687b ldr r3, [r7, #4] 800194e: 3208 adds r2, #8 8001950: 69b9 ldr r1, [r7, #24] 8001952: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001956: 687b ldr r3, [r7, #4] 8001958: 681b ldr r3, [r3, #0] 800195a: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 800195c: 69fb ldr r3, [r7, #28] 800195e: 005b lsls r3, r3, #1 8001960: 2203 movs r2, #3 8001962: fa02 f303 lsl.w r3, r2, r3 8001966: 43db mvns r3, r3 8001968: 69ba ldr r2, [r7, #24] 800196a: 4013 ands r3, r2 800196c: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800196e: 683b ldr r3, [r7, #0] 8001970: 685b ldr r3, [r3, #4] 8001972: f003 0203 and.w r2, r3, #3 8001976: 69fb ldr r3, [r7, #28] 8001978: 005b lsls r3, r3, #1 800197a: fa02 f303 lsl.w r3, r2, r3 800197e: 69ba ldr r2, [r7, #24] 8001980: 4313 orrs r3, r2 8001982: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8001984: 687b ldr r3, [r7, #4] 8001986: 69ba ldr r2, [r7, #24] 8001988: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 800198a: 683b ldr r3, [r7, #0] 800198c: 685b ldr r3, [r3, #4] 800198e: f403 3340 and.w r3, r3, #196608 ; 0x30000 8001992: 2b00 cmp r3, #0 8001994: f000 80d8 beq.w 8001b48 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001998: 4b2c ldr r3, [pc, #176] ; (8001a4c ) 800199a: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 800199e: 4a2b ldr r2, [pc, #172] ; (8001a4c ) 80019a0: f043 0302 orr.w r3, r3, #2 80019a4: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 80019a8: 4b28 ldr r3, [pc, #160] ; (8001a4c ) 80019aa: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 80019ae: f003 0302 and.w r3, r3, #2 80019b2: 60fb str r3, [r7, #12] 80019b4: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 80019b6: 4a26 ldr r2, [pc, #152] ; (8001a50 ) 80019b8: 69fb ldr r3, [r7, #28] 80019ba: 089b lsrs r3, r3, #2 80019bc: 3302 adds r3, #2 80019be: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80019c2: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 80019c4: 69fb ldr r3, [r7, #28] 80019c6: f003 0303 and.w r3, r3, #3 80019ca: 009b lsls r3, r3, #2 80019cc: 220f movs r2, #15 80019ce: fa02 f303 lsl.w r3, r2, r3 80019d2: 43db mvns r3, r3 80019d4: 69ba ldr r2, [r7, #24] 80019d6: 4013 ands r3, r2 80019d8: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 80019da: 687b ldr r3, [r7, #4] 80019dc: 4a1d ldr r2, [pc, #116] ; (8001a54 ) 80019de: 4293 cmp r3, r2 80019e0: d04a beq.n 8001a78 80019e2: 687b ldr r3, [r7, #4] 80019e4: 4a1c ldr r2, [pc, #112] ; (8001a58 ) 80019e6: 4293 cmp r3, r2 80019e8: d02b beq.n 8001a42 80019ea: 687b ldr r3, [r7, #4] 80019ec: 4a1b ldr r2, [pc, #108] ; (8001a5c ) 80019ee: 4293 cmp r3, r2 80019f0: d025 beq.n 8001a3e 80019f2: 687b ldr r3, [r7, #4] 80019f4: 4a1a ldr r2, [pc, #104] ; (8001a60 ) 80019f6: 4293 cmp r3, r2 80019f8: d01f beq.n 8001a3a 80019fa: 687b ldr r3, [r7, #4] 80019fc: 4a19 ldr r2, [pc, #100] ; (8001a64 ) 80019fe: 4293 cmp r3, r2 8001a00: d019 beq.n 8001a36 8001a02: 687b ldr r3, [r7, #4] 8001a04: 4a18 ldr r2, [pc, #96] ; (8001a68 ) 8001a06: 4293 cmp r3, r2 8001a08: d013 beq.n 8001a32 8001a0a: 687b ldr r3, [r7, #4] 8001a0c: 4a17 ldr r2, [pc, #92] ; (8001a6c ) 8001a0e: 4293 cmp r3, r2 8001a10: d00d beq.n 8001a2e 8001a12: 687b ldr r3, [r7, #4] 8001a14: 4a16 ldr r2, [pc, #88] ; (8001a70 ) 8001a16: 4293 cmp r3, r2 8001a18: d007 beq.n 8001a2a 8001a1a: 687b ldr r3, [r7, #4] 8001a1c: 4a15 ldr r2, [pc, #84] ; (8001a74 ) 8001a1e: 4293 cmp r3, r2 8001a20: d101 bne.n 8001a26 8001a22: 2309 movs r3, #9 8001a24: e029 b.n 8001a7a 8001a26: 230a movs r3, #10 8001a28: e027 b.n 8001a7a 8001a2a: 2307 movs r3, #7 8001a2c: e025 b.n 8001a7a 8001a2e: 2306 movs r3, #6 8001a30: e023 b.n 8001a7a 8001a32: 2305 movs r3, #5 8001a34: e021 b.n 8001a7a 8001a36: 2304 movs r3, #4 8001a38: e01f b.n 8001a7a 8001a3a: 2303 movs r3, #3 8001a3c: e01d b.n 8001a7a 8001a3e: 2302 movs r3, #2 8001a40: e01b b.n 8001a7a 8001a42: 2301 movs r3, #1 8001a44: e019 b.n 8001a7a 8001a46: bf00 nop 8001a48: 58000080 .word 0x58000080 8001a4c: 58024400 .word 0x58024400 8001a50: 58000400 .word 0x58000400 8001a54: 58020000 .word 0x58020000 8001a58: 58020400 .word 0x58020400 8001a5c: 58020800 .word 0x58020800 8001a60: 58020c00 .word 0x58020c00 8001a64: 58021000 .word 0x58021000 8001a68: 58021400 .word 0x58021400 8001a6c: 58021800 .word 0x58021800 8001a70: 58021c00 .word 0x58021c00 8001a74: 58022400 .word 0x58022400 8001a78: 2300 movs r3, #0 8001a7a: 69fa ldr r2, [r7, #28] 8001a7c: f002 0203 and.w r2, r2, #3 8001a80: 0092 lsls r2, r2, #2 8001a82: 4093 lsls r3, r2 8001a84: 69ba ldr r2, [r7, #24] 8001a86: 4313 orrs r3, r2 8001a88: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8001a8a: 4938 ldr r1, [pc, #224] ; (8001b6c ) 8001a8c: 69fb ldr r3, [r7, #28] 8001a8e: 089b lsrs r3, r3, #2 8001a90: 3302 adds r3, #2 8001a92: 69ba ldr r2, [r7, #24] 8001a94: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8001a98: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 8001a9c: 681b ldr r3, [r3, #0] 8001a9e: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001aa0: 693b ldr r3, [r7, #16] 8001aa2: 43db mvns r3, r3 8001aa4: 69ba ldr r2, [r7, #24] 8001aa6: 4013 ands r3, r2 8001aa8: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8001aaa: 683b ldr r3, [r7, #0] 8001aac: 685b ldr r3, [r3, #4] 8001aae: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8001ab2: 2b00 cmp r3, #0 8001ab4: d003 beq.n 8001abe { temp |= iocurrent; 8001ab6: 69ba ldr r2, [r7, #24] 8001ab8: 693b ldr r3, [r7, #16] 8001aba: 4313 orrs r3, r2 8001abc: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 8001abe: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 8001ac2: 69bb ldr r3, [r7, #24] 8001ac4: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 8001ac6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 8001aca: 685b ldr r3, [r3, #4] 8001acc: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001ace: 693b ldr r3, [r7, #16] 8001ad0: 43db mvns r3, r3 8001ad2: 69ba ldr r2, [r7, #24] 8001ad4: 4013 ands r3, r2 8001ad6: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8001ad8: 683b ldr r3, [r7, #0] 8001ada: 685b ldr r3, [r3, #4] 8001adc: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001ae0: 2b00 cmp r3, #0 8001ae2: d003 beq.n 8001aec { temp |= iocurrent; 8001ae4: 69ba ldr r2, [r7, #24] 8001ae6: 693b ldr r3, [r7, #16] 8001ae8: 4313 orrs r3, r2 8001aea: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 8001aec: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 8001af0: 69bb ldr r3, [r7, #24] 8001af2: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 8001af4: 697b ldr r3, [r7, #20] 8001af6: 685b ldr r3, [r3, #4] 8001af8: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001afa: 693b ldr r3, [r7, #16] 8001afc: 43db mvns r3, r3 8001afe: 69ba ldr r2, [r7, #24] 8001b00: 4013 ands r3, r2 8001b02: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8001b04: 683b ldr r3, [r7, #0] 8001b06: 685b ldr r3, [r3, #4] 8001b08: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001b0c: 2b00 cmp r3, #0 8001b0e: d003 beq.n 8001b18 { temp |= iocurrent; 8001b10: 69ba ldr r2, [r7, #24] 8001b12: 693b ldr r3, [r7, #16] 8001b14: 4313 orrs r3, r2 8001b16: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 8001b18: 697b ldr r3, [r7, #20] 8001b1a: 69ba ldr r2, [r7, #24] 8001b1c: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 8001b1e: 697b ldr r3, [r7, #20] 8001b20: 681b ldr r3, [r3, #0] 8001b22: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001b24: 693b ldr r3, [r7, #16] 8001b26: 43db mvns r3, r3 8001b28: 69ba ldr r2, [r7, #24] 8001b2a: 4013 ands r3, r2 8001b2c: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8001b2e: 683b ldr r3, [r7, #0] 8001b30: 685b ldr r3, [r3, #4] 8001b32: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001b36: 2b00 cmp r3, #0 8001b38: d003 beq.n 8001b42 { temp |= iocurrent; 8001b3a: 69ba ldr r2, [r7, #24] 8001b3c: 693b ldr r3, [r7, #16] 8001b3e: 4313 orrs r3, r2 8001b40: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 8001b42: 697b ldr r3, [r7, #20] 8001b44: 69ba ldr r2, [r7, #24] 8001b46: 601a str r2, [r3, #0] } } position++; 8001b48: 69fb ldr r3, [r7, #28] 8001b4a: 3301 adds r3, #1 8001b4c: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 8001b4e: 683b ldr r3, [r7, #0] 8001b50: 681a ldr r2, [r3, #0] 8001b52: 69fb ldr r3, [r7, #28] 8001b54: fa22 f303 lsr.w r3, r2, r3 8001b58: 2b00 cmp r3, #0 8001b5a: f47f ae6b bne.w 8001834 } } 8001b5e: bf00 nop 8001b60: bf00 nop 8001b62: 3724 adds r7, #36 ; 0x24 8001b64: 46bd mov sp, r7 8001b66: f85d 7b04 ldr.w r7, [sp], #4 8001b6a: 4770 bx lr 8001b6c: 58000400 .word 0x58000400 08001b70 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001b70: b480 push {r7} 8001b72: b083 sub sp, #12 8001b74: af00 add r7, sp, #0 8001b76: 6078 str r0, [r7, #4] 8001b78: 460b mov r3, r1 8001b7a: 807b strh r3, [r7, #2] 8001b7c: 4613 mov r3, r2 8001b7e: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001b80: 787b ldrb r3, [r7, #1] 8001b82: 2b00 cmp r3, #0 8001b84: d003 beq.n 8001b8e { GPIOx->BSRR = GPIO_Pin; 8001b86: 887a ldrh r2, [r7, #2] 8001b88: 687b ldr r3, [r7, #4] 8001b8a: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 8001b8c: e003 b.n 8001b96 GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 8001b8e: 887b ldrh r3, [r7, #2] 8001b90: 041a lsls r2, r3, #16 8001b92: 687b ldr r3, [r7, #4] 8001b94: 619a str r2, [r3, #24] } 8001b96: bf00 nop 8001b98: 370c adds r7, #12 8001b9a: 46bd mov sp, r7 8001b9c: f85d 7b04 ldr.w r7, [sp], #4 8001ba0: 4770 bx lr 08001ba2 : * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8001ba2: b480 push {r7} 8001ba4: b085 sub sp, #20 8001ba6: af00 add r7, sp, #0 8001ba8: 6078 str r0, [r7, #4] 8001baa: 460b mov r3, r1 8001bac: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 8001bae: 687b ldr r3, [r7, #4] 8001bb0: 695b ldr r3, [r3, #20] 8001bb2: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 8001bb4: 887a ldrh r2, [r7, #2] 8001bb6: 68fb ldr r3, [r7, #12] 8001bb8: 4013 ands r3, r2 8001bba: 041a lsls r2, r3, #16 8001bbc: 68fb ldr r3, [r7, #12] 8001bbe: 43d9 mvns r1, r3 8001bc0: 887b ldrh r3, [r7, #2] 8001bc2: 400b ands r3, r1 8001bc4: 431a orrs r2, r3 8001bc6: 687b ldr r3, [r7, #4] 8001bc8: 619a str r2, [r3, #24] } 8001bca: bf00 nop 8001bcc: 3714 adds r7, #20 8001bce: 46bd mov sp, r7 8001bd0: f85d 7b04 ldr.w r7, [sp], #4 8001bd4: 4770 bx lr 08001bd6 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8001bd6: b5f0 push {r4, r5, r6, r7, lr} 8001bd8: b08f sub sp, #60 ; 0x3c 8001bda: af0a add r7, sp, #40 ; 0x28 8001bdc: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx; uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8001bde: 687b ldr r3, [r7, #4] 8001be0: 2b00 cmp r3, #0 8001be2: d101 bne.n 8001be8 { return HAL_ERROR; 8001be4: 2301 movs r3, #1 8001be6: e116 b.n 8001e16 } /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); USBx = hpcd->Instance; 8001be8: 687b ldr r3, [r7, #4] 8001bea: 681b ldr r3, [r3, #0] 8001bec: 60bb str r3, [r7, #8] if (hpcd->State == HAL_PCD_STATE_RESET) 8001bee: 687b ldr r3, [r7, #4] 8001bf0: f893 33bd ldrb.w r3, [r3, #957] ; 0x3bd 8001bf4: b2db uxtb r3, r3 8001bf6: 2b00 cmp r3, #0 8001bf8: d106 bne.n 8001c08 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8001bfa: 687b ldr r3, [r7, #4] 8001bfc: 2200 movs r2, #0 8001bfe: f883 23bc strb.w r2, [r3, #956] ; 0x3bc /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8001c02: 6878 ldr r0, [r7, #4] 8001c04: f007 fad2 bl 80091ac #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8001c08: 687b ldr r3, [r7, #4] 8001c0a: 2203 movs r2, #3 8001c0c: f883 23bd strb.w r2, [r3, #957] ; 0x3bd /* Disable DMA mode for FS instance */ if ((USBx->CID & (0x1U << 8)) == 0U) 8001c10: 68bb ldr r3, [r7, #8] 8001c12: 6bdb ldr r3, [r3, #60] ; 0x3c 8001c14: f403 7380 and.w r3, r3, #256 ; 0x100 8001c18: 2b00 cmp r3, #0 8001c1a: d102 bne.n 8001c22 { hpcd->Init.dma_enable = 0U; 8001c1c: 687b ldr r3, [r7, #4] 8001c1e: 2200 movs r2, #0 8001c20: 611a str r2, [r3, #16] } /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8001c22: 687b ldr r3, [r7, #4] 8001c24: 681b ldr r3, [r3, #0] 8001c26: 4618 mov r0, r3 8001c28: f004 f99f bl 8005f6a /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8001c2c: 687b ldr r3, [r7, #4] 8001c2e: 681b ldr r3, [r3, #0] 8001c30: 603b str r3, [r7, #0] 8001c32: 687e ldr r6, [r7, #4] 8001c34: 466d mov r5, sp 8001c36: f106 0410 add.w r4, r6, #16 8001c3a: cc0f ldmia r4!, {r0, r1, r2, r3} 8001c3c: c50f stmia r5!, {r0, r1, r2, r3} 8001c3e: cc0f ldmia r4!, {r0, r1, r2, r3} 8001c40: c50f stmia r5!, {r0, r1, r2, r3} 8001c42: e894 0003 ldmia.w r4, {r0, r1} 8001c46: e885 0003 stmia.w r5, {r0, r1} 8001c4a: 1d33 adds r3, r6, #4 8001c4c: cb0e ldmia r3, {r1, r2, r3} 8001c4e: 6838 ldr r0, [r7, #0] 8001c50: f004 f86a bl 8005d28 8001c54: 4603 mov r3, r0 8001c56: 2b00 cmp r3, #0 8001c58: d005 beq.n 8001c66 { hpcd->State = HAL_PCD_STATE_ERROR; 8001c5a: 687b ldr r3, [r7, #4] 8001c5c: 2202 movs r2, #2 8001c5e: f883 23bd strb.w r2, [r3, #957] ; 0x3bd return HAL_ERROR; 8001c62: 2301 movs r3, #1 8001c64: e0d7 b.n 8001e16 } /* Force Device Mode*/ (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); 8001c66: 687b ldr r3, [r7, #4] 8001c68: 681b ldr r3, [r3, #0] 8001c6a: 2100 movs r1, #0 8001c6c: 4618 mov r0, r3 8001c6e: f004 f98d bl 8005f8c /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8001c72: 2300 movs r3, #0 8001c74: 73fb strb r3, [r7, #15] 8001c76: e04a b.n 8001d0e { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8001c78: 7bfa ldrb r2, [r7, #15] 8001c7a: 6879 ldr r1, [r7, #4] 8001c7c: 4613 mov r3, r2 8001c7e: 00db lsls r3, r3, #3 8001c80: 1a9b subs r3, r3, r2 8001c82: 009b lsls r3, r3, #2 8001c84: 440b add r3, r1 8001c86: 333d adds r3, #61 ; 0x3d 8001c88: 2201 movs r2, #1 8001c8a: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8001c8c: 7bfa ldrb r2, [r7, #15] 8001c8e: 6879 ldr r1, [r7, #4] 8001c90: 4613 mov r3, r2 8001c92: 00db lsls r3, r3, #3 8001c94: 1a9b subs r3, r3, r2 8001c96: 009b lsls r3, r3, #2 8001c98: 440b add r3, r1 8001c9a: 333c adds r3, #60 ; 0x3c 8001c9c: 7bfa ldrb r2, [r7, #15] 8001c9e: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 8001ca0: 7bfa ldrb r2, [r7, #15] 8001ca2: 7bfb ldrb r3, [r7, #15] 8001ca4: b298 uxth r0, r3 8001ca6: 6879 ldr r1, [r7, #4] 8001ca8: 4613 mov r3, r2 8001caa: 00db lsls r3, r3, #3 8001cac: 1a9b subs r3, r3, r2 8001cae: 009b lsls r3, r3, #2 8001cb0: 440b add r3, r1 8001cb2: 3342 adds r3, #66 ; 0x42 8001cb4: 4602 mov r2, r0 8001cb6: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 8001cb8: 7bfa ldrb r2, [r7, #15] 8001cba: 6879 ldr r1, [r7, #4] 8001cbc: 4613 mov r3, r2 8001cbe: 00db lsls r3, r3, #3 8001cc0: 1a9b subs r3, r3, r2 8001cc2: 009b lsls r3, r3, #2 8001cc4: 440b add r3, r1 8001cc6: 333f adds r3, #63 ; 0x3f 8001cc8: 2200 movs r2, #0 8001cca: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8001ccc: 7bfa ldrb r2, [r7, #15] 8001cce: 6879 ldr r1, [r7, #4] 8001cd0: 4613 mov r3, r2 8001cd2: 00db lsls r3, r3, #3 8001cd4: 1a9b subs r3, r3, r2 8001cd6: 009b lsls r3, r3, #2 8001cd8: 440b add r3, r1 8001cda: 3344 adds r3, #68 ; 0x44 8001cdc: 2200 movs r2, #0 8001cde: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 8001ce0: 7bfa ldrb r2, [r7, #15] 8001ce2: 6879 ldr r1, [r7, #4] 8001ce4: 4613 mov r3, r2 8001ce6: 00db lsls r3, r3, #3 8001ce8: 1a9b subs r3, r3, r2 8001cea: 009b lsls r3, r3, #2 8001cec: 440b add r3, r1 8001cee: 3348 adds r3, #72 ; 0x48 8001cf0: 2200 movs r2, #0 8001cf2: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8001cf4: 7bfa ldrb r2, [r7, #15] 8001cf6: 6879 ldr r1, [r7, #4] 8001cf8: 4613 mov r3, r2 8001cfa: 00db lsls r3, r3, #3 8001cfc: 1a9b subs r3, r3, r2 8001cfe: 009b lsls r3, r3, #2 8001d00: 440b add r3, r1 8001d02: 3350 adds r3, #80 ; 0x50 8001d04: 2200 movs r2, #0 8001d06: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8001d08: 7bfb ldrb r3, [r7, #15] 8001d0a: 3301 adds r3, #1 8001d0c: 73fb strb r3, [r7, #15] 8001d0e: 7bfa ldrb r2, [r7, #15] 8001d10: 687b ldr r3, [r7, #4] 8001d12: 685b ldr r3, [r3, #4] 8001d14: 429a cmp r2, r3 8001d16: d3af bcc.n 8001c78 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8001d18: 2300 movs r3, #0 8001d1a: 73fb strb r3, [r7, #15] 8001d1c: e044 b.n 8001da8 { hpcd->OUT_ep[i].is_in = 0U; 8001d1e: 7bfa ldrb r2, [r7, #15] 8001d20: 6879 ldr r1, [r7, #4] 8001d22: 4613 mov r3, r2 8001d24: 00db lsls r3, r3, #3 8001d26: 1a9b subs r3, r3, r2 8001d28: 009b lsls r3, r3, #2 8001d2a: 440b add r3, r1 8001d2c: f203 13fd addw r3, r3, #509 ; 0x1fd 8001d30: 2200 movs r2, #0 8001d32: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8001d34: 7bfa ldrb r2, [r7, #15] 8001d36: 6879 ldr r1, [r7, #4] 8001d38: 4613 mov r3, r2 8001d3a: 00db lsls r3, r3, #3 8001d3c: 1a9b subs r3, r3, r2 8001d3e: 009b lsls r3, r3, #2 8001d40: 440b add r3, r1 8001d42: f503 73fe add.w r3, r3, #508 ; 0x1fc 8001d46: 7bfa ldrb r2, [r7, #15] 8001d48: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8001d4a: 7bfa ldrb r2, [r7, #15] 8001d4c: 6879 ldr r1, [r7, #4] 8001d4e: 4613 mov r3, r2 8001d50: 00db lsls r3, r3, #3 8001d52: 1a9b subs r3, r3, r2 8001d54: 009b lsls r3, r3, #2 8001d56: 440b add r3, r1 8001d58: f203 13ff addw r3, r3, #511 ; 0x1ff 8001d5c: 2200 movs r2, #0 8001d5e: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8001d60: 7bfa ldrb r2, [r7, #15] 8001d62: 6879 ldr r1, [r7, #4] 8001d64: 4613 mov r3, r2 8001d66: 00db lsls r3, r3, #3 8001d68: 1a9b subs r3, r3, r2 8001d6a: 009b lsls r3, r3, #2 8001d6c: 440b add r3, r1 8001d6e: f503 7301 add.w r3, r3, #516 ; 0x204 8001d72: 2200 movs r2, #0 8001d74: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 8001d76: 7bfa ldrb r2, [r7, #15] 8001d78: 6879 ldr r1, [r7, #4] 8001d7a: 4613 mov r3, r2 8001d7c: 00db lsls r3, r3, #3 8001d7e: 1a9b subs r3, r3, r2 8001d80: 009b lsls r3, r3, #2 8001d82: 440b add r3, r1 8001d84: f503 7302 add.w r3, r3, #520 ; 0x208 8001d88: 2200 movs r2, #0 8001d8a: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8001d8c: 7bfa ldrb r2, [r7, #15] 8001d8e: 6879 ldr r1, [r7, #4] 8001d90: 4613 mov r3, r2 8001d92: 00db lsls r3, r3, #3 8001d94: 1a9b subs r3, r3, r2 8001d96: 009b lsls r3, r3, #2 8001d98: 440b add r3, r1 8001d9a: f503 7304 add.w r3, r3, #528 ; 0x210 8001d9e: 2200 movs r2, #0 8001da0: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8001da2: 7bfb ldrb r3, [r7, #15] 8001da4: 3301 adds r3, #1 8001da6: 73fb strb r3, [r7, #15] 8001da8: 7bfa ldrb r2, [r7, #15] 8001daa: 687b ldr r3, [r7, #4] 8001dac: 685b ldr r3, [r3, #4] 8001dae: 429a cmp r2, r3 8001db0: d3b5 bcc.n 8001d1e } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8001db2: 687b ldr r3, [r7, #4] 8001db4: 681b ldr r3, [r3, #0] 8001db6: 603b str r3, [r7, #0] 8001db8: 687e ldr r6, [r7, #4] 8001dba: 466d mov r5, sp 8001dbc: f106 0410 add.w r4, r6, #16 8001dc0: cc0f ldmia r4!, {r0, r1, r2, r3} 8001dc2: c50f stmia r5!, {r0, r1, r2, r3} 8001dc4: cc0f ldmia r4!, {r0, r1, r2, r3} 8001dc6: c50f stmia r5!, {r0, r1, r2, r3} 8001dc8: e894 0003 ldmia.w r4, {r0, r1} 8001dcc: e885 0003 stmia.w r5, {r0, r1} 8001dd0: 1d33 adds r3, r6, #4 8001dd2: cb0e ldmia r3, {r1, r2, r3} 8001dd4: 6838 ldr r0, [r7, #0] 8001dd6: f004 f925 bl 8006024 8001dda: 4603 mov r3, r0 8001ddc: 2b00 cmp r3, #0 8001dde: d005 beq.n 8001dec { hpcd->State = HAL_PCD_STATE_ERROR; 8001de0: 687b ldr r3, [r7, #4] 8001de2: 2202 movs r2, #2 8001de4: f883 23bd strb.w r2, [r3, #957] ; 0x3bd return HAL_ERROR; 8001de8: 2301 movs r3, #1 8001dea: e014 b.n 8001e16 } hpcd->USB_Address = 0U; 8001dec: 687b ldr r3, [r7, #4] 8001dee: 2200 movs r2, #0 8001df0: f883 2038 strb.w r2, [r3, #56] ; 0x38 hpcd->State = HAL_PCD_STATE_READY; 8001df4: 687b ldr r3, [r7, #4] 8001df6: 2201 movs r2, #1 8001df8: f883 23bd strb.w r2, [r3, #957] ; 0x3bd /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8001dfc: 687b ldr r3, [r7, #4] 8001dfe: 6a5b ldr r3, [r3, #36] ; 0x24 8001e00: 2b01 cmp r3, #1 8001e02: d102 bne.n 8001e0a { (void)HAL_PCDEx_ActivateLPM(hpcd); 8001e04: 6878 ldr r0, [r7, #4] 8001e06: f001 f885 bl 8002f14 } (void)USB_DevDisconnect(hpcd->Instance); 8001e0a: 687b ldr r3, [r7, #4] 8001e0c: 681b ldr r3, [r3, #0] 8001e0e: 4618 mov r0, r3 8001e10: f005 f9bd bl 800718e return HAL_OK; 8001e14: 2300 movs r3, #0 } 8001e16: 4618 mov r0, r3 8001e18: 3714 adds r7, #20 8001e1a: 46bd mov sp, r7 8001e1c: bdf0 pop {r4, r5, r6, r7, pc} 08001e1e : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 8001e1e: b580 push {r7, lr} 8001e20: b084 sub sp, #16 8001e22: af00 add r7, sp, #0 8001e24: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8001e26: 687b ldr r3, [r7, #4] 8001e28: 681b ldr r3, [r3, #0] 8001e2a: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 8001e2c: 687b ldr r3, [r7, #4] 8001e2e: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 8001e32: 2b01 cmp r3, #1 8001e34: d101 bne.n 8001e3a 8001e36: 2302 movs r3, #2 8001e38: e020 b.n 8001e7c 8001e3a: 687b ldr r3, [r7, #4] 8001e3c: 2201 movs r2, #1 8001e3e: f883 23bc strb.w r2, [r3, #956] ; 0x3bc if ((hpcd->Init.battery_charging_enable == 1U) && 8001e42: 687b ldr r3, [r7, #4] 8001e44: 6a9b ldr r3, [r3, #40] ; 0x28 8001e46: 2b01 cmp r3, #1 8001e48: d109 bne.n 8001e5e (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) 8001e4a: 687b ldr r3, [r7, #4] 8001e4c: 699b ldr r3, [r3, #24] if ((hpcd->Init.battery_charging_enable == 1U) && 8001e4e: 2b01 cmp r3, #1 8001e50: d005 beq.n 8001e5e { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8001e52: 68fb ldr r3, [r7, #12] 8001e54: 6b9b ldr r3, [r3, #56] ; 0x38 8001e56: f443 3280 orr.w r2, r3, #65536 ; 0x10000 8001e5a: 68fb ldr r3, [r7, #12] 8001e5c: 639a str r2, [r3, #56] ; 0x38 } __HAL_PCD_ENABLE(hpcd); 8001e5e: 687b ldr r3, [r7, #4] 8001e60: 681b ldr r3, [r3, #0] 8001e62: 4618 mov r0, r3 8001e64: f004 f870 bl 8005f48 (void)USB_DevConnect(hpcd->Instance); 8001e68: 687b ldr r3, [r7, #4] 8001e6a: 681b ldr r3, [r3, #0] 8001e6c: 4618 mov r0, r3 8001e6e: f005 f96d bl 800714c __HAL_UNLOCK(hpcd); 8001e72: 687b ldr r3, [r7, #4] 8001e74: 2200 movs r2, #0 8001e76: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 8001e7a: 2300 movs r3, #0 } 8001e7c: 4618 mov r0, r3 8001e7e: 3710 adds r7, #16 8001e80: 46bd mov sp, r7 8001e82: bd80 pop {r7, pc} 08001e84 : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 8001e84: b590 push {r4, r7, lr} 8001e86: b08d sub sp, #52 ; 0x34 8001e88: af00 add r7, sp, #0 8001e8a: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8001e8c: 687b ldr r3, [r7, #4] 8001e8e: 681b ldr r3, [r3, #0] 8001e90: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 8001e92: 6a3b ldr r3, [r7, #32] 8001e94: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t temp; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 8001e96: 687b ldr r3, [r7, #4] 8001e98: 681b ldr r3, [r3, #0] 8001e9a: 4618 mov r0, r3 8001e9c: f005 fa2b bl 80072f6 8001ea0: 4603 mov r3, r0 8001ea2: 2b00 cmp r3, #0 8001ea4: f040 83be bne.w 8002624 { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 8001ea8: 687b ldr r3, [r7, #4] 8001eaa: 681b ldr r3, [r3, #0] 8001eac: 4618 mov r0, r3 8001eae: f005 f98f bl 80071d0 8001eb2: 4603 mov r3, r0 8001eb4: 2b00 cmp r3, #0 8001eb6: f000 83b4 beq.w 8002622 { return; } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 8001eba: 687b ldr r3, [r7, #4] 8001ebc: 681b ldr r3, [r3, #0] 8001ebe: 4618 mov r0, r3 8001ec0: f005 f986 bl 80071d0 8001ec4: 4603 mov r3, r0 8001ec6: f003 0302 and.w r3, r3, #2 8001eca: 2b02 cmp r3, #2 8001ecc: d107 bne.n 8001ede { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 8001ece: 687b ldr r3, [r7, #4] 8001ed0: 681b ldr r3, [r3, #0] 8001ed2: 695a ldr r2, [r3, #20] 8001ed4: 687b ldr r3, [r7, #4] 8001ed6: 681b ldr r3, [r3, #0] 8001ed8: f002 0202 and.w r2, r2, #2 8001edc: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 8001ede: 687b ldr r3, [r7, #4] 8001ee0: 681b ldr r3, [r3, #0] 8001ee2: 4618 mov r0, r3 8001ee4: f005 f974 bl 80071d0 8001ee8: 4603 mov r3, r0 8001eea: f003 0310 and.w r3, r3, #16 8001eee: 2b10 cmp r3, #16 8001ef0: d161 bne.n 8001fb6 { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8001ef2: 687b ldr r3, [r7, #4] 8001ef4: 681b ldr r3, [r3, #0] 8001ef6: 699a ldr r2, [r3, #24] 8001ef8: 687b ldr r3, [r7, #4] 8001efa: 681b ldr r3, [r3, #0] 8001efc: f022 0210 bic.w r2, r2, #16 8001f00: 619a str r2, [r3, #24] temp = USBx->GRXSTSP; 8001f02: 6a3b ldr r3, [r7, #32] 8001f04: 6a1b ldr r3, [r3, #32] 8001f06: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; 8001f08: 69bb ldr r3, [r7, #24] 8001f0a: f003 020f and.w r2, r3, #15 8001f0e: 4613 mov r3, r2 8001f10: 00db lsls r3, r3, #3 8001f12: 1a9b subs r3, r3, r2 8001f14: 009b lsls r3, r3, #2 8001f16: f503 73fc add.w r3, r3, #504 ; 0x1f8 8001f1a: 687a ldr r2, [r7, #4] 8001f1c: 4413 add r3, r2 8001f1e: 3304 adds r3, #4 8001f20: 617b str r3, [r7, #20] if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 8001f22: 69bb ldr r3, [r7, #24] 8001f24: 0c5b lsrs r3, r3, #17 8001f26: f003 030f and.w r3, r3, #15 8001f2a: 2b02 cmp r3, #2 8001f2c: d124 bne.n 8001f78 { if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) 8001f2e: 69ba ldr r2, [r7, #24] 8001f30: f647 73f0 movw r3, #32752 ; 0x7ff0 8001f34: 4013 ands r3, r2 8001f36: 2b00 cmp r3, #0 8001f38: d035 beq.n 8001fa6 { (void)USB_ReadPacket(USBx, ep->xfer_buff, 8001f3a: 697b ldr r3, [r7, #20] 8001f3c: 68d9 ldr r1, [r3, #12] (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); 8001f3e: 69bb ldr r3, [r7, #24] 8001f40: 091b lsrs r3, r3, #4 8001f42: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 8001f44: f3c3 030a ubfx r3, r3, #0, #11 8001f48: b29b uxth r3, r3 8001f4a: 461a mov r2, r3 8001f4c: 6a38 ldr r0, [r7, #32] 8001f4e: f004 ffab bl 8006ea8 ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; 8001f52: 697b ldr r3, [r7, #20] 8001f54: 68da ldr r2, [r3, #12] 8001f56: 69bb ldr r3, [r7, #24] 8001f58: 091b lsrs r3, r3, #4 8001f5a: f3c3 030a ubfx r3, r3, #0, #11 8001f5e: 441a add r2, r3 8001f60: 697b ldr r3, [r7, #20] 8001f62: 60da str r2, [r3, #12] ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; 8001f64: 697b ldr r3, [r7, #20] 8001f66: 699a ldr r2, [r3, #24] 8001f68: 69bb ldr r3, [r7, #24] 8001f6a: 091b lsrs r3, r3, #4 8001f6c: f3c3 030a ubfx r3, r3, #0, #11 8001f70: 441a add r2, r3 8001f72: 697b ldr r3, [r7, #20] 8001f74: 619a str r2, [r3, #24] 8001f76: e016 b.n 8001fa6 } } else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 8001f78: 69bb ldr r3, [r7, #24] 8001f7a: 0c5b lsrs r3, r3, #17 8001f7c: f003 030f and.w r3, r3, #15 8001f80: 2b06 cmp r3, #6 8001f82: d110 bne.n 8001fa6 { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 8001f84: 687b ldr r3, [r7, #4] 8001f86: f503 7371 add.w r3, r3, #964 ; 0x3c4 8001f8a: 2208 movs r2, #8 8001f8c: 4619 mov r1, r3 8001f8e: 6a38 ldr r0, [r7, #32] 8001f90: f004 ff8a bl 8006ea8 ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; 8001f94: 697b ldr r3, [r7, #20] 8001f96: 699a ldr r2, [r3, #24] 8001f98: 69bb ldr r3, [r7, #24] 8001f9a: 091b lsrs r3, r3, #4 8001f9c: f3c3 030a ubfx r3, r3, #0, #11 8001fa0: 441a add r2, r3 8001fa2: 697b ldr r3, [r7, #20] 8001fa4: 619a str r2, [r3, #24] else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8001fa6: 687b ldr r3, [r7, #4] 8001fa8: 681b ldr r3, [r3, #0] 8001faa: 699a ldr r2, [r3, #24] 8001fac: 687b ldr r3, [r7, #4] 8001fae: 681b ldr r3, [r3, #0] 8001fb0: f042 0210 orr.w r2, r2, #16 8001fb4: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 8001fb6: 687b ldr r3, [r7, #4] 8001fb8: 681b ldr r3, [r3, #0] 8001fba: 4618 mov r0, r3 8001fbc: f005 f908 bl 80071d0 8001fc0: 4603 mov r3, r0 8001fc2: f403 2300 and.w r3, r3, #524288 ; 0x80000 8001fc6: f5b3 2f00 cmp.w r3, #524288 ; 0x80000 8001fca: d16e bne.n 80020aa { epnum = 0U; 8001fcc: 2300 movs r3, #0 8001fce: 627b str r3, [r7, #36] ; 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 8001fd0: 687b ldr r3, [r7, #4] 8001fd2: 681b ldr r3, [r3, #0] 8001fd4: 4618 mov r0, r3 8001fd6: f005 f90e bl 80071f6 8001fda: 62b8 str r0, [r7, #40] ; 0x28 while (ep_intr != 0U) 8001fdc: e062 b.n 80020a4 { if ((ep_intr & 0x1U) != 0U) 8001fde: 6abb ldr r3, [r7, #40] ; 0x28 8001fe0: f003 0301 and.w r3, r3, #1 8001fe4: 2b00 cmp r3, #0 8001fe6: d057 beq.n 8002098 { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8001fe8: 687b ldr r3, [r7, #4] 8001fea: 681b ldr r3, [r3, #0] 8001fec: 6a7a ldr r2, [r7, #36] ; 0x24 8001fee: b2d2 uxtb r2, r2 8001ff0: 4611 mov r1, r2 8001ff2: 4618 mov r0, r3 8001ff4: f005 f933 bl 800725e 8001ff8: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 8001ffa: 693b ldr r3, [r7, #16] 8001ffc: f003 0301 and.w r3, r3, #1 8002000: 2b00 cmp r3, #0 8002002: d00c beq.n 800201e { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 8002004: 6a7b ldr r3, [r7, #36] ; 0x24 8002006: 015a lsls r2, r3, #5 8002008: 69fb ldr r3, [r7, #28] 800200a: 4413 add r3, r2 800200c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002010: 461a mov r2, r3 8002012: 2301 movs r3, #1 8002014: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 8002016: 6a79 ldr r1, [r7, #36] ; 0x24 8002018: 6878 ldr r0, [r7, #4] 800201a: f000 fdd1 bl 8002bc0 } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 800201e: 693b ldr r3, [r7, #16] 8002020: f003 0308 and.w r3, r3, #8 8002024: 2b00 cmp r3, #0 8002026: d00c beq.n 8002042 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 8002028: 6a7b ldr r3, [r7, #36] ; 0x24 800202a: 015a lsls r2, r3, #5 800202c: 69fb ldr r3, [r7, #28] 800202e: 4413 add r3, r2 8002030: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002034: 461a mov r2, r3 8002036: 2308 movs r3, #8 8002038: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 800203a: 6a79 ldr r1, [r7, #36] ; 0x24 800203c: 6878 ldr r0, [r7, #4] 800203e: f000 fecb bl 8002dd8 } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 8002042: 693b ldr r3, [r7, #16] 8002044: f003 0310 and.w r3, r3, #16 8002048: 2b00 cmp r3, #0 800204a: d008 beq.n 800205e { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 800204c: 6a7b ldr r3, [r7, #36] ; 0x24 800204e: 015a lsls r2, r3, #5 8002050: 69fb ldr r3, [r7, #28] 8002052: 4413 add r3, r2 8002054: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002058: 461a mov r2, r3 800205a: 2310 movs r3, #16 800205c: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 800205e: 693b ldr r3, [r7, #16] 8002060: f003 0320 and.w r3, r3, #32 8002064: 2b00 cmp r3, #0 8002066: d008 beq.n 800207a { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8002068: 6a7b ldr r3, [r7, #36] ; 0x24 800206a: 015a lsls r2, r3, #5 800206c: 69fb ldr r3, [r7, #28] 800206e: 4413 add r3, r2 8002070: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002074: 461a mov r2, r3 8002076: 2320 movs r3, #32 8002078: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 800207a: 693b ldr r3, [r7, #16] 800207c: f403 5300 and.w r3, r3, #8192 ; 0x2000 8002080: 2b00 cmp r3, #0 8002082: d009 beq.n 8002098 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 8002084: 6a7b ldr r3, [r7, #36] ; 0x24 8002086: 015a lsls r2, r3, #5 8002088: 69fb ldr r3, [r7, #28] 800208a: 4413 add r3, r2 800208c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002090: 461a mov r2, r3 8002092: f44f 5300 mov.w r3, #8192 ; 0x2000 8002096: 6093 str r3, [r2, #8] } } epnum++; 8002098: 6a7b ldr r3, [r7, #36] ; 0x24 800209a: 3301 adds r3, #1 800209c: 627b str r3, [r7, #36] ; 0x24 ep_intr >>= 1U; 800209e: 6abb ldr r3, [r7, #40] ; 0x28 80020a0: 085b lsrs r3, r3, #1 80020a2: 62bb str r3, [r7, #40] ; 0x28 while (ep_intr != 0U) 80020a4: 6abb ldr r3, [r7, #40] ; 0x28 80020a6: 2b00 cmp r3, #0 80020a8: d199 bne.n 8001fde } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 80020aa: 687b ldr r3, [r7, #4] 80020ac: 681b ldr r3, [r3, #0] 80020ae: 4618 mov r0, r3 80020b0: f005 f88e bl 80071d0 80020b4: 4603 mov r3, r0 80020b6: f403 2380 and.w r3, r3, #262144 ; 0x40000 80020ba: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 80020be: f040 80c4 bne.w 800224a { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 80020c2: 687b ldr r3, [r7, #4] 80020c4: 681b ldr r3, [r3, #0] 80020c6: 4618 mov r0, r3 80020c8: f005 f8af bl 800722a 80020cc: 62b8 str r0, [r7, #40] ; 0x28 epnum = 0U; 80020ce: 2300 movs r3, #0 80020d0: 627b str r3, [r7, #36] ; 0x24 while (ep_intr != 0U) 80020d2: e0b6 b.n 8002242 { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 80020d4: 6abb ldr r3, [r7, #40] ; 0x28 80020d6: f003 0301 and.w r3, r3, #1 80020da: 2b00 cmp r3, #0 80020dc: f000 80ab beq.w 8002236 { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 80020e0: 687b ldr r3, [r7, #4] 80020e2: 681b ldr r3, [r3, #0] 80020e4: 6a7a ldr r2, [r7, #36] ; 0x24 80020e6: b2d2 uxtb r2, r2 80020e8: 4611 mov r1, r2 80020ea: 4618 mov r0, r3 80020ec: f005 f8d5 bl 800729a 80020f0: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 80020f2: 693b ldr r3, [r7, #16] 80020f4: f003 0301 and.w r3, r3, #1 80020f8: 2b00 cmp r3, #0 80020fa: d057 beq.n 80021ac { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 80020fc: 6a7b ldr r3, [r7, #36] ; 0x24 80020fe: f003 030f and.w r3, r3, #15 8002102: 2201 movs r2, #1 8002104: fa02 f303 lsl.w r3, r2, r3 8002108: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 800210a: 69fb ldr r3, [r7, #28] 800210c: f503 6300 add.w r3, r3, #2048 ; 0x800 8002110: 6b5a ldr r2, [r3, #52] ; 0x34 8002112: 68fb ldr r3, [r7, #12] 8002114: 43db mvns r3, r3 8002116: 69f9 ldr r1, [r7, #28] 8002118: f501 6100 add.w r1, r1, #2048 ; 0x800 800211c: 4013 ands r3, r2 800211e: 634b str r3, [r1, #52] ; 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 8002120: 6a7b ldr r3, [r7, #36] ; 0x24 8002122: 015a lsls r2, r3, #5 8002124: 69fb ldr r3, [r7, #28] 8002126: 4413 add r3, r2 8002128: f503 6310 add.w r3, r3, #2304 ; 0x900 800212c: 461a mov r2, r3 800212e: 2301 movs r3, #1 8002130: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 8002132: 687b ldr r3, [r7, #4] 8002134: 691b ldr r3, [r3, #16] 8002136: 2b01 cmp r3, #1 8002138: d132 bne.n 80021a0 { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 800213a: 6879 ldr r1, [r7, #4] 800213c: 6a7a ldr r2, [r7, #36] ; 0x24 800213e: 4613 mov r3, r2 8002140: 00db lsls r3, r3, #3 8002142: 1a9b subs r3, r3, r2 8002144: 009b lsls r3, r3, #2 8002146: 440b add r3, r1 8002148: 3348 adds r3, #72 ; 0x48 800214a: 6819 ldr r1, [r3, #0] 800214c: 6878 ldr r0, [r7, #4] 800214e: 6a7a ldr r2, [r7, #36] ; 0x24 8002150: 4613 mov r3, r2 8002152: 00db lsls r3, r3, #3 8002154: 1a9b subs r3, r3, r2 8002156: 009b lsls r3, r3, #2 8002158: 4403 add r3, r0 800215a: 3344 adds r3, #68 ; 0x44 800215c: 681b ldr r3, [r3, #0] 800215e: 4419 add r1, r3 8002160: 6878 ldr r0, [r7, #4] 8002162: 6a7a ldr r2, [r7, #36] ; 0x24 8002164: 4613 mov r3, r2 8002166: 00db lsls r3, r3, #3 8002168: 1a9b subs r3, r3, r2 800216a: 009b lsls r3, r3, #2 800216c: 4403 add r3, r0 800216e: 3348 adds r3, #72 ; 0x48 8002170: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 8002172: 6a7b ldr r3, [r7, #36] ; 0x24 8002174: 2b00 cmp r3, #0 8002176: d113 bne.n 80021a0 8002178: 6879 ldr r1, [r7, #4] 800217a: 6a7a ldr r2, [r7, #36] ; 0x24 800217c: 4613 mov r3, r2 800217e: 00db lsls r3, r3, #3 8002180: 1a9b subs r3, r3, r2 8002182: 009b lsls r3, r3, #2 8002184: 440b add r3, r1 8002186: 3350 adds r3, #80 ; 0x50 8002188: 681b ldr r3, [r3, #0] 800218a: 2b00 cmp r3, #0 800218c: d108 bne.n 80021a0 { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 800218e: 687b ldr r3, [r7, #4] 8002190: 6818 ldr r0, [r3, #0] 8002192: 687b ldr r3, [r7, #4] 8002194: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002198: 461a mov r2, r3 800219a: 2101 movs r1, #1 800219c: f005 f8de bl 800735c } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 80021a0: 6a7b ldr r3, [r7, #36] ; 0x24 80021a2: b2db uxtb r3, r3 80021a4: 4619 mov r1, r3 80021a6: 6878 ldr r0, [r7, #4] 80021a8: f007 f89f bl 80092ea #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 80021ac: 693b ldr r3, [r7, #16] 80021ae: f003 0308 and.w r3, r3, #8 80021b2: 2b00 cmp r3, #0 80021b4: d008 beq.n 80021c8 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 80021b6: 6a7b ldr r3, [r7, #36] ; 0x24 80021b8: 015a lsls r2, r3, #5 80021ba: 69fb ldr r3, [r7, #28] 80021bc: 4413 add r3, r2 80021be: f503 6310 add.w r3, r3, #2304 ; 0x900 80021c2: 461a mov r2, r3 80021c4: 2308 movs r3, #8 80021c6: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 80021c8: 693b ldr r3, [r7, #16] 80021ca: f003 0310 and.w r3, r3, #16 80021ce: 2b00 cmp r3, #0 80021d0: d008 beq.n 80021e4 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 80021d2: 6a7b ldr r3, [r7, #36] ; 0x24 80021d4: 015a lsls r2, r3, #5 80021d6: 69fb ldr r3, [r7, #28] 80021d8: 4413 add r3, r2 80021da: f503 6310 add.w r3, r3, #2304 ; 0x900 80021de: 461a mov r2, r3 80021e0: 2310 movs r3, #16 80021e2: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 80021e4: 693b ldr r3, [r7, #16] 80021e6: f003 0340 and.w r3, r3, #64 ; 0x40 80021ea: 2b00 cmp r3, #0 80021ec: d008 beq.n 8002200 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 80021ee: 6a7b ldr r3, [r7, #36] ; 0x24 80021f0: 015a lsls r2, r3, #5 80021f2: 69fb ldr r3, [r7, #28] 80021f4: 4413 add r3, r2 80021f6: f503 6310 add.w r3, r3, #2304 ; 0x900 80021fa: 461a mov r2, r3 80021fc: 2340 movs r3, #64 ; 0x40 80021fe: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 8002200: 693b ldr r3, [r7, #16] 8002202: f003 0302 and.w r3, r3, #2 8002206: 2b00 cmp r3, #0 8002208: d00c beq.n 8002224 { (void)USB_FlushTxFifo(USBx, epnum); 800220a: 6a79 ldr r1, [r7, #36] ; 0x24 800220c: 6a38 ldr r0, [r7, #32] 800220e: f004 f867 bl 80062e0 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 8002212: 6a7b ldr r3, [r7, #36] ; 0x24 8002214: 015a lsls r2, r3, #5 8002216: 69fb ldr r3, [r7, #28] 8002218: 4413 add r3, r2 800221a: f503 6310 add.w r3, r3, #2304 ; 0x900 800221e: 461a mov r2, r3 8002220: 2302 movs r3, #2 8002222: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 8002224: 693b ldr r3, [r7, #16] 8002226: f003 0380 and.w r3, r3, #128 ; 0x80 800222a: 2b00 cmp r3, #0 800222c: d003 beq.n 8002236 { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 800222e: 6a79 ldr r1, [r7, #36] ; 0x24 8002230: 6878 ldr r0, [r7, #4] 8002232: f000 fc38 bl 8002aa6 } } epnum++; 8002236: 6a7b ldr r3, [r7, #36] ; 0x24 8002238: 3301 adds r3, #1 800223a: 627b str r3, [r7, #36] ; 0x24 ep_intr >>= 1U; 800223c: 6abb ldr r3, [r7, #40] ; 0x28 800223e: 085b lsrs r3, r3, #1 8002240: 62bb str r3, [r7, #40] ; 0x28 while (ep_intr != 0U) 8002242: 6abb ldr r3, [r7, #40] ; 0x28 8002244: 2b00 cmp r3, #0 8002246: f47f af45 bne.w 80020d4 } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 800224a: 687b ldr r3, [r7, #4] 800224c: 681b ldr r3, [r3, #0] 800224e: 4618 mov r0, r3 8002250: f004 ffbe bl 80071d0 8002254: 4603 mov r3, r0 8002256: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 800225a: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 800225e: d122 bne.n 80022a6 { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 8002260: 69fb ldr r3, [r7, #28] 8002262: f503 6300 add.w r3, r3, #2048 ; 0x800 8002266: 685b ldr r3, [r3, #4] 8002268: 69fa ldr r2, [r7, #28] 800226a: f502 6200 add.w r2, r2, #2048 ; 0x800 800226e: f023 0301 bic.w r3, r3, #1 8002272: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 8002274: 687b ldr r3, [r7, #4] 8002276: f893 33f4 ldrb.w r3, [r3, #1012] ; 0x3f4 800227a: 2b01 cmp r3, #1 800227c: d108 bne.n 8002290 { hpcd->LPM_State = LPM_L0; 800227e: 687b ldr r3, [r7, #4] 8002280: 2200 movs r2, #0 8002282: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 8002286: 2100 movs r1, #0 8002288: 6878 ldr r0, [r7, #4] 800228a: f000 fe67 bl 8002f5c 800228e: e002 b.n 8002296 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 8002290: 6878 ldr r0, [r7, #4] 8002292: f007 f8a1 bl 80093d8 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 8002296: 687b ldr r3, [r7, #4] 8002298: 681b ldr r3, [r3, #0] 800229a: 695a ldr r2, [r3, #20] 800229c: 687b ldr r3, [r7, #4] 800229e: 681b ldr r3, [r3, #0] 80022a0: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000 80022a4: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 80022a6: 687b ldr r3, [r7, #4] 80022a8: 681b ldr r3, [r3, #0] 80022aa: 4618 mov r0, r3 80022ac: f004 ff90 bl 80071d0 80022b0: 4603 mov r3, r0 80022b2: f403 6300 and.w r3, r3, #2048 ; 0x800 80022b6: f5b3 6f00 cmp.w r3, #2048 ; 0x800 80022ba: d112 bne.n 80022e2 { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 80022bc: 69fb ldr r3, [r7, #28] 80022be: f503 6300 add.w r3, r3, #2048 ; 0x800 80022c2: 689b ldr r3, [r3, #8] 80022c4: f003 0301 and.w r3, r3, #1 80022c8: 2b01 cmp r3, #1 80022ca: d102 bne.n 80022d2 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 80022cc: 6878 ldr r0, [r7, #4] 80022ce: f007 f85d bl 800938c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 80022d2: 687b ldr r3, [r7, #4] 80022d4: 681b ldr r3, [r3, #0] 80022d6: 695a ldr r2, [r3, #20] 80022d8: 687b ldr r3, [r7, #4] 80022da: 681b ldr r3, [r3, #0] 80022dc: f402 6200 and.w r2, r2, #2048 ; 0x800 80022e0: 615a str r2, [r3, #20] } /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 80022e2: 687b ldr r3, [r7, #4] 80022e4: 681b ldr r3, [r3, #0] 80022e6: 4618 mov r0, r3 80022e8: f004 ff72 bl 80071d0 80022ec: 4603 mov r3, r0 80022ee: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80022f2: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 80022f6: d121 bne.n 800233c { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 80022f8: 687b ldr r3, [r7, #4] 80022fa: 681b ldr r3, [r3, #0] 80022fc: 695a ldr r2, [r3, #20] 80022fe: 687b ldr r3, [r7, #4] 8002300: 681b ldr r3, [r3, #0] 8002302: f002 6200 and.w r2, r2, #134217728 ; 0x8000000 8002306: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 8002308: 687b ldr r3, [r7, #4] 800230a: f893 33f4 ldrb.w r3, [r3, #1012] ; 0x3f4 800230e: 2b00 cmp r3, #0 8002310: d111 bne.n 8002336 { hpcd->LPM_State = LPM_L1; 8002312: 687b ldr r3, [r7, #4] 8002314: 2201 movs r2, #1 8002316: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4 hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 800231a: 687b ldr r3, [r7, #4] 800231c: 681b ldr r3, [r3, #0] 800231e: 6d5b ldr r3, [r3, #84] ; 0x54 8002320: 089b lsrs r3, r3, #2 8002322: f003 020f and.w r2, r3, #15 8002326: 687b ldr r3, [r7, #4] 8002328: f8c3 23f8 str.w r2, [r3, #1016] ; 0x3f8 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 800232c: 2101 movs r1, #1 800232e: 6878 ldr r0, [r7, #4] 8002330: f000 fe14 bl 8002f5c 8002334: e002 b.n 800233c else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8002336: 6878 ldr r0, [r7, #4] 8002338: f007 f828 bl 800938c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 800233c: 687b ldr r3, [r7, #4] 800233e: 681b ldr r3, [r3, #0] 8002340: 4618 mov r0, r3 8002342: f004 ff45 bl 80071d0 8002346: 4603 mov r3, r0 8002348: f403 5380 and.w r3, r3, #4096 ; 0x1000 800234c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8002350: f040 80b7 bne.w 80024c2 { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 8002354: 69fb ldr r3, [r7, #28] 8002356: f503 6300 add.w r3, r3, #2048 ; 0x800 800235a: 685b ldr r3, [r3, #4] 800235c: 69fa ldr r2, [r7, #28] 800235e: f502 6200 add.w r2, r2, #2048 ; 0x800 8002362: f023 0301 bic.w r3, r3, #1 8002366: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 8002368: 687b ldr r3, [r7, #4] 800236a: 681b ldr r3, [r3, #0] 800236c: 2110 movs r1, #16 800236e: 4618 mov r0, r3 8002370: f003 ffb6 bl 80062e0 for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002374: 2300 movs r3, #0 8002376: 62fb str r3, [r7, #44] ; 0x2c 8002378: e046 b.n 8002408 { USBx_INEP(i)->DIEPINT = 0xFB7FU; 800237a: 6afb ldr r3, [r7, #44] ; 0x2c 800237c: 015a lsls r2, r3, #5 800237e: 69fb ldr r3, [r7, #28] 8002380: 4413 add r3, r2 8002382: f503 6310 add.w r3, r3, #2304 ; 0x900 8002386: 461a mov r2, r3 8002388: f64f 337f movw r3, #64383 ; 0xfb7f 800238c: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 800238e: 6afb ldr r3, [r7, #44] ; 0x2c 8002390: 015a lsls r2, r3, #5 8002392: 69fb ldr r3, [r7, #28] 8002394: 4413 add r3, r2 8002396: f503 6310 add.w r3, r3, #2304 ; 0x900 800239a: 681b ldr r3, [r3, #0] 800239c: 6afa ldr r2, [r7, #44] ; 0x2c 800239e: 0151 lsls r1, r2, #5 80023a0: 69fa ldr r2, [r7, #28] 80023a2: 440a add r2, r1 80023a4: f502 6210 add.w r2, r2, #2304 ; 0x900 80023a8: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 80023ac: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 80023ae: 6afb ldr r3, [r7, #44] ; 0x2c 80023b0: 015a lsls r2, r3, #5 80023b2: 69fb ldr r3, [r7, #28] 80023b4: 4413 add r3, r2 80023b6: f503 6330 add.w r3, r3, #2816 ; 0xb00 80023ba: 461a mov r2, r3 80023bc: f64f 337f movw r3, #64383 ; 0xfb7f 80023c0: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 80023c2: 6afb ldr r3, [r7, #44] ; 0x2c 80023c4: 015a lsls r2, r3, #5 80023c6: 69fb ldr r3, [r7, #28] 80023c8: 4413 add r3, r2 80023ca: f503 6330 add.w r3, r3, #2816 ; 0xb00 80023ce: 681b ldr r3, [r3, #0] 80023d0: 6afa ldr r2, [r7, #44] ; 0x2c 80023d2: 0151 lsls r1, r2, #5 80023d4: 69fa ldr r2, [r7, #28] 80023d6: 440a add r2, r1 80023d8: f502 6230 add.w r2, r2, #2816 ; 0xb00 80023dc: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 80023e0: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 80023e2: 6afb ldr r3, [r7, #44] ; 0x2c 80023e4: 015a lsls r2, r3, #5 80023e6: 69fb ldr r3, [r7, #28] 80023e8: 4413 add r3, r2 80023ea: f503 6330 add.w r3, r3, #2816 ; 0xb00 80023ee: 681b ldr r3, [r3, #0] 80023f0: 6afa ldr r2, [r7, #44] ; 0x2c 80023f2: 0151 lsls r1, r2, #5 80023f4: 69fa ldr r2, [r7, #28] 80023f6: 440a add r2, r1 80023f8: f502 6230 add.w r2, r2, #2816 ; 0xb00 80023fc: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 8002400: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002402: 6afb ldr r3, [r7, #44] ; 0x2c 8002404: 3301 adds r3, #1 8002406: 62fb str r3, [r7, #44] ; 0x2c 8002408: 687b ldr r3, [r7, #4] 800240a: 685b ldr r3, [r3, #4] 800240c: 6afa ldr r2, [r7, #44] ; 0x2c 800240e: 429a cmp r2, r3 8002410: d3b3 bcc.n 800237a } USBx_DEVICE->DAINTMSK |= 0x10001U; 8002412: 69fb ldr r3, [r7, #28] 8002414: f503 6300 add.w r3, r3, #2048 ; 0x800 8002418: 69db ldr r3, [r3, #28] 800241a: 69fa ldr r2, [r7, #28] 800241c: f502 6200 add.w r2, r2, #2048 ; 0x800 8002420: f043 1301 orr.w r3, r3, #65537 ; 0x10001 8002424: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 8002426: 687b ldr r3, [r7, #4] 8002428: 6b1b ldr r3, [r3, #48] ; 0x30 800242a: 2b00 cmp r3, #0 800242c: d016 beq.n 800245c { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 800242e: 69fb ldr r3, [r7, #28] 8002430: f503 6300 add.w r3, r3, #2048 ; 0x800 8002434: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8002438: 69fa ldr r2, [r7, #28] 800243a: f502 6200 add.w r2, r2, #2048 ; 0x800 800243e: f043 030b orr.w r3, r3, #11 8002442: f8c2 3084 str.w r3, [r2, #132] ; 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 8002446: 69fb ldr r3, [r7, #28] 8002448: f503 6300 add.w r3, r3, #2048 ; 0x800 800244c: 6c5b ldr r3, [r3, #68] ; 0x44 800244e: 69fa ldr r2, [r7, #28] 8002450: f502 6200 add.w r2, r2, #2048 ; 0x800 8002454: f043 030b orr.w r3, r3, #11 8002458: 6453 str r3, [r2, #68] ; 0x44 800245a: e015 b.n 8002488 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 800245c: 69fb ldr r3, [r7, #28] 800245e: f503 6300 add.w r3, r3, #2048 ; 0x800 8002462: 695a ldr r2, [r3, #20] 8002464: 69fb ldr r3, [r7, #28] 8002466: f503 6300 add.w r3, r3, #2048 ; 0x800 800246a: 4619 mov r1, r3 800246c: f242 032b movw r3, #8235 ; 0x202b 8002470: 4313 orrs r3, r2 8002472: 614b str r3, [r1, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 8002474: 69fb ldr r3, [r7, #28] 8002476: f503 6300 add.w r3, r3, #2048 ; 0x800 800247a: 691b ldr r3, [r3, #16] 800247c: 69fa ldr r2, [r7, #28] 800247e: f502 6200 add.w r2, r2, #2048 ; 0x800 8002482: f043 030b orr.w r3, r3, #11 8002486: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 8002488: 69fb ldr r3, [r7, #28] 800248a: f503 6300 add.w r3, r3, #2048 ; 0x800 800248e: 681b ldr r3, [r3, #0] 8002490: 69fa ldr r2, [r7, #28] 8002492: f502 6200 add.w r2, r2, #2048 ; 0x800 8002496: f423 63fe bic.w r3, r3, #2032 ; 0x7f0 800249a: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 800249c: 687b ldr r3, [r7, #4] 800249e: 6818 ldr r0, [r3, #0] 80024a0: 687b ldr r3, [r7, #4] 80024a2: 691b ldr r3, [r3, #16] 80024a4: b2d9 uxtb r1, r3 (uint8_t *)hpcd->Setup); 80024a6: 687b ldr r3, [r7, #4] 80024a8: f503 7371 add.w r3, r3, #964 ; 0x3c4 (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 80024ac: 461a mov r2, r3 80024ae: f004 ff55 bl 800735c __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 80024b2: 687b ldr r3, [r7, #4] 80024b4: 681b ldr r3, [r3, #0] 80024b6: 695a ldr r2, [r3, #20] 80024b8: 687b ldr r3, [r7, #4] 80024ba: 681b ldr r3, [r3, #0] 80024bc: f402 5280 and.w r2, r2, #4096 ; 0x1000 80024c0: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 80024c2: 687b ldr r3, [r7, #4] 80024c4: 681b ldr r3, [r3, #0] 80024c6: 4618 mov r0, r3 80024c8: f004 fe82 bl 80071d0 80024cc: 4603 mov r3, r0 80024ce: f403 5300 and.w r3, r3, #8192 ; 0x2000 80024d2: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80024d6: d124 bne.n 8002522 { (void)USB_ActivateSetup(hpcd->Instance); 80024d8: 687b ldr r3, [r7, #4] 80024da: 681b ldr r3, [r3, #0] 80024dc: 4618 mov r0, r3 80024de: f004 ff19 bl 8007314 hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 80024e2: 687b ldr r3, [r7, #4] 80024e4: 681b ldr r3, [r3, #0] 80024e6: 4618 mov r0, r3 80024e8: f003 ff73 bl 80063d2 80024ec: 4603 mov r3, r0 80024ee: 461a mov r2, r3 80024f0: 687b ldr r3, [r7, #4] 80024f2: 60da str r2, [r3, #12] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 80024f4: 687b ldr r3, [r7, #4] 80024f6: 681c ldr r4, [r3, #0] 80024f8: f001 fc62 bl 8003dc0 80024fc: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 80024fe: 687b ldr r3, [r7, #4] 8002500: 68db ldr r3, [r3, #12] (void)USB_SetTurnaroundTime(hpcd->Instance, 8002502: b2db uxtb r3, r3 8002504: 461a mov r2, r3 8002506: 4620 mov r0, r4 8002508: f003 fc7c bl 8005e04 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 800250c: 6878 ldr r0, [r7, #4] 800250e: f006 ff14 bl 800933a #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 8002512: 687b ldr r3, [r7, #4] 8002514: 681b ldr r3, [r3, #0] 8002516: 695a ldr r2, [r3, #20] 8002518: 687b ldr r3, [r7, #4] 800251a: 681b ldr r3, [r3, #0] 800251c: f402 5200 and.w r2, r2, #8192 ; 0x2000 8002520: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 8002522: 687b ldr r3, [r7, #4] 8002524: 681b ldr r3, [r3, #0] 8002526: 4618 mov r0, r3 8002528: f004 fe52 bl 80071d0 800252c: 4603 mov r3, r0 800252e: f003 0308 and.w r3, r3, #8 8002532: 2b08 cmp r3, #8 8002534: d10a bne.n 800254c { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 8002536: 6878 ldr r0, [r7, #4] 8002538: f006 fef1 bl 800931e #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 800253c: 687b ldr r3, [r7, #4] 800253e: 681b ldr r3, [r3, #0] 8002540: 695a ldr r2, [r3, #20] 8002542: 687b ldr r3, [r7, #4] 8002544: 681b ldr r3, [r3, #0] 8002546: f002 0208 and.w r2, r2, #8 800254a: 615a str r2, [r3, #20] } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 800254c: 687b ldr r3, [r7, #4] 800254e: 681b ldr r3, [r3, #0] 8002550: 4618 mov r0, r3 8002552: f004 fe3d bl 80071d0 8002556: 4603 mov r3, r0 8002558: f403 1380 and.w r3, r3, #1048576 ; 0x100000 800255c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8002560: d10f bne.n 8002582 { /* Keep application checking the corresponding Iso IN endpoint causing the incomplete Interrupt */ epnum = 0U; 8002562: 2300 movs r3, #0 8002564: 627b str r3, [r7, #36] ; 0x24 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 8002566: 6a7b ldr r3, [r7, #36] ; 0x24 8002568: b2db uxtb r3, r3 800256a: 4619 mov r1, r3 800256c: 6878 ldr r0, [r7, #4] 800256e: f006 ff53 bl 8009418 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 8002572: 687b ldr r3, [r7, #4] 8002574: 681b ldr r3, [r3, #0] 8002576: 695a ldr r2, [r3, #20] 8002578: 687b ldr r3, [r7, #4] 800257a: 681b ldr r3, [r3, #0] 800257c: f402 1280 and.w r2, r2, #1048576 ; 0x100000 8002580: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 8002582: 687b ldr r3, [r7, #4] 8002584: 681b ldr r3, [r3, #0] 8002586: 4618 mov r0, r3 8002588: f004 fe22 bl 80071d0 800258c: 4603 mov r3, r0 800258e: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8002592: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8002596: d10f bne.n 80025b8 { /* Keep application checking the corresponding Iso OUT endpoint causing the incomplete Interrupt */ epnum = 0U; 8002598: 2300 movs r3, #0 800259a: 627b str r3, [r7, #36] ; 0x24 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 800259c: 6a7b ldr r3, [r7, #36] ; 0x24 800259e: b2db uxtb r3, r3 80025a0: 4619 mov r1, r3 80025a2: 6878 ldr r0, [r7, #4] 80025a4: f006 ff26 bl 80093f4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 80025a8: 687b ldr r3, [r7, #4] 80025aa: 681b ldr r3, [r3, #0] 80025ac: 695a ldr r2, [r3, #20] 80025ae: 687b ldr r3, [r7, #4] 80025b0: 681b ldr r3, [r3, #0] 80025b2: f402 1200 and.w r2, r2, #2097152 ; 0x200000 80025b6: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 80025b8: 687b ldr r3, [r7, #4] 80025ba: 681b ldr r3, [r3, #0] 80025bc: 4618 mov r0, r3 80025be: f004 fe07 bl 80071d0 80025c2: 4603 mov r3, r0 80025c4: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 80025c8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80025cc: d10a bne.n 80025e4 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 80025ce: 6878 ldr r0, [r7, #4] 80025d0: f006 ff34 bl 800943c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 80025d4: 687b ldr r3, [r7, #4] 80025d6: 681b ldr r3, [r3, #0] 80025d8: 695a ldr r2, [r3, #20] 80025da: 687b ldr r3, [r7, #4] 80025dc: 681b ldr r3, [r3, #0] 80025de: f002 4280 and.w r2, r2, #1073741824 ; 0x40000000 80025e2: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 80025e4: 687b ldr r3, [r7, #4] 80025e6: 681b ldr r3, [r3, #0] 80025e8: 4618 mov r0, r3 80025ea: f004 fdf1 bl 80071d0 80025ee: 4603 mov r3, r0 80025f0: f003 0304 and.w r3, r3, #4 80025f4: 2b04 cmp r3, #4 80025f6: d115 bne.n 8002624 { temp = hpcd->Instance->GOTGINT; 80025f8: 687b ldr r3, [r7, #4] 80025fa: 681b ldr r3, [r3, #0] 80025fc: 685b ldr r3, [r3, #4] 80025fe: 61bb str r3, [r7, #24] if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 8002600: 69bb ldr r3, [r7, #24] 8002602: f003 0304 and.w r3, r3, #4 8002606: 2b00 cmp r3, #0 8002608: d002 beq.n 8002610 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 800260a: 6878 ldr r0, [r7, #4] 800260c: f006 ff24 bl 8009458 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= temp; 8002610: 687b ldr r3, [r7, #4] 8002612: 681b ldr r3, [r3, #0] 8002614: 6859 ldr r1, [r3, #4] 8002616: 687b ldr r3, [r7, #4] 8002618: 681b ldr r3, [r3, #0] 800261a: 69ba ldr r2, [r7, #24] 800261c: 430a orrs r2, r1 800261e: 605a str r2, [r3, #4] 8002620: e000 b.n 8002624 return; 8002622: bf00 nop } } } 8002624: 3734 adds r7, #52 ; 0x34 8002626: 46bd mov sp, r7 8002628: bd90 pop {r4, r7, pc} 0800262a : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 800262a: b580 push {r7, lr} 800262c: b082 sub sp, #8 800262e: af00 add r7, sp, #0 8002630: 6078 str r0, [r7, #4] 8002632: 460b mov r3, r1 8002634: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 8002636: 687b ldr r3, [r7, #4] 8002638: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 800263c: 2b01 cmp r3, #1 800263e: d101 bne.n 8002644 8002640: 2302 movs r3, #2 8002642: e013 b.n 800266c 8002644: 687b ldr r3, [r7, #4] 8002646: 2201 movs r2, #1 8002648: f883 23bc strb.w r2, [r3, #956] ; 0x3bc hpcd->USB_Address = address; 800264c: 687b ldr r3, [r7, #4] 800264e: 78fa ldrb r2, [r7, #3] 8002650: f883 2038 strb.w r2, [r3, #56] ; 0x38 (void)USB_SetDevAddress(hpcd->Instance, address); 8002654: 687b ldr r3, [r7, #4] 8002656: 681b ldr r3, [r3, #0] 8002658: 78fa ldrb r2, [r7, #3] 800265a: 4611 mov r1, r2 800265c: 4618 mov r0, r3 800265e: f004 fd4f bl 8007100 __HAL_UNLOCK(hpcd); 8002662: 687b ldr r3, [r7, #4] 8002664: 2200 movs r2, #0 8002666: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 800266a: 2300 movs r3, #0 } 800266c: 4618 mov r0, r3 800266e: 3708 adds r7, #8 8002670: 46bd mov sp, r7 8002672: bd80 pop {r7, pc} 08002674 : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 8002674: b580 push {r7, lr} 8002676: b084 sub sp, #16 8002678: af00 add r7, sp, #0 800267a: 6078 str r0, [r7, #4] 800267c: 4608 mov r0, r1 800267e: 4611 mov r1, r2 8002680: 461a mov r2, r3 8002682: 4603 mov r3, r0 8002684: 70fb strb r3, [r7, #3] 8002686: 460b mov r3, r1 8002688: 803b strh r3, [r7, #0] 800268a: 4613 mov r3, r2 800268c: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 800268e: 2300 movs r3, #0 8002690: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8002692: f997 3003 ldrsb.w r3, [r7, #3] 8002696: 2b00 cmp r3, #0 8002698: da0f bge.n 80026ba { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800269a: 78fb ldrb r3, [r7, #3] 800269c: f003 020f and.w r2, r3, #15 80026a0: 4613 mov r3, r2 80026a2: 00db lsls r3, r3, #3 80026a4: 1a9b subs r3, r3, r2 80026a6: 009b lsls r3, r3, #2 80026a8: 3338 adds r3, #56 ; 0x38 80026aa: 687a ldr r2, [r7, #4] 80026ac: 4413 add r3, r2 80026ae: 3304 adds r3, #4 80026b0: 60fb str r3, [r7, #12] ep->is_in = 1U; 80026b2: 68fb ldr r3, [r7, #12] 80026b4: 2201 movs r2, #1 80026b6: 705a strb r2, [r3, #1] 80026b8: e00f b.n 80026da } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80026ba: 78fb ldrb r3, [r7, #3] 80026bc: f003 020f and.w r2, r3, #15 80026c0: 4613 mov r3, r2 80026c2: 00db lsls r3, r3, #3 80026c4: 1a9b subs r3, r3, r2 80026c6: 009b lsls r3, r3, #2 80026c8: f503 73fc add.w r3, r3, #504 ; 0x1f8 80026cc: 687a ldr r2, [r7, #4] 80026ce: 4413 add r3, r2 80026d0: 3304 adds r3, #4 80026d2: 60fb str r3, [r7, #12] ep->is_in = 0U; 80026d4: 68fb ldr r3, [r7, #12] 80026d6: 2200 movs r2, #0 80026d8: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 80026da: 78fb ldrb r3, [r7, #3] 80026dc: f003 030f and.w r3, r3, #15 80026e0: b2da uxtb r2, r3 80026e2: 68fb ldr r3, [r7, #12] 80026e4: 701a strb r2, [r3, #0] ep->maxpacket = ep_mps; 80026e6: 883a ldrh r2, [r7, #0] 80026e8: 68fb ldr r3, [r7, #12] 80026ea: 609a str r2, [r3, #8] ep->type = ep_type; 80026ec: 68fb ldr r3, [r7, #12] 80026ee: 78ba ldrb r2, [r7, #2] 80026f0: 70da strb r2, [r3, #3] if (ep->is_in != 0U) 80026f2: 68fb ldr r3, [r7, #12] 80026f4: 785b ldrb r3, [r3, #1] 80026f6: 2b00 cmp r3, #0 80026f8: d004 beq.n 8002704 { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 80026fa: 68fb ldr r3, [r7, #12] 80026fc: 781b ldrb r3, [r3, #0] 80026fe: b29a uxth r2, r3 8002700: 68fb ldr r3, [r7, #12] 8002702: 80da strh r2, [r3, #6] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 8002704: 78bb ldrb r3, [r7, #2] 8002706: 2b02 cmp r3, #2 8002708: d102 bne.n 8002710 { ep->data_pid_start = 0U; 800270a: 68fb ldr r3, [r7, #12] 800270c: 2200 movs r2, #0 800270e: 711a strb r2, [r3, #4] } __HAL_LOCK(hpcd); 8002710: 687b ldr r3, [r7, #4] 8002712: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 8002716: 2b01 cmp r3, #1 8002718: d101 bne.n 800271e 800271a: 2302 movs r3, #2 800271c: e00e b.n 800273c 800271e: 687b ldr r3, [r7, #4] 8002720: 2201 movs r2, #1 8002722: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_ActivateEndpoint(hpcd->Instance, ep); 8002726: 687b ldr r3, [r7, #4] 8002728: 681b ldr r3, [r3, #0] 800272a: 68f9 ldr r1, [r7, #12] 800272c: 4618 mov r0, r3 800272e: f003 fe75 bl 800641c __HAL_UNLOCK(hpcd); 8002732: 687b ldr r3, [r7, #4] 8002734: 2200 movs r2, #0 8002736: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return ret; 800273a: 7afb ldrb r3, [r7, #11] } 800273c: 4618 mov r0, r3 800273e: 3710 adds r7, #16 8002740: 46bd mov sp, r7 8002742: bd80 pop {r7, pc} 08002744 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8002744: b580 push {r7, lr} 8002746: b084 sub sp, #16 8002748: af00 add r7, sp, #0 800274a: 6078 str r0, [r7, #4] 800274c: 460b mov r3, r1 800274e: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8002750: f997 3003 ldrsb.w r3, [r7, #3] 8002754: 2b00 cmp r3, #0 8002756: da0f bge.n 8002778 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8002758: 78fb ldrb r3, [r7, #3] 800275a: f003 020f and.w r2, r3, #15 800275e: 4613 mov r3, r2 8002760: 00db lsls r3, r3, #3 8002762: 1a9b subs r3, r3, r2 8002764: 009b lsls r3, r3, #2 8002766: 3338 adds r3, #56 ; 0x38 8002768: 687a ldr r2, [r7, #4] 800276a: 4413 add r3, r2 800276c: 3304 adds r3, #4 800276e: 60fb str r3, [r7, #12] ep->is_in = 1U; 8002770: 68fb ldr r3, [r7, #12] 8002772: 2201 movs r2, #1 8002774: 705a strb r2, [r3, #1] 8002776: e00f b.n 8002798 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8002778: 78fb ldrb r3, [r7, #3] 800277a: f003 020f and.w r2, r3, #15 800277e: 4613 mov r3, r2 8002780: 00db lsls r3, r3, #3 8002782: 1a9b subs r3, r3, r2 8002784: 009b lsls r3, r3, #2 8002786: f503 73fc add.w r3, r3, #504 ; 0x1f8 800278a: 687a ldr r2, [r7, #4] 800278c: 4413 add r3, r2 800278e: 3304 adds r3, #4 8002790: 60fb str r3, [r7, #12] ep->is_in = 0U; 8002792: 68fb ldr r3, [r7, #12] 8002794: 2200 movs r2, #0 8002796: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8002798: 78fb ldrb r3, [r7, #3] 800279a: f003 030f and.w r3, r3, #15 800279e: b2da uxtb r2, r3 80027a0: 68fb ldr r3, [r7, #12] 80027a2: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 80027a4: 687b ldr r3, [r7, #4] 80027a6: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 80027aa: 2b01 cmp r3, #1 80027ac: d101 bne.n 80027b2 80027ae: 2302 movs r3, #2 80027b0: e00e b.n 80027d0 80027b2: 687b ldr r3, [r7, #4] 80027b4: 2201 movs r2, #1 80027b6: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 80027ba: 687b ldr r3, [r7, #4] 80027bc: 681b ldr r3, [r3, #0] 80027be: 68f9 ldr r1, [r7, #12] 80027c0: 4618 mov r0, r3 80027c2: f003 feb3 bl 800652c __HAL_UNLOCK(hpcd); 80027c6: 687b ldr r3, [r7, #4] 80027c8: 2200 movs r2, #0 80027ca: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 80027ce: 2300 movs r3, #0 } 80027d0: 4618 mov r0, r3 80027d2: 3710 adds r7, #16 80027d4: 46bd mov sp, r7 80027d6: bd80 pop {r7, pc} 080027d8 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 80027d8: b580 push {r7, lr} 80027da: b086 sub sp, #24 80027dc: af00 add r7, sp, #0 80027de: 60f8 str r0, [r7, #12] 80027e0: 607a str r2, [r7, #4] 80027e2: 603b str r3, [r7, #0] 80027e4: 460b mov r3, r1 80027e6: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80027e8: 7afb ldrb r3, [r7, #11] 80027ea: f003 020f and.w r2, r3, #15 80027ee: 4613 mov r3, r2 80027f0: 00db lsls r3, r3, #3 80027f2: 1a9b subs r3, r3, r2 80027f4: 009b lsls r3, r3, #2 80027f6: f503 73fc add.w r3, r3, #504 ; 0x1f8 80027fa: 68fa ldr r2, [r7, #12] 80027fc: 4413 add r3, r2 80027fe: 3304 adds r3, #4 8002800: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8002802: 697b ldr r3, [r7, #20] 8002804: 687a ldr r2, [r7, #4] 8002806: 60da str r2, [r3, #12] ep->xfer_len = len; 8002808: 697b ldr r3, [r7, #20] 800280a: 683a ldr r2, [r7, #0] 800280c: 615a str r2, [r3, #20] ep->xfer_count = 0U; 800280e: 697b ldr r3, [r7, #20] 8002810: 2200 movs r2, #0 8002812: 619a str r2, [r3, #24] ep->is_in = 0U; 8002814: 697b ldr r3, [r7, #20] 8002816: 2200 movs r2, #0 8002818: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 800281a: 7afb ldrb r3, [r7, #11] 800281c: f003 030f and.w r3, r3, #15 8002820: b2da uxtb r2, r3 8002822: 697b ldr r3, [r7, #20] 8002824: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8002826: 68fb ldr r3, [r7, #12] 8002828: 691b ldr r3, [r3, #16] 800282a: 2b01 cmp r3, #1 800282c: d102 bne.n 8002834 { ep->dma_addr = (uint32_t)pBuf; 800282e: 687a ldr r2, [r7, #4] 8002830: 697b ldr r3, [r7, #20] 8002832: 611a str r2, [r3, #16] } if ((ep_addr & EP_ADDR_MSK) == 0U) 8002834: 7afb ldrb r3, [r7, #11] 8002836: f003 030f and.w r3, r3, #15 800283a: 2b00 cmp r3, #0 800283c: d109 bne.n 8002852 { (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 800283e: 68fb ldr r3, [r7, #12] 8002840: 6818 ldr r0, [r3, #0] 8002842: 68fb ldr r3, [r7, #12] 8002844: 691b ldr r3, [r3, #16] 8002846: b2db uxtb r3, r3 8002848: 461a mov r2, r3 800284a: 6979 ldr r1, [r7, #20] 800284c: f004 f996 bl 8006b7c 8002850: e008 b.n 8002864 } else { (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8002852: 68fb ldr r3, [r7, #12] 8002854: 6818 ldr r0, [r3, #0] 8002856: 68fb ldr r3, [r7, #12] 8002858: 691b ldr r3, [r3, #16] 800285a: b2db uxtb r3, r3 800285c: 461a mov r2, r3 800285e: 6979 ldr r1, [r7, #20] 8002860: f003 ff40 bl 80066e4 } return HAL_OK; 8002864: 2300 movs r3, #0 } 8002866: 4618 mov r0, r3 8002868: 3718 adds r7, #24 800286a: 46bd mov sp, r7 800286c: bd80 pop {r7, pc} 0800286e : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval Data Size */ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 800286e: b480 push {r7} 8002870: b083 sub sp, #12 8002872: af00 add r7, sp, #0 8002874: 6078 str r0, [r7, #4] 8002876: 460b mov r3, r1 8002878: 70fb strb r3, [r7, #3] return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; 800287a: 78fb ldrb r3, [r7, #3] 800287c: f003 020f and.w r2, r3, #15 8002880: 6879 ldr r1, [r7, #4] 8002882: 4613 mov r3, r2 8002884: 00db lsls r3, r3, #3 8002886: 1a9b subs r3, r3, r2 8002888: 009b lsls r3, r3, #2 800288a: 440b add r3, r1 800288c: f503 7305 add.w r3, r3, #532 ; 0x214 8002890: 681b ldr r3, [r3, #0] } 8002892: 4618 mov r0, r3 8002894: 370c adds r7, #12 8002896: 46bd mov sp, r7 8002898: f85d 7b04 ldr.w r7, [sp], #4 800289c: 4770 bx lr 0800289e : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 800289e: b580 push {r7, lr} 80028a0: b086 sub sp, #24 80028a2: af00 add r7, sp, #0 80028a4: 60f8 str r0, [r7, #12] 80028a6: 607a str r2, [r7, #4] 80028a8: 603b str r3, [r7, #0] 80028aa: 460b mov r3, r1 80028ac: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 80028ae: 7afb ldrb r3, [r7, #11] 80028b0: f003 020f and.w r2, r3, #15 80028b4: 4613 mov r3, r2 80028b6: 00db lsls r3, r3, #3 80028b8: 1a9b subs r3, r3, r2 80028ba: 009b lsls r3, r3, #2 80028bc: 3338 adds r3, #56 ; 0x38 80028be: 68fa ldr r2, [r7, #12] 80028c0: 4413 add r3, r2 80028c2: 3304 adds r3, #4 80028c4: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 80028c6: 697b ldr r3, [r7, #20] 80028c8: 687a ldr r2, [r7, #4] 80028ca: 60da str r2, [r3, #12] ep->xfer_len = len; 80028cc: 697b ldr r3, [r7, #20] 80028ce: 683a ldr r2, [r7, #0] 80028d0: 615a str r2, [r3, #20] ep->xfer_count = 0U; 80028d2: 697b ldr r3, [r7, #20] 80028d4: 2200 movs r2, #0 80028d6: 619a str r2, [r3, #24] ep->is_in = 1U; 80028d8: 697b ldr r3, [r7, #20] 80028da: 2201 movs r2, #1 80028dc: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 80028de: 7afb ldrb r3, [r7, #11] 80028e0: f003 030f and.w r3, r3, #15 80028e4: b2da uxtb r2, r3 80028e6: 697b ldr r3, [r7, #20] 80028e8: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 80028ea: 68fb ldr r3, [r7, #12] 80028ec: 691b ldr r3, [r3, #16] 80028ee: 2b01 cmp r3, #1 80028f0: d102 bne.n 80028f8 { ep->dma_addr = (uint32_t)pBuf; 80028f2: 687a ldr r2, [r7, #4] 80028f4: 697b ldr r3, [r7, #20] 80028f6: 611a str r2, [r3, #16] } if ((ep_addr & EP_ADDR_MSK) == 0U) 80028f8: 7afb ldrb r3, [r7, #11] 80028fa: f003 030f and.w r3, r3, #15 80028fe: 2b00 cmp r3, #0 8002900: d109 bne.n 8002916 { (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8002902: 68fb ldr r3, [r7, #12] 8002904: 6818 ldr r0, [r3, #0] 8002906: 68fb ldr r3, [r7, #12] 8002908: 691b ldr r3, [r3, #16] 800290a: b2db uxtb r3, r3 800290c: 461a mov r2, r3 800290e: 6979 ldr r1, [r7, #20] 8002910: f004 f934 bl 8006b7c 8002914: e008 b.n 8002928 } else { (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8002916: 68fb ldr r3, [r7, #12] 8002918: 6818 ldr r0, [r3, #0] 800291a: 68fb ldr r3, [r7, #12] 800291c: 691b ldr r3, [r3, #16] 800291e: b2db uxtb r3, r3 8002920: 461a mov r2, r3 8002922: 6979 ldr r1, [r7, #20] 8002924: f003 fede bl 80066e4 } return HAL_OK; 8002928: 2300 movs r3, #0 } 800292a: 4618 mov r0, r3 800292c: 3718 adds r7, #24 800292e: 46bd mov sp, r7 8002930: bd80 pop {r7, pc} 08002932 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8002932: b580 push {r7, lr} 8002934: b084 sub sp, #16 8002936: af00 add r7, sp, #0 8002938: 6078 str r0, [r7, #4] 800293a: 460b mov r3, r1 800293c: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 800293e: 78fb ldrb r3, [r7, #3] 8002940: f003 020f and.w r2, r3, #15 8002944: 687b ldr r3, [r7, #4] 8002946: 685b ldr r3, [r3, #4] 8002948: 429a cmp r2, r3 800294a: d901 bls.n 8002950 { return HAL_ERROR; 800294c: 2301 movs r3, #1 800294e: e050 b.n 80029f2 } if ((0x80U & ep_addr) == 0x80U) 8002950: f997 3003 ldrsb.w r3, [r7, #3] 8002954: 2b00 cmp r3, #0 8002956: da0f bge.n 8002978 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8002958: 78fb ldrb r3, [r7, #3] 800295a: f003 020f and.w r2, r3, #15 800295e: 4613 mov r3, r2 8002960: 00db lsls r3, r3, #3 8002962: 1a9b subs r3, r3, r2 8002964: 009b lsls r3, r3, #2 8002966: 3338 adds r3, #56 ; 0x38 8002968: 687a ldr r2, [r7, #4] 800296a: 4413 add r3, r2 800296c: 3304 adds r3, #4 800296e: 60fb str r3, [r7, #12] ep->is_in = 1U; 8002970: 68fb ldr r3, [r7, #12] 8002972: 2201 movs r2, #1 8002974: 705a strb r2, [r3, #1] 8002976: e00d b.n 8002994 } else { ep = &hpcd->OUT_ep[ep_addr]; 8002978: 78fa ldrb r2, [r7, #3] 800297a: 4613 mov r3, r2 800297c: 00db lsls r3, r3, #3 800297e: 1a9b subs r3, r3, r2 8002980: 009b lsls r3, r3, #2 8002982: f503 73fc add.w r3, r3, #504 ; 0x1f8 8002986: 687a ldr r2, [r7, #4] 8002988: 4413 add r3, r2 800298a: 3304 adds r3, #4 800298c: 60fb str r3, [r7, #12] ep->is_in = 0U; 800298e: 68fb ldr r3, [r7, #12] 8002990: 2200 movs r2, #0 8002992: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8002994: 68fb ldr r3, [r7, #12] 8002996: 2201 movs r2, #1 8002998: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 800299a: 78fb ldrb r3, [r7, #3] 800299c: f003 030f and.w r3, r3, #15 80029a0: b2da uxtb r2, r3 80029a2: 68fb ldr r3, [r7, #12] 80029a4: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 80029a6: 687b ldr r3, [r7, #4] 80029a8: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 80029ac: 2b01 cmp r3, #1 80029ae: d101 bne.n 80029b4 80029b0: 2302 movs r3, #2 80029b2: e01e b.n 80029f2 80029b4: 687b ldr r3, [r7, #4] 80029b6: 2201 movs r2, #1 80029b8: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_EPSetStall(hpcd->Instance, ep); 80029bc: 687b ldr r3, [r7, #4] 80029be: 681b ldr r3, [r3, #0] 80029c0: 68f9 ldr r1, [r7, #12] 80029c2: 4618 mov r0, r3 80029c4: f004 fac8 bl 8006f58 if ((ep_addr & EP_ADDR_MSK) == 0U) 80029c8: 78fb ldrb r3, [r7, #3] 80029ca: f003 030f and.w r3, r3, #15 80029ce: 2b00 cmp r3, #0 80029d0: d10a bne.n 80029e8 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 80029d2: 687b ldr r3, [r7, #4] 80029d4: 6818 ldr r0, [r3, #0] 80029d6: 687b ldr r3, [r7, #4] 80029d8: 691b ldr r3, [r3, #16] 80029da: b2d9 uxtb r1, r3 80029dc: 687b ldr r3, [r7, #4] 80029de: f503 7371 add.w r3, r3, #964 ; 0x3c4 80029e2: 461a mov r2, r3 80029e4: f004 fcba bl 800735c } __HAL_UNLOCK(hpcd); 80029e8: 687b ldr r3, [r7, #4] 80029ea: 2200 movs r2, #0 80029ec: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 80029f0: 2300 movs r3, #0 } 80029f2: 4618 mov r0, r3 80029f4: 3710 adds r7, #16 80029f6: 46bd mov sp, r7 80029f8: bd80 pop {r7, pc} 080029fa : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 80029fa: b580 push {r7, lr} 80029fc: b084 sub sp, #16 80029fe: af00 add r7, sp, #0 8002a00: 6078 str r0, [r7, #4] 8002a02: 460b mov r3, r1 8002a04: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8002a06: 78fb ldrb r3, [r7, #3] 8002a08: f003 020f and.w r2, r3, #15 8002a0c: 687b ldr r3, [r7, #4] 8002a0e: 685b ldr r3, [r3, #4] 8002a10: 429a cmp r2, r3 8002a12: d901 bls.n 8002a18 { return HAL_ERROR; 8002a14: 2301 movs r3, #1 8002a16: e042 b.n 8002a9e } if ((0x80U & ep_addr) == 0x80U) 8002a18: f997 3003 ldrsb.w r3, [r7, #3] 8002a1c: 2b00 cmp r3, #0 8002a1e: da0f bge.n 8002a40 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8002a20: 78fb ldrb r3, [r7, #3] 8002a22: f003 020f and.w r2, r3, #15 8002a26: 4613 mov r3, r2 8002a28: 00db lsls r3, r3, #3 8002a2a: 1a9b subs r3, r3, r2 8002a2c: 009b lsls r3, r3, #2 8002a2e: 3338 adds r3, #56 ; 0x38 8002a30: 687a ldr r2, [r7, #4] 8002a32: 4413 add r3, r2 8002a34: 3304 adds r3, #4 8002a36: 60fb str r3, [r7, #12] ep->is_in = 1U; 8002a38: 68fb ldr r3, [r7, #12] 8002a3a: 2201 movs r2, #1 8002a3c: 705a strb r2, [r3, #1] 8002a3e: e00f b.n 8002a60 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8002a40: 78fb ldrb r3, [r7, #3] 8002a42: f003 020f and.w r2, r3, #15 8002a46: 4613 mov r3, r2 8002a48: 00db lsls r3, r3, #3 8002a4a: 1a9b subs r3, r3, r2 8002a4c: 009b lsls r3, r3, #2 8002a4e: f503 73fc add.w r3, r3, #504 ; 0x1f8 8002a52: 687a ldr r2, [r7, #4] 8002a54: 4413 add r3, r2 8002a56: 3304 adds r3, #4 8002a58: 60fb str r3, [r7, #12] ep->is_in = 0U; 8002a5a: 68fb ldr r3, [r7, #12] 8002a5c: 2200 movs r2, #0 8002a5e: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8002a60: 68fb ldr r3, [r7, #12] 8002a62: 2200 movs r2, #0 8002a64: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8002a66: 78fb ldrb r3, [r7, #3] 8002a68: f003 030f and.w r3, r3, #15 8002a6c: b2da uxtb r2, r3 8002a6e: 68fb ldr r3, [r7, #12] 8002a70: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8002a72: 687b ldr r3, [r7, #4] 8002a74: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 8002a78: 2b01 cmp r3, #1 8002a7a: d101 bne.n 8002a80 8002a7c: 2302 movs r3, #2 8002a7e: e00e b.n 8002a9e 8002a80: 687b ldr r3, [r7, #4] 8002a82: 2201 movs r2, #1 8002a84: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_EPClearStall(hpcd->Instance, ep); 8002a88: 687b ldr r3, [r7, #4] 8002a8a: 681b ldr r3, [r3, #0] 8002a8c: 68f9 ldr r1, [r7, #12] 8002a8e: 4618 mov r0, r3 8002a90: f004 fad0 bl 8007034 __HAL_UNLOCK(hpcd); 8002a94: 687b ldr r3, [r7, #4] 8002a96: 2200 movs r2, #0 8002a98: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 8002a9c: 2300 movs r3, #0 } 8002a9e: 4618 mov r0, r3 8002aa0: 3710 adds r7, #16 8002aa2: 46bd mov sp, r7 8002aa4: bd80 pop {r7, pc} 08002aa6 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8002aa6: b580 push {r7, lr} 8002aa8: b08a sub sp, #40 ; 0x28 8002aaa: af02 add r7, sp, #8 8002aac: 6078 str r0, [r7, #4] 8002aae: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002ab0: 687b ldr r3, [r7, #4] 8002ab2: 681b ldr r3, [r3, #0] 8002ab4: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8002ab6: 697b ldr r3, [r7, #20] 8002ab8: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 8002aba: 683a ldr r2, [r7, #0] 8002abc: 4613 mov r3, r2 8002abe: 00db lsls r3, r3, #3 8002ac0: 1a9b subs r3, r3, r2 8002ac2: 009b lsls r3, r3, #2 8002ac4: 3338 adds r3, #56 ; 0x38 8002ac6: 687a ldr r2, [r7, #4] 8002ac8: 4413 add r3, r2 8002aca: 3304 adds r3, #4 8002acc: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 8002ace: 68fb ldr r3, [r7, #12] 8002ad0: 699a ldr r2, [r3, #24] 8002ad2: 68fb ldr r3, [r7, #12] 8002ad4: 695b ldr r3, [r3, #20] 8002ad6: 429a cmp r2, r3 8002ad8: d901 bls.n 8002ade { return HAL_ERROR; 8002ada: 2301 movs r3, #1 8002adc: e06c b.n 8002bb8 } len = ep->xfer_len - ep->xfer_count; 8002ade: 68fb ldr r3, [r7, #12] 8002ae0: 695a ldr r2, [r3, #20] 8002ae2: 68fb ldr r3, [r7, #12] 8002ae4: 699b ldr r3, [r3, #24] 8002ae6: 1ad3 subs r3, r2, r3 8002ae8: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8002aea: 68fb ldr r3, [r7, #12] 8002aec: 689b ldr r3, [r3, #8] 8002aee: 69fa ldr r2, [r7, #28] 8002af0: 429a cmp r2, r3 8002af2: d902 bls.n 8002afa { len = ep->maxpacket; 8002af4: 68fb ldr r3, [r7, #12] 8002af6: 689b ldr r3, [r3, #8] 8002af8: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8002afa: 69fb ldr r3, [r7, #28] 8002afc: 3303 adds r3, #3 8002afe: 089b lsrs r3, r3, #2 8002b00: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8002b02: e02b b.n 8002b5c (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 8002b04: 68fb ldr r3, [r7, #12] 8002b06: 695a ldr r2, [r3, #20] 8002b08: 68fb ldr r3, [r7, #12] 8002b0a: 699b ldr r3, [r3, #24] 8002b0c: 1ad3 subs r3, r2, r3 8002b0e: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8002b10: 68fb ldr r3, [r7, #12] 8002b12: 689b ldr r3, [r3, #8] 8002b14: 69fa ldr r2, [r7, #28] 8002b16: 429a cmp r2, r3 8002b18: d902 bls.n 8002b20 { len = ep->maxpacket; 8002b1a: 68fb ldr r3, [r7, #12] 8002b1c: 689b ldr r3, [r3, #8] 8002b1e: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8002b20: 69fb ldr r3, [r7, #28] 8002b22: 3303 adds r3, #3 8002b24: 089b lsrs r3, r3, #2 8002b26: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8002b28: 68fb ldr r3, [r7, #12] 8002b2a: 68d9 ldr r1, [r3, #12] 8002b2c: 683b ldr r3, [r7, #0] 8002b2e: b2da uxtb r2, r3 8002b30: 69fb ldr r3, [r7, #28] 8002b32: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 8002b34: 687b ldr r3, [r7, #4] 8002b36: 691b ldr r3, [r3, #16] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8002b38: b2db uxtb r3, r3 8002b3a: 9300 str r3, [sp, #0] 8002b3c: 4603 mov r3, r0 8002b3e: 6978 ldr r0, [r7, #20] 8002b40: f004 f974 bl 8006e2c ep->xfer_buff += len; 8002b44: 68fb ldr r3, [r7, #12] 8002b46: 68da ldr r2, [r3, #12] 8002b48: 69fb ldr r3, [r7, #28] 8002b4a: 441a add r2, r3 8002b4c: 68fb ldr r3, [r7, #12] 8002b4e: 60da str r2, [r3, #12] ep->xfer_count += len; 8002b50: 68fb ldr r3, [r7, #12] 8002b52: 699a ldr r2, [r3, #24] 8002b54: 69fb ldr r3, [r7, #28] 8002b56: 441a add r2, r3 8002b58: 68fb ldr r3, [r7, #12] 8002b5a: 619a str r2, [r3, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8002b5c: 683b ldr r3, [r7, #0] 8002b5e: 015a lsls r2, r3, #5 8002b60: 693b ldr r3, [r7, #16] 8002b62: 4413 add r3, r2 8002b64: f503 6310 add.w r3, r3, #2304 ; 0x900 8002b68: 699b ldr r3, [r3, #24] 8002b6a: b29b uxth r3, r3 8002b6c: 69ba ldr r2, [r7, #24] 8002b6e: 429a cmp r2, r3 8002b70: d809 bhi.n 8002b86 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8002b72: 68fb ldr r3, [r7, #12] 8002b74: 699a ldr r2, [r3, #24] 8002b76: 68fb ldr r3, [r7, #12] 8002b78: 695b ldr r3, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8002b7a: 429a cmp r2, r3 8002b7c: d203 bcs.n 8002b86 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8002b7e: 68fb ldr r3, [r7, #12] 8002b80: 695b ldr r3, [r3, #20] 8002b82: 2b00 cmp r3, #0 8002b84: d1be bne.n 8002b04 } if (ep->xfer_len <= ep->xfer_count) 8002b86: 68fb ldr r3, [r7, #12] 8002b88: 695a ldr r2, [r3, #20] 8002b8a: 68fb ldr r3, [r7, #12] 8002b8c: 699b ldr r3, [r3, #24] 8002b8e: 429a cmp r2, r3 8002b90: d811 bhi.n 8002bb6 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8002b92: 683b ldr r3, [r7, #0] 8002b94: f003 030f and.w r3, r3, #15 8002b98: 2201 movs r2, #1 8002b9a: fa02 f303 lsl.w r3, r2, r3 8002b9e: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8002ba0: 693b ldr r3, [r7, #16] 8002ba2: f503 6300 add.w r3, r3, #2048 ; 0x800 8002ba6: 6b5a ldr r2, [r3, #52] ; 0x34 8002ba8: 68bb ldr r3, [r7, #8] 8002baa: 43db mvns r3, r3 8002bac: 6939 ldr r1, [r7, #16] 8002bae: f501 6100 add.w r1, r1, #2048 ; 0x800 8002bb2: 4013 ands r3, r2 8002bb4: 634b str r3, [r1, #52] ; 0x34 } return HAL_OK; 8002bb6: 2300 movs r3, #0 } 8002bb8: 4618 mov r0, r3 8002bba: 3720 adds r7, #32 8002bbc: 46bd mov sp, r7 8002bbe: bd80 pop {r7, pc} 08002bc0 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8002bc0: b580 push {r7, lr} 8002bc2: b086 sub sp, #24 8002bc4: af00 add r7, sp, #0 8002bc6: 6078 str r0, [r7, #4] 8002bc8: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002bca: 687b ldr r3, [r7, #4] 8002bcc: 681b ldr r3, [r3, #0] 8002bce: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8002bd0: 697b ldr r3, [r7, #20] 8002bd2: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); 8002bd4: 697b ldr r3, [r7, #20] 8002bd6: 333c adds r3, #60 ; 0x3c 8002bd8: 3304 adds r3, #4 8002bda: 681b ldr r3, [r3, #0] 8002bdc: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8002bde: 683b ldr r3, [r7, #0] 8002be0: 015a lsls r2, r3, #5 8002be2: 693b ldr r3, [r7, #16] 8002be4: 4413 add r3, r2 8002be6: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002bea: 689b ldr r3, [r3, #8] 8002bec: 60bb str r3, [r7, #8] if (hpcd->Init.dma_enable == 1U) 8002bee: 687b ldr r3, [r7, #4] 8002bf0: 691b ldr r3, [r3, #16] 8002bf2: 2b01 cmp r3, #1 8002bf4: f040 80a0 bne.w 8002d38 { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 8002bf8: 68bb ldr r3, [r7, #8] 8002bfa: f003 0308 and.w r3, r3, #8 8002bfe: 2b00 cmp r3, #0 8002c00: d015 beq.n 8002c2e { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002c02: 68fb ldr r3, [r7, #12] 8002c04: 4a72 ldr r2, [pc, #456] ; (8002dd0 ) 8002c06: 4293 cmp r3, r2 8002c08: f240 80dd bls.w 8002dc6 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8002c0c: 68bb ldr r3, [r7, #8] 8002c0e: f403 4300 and.w r3, r3, #32768 ; 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002c12: 2b00 cmp r3, #0 8002c14: f000 80d7 beq.w 8002dc6 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8002c18: 683b ldr r3, [r7, #0] 8002c1a: 015a lsls r2, r3, #5 8002c1c: 693b ldr r3, [r7, #16] 8002c1e: 4413 add r3, r2 8002c20: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002c24: 461a mov r2, r3 8002c26: f44f 4300 mov.w r3, #32768 ; 0x8000 8002c2a: 6093 str r3, [r2, #8] 8002c2c: e0cb b.n 8002dc6 } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 8002c2e: 68bb ldr r3, [r7, #8] 8002c30: f003 0320 and.w r3, r3, #32 8002c34: 2b00 cmp r3, #0 8002c36: d009 beq.n 8002c4c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8002c38: 683b ldr r3, [r7, #0] 8002c3a: 015a lsls r2, r3, #5 8002c3c: 693b ldr r3, [r7, #16] 8002c3e: 4413 add r3, r2 8002c40: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002c44: 461a mov r2, r3 8002c46: 2320 movs r3, #32 8002c48: 6093 str r3, [r2, #8] 8002c4a: e0bc b.n 8002dc6 } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 8002c4c: 68bb ldr r3, [r7, #8] 8002c4e: f003 0328 and.w r3, r3, #40 ; 0x28 8002c52: 2b00 cmp r3, #0 8002c54: f040 80b7 bne.w 8002dc6 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002c58: 68fb ldr r3, [r7, #12] 8002c5a: 4a5d ldr r2, [pc, #372] ; (8002dd0 ) 8002c5c: 4293 cmp r3, r2 8002c5e: d90f bls.n 8002c80 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8002c60: 68bb ldr r3, [r7, #8] 8002c62: f403 4300 and.w r3, r3, #32768 ; 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002c66: 2b00 cmp r3, #0 8002c68: d00a beq.n 8002c80 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8002c6a: 683b ldr r3, [r7, #0] 8002c6c: 015a lsls r2, r3, #5 8002c6e: 693b ldr r3, [r7, #16] 8002c70: 4413 add r3, r2 8002c72: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002c76: 461a mov r2, r3 8002c78: f44f 4300 mov.w r3, #32768 ; 0x8000 8002c7c: 6093 str r3, [r2, #8] 8002c7e: e0a2 b.n 8002dc6 } else { /* out data packet received over EP0 */ hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket - 8002c80: 6879 ldr r1, [r7, #4] 8002c82: 683a ldr r2, [r7, #0] 8002c84: 4613 mov r3, r2 8002c86: 00db lsls r3, r3, #3 8002c88: 1a9b subs r3, r3, r2 8002c8a: 009b lsls r3, r3, #2 8002c8c: 440b add r3, r1 8002c8e: f503 7301 add.w r3, r3, #516 ; 0x204 8002c92: 681a ldr r2, [r3, #0] (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 8002c94: 683b ldr r3, [r7, #0] 8002c96: 0159 lsls r1, r3, #5 8002c98: 693b ldr r3, [r7, #16] 8002c9a: 440b add r3, r1 8002c9c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002ca0: 691b ldr r3, [r3, #16] 8002ca2: f3c3 0312 ubfx r3, r3, #0, #19 hpcd->OUT_ep[epnum].maxpacket - 8002ca6: 1ad1 subs r1, r2, r3 hpcd->OUT_ep[epnum].xfer_count = 8002ca8: 6878 ldr r0, [r7, #4] 8002caa: 683a ldr r2, [r7, #0] 8002cac: 4613 mov r3, r2 8002cae: 00db lsls r3, r3, #3 8002cb0: 1a9b subs r3, r3, r2 8002cb2: 009b lsls r3, r3, #2 8002cb4: 4403 add r3, r0 8002cb6: f503 7305 add.w r3, r3, #532 ; 0x214 8002cba: 6019 str r1, [r3, #0] hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; 8002cbc: 6879 ldr r1, [r7, #4] 8002cbe: 683a ldr r2, [r7, #0] 8002cc0: 4613 mov r3, r2 8002cc2: 00db lsls r3, r3, #3 8002cc4: 1a9b subs r3, r3, r2 8002cc6: 009b lsls r3, r3, #2 8002cc8: 440b add r3, r1 8002cca: f503 7302 add.w r3, r3, #520 ; 0x208 8002cce: 6819 ldr r1, [r3, #0] 8002cd0: 6878 ldr r0, [r7, #4] 8002cd2: 683a ldr r2, [r7, #0] 8002cd4: 4613 mov r3, r2 8002cd6: 00db lsls r3, r3, #3 8002cd8: 1a9b subs r3, r3, r2 8002cda: 009b lsls r3, r3, #2 8002cdc: 4403 add r3, r0 8002cde: f503 7301 add.w r3, r3, #516 ; 0x204 8002ce2: 681b ldr r3, [r3, #0] 8002ce4: 4419 add r1, r3 8002ce6: 6878 ldr r0, [r7, #4] 8002ce8: 683a ldr r2, [r7, #0] 8002cea: 4613 mov r3, r2 8002cec: 00db lsls r3, r3, #3 8002cee: 1a9b subs r3, r3, r2 8002cf0: 009b lsls r3, r3, #2 8002cf2: 4403 add r3, r0 8002cf4: f503 7302 add.w r3, r3, #520 ; 0x208 8002cf8: 6019 str r1, [r3, #0] if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8002cfa: 683b ldr r3, [r7, #0] 8002cfc: 2b00 cmp r3, #0 8002cfe: d114 bne.n 8002d2a 8002d00: 6879 ldr r1, [r7, #4] 8002d02: 683a ldr r2, [r7, #0] 8002d04: 4613 mov r3, r2 8002d06: 00db lsls r3, r3, #3 8002d08: 1a9b subs r3, r3, r2 8002d0a: 009b lsls r3, r3, #2 8002d0c: 440b add r3, r1 8002d0e: f503 7304 add.w r3, r3, #528 ; 0x210 8002d12: 681b ldr r3, [r3, #0] 8002d14: 2b00 cmp r3, #0 8002d16: d108 bne.n 8002d2a { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8002d18: 687b ldr r3, [r7, #4] 8002d1a: 6818 ldr r0, [r3, #0] 8002d1c: 687b ldr r3, [r7, #4] 8002d1e: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002d22: 461a mov r2, r3 8002d24: 2101 movs r1, #1 8002d26: f004 fb19 bl 800735c } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8002d2a: 683b ldr r3, [r7, #0] 8002d2c: b2db uxtb r3, r3 8002d2e: 4619 mov r1, r3 8002d30: 6878 ldr r0, [r7, #4] 8002d32: f006 fabf bl 80092b4 8002d36: e046 b.n 8002dc6 /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 8002d38: 68fb ldr r3, [r7, #12] 8002d3a: 4a26 ldr r2, [pc, #152] ; (8002dd4 ) 8002d3c: 4293 cmp r3, r2 8002d3e: d124 bne.n 8002d8a { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 8002d40: 68bb ldr r3, [r7, #8] 8002d42: f403 4300 and.w r3, r3, #32768 ; 0x8000 8002d46: 2b00 cmp r3, #0 8002d48: d00a beq.n 8002d60 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8002d4a: 683b ldr r3, [r7, #0] 8002d4c: 015a lsls r2, r3, #5 8002d4e: 693b ldr r3, [r7, #16] 8002d50: 4413 add r3, r2 8002d52: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002d56: 461a mov r2, r3 8002d58: f44f 4300 mov.w r3, #32768 ; 0x8000 8002d5c: 6093 str r3, [r2, #8] 8002d5e: e032 b.n 8002dc6 } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8002d60: 68bb ldr r3, [r7, #8] 8002d62: f003 0320 and.w r3, r3, #32 8002d66: 2b00 cmp r3, #0 8002d68: d008 beq.n 8002d7c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8002d6a: 683b ldr r3, [r7, #0] 8002d6c: 015a lsls r2, r3, #5 8002d6e: 693b ldr r3, [r7, #16] 8002d70: 4413 add r3, r2 8002d72: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002d76: 461a mov r2, r3 8002d78: 2320 movs r3, #32 8002d7a: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8002d7c: 683b ldr r3, [r7, #0] 8002d7e: b2db uxtb r3, r3 8002d80: 4619 mov r1, r3 8002d82: 6878 ldr r0, [r7, #4] 8002d84: f006 fa96 bl 80092b4 8002d88: e01d b.n 8002dc6 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8002d8a: 683b ldr r3, [r7, #0] 8002d8c: 2b00 cmp r3, #0 8002d8e: d114 bne.n 8002dba 8002d90: 6879 ldr r1, [r7, #4] 8002d92: 683a ldr r2, [r7, #0] 8002d94: 4613 mov r3, r2 8002d96: 00db lsls r3, r3, #3 8002d98: 1a9b subs r3, r3, r2 8002d9a: 009b lsls r3, r3, #2 8002d9c: 440b add r3, r1 8002d9e: f503 7304 add.w r3, r3, #528 ; 0x210 8002da2: 681b ldr r3, [r3, #0] 8002da4: 2b00 cmp r3, #0 8002da6: d108 bne.n 8002dba { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 8002da8: 687b ldr r3, [r7, #4] 8002daa: 6818 ldr r0, [r3, #0] 8002dac: 687b ldr r3, [r7, #4] 8002dae: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002db2: 461a mov r2, r3 8002db4: 2100 movs r1, #0 8002db6: f004 fad1 bl 800735c } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8002dba: 683b ldr r3, [r7, #0] 8002dbc: b2db uxtb r3, r3 8002dbe: 4619 mov r1, r3 8002dc0: 6878 ldr r0, [r7, #4] 8002dc2: f006 fa77 bl 80092b4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 8002dc6: 2300 movs r3, #0 } 8002dc8: 4618 mov r0, r3 8002dca: 3718 adds r7, #24 8002dcc: 46bd mov sp, r7 8002dce: bd80 pop {r7, pc} 8002dd0: 4f54300a .word 0x4f54300a 8002dd4: 4f54310a .word 0x4f54310a 08002dd8 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8002dd8: b580 push {r7, lr} 8002dda: b086 sub sp, #24 8002ddc: af00 add r7, sp, #0 8002dde: 6078 str r0, [r7, #4] 8002de0: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002de2: 687b ldr r3, [r7, #4] 8002de4: 681b ldr r3, [r3, #0] 8002de6: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8002de8: 697b ldr r3, [r7, #20] 8002dea: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); 8002dec: 697b ldr r3, [r7, #20] 8002dee: 333c adds r3, #60 ; 0x3c 8002df0: 3304 adds r3, #4 8002df2: 681b ldr r3, [r3, #0] 8002df4: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8002df6: 683b ldr r3, [r7, #0] 8002df8: 015a lsls r2, r3, #5 8002dfa: 693b ldr r3, [r7, #16] 8002dfc: 4413 add r3, r2 8002dfe: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002e02: 689b ldr r3, [r3, #8] 8002e04: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002e06: 68fb ldr r3, [r7, #12] 8002e08: 4a15 ldr r2, [pc, #84] ; (8002e60 ) 8002e0a: 4293 cmp r3, r2 8002e0c: d90e bls.n 8002e2c ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8002e0e: 68bb ldr r3, [r7, #8] 8002e10: f403 4300 and.w r3, r3, #32768 ; 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002e14: 2b00 cmp r3, #0 8002e16: d009 beq.n 8002e2c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8002e18: 683b ldr r3, [r7, #0] 8002e1a: 015a lsls r2, r3, #5 8002e1c: 693b ldr r3, [r7, #16] 8002e1e: 4413 add r3, r2 8002e20: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002e24: 461a mov r2, r3 8002e26: f44f 4300 mov.w r3, #32768 ; 0x8000 8002e2a: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 8002e2c: 6878 ldr r0, [r7, #4] 8002e2e: f006 fa2f bl 8009290 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 8002e32: 68fb ldr r3, [r7, #12] 8002e34: 4a0a ldr r2, [pc, #40] ; (8002e60 ) 8002e36: 4293 cmp r3, r2 8002e38: d90c bls.n 8002e54 8002e3a: 687b ldr r3, [r7, #4] 8002e3c: 691b ldr r3, [r3, #16] 8002e3e: 2b01 cmp r3, #1 8002e40: d108 bne.n 8002e54 { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8002e42: 687b ldr r3, [r7, #4] 8002e44: 6818 ldr r0, [r3, #0] 8002e46: 687b ldr r3, [r7, #4] 8002e48: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002e4c: 461a mov r2, r3 8002e4e: 2101 movs r1, #1 8002e50: f004 fa84 bl 800735c } return HAL_OK; 8002e54: 2300 movs r3, #0 } 8002e56: 4618 mov r0, r3 8002e58: 3718 adds r7, #24 8002e5a: 46bd mov sp, r7 8002e5c: bd80 pop {r7, pc} 8002e5e: bf00 nop 8002e60: 4f54300a .word 0x4f54300a 08002e64 : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 8002e64: b480 push {r7} 8002e66: b085 sub sp, #20 8002e68: af00 add r7, sp, #0 8002e6a: 6078 str r0, [r7, #4] 8002e6c: 460b mov r3, r1 8002e6e: 70fb strb r3, [r7, #3] 8002e70: 4613 mov r3, r2 8002e72: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 8002e74: 687b ldr r3, [r7, #4] 8002e76: 681b ldr r3, [r3, #0] 8002e78: 6a5b ldr r3, [r3, #36] ; 0x24 8002e7a: 60bb str r3, [r7, #8] if (fifo == 0U) 8002e7c: 78fb ldrb r3, [r7, #3] 8002e7e: 2b00 cmp r3, #0 8002e80: d107 bne.n 8002e92 { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 8002e82: 883b ldrh r3, [r7, #0] 8002e84: 0419 lsls r1, r3, #16 8002e86: 687b ldr r3, [r7, #4] 8002e88: 681b ldr r3, [r3, #0] 8002e8a: 68ba ldr r2, [r7, #8] 8002e8c: 430a orrs r2, r1 8002e8e: 629a str r2, [r3, #40] ; 0x28 8002e90: e028 b.n 8002ee4 } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 8002e92: 687b ldr r3, [r7, #4] 8002e94: 681b ldr r3, [r3, #0] 8002e96: 6a9b ldr r3, [r3, #40] ; 0x28 8002e98: 0c1b lsrs r3, r3, #16 8002e9a: 68ba ldr r2, [r7, #8] 8002e9c: 4413 add r3, r2 8002e9e: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8002ea0: 2300 movs r3, #0 8002ea2: 73fb strb r3, [r7, #15] 8002ea4: e00d b.n 8002ec2 { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 8002ea6: 687b ldr r3, [r7, #4] 8002ea8: 681a ldr r2, [r3, #0] 8002eaa: 7bfb ldrb r3, [r7, #15] 8002eac: 3340 adds r3, #64 ; 0x40 8002eae: 009b lsls r3, r3, #2 8002eb0: 4413 add r3, r2 8002eb2: 685b ldr r3, [r3, #4] 8002eb4: 0c1b lsrs r3, r3, #16 8002eb6: 68ba ldr r2, [r7, #8] 8002eb8: 4413 add r3, r2 8002eba: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8002ebc: 7bfb ldrb r3, [r7, #15] 8002ebe: 3301 adds r3, #1 8002ec0: 73fb strb r3, [r7, #15] 8002ec2: 7bfa ldrb r2, [r7, #15] 8002ec4: 78fb ldrb r3, [r7, #3] 8002ec6: 3b01 subs r3, #1 8002ec8: 429a cmp r2, r3 8002eca: d3ec bcc.n 8002ea6 } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 8002ecc: 883b ldrh r3, [r7, #0] 8002ece: 0418 lsls r0, r3, #16 8002ed0: 687b ldr r3, [r7, #4] 8002ed2: 6819 ldr r1, [r3, #0] 8002ed4: 78fb ldrb r3, [r7, #3] 8002ed6: 3b01 subs r3, #1 8002ed8: 68ba ldr r2, [r7, #8] 8002eda: 4302 orrs r2, r0 8002edc: 3340 adds r3, #64 ; 0x40 8002ede: 009b lsls r3, r3, #2 8002ee0: 440b add r3, r1 8002ee2: 605a str r2, [r3, #4] } return HAL_OK; 8002ee4: 2300 movs r3, #0 } 8002ee6: 4618 mov r0, r3 8002ee8: 3714 adds r7, #20 8002eea: 46bd mov sp, r7 8002eec: f85d 7b04 ldr.w r7, [sp], #4 8002ef0: 4770 bx lr 08002ef2 : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 8002ef2: b480 push {r7} 8002ef4: b083 sub sp, #12 8002ef6: af00 add r7, sp, #0 8002ef8: 6078 str r0, [r7, #4] 8002efa: 460b mov r3, r1 8002efc: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 8002efe: 687b ldr r3, [r7, #4] 8002f00: 681b ldr r3, [r3, #0] 8002f02: 887a ldrh r2, [r7, #2] 8002f04: 625a str r2, [r3, #36] ; 0x24 return HAL_OK; 8002f06: 2300 movs r3, #0 } 8002f08: 4618 mov r0, r3 8002f0a: 370c adds r7, #12 8002f0c: 46bd mov sp, r7 8002f0e: f85d 7b04 ldr.w r7, [sp], #4 8002f12: 4770 bx lr 08002f14 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 8002f14: b480 push {r7} 8002f16: b085 sub sp, #20 8002f18: af00 add r7, sp, #0 8002f1a: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002f1c: 687b ldr r3, [r7, #4] 8002f1e: 681b ldr r3, [r3, #0] 8002f20: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 8002f22: 687b ldr r3, [r7, #4] 8002f24: 2201 movs r2, #1 8002f26: f8c3 23fc str.w r2, [r3, #1020] ; 0x3fc hpcd->LPM_State = LPM_L0; 8002f2a: 687b ldr r3, [r7, #4] 8002f2c: 2200 movs r2, #0 8002f2e: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4 USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 8002f32: 68fb ldr r3, [r7, #12] 8002f34: 699b ldr r3, [r3, #24] 8002f36: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000 8002f3a: 68fb ldr r3, [r7, #12] 8002f3c: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 8002f3e: 68fb ldr r3, [r7, #12] 8002f40: 6d5a ldr r2, [r3, #84] ; 0x54 8002f42: 4b05 ldr r3, [pc, #20] ; (8002f58 ) 8002f44: 4313 orrs r3, r2 8002f46: 68fa ldr r2, [r7, #12] 8002f48: 6553 str r3, [r2, #84] ; 0x54 return HAL_OK; 8002f4a: 2300 movs r3, #0 } 8002f4c: 4618 mov r0, r3 8002f4e: 3714 adds r7, #20 8002f50: 46bd mov sp, r7 8002f52: f85d 7b04 ldr.w r7, [sp], #4 8002f56: 4770 bx lr 8002f58: 10000003 .word 0x10000003 08002f5c : * @param hpcd PCD handle * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 8002f5c: b480 push {r7} 8002f5e: b083 sub sp, #12 8002f60: af00 add r7, sp, #0 8002f62: 6078 str r0, [r7, #4] 8002f64: 460b mov r3, r1 8002f66: 70fb strb r3, [r7, #3] UNUSED(msg); /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCDEx_LPM_Callback could be implemented in the user file */ } 8002f68: bf00 nop 8002f6a: 370c adds r7, #12 8002f6c: 46bd mov sp, r7 8002f6e: f85d 7b04 ldr.w r7, [sp], #4 8002f72: 4770 bx lr 08002f74 : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 8002f74: b580 push {r7, lr} 8002f76: b084 sub sp, #16 8002f78: af00 add r7, sp, #0 8002f7a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 8002f7c: 4b19 ldr r3, [pc, #100] ; (8002fe4 ) 8002f7e: 68db ldr r3, [r3, #12] 8002f80: f003 0304 and.w r3, r3, #4 8002f84: 2b04 cmp r3, #4 8002f86: d00a beq.n 8002f9e #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 8002f88: 4b16 ldr r3, [pc, #88] ; (8002fe4 ) 8002f8a: 68db ldr r3, [r3, #12] 8002f8c: f003 0307 and.w r3, r3, #7 8002f90: 687a ldr r2, [r7, #4] 8002f92: 429a cmp r2, r3 8002f94: d001 beq.n 8002f9a { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 8002f96: 2301 movs r3, #1 8002f98: e01f b.n 8002fda else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 8002f9a: 2300 movs r3, #0 8002f9c: e01d b.n 8002fda } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 8002f9e: 4b11 ldr r3, [pc, #68] ; (8002fe4 ) 8002fa0: 68db ldr r3, [r3, #12] 8002fa2: f023 0207 bic.w r2, r3, #7 8002fa6: 490f ldr r1, [pc, #60] ; (8002fe4 ) 8002fa8: 687b ldr r3, [r7, #4] 8002faa: 4313 orrs r3, r2 8002fac: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 8002fae: f7fe faf7 bl 80015a0 8002fb2: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 8002fb4: e009 b.n 8002fca { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 8002fb6: f7fe faf3 bl 80015a0 8002fba: 4602 mov r2, r0 8002fbc: 68fb ldr r3, [r7, #12] 8002fbe: 1ad3 subs r3, r2, r3 8002fc0: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 8002fc4: d901 bls.n 8002fca { return HAL_ERROR; 8002fc6: 2301 movs r3, #1 8002fc8: e007 b.n 8002fda while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 8002fca: 4b06 ldr r3, [pc, #24] ; (8002fe4 ) 8002fcc: 685b ldr r3, [r3, #4] 8002fce: f403 5300 and.w r3, r3, #8192 ; 0x2000 8002fd2: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8002fd6: d1ee bne.n 8002fb6 } } } #endif /* defined (SMPS) */ return HAL_OK; 8002fd8: 2300 movs r3, #0 } 8002fda: 4618 mov r0, r3 8002fdc: 3710 adds r7, #16 8002fde: 46bd mov sp, r7 8002fe0: bd80 pop {r7, pc} 8002fe2: bf00 nop 8002fe4: 58024800 .word 0x58024800 08002fe8 : /** * @brief Enable the USB voltage level detector. * @retval None. */ void HAL_PWREx_EnableUSBVoltageDetector (void) { 8002fe8: b480 push {r7} 8002fea: af00 add r7, sp, #0 /* Enable the USB voltage detector */ SET_BIT (PWR->CR3, PWR_CR3_USB33DEN); 8002fec: 4b05 ldr r3, [pc, #20] ; (8003004 ) 8002fee: 68db ldr r3, [r3, #12] 8002ff0: 4a04 ldr r2, [pc, #16] ; (8003004 ) 8002ff2: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8002ff6: 60d3 str r3, [r2, #12] } 8002ff8: bf00 nop 8002ffa: 46bd mov sp, r7 8002ffc: f85d 7b04 ldr.w r7, [sp], #4 8003000: 4770 bx lr 8003002: bf00 nop 8003004: 58024800 .word 0x58024800 08003008 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8003008: b580 push {r7, lr} 800300a: b08c sub sp, #48 ; 0x30 800300c: af00 add r7, sp, #0 800300e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8003010: 687b ldr r3, [r7, #4] 8003012: 2b00 cmp r3, #0 8003014: d101 bne.n 800301a { return HAL_ERROR; 8003016: 2301 movs r3, #1 8003018: e397 b.n 800374a } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800301a: 687b ldr r3, [r7, #4] 800301c: 681b ldr r3, [r3, #0] 800301e: f003 0301 and.w r3, r3, #1 8003022: 2b00 cmp r3, #0 8003024: f000 8087 beq.w 8003136 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003028: 4b9e ldr r3, [pc, #632] ; (80032a4 ) 800302a: 691b ldr r3, [r3, #16] 800302c: f003 0338 and.w r3, r3, #56 ; 0x38 8003030: 62fb str r3, [r7, #44] ; 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8003032: 4b9c ldr r3, [pc, #624] ; (80032a4 ) 8003034: 6a9b ldr r3, [r3, #40] ; 0x28 8003036: 62bb str r3, [r7, #40] ; 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 8003038: 6afb ldr r3, [r7, #44] ; 0x2c 800303a: 2b10 cmp r3, #16 800303c: d007 beq.n 800304e 800303e: 6afb ldr r3, [r7, #44] ; 0x2c 8003040: 2b18 cmp r3, #24 8003042: d110 bne.n 8003066 8003044: 6abb ldr r3, [r7, #40] ; 0x28 8003046: f003 0303 and.w r3, r3, #3 800304a: 2b02 cmp r3, #2 800304c: d10b bne.n 8003066 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800304e: 4b95 ldr r3, [pc, #596] ; (80032a4 ) 8003050: 681b ldr r3, [r3, #0] 8003052: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003056: 2b00 cmp r3, #0 8003058: d06c beq.n 8003134 800305a: 687b ldr r3, [r7, #4] 800305c: 685b ldr r3, [r3, #4] 800305e: 2b00 cmp r3, #0 8003060: d168 bne.n 8003134 { return HAL_ERROR; 8003062: 2301 movs r3, #1 8003064: e371 b.n 800374a } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8003066: 687b ldr r3, [r7, #4] 8003068: 685b ldr r3, [r3, #4] 800306a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800306e: d106 bne.n 800307e 8003070: 4b8c ldr r3, [pc, #560] ; (80032a4 ) 8003072: 681b ldr r3, [r3, #0] 8003074: 4a8b ldr r2, [pc, #556] ; (80032a4 ) 8003076: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800307a: 6013 str r3, [r2, #0] 800307c: e02e b.n 80030dc 800307e: 687b ldr r3, [r7, #4] 8003080: 685b ldr r3, [r3, #4] 8003082: 2b00 cmp r3, #0 8003084: d10c bne.n 80030a0 8003086: 4b87 ldr r3, [pc, #540] ; (80032a4 ) 8003088: 681b ldr r3, [r3, #0] 800308a: 4a86 ldr r2, [pc, #536] ; (80032a4 ) 800308c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8003090: 6013 str r3, [r2, #0] 8003092: 4b84 ldr r3, [pc, #528] ; (80032a4 ) 8003094: 681b ldr r3, [r3, #0] 8003096: 4a83 ldr r2, [pc, #524] ; (80032a4 ) 8003098: f423 2380 bic.w r3, r3, #262144 ; 0x40000 800309c: 6013 str r3, [r2, #0] 800309e: e01d b.n 80030dc 80030a0: 687b ldr r3, [r7, #4] 80030a2: 685b ldr r3, [r3, #4] 80030a4: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80030a8: d10c bne.n 80030c4 80030aa: 4b7e ldr r3, [pc, #504] ; (80032a4 ) 80030ac: 681b ldr r3, [r3, #0] 80030ae: 4a7d ldr r2, [pc, #500] ; (80032a4 ) 80030b0: f443 2380 orr.w r3, r3, #262144 ; 0x40000 80030b4: 6013 str r3, [r2, #0] 80030b6: 4b7b ldr r3, [pc, #492] ; (80032a4 ) 80030b8: 681b ldr r3, [r3, #0] 80030ba: 4a7a ldr r2, [pc, #488] ; (80032a4 ) 80030bc: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80030c0: 6013 str r3, [r2, #0] 80030c2: e00b b.n 80030dc 80030c4: 4b77 ldr r3, [pc, #476] ; (80032a4 ) 80030c6: 681b ldr r3, [r3, #0] 80030c8: 4a76 ldr r2, [pc, #472] ; (80032a4 ) 80030ca: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80030ce: 6013 str r3, [r2, #0] 80030d0: 4b74 ldr r3, [pc, #464] ; (80032a4 ) 80030d2: 681b ldr r3, [r3, #0] 80030d4: 4a73 ldr r2, [pc, #460] ; (80032a4 ) 80030d6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80030da: 6013 str r3, [r2, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80030dc: 687b ldr r3, [r7, #4] 80030de: 685b ldr r3, [r3, #4] 80030e0: 2b00 cmp r3, #0 80030e2: d013 beq.n 800310c { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80030e4: f7fe fa5c bl 80015a0 80030e8: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80030ea: e008 b.n 80030fe { if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80030ec: f7fe fa58 bl 80015a0 80030f0: 4602 mov r2, r0 80030f2: 6a7b ldr r3, [r7, #36] ; 0x24 80030f4: 1ad3 subs r3, r2, r3 80030f6: 2b64 cmp r3, #100 ; 0x64 80030f8: d901 bls.n 80030fe { return HAL_TIMEOUT; 80030fa: 2303 movs r3, #3 80030fc: e325 b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80030fe: 4b69 ldr r3, [pc, #420] ; (80032a4 ) 8003100: 681b ldr r3, [r3, #0] 8003102: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003106: 2b00 cmp r3, #0 8003108: d0f0 beq.n 80030ec 800310a: e014 b.n 8003136 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800310c: f7fe fa48 bl 80015a0 8003110: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 8003112: e008 b.n 8003126 { if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8003114: f7fe fa44 bl 80015a0 8003118: 4602 mov r2, r0 800311a: 6a7b ldr r3, [r7, #36] ; 0x24 800311c: 1ad3 subs r3, r2, r3 800311e: 2b64 cmp r3, #100 ; 0x64 8003120: d901 bls.n 8003126 { return HAL_TIMEOUT; 8003122: 2303 movs r3, #3 8003124: e311 b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 8003126: 4b5f ldr r3, [pc, #380] ; (80032a4 ) 8003128: 681b ldr r3, [r3, #0] 800312a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800312e: 2b00 cmp r3, #0 8003130: d1f0 bne.n 8003114 8003132: e000 b.n 8003136 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003134: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8003136: 687b ldr r3, [r7, #4] 8003138: 681b ldr r3, [r3, #0] 800313a: f003 0302 and.w r3, r3, #2 800313e: 2b00 cmp r3, #0 8003140: f000 808a beq.w 8003258 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003144: 4b57 ldr r3, [pc, #348] ; (80032a4 ) 8003146: 691b ldr r3, [r3, #16] 8003148: f003 0338 and.w r3, r3, #56 ; 0x38 800314c: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800314e: 4b55 ldr r3, [pc, #340] ; (80032a4 ) 8003150: 6a9b ldr r3, [r3, #40] ; 0x28 8003152: 61fb str r3, [r7, #28] if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 8003154: 6a3b ldr r3, [r7, #32] 8003156: 2b00 cmp r3, #0 8003158: d007 beq.n 800316a 800315a: 6a3b ldr r3, [r7, #32] 800315c: 2b18 cmp r3, #24 800315e: d137 bne.n 80031d0 8003160: 69fb ldr r3, [r7, #28] 8003162: f003 0303 and.w r3, r3, #3 8003166: 2b00 cmp r3, #0 8003168: d132 bne.n 80031d0 { /* When HSI is used as system clock it will not be disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800316a: 4b4e ldr r3, [pc, #312] ; (80032a4 ) 800316c: 681b ldr r3, [r3, #0] 800316e: f003 0304 and.w r3, r3, #4 8003172: 2b00 cmp r3, #0 8003174: d005 beq.n 8003182 8003176: 687b ldr r3, [r7, #4] 8003178: 68db ldr r3, [r3, #12] 800317a: 2b00 cmp r3, #0 800317c: d101 bne.n 8003182 { return HAL_ERROR; 800317e: 2301 movs r3, #1 8003180: e2e3 b.n 800374a } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 8003182: 4b48 ldr r3, [pc, #288] ; (80032a4 ) 8003184: 681b ldr r3, [r3, #0] 8003186: f023 0219 bic.w r2, r3, #25 800318a: 687b ldr r3, [r7, #4] 800318c: 68db ldr r3, [r3, #12] 800318e: 4945 ldr r1, [pc, #276] ; (80032a4 ) 8003190: 4313 orrs r3, r2 8003192: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003194: f7fe fa04 bl 80015a0 8003198: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800319a: e008 b.n 80031ae { if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 800319c: f7fe fa00 bl 80015a0 80031a0: 4602 mov r2, r0 80031a2: 6a7b ldr r3, [r7, #36] ; 0x24 80031a4: 1ad3 subs r3, r2, r3 80031a6: 2b02 cmp r3, #2 80031a8: d901 bls.n 80031ae { return HAL_TIMEOUT; 80031aa: 2303 movs r3, #3 80031ac: e2cd b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80031ae: 4b3d ldr r3, [pc, #244] ; (80032a4 ) 80031b0: 681b ldr r3, [r3, #0] 80031b2: f003 0304 and.w r3, r3, #4 80031b6: 2b00 cmp r3, #0 80031b8: d0f0 beq.n 800319c } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80031ba: 4b3a ldr r3, [pc, #232] ; (80032a4 ) 80031bc: 685b ldr r3, [r3, #4] 80031be: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 80031c2: 687b ldr r3, [r7, #4] 80031c4: 691b ldr r3, [r3, #16] 80031c6: 061b lsls r3, r3, #24 80031c8: 4936 ldr r1, [pc, #216] ; (80032a4 ) 80031ca: 4313 orrs r3, r2 80031cc: 604b str r3, [r1, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80031ce: e043 b.n 8003258 } else { /* Check the HSI State */ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) 80031d0: 687b ldr r3, [r7, #4] 80031d2: 68db ldr r3, [r3, #12] 80031d4: 2b00 cmp r3, #0 80031d6: d026 beq.n 8003226 { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 80031d8: 4b32 ldr r3, [pc, #200] ; (80032a4 ) 80031da: 681b ldr r3, [r3, #0] 80031dc: f023 0219 bic.w r2, r3, #25 80031e0: 687b ldr r3, [r7, #4] 80031e2: 68db ldr r3, [r3, #12] 80031e4: 492f ldr r1, [pc, #188] ; (80032a4 ) 80031e6: 4313 orrs r3, r2 80031e8: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80031ea: f7fe f9d9 bl 80015a0 80031ee: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80031f0: e008 b.n 8003204 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 80031f2: f7fe f9d5 bl 80015a0 80031f6: 4602 mov r2, r0 80031f8: 6a7b ldr r3, [r7, #36] ; 0x24 80031fa: 1ad3 subs r3, r2, r3 80031fc: 2b02 cmp r3, #2 80031fe: d901 bls.n 8003204 { return HAL_TIMEOUT; 8003200: 2303 movs r3, #3 8003202: e2a2 b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8003204: 4b27 ldr r3, [pc, #156] ; (80032a4 ) 8003206: 681b ldr r3, [r3, #0] 8003208: f003 0304 and.w r3, r3, #4 800320c: 2b00 cmp r3, #0 800320e: d0f0 beq.n 80031f2 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003210: 4b24 ldr r3, [pc, #144] ; (80032a4 ) 8003212: 685b ldr r3, [r3, #4] 8003214: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 8003218: 687b ldr r3, [r7, #4] 800321a: 691b ldr r3, [r3, #16] 800321c: 061b lsls r3, r3, #24 800321e: 4921 ldr r1, [pc, #132] ; (80032a4 ) 8003220: 4313 orrs r3, r2 8003222: 604b str r3, [r1, #4] 8003224: e018 b.n 8003258 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8003226: 4b1f ldr r3, [pc, #124] ; (80032a4 ) 8003228: 681b ldr r3, [r3, #0] 800322a: 4a1e ldr r2, [pc, #120] ; (80032a4 ) 800322c: f023 0301 bic.w r3, r3, #1 8003230: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003232: f7fe f9b5 bl 80015a0 8003236: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8003238: e008 b.n 800324c { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 800323a: f7fe f9b1 bl 80015a0 800323e: 4602 mov r2, r0 8003240: 6a7b ldr r3, [r7, #36] ; 0x24 8003242: 1ad3 subs r3, r2, r3 8003244: 2b02 cmp r3, #2 8003246: d901 bls.n 800324c { return HAL_TIMEOUT; 8003248: 2303 movs r3, #3 800324a: e27e b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800324c: 4b15 ldr r3, [pc, #84] ; (80032a4 ) 800324e: 681b ldr r3, [r3, #0] 8003250: f003 0304 and.w r3, r3, #4 8003254: 2b00 cmp r3, #0 8003256: d1f0 bne.n 800323a } } } } /*----------------------------- CSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 8003258: 687b ldr r3, [r7, #4] 800325a: 681b ldr r3, [r3, #0] 800325c: f003 0310 and.w r3, r3, #16 8003260: 2b00 cmp r3, #0 8003262: d06d beq.n 8003340 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003264: 4b0f ldr r3, [pc, #60] ; (80032a4 ) 8003266: 691b ldr r3, [r3, #16] 8003268: f003 0338 and.w r3, r3, #56 ; 0x38 800326c: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800326e: 4b0d ldr r3, [pc, #52] ; (80032a4 ) 8003270: 6a9b ldr r3, [r3, #40] ; 0x28 8003272: 617b str r3, [r7, #20] if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 8003274: 69bb ldr r3, [r7, #24] 8003276: 2b08 cmp r3, #8 8003278: d007 beq.n 800328a 800327a: 69bb ldr r3, [r7, #24] 800327c: 2b18 cmp r3, #24 800327e: d11e bne.n 80032be 8003280: 697b ldr r3, [r7, #20] 8003282: f003 0303 and.w r3, r3, #3 8003286: 2b01 cmp r3, #1 8003288: d119 bne.n 80032be { /* When CSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800328a: 4b06 ldr r3, [pc, #24] ; (80032a4 ) 800328c: 681b ldr r3, [r3, #0] 800328e: f403 7380 and.w r3, r3, #256 ; 0x100 8003292: 2b00 cmp r3, #0 8003294: d008 beq.n 80032a8 8003296: 687b ldr r3, [r7, #4] 8003298: 69db ldr r3, [r3, #28] 800329a: 2b80 cmp r3, #128 ; 0x80 800329c: d004 beq.n 80032a8 { return HAL_ERROR; 800329e: 2301 movs r3, #1 80032a0: e253 b.n 800374a 80032a2: bf00 nop 80032a4: 58024400 .word 0x58024400 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80032a8: 4ba3 ldr r3, [pc, #652] ; (8003538 ) 80032aa: 68db ldr r3, [r3, #12] 80032ac: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 80032b0: 687b ldr r3, [r7, #4] 80032b2: 6a1b ldr r3, [r3, #32] 80032b4: 061b lsls r3, r3, #24 80032b6: 49a0 ldr r1, [pc, #640] ; (8003538 ) 80032b8: 4313 orrs r3, r2 80032ba: 60cb str r3, [r1, #12] if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80032bc: e040 b.n 8003340 } } else { /* Check the CSI State */ if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF) 80032be: 687b ldr r3, [r7, #4] 80032c0: 69db ldr r3, [r3, #28] 80032c2: 2b00 cmp r3, #0 80032c4: d023 beq.n 800330e { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 80032c6: 4b9c ldr r3, [pc, #624] ; (8003538 ) 80032c8: 681b ldr r3, [r3, #0] 80032ca: 4a9b ldr r2, [pc, #620] ; (8003538 ) 80032cc: f043 0380 orr.w r3, r3, #128 ; 0x80 80032d0: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80032d2: f7fe f965 bl 80015a0 80032d6: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80032d8: e008 b.n 80032ec { if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) 80032da: f7fe f961 bl 80015a0 80032de: 4602 mov r2, r0 80032e0: 6a7b ldr r3, [r7, #36] ; 0x24 80032e2: 1ad3 subs r3, r2, r3 80032e4: 2b02 cmp r3, #2 80032e6: d901 bls.n 80032ec { return HAL_TIMEOUT; 80032e8: 2303 movs r3, #3 80032ea: e22e b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80032ec: 4b92 ldr r3, [pc, #584] ; (8003538 ) 80032ee: 681b ldr r3, [r3, #0] 80032f0: f403 7380 and.w r3, r3, #256 ; 0x100 80032f4: 2b00 cmp r3, #0 80032f6: d0f0 beq.n 80032da } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80032f8: 4b8f ldr r3, [pc, #572] ; (8003538 ) 80032fa: 68db ldr r3, [r3, #12] 80032fc: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 8003300: 687b ldr r3, [r7, #4] 8003302: 6a1b ldr r3, [r3, #32] 8003304: 061b lsls r3, r3, #24 8003306: 498c ldr r1, [pc, #560] ; (8003538 ) 8003308: 4313 orrs r3, r2 800330a: 60cb str r3, [r1, #12] 800330c: e018 b.n 8003340 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800330e: 4b8a ldr r3, [pc, #552] ; (8003538 ) 8003310: 681b ldr r3, [r3, #0] 8003312: 4a89 ldr r2, [pc, #548] ; (8003538 ) 8003314: f023 0380 bic.w r3, r3, #128 ; 0x80 8003318: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800331a: f7fe f941 bl 80015a0 800331e: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 8003320: e008 b.n 8003334 { if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) 8003322: f7fe f93d bl 80015a0 8003326: 4602 mov r2, r0 8003328: 6a7b ldr r3, [r7, #36] ; 0x24 800332a: 1ad3 subs r3, r2, r3 800332c: 2b02 cmp r3, #2 800332e: d901 bls.n 8003334 { return HAL_TIMEOUT; 8003330: 2303 movs r3, #3 8003332: e20a b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 8003334: 4b80 ldr r3, [pc, #512] ; (8003538 ) 8003336: 681b ldr r3, [r3, #0] 8003338: f403 7380 and.w r3, r3, #256 ; 0x100 800333c: 2b00 cmp r3, #0 800333e: d1f0 bne.n 8003322 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8003340: 687b ldr r3, [r7, #4] 8003342: 681b ldr r3, [r3, #0] 8003344: f003 0308 and.w r3, r3, #8 8003348: 2b00 cmp r3, #0 800334a: d036 beq.n 80033ba { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) 800334c: 687b ldr r3, [r7, #4] 800334e: 695b ldr r3, [r3, #20] 8003350: 2b00 cmp r3, #0 8003352: d019 beq.n 8003388 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8003354: 4b78 ldr r3, [pc, #480] ; (8003538 ) 8003356: 6f5b ldr r3, [r3, #116] ; 0x74 8003358: 4a77 ldr r2, [pc, #476] ; (8003538 ) 800335a: f043 0301 orr.w r3, r3, #1 800335e: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003360: f7fe f91e bl 80015a0 8003364: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 8003366: e008 b.n 800337a { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8003368: f7fe f91a bl 80015a0 800336c: 4602 mov r2, r0 800336e: 6a7b ldr r3, [r7, #36] ; 0x24 8003370: 1ad3 subs r3, r2, r3 8003372: 2b02 cmp r3, #2 8003374: d901 bls.n 800337a { return HAL_TIMEOUT; 8003376: 2303 movs r3, #3 8003378: e1e7 b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800337a: 4b6f ldr r3, [pc, #444] ; (8003538 ) 800337c: 6f5b ldr r3, [r3, #116] ; 0x74 800337e: f003 0302 and.w r3, r3, #2 8003382: 2b00 cmp r3, #0 8003384: d0f0 beq.n 8003368 8003386: e018 b.n 80033ba } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8003388: 4b6b ldr r3, [pc, #428] ; (8003538 ) 800338a: 6f5b ldr r3, [r3, #116] ; 0x74 800338c: 4a6a ldr r2, [pc, #424] ; (8003538 ) 800338e: f023 0301 bic.w r3, r3, #1 8003392: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003394: f7fe f904 bl 80015a0 8003398: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800339a: e008 b.n 80033ae { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 800339c: f7fe f900 bl 80015a0 80033a0: 4602 mov r2, r0 80033a2: 6a7b ldr r3, [r7, #36] ; 0x24 80033a4: 1ad3 subs r3, r2, r3 80033a6: 2b02 cmp r3, #2 80033a8: d901 bls.n 80033ae { return HAL_TIMEOUT; 80033aa: 2303 movs r3, #3 80033ac: e1cd b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 80033ae: 4b62 ldr r3, [pc, #392] ; (8003538 ) 80033b0: 6f5b ldr r3, [r3, #116] ; 0x74 80033b2: f003 0302 and.w r3, r3, #2 80033b6: 2b00 cmp r3, #0 80033b8: d1f0 bne.n 800339c } } } /*------------------------------ HSI48 Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 80033ba: 687b ldr r3, [r7, #4] 80033bc: 681b ldr r3, [r3, #0] 80033be: f003 0320 and.w r3, r3, #32 80033c2: 2b00 cmp r3, #0 80033c4: d036 beq.n 8003434 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF) 80033c6: 687b ldr r3, [r7, #4] 80033c8: 699b ldr r3, [r3, #24] 80033ca: 2b00 cmp r3, #0 80033cc: d019 beq.n 8003402 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 80033ce: 4b5a ldr r3, [pc, #360] ; (8003538 ) 80033d0: 681b ldr r3, [r3, #0] 80033d2: 4a59 ldr r2, [pc, #356] ; (8003538 ) 80033d4: f443 5380 orr.w r3, r3, #4096 ; 0x1000 80033d8: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 80033da: f7fe f8e1 bl 80015a0 80033de: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 80033e0: e008 b.n 80033f4 { if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) 80033e2: f7fe f8dd bl 80015a0 80033e6: 4602 mov r2, r0 80033e8: 6a7b ldr r3, [r7, #36] ; 0x24 80033ea: 1ad3 subs r3, r2, r3 80033ec: 2b02 cmp r3, #2 80033ee: d901 bls.n 80033f4 { return HAL_TIMEOUT; 80033f0: 2303 movs r3, #3 80033f2: e1aa b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 80033f4: 4b50 ldr r3, [pc, #320] ; (8003538 ) 80033f6: 681b ldr r3, [r3, #0] 80033f8: f403 5300 and.w r3, r3, #8192 ; 0x2000 80033fc: 2b00 cmp r3, #0 80033fe: d0f0 beq.n 80033e2 8003400: e018 b.n 8003434 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 8003402: 4b4d ldr r3, [pc, #308] ; (8003538 ) 8003404: 681b ldr r3, [r3, #0] 8003406: 4a4c ldr r2, [pc, #304] ; (8003538 ) 8003408: f423 5380 bic.w r3, r3, #4096 ; 0x1000 800340c: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800340e: f7fe f8c7 bl 80015a0 8003412: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 8003414: e008 b.n 8003428 { if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) 8003416: f7fe f8c3 bl 80015a0 800341a: 4602 mov r2, r0 800341c: 6a7b ldr r3, [r7, #36] ; 0x24 800341e: 1ad3 subs r3, r2, r3 8003420: 2b02 cmp r3, #2 8003422: d901 bls.n 8003428 { return HAL_TIMEOUT; 8003424: 2303 movs r3, #3 8003426: e190 b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 8003428: 4b43 ldr r3, [pc, #268] ; (8003538 ) 800342a: 681b ldr r3, [r3, #0] 800342c: f403 5300 and.w r3, r3, #8192 ; 0x2000 8003430: 2b00 cmp r3, #0 8003432: d1f0 bne.n 8003416 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8003434: 687b ldr r3, [r7, #4] 8003436: 681b ldr r3, [r3, #0] 8003438: f003 0304 and.w r3, r3, #4 800343c: 2b00 cmp r3, #0 800343e: f000 8085 beq.w 800354c { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 8003442: 4b3e ldr r3, [pc, #248] ; (800353c ) 8003444: 681b ldr r3, [r3, #0] 8003446: 4a3d ldr r2, [pc, #244] ; (800353c ) 8003448: f443 7380 orr.w r3, r3, #256 ; 0x100 800344c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800344e: f7fe f8a7 bl 80015a0 8003452: 6278 str r0, [r7, #36] ; 0x24 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003454: e008 b.n 8003468 { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) 8003456: f7fe f8a3 bl 80015a0 800345a: 4602 mov r2, r0 800345c: 6a7b ldr r3, [r7, #36] ; 0x24 800345e: 1ad3 subs r3, r2, r3 8003460: 2b64 cmp r3, #100 ; 0x64 8003462: d901 bls.n 8003468 { return HAL_TIMEOUT; 8003464: 2303 movs r3, #3 8003466: e170 b.n 800374a while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003468: 4b34 ldr r3, [pc, #208] ; (800353c ) 800346a: 681b ldr r3, [r3, #0] 800346c: f403 7380 and.w r3, r3, #256 ; 0x100 8003470: 2b00 cmp r3, #0 8003472: d0f0 beq.n 8003456 } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8003474: 687b ldr r3, [r7, #4] 8003476: 689b ldr r3, [r3, #8] 8003478: 2b01 cmp r3, #1 800347a: d106 bne.n 800348a 800347c: 4b2e ldr r3, [pc, #184] ; (8003538 ) 800347e: 6f1b ldr r3, [r3, #112] ; 0x70 8003480: 4a2d ldr r2, [pc, #180] ; (8003538 ) 8003482: f043 0301 orr.w r3, r3, #1 8003486: 6713 str r3, [r2, #112] ; 0x70 8003488: e02d b.n 80034e6 800348a: 687b ldr r3, [r7, #4] 800348c: 689b ldr r3, [r3, #8] 800348e: 2b00 cmp r3, #0 8003490: d10c bne.n 80034ac 8003492: 4b29 ldr r3, [pc, #164] ; (8003538 ) 8003494: 6f1b ldr r3, [r3, #112] ; 0x70 8003496: 4a28 ldr r2, [pc, #160] ; (8003538 ) 8003498: f023 0301 bic.w r3, r3, #1 800349c: 6713 str r3, [r2, #112] ; 0x70 800349e: 4b26 ldr r3, [pc, #152] ; (8003538 ) 80034a0: 6f1b ldr r3, [r3, #112] ; 0x70 80034a2: 4a25 ldr r2, [pc, #148] ; (8003538 ) 80034a4: f023 0304 bic.w r3, r3, #4 80034a8: 6713 str r3, [r2, #112] ; 0x70 80034aa: e01c b.n 80034e6 80034ac: 687b ldr r3, [r7, #4] 80034ae: 689b ldr r3, [r3, #8] 80034b0: 2b05 cmp r3, #5 80034b2: d10c bne.n 80034ce 80034b4: 4b20 ldr r3, [pc, #128] ; (8003538 ) 80034b6: 6f1b ldr r3, [r3, #112] ; 0x70 80034b8: 4a1f ldr r2, [pc, #124] ; (8003538 ) 80034ba: f043 0304 orr.w r3, r3, #4 80034be: 6713 str r3, [r2, #112] ; 0x70 80034c0: 4b1d ldr r3, [pc, #116] ; (8003538 ) 80034c2: 6f1b ldr r3, [r3, #112] ; 0x70 80034c4: 4a1c ldr r2, [pc, #112] ; (8003538 ) 80034c6: f043 0301 orr.w r3, r3, #1 80034ca: 6713 str r3, [r2, #112] ; 0x70 80034cc: e00b b.n 80034e6 80034ce: 4b1a ldr r3, [pc, #104] ; (8003538 ) 80034d0: 6f1b ldr r3, [r3, #112] ; 0x70 80034d2: 4a19 ldr r2, [pc, #100] ; (8003538 ) 80034d4: f023 0301 bic.w r3, r3, #1 80034d8: 6713 str r3, [r2, #112] ; 0x70 80034da: 4b17 ldr r3, [pc, #92] ; (8003538 ) 80034dc: 6f1b ldr r3, [r3, #112] ; 0x70 80034de: 4a16 ldr r2, [pc, #88] ; (8003538 ) 80034e0: f023 0304 bic.w r3, r3, #4 80034e4: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 80034e6: 687b ldr r3, [r7, #4] 80034e8: 689b ldr r3, [r3, #8] 80034ea: 2b00 cmp r3, #0 80034ec: d015 beq.n 800351a { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80034ee: f7fe f857 bl 80015a0 80034f2: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 80034f4: e00a b.n 800350c { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 80034f6: f7fe f853 bl 80015a0 80034fa: 4602 mov r2, r0 80034fc: 6a7b ldr r3, [r7, #36] ; 0x24 80034fe: 1ad3 subs r3, r2, r3 8003500: f241 3288 movw r2, #5000 ; 0x1388 8003504: 4293 cmp r3, r2 8003506: d901 bls.n 800350c { return HAL_TIMEOUT; 8003508: 2303 movs r3, #3 800350a: e11e b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800350c: 4b0a ldr r3, [pc, #40] ; (8003538 ) 800350e: 6f1b ldr r3, [r3, #112] ; 0x70 8003510: f003 0302 and.w r3, r3, #2 8003514: 2b00 cmp r3, #0 8003516: d0ee beq.n 80034f6 8003518: e018 b.n 800354c } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800351a: f7fe f841 bl 80015a0 800351e: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8003520: e00e b.n 8003540 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8003522: f7fe f83d bl 80015a0 8003526: 4602 mov r2, r0 8003528: 6a7b ldr r3, [r7, #36] ; 0x24 800352a: 1ad3 subs r3, r2, r3 800352c: f241 3288 movw r2, #5000 ; 0x1388 8003530: 4293 cmp r3, r2 8003532: d905 bls.n 8003540 { return HAL_TIMEOUT; 8003534: 2303 movs r3, #3 8003536: e108 b.n 800374a 8003538: 58024400 .word 0x58024400 800353c: 58024800 .word 0x58024800 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8003540: 4b84 ldr r3, [pc, #528] ; (8003754 ) 8003542: 6f1b ldr r3, [r3, #112] ; 0x70 8003544: f003 0302 and.w r3, r3, #2 8003548: 2b00 cmp r3, #0 800354a: d1ea bne.n 8003522 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800354c: 687b ldr r3, [r7, #4] 800354e: 6a5b ldr r3, [r3, #36] ; 0x24 8003550: 2b00 cmp r3, #0 8003552: f000 80f9 beq.w 8003748 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 8003556: 4b7f ldr r3, [pc, #508] ; (8003754 ) 8003558: 691b ldr r3, [r3, #16] 800355a: f003 0338 and.w r3, r3, #56 ; 0x38 800355e: 2b18 cmp r3, #24 8003560: f000 80b4 beq.w 80036cc { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8003564: 687b ldr r3, [r7, #4] 8003566: 6a5b ldr r3, [r3, #36] ; 0x24 8003568: 2b02 cmp r3, #2 800356a: f040 8095 bne.w 8003698 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800356e: 4b79 ldr r3, [pc, #484] ; (8003754 ) 8003570: 681b ldr r3, [r3, #0] 8003572: 4a78 ldr r2, [pc, #480] ; (8003754 ) 8003574: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8003578: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800357a: f7fe f811 bl 80015a0 800357e: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8003580: e008 b.n 8003594 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8003582: f7fe f80d bl 80015a0 8003586: 4602 mov r2, r0 8003588: 6a7b ldr r3, [r7, #36] ; 0x24 800358a: 1ad3 subs r3, r2, r3 800358c: 2b02 cmp r3, #2 800358e: d901 bls.n 8003594 { return HAL_TIMEOUT; 8003590: 2303 movs r3, #3 8003592: e0da b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8003594: 4b6f ldr r3, [pc, #444] ; (8003754 ) 8003596: 681b ldr r3, [r3, #0] 8003598: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800359c: 2b00 cmp r3, #0 800359e: d1f0 bne.n 8003582 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80035a0: 4b6c ldr r3, [pc, #432] ; (8003754 ) 80035a2: 6a9a ldr r2, [r3, #40] ; 0x28 80035a4: 4b6c ldr r3, [pc, #432] ; (8003758 ) 80035a6: 4013 ands r3, r2 80035a8: 687a ldr r2, [r7, #4] 80035aa: 6a91 ldr r1, [r2, #40] ; 0x28 80035ac: 687a ldr r2, [r7, #4] 80035ae: 6ad2 ldr r2, [r2, #44] ; 0x2c 80035b0: 0112 lsls r2, r2, #4 80035b2: 430a orrs r2, r1 80035b4: 4967 ldr r1, [pc, #412] ; (8003754 ) 80035b6: 4313 orrs r3, r2 80035b8: 628b str r3, [r1, #40] ; 0x28 80035ba: 687b ldr r3, [r7, #4] 80035bc: 6b1b ldr r3, [r3, #48] ; 0x30 80035be: 3b01 subs r3, #1 80035c0: f3c3 0208 ubfx r2, r3, #0, #9 80035c4: 687b ldr r3, [r7, #4] 80035c6: 6b5b ldr r3, [r3, #52] ; 0x34 80035c8: 3b01 subs r3, #1 80035ca: 025b lsls r3, r3, #9 80035cc: b29b uxth r3, r3 80035ce: 431a orrs r2, r3 80035d0: 687b ldr r3, [r7, #4] 80035d2: 6b9b ldr r3, [r3, #56] ; 0x38 80035d4: 3b01 subs r3, #1 80035d6: 041b lsls r3, r3, #16 80035d8: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 80035dc: 431a orrs r2, r3 80035de: 687b ldr r3, [r7, #4] 80035e0: 6bdb ldr r3, [r3, #60] ; 0x3c 80035e2: 3b01 subs r3, #1 80035e4: 061b lsls r3, r3, #24 80035e6: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 80035ea: 495a ldr r1, [pc, #360] ; (8003754 ) 80035ec: 4313 orrs r3, r2 80035ee: 630b str r3, [r1, #48] ; 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 80035f0: 4b58 ldr r3, [pc, #352] ; (8003754 ) 80035f2: 6adb ldr r3, [r3, #44] ; 0x2c 80035f4: 4a57 ldr r2, [pc, #348] ; (8003754 ) 80035f6: f023 0301 bic.w r3, r3, #1 80035fa: 62d3 str r3, [r2, #44] ; 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 80035fc: 4b55 ldr r3, [pc, #340] ; (8003754 ) 80035fe: 6b5a ldr r2, [r3, #52] ; 0x34 8003600: 4b56 ldr r3, [pc, #344] ; (800375c ) 8003602: 4013 ands r3, r2 8003604: 687a ldr r2, [r7, #4] 8003606: 6c92 ldr r2, [r2, #72] ; 0x48 8003608: 00d2 lsls r2, r2, #3 800360a: 4952 ldr r1, [pc, #328] ; (8003754 ) 800360c: 4313 orrs r3, r2 800360e: 634b str r3, [r1, #52] ; 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 8003610: 4b50 ldr r3, [pc, #320] ; (8003754 ) 8003612: 6adb ldr r3, [r3, #44] ; 0x2c 8003614: f023 020c bic.w r2, r3, #12 8003618: 687b ldr r3, [r7, #4] 800361a: 6c1b ldr r3, [r3, #64] ; 0x40 800361c: 494d ldr r1, [pc, #308] ; (8003754 ) 800361e: 4313 orrs r3, r2 8003620: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 8003622: 4b4c ldr r3, [pc, #304] ; (8003754 ) 8003624: 6adb ldr r3, [r3, #44] ; 0x2c 8003626: f023 0202 bic.w r2, r3, #2 800362a: 687b ldr r3, [r7, #4] 800362c: 6c5b ldr r3, [r3, #68] ; 0x44 800362e: 4949 ldr r1, [pc, #292] ; (8003754 ) 8003630: 4313 orrs r3, r2 8003632: 62cb str r3, [r1, #44] ; 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 8003634: 4b47 ldr r3, [pc, #284] ; (8003754 ) 8003636: 6adb ldr r3, [r3, #44] ; 0x2c 8003638: 4a46 ldr r2, [pc, #280] ; (8003754 ) 800363a: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800363e: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003640: 4b44 ldr r3, [pc, #272] ; (8003754 ) 8003642: 6adb ldr r3, [r3, #44] ; 0x2c 8003644: 4a43 ldr r2, [pc, #268] ; (8003754 ) 8003646: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800364a: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 800364c: 4b41 ldr r3, [pc, #260] ; (8003754 ) 800364e: 6adb ldr r3, [r3, #44] ; 0x2c 8003650: 4a40 ldr r2, [pc, #256] ; (8003754 ) 8003652: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8003656: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 8003658: 4b3e ldr r3, [pc, #248] ; (8003754 ) 800365a: 6adb ldr r3, [r3, #44] ; 0x2c 800365c: 4a3d ldr r2, [pc, #244] ; (8003754 ) 800365e: f043 0301 orr.w r3, r3, #1 8003662: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8003664: 4b3b ldr r3, [pc, #236] ; (8003754 ) 8003666: 681b ldr r3, [r3, #0] 8003668: 4a3a ldr r2, [pc, #232] ; (8003754 ) 800366a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 800366e: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003670: f7fd ff96 bl 80015a0 8003674: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8003676: e008 b.n 800368a { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8003678: f7fd ff92 bl 80015a0 800367c: 4602 mov r2, r0 800367e: 6a7b ldr r3, [r7, #36] ; 0x24 8003680: 1ad3 subs r3, r2, r3 8003682: 2b02 cmp r3, #2 8003684: d901 bls.n 800368a { return HAL_TIMEOUT; 8003686: 2303 movs r3, #3 8003688: e05f b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800368a: 4b32 ldr r3, [pc, #200] ; (8003754 ) 800368c: 681b ldr r3, [r3, #0] 800368e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003692: 2b00 cmp r3, #0 8003694: d0f0 beq.n 8003678 8003696: e057 b.n 8003748 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003698: 4b2e ldr r3, [pc, #184] ; (8003754 ) 800369a: 681b ldr r3, [r3, #0] 800369c: 4a2d ldr r2, [pc, #180] ; (8003754 ) 800369e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 80036a2: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80036a4: f7fd ff7c bl 80015a0 80036a8: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80036aa: e008 b.n 80036be { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 80036ac: f7fd ff78 bl 80015a0 80036b0: 4602 mov r2, r0 80036b2: 6a7b ldr r3, [r7, #36] ; 0x24 80036b4: 1ad3 subs r3, r2, r3 80036b6: 2b02 cmp r3, #2 80036b8: d901 bls.n 80036be { return HAL_TIMEOUT; 80036ba: 2303 movs r3, #3 80036bc: e045 b.n 800374a while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80036be: 4b25 ldr r3, [pc, #148] ; (8003754 ) 80036c0: 681b ldr r3, [r3, #0] 80036c2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80036c6: 2b00 cmp r3, #0 80036c8: d1f0 bne.n 80036ac 80036ca: e03d b.n 8003748 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 80036cc: 4b21 ldr r3, [pc, #132] ; (8003754 ) 80036ce: 6a9b ldr r3, [r3, #40] ; 0x28 80036d0: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 80036d2: 4b20 ldr r3, [pc, #128] ; (8003754 ) 80036d4: 6b1b ldr r3, [r3, #48] ; 0x30 80036d6: 60fb str r3, [r7, #12] if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80036d8: 687b ldr r3, [r7, #4] 80036da: 6a5b ldr r3, [r3, #36] ; 0x24 80036dc: 2b01 cmp r3, #1 80036de: d031 beq.n 8003744 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80036e0: 693b ldr r3, [r7, #16] 80036e2: f003 0203 and.w r2, r3, #3 80036e6: 687b ldr r3, [r7, #4] 80036e8: 6a9b ldr r3, [r3, #40] ; 0x28 if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80036ea: 429a cmp r2, r3 80036ec: d12a bne.n 8003744 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 80036ee: 693b ldr r3, [r7, #16] 80036f0: 091b lsrs r3, r3, #4 80036f2: f003 023f and.w r2, r3, #63 ; 0x3f 80036f6: 687b ldr r3, [r7, #4] 80036f8: 6adb ldr r3, [r3, #44] ; 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80036fa: 429a cmp r2, r3 80036fc: d122 bne.n 8003744 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 80036fe: 68fb ldr r3, [r7, #12] 8003700: f3c3 0208 ubfx r2, r3, #0, #9 8003704: 687b ldr r3, [r7, #4] 8003706: 6b1b ldr r3, [r3, #48] ; 0x30 8003708: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800370a: 429a cmp r2, r3 800370c: d11a bne.n 8003744 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800370e: 68fb ldr r3, [r7, #12] 8003710: 0a5b lsrs r3, r3, #9 8003712: f003 027f and.w r2, r3, #127 ; 0x7f 8003716: 687b ldr r3, [r7, #4] 8003718: 6b5b ldr r3, [r3, #52] ; 0x34 800371a: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800371c: 429a cmp r2, r3 800371e: d111 bne.n 8003744 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8003720: 68fb ldr r3, [r7, #12] 8003722: 0c1b lsrs r3, r3, #16 8003724: f003 027f and.w r2, r3, #127 ; 0x7f 8003728: 687b ldr r3, [r7, #4] 800372a: 6b9b ldr r3, [r3, #56] ; 0x38 800372c: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800372e: 429a cmp r2, r3 8003730: d108 bne.n 8003744 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 8003732: 68fb ldr r3, [r7, #12] 8003734: 0e1b lsrs r3, r3, #24 8003736: f003 027f and.w r2, r3, #127 ; 0x7f 800373a: 687b ldr r3, [r7, #4] 800373c: 6bdb ldr r3, [r3, #60] ; 0x3c 800373e: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8003740: 429a cmp r2, r3 8003742: d001 beq.n 8003748 { return HAL_ERROR; 8003744: 2301 movs r3, #1 8003746: e000 b.n 800374a } } } return HAL_OK; 8003748: 2300 movs r3, #0 } 800374a: 4618 mov r0, r3 800374c: 3730 adds r7, #48 ; 0x30 800374e: 46bd mov sp, r7 8003750: bd80 pop {r7, pc} 8003752: bf00 nop 8003754: 58024400 .word 0x58024400 8003758: fffffc0c .word 0xfffffc0c 800375c: ffff0007 .word 0xffff0007 08003760 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003760: b580 push {r7, lr} 8003762: b086 sub sp, #24 8003764: af00 add r7, sp, #0 8003766: 6078 str r0, [r7, #4] 8003768: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 800376a: 687b ldr r3, [r7, #4] 800376c: 2b00 cmp r3, #0 800376e: d101 bne.n 8003774 { return HAL_ERROR; 8003770: 2301 movs r3, #1 8003772: e19c b.n 8003aae /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8003774: 4b8a ldr r3, [pc, #552] ; (80039a0 ) 8003776: 681b ldr r3, [r3, #0] 8003778: f003 030f and.w r3, r3, #15 800377c: 683a ldr r2, [r7, #0] 800377e: 429a cmp r2, r3 8003780: d910 bls.n 80037a4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003782: 4b87 ldr r3, [pc, #540] ; (80039a0 ) 8003784: 681b ldr r3, [r3, #0] 8003786: f023 020f bic.w r2, r3, #15 800378a: 4985 ldr r1, [pc, #532] ; (80039a0 ) 800378c: 683b ldr r3, [r7, #0] 800378e: 4313 orrs r3, r2 8003790: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8003792: 4b83 ldr r3, [pc, #524] ; (80039a0 ) 8003794: 681b ldr r3, [r3, #0] 8003796: f003 030f and.w r3, r3, #15 800379a: 683a ldr r2, [r7, #0] 800379c: 429a cmp r2, r3 800379e: d001 beq.n 80037a4 { return HAL_ERROR; 80037a0: 2301 movs r3, #1 80037a2: e184 b.n 8003aae } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 80037a4: 687b ldr r3, [r7, #4] 80037a6: 681b ldr r3, [r3, #0] 80037a8: f003 0304 and.w r3, r3, #4 80037ac: 2b00 cmp r3, #0 80037ae: d010 beq.n 80037d2 { #if defined (RCC_D1CFGR_D1PPRE) if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 80037b0: 687b ldr r3, [r7, #4] 80037b2: 691a ldr r2, [r3, #16] 80037b4: 4b7b ldr r3, [pc, #492] ; (80039a4 ) 80037b6: 699b ldr r3, [r3, #24] 80037b8: f003 0370 and.w r3, r3, #112 ; 0x70 80037bc: 429a cmp r2, r3 80037be: d908 bls.n 80037d2 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 80037c0: 4b78 ldr r3, [pc, #480] ; (80039a4 ) 80037c2: 699b ldr r3, [r3, #24] 80037c4: f023 0270 bic.w r2, r3, #112 ; 0x70 80037c8: 687b ldr r3, [r7, #4] 80037ca: 691b ldr r3, [r3, #16] 80037cc: 4975 ldr r1, [pc, #468] ; (80039a4 ) 80037ce: 4313 orrs r3, r2 80037d0: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80037d2: 687b ldr r3, [r7, #4] 80037d4: 681b ldr r3, [r3, #0] 80037d6: f003 0308 and.w r3, r3, #8 80037da: 2b00 cmp r3, #0 80037dc: d010 beq.n 8003800 { #if defined (RCC_D2CFGR_D2PPRE1) if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 80037de: 687b ldr r3, [r7, #4] 80037e0: 695a ldr r2, [r3, #20] 80037e2: 4b70 ldr r3, [pc, #448] ; (80039a4 ) 80037e4: 69db ldr r3, [r3, #28] 80037e6: f003 0370 and.w r3, r3, #112 ; 0x70 80037ea: 429a cmp r2, r3 80037ec: d908 bls.n 8003800 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 80037ee: 4b6d ldr r3, [pc, #436] ; (80039a4 ) 80037f0: 69db ldr r3, [r3, #28] 80037f2: f023 0270 bic.w r2, r3, #112 ; 0x70 80037f6: 687b ldr r3, [r7, #4] 80037f8: 695b ldr r3, [r3, #20] 80037fa: 496a ldr r1, [pc, #424] ; (80039a4 ) 80037fc: 4313 orrs r3, r2 80037fe: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003800: 687b ldr r3, [r7, #4] 8003802: 681b ldr r3, [r3, #0] 8003804: f003 0310 and.w r3, r3, #16 8003808: 2b00 cmp r3, #0 800380a: d010 beq.n 800382e { #if defined(RCC_D2CFGR_D2PPRE2) if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800380c: 687b ldr r3, [r7, #4] 800380e: 699a ldr r2, [r3, #24] 8003810: 4b64 ldr r3, [pc, #400] ; (80039a4 ) 8003812: 69db ldr r3, [r3, #28] 8003814: f403 63e0 and.w r3, r3, #1792 ; 0x700 8003818: 429a cmp r2, r3 800381a: d908 bls.n 800382e { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800381c: 4b61 ldr r3, [pc, #388] ; (80039a4 ) 800381e: 69db ldr r3, [r3, #28] 8003820: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8003824: 687b ldr r3, [r7, #4] 8003826: 699b ldr r3, [r3, #24] 8003828: 495e ldr r1, [pc, #376] ; (80039a4 ) 800382a: 4313 orrs r3, r2 800382c: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800382e: 687b ldr r3, [r7, #4] 8003830: 681b ldr r3, [r3, #0] 8003832: f003 0320 and.w r3, r3, #32 8003836: 2b00 cmp r3, #0 8003838: d010 beq.n 800385c { #if defined(RCC_D3CFGR_D3PPRE) if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800383a: 687b ldr r3, [r7, #4] 800383c: 69da ldr r2, [r3, #28] 800383e: 4b59 ldr r3, [pc, #356] ; (80039a4 ) 8003840: 6a1b ldr r3, [r3, #32] 8003842: f003 0370 and.w r3, r3, #112 ; 0x70 8003846: 429a cmp r2, r3 8003848: d908 bls.n 800385c { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); 800384a: 4b56 ldr r3, [pc, #344] ; (80039a4 ) 800384c: 6a1b ldr r3, [r3, #32] 800384e: f023 0270 bic.w r2, r3, #112 ; 0x70 8003852: 687b ldr r3, [r7, #4] 8003854: 69db ldr r3, [r3, #28] 8003856: 4953 ldr r1, [pc, #332] ; (80039a4 ) 8003858: 4313 orrs r3, r2 800385a: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800385c: 687b ldr r3, [r7, #4] 800385e: 681b ldr r3, [r3, #0] 8003860: f003 0302 and.w r3, r3, #2 8003864: 2b00 cmp r3, #0 8003866: d010 beq.n 800388a { #if defined (RCC_D1CFGR_HPRE) if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 8003868: 687b ldr r3, [r7, #4] 800386a: 68da ldr r2, [r3, #12] 800386c: 4b4d ldr r3, [pc, #308] ; (80039a4 ) 800386e: 699b ldr r3, [r3, #24] 8003870: f003 030f and.w r3, r3, #15 8003874: 429a cmp r2, r3 8003876: d908 bls.n 800388a { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003878: 4b4a ldr r3, [pc, #296] ; (80039a4 ) 800387a: 699b ldr r3, [r3, #24] 800387c: f023 020f bic.w r2, r3, #15 8003880: 687b ldr r3, [r7, #4] 8003882: 68db ldr r3, [r3, #12] 8003884: 4947 ldr r1, [pc, #284] ; (80039a4 ) 8003886: 4313 orrs r3, r2 8003888: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800388a: 687b ldr r3, [r7, #4] 800388c: 681b ldr r3, [r3, #0] 800388e: f003 0301 and.w r3, r3, #1 8003892: 2b00 cmp r3, #0 8003894: d055 beq.n 8003942 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 8003896: 4b43 ldr r3, [pc, #268] ; (80039a4 ) 8003898: 699b ldr r3, [r3, #24] 800389a: f423 6270 bic.w r2, r3, #3840 ; 0xf00 800389e: 687b ldr r3, [r7, #4] 80038a0: 689b ldr r3, [r3, #8] 80038a2: 4940 ldr r1, [pc, #256] ; (80039a4 ) 80038a4: 4313 orrs r3, r2 80038a6: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80038a8: 687b ldr r3, [r7, #4] 80038aa: 685b ldr r3, [r3, #4] 80038ac: 2b02 cmp r3, #2 80038ae: d107 bne.n 80038c0 { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80038b0: 4b3c ldr r3, [pc, #240] ; (80039a4 ) 80038b2: 681b ldr r3, [r3, #0] 80038b4: f403 3300 and.w r3, r3, #131072 ; 0x20000 80038b8: 2b00 cmp r3, #0 80038ba: d121 bne.n 8003900 { return HAL_ERROR; 80038bc: 2301 movs r3, #1 80038be: e0f6 b.n 8003aae } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80038c0: 687b ldr r3, [r7, #4] 80038c2: 685b ldr r3, [r3, #4] 80038c4: 2b03 cmp r3, #3 80038c6: d107 bne.n 80038d8 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 80038c8: 4b36 ldr r3, [pc, #216] ; (80039a4 ) 80038ca: 681b ldr r3, [r3, #0] 80038cc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80038d0: 2b00 cmp r3, #0 80038d2: d115 bne.n 8003900 { return HAL_ERROR; 80038d4: 2301 movs r3, #1 80038d6: e0ea b.n 8003aae } } /* CSI is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 80038d8: 687b ldr r3, [r7, #4] 80038da: 685b ldr r3, [r3, #4] 80038dc: 2b01 cmp r3, #1 80038de: d107 bne.n 80038f0 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80038e0: 4b30 ldr r3, [pc, #192] ; (80039a4 ) 80038e2: 681b ldr r3, [r3, #0] 80038e4: f403 7380 and.w r3, r3, #256 ; 0x100 80038e8: 2b00 cmp r3, #0 80038ea: d109 bne.n 8003900 { return HAL_ERROR; 80038ec: 2301 movs r3, #1 80038ee: e0de b.n 8003aae } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80038f0: 4b2c ldr r3, [pc, #176] ; (80039a4 ) 80038f2: 681b ldr r3, [r3, #0] 80038f4: f003 0304 and.w r3, r3, #4 80038f8: 2b00 cmp r3, #0 80038fa: d101 bne.n 8003900 { return HAL_ERROR; 80038fc: 2301 movs r3, #1 80038fe: e0d6 b.n 8003aae } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8003900: 4b28 ldr r3, [pc, #160] ; (80039a4 ) 8003902: 691b ldr r3, [r3, #16] 8003904: f023 0207 bic.w r2, r3, #7 8003908: 687b ldr r3, [r7, #4] 800390a: 685b ldr r3, [r3, #4] 800390c: 4925 ldr r1, [pc, #148] ; (80039a4 ) 800390e: 4313 orrs r3, r2 8003910: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003912: f7fd fe45 bl 80015a0 8003916: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003918: e00a b.n 8003930 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 800391a: f7fd fe41 bl 80015a0 800391e: 4602 mov r2, r0 8003920: 697b ldr r3, [r7, #20] 8003922: 1ad3 subs r3, r2, r3 8003924: f241 3288 movw r2, #5000 ; 0x1388 8003928: 4293 cmp r3, r2 800392a: d901 bls.n 8003930 { return HAL_TIMEOUT; 800392c: 2303 movs r3, #3 800392e: e0be b.n 8003aae while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003930: 4b1c ldr r3, [pc, #112] ; (80039a4 ) 8003932: 691b ldr r3, [r3, #16] 8003934: f003 0238 and.w r2, r3, #56 ; 0x38 8003938: 687b ldr r3, [r7, #4] 800393a: 685b ldr r3, [r3, #4] 800393c: 00db lsls r3, r3, #3 800393e: 429a cmp r2, r3 8003940: d1eb bne.n 800391a } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003942: 687b ldr r3, [r7, #4] 8003944: 681b ldr r3, [r3, #0] 8003946: f003 0302 and.w r3, r3, #2 800394a: 2b00 cmp r3, #0 800394c: d010 beq.n 8003970 { #if defined(RCC_D1CFGR_HPRE) if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800394e: 687b ldr r3, [r7, #4] 8003950: 68da ldr r2, [r3, #12] 8003952: 4b14 ldr r3, [pc, #80] ; (80039a4 ) 8003954: 699b ldr r3, [r3, #24] 8003956: f003 030f and.w r3, r3, #15 800395a: 429a cmp r2, r3 800395c: d208 bcs.n 8003970 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800395e: 4b11 ldr r3, [pc, #68] ; (80039a4 ) 8003960: 699b ldr r3, [r3, #24] 8003962: f023 020f bic.w r2, r3, #15 8003966: 687b ldr r3, [r7, #4] 8003968: 68db ldr r3, [r3, #12] 800396a: 490e ldr r1, [pc, #56] ; (80039a4 ) 800396c: 4313 orrs r3, r2 800396e: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8003970: 4b0b ldr r3, [pc, #44] ; (80039a0 ) 8003972: 681b ldr r3, [r3, #0] 8003974: f003 030f and.w r3, r3, #15 8003978: 683a ldr r2, [r7, #0] 800397a: 429a cmp r2, r3 800397c: d214 bcs.n 80039a8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800397e: 4b08 ldr r3, [pc, #32] ; (80039a0 ) 8003980: 681b ldr r3, [r3, #0] 8003982: f023 020f bic.w r2, r3, #15 8003986: 4906 ldr r1, [pc, #24] ; (80039a0 ) 8003988: 683b ldr r3, [r7, #0] 800398a: 4313 orrs r3, r2 800398c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 800398e: 4b04 ldr r3, [pc, #16] ; (80039a0 ) 8003990: 681b ldr r3, [r3, #0] 8003992: f003 030f and.w r3, r3, #15 8003996: 683a ldr r2, [r7, #0] 8003998: 429a cmp r2, r3 800399a: d005 beq.n 80039a8 { return HAL_ERROR; 800399c: 2301 movs r3, #1 800399e: e086 b.n 8003aae 80039a0: 52002000 .word 0x52002000 80039a4: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 80039a8: 687b ldr r3, [r7, #4] 80039aa: 681b ldr r3, [r3, #0] 80039ac: f003 0304 and.w r3, r3, #4 80039b0: 2b00 cmp r3, #0 80039b2: d010 beq.n 80039d6 { #if defined(RCC_D1CFGR_D1PPRE) if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 80039b4: 687b ldr r3, [r7, #4] 80039b6: 691a ldr r2, [r3, #16] 80039b8: 4b3f ldr r3, [pc, #252] ; (8003ab8 ) 80039ba: 699b ldr r3, [r3, #24] 80039bc: f003 0370 and.w r3, r3, #112 ; 0x70 80039c0: 429a cmp r2, r3 80039c2: d208 bcs.n 80039d6 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 80039c4: 4b3c ldr r3, [pc, #240] ; (8003ab8 ) 80039c6: 699b ldr r3, [r3, #24] 80039c8: f023 0270 bic.w r2, r3, #112 ; 0x70 80039cc: 687b ldr r3, [r7, #4] 80039ce: 691b ldr r3, [r3, #16] 80039d0: 4939 ldr r1, [pc, #228] ; (8003ab8 ) 80039d2: 4313 orrs r3, r2 80039d4: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80039d6: 687b ldr r3, [r7, #4] 80039d8: 681b ldr r3, [r3, #0] 80039da: f003 0308 and.w r3, r3, #8 80039de: 2b00 cmp r3, #0 80039e0: d010 beq.n 8003a04 { #if defined(RCC_D2CFGR_D2PPRE1) if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 80039e2: 687b ldr r3, [r7, #4] 80039e4: 695a ldr r2, [r3, #20] 80039e6: 4b34 ldr r3, [pc, #208] ; (8003ab8 ) 80039e8: 69db ldr r3, [r3, #28] 80039ea: f003 0370 and.w r3, r3, #112 ; 0x70 80039ee: 429a cmp r2, r3 80039f0: d208 bcs.n 8003a04 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 80039f2: 4b31 ldr r3, [pc, #196] ; (8003ab8 ) 80039f4: 69db ldr r3, [r3, #28] 80039f6: f023 0270 bic.w r2, r3, #112 ; 0x70 80039fa: 687b ldr r3, [r7, #4] 80039fc: 695b ldr r3, [r3, #20] 80039fe: 492e ldr r1, [pc, #184] ; (8003ab8 ) 8003a00: 4313 orrs r3, r2 8003a02: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003a04: 687b ldr r3, [r7, #4] 8003a06: 681b ldr r3, [r3, #0] 8003a08: f003 0310 and.w r3, r3, #16 8003a0c: 2b00 cmp r3, #0 8003a0e: d010 beq.n 8003a32 { #if defined (RCC_D2CFGR_D2PPRE2) if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 8003a10: 687b ldr r3, [r7, #4] 8003a12: 699a ldr r2, [r3, #24] 8003a14: 4b28 ldr r3, [pc, #160] ; (8003ab8 ) 8003a16: 69db ldr r3, [r3, #28] 8003a18: f403 63e0 and.w r3, r3, #1792 ; 0x700 8003a1c: 429a cmp r2, r3 8003a1e: d208 bcs.n 8003a32 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8003a20: 4b25 ldr r3, [pc, #148] ; (8003ab8 ) 8003a22: 69db ldr r3, [r3, #28] 8003a24: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8003a28: 687b ldr r3, [r7, #4] 8003a2a: 699b ldr r3, [r3, #24] 8003a2c: 4922 ldr r1, [pc, #136] ; (8003ab8 ) 8003a2e: 4313 orrs r3, r2 8003a30: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8003a32: 687b ldr r3, [r7, #4] 8003a34: 681b ldr r3, [r3, #0] 8003a36: f003 0320 and.w r3, r3, #32 8003a3a: 2b00 cmp r3, #0 8003a3c: d010 beq.n 8003a60 { #if defined(RCC_D3CFGR_D3PPRE) if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 8003a3e: 687b ldr r3, [r7, #4] 8003a40: 69da ldr r2, [r3, #28] 8003a42: 4b1d ldr r3, [pc, #116] ; (8003ab8 ) 8003a44: 6a1b ldr r3, [r3, #32] 8003a46: f003 0370 and.w r3, r3, #112 ; 0x70 8003a4a: 429a cmp r2, r3 8003a4c: d208 bcs.n 8003a60 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); 8003a4e: 4b1a ldr r3, [pc, #104] ; (8003ab8 ) 8003a50: 6a1b ldr r3, [r3, #32] 8003a52: f023 0270 bic.w r2, r3, #112 ; 0x70 8003a56: 687b ldr r3, [r7, #4] 8003a58: 69db ldr r3, [r3, #28] 8003a5a: 4917 ldr r1, [pc, #92] ; (8003ab8 ) 8003a5c: 4313 orrs r3, r2 8003a5e: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8003a60: f000 f834 bl 8003acc 8003a64: 4602 mov r2, r0 8003a66: 4b14 ldr r3, [pc, #80] ; (8003ab8 ) 8003a68: 699b ldr r3, [r3, #24] 8003a6a: 0a1b lsrs r3, r3, #8 8003a6c: f003 030f and.w r3, r3, #15 8003a70: 4912 ldr r1, [pc, #72] ; (8003abc ) 8003a72: 5ccb ldrb r3, [r1, r3] 8003a74: f003 031f and.w r3, r3, #31 8003a78: fa22 f303 lsr.w r3, r2, r3 8003a7c: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8003a7e: 4b0e ldr r3, [pc, #56] ; (8003ab8 ) 8003a80: 699b ldr r3, [r3, #24] 8003a82: f003 030f and.w r3, r3, #15 8003a86: 4a0d ldr r2, [pc, #52] ; (8003abc ) 8003a88: 5cd3 ldrb r3, [r2, r3] 8003a8a: f003 031f and.w r3, r3, #31 8003a8e: 693a ldr r2, [r7, #16] 8003a90: fa22 f303 lsr.w r3, r2, r3 8003a94: 4a0a ldr r2, [pc, #40] ; (8003ac0 ) 8003a96: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8003a98: 4a0a ldr r2, [pc, #40] ; (8003ac4 ) 8003a9a: 693b ldr r3, [r7, #16] 8003a9c: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick (uwTickPrio); 8003a9e: 4b0a ldr r3, [pc, #40] ; (8003ac8 ) 8003aa0: 681b ldr r3, [r3, #0] 8003aa2: 4618 mov r0, r3 8003aa4: f7fd fd32 bl 800150c 8003aa8: 4603 mov r3, r0 8003aaa: 73fb strb r3, [r7, #15] return halstatus; 8003aac: 7bfb ldrb r3, [r7, #15] } 8003aae: 4618 mov r0, r3 8003ab0: 3718 adds r7, #24 8003ab2: 46bd mov sp, r7 8003ab4: bd80 pop {r7, pc} 8003ab6: bf00 nop 8003ab8: 58024400 .word 0x58024400 8003abc: 0800a958 .word 0x0800a958 8003ac0: 24000004 .word 0x24000004 8003ac4: 24000000 .word 0x24000000 8003ac8: 24000008 .word 0x24000008 08003acc : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8003acc: b480 push {r7} 8003ace: b089 sub sp, #36 ; 0x24 8003ad0: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8003ad2: 4bb3 ldr r3, [pc, #716] ; (8003da0 ) 8003ad4: 691b ldr r3, [r3, #16] 8003ad6: f003 0338 and.w r3, r3, #56 ; 0x38 8003ada: 2b18 cmp r3, #24 8003adc: f200 8155 bhi.w 8003d8a 8003ae0: a201 add r2, pc, #4 ; (adr r2, 8003ae8 ) 8003ae2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003ae6: bf00 nop 8003ae8: 08003b4d .word 0x08003b4d 8003aec: 08003d8b .word 0x08003d8b 8003af0: 08003d8b .word 0x08003d8b 8003af4: 08003d8b .word 0x08003d8b 8003af8: 08003d8b .word 0x08003d8b 8003afc: 08003d8b .word 0x08003d8b 8003b00: 08003d8b .word 0x08003d8b 8003b04: 08003d8b .word 0x08003d8b 8003b08: 08003b73 .word 0x08003b73 8003b0c: 08003d8b .word 0x08003d8b 8003b10: 08003d8b .word 0x08003d8b 8003b14: 08003d8b .word 0x08003d8b 8003b18: 08003d8b .word 0x08003d8b 8003b1c: 08003d8b .word 0x08003d8b 8003b20: 08003d8b .word 0x08003d8b 8003b24: 08003d8b .word 0x08003d8b 8003b28: 08003b79 .word 0x08003b79 8003b2c: 08003d8b .word 0x08003d8b 8003b30: 08003d8b .word 0x08003d8b 8003b34: 08003d8b .word 0x08003d8b 8003b38: 08003d8b .word 0x08003d8b 8003b3c: 08003d8b .word 0x08003d8b 8003b40: 08003d8b .word 0x08003d8b 8003b44: 08003d8b .word 0x08003d8b 8003b48: 08003b7f .word 0x08003b7f { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8003b4c: 4b94 ldr r3, [pc, #592] ; (8003da0 ) 8003b4e: 681b ldr r3, [r3, #0] 8003b50: f003 0320 and.w r3, r3, #32 8003b54: 2b00 cmp r3, #0 8003b56: d009 beq.n 8003b6c { sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8003b58: 4b91 ldr r3, [pc, #580] ; (8003da0 ) 8003b5a: 681b ldr r3, [r3, #0] 8003b5c: 08db lsrs r3, r3, #3 8003b5e: f003 0303 and.w r3, r3, #3 8003b62: 4a90 ldr r2, [pc, #576] ; (8003da4 ) 8003b64: fa22 f303 lsr.w r3, r2, r3 8003b68: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 8003b6a: e111 b.n 8003d90 sysclockfreq = (uint32_t) HSI_VALUE; 8003b6c: 4b8d ldr r3, [pc, #564] ; (8003da4 ) 8003b6e: 61bb str r3, [r7, #24] break; 8003b70: e10e b.n 8003d90 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 8003b72: 4b8d ldr r3, [pc, #564] ; (8003da8 ) 8003b74: 61bb str r3, [r7, #24] break; 8003b76: e10b b.n 8003d90 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8003b78: 4b8c ldr r3, [pc, #560] ; (8003dac ) 8003b7a: 61bb str r3, [r7, #24] break; 8003b7c: e108 b.n 8003d90 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8003b7e: 4b88 ldr r3, [pc, #544] ; (8003da0 ) 8003b80: 6a9b ldr r3, [r3, #40] ; 0x28 8003b82: f003 0303 and.w r3, r3, #3 8003b86: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; 8003b88: 4b85 ldr r3, [pc, #532] ; (8003da0 ) 8003b8a: 6a9b ldr r3, [r3, #40] ; 0x28 8003b8c: 091b lsrs r3, r3, #4 8003b8e: f003 033f and.w r3, r3, #63 ; 0x3f 8003b92: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); 8003b94: 4b82 ldr r3, [pc, #520] ; (8003da0 ) 8003b96: 6adb ldr r3, [r3, #44] ; 0x2c 8003b98: f003 0301 and.w r3, r3, #1 8003b9c: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); 8003b9e: 4b80 ldr r3, [pc, #512] ; (8003da0 ) 8003ba0: 6b5b ldr r3, [r3, #52] ; 0x34 8003ba2: 08db lsrs r3, r3, #3 8003ba4: f3c3 030c ubfx r3, r3, #0, #13 8003ba8: 68fa ldr r2, [r7, #12] 8003baa: fb02 f303 mul.w r3, r2, r3 8003bae: ee07 3a90 vmov s15, r3 8003bb2: eef8 7a67 vcvt.f32.u32 s15, s15 8003bb6: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 8003bba: 693b ldr r3, [r7, #16] 8003bbc: 2b00 cmp r3, #0 8003bbe: f000 80e1 beq.w 8003d84 8003bc2: 697b ldr r3, [r7, #20] 8003bc4: 2b02 cmp r3, #2 8003bc6: f000 8083 beq.w 8003cd0 8003bca: 697b ldr r3, [r7, #20] 8003bcc: 2b02 cmp r3, #2 8003bce: f200 80a1 bhi.w 8003d14 8003bd2: 697b ldr r3, [r7, #20] 8003bd4: 2b00 cmp r3, #0 8003bd6: d003 beq.n 8003be0 8003bd8: 697b ldr r3, [r7, #20] 8003bda: 2b01 cmp r3, #1 8003bdc: d056 beq.n 8003c8c 8003bde: e099 b.n 8003d14 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8003be0: 4b6f ldr r3, [pc, #444] ; (8003da0 ) 8003be2: 681b ldr r3, [r3, #0] 8003be4: f003 0320 and.w r3, r3, #32 8003be8: 2b00 cmp r3, #0 8003bea: d02d beq.n 8003c48 { hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8003bec: 4b6c ldr r3, [pc, #432] ; (8003da0 ) 8003bee: 681b ldr r3, [r3, #0] 8003bf0: 08db lsrs r3, r3, #3 8003bf2: f003 0303 and.w r3, r3, #3 8003bf6: 4a6b ldr r2, [pc, #428] ; (8003da4 ) 8003bf8: fa22 f303 lsr.w r3, r2, r3 8003bfc: 607b str r3, [r7, #4] pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8003bfe: 687b ldr r3, [r7, #4] 8003c00: ee07 3a90 vmov s15, r3 8003c04: eef8 6a67 vcvt.f32.u32 s13, s15 8003c08: 693b ldr r3, [r7, #16] 8003c0a: ee07 3a90 vmov s15, r3 8003c0e: eef8 7a67 vcvt.f32.u32 s15, s15 8003c12: ee86 7aa7 vdiv.f32 s14, s13, s15 8003c16: 4b62 ldr r3, [pc, #392] ; (8003da0 ) 8003c18: 6b1b ldr r3, [r3, #48] ; 0x30 8003c1a: f3c3 0308 ubfx r3, r3, #0, #9 8003c1e: ee07 3a90 vmov s15, r3 8003c22: eef8 6a67 vcvt.f32.u32 s13, s15 8003c26: ed97 6a02 vldr s12, [r7, #8] 8003c2a: eddf 5a61 vldr s11, [pc, #388] ; 8003db0 8003c2e: eec6 7a25 vdiv.f32 s15, s12, s11 8003c32: ee76 7aa7 vadd.f32 s15, s13, s15 8003c36: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003c3a: ee77 7aa6 vadd.f32 s15, s15, s13 8003c3e: ee67 7a27 vmul.f32 s15, s14, s15 8003c42: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); } break; 8003c46: e087 b.n 8003d58 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8003c48: 693b ldr r3, [r7, #16] 8003c4a: ee07 3a90 vmov s15, r3 8003c4e: eef8 7a67 vcvt.f32.u32 s15, s15 8003c52: eddf 6a58 vldr s13, [pc, #352] ; 8003db4 8003c56: ee86 7aa7 vdiv.f32 s14, s13, s15 8003c5a: 4b51 ldr r3, [pc, #324] ; (8003da0 ) 8003c5c: 6b1b ldr r3, [r3, #48] ; 0x30 8003c5e: f3c3 0308 ubfx r3, r3, #0, #9 8003c62: ee07 3a90 vmov s15, r3 8003c66: eef8 6a67 vcvt.f32.u32 s13, s15 8003c6a: ed97 6a02 vldr s12, [r7, #8] 8003c6e: eddf 5a50 vldr s11, [pc, #320] ; 8003db0 8003c72: eec6 7a25 vdiv.f32 s15, s12, s11 8003c76: ee76 7aa7 vadd.f32 s15, s13, s15 8003c7a: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003c7e: ee77 7aa6 vadd.f32 s15, s15, s13 8003c82: ee67 7a27 vmul.f32 s15, s14, s15 8003c86: edc7 7a07 vstr s15, [r7, #28] break; 8003c8a: e065 b.n 8003d58 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8003c8c: 693b ldr r3, [r7, #16] 8003c8e: ee07 3a90 vmov s15, r3 8003c92: eef8 7a67 vcvt.f32.u32 s15, s15 8003c96: eddf 6a48 vldr s13, [pc, #288] ; 8003db8 8003c9a: ee86 7aa7 vdiv.f32 s14, s13, s15 8003c9e: 4b40 ldr r3, [pc, #256] ; (8003da0 ) 8003ca0: 6b1b ldr r3, [r3, #48] ; 0x30 8003ca2: f3c3 0308 ubfx r3, r3, #0, #9 8003ca6: ee07 3a90 vmov s15, r3 8003caa: eef8 6a67 vcvt.f32.u32 s13, s15 8003cae: ed97 6a02 vldr s12, [r7, #8] 8003cb2: eddf 5a3f vldr s11, [pc, #252] ; 8003db0 8003cb6: eec6 7a25 vdiv.f32 s15, s12, s11 8003cba: ee76 7aa7 vadd.f32 s15, s13, s15 8003cbe: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003cc2: ee77 7aa6 vadd.f32 s15, s15, s13 8003cc6: ee67 7a27 vmul.f32 s15, s14, s15 8003cca: edc7 7a07 vstr s15, [r7, #28] break; 8003cce: e043 b.n 8003d58 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8003cd0: 693b ldr r3, [r7, #16] 8003cd2: ee07 3a90 vmov s15, r3 8003cd6: eef8 7a67 vcvt.f32.u32 s15, s15 8003cda: eddf 6a38 vldr s13, [pc, #224] ; 8003dbc 8003cde: ee86 7aa7 vdiv.f32 s14, s13, s15 8003ce2: 4b2f ldr r3, [pc, #188] ; (8003da0 ) 8003ce4: 6b1b ldr r3, [r3, #48] ; 0x30 8003ce6: f3c3 0308 ubfx r3, r3, #0, #9 8003cea: ee07 3a90 vmov s15, r3 8003cee: eef8 6a67 vcvt.f32.u32 s13, s15 8003cf2: ed97 6a02 vldr s12, [r7, #8] 8003cf6: eddf 5a2e vldr s11, [pc, #184] ; 8003db0 8003cfa: eec6 7a25 vdiv.f32 s15, s12, s11 8003cfe: ee76 7aa7 vadd.f32 s15, s13, s15 8003d02: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003d06: ee77 7aa6 vadd.f32 s15, s15, s13 8003d0a: ee67 7a27 vmul.f32 s15, s14, s15 8003d0e: edc7 7a07 vstr s15, [r7, #28] break; 8003d12: e021 b.n 8003d58 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8003d14: 693b ldr r3, [r7, #16] 8003d16: ee07 3a90 vmov s15, r3 8003d1a: eef8 7a67 vcvt.f32.u32 s15, s15 8003d1e: eddf 6a26 vldr s13, [pc, #152] ; 8003db8 8003d22: ee86 7aa7 vdiv.f32 s14, s13, s15 8003d26: 4b1e ldr r3, [pc, #120] ; (8003da0 ) 8003d28: 6b1b ldr r3, [r3, #48] ; 0x30 8003d2a: f3c3 0308 ubfx r3, r3, #0, #9 8003d2e: ee07 3a90 vmov s15, r3 8003d32: eef8 6a67 vcvt.f32.u32 s13, s15 8003d36: ed97 6a02 vldr s12, [r7, #8] 8003d3a: eddf 5a1d vldr s11, [pc, #116] ; 8003db0 8003d3e: eec6 7a25 vdiv.f32 s15, s12, s11 8003d42: ee76 7aa7 vadd.f32 s15, s13, s15 8003d46: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003d4a: ee77 7aa6 vadd.f32 s15, s15, s13 8003d4e: ee67 7a27 vmul.f32 s15, s14, s15 8003d52: edc7 7a07 vstr s15, [r7, #28] break; 8003d56: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; 8003d58: 4b11 ldr r3, [pc, #68] ; (8003da0 ) 8003d5a: 6b1b ldr r3, [r3, #48] ; 0x30 8003d5c: 0a5b lsrs r3, r3, #9 8003d5e: f003 037f and.w r3, r3, #127 ; 0x7f 8003d62: 3301 adds r3, #1 8003d64: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco/(float_t)pllp); 8003d66: 683b ldr r3, [r7, #0] 8003d68: ee07 3a90 vmov s15, r3 8003d6c: eeb8 7a67 vcvt.f32.u32 s14, s15 8003d70: edd7 6a07 vldr s13, [r7, #28] 8003d74: eec6 7a87 vdiv.f32 s15, s13, s14 8003d78: eefc 7ae7 vcvt.u32.f32 s15, s15 8003d7c: ee17 3a90 vmov r3, s15 8003d80: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 8003d82: e005 b.n 8003d90 sysclockfreq = 0U; 8003d84: 2300 movs r3, #0 8003d86: 61bb str r3, [r7, #24] break; 8003d88: e002 b.n 8003d90 default: sysclockfreq = CSI_VALUE; 8003d8a: 4b07 ldr r3, [pc, #28] ; (8003da8 ) 8003d8c: 61bb str r3, [r7, #24] break; 8003d8e: bf00 nop } return sysclockfreq; 8003d90: 69bb ldr r3, [r7, #24] } 8003d92: 4618 mov r0, r3 8003d94: 3724 adds r7, #36 ; 0x24 8003d96: 46bd mov sp, r7 8003d98: f85d 7b04 ldr.w r7, [sp], #4 8003d9c: 4770 bx lr 8003d9e: bf00 nop 8003da0: 58024400 .word 0x58024400 8003da4: 03d09000 .word 0x03d09000 8003da8: 003d0900 .word 0x003d0900 8003dac: 007a1200 .word 0x007a1200 8003db0: 46000000 .word 0x46000000 8003db4: 4c742400 .word 0x4c742400 8003db8: 4a742400 .word 0x4a742400 8003dbc: 4af42400 .word 0x4af42400 08003dc0 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8003dc0: b580 push {r7, lr} 8003dc2: b082 sub sp, #8 8003dc4: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8003dc6: f7ff fe81 bl 8003acc 8003dca: 4602 mov r2, r0 8003dcc: 4b10 ldr r3, [pc, #64] ; (8003e10 ) 8003dce: 699b ldr r3, [r3, #24] 8003dd0: 0a1b lsrs r3, r3, #8 8003dd2: f003 030f and.w r3, r3, #15 8003dd6: 490f ldr r1, [pc, #60] ; (8003e14 ) 8003dd8: 5ccb ldrb r3, [r1, r3] 8003dda: f003 031f and.w r3, r3, #31 8003dde: fa22 f303 lsr.w r3, r2, r3 8003de2: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8003de4: 4b0a ldr r3, [pc, #40] ; (8003e10 ) 8003de6: 699b ldr r3, [r3, #24] 8003de8: f003 030f and.w r3, r3, #15 8003dec: 4a09 ldr r2, [pc, #36] ; (8003e14 ) 8003dee: 5cd3 ldrb r3, [r2, r3] 8003df0: f003 031f and.w r3, r3, #31 8003df4: 687a ldr r2, [r7, #4] 8003df6: fa22 f303 lsr.w r3, r2, r3 8003dfa: 4a07 ldr r2, [pc, #28] ; (8003e18 ) 8003dfc: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8003dfe: 4a07 ldr r2, [pc, #28] ; (8003e1c ) 8003e00: 687b ldr r3, [r7, #4] 8003e02: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 8003e04: 4b04 ldr r3, [pc, #16] ; (8003e18 ) 8003e06: 681b ldr r3, [r3, #0] } 8003e08: 4618 mov r0, r3 8003e0a: 3708 adds r7, #8 8003e0c: 46bd mov sp, r7 8003e0e: bd80 pop {r7, pc} 8003e10: 58024400 .word 0x58024400 8003e14: 0800a958 .word 0x0800a958 8003e18: 24000004 .word 0x24000004 8003e1c: 24000000 .word 0x24000000 08003e20 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8003e20: b580 push {r7, lr} 8003e22: b086 sub sp, #24 8003e24: af00 add r7, sp, #0 8003e26: 6078 str r0, [r7, #4] uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8003e28: 2300 movs r3, #0 8003e2a: 75fb strb r3, [r7, #23] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8003e2c: 2300 movs r3, #0 8003e2e: 75bb strb r3, [r7, #22] /*---------------------------- SPDIFRX configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8003e30: 687b ldr r3, [r7, #4] 8003e32: 681b ldr r3, [r3, #0] 8003e34: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8003e38: 2b00 cmp r3, #0 8003e3a: d03f beq.n 8003ebc { switch(PeriphClkInit->SpdifrxClockSelection) 8003e3c: 687b ldr r3, [r7, #4] 8003e3e: 6e1b ldr r3, [r3, #96] ; 0x60 8003e40: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8003e44: d02a beq.n 8003e9c 8003e46: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8003e4a: d824 bhi.n 8003e96 8003e4c: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8003e50: d018 beq.n 8003e84 8003e52: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8003e56: d81e bhi.n 8003e96 8003e58: 2b00 cmp r3, #0 8003e5a: d003 beq.n 8003e64 8003e5c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8003e60: d007 beq.n 8003e72 8003e62: e018 b.n 8003e96 { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003e64: 4bab ldr r3, [pc, #684] ; (8004114 ) 8003e66: 6adb ldr r3, [r3, #44] ; 0x2c 8003e68: 4aaa ldr r2, [pc, #680] ; (8004114 ) 8003e6a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003e6e: 62d3 str r3, [r2, #44] ; 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 8003e70: e015 b.n 8003e9e case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8003e72: 687b ldr r3, [r7, #4] 8003e74: 3304 adds r3, #4 8003e76: 2102 movs r1, #2 8003e78: 4618 mov r0, r3 8003e7a: f000 fecb bl 8004c14 8003e7e: 4603 mov r3, r0 8003e80: 75fb strb r3, [r7, #23] /* SPDIFRX clock source configuration done later after clock selection check */ break; 8003e82: e00c b.n 8003e9e case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8003e84: 687b ldr r3, [r7, #4] 8003e86: 3324 adds r3, #36 ; 0x24 8003e88: 2102 movs r1, #2 8003e8a: 4618 mov r0, r3 8003e8c: f000 ff74 bl 8004d78 8003e90: 4603 mov r3, r0 8003e92: 75fb strb r3, [r7, #23] /* SPDIFRX clock source configuration done later after clock selection check */ break; 8003e94: e003 b.n 8003e9e /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003e96: 2301 movs r3, #1 8003e98: 75fb strb r3, [r7, #23] break; 8003e9a: e000 b.n 8003e9e break; 8003e9c: bf00 nop } if(ret == HAL_OK) 8003e9e: 7dfb ldrb r3, [r7, #23] 8003ea0: 2b00 cmp r3, #0 8003ea2: d109 bne.n 8003eb8 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 8003ea4: 4b9b ldr r3, [pc, #620] ; (8004114 ) 8003ea6: 6d1b ldr r3, [r3, #80] ; 0x50 8003ea8: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8003eac: 687b ldr r3, [r7, #4] 8003eae: 6e1b ldr r3, [r3, #96] ; 0x60 8003eb0: 4998 ldr r1, [pc, #608] ; (8004114 ) 8003eb2: 4313 orrs r3, r2 8003eb4: 650b str r3, [r1, #80] ; 0x50 8003eb6: e001 b.n 8003ebc } else { /* set overall return value */ status = ret; 8003eb8: 7dfb ldrb r3, [r7, #23] 8003eba: 75bb strb r3, [r7, #22] } } /*---------------------------- SAI1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8003ebc: 687b ldr r3, [r7, #4] 8003ebe: 681b ldr r3, [r3, #0] 8003ec0: f403 7380 and.w r3, r3, #256 ; 0x100 8003ec4: 2b00 cmp r3, #0 8003ec6: d03d beq.n 8003f44 { switch(PeriphClkInit->Sai1ClockSelection) 8003ec8: 687b ldr r3, [r7, #4] 8003eca: 6d5b ldr r3, [r3, #84] ; 0x54 8003ecc: 2b04 cmp r3, #4 8003ece: d826 bhi.n 8003f1e 8003ed0: a201 add r2, pc, #4 ; (adr r2, 8003ed8 ) 8003ed2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003ed6: bf00 nop 8003ed8: 08003eed .word 0x08003eed 8003edc: 08003efb .word 0x08003efb 8003ee0: 08003f0d .word 0x08003f0d 8003ee4: 08003f25 .word 0x08003f25 8003ee8: 08003f25 .word 0x08003f25 { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003eec: 4b89 ldr r3, [pc, #548] ; (8004114 ) 8003eee: 6adb ldr r3, [r3, #44] ; 0x2c 8003ef0: 4a88 ldr r2, [pc, #544] ; (8004114 ) 8003ef2: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003ef6: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8003ef8: e015 b.n 8003f26 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8003efa: 687b ldr r3, [r7, #4] 8003efc: 3304 adds r3, #4 8003efe: 2100 movs r1, #0 8003f00: 4618 mov r0, r3 8003f02: f000 fe87 bl 8004c14 8003f06: 4603 mov r3, r0 8003f08: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 8003f0a: e00c b.n 8003f26 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 8003f0c: 687b ldr r3, [r7, #4] 8003f0e: 3324 adds r3, #36 ; 0x24 8003f10: 2100 movs r1, #0 8003f12: 4618 mov r0, r3 8003f14: f000 ff30 bl 8004d78 8003f18: 4603 mov r3, r0 8003f1a: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 8003f1c: e003 b.n 8003f26 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003f1e: 2301 movs r3, #1 8003f20: 75fb strb r3, [r7, #23] break; 8003f22: e000 b.n 8003f26 break; 8003f24: bf00 nop } if(ret == HAL_OK) 8003f26: 7dfb ldrb r3, [r7, #23] 8003f28: 2b00 cmp r3, #0 8003f2a: d109 bne.n 8003f40 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8003f2c: 4b79 ldr r3, [pc, #484] ; (8004114 ) 8003f2e: 6d1b ldr r3, [r3, #80] ; 0x50 8003f30: f023 0207 bic.w r2, r3, #7 8003f34: 687b ldr r3, [r7, #4] 8003f36: 6d5b ldr r3, [r3, #84] ; 0x54 8003f38: 4976 ldr r1, [pc, #472] ; (8004114 ) 8003f3a: 4313 orrs r3, r2 8003f3c: 650b str r3, [r1, #80] ; 0x50 8003f3e: e001 b.n 8003f44 } else { /* set overall return value */ status = ret; 8003f40: 7dfb ldrb r3, [r7, #23] 8003f42: 75bb strb r3, [r7, #22] } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 8003f44: 687b ldr r3, [r7, #4] 8003f46: 681b ldr r3, [r3, #0] 8003f48: f403 6380 and.w r3, r3, #1024 ; 0x400 8003f4c: 2b00 cmp r3, #0 8003f4e: d051 beq.n 8003ff4 { switch(PeriphClkInit->Sai4AClockSelection) 8003f50: 687b ldr r3, [r7, #4] 8003f52: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 8003f56: f5b3 0f20 cmp.w r3, #10485760 ; 0xa00000 8003f5a: d036 beq.n 8003fca 8003f5c: f5b3 0f20 cmp.w r3, #10485760 ; 0xa00000 8003f60: d830 bhi.n 8003fc4 8003f62: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 8003f66: d032 beq.n 8003fce 8003f68: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 8003f6c: d82a bhi.n 8003fc4 8003f6e: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000 8003f72: d02e beq.n 8003fd2 8003f74: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000 8003f78: d824 bhi.n 8003fc4 8003f7a: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8003f7e: d018 beq.n 8003fb2 8003f80: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8003f84: d81e bhi.n 8003fc4 8003f86: 2b00 cmp r3, #0 8003f88: d003 beq.n 8003f92 8003f8a: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8003f8e: d007 beq.n 8003fa0 8003f90: e018 b.n 8003fc4 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003f92: 4b60 ldr r3, [pc, #384] ; (8004114 ) 8003f94: 6adb ldr r3, [r3, #44] ; 0x2c 8003f96: 4a5f ldr r2, [pc, #380] ; (8004114 ) 8003f98: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003f9c: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8003f9e: e019 b.n 8003fd4 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8003fa0: 687b ldr r3, [r7, #4] 8003fa2: 3304 adds r3, #4 8003fa4: 2100 movs r1, #0 8003fa6: 4618 mov r0, r3 8003fa8: f000 fe34 bl 8004c14 8003fac: 4603 mov r3, r0 8003fae: 75fb strb r3, [r7, #23] /* SAI2 clock source configuration done later after clock selection check */ break; 8003fb0: e010 b.n 8003fd4 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 8003fb2: 687b ldr r3, [r7, #4] 8003fb4: 3324 adds r3, #36 ; 0x24 8003fb6: 2100 movs r1, #0 8003fb8: 4618 mov r0, r3 8003fba: f000 fedd bl 8004d78 8003fbe: 4603 mov r3, r0 8003fc0: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 8003fc2: e007 b.n 8003fd4 /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 8003fc4: 2301 movs r3, #1 8003fc6: 75fb strb r3, [r7, #23] break; 8003fc8: e004 b.n 8003fd4 break; 8003fca: bf00 nop 8003fcc: e002 b.n 8003fd4 break; 8003fce: bf00 nop 8003fd0: e000 b.n 8003fd4 break; 8003fd2: bf00 nop } if(ret == HAL_OK) 8003fd4: 7dfb ldrb r3, [r7, #23] 8003fd6: 2b00 cmp r3, #0 8003fd8: d10a bne.n 8003ff0 { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 8003fda: 4b4e ldr r3, [pc, #312] ; (8004114 ) 8003fdc: 6d9b ldr r3, [r3, #88] ; 0x58 8003fde: f423 0260 bic.w r2, r3, #14680064 ; 0xe00000 8003fe2: 687b ldr r3, [r7, #4] 8003fe4: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 8003fe8: 494a ldr r1, [pc, #296] ; (8004114 ) 8003fea: 4313 orrs r3, r2 8003fec: 658b str r3, [r1, #88] ; 0x58 8003fee: e001 b.n 8003ff4 } else { /* set overall return value */ status = ret; 8003ff0: 7dfb ldrb r3, [r7, #23] 8003ff2: 75bb strb r3, [r7, #22] } } /*---------------------------- SAI4B configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 8003ff4: 687b ldr r3, [r7, #4] 8003ff6: 681b ldr r3, [r3, #0] 8003ff8: f403 6300 and.w r3, r3, #2048 ; 0x800 8003ffc: 2b00 cmp r3, #0 8003ffe: d051 beq.n 80040a4 { switch(PeriphClkInit->Sai4BClockSelection) 8004000: 687b ldr r3, [r7, #4] 8004002: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 8004006: f1b3 6fa0 cmp.w r3, #83886080 ; 0x5000000 800400a: d036 beq.n 800407a 800400c: f1b3 6fa0 cmp.w r3, #83886080 ; 0x5000000 8004010: d830 bhi.n 8004074 8004012: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 8004016: d032 beq.n 800407e 8004018: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 800401c: d82a bhi.n 8004074 800401e: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000 8004022: d02e beq.n 8004082 8004024: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000 8004028: d824 bhi.n 8004074 800402a: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800402e: d018 beq.n 8004062 8004030: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 8004034: d81e bhi.n 8004074 8004036: 2b00 cmp r3, #0 8004038: d003 beq.n 8004042 800403a: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 800403e: d007 beq.n 8004050 8004040: e018 b.n 8004074 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004042: 4b34 ldr r3, [pc, #208] ; (8004114 ) 8004044: 6adb ldr r3, [r3, #44] ; 0x2c 8004046: 4a33 ldr r2, [pc, #204] ; (8004114 ) 8004048: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800404c: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800404e: e019 b.n 8004084 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8004050: 687b ldr r3, [r7, #4] 8004052: 3304 adds r3, #4 8004054: 2100 movs r1, #0 8004056: 4618 mov r0, r3 8004058: f000 fddc bl 8004c14 800405c: 4603 mov r3, r0 800405e: 75fb strb r3, [r7, #23] /* SAI2 clock source configuration done later after clock selection check */ break; 8004060: e010 b.n 8004084 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 8004062: 687b ldr r3, [r7, #4] 8004064: 3324 adds r3, #36 ; 0x24 8004066: 2100 movs r1, #0 8004068: 4618 mov r0, r3 800406a: f000 fe85 bl 8004d78 800406e: 4603 mov r3, r0 8004070: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 8004072: e007 b.n 8004084 /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 8004074: 2301 movs r3, #1 8004076: 75fb strb r3, [r7, #23] break; 8004078: e004 b.n 8004084 break; 800407a: bf00 nop 800407c: e002 b.n 8004084 break; 800407e: bf00 nop 8004080: e000 b.n 8004084 break; 8004082: bf00 nop } if(ret == HAL_OK) 8004084: 7dfb ldrb r3, [r7, #23] 8004086: 2b00 cmp r3, #0 8004088: d10a bne.n 80040a0 { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 800408a: 4b22 ldr r3, [pc, #136] ; (8004114 ) 800408c: 6d9b ldr r3, [r3, #88] ; 0x58 800408e: f023 62e0 bic.w r2, r3, #117440512 ; 0x7000000 8004092: 687b ldr r3, [r7, #4] 8004094: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 8004098: 491e ldr r1, [pc, #120] ; (8004114 ) 800409a: 4313 orrs r3, r2 800409c: 658b str r3, [r1, #88] ; 0x58 800409e: e001 b.n 80040a4 } else { /* set overall return value */ status = ret; 80040a0: 7dfb ldrb r3, [r7, #23] 80040a2: 75bb strb r3, [r7, #22] } #endif /*QUADSPI*/ #if defined(OCTOSPI1) || defined(OCTOSPI2) /*---------------------------- OCTOSPI configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) 80040a4: 687b ldr r3, [r7, #4] 80040a6: 681b ldr r3, [r3, #0] 80040a8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80040ac: 2b00 cmp r3, #0 80040ae: d035 beq.n 800411c { switch(PeriphClkInit->OspiClockSelection) 80040b0: 687b ldr r3, [r7, #4] 80040b2: 6c9b ldr r3, [r3, #72] ; 0x48 80040b4: 2b30 cmp r3, #48 ; 0x30 80040b6: d01c beq.n 80040f2 80040b8: 2b30 cmp r3, #48 ; 0x30 80040ba: d817 bhi.n 80040ec 80040bc: 2b20 cmp r3, #32 80040be: d00c beq.n 80040da 80040c0: 2b20 cmp r3, #32 80040c2: d813 bhi.n 80040ec 80040c4: 2b00 cmp r3, #0 80040c6: d016 beq.n 80040f6 80040c8: 2b10 cmp r3, #16 80040ca: d10f bne.n 80040ec { case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ /* Enable OSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80040cc: 4b11 ldr r3, [pc, #68] ; (8004114 ) 80040ce: 6adb ldr r3, [r3, #44] ; 0x2c 80040d0: 4a10 ldr r2, [pc, #64] ; (8004114 ) 80040d2: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80040d6: 62d3 str r3, [r2, #44] ; 0x2c /* OSPI clock source configuration done later after clock selection check */ break; 80040d8: e00e b.n 80040f8 case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 80040da: 687b ldr r3, [r7, #4] 80040dc: 3304 adds r3, #4 80040de: 2102 movs r1, #2 80040e0: 4618 mov r0, r3 80040e2: f000 fd97 bl 8004c14 80040e6: 4603 mov r3, r0 80040e8: 75fb strb r3, [r7, #23] /* OSPI clock source configuration done later after clock selection check */ break; 80040ea: e005 b.n 80040f8 case RCC_OSPICLKSOURCE_HCLK: /* HCLK clock selected as OSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 80040ec: 2301 movs r3, #1 80040ee: 75fb strb r3, [r7, #23] break; 80040f0: e002 b.n 80040f8 break; 80040f2: bf00 nop 80040f4: e000 b.n 80040f8 break; 80040f6: bf00 nop } if(ret == HAL_OK) 80040f8: 7dfb ldrb r3, [r7, #23] 80040fa: 2b00 cmp r3, #0 80040fc: d10c bne.n 8004118 { /* Set the source of OSPI clock*/ __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); 80040fe: 4b05 ldr r3, [pc, #20] ; (8004114 ) 8004100: 6cdb ldr r3, [r3, #76] ; 0x4c 8004102: f023 0230 bic.w r2, r3, #48 ; 0x30 8004106: 687b ldr r3, [r7, #4] 8004108: 6c9b ldr r3, [r3, #72] ; 0x48 800410a: 4902 ldr r1, [pc, #8] ; (8004114 ) 800410c: 4313 orrs r3, r2 800410e: 64cb str r3, [r1, #76] ; 0x4c 8004110: e004 b.n 800411c 8004112: bf00 nop 8004114: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8004118: 7dfb ldrb r3, [r7, #23] 800411a: 75bb strb r3, [r7, #22] } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800411c: 687b ldr r3, [r7, #4] 800411e: 681b ldr r3, [r3, #0] 8004120: f403 5380 and.w r3, r3, #4096 ; 0x1000 8004124: 2b00 cmp r3, #0 8004126: d047 beq.n 80041b8 { switch(PeriphClkInit->Spi123ClockSelection) 8004128: 687b ldr r3, [r7, #4] 800412a: 6d9b ldr r3, [r3, #88] ; 0x58 800412c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8004130: d030 beq.n 8004194 8004132: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8004136: d82a bhi.n 800418e 8004138: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 800413c: d02c beq.n 8004198 800413e: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 8004142: d824 bhi.n 800418e 8004144: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8004148: d018 beq.n 800417c 800414a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800414e: d81e bhi.n 800418e 8004150: 2b00 cmp r3, #0 8004152: d003 beq.n 800415c 8004154: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004158: d007 beq.n 800416a 800415a: e018 b.n 800418e { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800415c: 4bac ldr r3, [pc, #688] ; (8004410 ) 800415e: 6adb ldr r3, [r3, #44] ; 0x2c 8004160: 4aab ldr r2, [pc, #684] ; (8004410 ) 8004162: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004166: 62d3 str r3, [r2, #44] ; 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8004168: e017 b.n 800419a case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 800416a: 687b ldr r3, [r7, #4] 800416c: 3304 adds r3, #4 800416e: 2100 movs r1, #0 8004170: 4618 mov r0, r3 8004172: f000 fd4f bl 8004c14 8004176: 4603 mov r3, r0 8004178: 75fb strb r3, [r7, #23] /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800417a: e00e b.n 800419a case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 800417c: 687b ldr r3, [r7, #4] 800417e: 3324 adds r3, #36 ; 0x24 8004180: 2100 movs r1, #0 8004182: 4618 mov r0, r3 8004184: f000 fdf8 bl 8004d78 8004188: 4603 mov r3, r0 800418a: 75fb strb r3, [r7, #23] /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800418c: e005 b.n 800419a /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800418e: 2301 movs r3, #1 8004190: 75fb strb r3, [r7, #23] break; 8004192: e002 b.n 800419a break; 8004194: bf00 nop 8004196: e000 b.n 800419a break; 8004198: bf00 nop } if(ret == HAL_OK) 800419a: 7dfb ldrb r3, [r7, #23] 800419c: 2b00 cmp r3, #0 800419e: d109 bne.n 80041b4 { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 80041a0: 4b9b ldr r3, [pc, #620] ; (8004410 ) 80041a2: 6d1b ldr r3, [r3, #80] ; 0x50 80041a4: f423 42e0 bic.w r2, r3, #28672 ; 0x7000 80041a8: 687b ldr r3, [r7, #4] 80041aa: 6d9b ldr r3, [r3, #88] ; 0x58 80041ac: 4998 ldr r1, [pc, #608] ; (8004410 ) 80041ae: 4313 orrs r3, r2 80041b0: 650b str r3, [r1, #80] ; 0x50 80041b2: e001 b.n 80041b8 } else { /* set overall return value */ status = ret; 80041b4: 7dfb ldrb r3, [r7, #23] 80041b6: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 80041b8: 687b ldr r3, [r7, #4] 80041ba: 681b ldr r3, [r3, #0] 80041bc: f403 5300 and.w r3, r3, #8192 ; 0x2000 80041c0: 2b00 cmp r3, #0 80041c2: d049 beq.n 8004258 { switch(PeriphClkInit->Spi45ClockSelection) 80041c4: 687b ldr r3, [r7, #4] 80041c6: 6ddb ldr r3, [r3, #92] ; 0x5c 80041c8: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80041cc: d02e beq.n 800422c 80041ce: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80041d2: d828 bhi.n 8004226 80041d4: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 80041d8: d02a beq.n 8004230 80041da: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 80041de: d822 bhi.n 8004226 80041e0: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 80041e4: d026 beq.n 8004234 80041e6: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 80041ea: d81c bhi.n 8004226 80041ec: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80041f0: d010 beq.n 8004214 80041f2: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80041f6: d816 bhi.n 8004226 80041f8: 2b00 cmp r3, #0 80041fa: d01d beq.n 8004238 80041fc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8004200: d111 bne.n 8004226 /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8004202: 687b ldr r3, [r7, #4] 8004204: 3304 adds r3, #4 8004206: 2101 movs r1, #1 8004208: 4618 mov r0, r3 800420a: f000 fd03 bl 8004c14 800420e: 4603 mov r3, r0 8004210: 75fb strb r3, [r7, #23] /* SPI4/5 clock source configuration done later after clock selection check */ break; 8004212: e012 b.n 800423a case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8004214: 687b ldr r3, [r7, #4] 8004216: 3324 adds r3, #36 ; 0x24 8004218: 2101 movs r1, #1 800421a: 4618 mov r0, r3 800421c: f000 fdac bl 8004d78 8004220: 4603 mov r3, r0 8004222: 75fb strb r3, [r7, #23] /* SPI4/5 clock source configuration done later after clock selection check */ break; 8004224: e009 b.n 800423a /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004226: 2301 movs r3, #1 8004228: 75fb strb r3, [r7, #23] break; 800422a: e006 b.n 800423a break; 800422c: bf00 nop 800422e: e004 b.n 800423a break; 8004230: bf00 nop 8004232: e002 b.n 800423a break; 8004234: bf00 nop 8004236: e000 b.n 800423a break; 8004238: bf00 nop } if(ret == HAL_OK) 800423a: 7dfb ldrb r3, [r7, #23] 800423c: 2b00 cmp r3, #0 800423e: d109 bne.n 8004254 { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 8004240: 4b73 ldr r3, [pc, #460] ; (8004410 ) 8004242: 6d1b ldr r3, [r3, #80] ; 0x50 8004244: f423 22e0 bic.w r2, r3, #458752 ; 0x70000 8004248: 687b ldr r3, [r7, #4] 800424a: 6ddb ldr r3, [r3, #92] ; 0x5c 800424c: 4970 ldr r1, [pc, #448] ; (8004410 ) 800424e: 4313 orrs r3, r2 8004250: 650b str r3, [r1, #80] ; 0x50 8004252: e001 b.n 8004258 } else { /* set overall return value */ status = ret; 8004254: 7dfb ldrb r3, [r7, #23] 8004256: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI6 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 8004258: 687b ldr r3, [r7, #4] 800425a: 681b ldr r3, [r3, #0] 800425c: f403 4380 and.w r3, r3, #16384 ; 0x4000 8004260: 2b00 cmp r3, #0 8004262: d04b beq.n 80042fc { switch(PeriphClkInit->Spi6ClockSelection) 8004264: 687b ldr r3, [r7, #4] 8004266: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 800426a: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 800426e: d02e beq.n 80042ce 8004270: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8004274: d828 bhi.n 80042c8 8004276: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800427a: d02a beq.n 80042d2 800427c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004280: d822 bhi.n 80042c8 8004282: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8004286: d026 beq.n 80042d6 8004288: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 800428c: d81c bhi.n 80042c8 800428e: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004292: d010 beq.n 80042b6 8004294: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004298: d816 bhi.n 80042c8 800429a: 2b00 cmp r3, #0 800429c: d01d beq.n 80042da 800429e: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 80042a2: d111 bne.n 80042c8 /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 80042a4: 687b ldr r3, [r7, #4] 80042a6: 3304 adds r3, #4 80042a8: 2101 movs r1, #1 80042aa: 4618 mov r0, r3 80042ac: f000 fcb2 bl 8004c14 80042b0: 4603 mov r3, r0 80042b2: 75fb strb r3, [r7, #23] /* SPI6 clock source configuration done later after clock selection check */ break; 80042b4: e012 b.n 80042dc case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 80042b6: 687b ldr r3, [r7, #4] 80042b8: 3324 adds r3, #36 ; 0x24 80042ba: 2101 movs r1, #1 80042bc: 4618 mov r0, r3 80042be: f000 fd5b bl 8004d78 80042c2: 4603 mov r3, r0 80042c4: 75fb strb r3, [r7, #23] /* SPI6 clock source configuration done later after clock selection check */ break; 80042c6: e009 b.n 80042dc /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 80042c8: 2301 movs r3, #1 80042ca: 75fb strb r3, [r7, #23] break; 80042cc: e006 b.n 80042dc break; 80042ce: bf00 nop 80042d0: e004 b.n 80042dc break; 80042d2: bf00 nop 80042d4: e002 b.n 80042dc break; 80042d6: bf00 nop 80042d8: e000 b.n 80042dc break; 80042da: bf00 nop } if(ret == HAL_OK) 80042dc: 7dfb ldrb r3, [r7, #23] 80042de: 2b00 cmp r3, #0 80042e0: d10a bne.n 80042f8 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 80042e2: 4b4b ldr r3, [pc, #300] ; (8004410 ) 80042e4: 6d9b ldr r3, [r3, #88] ; 0x58 80042e6: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000 80042ea: 687b ldr r3, [r7, #4] 80042ec: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 80042f0: 4947 ldr r1, [pc, #284] ; (8004410 ) 80042f2: 4313 orrs r3, r2 80042f4: 658b str r3, [r1, #88] ; 0x58 80042f6: e001 b.n 80042fc } else { /* set overall return value */ status = ret; 80042f8: 7dfb ldrb r3, [r7, #23] 80042fa: 75bb strb r3, [r7, #22] } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 80042fc: 687b ldr r3, [r7, #4] 80042fe: 681b ldr r3, [r3, #0] 8004300: f403 4300 and.w r3, r3, #32768 ; 0x8000 8004304: 2b00 cmp r3, #0 8004306: d02f beq.n 8004368 { switch(PeriphClkInit->FdcanClockSelection) 8004308: 687b ldr r3, [r7, #4] 800430a: 6e9b ldr r3, [r3, #104] ; 0x68 800430c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004310: d00e beq.n 8004330 8004312: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004316: d814 bhi.n 8004342 8004318: 2b00 cmp r3, #0 800431a: d015 beq.n 8004348 800431c: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8004320: d10f bne.n 8004342 { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004322: 4b3b ldr r3, [pc, #236] ; (8004410 ) 8004324: 6adb ldr r3, [r3, #44] ; 0x2c 8004326: 4a3a ldr r2, [pc, #232] ; (8004410 ) 8004328: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800432c: 62d3 str r3, [r2, #44] ; 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 800432e: e00c b.n 800434a case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8004330: 687b ldr r3, [r7, #4] 8004332: 3304 adds r3, #4 8004334: 2101 movs r1, #1 8004336: 4618 mov r0, r3 8004338: f000 fc6c bl 8004c14 800433c: 4603 mov r3, r0 800433e: 75fb strb r3, [r7, #23] /* FDCAN clock source configuration done later after clock selection check */ break; 8004340: e003 b.n 800434a /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004342: 2301 movs r3, #1 8004344: 75fb strb r3, [r7, #23] break; 8004346: e000 b.n 800434a break; 8004348: bf00 nop } if(ret == HAL_OK) 800434a: 7dfb ldrb r3, [r7, #23] 800434c: 2b00 cmp r3, #0 800434e: d109 bne.n 8004364 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 8004350: 4b2f ldr r3, [pc, #188] ; (8004410 ) 8004352: 6d1b ldr r3, [r3, #80] ; 0x50 8004354: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 8004358: 687b ldr r3, [r7, #4] 800435a: 6e9b ldr r3, [r3, #104] ; 0x68 800435c: 492c ldr r1, [pc, #176] ; (8004410 ) 800435e: 4313 orrs r3, r2 8004360: 650b str r3, [r1, #80] ; 0x50 8004362: e001 b.n 8004368 } else { /* set overall return value */ status = ret; 8004364: 7dfb ldrb r3, [r7, #23] 8004366: 75bb strb r3, [r7, #22] } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 8004368: 687b ldr r3, [r7, #4] 800436a: 681b ldr r3, [r3, #0] 800436c: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8004370: 2b00 cmp r3, #0 8004372: d032 beq.n 80043da { switch(PeriphClkInit->FmcClockSelection) 8004374: 687b ldr r3, [r7, #4] 8004376: 6c5b ldr r3, [r3, #68] ; 0x44 8004378: 2b03 cmp r3, #3 800437a: d81b bhi.n 80043b4 800437c: a201 add r2, pc, #4 ; (adr r2, 8004384 ) 800437e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004382: bf00 nop 8004384: 080043bb .word 0x080043bb 8004388: 08004395 .word 0x08004395 800438c: 080043a3 .word 0x080043a3 8004390: 080043bb .word 0x080043bb { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004394: 4b1e ldr r3, [pc, #120] ; (8004410 ) 8004396: 6adb ldr r3, [r3, #44] ; 0x2c 8004398: 4a1d ldr r2, [pc, #116] ; (8004410 ) 800439a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800439e: 62d3 str r3, [r2, #44] ; 0x2c /* FMC clock source configuration done later after clock selection check */ break; 80043a0: e00c b.n 80043bc case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 80043a2: 687b ldr r3, [r7, #4] 80043a4: 3304 adds r3, #4 80043a6: 2102 movs r1, #2 80043a8: 4618 mov r0, r3 80043aa: f000 fc33 bl 8004c14 80043ae: 4603 mov r3, r0 80043b0: 75fb strb r3, [r7, #23] /* FMC clock source configuration done later after clock selection check */ break; 80043b2: e003 b.n 80043bc case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 80043b4: 2301 movs r3, #1 80043b6: 75fb strb r3, [r7, #23] break; 80043b8: e000 b.n 80043bc break; 80043ba: bf00 nop } if(ret == HAL_OK) 80043bc: 7dfb ldrb r3, [r7, #23] 80043be: 2b00 cmp r3, #0 80043c0: d109 bne.n 80043d6 { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 80043c2: 4b13 ldr r3, [pc, #76] ; (8004410 ) 80043c4: 6cdb ldr r3, [r3, #76] ; 0x4c 80043c6: f023 0203 bic.w r2, r3, #3 80043ca: 687b ldr r3, [r7, #4] 80043cc: 6c5b ldr r3, [r3, #68] ; 0x44 80043ce: 4910 ldr r1, [pc, #64] ; (8004410 ) 80043d0: 4313 orrs r3, r2 80043d2: 64cb str r3, [r1, #76] ; 0x4c 80043d4: e001 b.n 80043da } else { /* set overall return value */ status = ret; 80043d6: 7dfb ldrb r3, [r7, #23] 80043d8: 75bb strb r3, [r7, #22] } } /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 80043da: 687b ldr r3, [r7, #4] 80043dc: 681b ldr r3, [r3, #0] 80043de: f403 0380 and.w r3, r3, #4194304 ; 0x400000 80043e2: 2b00 cmp r3, #0 80043e4: f000 808a beq.w 80044fc { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 80043e8: 4b0a ldr r3, [pc, #40] ; (8004414 ) 80043ea: 681b ldr r3, [r3, #0] 80043ec: 4a09 ldr r2, [pc, #36] ; (8004414 ) 80043ee: f443 7380 orr.w r3, r3, #256 ; 0x100 80043f2: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80043f4: f7fd f8d4 bl 80015a0 80043f8: 6138 str r0, [r7, #16] while((PWR->CR1 & PWR_CR1_DBP) == 0U) 80043fa: e00d b.n 8004418 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80043fc: f7fd f8d0 bl 80015a0 8004400: 4602 mov r2, r0 8004402: 693b ldr r3, [r7, #16] 8004404: 1ad3 subs r3, r2, r3 8004406: 2b64 cmp r3, #100 ; 0x64 8004408: d906 bls.n 8004418 { ret = HAL_TIMEOUT; 800440a: 2303 movs r3, #3 800440c: 75fb strb r3, [r7, #23] break; 800440e: e009 b.n 8004424 8004410: 58024400 .word 0x58024400 8004414: 58024800 .word 0x58024800 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8004418: 4bb9 ldr r3, [pc, #740] ; (8004700 ) 800441a: 681b ldr r3, [r3, #0] 800441c: f403 7380 and.w r3, r3, #256 ; 0x100 8004420: 2b00 cmp r3, #0 8004422: d0eb beq.n 80043fc } } if(ret == HAL_OK) 8004424: 7dfb ldrb r3, [r7, #23] 8004426: 2b00 cmp r3, #0 8004428: d166 bne.n 80044f8 { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 800442a: 4bb6 ldr r3, [pc, #728] ; (8004704 ) 800442c: 6f1a ldr r2, [r3, #112] ; 0x70 800442e: 687b ldr r3, [r7, #4] 8004430: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 8004434: 4053 eors r3, r2 8004436: f403 7340 and.w r3, r3, #768 ; 0x300 800443a: 2b00 cmp r3, #0 800443c: d013 beq.n 8004466 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800443e: 4bb1 ldr r3, [pc, #708] ; (8004704 ) 8004440: 6f1b ldr r3, [r3, #112] ; 0x70 8004442: f423 7340 bic.w r3, r3, #768 ; 0x300 8004446: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8004448: 4bae ldr r3, [pc, #696] ; (8004704 ) 800444a: 6f1b ldr r3, [r3, #112] ; 0x70 800444c: 4aad ldr r2, [pc, #692] ; (8004704 ) 800444e: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8004452: 6713 str r3, [r2, #112] ; 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 8004454: 4bab ldr r3, [pc, #684] ; (8004704 ) 8004456: 6f1b ldr r3, [r3, #112] ; 0x70 8004458: 4aaa ldr r2, [pc, #680] ; (8004704 ) 800445a: f423 3380 bic.w r3, r3, #65536 ; 0x10000 800445e: 6713 str r3, [r2, #112] ; 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 8004460: 4aa8 ldr r2, [pc, #672] ; (8004704 ) 8004462: 68fb ldr r3, [r7, #12] 8004464: 6713 str r3, [r2, #112] ; 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 8004466: 687b ldr r3, [r7, #4] 8004468: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 800446c: f5b3 7f80 cmp.w r3, #256 ; 0x100 8004470: d115 bne.n 800449e { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004472: f7fd f895 bl 80015a0 8004476: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8004478: e00b b.n 8004492 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800447a: f7fd f891 bl 80015a0 800447e: 4602 mov r2, r0 8004480: 693b ldr r3, [r7, #16] 8004482: 1ad3 subs r3, r2, r3 8004484: f241 3288 movw r2, #5000 ; 0x1388 8004488: 4293 cmp r3, r2 800448a: d902 bls.n 8004492 { ret = HAL_TIMEOUT; 800448c: 2303 movs r3, #3 800448e: 75fb strb r3, [r7, #23] break; 8004490: e005 b.n 800449e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8004492: 4b9c ldr r3, [pc, #624] ; (8004704 ) 8004494: 6f1b ldr r3, [r3, #112] ; 0x70 8004496: f003 0302 and.w r3, r3, #2 800449a: 2b00 cmp r3, #0 800449c: d0ed beq.n 800447a } } } if(ret == HAL_OK) 800449e: 7dfb ldrb r3, [r7, #23] 80044a0: 2b00 cmp r3, #0 80044a2: d126 bne.n 80044f2 { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80044a4: 687b ldr r3, [r7, #4] 80044a6: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 80044aa: f403 7340 and.w r3, r3, #768 ; 0x300 80044ae: f5b3 7f40 cmp.w r3, #768 ; 0x300 80044b2: d10d bne.n 80044d0 80044b4: 4b93 ldr r3, [pc, #588] ; (8004704 ) 80044b6: 691b ldr r3, [r3, #16] 80044b8: f423 527c bic.w r2, r3, #16128 ; 0x3f00 80044bc: 687b ldr r3, [r7, #4] 80044be: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 80044c2: 0919 lsrs r1, r3, #4 80044c4: 4b90 ldr r3, [pc, #576] ; (8004708 ) 80044c6: 400b ands r3, r1 80044c8: 498e ldr r1, [pc, #568] ; (8004704 ) 80044ca: 4313 orrs r3, r2 80044cc: 610b str r3, [r1, #16] 80044ce: e005 b.n 80044dc 80044d0: 4b8c ldr r3, [pc, #560] ; (8004704 ) 80044d2: 691b ldr r3, [r3, #16] 80044d4: 4a8b ldr r2, [pc, #556] ; (8004704 ) 80044d6: f423 537c bic.w r3, r3, #16128 ; 0x3f00 80044da: 6113 str r3, [r2, #16] 80044dc: 4b89 ldr r3, [pc, #548] ; (8004704 ) 80044de: 6f1a ldr r2, [r3, #112] ; 0x70 80044e0: 687b ldr r3, [r7, #4] 80044e2: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 80044e6: f3c3 030b ubfx r3, r3, #0, #12 80044ea: 4986 ldr r1, [pc, #536] ; (8004704 ) 80044ec: 4313 orrs r3, r2 80044ee: 670b str r3, [r1, #112] ; 0x70 80044f0: e004 b.n 80044fc } else { /* set overall return value */ status = ret; 80044f2: 7dfb ldrb r3, [r7, #23] 80044f4: 75bb strb r3, [r7, #22] 80044f6: e001 b.n 80044fc } } else { /* set overall return value */ status = ret; 80044f8: 7dfb ldrb r3, [r7, #23] 80044fa: 75bb strb r3, [r7, #22] } } /*-------------------------- USART1/6 configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 80044fc: 687b ldr r3, [r7, #4] 80044fe: 681b ldr r3, [r3, #0] 8004500: f003 0301 and.w r3, r3, #1 8004504: 2b00 cmp r3, #0 8004506: d07e beq.n 8004606 { switch(PeriphClkInit->Usart16ClockSelection) 8004508: 687b ldr r3, [r7, #4] 800450a: 6f5b ldr r3, [r3, #116] ; 0x74 800450c: 2b28 cmp r3, #40 ; 0x28 800450e: d867 bhi.n 80045e0 8004510: a201 add r2, pc, #4 ; (adr r2, 8004518 ) 8004512: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004516: bf00 nop 8004518: 080045e7 .word 0x080045e7 800451c: 080045e1 .word 0x080045e1 8004520: 080045e1 .word 0x080045e1 8004524: 080045e1 .word 0x080045e1 8004528: 080045e1 .word 0x080045e1 800452c: 080045e1 .word 0x080045e1 8004530: 080045e1 .word 0x080045e1 8004534: 080045e1 .word 0x080045e1 8004538: 080045bd .word 0x080045bd 800453c: 080045e1 .word 0x080045e1 8004540: 080045e1 .word 0x080045e1 8004544: 080045e1 .word 0x080045e1 8004548: 080045e1 .word 0x080045e1 800454c: 080045e1 .word 0x080045e1 8004550: 080045e1 .word 0x080045e1 8004554: 080045e1 .word 0x080045e1 8004558: 080045cf .word 0x080045cf 800455c: 080045e1 .word 0x080045e1 8004560: 080045e1 .word 0x080045e1 8004564: 080045e1 .word 0x080045e1 8004568: 080045e1 .word 0x080045e1 800456c: 080045e1 .word 0x080045e1 8004570: 080045e1 .word 0x080045e1 8004574: 080045e1 .word 0x080045e1 8004578: 080045e7 .word 0x080045e7 800457c: 080045e1 .word 0x080045e1 8004580: 080045e1 .word 0x080045e1 8004584: 080045e1 .word 0x080045e1 8004588: 080045e1 .word 0x080045e1 800458c: 080045e1 .word 0x080045e1 8004590: 080045e1 .word 0x080045e1 8004594: 080045e1 .word 0x080045e1 8004598: 080045e7 .word 0x080045e7 800459c: 080045e1 .word 0x080045e1 80045a0: 080045e1 .word 0x080045e1 80045a4: 080045e1 .word 0x080045e1 80045a8: 080045e1 .word 0x080045e1 80045ac: 080045e1 .word 0x080045e1 80045b0: 080045e1 .word 0x080045e1 80045b4: 080045e1 .word 0x080045e1 80045b8: 080045e7 .word 0x080045e7 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 80045bc: 687b ldr r3, [r7, #4] 80045be: 3304 adds r3, #4 80045c0: 2101 movs r1, #1 80045c2: 4618 mov r0, r3 80045c4: f000 fb26 bl 8004c14 80045c8: 4603 mov r3, r0 80045ca: 75fb strb r3, [r7, #23] /* USART1/6 clock source configuration done later after clock selection check */ break; 80045cc: e00c b.n 80045e8 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 80045ce: 687b ldr r3, [r7, #4] 80045d0: 3324 adds r3, #36 ; 0x24 80045d2: 2101 movs r1, #1 80045d4: 4618 mov r0, r3 80045d6: f000 fbcf bl 8004d78 80045da: 4603 mov r3, r0 80045dc: 75fb strb r3, [r7, #23] /* USART1/6 clock source configuration done later after clock selection check */ break; 80045de: e003 b.n 80045e8 /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80045e0: 2301 movs r3, #1 80045e2: 75fb strb r3, [r7, #23] break; 80045e4: e000 b.n 80045e8 break; 80045e6: bf00 nop } if(ret == HAL_OK) 80045e8: 7dfb ldrb r3, [r7, #23] 80045ea: 2b00 cmp r3, #0 80045ec: d109 bne.n 8004602 { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 80045ee: 4b45 ldr r3, [pc, #276] ; (8004704 ) 80045f0: 6d5b ldr r3, [r3, #84] ; 0x54 80045f2: f023 0238 bic.w r2, r3, #56 ; 0x38 80045f6: 687b ldr r3, [r7, #4] 80045f8: 6f5b ldr r3, [r3, #116] ; 0x74 80045fa: 4942 ldr r1, [pc, #264] ; (8004704 ) 80045fc: 4313 orrs r3, r2 80045fe: 654b str r3, [r1, #84] ; 0x54 8004600: e001 b.n 8004606 } else { /* set overall return value */ status = ret; 8004602: 7dfb ldrb r3, [r7, #23] 8004604: 75bb strb r3, [r7, #22] } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 8004606: 687b ldr r3, [r7, #4] 8004608: 681b ldr r3, [r3, #0] 800460a: f003 0302 and.w r3, r3, #2 800460e: 2b00 cmp r3, #0 8004610: d037 beq.n 8004682 { switch(PeriphClkInit->Usart234578ClockSelection) 8004612: 687b ldr r3, [r7, #4] 8004614: 6f1b ldr r3, [r3, #112] ; 0x70 8004616: 2b05 cmp r3, #5 8004618: d820 bhi.n 800465c 800461a: a201 add r2, pc, #4 ; (adr r2, 8004620 ) 800461c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004620: 08004663 .word 0x08004663 8004624: 08004639 .word 0x08004639 8004628: 0800464b .word 0x0800464b 800462c: 08004663 .word 0x08004663 8004630: 08004663 .word 0x08004663 8004634: 08004663 .word 0x08004663 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8004638: 687b ldr r3, [r7, #4] 800463a: 3304 adds r3, #4 800463c: 2101 movs r1, #1 800463e: 4618 mov r0, r3 8004640: f000 fae8 bl 8004c14 8004644: 4603 mov r3, r0 8004646: 75fb strb r3, [r7, #23] /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8004648: e00c b.n 8004664 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 800464a: 687b ldr r3, [r7, #4] 800464c: 3324 adds r3, #36 ; 0x24 800464e: 2101 movs r1, #1 8004650: 4618 mov r0, r3 8004652: f000 fb91 bl 8004d78 8004656: 4603 mov r3, r0 8004658: 75fb strb r3, [r7, #23] /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800465a: e003 b.n 8004664 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800465c: 2301 movs r3, #1 800465e: 75fb strb r3, [r7, #23] break; 8004660: e000 b.n 8004664 break; 8004662: bf00 nop } if(ret == HAL_OK) 8004664: 7dfb ldrb r3, [r7, #23] 8004666: 2b00 cmp r3, #0 8004668: d109 bne.n 800467e { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 800466a: 4b26 ldr r3, [pc, #152] ; (8004704 ) 800466c: 6d5b ldr r3, [r3, #84] ; 0x54 800466e: f023 0207 bic.w r2, r3, #7 8004672: 687b ldr r3, [r7, #4] 8004674: 6f1b ldr r3, [r3, #112] ; 0x70 8004676: 4923 ldr r1, [pc, #140] ; (8004704 ) 8004678: 4313 orrs r3, r2 800467a: 654b str r3, [r1, #84] ; 0x54 800467c: e001 b.n 8004682 } else { /* set overall return value */ status = ret; 800467e: 7dfb ldrb r3, [r7, #23] 8004680: 75bb strb r3, [r7, #22] } } /*-------------------------- LPUART1 Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8004682: 687b ldr r3, [r7, #4] 8004684: 681b ldr r3, [r3, #0] 8004686: f003 0304 and.w r3, r3, #4 800468a: 2b00 cmp r3, #0 800468c: d040 beq.n 8004710 { switch(PeriphClkInit->Lpuart1ClockSelection) 800468e: 687b ldr r3, [r7, #4] 8004690: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8004694: 2b05 cmp r3, #5 8004696: d821 bhi.n 80046dc 8004698: a201 add r2, pc, #4 ; (adr r2, 80046a0 ) 800469a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800469e: bf00 nop 80046a0: 080046e3 .word 0x080046e3 80046a4: 080046b9 .word 0x080046b9 80046a8: 080046cb .word 0x080046cb 80046ac: 080046e3 .word 0x080046e3 80046b0: 080046e3 .word 0x080046e3 80046b4: 080046e3 .word 0x080046e3 case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 80046b8: 687b ldr r3, [r7, #4] 80046ba: 3304 adds r3, #4 80046bc: 2101 movs r1, #1 80046be: 4618 mov r0, r3 80046c0: f000 faa8 bl 8004c14 80046c4: 4603 mov r3, r0 80046c6: 75fb strb r3, [r7, #23] /* LPUART1 clock source configuration done later after clock selection check */ break; 80046c8: e00c b.n 80046e4 case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 80046ca: 687b ldr r3, [r7, #4] 80046cc: 3324 adds r3, #36 ; 0x24 80046ce: 2101 movs r1, #1 80046d0: 4618 mov r0, r3 80046d2: f000 fb51 bl 8004d78 80046d6: 4603 mov r3, r0 80046d8: 75fb strb r3, [r7, #23] /* LPUART1 clock source configuration done later after clock selection check */ break; 80046da: e003 b.n 80046e4 /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80046dc: 2301 movs r3, #1 80046de: 75fb strb r3, [r7, #23] break; 80046e0: e000 b.n 80046e4 break; 80046e2: bf00 nop } if(ret == HAL_OK) 80046e4: 7dfb ldrb r3, [r7, #23] 80046e6: 2b00 cmp r3, #0 80046e8: d110 bne.n 800470c { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 80046ea: 4b06 ldr r3, [pc, #24] ; (8004704 ) 80046ec: 6d9b ldr r3, [r3, #88] ; 0x58 80046ee: f023 0207 bic.w r2, r3, #7 80046f2: 687b ldr r3, [r7, #4] 80046f4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 80046f8: 4902 ldr r1, [pc, #8] ; (8004704 ) 80046fa: 4313 orrs r3, r2 80046fc: 658b str r3, [r1, #88] ; 0x58 80046fe: e007 b.n 8004710 8004700: 58024800 .word 0x58024800 8004704: 58024400 .word 0x58024400 8004708: 00ffffcf .word 0x00ffffcf } else { /* set overall return value */ status = ret; 800470c: 7dfb ldrb r3, [r7, #23] 800470e: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8004710: 687b ldr r3, [r7, #4] 8004712: 681b ldr r3, [r3, #0] 8004714: f003 0320 and.w r3, r3, #32 8004718: 2b00 cmp r3, #0 800471a: d04b beq.n 80047b4 { switch(PeriphClkInit->Lptim1ClockSelection) 800471c: 687b ldr r3, [r7, #4] 800471e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8004722: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8004726: d02e beq.n 8004786 8004728: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 800472c: d828 bhi.n 8004780 800472e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004732: d02a beq.n 800478a 8004734: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004738: d822 bhi.n 8004780 800473a: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 800473e: d026 beq.n 800478e 8004740: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8004744: d81c bhi.n 8004780 8004746: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800474a: d010 beq.n 800476e 800474c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004750: d816 bhi.n 8004780 8004752: 2b00 cmp r3, #0 8004754: d01d beq.n 8004792 8004756: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 800475a: d111 bne.n 8004780 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 800475c: 687b ldr r3, [r7, #4] 800475e: 3304 adds r3, #4 8004760: 2100 movs r1, #0 8004762: 4618 mov r0, r3 8004764: f000 fa56 bl 8004c14 8004768: 4603 mov r3, r0 800476a: 75fb strb r3, [r7, #23] /* LPTIM1 clock source configuration done later after clock selection check */ break; 800476c: e012 b.n 8004794 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 800476e: 687b ldr r3, [r7, #4] 8004770: 3324 adds r3, #36 ; 0x24 8004772: 2102 movs r1, #2 8004774: 4618 mov r0, r3 8004776: f000 faff bl 8004d78 800477a: 4603 mov r3, r0 800477c: 75fb strb r3, [r7, #23] /* LPTIM1 clock source configuration done later after clock selection check */ break; 800477e: e009 b.n 8004794 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004780: 2301 movs r3, #1 8004782: 75fb strb r3, [r7, #23] break; 8004784: e006 b.n 8004794 break; 8004786: bf00 nop 8004788: e004 b.n 8004794 break; 800478a: bf00 nop 800478c: e002 b.n 8004794 break; 800478e: bf00 nop 8004790: e000 b.n 8004794 break; 8004792: bf00 nop } if(ret == HAL_OK) 8004794: 7dfb ldrb r3, [r7, #23] 8004796: 2b00 cmp r3, #0 8004798: d10a bne.n 80047b0 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800479a: 4bb2 ldr r3, [pc, #712] ; (8004a64 ) 800479c: 6d5b ldr r3, [r3, #84] ; 0x54 800479e: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000 80047a2: 687b ldr r3, [r7, #4] 80047a4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80047a8: 49ae ldr r1, [pc, #696] ; (8004a64 ) 80047aa: 4313 orrs r3, r2 80047ac: 654b str r3, [r1, #84] ; 0x54 80047ae: e001 b.n 80047b4 } else { /* set overall return value */ status = ret; 80047b0: 7dfb ldrb r3, [r7, #23] 80047b2: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 80047b4: 687b ldr r3, [r7, #4] 80047b6: 681b ldr r3, [r3, #0] 80047b8: f003 0340 and.w r3, r3, #64 ; 0x40 80047bc: 2b00 cmp r3, #0 80047be: d04b beq.n 8004858 { switch(PeriphClkInit->Lptim2ClockSelection) 80047c0: 687b ldr r3, [r7, #4] 80047c2: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 80047c6: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 80047ca: d02e beq.n 800482a 80047cc: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 80047d0: d828 bhi.n 8004824 80047d2: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80047d6: d02a beq.n 800482e 80047d8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80047dc: d822 bhi.n 8004824 80047de: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 80047e2: d026 beq.n 8004832 80047e4: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 80047e8: d81c bhi.n 8004824 80047ea: f5b3 6f00 cmp.w r3, #2048 ; 0x800 80047ee: d010 beq.n 8004812 80047f0: f5b3 6f00 cmp.w r3, #2048 ; 0x800 80047f4: d816 bhi.n 8004824 80047f6: 2b00 cmp r3, #0 80047f8: d01d beq.n 8004836 80047fa: f5b3 6f80 cmp.w r3, #1024 ; 0x400 80047fe: d111 bne.n 8004824 /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8004800: 687b ldr r3, [r7, #4] 8004802: 3304 adds r3, #4 8004804: 2100 movs r1, #0 8004806: 4618 mov r0, r3 8004808: f000 fa04 bl 8004c14 800480c: 4603 mov r3, r0 800480e: 75fb strb r3, [r7, #23] /* LPTIM2 clock source configuration done later after clock selection check */ break; 8004810: e012 b.n 8004838 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8004812: 687b ldr r3, [r7, #4] 8004814: 3324 adds r3, #36 ; 0x24 8004816: 2102 movs r1, #2 8004818: 4618 mov r0, r3 800481a: f000 faad bl 8004d78 800481e: 4603 mov r3, r0 8004820: 75fb strb r3, [r7, #23] /* LPTIM2 clock source configuration done later after clock selection check */ break; 8004822: e009 b.n 8004838 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004824: 2301 movs r3, #1 8004826: 75fb strb r3, [r7, #23] break; 8004828: e006 b.n 8004838 break; 800482a: bf00 nop 800482c: e004 b.n 8004838 break; 800482e: bf00 nop 8004830: e002 b.n 8004838 break; 8004832: bf00 nop 8004834: e000 b.n 8004838 break; 8004836: bf00 nop } if(ret == HAL_OK) 8004838: 7dfb ldrb r3, [r7, #23] 800483a: 2b00 cmp r3, #0 800483c: d10a bne.n 8004854 { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800483e: 4b89 ldr r3, [pc, #548] ; (8004a64 ) 8004840: 6d9b ldr r3, [r3, #88] ; 0x58 8004842: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 8004846: 687b ldr r3, [r7, #4] 8004848: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 800484c: 4985 ldr r1, [pc, #532] ; (8004a64 ) 800484e: 4313 orrs r3, r2 8004850: 658b str r3, [r1, #88] ; 0x58 8004852: e001 b.n 8004858 } else { /* set overall return value */ status = ret; 8004854: 7dfb ldrb r3, [r7, #23] 8004856: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 8004858: 687b ldr r3, [r7, #4] 800485a: 681b ldr r3, [r3, #0] 800485c: f003 0380 and.w r3, r3, #128 ; 0x80 8004860: 2b00 cmp r3, #0 8004862: d04b beq.n 80048fc { switch(PeriphClkInit->Lptim345ClockSelection) 8004864: 687b ldr r3, [r7, #4] 8004866: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 800486a: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 800486e: d02e beq.n 80048ce 8004870: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 8004874: d828 bhi.n 80048c8 8004876: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 800487a: d02a beq.n 80048d2 800487c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8004880: d822 bhi.n 80048c8 8004882: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 8004886: d026 beq.n 80048d6 8004888: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 800488c: d81c bhi.n 80048c8 800488e: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8004892: d010 beq.n 80048b6 8004894: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8004898: d816 bhi.n 80048c8 800489a: 2b00 cmp r3, #0 800489c: d01d beq.n 80048da 800489e: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80048a2: d111 bne.n 80048c8 case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 80048a4: 687b ldr r3, [r7, #4] 80048a6: 3304 adds r3, #4 80048a8: 2100 movs r1, #0 80048aa: 4618 mov r0, r3 80048ac: f000 f9b2 bl 8004c14 80048b0: 4603 mov r3, r0 80048b2: 75fb strb r3, [r7, #23] /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 80048b4: e012 b.n 80048dc case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 80048b6: 687b ldr r3, [r7, #4] 80048b8: 3324 adds r3, #36 ; 0x24 80048ba: 2102 movs r1, #2 80048bc: 4618 mov r0, r3 80048be: f000 fa5b bl 8004d78 80048c2: 4603 mov r3, r0 80048c4: 75fb strb r3, [r7, #23] /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 80048c6: e009 b.n 80048dc /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80048c8: 2301 movs r3, #1 80048ca: 75fb strb r3, [r7, #23] break; 80048cc: e006 b.n 80048dc break; 80048ce: bf00 nop 80048d0: e004 b.n 80048dc break; 80048d2: bf00 nop 80048d4: e002 b.n 80048dc break; 80048d6: bf00 nop 80048d8: e000 b.n 80048dc break; 80048da: bf00 nop } if(ret == HAL_OK) 80048dc: 7dfb ldrb r3, [r7, #23] 80048de: 2b00 cmp r3, #0 80048e0: d10a bne.n 80048f8 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 80048e2: 4b60 ldr r3, [pc, #384] ; (8004a64 ) 80048e4: 6d9b ldr r3, [r3, #88] ; 0x58 80048e6: f423 4260 bic.w r2, r3, #57344 ; 0xe000 80048ea: 687b ldr r3, [r7, #4] 80048ec: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 80048f0: 495c ldr r1, [pc, #368] ; (8004a64 ) 80048f2: 4313 orrs r3, r2 80048f4: 658b str r3, [r1, #88] ; 0x58 80048f6: e001 b.n 80048fc } else { /* set overall return value */ status = ret; 80048f8: 7dfb ldrb r3, [r7, #23] 80048fa: 75bb strb r3, [r7, #22] } } /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ #if defined(I2C5) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) 80048fc: 687b ldr r3, [r7, #4] 80048fe: 681b ldr r3, [r3, #0] 8004900: f003 0308 and.w r3, r3, #8 8004904: 2b00 cmp r3, #0 8004906: d018 beq.n 800493a { /* Check the parameters */ assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection)); if ((PeriphClkInit->I2c1235ClockSelection )== RCC_I2C1235CLKSOURCE_PLL3 ) 8004908: 687b ldr r3, [r7, #4] 800490a: 6fdb ldr r3, [r3, #124] ; 0x7c 800490c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004910: d10a bne.n 8004928 { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 8004912: 687b ldr r3, [r7, #4] 8004914: 3324 adds r3, #36 ; 0x24 8004916: 2102 movs r1, #2 8004918: 4618 mov r0, r3 800491a: f000 fa2d bl 8004d78 800491e: 4603 mov r3, r0 8004920: 2b00 cmp r3, #0 8004922: d001 beq.n 8004928 { status = HAL_ERROR; 8004924: 2301 movs r3, #1 8004926: 75bb strb r3, [r7, #22] } } __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); 8004928: 4b4e ldr r3, [pc, #312] ; (8004a64 ) 800492a: 6d5b ldr r3, [r3, #84] ; 0x54 800492c: f423 5240 bic.w r2, r3, #12288 ; 0x3000 8004930: 687b ldr r3, [r7, #4] 8004932: 6fdb ldr r3, [r3, #124] ; 0x7c 8004934: 494b ldr r1, [pc, #300] ; (8004a64 ) 8004936: 4313 orrs r3, r2 8004938: 654b str r3, [r1, #84] ; 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800493a: 687b ldr r3, [r7, #4] 800493c: 681b ldr r3, [r3, #0] 800493e: f003 0310 and.w r3, r3, #16 8004942: 2b00 cmp r3, #0 8004944: d01a beq.n 800497c { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 ) 8004946: 687b ldr r3, [r7, #4] 8004948: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 800494c: f5b3 7f80 cmp.w r3, #256 ; 0x100 8004950: d10a bne.n 8004968 { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 8004952: 687b ldr r3, [r7, #4] 8004954: 3324 adds r3, #36 ; 0x24 8004956: 2102 movs r1, #2 8004958: 4618 mov r0, r3 800495a: f000 fa0d bl 8004d78 800495e: 4603 mov r3, r0 8004960: 2b00 cmp r3, #0 8004962: d001 beq.n 8004968 { status = HAL_ERROR; 8004964: 2301 movs r3, #1 8004966: 75bb strb r3, [r7, #22] } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 8004968: 4b3e ldr r3, [pc, #248] ; (8004a64 ) 800496a: 6d9b ldr r3, [r3, #88] ; 0x58 800496c: f423 7240 bic.w r2, r3, #768 ; 0x300 8004970: 687b ldr r3, [r7, #4] 8004972: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8004976: 493b ldr r1, [pc, #236] ; (8004a64 ) 8004978: 4313 orrs r3, r2 800497a: 658b str r3, [r1, #88] ; 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800497c: 687b ldr r3, [r7, #4] 800497e: 681b ldr r3, [r3, #0] 8004980: f403 2300 and.w r3, r3, #524288 ; 0x80000 8004984: 2b00 cmp r3, #0 8004986: d034 beq.n 80049f2 { switch(PeriphClkInit->AdcClockSelection) 8004988: 687b ldr r3, [r7, #4] 800498a: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 800498e: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8004992: d01d beq.n 80049d0 8004994: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8004998: d817 bhi.n 80049ca 800499a: 2b00 cmp r3, #0 800499c: d003 beq.n 80049a6 800499e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80049a2: d009 beq.n 80049b8 80049a4: e011 b.n 80049ca { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 80049a6: 687b ldr r3, [r7, #4] 80049a8: 3304 adds r3, #4 80049aa: 2100 movs r1, #0 80049ac: 4618 mov r0, r3 80049ae: f000 f931 bl 8004c14 80049b2: 4603 mov r3, r0 80049b4: 75fb strb r3, [r7, #23] /* ADC clock source configuration done later after clock selection check */ break; 80049b6: e00c b.n 80049d2 case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 80049b8: 687b ldr r3, [r7, #4] 80049ba: 3324 adds r3, #36 ; 0x24 80049bc: 2102 movs r1, #2 80049be: 4618 mov r0, r3 80049c0: f000 f9da bl 8004d78 80049c4: 4603 mov r3, r0 80049c6: 75fb strb r3, [r7, #23] /* ADC clock source configuration done later after clock selection check */ break; 80049c8: e003 b.n 80049d2 /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80049ca: 2301 movs r3, #1 80049cc: 75fb strb r3, [r7, #23] break; 80049ce: e000 b.n 80049d2 break; 80049d0: bf00 nop } if(ret == HAL_OK) 80049d2: 7dfb ldrb r3, [r7, #23] 80049d4: 2b00 cmp r3, #0 80049d6: d10a bne.n 80049ee { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 80049d8: 4b22 ldr r3, [pc, #136] ; (8004a64 ) 80049da: 6d9b ldr r3, [r3, #88] ; 0x58 80049dc: f423 3240 bic.w r2, r3, #196608 ; 0x30000 80049e0: 687b ldr r3, [r7, #4] 80049e2: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 80049e6: 491f ldr r1, [pc, #124] ; (8004a64 ) 80049e8: 4313 orrs r3, r2 80049ea: 658b str r3, [r1, #88] ; 0x58 80049ec: e001 b.n 80049f2 } else { /* set overall return value */ status = ret; 80049ee: 7dfb ldrb r3, [r7, #23] 80049f0: 75bb strb r3, [r7, #22] } } /*------------------------------ USB Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 80049f2: 687b ldr r3, [r7, #4] 80049f4: 681b ldr r3, [r3, #0] 80049f6: f403 2380 and.w r3, r3, #262144 ; 0x40000 80049fa: 2b00 cmp r3, #0 80049fc: d036 beq.n 8004a6c { switch(PeriphClkInit->UsbClockSelection) 80049fe: 687b ldr r3, [r7, #4] 8004a00: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8004a04: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8004a08: d01c beq.n 8004a44 8004a0a: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8004a0e: d816 bhi.n 8004a3e 8004a10: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8004a14: d003 beq.n 8004a1e 8004a16: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8004a1a: d007 beq.n 8004a2c 8004a1c: e00f b.n 8004a3e { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004a1e: 4b11 ldr r3, [pc, #68] ; (8004a64 ) 8004a20: 6adb ldr r3, [r3, #44] ; 0x2c 8004a22: 4a10 ldr r2, [pc, #64] ; (8004a64 ) 8004a24: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004a28: 62d3 str r3, [r2, #44] ; 0x2c /* USB clock source configuration done later after clock selection check */ break; 8004a2a: e00c b.n 8004a46 case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8004a2c: 687b ldr r3, [r7, #4] 8004a2e: 3324 adds r3, #36 ; 0x24 8004a30: 2101 movs r1, #1 8004a32: 4618 mov r0, r3 8004a34: f000 f9a0 bl 8004d78 8004a38: 4603 mov r3, r0 8004a3a: 75fb strb r3, [r7, #23] /* USB clock source configuration done later after clock selection check */ break; 8004a3c: e003 b.n 8004a46 /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004a3e: 2301 movs r3, #1 8004a40: 75fb strb r3, [r7, #23] break; 8004a42: e000 b.n 8004a46 break; 8004a44: bf00 nop } if(ret == HAL_OK) 8004a46: 7dfb ldrb r3, [r7, #23] 8004a48: 2b00 cmp r3, #0 8004a4a: d10d bne.n 8004a68 { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8004a4c: 4b05 ldr r3, [pc, #20] ; (8004a64 ) 8004a4e: 6d5b ldr r3, [r3, #84] ; 0x54 8004a50: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8004a54: 687b ldr r3, [r7, #4] 8004a56: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8004a5a: 4902 ldr r1, [pc, #8] ; (8004a64 ) 8004a5c: 4313 orrs r3, r2 8004a5e: 654b str r3, [r1, #84] ; 0x54 8004a60: e004 b.n 8004a6c 8004a62: bf00 nop 8004a64: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8004a68: 7dfb ldrb r3, [r7, #23] 8004a6a: 75bb strb r3, [r7, #22] } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 8004a6c: 687b ldr r3, [r7, #4] 8004a6e: 681b ldr r3, [r3, #0] 8004a70: f403 3380 and.w r3, r3, #65536 ; 0x10000 8004a74: 2b00 cmp r3, #0 8004a76: d029 beq.n 8004acc { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch(PeriphClkInit->SdmmcClockSelection) 8004a78: 687b ldr r3, [r7, #4] 8004a7a: 6cdb ldr r3, [r3, #76] ; 0x4c 8004a7c: 2b00 cmp r3, #0 8004a7e: d003 beq.n 8004a88 8004a80: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8004a84: d007 beq.n 8004a96 8004a86: e00f b.n 8004aa8 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004a88: 4b61 ldr r3, [pc, #388] ; (8004c10 ) 8004a8a: 6adb ldr r3, [r3, #44] ; 0x2c 8004a8c: 4a60 ldr r2, [pc, #384] ; (8004c10 ) 8004a8e: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004a92: 62d3 str r3, [r2, #44] ; 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 8004a94: e00b b.n 8004aae case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8004a96: 687b ldr r3, [r7, #4] 8004a98: 3304 adds r3, #4 8004a9a: 2102 movs r1, #2 8004a9c: 4618 mov r0, r3 8004a9e: f000 f8b9 bl 8004c14 8004aa2: 4603 mov r3, r0 8004aa4: 75fb strb r3, [r7, #23] /* SDMMC clock source configuration done later after clock selection check */ break; 8004aa6: e002 b.n 8004aae default: ret = HAL_ERROR; 8004aa8: 2301 movs r3, #1 8004aaa: 75fb strb r3, [r7, #23] break; 8004aac: bf00 nop } if(ret == HAL_OK) 8004aae: 7dfb ldrb r3, [r7, #23] 8004ab0: 2b00 cmp r3, #0 8004ab2: d109 bne.n 8004ac8 { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 8004ab4: 4b56 ldr r3, [pc, #344] ; (8004c10 ) 8004ab6: 6cdb ldr r3, [r3, #76] ; 0x4c 8004ab8: f423 3280 bic.w r2, r3, #65536 ; 0x10000 8004abc: 687b ldr r3, [r7, #4] 8004abe: 6cdb ldr r3, [r3, #76] ; 0x4c 8004ac0: 4953 ldr r1, [pc, #332] ; (8004c10 ) 8004ac2: 4313 orrs r3, r2 8004ac4: 64cb str r3, [r1, #76] ; 0x4c 8004ac6: e001 b.n 8004acc } else { /* set overall return value */ status = ret; 8004ac8: 7dfb ldrb r3, [r7, #23] 8004aca: 75bb strb r3, [r7, #22] } } #if defined(LTDC) /*-------------------------------------- LTDC Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 8004acc: 687b ldr r3, [r7, #4] 8004ace: 681b ldr r3, [r3, #0] 8004ad0: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8004ad4: 2b00 cmp r3, #0 8004ad6: d00a beq.n 8004aee { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK) 8004ad8: 687b ldr r3, [r7, #4] 8004ada: 3324 adds r3, #36 ; 0x24 8004adc: 2102 movs r1, #2 8004ade: 4618 mov r0, r3 8004ae0: f000 f94a bl 8004d78 8004ae4: 4603 mov r3, r0 8004ae6: 2b00 cmp r3, #0 8004ae8: d001 beq.n 8004aee { status=HAL_ERROR; 8004aea: 2301 movs r3, #1 8004aec: 75bb strb r3, [r7, #22] } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 8004aee: 687b ldr r3, [r7, #4] 8004af0: 681b ldr r3, [r3, #0] 8004af2: f403 3300 and.w r3, r3, #131072 ; 0x20000 8004af6: 2b00 cmp r3, #0 8004af8: d030 beq.n 8004b5c { switch(PeriphClkInit->RngClockSelection) 8004afa: 687b ldr r3, [r7, #4] 8004afc: 6f9b ldr r3, [r3, #120] ; 0x78 8004afe: f5b3 7f40 cmp.w r3, #768 ; 0x300 8004b02: d017 beq.n 8004b34 8004b04: f5b3 7f40 cmp.w r3, #768 ; 0x300 8004b08: d811 bhi.n 8004b2e 8004b0a: f5b3 7f00 cmp.w r3, #512 ; 0x200 8004b0e: d013 beq.n 8004b38 8004b10: f5b3 7f00 cmp.w r3, #512 ; 0x200 8004b14: d80b bhi.n 8004b2e 8004b16: 2b00 cmp r3, #0 8004b18: d010 beq.n 8004b3c 8004b1a: f5b3 7f80 cmp.w r3, #256 ; 0x100 8004b1e: d106 bne.n 8004b2e { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004b20: 4b3b ldr r3, [pc, #236] ; (8004c10 ) 8004b22: 6adb ldr r3, [r3, #44] ; 0x2c 8004b24: 4a3a ldr r2, [pc, #232] ; (8004c10 ) 8004b26: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004b2a: 62d3 str r3, [r2, #44] ; 0x2c /* RNG clock source configuration done later after clock selection check */ break; 8004b2c: e007 b.n 8004b3e /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004b2e: 2301 movs r3, #1 8004b30: 75fb strb r3, [r7, #23] break; 8004b32: e004 b.n 8004b3e break; 8004b34: bf00 nop 8004b36: e002 b.n 8004b3e break; 8004b38: bf00 nop 8004b3a: e000 b.n 8004b3e break; 8004b3c: bf00 nop } if(ret == HAL_OK) 8004b3e: 7dfb ldrb r3, [r7, #23] 8004b40: 2b00 cmp r3, #0 8004b42: d109 bne.n 8004b58 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 8004b44: 4b32 ldr r3, [pc, #200] ; (8004c10 ) 8004b46: 6d5b ldr r3, [r3, #84] ; 0x54 8004b48: f423 7240 bic.w r2, r3, #768 ; 0x300 8004b4c: 687b ldr r3, [r7, #4] 8004b4e: 6f9b ldr r3, [r3, #120] ; 0x78 8004b50: 492f ldr r1, [pc, #188] ; (8004c10 ) 8004b52: 4313 orrs r3, r2 8004b54: 654b str r3, [r1, #84] ; 0x54 8004b56: e001 b.n 8004b5c } else { /* set overall return value */ status = ret; 8004b58: 7dfb ldrb r3, [r7, #23] 8004b5a: 75bb strb r3, [r7, #22] } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 8004b5c: 687b ldr r3, [r7, #4] 8004b5e: 681b ldr r3, [r3, #0] 8004b60: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8004b64: 2b00 cmp r3, #0 8004b66: d008 beq.n 8004b7a { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 8004b68: 4b29 ldr r3, [pc, #164] ; (8004c10 ) 8004b6a: 6d1b ldr r3, [r3, #80] ; 0x50 8004b6c: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 8004b70: 687b ldr r3, [r7, #4] 8004b72: 6edb ldr r3, [r3, #108] ; 0x6c 8004b74: 4926 ldr r1, [pc, #152] ; (8004c10 ) 8004b76: 4313 orrs r3, r2 8004b78: 650b str r3, [r1, #80] ; 0x50 /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 8004b7a: 687b ldr r3, [r7, #4] 8004b7c: 681b ldr r3, [r3, #0] 8004b7e: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8004b82: 2b00 cmp r3, #0 8004b84: d008 beq.n 8004b98 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 8004b86: 4b22 ldr r3, [pc, #136] ; (8004c10 ) 8004b88: 6d1b ldr r3, [r3, #80] ; 0x50 8004b8a: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000 8004b8e: 687b ldr r3, [r7, #4] 8004b90: 6e5b ldr r3, [r3, #100] ; 0x64 8004b92: 491f ldr r1, [pc, #124] ; (8004c10 ) 8004b94: 4313 orrs r3, r2 8004b96: 650b str r3, [r1, #80] ; 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 8004b98: 687b ldr r3, [r7, #4] 8004b9a: 681b ldr r3, [r3, #0] 8004b9c: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 8004ba0: 2b00 cmp r3, #0 8004ba2: d00d beq.n 8004bc0 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8004ba4: 4b1a ldr r3, [pc, #104] ; (8004c10 ) 8004ba6: 691b ldr r3, [r3, #16] 8004ba8: 4a19 ldr r2, [pc, #100] ; (8004c10 ) 8004baa: f423 4300 bic.w r3, r3, #32768 ; 0x8000 8004bae: 6113 str r3, [r2, #16] 8004bb0: 4b17 ldr r3, [pc, #92] ; (8004c10 ) 8004bb2: 691a ldr r2, [r3, #16] 8004bb4: 687b ldr r3, [r7, #4] 8004bb6: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8004bba: 4915 ldr r1, [pc, #84] ; (8004c10 ) 8004bbc: 4313 orrs r3, r2 8004bbe: 610b str r3, [r1, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 8004bc0: 687b ldr r3, [r7, #4] 8004bc2: 681b ldr r3, [r3, #0] 8004bc4: 2b00 cmp r3, #0 8004bc6: da08 bge.n 8004bda { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 8004bc8: 4b11 ldr r3, [pc, #68] ; (8004c10 ) 8004bca: 6cdb ldr r3, [r3, #76] ; 0x4c 8004bcc: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 8004bd0: 687b ldr r3, [r7, #4] 8004bd2: 6d1b ldr r3, [r3, #80] ; 0x50 8004bd4: 490e ldr r1, [pc, #56] ; (8004c10 ) 8004bd6: 4313 orrs r3, r2 8004bd8: 64cb str r3, [r1, #76] ; 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 8004bda: 687b ldr r3, [r7, #4] 8004bdc: 681b ldr r3, [r3, #0] 8004bde: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8004be2: 2b00 cmp r3, #0 8004be4: d009 beq.n 8004bfa { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 8004be6: 4b0a ldr r3, [pc, #40] ; (8004c10 ) 8004be8: 6d5b ldr r3, [r3, #84] ; 0x54 8004bea: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 8004bee: 687b ldr r3, [r7, #4] 8004bf0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8004bf4: 4906 ldr r1, [pc, #24] ; (8004c10 ) 8004bf6: 4313 orrs r3, r2 8004bf8: 654b str r3, [r1, #84] ; 0x54 } if (status == HAL_OK) 8004bfa: 7dbb ldrb r3, [r7, #22] 8004bfc: 2b00 cmp r3, #0 8004bfe: d101 bne.n 8004c04 { return HAL_OK; 8004c00: 2300 movs r3, #0 8004c02: e000 b.n 8004c06 } return HAL_ERROR; 8004c04: 2301 movs r3, #1 } 8004c06: 4618 mov r0, r3 8004c08: 3718 adds r7, #24 8004c0a: 46bd mov sp, r7 8004c0c: bd80 pop {r7, pc} 8004c0e: bf00 nop 8004c10: 58024400 .word 0x58024400 08004c14 : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 8004c14: b580 push {r7, lr} 8004c16: b084 sub sp, #16 8004c18: af00 add r7, sp, #0 8004c1a: 6078 str r0, [r7, #4] 8004c1c: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 8004c1e: 2300 movs r3, #0 8004c20: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8004c22: 4b53 ldr r3, [pc, #332] ; (8004d70 ) 8004c24: 6a9b ldr r3, [r3, #40] ; 0x28 8004c26: f003 0303 and.w r3, r3, #3 8004c2a: 2b03 cmp r3, #3 8004c2c: d101 bne.n 8004c32 { return HAL_ERROR; 8004c2e: 2301 movs r3, #1 8004c30: e099 b.n 8004d66 else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8004c32: 4b4f ldr r3, [pc, #316] ; (8004d70 ) 8004c34: 681b ldr r3, [r3, #0] 8004c36: 4a4e ldr r2, [pc, #312] ; (8004d70 ) 8004c38: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 8004c3c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004c3e: f7fc fcaf bl 80015a0 8004c42: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 8004c44: e008 b.n 8004c58 { if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 8004c46: f7fc fcab bl 80015a0 8004c4a: 4602 mov r2, r0 8004c4c: 68bb ldr r3, [r7, #8] 8004c4e: 1ad3 subs r3, r2, r3 8004c50: 2b02 cmp r3, #2 8004c52: d901 bls.n 8004c58 { return HAL_TIMEOUT; 8004c54: 2303 movs r3, #3 8004c56: e086 b.n 8004d66 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 8004c58: 4b45 ldr r3, [pc, #276] ; (8004d70 ) 8004c5a: 681b ldr r3, [r3, #0] 8004c5c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8004c60: 2b00 cmp r3, #0 8004c62: d1f0 bne.n 8004c46 } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 8004c64: 4b42 ldr r3, [pc, #264] ; (8004d70 ) 8004c66: 6a9b ldr r3, [r3, #40] ; 0x28 8004c68: f423 327c bic.w r2, r3, #258048 ; 0x3f000 8004c6c: 687b ldr r3, [r7, #4] 8004c6e: 681b ldr r3, [r3, #0] 8004c70: 031b lsls r3, r3, #12 8004c72: 493f ldr r1, [pc, #252] ; (8004d70 ) 8004c74: 4313 orrs r3, r2 8004c76: 628b str r3, [r1, #40] ; 0x28 8004c78: 687b ldr r3, [r7, #4] 8004c7a: 685b ldr r3, [r3, #4] 8004c7c: 3b01 subs r3, #1 8004c7e: f3c3 0208 ubfx r2, r3, #0, #9 8004c82: 687b ldr r3, [r7, #4] 8004c84: 689b ldr r3, [r3, #8] 8004c86: 3b01 subs r3, #1 8004c88: 025b lsls r3, r3, #9 8004c8a: b29b uxth r3, r3 8004c8c: 431a orrs r2, r3 8004c8e: 687b ldr r3, [r7, #4] 8004c90: 68db ldr r3, [r3, #12] 8004c92: 3b01 subs r3, #1 8004c94: 041b lsls r3, r3, #16 8004c96: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8004c9a: 431a orrs r2, r3 8004c9c: 687b ldr r3, [r7, #4] 8004c9e: 691b ldr r3, [r3, #16] 8004ca0: 3b01 subs r3, #1 8004ca2: 061b lsls r3, r3, #24 8004ca4: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 8004ca8: 4931 ldr r1, [pc, #196] ; (8004d70 ) 8004caa: 4313 orrs r3, r2 8004cac: 638b str r3, [r1, #56] ; 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 8004cae: 4b30 ldr r3, [pc, #192] ; (8004d70 ) 8004cb0: 6adb ldr r3, [r3, #44] ; 0x2c 8004cb2: f023 02c0 bic.w r2, r3, #192 ; 0xc0 8004cb6: 687b ldr r3, [r7, #4] 8004cb8: 695b ldr r3, [r3, #20] 8004cba: 492d ldr r1, [pc, #180] ; (8004d70 ) 8004cbc: 4313 orrs r3, r2 8004cbe: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 8004cc0: 4b2b ldr r3, [pc, #172] ; (8004d70 ) 8004cc2: 6adb ldr r3, [r3, #44] ; 0x2c 8004cc4: f023 0220 bic.w r2, r3, #32 8004cc8: 687b ldr r3, [r7, #4] 8004cca: 699b ldr r3, [r3, #24] 8004ccc: 4928 ldr r1, [pc, #160] ; (8004d70 ) 8004cce: 4313 orrs r3, r2 8004cd0: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 8004cd2: 4b27 ldr r3, [pc, #156] ; (8004d70 ) 8004cd4: 6adb ldr r3, [r3, #44] ; 0x2c 8004cd6: 4a26 ldr r2, [pc, #152] ; (8004d70 ) 8004cd8: f023 0310 bic.w r3, r3, #16 8004cdc: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 8004cde: 4b24 ldr r3, [pc, #144] ; (8004d70 ) 8004ce0: 6bda ldr r2, [r3, #60] ; 0x3c 8004ce2: 4b24 ldr r3, [pc, #144] ; (8004d74 ) 8004ce4: 4013 ands r3, r2 8004ce6: 687a ldr r2, [r7, #4] 8004ce8: 69d2 ldr r2, [r2, #28] 8004cea: 00d2 lsls r2, r2, #3 8004cec: 4920 ldr r1, [pc, #128] ; (8004d70 ) 8004cee: 4313 orrs r3, r2 8004cf0: 63cb str r3, [r1, #60] ; 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 8004cf2: 4b1f ldr r3, [pc, #124] ; (8004d70 ) 8004cf4: 6adb ldr r3, [r3, #44] ; 0x2c 8004cf6: 4a1e ldr r2, [pc, #120] ; (8004d70 ) 8004cf8: f043 0310 orr.w r3, r3, #16 8004cfc: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL2 clock output */ if(Divider == DIVIDER_P_UPDATE) 8004cfe: 683b ldr r3, [r7, #0] 8004d00: 2b00 cmp r3, #0 8004d02: d106 bne.n 8004d12 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 8004d04: 4b1a ldr r3, [pc, #104] ; (8004d70 ) 8004d06: 6adb ldr r3, [r3, #44] ; 0x2c 8004d08: 4a19 ldr r2, [pc, #100] ; (8004d70 ) 8004d0a: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8004d0e: 62d3 str r3, [r2, #44] ; 0x2c 8004d10: e00f b.n 8004d32 } else if(Divider == DIVIDER_Q_UPDATE) 8004d12: 683b ldr r3, [r7, #0] 8004d14: 2b01 cmp r3, #1 8004d16: d106 bne.n 8004d26 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 8004d18: 4b15 ldr r3, [pc, #84] ; (8004d70 ) 8004d1a: 6adb ldr r3, [r3, #44] ; 0x2c 8004d1c: 4a14 ldr r2, [pc, #80] ; (8004d70 ) 8004d1e: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8004d22: 62d3 str r3, [r2, #44] ; 0x2c 8004d24: e005 b.n 8004d32 } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 8004d26: 4b12 ldr r3, [pc, #72] ; (8004d70 ) 8004d28: 6adb ldr r3, [r3, #44] ; 0x2c 8004d2a: 4a11 ldr r2, [pc, #68] ; (8004d70 ) 8004d2c: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8004d30: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 8004d32: 4b0f ldr r3, [pc, #60] ; (8004d70 ) 8004d34: 681b ldr r3, [r3, #0] 8004d36: 4a0e ldr r2, [pc, #56] ; (8004d70 ) 8004d38: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8004d3c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004d3e: f7fc fc2f bl 80015a0 8004d42: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 8004d44: e008 b.n 8004d58 { if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 8004d46: f7fc fc2b bl 80015a0 8004d4a: 4602 mov r2, r0 8004d4c: 68bb ldr r3, [r7, #8] 8004d4e: 1ad3 subs r3, r2, r3 8004d50: 2b02 cmp r3, #2 8004d52: d901 bls.n 8004d58 { return HAL_TIMEOUT; 8004d54: 2303 movs r3, #3 8004d56: e006 b.n 8004d66 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 8004d58: 4b05 ldr r3, [pc, #20] ; (8004d70 ) 8004d5a: 681b ldr r3, [r3, #0] 8004d5c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8004d60: 2b00 cmp r3, #0 8004d62: d0f0 beq.n 8004d46 } } return status; 8004d64: 7bfb ldrb r3, [r7, #15] } 8004d66: 4618 mov r0, r3 8004d68: 3710 adds r7, #16 8004d6a: 46bd mov sp, r7 8004d6c: bd80 pop {r7, pc} 8004d6e: bf00 nop 8004d70: 58024400 .word 0x58024400 8004d74: ffff0007 .word 0xffff0007 08004d78 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 8004d78: b580 push {r7, lr} 8004d7a: b084 sub sp, #16 8004d7c: af00 add r7, sp, #0 8004d7e: 6078 str r0, [r7, #4] 8004d80: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 8004d82: 2300 movs r3, #0 8004d84: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8004d86: 4b53 ldr r3, [pc, #332] ; (8004ed4 ) 8004d88: 6a9b ldr r3, [r3, #40] ; 0x28 8004d8a: f003 0303 and.w r3, r3, #3 8004d8e: 2b03 cmp r3, #3 8004d90: d101 bne.n 8004d96 { return HAL_ERROR; 8004d92: 2301 movs r3, #1 8004d94: e099 b.n 8004eca else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 8004d96: 4b4f ldr r3, [pc, #316] ; (8004ed4 ) 8004d98: 681b ldr r3, [r3, #0] 8004d9a: 4a4e ldr r2, [pc, #312] ; (8004ed4 ) 8004d9c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8004da0: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004da2: f7fc fbfd bl 80015a0 8004da6: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 8004da8: e008 b.n 8004dbc { if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 8004daa: f7fc fbf9 bl 80015a0 8004dae: 4602 mov r2, r0 8004db0: 68bb ldr r3, [r7, #8] 8004db2: 1ad3 subs r3, r2, r3 8004db4: 2b02 cmp r3, #2 8004db6: d901 bls.n 8004dbc { return HAL_TIMEOUT; 8004db8: 2303 movs r3, #3 8004dba: e086 b.n 8004eca while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 8004dbc: 4b45 ldr r3, [pc, #276] ; (8004ed4 ) 8004dbe: 681b ldr r3, [r3, #0] 8004dc0: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8004dc4: 2b00 cmp r3, #0 8004dc6: d1f0 bne.n 8004daa } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 8004dc8: 4b42 ldr r3, [pc, #264] ; (8004ed4 ) 8004dca: 6a9b ldr r3, [r3, #40] ; 0x28 8004dcc: f023 727c bic.w r2, r3, #66060288 ; 0x3f00000 8004dd0: 687b ldr r3, [r7, #4] 8004dd2: 681b ldr r3, [r3, #0] 8004dd4: 051b lsls r3, r3, #20 8004dd6: 493f ldr r1, [pc, #252] ; (8004ed4 ) 8004dd8: 4313 orrs r3, r2 8004dda: 628b str r3, [r1, #40] ; 0x28 8004ddc: 687b ldr r3, [r7, #4] 8004dde: 685b ldr r3, [r3, #4] 8004de0: 3b01 subs r3, #1 8004de2: f3c3 0208 ubfx r2, r3, #0, #9 8004de6: 687b ldr r3, [r7, #4] 8004de8: 689b ldr r3, [r3, #8] 8004dea: 3b01 subs r3, #1 8004dec: 025b lsls r3, r3, #9 8004dee: b29b uxth r3, r3 8004df0: 431a orrs r2, r3 8004df2: 687b ldr r3, [r7, #4] 8004df4: 68db ldr r3, [r3, #12] 8004df6: 3b01 subs r3, #1 8004df8: 041b lsls r3, r3, #16 8004dfa: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8004dfe: 431a orrs r2, r3 8004e00: 687b ldr r3, [r7, #4] 8004e02: 691b ldr r3, [r3, #16] 8004e04: 3b01 subs r3, #1 8004e06: 061b lsls r3, r3, #24 8004e08: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 8004e0c: 4931 ldr r1, [pc, #196] ; (8004ed4 ) 8004e0e: 4313 orrs r3, r2 8004e10: 640b str r3, [r1, #64] ; 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 8004e12: 4b30 ldr r3, [pc, #192] ; (8004ed4 ) 8004e14: 6adb ldr r3, [r3, #44] ; 0x2c 8004e16: f423 6240 bic.w r2, r3, #3072 ; 0xc00 8004e1a: 687b ldr r3, [r7, #4] 8004e1c: 695b ldr r3, [r3, #20] 8004e1e: 492d ldr r1, [pc, #180] ; (8004ed4 ) 8004e20: 4313 orrs r3, r2 8004e22: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 8004e24: 4b2b ldr r3, [pc, #172] ; (8004ed4 ) 8004e26: 6adb ldr r3, [r3, #44] ; 0x2c 8004e28: f423 7200 bic.w r2, r3, #512 ; 0x200 8004e2c: 687b ldr r3, [r7, #4] 8004e2e: 699b ldr r3, [r3, #24] 8004e30: 4928 ldr r1, [pc, #160] ; (8004ed4 ) 8004e32: 4313 orrs r3, r2 8004e34: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 8004e36: 4b27 ldr r3, [pc, #156] ; (8004ed4 ) 8004e38: 6adb ldr r3, [r3, #44] ; 0x2c 8004e3a: 4a26 ldr r2, [pc, #152] ; (8004ed4 ) 8004e3c: f423 7380 bic.w r3, r3, #256 ; 0x100 8004e40: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 8004e42: 4b24 ldr r3, [pc, #144] ; (8004ed4 ) 8004e44: 6c5a ldr r2, [r3, #68] ; 0x44 8004e46: 4b24 ldr r3, [pc, #144] ; (8004ed8 ) 8004e48: 4013 ands r3, r2 8004e4a: 687a ldr r2, [r7, #4] 8004e4c: 69d2 ldr r2, [r2, #28] 8004e4e: 00d2 lsls r2, r2, #3 8004e50: 4920 ldr r1, [pc, #128] ; (8004ed4 ) 8004e52: 4313 orrs r3, r2 8004e54: 644b str r3, [r1, #68] ; 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 8004e56: 4b1f ldr r3, [pc, #124] ; (8004ed4 ) 8004e58: 6adb ldr r3, [r3, #44] ; 0x2c 8004e5a: 4a1e ldr r2, [pc, #120] ; (8004ed4 ) 8004e5c: f443 7380 orr.w r3, r3, #256 ; 0x100 8004e60: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL3 clock output */ if(Divider == DIVIDER_P_UPDATE) 8004e62: 683b ldr r3, [r7, #0] 8004e64: 2b00 cmp r3, #0 8004e66: d106 bne.n 8004e76 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 8004e68: 4b1a ldr r3, [pc, #104] ; (8004ed4 ) 8004e6a: 6adb ldr r3, [r3, #44] ; 0x2c 8004e6c: 4a19 ldr r2, [pc, #100] ; (8004ed4 ) 8004e6e: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 8004e72: 62d3 str r3, [r2, #44] ; 0x2c 8004e74: e00f b.n 8004e96 } else if(Divider == DIVIDER_Q_UPDATE) 8004e76: 683b ldr r3, [r7, #0] 8004e78: 2b01 cmp r3, #1 8004e7a: d106 bne.n 8004e8a { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 8004e7c: 4b15 ldr r3, [pc, #84] ; (8004ed4 ) 8004e7e: 6adb ldr r3, [r3, #44] ; 0x2c 8004e80: 4a14 ldr r2, [pc, #80] ; (8004ed4 ) 8004e82: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 8004e86: 62d3 str r3, [r2, #44] ; 0x2c 8004e88: e005 b.n 8004e96 } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 8004e8a: 4b12 ldr r3, [pc, #72] ; (8004ed4 ) 8004e8c: 6adb ldr r3, [r3, #44] ; 0x2c 8004e8e: 4a11 ldr r2, [pc, #68] ; (8004ed4 ) 8004e90: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8004e94: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 8004e96: 4b0f ldr r3, [pc, #60] ; (8004ed4 ) 8004e98: 681b ldr r3, [r3, #0] 8004e9a: 4a0e ldr r2, [pc, #56] ; (8004ed4 ) 8004e9c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8004ea0: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004ea2: f7fc fb7d bl 80015a0 8004ea6: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 8004ea8: e008 b.n 8004ebc { if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 8004eaa: f7fc fb79 bl 80015a0 8004eae: 4602 mov r2, r0 8004eb0: 68bb ldr r3, [r7, #8] 8004eb2: 1ad3 subs r3, r2, r3 8004eb4: 2b02 cmp r3, #2 8004eb6: d901 bls.n 8004ebc { return HAL_TIMEOUT; 8004eb8: 2303 movs r3, #3 8004eba: e006 b.n 8004eca while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 8004ebc: 4b05 ldr r3, [pc, #20] ; (8004ed4 ) 8004ebe: 681b ldr r3, [r3, #0] 8004ec0: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8004ec4: 2b00 cmp r3, #0 8004ec6: d0f0 beq.n 8004eaa } } return status; 8004ec8: 7bfb ldrb r3, [r7, #15] } 8004eca: 4618 mov r0, r3 8004ecc: 3710 adds r7, #16 8004ece: 46bd mov sp, r7 8004ed0: bd80 pop {r7, pc} 8004ed2: bf00 nop 8004ed4: 58024400 .word 0x58024400 8004ed8: ffff0007 .word 0xffff0007 08004edc : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8004edc: b580 push {r7, lr} 8004ede: b082 sub sp, #8 8004ee0: af00 add r7, sp, #0 8004ee2: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8004ee4: 687b ldr r3, [r7, #4] 8004ee6: 2b00 cmp r3, #0 8004ee8: d101 bne.n 8004eee { return HAL_ERROR; 8004eea: 2301 movs r3, #1 8004eec: e049 b.n 8004f82 assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8004eee: 687b ldr r3, [r7, #4] 8004ef0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8004ef4: b2db uxtb r3, r3 8004ef6: 2b00 cmp r3, #0 8004ef8: d106 bne.n 8004f08 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8004efa: 687b ldr r3, [r7, #4] 8004efc: 2200 movs r2, #0 8004efe: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8004f02: 6878 ldr r0, [r7, #4] 8004f04: f7fc f8f8 bl 80010f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8004f08: 687b ldr r3, [r7, #4] 8004f0a: 2202 movs r2, #2 8004f0c: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8004f10: 687b ldr r3, [r7, #4] 8004f12: 681a ldr r2, [r3, #0] 8004f14: 687b ldr r3, [r7, #4] 8004f16: 3304 adds r3, #4 8004f18: 4619 mov r1, r3 8004f1a: 4610 mov r0, r2 8004f1c: f000 fafc bl 8005518 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8004f20: 687b ldr r3, [r7, #4] 8004f22: 2201 movs r2, #1 8004f24: f883 2048 strb.w r2, [r3, #72] ; 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004f28: 687b ldr r3, [r7, #4] 8004f2a: 2201 movs r2, #1 8004f2c: f883 203e strb.w r2, [r3, #62] ; 0x3e 8004f30: 687b ldr r3, [r7, #4] 8004f32: 2201 movs r2, #1 8004f34: f883 203f strb.w r2, [r3, #63] ; 0x3f 8004f38: 687b ldr r3, [r7, #4] 8004f3a: 2201 movs r2, #1 8004f3c: f883 2040 strb.w r2, [r3, #64] ; 0x40 8004f40: 687b ldr r3, [r7, #4] 8004f42: 2201 movs r2, #1 8004f44: f883 2041 strb.w r2, [r3, #65] ; 0x41 8004f48: 687b ldr r3, [r7, #4] 8004f4a: 2201 movs r2, #1 8004f4c: f883 2042 strb.w r2, [r3, #66] ; 0x42 8004f50: 687b ldr r3, [r7, #4] 8004f52: 2201 movs r2, #1 8004f54: f883 2043 strb.w r2, [r3, #67] ; 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004f58: 687b ldr r3, [r7, #4] 8004f5a: 2201 movs r2, #1 8004f5c: f883 2044 strb.w r2, [r3, #68] ; 0x44 8004f60: 687b ldr r3, [r7, #4] 8004f62: 2201 movs r2, #1 8004f64: f883 2045 strb.w r2, [r3, #69] ; 0x45 8004f68: 687b ldr r3, [r7, #4] 8004f6a: 2201 movs r2, #1 8004f6c: f883 2046 strb.w r2, [r3, #70] ; 0x46 8004f70: 687b ldr r3, [r7, #4] 8004f72: 2201 movs r2, #1 8004f74: f883 2047 strb.w r2, [r3, #71] ; 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8004f78: 687b ldr r3, [r7, #4] 8004f7a: 2201 movs r2, #1 8004f7c: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8004f80: 2300 movs r3, #0 } 8004f82: 4618 mov r0, r3 8004f84: 3708 adds r7, #8 8004f86: 46bd mov sp, r7 8004f88: bd80 pop {r7, pc} ... 08004f8c : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8004f8c: b480 push {r7} 8004f8e: b085 sub sp, #20 8004f90: af00 add r7, sp, #0 8004f92: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 8004f94: 687b ldr r3, [r7, #4] 8004f96: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8004f9a: b2db uxtb r3, r3 8004f9c: 2b01 cmp r3, #1 8004f9e: d001 beq.n 8004fa4 { return HAL_ERROR; 8004fa0: 2301 movs r3, #1 8004fa2: e05e b.n 8005062 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8004fa4: 687b ldr r3, [r7, #4] 8004fa6: 2202 movs r2, #2 8004fa8: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8004fac: 687b ldr r3, [r7, #4] 8004fae: 681b ldr r3, [r3, #0] 8004fb0: 68da ldr r2, [r3, #12] 8004fb2: 687b ldr r3, [r7, #4] 8004fb4: 681b ldr r3, [r3, #0] 8004fb6: f042 0201 orr.w r2, r2, #1 8004fba: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8004fbc: 687b ldr r3, [r7, #4] 8004fbe: 681b ldr r3, [r3, #0] 8004fc0: 4a2b ldr r2, [pc, #172] ; (8005070 ) 8004fc2: 4293 cmp r3, r2 8004fc4: d02c beq.n 8005020 8004fc6: 687b ldr r3, [r7, #4] 8004fc8: 681b ldr r3, [r3, #0] 8004fca: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004fce: d027 beq.n 8005020 8004fd0: 687b ldr r3, [r7, #4] 8004fd2: 681b ldr r3, [r3, #0] 8004fd4: 4a27 ldr r2, [pc, #156] ; (8005074 ) 8004fd6: 4293 cmp r3, r2 8004fd8: d022 beq.n 8005020 8004fda: 687b ldr r3, [r7, #4] 8004fdc: 681b ldr r3, [r3, #0] 8004fde: 4a26 ldr r2, [pc, #152] ; (8005078 ) 8004fe0: 4293 cmp r3, r2 8004fe2: d01d beq.n 8005020 8004fe4: 687b ldr r3, [r7, #4] 8004fe6: 681b ldr r3, [r3, #0] 8004fe8: 4a24 ldr r2, [pc, #144] ; (800507c ) 8004fea: 4293 cmp r3, r2 8004fec: d018 beq.n 8005020 8004fee: 687b ldr r3, [r7, #4] 8004ff0: 681b ldr r3, [r3, #0] 8004ff2: 4a23 ldr r2, [pc, #140] ; (8005080 ) 8004ff4: 4293 cmp r3, r2 8004ff6: d013 beq.n 8005020 8004ff8: 687b ldr r3, [r7, #4] 8004ffa: 681b ldr r3, [r3, #0] 8004ffc: 4a21 ldr r2, [pc, #132] ; (8005084 ) 8004ffe: 4293 cmp r3, r2 8005000: d00e beq.n 8005020 8005002: 687b ldr r3, [r7, #4] 8005004: 681b ldr r3, [r3, #0] 8005006: 4a20 ldr r2, [pc, #128] ; (8005088 ) 8005008: 4293 cmp r3, r2 800500a: d009 beq.n 8005020 800500c: 687b ldr r3, [r7, #4] 800500e: 681b ldr r3, [r3, #0] 8005010: 4a1e ldr r2, [pc, #120] ; (800508c ) 8005012: 4293 cmp r3, r2 8005014: d004 beq.n 8005020 8005016: 687b ldr r3, [r7, #4] 8005018: 681b ldr r3, [r3, #0] 800501a: 4a1d ldr r2, [pc, #116] ; (8005090 ) 800501c: 4293 cmp r3, r2 800501e: d115 bne.n 800504c { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8005020: 687b ldr r3, [r7, #4] 8005022: 681b ldr r3, [r3, #0] 8005024: 689a ldr r2, [r3, #8] 8005026: 4b1b ldr r3, [pc, #108] ; (8005094 ) 8005028: 4013 ands r3, r2 800502a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800502c: 68fb ldr r3, [r7, #12] 800502e: 2b06 cmp r3, #6 8005030: d015 beq.n 800505e 8005032: 68fb ldr r3, [r7, #12] 8005034: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8005038: d011 beq.n 800505e { __HAL_TIM_ENABLE(htim); 800503a: 687b ldr r3, [r7, #4] 800503c: 681b ldr r3, [r3, #0] 800503e: 681a ldr r2, [r3, #0] 8005040: 687b ldr r3, [r7, #4] 8005042: 681b ldr r3, [r3, #0] 8005044: f042 0201 orr.w r2, r2, #1 8005048: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800504a: e008 b.n 800505e } } else { __HAL_TIM_ENABLE(htim); 800504c: 687b ldr r3, [r7, #4] 800504e: 681b ldr r3, [r3, #0] 8005050: 681a ldr r2, [r3, #0] 8005052: 687b ldr r3, [r7, #4] 8005054: 681b ldr r3, [r3, #0] 8005056: f042 0201 orr.w r2, r2, #1 800505a: 601a str r2, [r3, #0] 800505c: e000 b.n 8005060 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800505e: bf00 nop } /* Return function status */ return HAL_OK; 8005060: 2300 movs r3, #0 } 8005062: 4618 mov r0, r3 8005064: 3714 adds r7, #20 8005066: 46bd mov sp, r7 8005068: f85d 7b04 ldr.w r7, [sp], #4 800506c: 4770 bx lr 800506e: bf00 nop 8005070: 40010000 .word 0x40010000 8005074: 40000400 .word 0x40000400 8005078: 40000800 .word 0x40000800 800507c: 40000c00 .word 0x40000c00 8005080: 40010400 .word 0x40010400 8005084: 40001800 .word 0x40001800 8005088: 40014000 .word 0x40014000 800508c: 4000e000 .word 0x4000e000 8005090: 4000e400 .word 0x4000e400 8005094: 00010007 .word 0x00010007 08005098 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8005098: b580 push {r7, lr} 800509a: b082 sub sp, #8 800509c: af00 add r7, sp, #0 800509e: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 80050a0: 687b ldr r3, [r7, #4] 80050a2: 681b ldr r3, [r3, #0] 80050a4: 691b ldr r3, [r3, #16] 80050a6: f003 0302 and.w r3, r3, #2 80050aa: 2b02 cmp r3, #2 80050ac: d122 bne.n 80050f4 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 80050ae: 687b ldr r3, [r7, #4] 80050b0: 681b ldr r3, [r3, #0] 80050b2: 68db ldr r3, [r3, #12] 80050b4: f003 0302 and.w r3, r3, #2 80050b8: 2b02 cmp r3, #2 80050ba: d11b bne.n 80050f4 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 80050bc: 687b ldr r3, [r7, #4] 80050be: 681b ldr r3, [r3, #0] 80050c0: f06f 0202 mvn.w r2, #2 80050c4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80050c6: 687b ldr r3, [r7, #4] 80050c8: 2201 movs r2, #1 80050ca: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80050cc: 687b ldr r3, [r7, #4] 80050ce: 681b ldr r3, [r3, #0] 80050d0: 699b ldr r3, [r3, #24] 80050d2: f003 0303 and.w r3, r3, #3 80050d6: 2b00 cmp r3, #0 80050d8: d003 beq.n 80050e2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80050da: 6878 ldr r0, [r7, #4] 80050dc: f000 f9fe bl 80054dc 80050e0: e005 b.n 80050ee { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80050e2: 6878 ldr r0, [r7, #4] 80050e4: f000 f9f0 bl 80054c8 HAL_TIM_PWM_PulseFinishedCallback(htim); 80050e8: 6878 ldr r0, [r7, #4] 80050ea: f000 fa01 bl 80054f0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80050ee: 687b ldr r3, [r7, #4] 80050f0: 2200 movs r2, #0 80050f2: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 80050f4: 687b ldr r3, [r7, #4] 80050f6: 681b ldr r3, [r3, #0] 80050f8: 691b ldr r3, [r3, #16] 80050fa: f003 0304 and.w r3, r3, #4 80050fe: 2b04 cmp r3, #4 8005100: d122 bne.n 8005148 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 8005102: 687b ldr r3, [r7, #4] 8005104: 681b ldr r3, [r3, #0] 8005106: 68db ldr r3, [r3, #12] 8005108: f003 0304 and.w r3, r3, #4 800510c: 2b04 cmp r3, #4 800510e: d11b bne.n 8005148 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 8005110: 687b ldr r3, [r7, #4] 8005112: 681b ldr r3, [r3, #0] 8005114: f06f 0204 mvn.w r2, #4 8005118: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800511a: 687b ldr r3, [r7, #4] 800511c: 2202 movs r2, #2 800511e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8005120: 687b ldr r3, [r7, #4] 8005122: 681b ldr r3, [r3, #0] 8005124: 699b ldr r3, [r3, #24] 8005126: f403 7340 and.w r3, r3, #768 ; 0x300 800512a: 2b00 cmp r3, #0 800512c: d003 beq.n 8005136 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800512e: 6878 ldr r0, [r7, #4] 8005130: f000 f9d4 bl 80054dc 8005134: e005 b.n 8005142 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005136: 6878 ldr r0, [r7, #4] 8005138: f000 f9c6 bl 80054c8 HAL_TIM_PWM_PulseFinishedCallback(htim); 800513c: 6878 ldr r0, [r7, #4] 800513e: f000 f9d7 bl 80054f0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005142: 687b ldr r3, [r7, #4] 8005144: 2200 movs r2, #0 8005146: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 8005148: 687b ldr r3, [r7, #4] 800514a: 681b ldr r3, [r3, #0] 800514c: 691b ldr r3, [r3, #16] 800514e: f003 0308 and.w r3, r3, #8 8005152: 2b08 cmp r3, #8 8005154: d122 bne.n 800519c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 8005156: 687b ldr r3, [r7, #4] 8005158: 681b ldr r3, [r3, #0] 800515a: 68db ldr r3, [r3, #12] 800515c: f003 0308 and.w r3, r3, #8 8005160: 2b08 cmp r3, #8 8005162: d11b bne.n 800519c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 8005164: 687b ldr r3, [r7, #4] 8005166: 681b ldr r3, [r3, #0] 8005168: f06f 0208 mvn.w r2, #8 800516c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800516e: 687b ldr r3, [r7, #4] 8005170: 2204 movs r2, #4 8005172: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8005174: 687b ldr r3, [r7, #4] 8005176: 681b ldr r3, [r3, #0] 8005178: 69db ldr r3, [r3, #28] 800517a: f003 0303 and.w r3, r3, #3 800517e: 2b00 cmp r3, #0 8005180: d003 beq.n 800518a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8005182: 6878 ldr r0, [r7, #4] 8005184: f000 f9aa bl 80054dc 8005188: e005 b.n 8005196 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800518a: 6878 ldr r0, [r7, #4] 800518c: f000 f99c bl 80054c8 HAL_TIM_PWM_PulseFinishedCallback(htim); 8005190: 6878 ldr r0, [r7, #4] 8005192: f000 f9ad bl 80054f0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005196: 687b ldr r3, [r7, #4] 8005198: 2200 movs r2, #0 800519a: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 800519c: 687b ldr r3, [r7, #4] 800519e: 681b ldr r3, [r3, #0] 80051a0: 691b ldr r3, [r3, #16] 80051a2: f003 0310 and.w r3, r3, #16 80051a6: 2b10 cmp r3, #16 80051a8: d122 bne.n 80051f0 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 80051aa: 687b ldr r3, [r7, #4] 80051ac: 681b ldr r3, [r3, #0] 80051ae: 68db ldr r3, [r3, #12] 80051b0: f003 0310 and.w r3, r3, #16 80051b4: 2b10 cmp r3, #16 80051b6: d11b bne.n 80051f0 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 80051b8: 687b ldr r3, [r7, #4] 80051ba: 681b ldr r3, [r3, #0] 80051bc: f06f 0210 mvn.w r2, #16 80051c0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80051c2: 687b ldr r3, [r7, #4] 80051c4: 2208 movs r2, #8 80051c6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 80051c8: 687b ldr r3, [r7, #4] 80051ca: 681b ldr r3, [r3, #0] 80051cc: 69db ldr r3, [r3, #28] 80051ce: f403 7340 and.w r3, r3, #768 ; 0x300 80051d2: 2b00 cmp r3, #0 80051d4: d003 beq.n 80051de { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80051d6: 6878 ldr r0, [r7, #4] 80051d8: f000 f980 bl 80054dc 80051dc: e005 b.n 80051ea { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80051de: 6878 ldr r0, [r7, #4] 80051e0: f000 f972 bl 80054c8 HAL_TIM_PWM_PulseFinishedCallback(htim); 80051e4: 6878 ldr r0, [r7, #4] 80051e6: f000 f983 bl 80054f0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80051ea: 687b ldr r3, [r7, #4] 80051ec: 2200 movs r2, #0 80051ee: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 80051f0: 687b ldr r3, [r7, #4] 80051f2: 681b ldr r3, [r3, #0] 80051f4: 691b ldr r3, [r3, #16] 80051f6: f003 0301 and.w r3, r3, #1 80051fa: 2b01 cmp r3, #1 80051fc: d10e bne.n 800521c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 80051fe: 687b ldr r3, [r7, #4] 8005200: 681b ldr r3, [r3, #0] 8005202: 68db ldr r3, [r3, #12] 8005204: f003 0301 and.w r3, r3, #1 8005208: 2b01 cmp r3, #1 800520a: d107 bne.n 800521c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 800520c: 687b ldr r3, [r7, #4] 800520e: 681b ldr r3, [r3, #0] 8005210: f06f 0201 mvn.w r2, #1 8005214: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8005216: 6878 ldr r0, [r7, #4] 8005218: f7fb fbd8 bl 80009cc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 800521c: 687b ldr r3, [r7, #4] 800521e: 681b ldr r3, [r3, #0] 8005220: 691b ldr r3, [r3, #16] 8005222: f003 0380 and.w r3, r3, #128 ; 0x80 8005226: 2b80 cmp r3, #128 ; 0x80 8005228: d10e bne.n 8005248 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 800522a: 687b ldr r3, [r7, #4] 800522c: 681b ldr r3, [r3, #0] 800522e: 68db ldr r3, [r3, #12] 8005230: f003 0380 and.w r3, r3, #128 ; 0x80 8005234: 2b80 cmp r3, #128 ; 0x80 8005236: d107 bne.n 8005248 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 8005238: 687b ldr r3, [r7, #4] 800523a: 681b ldr r3, [r3, #0] 800523c: f06f 0280 mvn.w r2, #128 ; 0x80 8005240: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8005242: 6878 ldr r0, [r7, #4] 8005244: f000 fb52 bl 80058ec #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) 8005248: 687b ldr r3, [r7, #4] 800524a: 681b ldr r3, [r3, #0] 800524c: 691b ldr r3, [r3, #16] 800524e: f403 7380 and.w r3, r3, #256 ; 0x100 8005252: f5b3 7f80 cmp.w r3, #256 ; 0x100 8005256: d10e bne.n 8005276 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 8005258: 687b ldr r3, [r7, #4] 800525a: 681b ldr r3, [r3, #0] 800525c: 68db ldr r3, [r3, #12] 800525e: f003 0380 and.w r3, r3, #128 ; 0x80 8005262: 2b80 cmp r3, #128 ; 0x80 8005264: d107 bne.n 8005276 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 8005266: 687b ldr r3, [r7, #4] 8005268: 681b ldr r3, [r3, #0] 800526a: f46f 7280 mvn.w r2, #256 ; 0x100 800526e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 8005270: 6878 ldr r0, [r7, #4] 8005272: f000 fb45 bl 8005900 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 8005276: 687b ldr r3, [r7, #4] 8005278: 681b ldr r3, [r3, #0] 800527a: 691b ldr r3, [r3, #16] 800527c: f003 0340 and.w r3, r3, #64 ; 0x40 8005280: 2b40 cmp r3, #64 ; 0x40 8005282: d10e bne.n 80052a2 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 8005284: 687b ldr r3, [r7, #4] 8005286: 681b ldr r3, [r3, #0] 8005288: 68db ldr r3, [r3, #12] 800528a: f003 0340 and.w r3, r3, #64 ; 0x40 800528e: 2b40 cmp r3, #64 ; 0x40 8005290: d107 bne.n 80052a2 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 8005292: 687b ldr r3, [r7, #4] 8005294: 681b ldr r3, [r3, #0] 8005296: f06f 0240 mvn.w r2, #64 ; 0x40 800529a: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800529c: 6878 ldr r0, [r7, #4] 800529e: f000 f931 bl 8005504 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 80052a2: 687b ldr r3, [r7, #4] 80052a4: 681b ldr r3, [r3, #0] 80052a6: 691b ldr r3, [r3, #16] 80052a8: f003 0320 and.w r3, r3, #32 80052ac: 2b20 cmp r3, #32 80052ae: d10e bne.n 80052ce { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 80052b0: 687b ldr r3, [r7, #4] 80052b2: 681b ldr r3, [r3, #0] 80052b4: 68db ldr r3, [r3, #12] 80052b6: f003 0320 and.w r3, r3, #32 80052ba: 2b20 cmp r3, #32 80052bc: d107 bne.n 80052ce { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 80052be: 687b ldr r3, [r7, #4] 80052c0: 681b ldr r3, [r3, #0] 80052c2: f06f 0220 mvn.w r2, #32 80052c6: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 80052c8: 6878 ldr r0, [r7, #4] 80052ca: f000 fb05 bl 80058d8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 80052ce: bf00 nop 80052d0: 3708 adds r7, #8 80052d2: 46bd mov sp, r7 80052d4: bd80 pop {r7, pc} ... 080052d8 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { 80052d8: b580 push {r7, lr} 80052da: b084 sub sp, #16 80052dc: af00 add r7, sp, #0 80052de: 6078 str r0, [r7, #4] 80052e0: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80052e2: 2300 movs r3, #0 80052e4: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 80052e6: 687b ldr r3, [r7, #4] 80052e8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 80052ec: 2b01 cmp r3, #1 80052ee: d101 bne.n 80052f4 80052f0: 2302 movs r3, #2 80052f2: e0dc b.n 80054ae 80052f4: 687b ldr r3, [r7, #4] 80052f6: 2201 movs r2, #1 80052f8: f883 203c strb.w r2, [r3, #60] ; 0x3c htim->State = HAL_TIM_STATE_BUSY; 80052fc: 687b ldr r3, [r7, #4] 80052fe: 2202 movs r2, #2 8005300: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8005304: 687b ldr r3, [r7, #4] 8005306: 681b ldr r3, [r3, #0] 8005308: 689b ldr r3, [r3, #8] 800530a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 800530c: 68ba ldr r2, [r7, #8] 800530e: 4b6a ldr r3, [pc, #424] ; (80054b8 ) 8005310: 4013 ands r3, r2 8005312: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8005314: 68bb ldr r3, [r7, #8] 8005316: f423 437f bic.w r3, r3, #65280 ; 0xff00 800531a: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 800531c: 687b ldr r3, [r7, #4] 800531e: 681b ldr r3, [r3, #0] 8005320: 68ba ldr r2, [r7, #8] 8005322: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8005324: 683b ldr r3, [r7, #0] 8005326: 681b ldr r3, [r3, #0] 8005328: 4a64 ldr r2, [pc, #400] ; (80054bc ) 800532a: 4293 cmp r3, r2 800532c: f000 80a9 beq.w 8005482 8005330: 4a62 ldr r2, [pc, #392] ; (80054bc ) 8005332: 4293 cmp r3, r2 8005334: f200 80ae bhi.w 8005494 8005338: 4a61 ldr r2, [pc, #388] ; (80054c0 ) 800533a: 4293 cmp r3, r2 800533c: f000 80a1 beq.w 8005482 8005340: 4a5f ldr r2, [pc, #380] ; (80054c0 ) 8005342: 4293 cmp r3, r2 8005344: f200 80a6 bhi.w 8005494 8005348: 4a5e ldr r2, [pc, #376] ; (80054c4 ) 800534a: 4293 cmp r3, r2 800534c: f000 8099 beq.w 8005482 8005350: 4a5c ldr r2, [pc, #368] ; (80054c4 ) 8005352: 4293 cmp r3, r2 8005354: f200 809e bhi.w 8005494 8005358: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010 800535c: f000 8091 beq.w 8005482 8005360: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010 8005364: f200 8096 bhi.w 8005494 8005368: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 800536c: f000 8089 beq.w 8005482 8005370: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8005374: f200 808e bhi.w 8005494 8005378: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800537c: d03e beq.n 80053fc 800537e: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8005382: f200 8087 bhi.w 8005494 8005386: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 800538a: f000 8086 beq.w 800549a 800538e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8005392: d87f bhi.n 8005494 8005394: 2b70 cmp r3, #112 ; 0x70 8005396: d01a beq.n 80053ce 8005398: 2b70 cmp r3, #112 ; 0x70 800539a: d87b bhi.n 8005494 800539c: 2b60 cmp r3, #96 ; 0x60 800539e: d050 beq.n 8005442 80053a0: 2b60 cmp r3, #96 ; 0x60 80053a2: d877 bhi.n 8005494 80053a4: 2b50 cmp r3, #80 ; 0x50 80053a6: d03c beq.n 8005422 80053a8: 2b50 cmp r3, #80 ; 0x50 80053aa: d873 bhi.n 8005494 80053ac: 2b40 cmp r3, #64 ; 0x40 80053ae: d058 beq.n 8005462 80053b0: 2b40 cmp r3, #64 ; 0x40 80053b2: d86f bhi.n 8005494 80053b4: 2b30 cmp r3, #48 ; 0x30 80053b6: d064 beq.n 8005482 80053b8: 2b30 cmp r3, #48 ; 0x30 80053ba: d86b bhi.n 8005494 80053bc: 2b20 cmp r3, #32 80053be: d060 beq.n 8005482 80053c0: 2b20 cmp r3, #32 80053c2: d867 bhi.n 8005494 80053c4: 2b00 cmp r3, #0 80053c6: d05c beq.n 8005482 80053c8: 2b10 cmp r3, #16 80053ca: d05a beq.n 8005482 80053cc: e062 b.n 8005494 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80053ce: 687b ldr r3, [r7, #4] 80053d0: 6818 ldr r0, [r3, #0] 80053d2: 683b ldr r3, [r7, #0] 80053d4: 6899 ldr r1, [r3, #8] 80053d6: 683b ldr r3, [r7, #0] 80053d8: 685a ldr r2, [r3, #4] 80053da: 683b ldr r3, [r7, #0] 80053dc: 68db ldr r3, [r3, #12] 80053de: f000 f9bf bl 8005760 sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 80053e2: 687b ldr r3, [r7, #4] 80053e4: 681b ldr r3, [r3, #0] 80053e6: 689b ldr r3, [r3, #8] 80053e8: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 80053ea: 68bb ldr r3, [r7, #8] 80053ec: f043 0377 orr.w r3, r3, #119 ; 0x77 80053f0: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80053f2: 687b ldr r3, [r7, #4] 80053f4: 681b ldr r3, [r3, #0] 80053f6: 68ba ldr r2, [r7, #8] 80053f8: 609a str r2, [r3, #8] break; 80053fa: e04f b.n 800549c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80053fc: 687b ldr r3, [r7, #4] 80053fe: 6818 ldr r0, [r3, #0] 8005400: 683b ldr r3, [r7, #0] 8005402: 6899 ldr r1, [r3, #8] 8005404: 683b ldr r3, [r7, #0] 8005406: 685a ldr r2, [r3, #4] 8005408: 683b ldr r3, [r7, #0] 800540a: 68db ldr r3, [r3, #12] 800540c: f000 f9a8 bl 8005760 sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8005410: 687b ldr r3, [r7, #4] 8005412: 681b ldr r3, [r3, #0] 8005414: 689a ldr r2, [r3, #8] 8005416: 687b ldr r3, [r7, #4] 8005418: 681b ldr r3, [r3, #0] 800541a: f442 4280 orr.w r2, r2, #16384 ; 0x4000 800541e: 609a str r2, [r3, #8] break; 8005420: e03c b.n 800549c /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8005422: 687b ldr r3, [r7, #4] 8005424: 6818 ldr r0, [r3, #0] 8005426: 683b ldr r3, [r7, #0] 8005428: 6859 ldr r1, [r3, #4] 800542a: 683b ldr r3, [r7, #0] 800542c: 68db ldr r3, [r3, #12] 800542e: 461a mov r2, r3 8005430: f000 f918 bl 8005664 sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8005434: 687b ldr r3, [r7, #4] 8005436: 681b ldr r3, [r3, #0] 8005438: 2150 movs r1, #80 ; 0x50 800543a: 4618 mov r0, r3 800543c: f000 f972 bl 8005724 break; 8005440: e02c b.n 800549c /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 8005442: 687b ldr r3, [r7, #4] 8005444: 6818 ldr r0, [r3, #0] 8005446: 683b ldr r3, [r7, #0] 8005448: 6859 ldr r1, [r3, #4] 800544a: 683b ldr r3, [r7, #0] 800544c: 68db ldr r3, [r3, #12] 800544e: 461a mov r2, r3 8005450: f000 f937 bl 80056c2 sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8005454: 687b ldr r3, [r7, #4] 8005456: 681b ldr r3, [r3, #0] 8005458: 2160 movs r1, #96 ; 0x60 800545a: 4618 mov r0, r3 800545c: f000 f962 bl 8005724 break; 8005460: e01c b.n 800549c /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8005462: 687b ldr r3, [r7, #4] 8005464: 6818 ldr r0, [r3, #0] 8005466: 683b ldr r3, [r7, #0] 8005468: 6859 ldr r1, [r3, #4] 800546a: 683b ldr r3, [r7, #0] 800546c: 68db ldr r3, [r3, #12] 800546e: 461a mov r2, r3 8005470: f000 f8f8 bl 8005664 sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8005474: 687b ldr r3, [r7, #4] 8005476: 681b ldr r3, [r3, #0] 8005478: 2140 movs r1, #64 ; 0x40 800547a: 4618 mov r0, r3 800547c: f000 f952 bl 8005724 break; 8005480: e00c b.n 800549c case TIM_CLOCKSOURCE_ITR8: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 8005482: 687b ldr r3, [r7, #4] 8005484: 681a ldr r2, [r3, #0] 8005486: 683b ldr r3, [r7, #0] 8005488: 681b ldr r3, [r3, #0] 800548a: 4619 mov r1, r3 800548c: 4610 mov r0, r2 800548e: f000 f949 bl 8005724 break; 8005492: e003 b.n 800549c } default: status = HAL_ERROR; 8005494: 2301 movs r3, #1 8005496: 73fb strb r3, [r7, #15] break; 8005498: e000 b.n 800549c break; 800549a: bf00 nop } htim->State = HAL_TIM_STATE_READY; 800549c: 687b ldr r3, [r7, #4] 800549e: 2201 movs r2, #1 80054a0: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 80054a4: 687b ldr r3, [r7, #4] 80054a6: 2200 movs r2, #0 80054a8: f883 203c strb.w r2, [r3, #60] ; 0x3c return status; 80054ac: 7bfb ldrb r3, [r7, #15] } 80054ae: 4618 mov r0, r3 80054b0: 3710 adds r7, #16 80054b2: 46bd mov sp, r7 80054b4: bd80 pop {r7, pc} 80054b6: bf00 nop 80054b8: ffceff88 .word 0xffceff88 80054bc: 00100040 .word 0x00100040 80054c0: 00100030 .word 0x00100030 80054c4: 00100020 .word 0x00100020 080054c8 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80054c8: b480 push {r7} 80054ca: b083 sub sp, #12 80054cc: af00 add r7, sp, #0 80054ce: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80054d0: bf00 nop 80054d2: 370c adds r7, #12 80054d4: 46bd mov sp, r7 80054d6: f85d 7b04 ldr.w r7, [sp], #4 80054da: 4770 bx lr 080054dc : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80054dc: b480 push {r7} 80054de: b083 sub sp, #12 80054e0: af00 add r7, sp, #0 80054e2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 80054e4: bf00 nop 80054e6: 370c adds r7, #12 80054e8: 46bd mov sp, r7 80054ea: f85d 7b04 ldr.w r7, [sp], #4 80054ee: 4770 bx lr 080054f0 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80054f0: b480 push {r7} 80054f2: b083 sub sp, #12 80054f4: af00 add r7, sp, #0 80054f6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 80054f8: bf00 nop 80054fa: 370c adds r7, #12 80054fc: 46bd mov sp, r7 80054fe: f85d 7b04 ldr.w r7, [sp], #4 8005502: 4770 bx lr 08005504 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8005504: b480 push {r7} 8005506: b083 sub sp, #12 8005508: af00 add r7, sp, #0 800550a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 800550c: bf00 nop 800550e: 370c adds r7, #12 8005510: 46bd mov sp, r7 8005512: f85d 7b04 ldr.w r7, [sp], #4 8005516: 4770 bx lr 08005518 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 8005518: b480 push {r7} 800551a: b085 sub sp, #20 800551c: af00 add r7, sp, #0 800551e: 6078 str r0, [r7, #4] 8005520: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8005522: 687b ldr r3, [r7, #4] 8005524: 681b ldr r3, [r3, #0] 8005526: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8005528: 687b ldr r3, [r7, #4] 800552a: 4a44 ldr r2, [pc, #272] ; (800563c ) 800552c: 4293 cmp r3, r2 800552e: d013 beq.n 8005558 8005530: 687b ldr r3, [r7, #4] 8005532: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8005536: d00f beq.n 8005558 8005538: 687b ldr r3, [r7, #4] 800553a: 4a41 ldr r2, [pc, #260] ; (8005640 ) 800553c: 4293 cmp r3, r2 800553e: d00b beq.n 8005558 8005540: 687b ldr r3, [r7, #4] 8005542: 4a40 ldr r2, [pc, #256] ; (8005644 ) 8005544: 4293 cmp r3, r2 8005546: d007 beq.n 8005558 8005548: 687b ldr r3, [r7, #4] 800554a: 4a3f ldr r2, [pc, #252] ; (8005648 ) 800554c: 4293 cmp r3, r2 800554e: d003 beq.n 8005558 8005550: 687b ldr r3, [r7, #4] 8005552: 4a3e ldr r2, [pc, #248] ; (800564c ) 8005554: 4293 cmp r3, r2 8005556: d108 bne.n 800556a { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8005558: 68fb ldr r3, [r7, #12] 800555a: f023 0370 bic.w r3, r3, #112 ; 0x70 800555e: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8005560: 683b ldr r3, [r7, #0] 8005562: 685b ldr r3, [r3, #4] 8005564: 68fa ldr r2, [r7, #12] 8005566: 4313 orrs r3, r2 8005568: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800556a: 687b ldr r3, [r7, #4] 800556c: 4a33 ldr r2, [pc, #204] ; (800563c ) 800556e: 4293 cmp r3, r2 8005570: d027 beq.n 80055c2 8005572: 687b ldr r3, [r7, #4] 8005574: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8005578: d023 beq.n 80055c2 800557a: 687b ldr r3, [r7, #4] 800557c: 4a30 ldr r2, [pc, #192] ; (8005640 ) 800557e: 4293 cmp r3, r2 8005580: d01f beq.n 80055c2 8005582: 687b ldr r3, [r7, #4] 8005584: 4a2f ldr r2, [pc, #188] ; (8005644 ) 8005586: 4293 cmp r3, r2 8005588: d01b beq.n 80055c2 800558a: 687b ldr r3, [r7, #4] 800558c: 4a2e ldr r2, [pc, #184] ; (8005648 ) 800558e: 4293 cmp r3, r2 8005590: d017 beq.n 80055c2 8005592: 687b ldr r3, [r7, #4] 8005594: 4a2d ldr r2, [pc, #180] ; (800564c ) 8005596: 4293 cmp r3, r2 8005598: d013 beq.n 80055c2 800559a: 687b ldr r3, [r7, #4] 800559c: 4a2c ldr r2, [pc, #176] ; (8005650 ) 800559e: 4293 cmp r3, r2 80055a0: d00f beq.n 80055c2 80055a2: 687b ldr r3, [r7, #4] 80055a4: 4a2b ldr r2, [pc, #172] ; (8005654 ) 80055a6: 4293 cmp r3, r2 80055a8: d00b beq.n 80055c2 80055aa: 687b ldr r3, [r7, #4] 80055ac: 4a2a ldr r2, [pc, #168] ; (8005658 ) 80055ae: 4293 cmp r3, r2 80055b0: d007 beq.n 80055c2 80055b2: 687b ldr r3, [r7, #4] 80055b4: 4a29 ldr r2, [pc, #164] ; (800565c ) 80055b6: 4293 cmp r3, r2 80055b8: d003 beq.n 80055c2 80055ba: 687b ldr r3, [r7, #4] 80055bc: 4a28 ldr r2, [pc, #160] ; (8005660 ) 80055be: 4293 cmp r3, r2 80055c0: d108 bne.n 80055d4 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80055c2: 68fb ldr r3, [r7, #12] 80055c4: f423 7340 bic.w r3, r3, #768 ; 0x300 80055c8: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80055ca: 683b ldr r3, [r7, #0] 80055cc: 68db ldr r3, [r3, #12] 80055ce: 68fa ldr r2, [r7, #12] 80055d0: 4313 orrs r3, r2 80055d2: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80055d4: 68fb ldr r3, [r7, #12] 80055d6: f023 0280 bic.w r2, r3, #128 ; 0x80 80055da: 683b ldr r3, [r7, #0] 80055dc: 695b ldr r3, [r3, #20] 80055de: 4313 orrs r3, r2 80055e0: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 80055e2: 687b ldr r3, [r7, #4] 80055e4: 68fa ldr r2, [r7, #12] 80055e6: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80055e8: 683b ldr r3, [r7, #0] 80055ea: 689a ldr r2, [r3, #8] 80055ec: 687b ldr r3, [r7, #4] 80055ee: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80055f0: 683b ldr r3, [r7, #0] 80055f2: 681a ldr r2, [r3, #0] 80055f4: 687b ldr r3, [r7, #4] 80055f6: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80055f8: 687b ldr r3, [r7, #4] 80055fa: 4a10 ldr r2, [pc, #64] ; (800563c ) 80055fc: 4293 cmp r3, r2 80055fe: d00f beq.n 8005620 8005600: 687b ldr r3, [r7, #4] 8005602: 4a12 ldr r2, [pc, #72] ; (800564c ) 8005604: 4293 cmp r3, r2 8005606: d00b beq.n 8005620 8005608: 687b ldr r3, [r7, #4] 800560a: 4a11 ldr r2, [pc, #68] ; (8005650 ) 800560c: 4293 cmp r3, r2 800560e: d007 beq.n 8005620 8005610: 687b ldr r3, [r7, #4] 8005612: 4a10 ldr r2, [pc, #64] ; (8005654 ) 8005614: 4293 cmp r3, r2 8005616: d003 beq.n 8005620 8005618: 687b ldr r3, [r7, #4] 800561a: 4a0f ldr r2, [pc, #60] ; (8005658 ) 800561c: 4293 cmp r3, r2 800561e: d103 bne.n 8005628 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8005620: 683b ldr r3, [r7, #0] 8005622: 691a ldr r2, [r3, #16] 8005624: 687b ldr r3, [r7, #4] 8005626: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8005628: 687b ldr r3, [r7, #4] 800562a: 2201 movs r2, #1 800562c: 615a str r2, [r3, #20] } 800562e: bf00 nop 8005630: 3714 adds r7, #20 8005632: 46bd mov sp, r7 8005634: f85d 7b04 ldr.w r7, [sp], #4 8005638: 4770 bx lr 800563a: bf00 nop 800563c: 40010000 .word 0x40010000 8005640: 40000400 .word 0x40000400 8005644: 40000800 .word 0x40000800 8005648: 40000c00 .word 0x40000c00 800564c: 40010400 .word 0x40010400 8005650: 40014000 .word 0x40014000 8005654: 40014400 .word 0x40014400 8005658: 40014800 .word 0x40014800 800565c: 4000e000 .word 0x4000e000 8005660: 4000e400 .word 0x4000e400 08005664 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8005664: b480 push {r7} 8005666: b087 sub sp, #28 8005668: af00 add r7, sp, #0 800566a: 60f8 str r0, [r7, #12] 800566c: 60b9 str r1, [r7, #8] 800566e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8005670: 68fb ldr r3, [r7, #12] 8005672: 6a1b ldr r3, [r3, #32] 8005674: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8005676: 68fb ldr r3, [r7, #12] 8005678: 6a1b ldr r3, [r3, #32] 800567a: f023 0201 bic.w r2, r3, #1 800567e: 68fb ldr r3, [r7, #12] 8005680: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8005682: 68fb ldr r3, [r7, #12] 8005684: 699b ldr r3, [r3, #24] 8005686: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8005688: 693b ldr r3, [r7, #16] 800568a: f023 03f0 bic.w r3, r3, #240 ; 0xf0 800568e: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8005690: 687b ldr r3, [r7, #4] 8005692: 011b lsls r3, r3, #4 8005694: 693a ldr r2, [r7, #16] 8005696: 4313 orrs r3, r2 8005698: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 800569a: 697b ldr r3, [r7, #20] 800569c: f023 030a bic.w r3, r3, #10 80056a0: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 80056a2: 697a ldr r2, [r7, #20] 80056a4: 68bb ldr r3, [r7, #8] 80056a6: 4313 orrs r3, r2 80056a8: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 80056aa: 68fb ldr r3, [r7, #12] 80056ac: 693a ldr r2, [r7, #16] 80056ae: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 80056b0: 68fb ldr r3, [r7, #12] 80056b2: 697a ldr r2, [r7, #20] 80056b4: 621a str r2, [r3, #32] } 80056b6: bf00 nop 80056b8: 371c adds r7, #28 80056ba: 46bd mov sp, r7 80056bc: f85d 7b04 ldr.w r7, [sp], #4 80056c0: 4770 bx lr 080056c2 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 80056c2: b480 push {r7} 80056c4: b087 sub sp, #28 80056c6: af00 add r7, sp, #0 80056c8: 60f8 str r0, [r7, #12] 80056ca: 60b9 str r1, [r7, #8] 80056cc: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80056ce: 68fb ldr r3, [r7, #12] 80056d0: 6a1b ldr r3, [r3, #32] 80056d2: f023 0210 bic.w r2, r3, #16 80056d6: 68fb ldr r3, [r7, #12] 80056d8: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 80056da: 68fb ldr r3, [r7, #12] 80056dc: 699b ldr r3, [r3, #24] 80056de: 617b str r3, [r7, #20] tmpccer = TIMx->CCER; 80056e0: 68fb ldr r3, [r7, #12] 80056e2: 6a1b ldr r3, [r3, #32] 80056e4: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 80056e6: 697b ldr r3, [r7, #20] 80056e8: f423 4370 bic.w r3, r3, #61440 ; 0xf000 80056ec: 617b str r3, [r7, #20] tmpccmr1 |= (TIM_ICFilter << 12U); 80056ee: 687b ldr r3, [r7, #4] 80056f0: 031b lsls r3, r3, #12 80056f2: 697a ldr r2, [r7, #20] 80056f4: 4313 orrs r3, r2 80056f6: 617b str r3, [r7, #20] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 80056f8: 693b ldr r3, [r7, #16] 80056fa: f023 03a0 bic.w r3, r3, #160 ; 0xa0 80056fe: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity << 4U); 8005700: 68bb ldr r3, [r7, #8] 8005702: 011b lsls r3, r3, #4 8005704: 693a ldr r2, [r7, #16] 8005706: 4313 orrs r3, r2 8005708: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 800570a: 68fb ldr r3, [r7, #12] 800570c: 697a ldr r2, [r7, #20] 800570e: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8005710: 68fb ldr r3, [r7, #12] 8005712: 693a ldr r2, [r7, #16] 8005714: 621a str r2, [r3, #32] } 8005716: bf00 nop 8005718: 371c adds r7, #28 800571a: 46bd mov sp, r7 800571c: f85d 7b04 ldr.w r7, [sp], #4 8005720: 4770 bx lr ... 08005724 : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8005724: b480 push {r7} 8005726: b085 sub sp, #20 8005728: af00 add r7, sp, #0 800572a: 6078 str r0, [r7, #4] 800572c: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 800572e: 687b ldr r3, [r7, #4] 8005730: 689b ldr r3, [r3, #8] 8005732: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8005734: 68fa ldr r2, [r7, #12] 8005736: 4b09 ldr r3, [pc, #36] ; (800575c ) 8005738: 4013 ands r3, r2 800573a: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 800573c: 683a ldr r2, [r7, #0] 800573e: 68fb ldr r3, [r7, #12] 8005740: 4313 orrs r3, r2 8005742: f043 0307 orr.w r3, r3, #7 8005746: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8005748: 687b ldr r3, [r7, #4] 800574a: 68fa ldr r2, [r7, #12] 800574c: 609a str r2, [r3, #8] } 800574e: bf00 nop 8005750: 3714 adds r7, #20 8005752: 46bd mov sp, r7 8005754: f85d 7b04 ldr.w r7, [sp], #4 8005758: 4770 bx lr 800575a: bf00 nop 800575c: ffcfff8f .word 0xffcfff8f 08005760 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8005760: b480 push {r7} 8005762: b087 sub sp, #28 8005764: af00 add r7, sp, #0 8005766: 60f8 str r0, [r7, #12] 8005768: 60b9 str r1, [r7, #8] 800576a: 607a str r2, [r7, #4] 800576c: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 800576e: 68fb ldr r3, [r7, #12] 8005770: 689b ldr r3, [r3, #8] 8005772: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8005774: 697b ldr r3, [r7, #20] 8005776: f423 437f bic.w r3, r3, #65280 ; 0xff00 800577a: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 800577c: 683b ldr r3, [r7, #0] 800577e: 021a lsls r2, r3, #8 8005780: 687b ldr r3, [r7, #4] 8005782: 431a orrs r2, r3 8005784: 68bb ldr r3, [r7, #8] 8005786: 4313 orrs r3, r2 8005788: 697a ldr r2, [r7, #20] 800578a: 4313 orrs r3, r2 800578c: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 800578e: 68fb ldr r3, [r7, #12] 8005790: 697a ldr r2, [r7, #20] 8005792: 609a str r2, [r3, #8] } 8005794: bf00 nop 8005796: 371c adds r7, #28 8005798: 46bd mov sp, r7 800579a: f85d 7b04 ldr.w r7, [sp], #4 800579e: 4770 bx lr 080057a0 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { 80057a0: b480 push {r7} 80057a2: b085 sub sp, #20 80057a4: af00 add r7, sp, #0 80057a6: 6078 str r0, [r7, #4] 80057a8: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 80057aa: 687b ldr r3, [r7, #4] 80057ac: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 80057b0: 2b01 cmp r3, #1 80057b2: d101 bne.n 80057b8 80057b4: 2302 movs r3, #2 80057b6: e077 b.n 80058a8 80057b8: 687b ldr r3, [r7, #4] 80057ba: 2201 movs r2, #1 80057bc: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 80057c0: 687b ldr r3, [r7, #4] 80057c2: 2202 movs r2, #2 80057c4: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 80057c8: 687b ldr r3, [r7, #4] 80057ca: 681b ldr r3, [r3, #0] 80057cc: 685b ldr r3, [r3, #4] 80057ce: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80057d0: 687b ldr r3, [r7, #4] 80057d2: 681b ldr r3, [r3, #0] 80057d4: 689b ldr r3, [r3, #8] 80057d6: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 80057d8: 687b ldr r3, [r7, #4] 80057da: 681b ldr r3, [r3, #0] 80057dc: 4a35 ldr r2, [pc, #212] ; (80058b4 ) 80057de: 4293 cmp r3, r2 80057e0: d004 beq.n 80057ec 80057e2: 687b ldr r3, [r7, #4] 80057e4: 681b ldr r3, [r3, #0] 80057e6: 4a34 ldr r2, [pc, #208] ; (80058b8 ) 80057e8: 4293 cmp r3, r2 80057ea: d108 bne.n 80057fe { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 80057ec: 68fb ldr r3, [r7, #12] 80057ee: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 80057f2: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 80057f4: 683b ldr r3, [r7, #0] 80057f6: 685b ldr r3, [r3, #4] 80057f8: 68fa ldr r2, [r7, #12] 80057fa: 4313 orrs r3, r2 80057fc: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80057fe: 68fb ldr r3, [r7, #12] 8005800: f023 0370 bic.w r3, r3, #112 ; 0x70 8005804: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8005806: 683b ldr r3, [r7, #0] 8005808: 681b ldr r3, [r3, #0] 800580a: 68fa ldr r2, [r7, #12] 800580c: 4313 orrs r3, r2 800580e: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8005810: 687b ldr r3, [r7, #4] 8005812: 681b ldr r3, [r3, #0] 8005814: 68fa ldr r2, [r7, #12] 8005816: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005818: 687b ldr r3, [r7, #4] 800581a: 681b ldr r3, [r3, #0] 800581c: 4a25 ldr r2, [pc, #148] ; (80058b4 ) 800581e: 4293 cmp r3, r2 8005820: d02c beq.n 800587c 8005822: 687b ldr r3, [r7, #4] 8005824: 681b ldr r3, [r3, #0] 8005826: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800582a: d027 beq.n 800587c 800582c: 687b ldr r3, [r7, #4] 800582e: 681b ldr r3, [r3, #0] 8005830: 4a22 ldr r2, [pc, #136] ; (80058bc ) 8005832: 4293 cmp r3, r2 8005834: d022 beq.n 800587c 8005836: 687b ldr r3, [r7, #4] 8005838: 681b ldr r3, [r3, #0] 800583a: 4a21 ldr r2, [pc, #132] ; (80058c0 ) 800583c: 4293 cmp r3, r2 800583e: d01d beq.n 800587c 8005840: 687b ldr r3, [r7, #4] 8005842: 681b ldr r3, [r3, #0] 8005844: 4a1f ldr r2, [pc, #124] ; (80058c4 ) 8005846: 4293 cmp r3, r2 8005848: d018 beq.n 800587c 800584a: 687b ldr r3, [r7, #4] 800584c: 681b ldr r3, [r3, #0] 800584e: 4a1a ldr r2, [pc, #104] ; (80058b8 ) 8005850: 4293 cmp r3, r2 8005852: d013 beq.n 800587c 8005854: 687b ldr r3, [r7, #4] 8005856: 681b ldr r3, [r3, #0] 8005858: 4a1b ldr r2, [pc, #108] ; (80058c8 ) 800585a: 4293 cmp r3, r2 800585c: d00e beq.n 800587c 800585e: 687b ldr r3, [r7, #4] 8005860: 681b ldr r3, [r3, #0] 8005862: 4a1a ldr r2, [pc, #104] ; (80058cc ) 8005864: 4293 cmp r3, r2 8005866: d009 beq.n 800587c 8005868: 687b ldr r3, [r7, #4] 800586a: 681b ldr r3, [r3, #0] 800586c: 4a18 ldr r2, [pc, #96] ; (80058d0 ) 800586e: 4293 cmp r3, r2 8005870: d004 beq.n 800587c 8005872: 687b ldr r3, [r7, #4] 8005874: 681b ldr r3, [r3, #0] 8005876: 4a17 ldr r2, [pc, #92] ; (80058d4 ) 8005878: 4293 cmp r3, r2 800587a: d10c bne.n 8005896 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 800587c: 68bb ldr r3, [r7, #8] 800587e: f023 0380 bic.w r3, r3, #128 ; 0x80 8005882: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8005884: 683b ldr r3, [r7, #0] 8005886: 689b ldr r3, [r3, #8] 8005888: 68ba ldr r2, [r7, #8] 800588a: 4313 orrs r3, r2 800588c: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800588e: 687b ldr r3, [r7, #4] 8005890: 681b ldr r3, [r3, #0] 8005892: 68ba ldr r2, [r7, #8] 8005894: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8005896: 687b ldr r3, [r7, #4] 8005898: 2201 movs r2, #1 800589a: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 800589e: 687b ldr r3, [r7, #4] 80058a0: 2200 movs r2, #0 80058a2: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 80058a6: 2300 movs r3, #0 } 80058a8: 4618 mov r0, r3 80058aa: 3714 adds r7, #20 80058ac: 46bd mov sp, r7 80058ae: f85d 7b04 ldr.w r7, [sp], #4 80058b2: 4770 bx lr 80058b4: 40010000 .word 0x40010000 80058b8: 40010400 .word 0x40010400 80058bc: 40000400 .word 0x40000400 80058c0: 40000800 .word 0x40000800 80058c4: 40000c00 .word 0x40000c00 80058c8: 40001800 .word 0x40001800 80058cc: 40014000 .word 0x40014000 80058d0: 4000e000 .word 0x4000e000 80058d4: 4000e400 .word 0x4000e400 080058d8 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 80058d8: b480 push {r7} 80058da: b083 sub sp, #12 80058dc: af00 add r7, sp, #0 80058de: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 80058e0: bf00 nop 80058e2: 370c adds r7, #12 80058e4: 46bd mov sp, r7 80058e6: f85d 7b04 ldr.w r7, [sp], #4 80058ea: 4770 bx lr 080058ec : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 80058ec: b480 push {r7} 80058ee: b083 sub sp, #12 80058f0: af00 add r7, sp, #0 80058f2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 80058f4: bf00 nop 80058f6: 370c adds r7, #12 80058f8: 46bd mov sp, r7 80058fa: f85d 7b04 ldr.w r7, [sp], #4 80058fe: 4770 bx lr 08005900 : * @brief Hall Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 8005900: b480 push {r7} 8005902: b083 sub sp, #12 8005904: af00 add r7, sp, #0 8005906: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8005908: bf00 nop 800590a: 370c adds r7, #12 800590c: 46bd mov sp, r7 800590e: f85d 7b04 ldr.w r7, [sp], #4 8005912: 4770 bx lr 08005914 : * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { 8005914: b480 push {r7} 8005916: b085 sub sp, #20 8005918: af00 add r7, sp, #0 800591a: 60f8 str r0, [r7, #12] 800591c: 60b9 str r1, [r7, #8] 800591e: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); 8005920: 68fb ldr r3, [r7, #12] 8005922: 6819 ldr r1, [r3, #0] 8005924: 68bb ldr r3, [r7, #8] 8005926: fb03 f203 mul.w r2, r3, r3 800592a: 4613 mov r3, r2 800592c: 005b lsls r3, r3, #1 800592e: 4413 add r3, r2 8005930: 43db mvns r3, r3 8005932: ea01 0203 and.w r2, r1, r3 8005936: 68bb ldr r3, [r7, #8] 8005938: fb03 f303 mul.w r3, r3, r3 800593c: 6879 ldr r1, [r7, #4] 800593e: fb01 f303 mul.w r3, r1, r3 8005942: 431a orrs r2, r3 8005944: 68fb ldr r3, [r7, #12] 8005946: 601a str r2, [r3, #0] } 8005948: bf00 nop 800594a: 3714 adds r7, #20 800594c: 46bd mov sp, r7 800594e: f85d 7b04 ldr.w r7, [sp], #4 8005952: 4770 bx lr 08005954 : * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) { 8005954: b480 push {r7} 8005956: b085 sub sp, #20 8005958: af00 add r7, sp, #0 800595a: 60f8 str r0, [r7, #12] 800595c: 60b9 str r1, [r7, #8] 800595e: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); 8005960: 68fb ldr r3, [r7, #12] 8005962: 685a ldr r2, [r3, #4] 8005964: 68bb ldr r3, [r7, #8] 8005966: 43db mvns r3, r3 8005968: 401a ands r2, r3 800596a: 68bb ldr r3, [r7, #8] 800596c: 6879 ldr r1, [r7, #4] 800596e: fb01 f303 mul.w r3, r1, r3 8005972: 431a orrs r2, r3 8005974: 68fb ldr r3, [r7, #12] 8005976: 605a str r2, [r3, #4] } 8005978: bf00 nop 800597a: 3714 adds r7, #20 800597c: 46bd mov sp, r7 800597e: f85d 7b04 ldr.w r7, [sp], #4 8005982: 4770 bx lr 08005984 : * @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) { 8005984: b480 push {r7} 8005986: b085 sub sp, #20 8005988: af00 add r7, sp, #0 800598a: 60f8 str r0, [r7, #12] 800598c: 60b9 str r1, [r7, #8] 800598e: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed)); 8005990: 68fb ldr r3, [r7, #12] 8005992: 6899 ldr r1, [r3, #8] 8005994: 68bb ldr r3, [r7, #8] 8005996: fb03 f203 mul.w r2, r3, r3 800599a: 4613 mov r3, r2 800599c: 005b lsls r3, r3, #1 800599e: 4413 add r3, r2 80059a0: 43db mvns r3, r3 80059a2: ea01 0203 and.w r2, r1, r3 80059a6: 68bb ldr r3, [r7, #8] 80059a8: fb03 f303 mul.w r3, r3, r3 80059ac: 6879 ldr r1, [r7, #4] 80059ae: fb01 f303 mul.w r3, r1, r3 80059b2: 431a orrs r2, r3 80059b4: 68fb ldr r3, [r7, #12] 80059b6: 609a str r2, [r3, #8] } 80059b8: bf00 nop 80059ba: 3714 adds r7, #20 80059bc: 46bd mov sp, r7 80059be: f85d 7b04 ldr.w r7, [sp], #4 80059c2: 4770 bx lr 080059c4 : * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) { 80059c4: b480 push {r7} 80059c6: b085 sub sp, #20 80059c8: af00 add r7, sp, #0 80059ca: 60f8 str r0, [r7, #12] 80059cc: 60b9 str r1, [r7, #8] 80059ce: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); 80059d0: 68fb ldr r3, [r7, #12] 80059d2: 68d9 ldr r1, [r3, #12] 80059d4: 68bb ldr r3, [r7, #8] 80059d6: fb03 f203 mul.w r2, r3, r3 80059da: 4613 mov r3, r2 80059dc: 005b lsls r3, r3, #1 80059de: 4413 add r3, r2 80059e0: 43db mvns r3, r3 80059e2: ea01 0203 and.w r2, r1, r3 80059e6: 68bb ldr r3, [r7, #8] 80059e8: fb03 f303 mul.w r3, r3, r3 80059ec: 6879 ldr r1, [r7, #4] 80059ee: fb01 f303 mul.w r3, r1, r3 80059f2: 431a orrs r2, r3 80059f4: 68fb ldr r3, [r7, #12] 80059f6: 60da str r2, [r3, #12] } 80059f8: bf00 nop 80059fa: 3714 adds r7, #20 80059fc: 46bd mov sp, r7 80059fe: f85d 7b04 ldr.w r7, [sp], #4 8005a02: 4770 bx lr 08005a04 : * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 * @retval None */ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { 8005a04: b480 push {r7} 8005a06: b085 sub sp, #20 8005a08: af00 add r7, sp, #0 8005a0a: 60f8 str r0, [r7, #12] 8005a0c: 60b9 str r1, [r7, #8] 8005a0e: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), 8005a10: 68fb ldr r3, [r7, #12] 8005a12: 6a19 ldr r1, [r3, #32] 8005a14: 68bb ldr r3, [r7, #8] 8005a16: fb03 f303 mul.w r3, r3, r3 8005a1a: 68ba ldr r2, [r7, #8] 8005a1c: fb02 f303 mul.w r3, r2, r3 8005a20: 68ba ldr r2, [r7, #8] 8005a22: fb02 f203 mul.w r2, r2, r3 8005a26: 4613 mov r3, r2 8005a28: 011b lsls r3, r3, #4 8005a2a: 1a9b subs r3, r3, r2 8005a2c: 43db mvns r3, r3 8005a2e: ea01 0203 and.w r2, r1, r3 8005a32: 68bb ldr r3, [r7, #8] 8005a34: fb03 f303 mul.w r3, r3, r3 8005a38: 68b9 ldr r1, [r7, #8] 8005a3a: fb01 f303 mul.w r3, r1, r3 8005a3e: 68b9 ldr r1, [r7, #8] 8005a40: fb01 f303 mul.w r3, r1, r3 8005a44: 6879 ldr r1, [r7, #4] 8005a46: fb01 f303 mul.w r3, r1, r3 8005a4a: 431a orrs r2, r3 8005a4c: 68fb ldr r3, [r7, #12] 8005a4e: 621a str r2, [r3, #32] ((((Pin * Pin) * Pin) * Pin) * Alternate)); } 8005a50: bf00 nop 8005a52: 3714 adds r7, #20 8005a54: 46bd mov sp, r7 8005a56: f85d 7b04 ldr.w r7, [sp], #4 8005a5a: 4770 bx lr 08005a5c : * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 * @retval None */ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { 8005a5c: b480 push {r7} 8005a5e: b085 sub sp, #20 8005a60: af00 add r7, sp, #0 8005a62: 60f8 str r0, [r7, #12] 8005a64: 60b9 str r1, [r7, #8] 8005a66: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), 8005a68: 68fb ldr r3, [r7, #12] 8005a6a: 6a59 ldr r1, [r3, #36] ; 0x24 8005a6c: 68bb ldr r3, [r7, #8] 8005a6e: 0a1b lsrs r3, r3, #8 8005a70: 68ba ldr r2, [r7, #8] 8005a72: 0a12 lsrs r2, r2, #8 8005a74: fb02 f303 mul.w r3, r2, r3 8005a78: 68ba ldr r2, [r7, #8] 8005a7a: 0a12 lsrs r2, r2, #8 8005a7c: fb02 f303 mul.w r3, r2, r3 8005a80: 68ba ldr r2, [r7, #8] 8005a82: 0a12 lsrs r2, r2, #8 8005a84: fb02 f203 mul.w r2, r2, r3 8005a88: 4613 mov r3, r2 8005a8a: 011b lsls r3, r3, #4 8005a8c: 1a9b subs r3, r3, r2 8005a8e: 43db mvns r3, r3 8005a90: ea01 0203 and.w r2, r1, r3 8005a94: 68bb ldr r3, [r7, #8] 8005a96: 0a1b lsrs r3, r3, #8 8005a98: 68b9 ldr r1, [r7, #8] 8005a9a: 0a09 lsrs r1, r1, #8 8005a9c: fb01 f303 mul.w r3, r1, r3 8005aa0: 68b9 ldr r1, [r7, #8] 8005aa2: 0a09 lsrs r1, r1, #8 8005aa4: fb01 f303 mul.w r3, r1, r3 8005aa8: 68b9 ldr r1, [r7, #8] 8005aaa: 0a09 lsrs r1, r1, #8 8005aac: fb01 f303 mul.w r3, r1, r3 8005ab0: 6879 ldr r1, [r7, #4] 8005ab2: fb01 f303 mul.w r3, r1, r3 8005ab6: 431a orrs r2, r3 8005ab8: 68fb ldr r3, [r7, #12] 8005aba: 625a str r2, [r3, #36] ; 0x24 (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); } 8005abc: bf00 nop 8005abe: 3714 adds r7, #20 8005ac0: 46bd mov sp, r7 8005ac2: f85d 7b04 ldr.w r7, [sp], #4 8005ac6: 4770 bx lr 08005ac8 : * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content * - ERROR: Not applicable */ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) { 8005ac8: b580 push {r7, lr} 8005aca: b088 sub sp, #32 8005acc: af00 add r7, sp, #0 8005ace: 6078 str r0, [r7, #4] 8005ad0: 6039 str r1, [r7, #0] assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); /* ------------------------- Configure the port pins ---------------- */ /* Initialize pinpos on first pin set */ pinpos = POSITION_VAL(GPIO_InitStruct->Pin); 8005ad2: 683b ldr r3, [r7, #0] 8005ad4: 681b ldr r3, [r3, #0] 8005ad6: 613b str r3, [r7, #16] uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005ad8: 693b ldr r3, [r7, #16] 8005ada: fa93 f3a3 rbit r3, r3 8005ade: 60fb str r3, [r7, #12] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8005ae0: 68fb ldr r3, [r7, #12] 8005ae2: 617b str r3, [r7, #20] optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 8005ae4: 697b ldr r3, [r7, #20] 8005ae6: 2b00 cmp r3, #0 8005ae8: d101 bne.n 8005aee { return 32U; 8005aea: 2320 movs r3, #32 8005aec: e003 b.n 8005af6 } return __builtin_clz(value); 8005aee: 697b ldr r3, [r7, #20] 8005af0: fab3 f383 clz r3, r3 8005af4: b2db uxtb r3, r3 8005af6: 61fb str r3, [r7, #28] /* Configure the port pins */ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) 8005af8: e048 b.n 8005b8c { /* Get current io position */ currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos); 8005afa: 683b ldr r3, [r7, #0] 8005afc: 681a ldr r2, [r3, #0] 8005afe: 2101 movs r1, #1 8005b00: 69fb ldr r3, [r7, #28] 8005b02: fa01 f303 lsl.w r3, r1, r3 8005b06: 4013 ands r3, r2 8005b08: 61bb str r3, [r7, #24] if (currentpin != 0x00000000U) 8005b0a: 69bb ldr r3, [r7, #24] 8005b0c: 2b00 cmp r3, #0 8005b0e: d03a beq.n 8005b86 { if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) 8005b10: 683b ldr r3, [r7, #0] 8005b12: 685b ldr r3, [r3, #4] 8005b14: 2b01 cmp r3, #1 8005b16: d003 beq.n 8005b20 8005b18: 683b ldr r3, [r7, #0] 8005b1a: 685b ldr r3, [r3, #4] 8005b1c: 2b02 cmp r3, #2 8005b1e: d10e bne.n 8005b3e { /* Check Speed mode parameters */ assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); /* Speed mode configuration */ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); 8005b20: 683b ldr r3, [r7, #0] 8005b22: 689b ldr r3, [r3, #8] 8005b24: 461a mov r2, r3 8005b26: 69b9 ldr r1, [r7, #24] 8005b28: 6878 ldr r0, [r7, #4] 8005b2a: f7ff ff2b bl 8005984 /* Check Output mode parameters */ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); /* Output mode configuration*/ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); 8005b2e: 683b ldr r3, [r7, #0] 8005b30: 6819 ldr r1, [r3, #0] 8005b32: 683b ldr r3, [r7, #0] 8005b34: 68db ldr r3, [r3, #12] 8005b36: 461a mov r2, r3 8005b38: 6878 ldr r0, [r7, #4] 8005b3a: f7ff ff0b bl 8005954 } /* Pull-up Pull down resistor configuration*/ LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); 8005b3e: 683b ldr r3, [r7, #0] 8005b40: 691b ldr r3, [r3, #16] 8005b42: 461a mov r2, r3 8005b44: 69b9 ldr r1, [r7, #24] 8005b46: 6878 ldr r0, [r7, #4] 8005b48: f7ff ff3c bl 80059c4 if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) 8005b4c: 683b ldr r3, [r7, #0] 8005b4e: 685b ldr r3, [r3, #4] 8005b50: 2b02 cmp r3, #2 8005b52: d111 bne.n 8005b78 { /* Check Alternate parameter */ assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); /* Alternate function configuration */ if (currentpin < LL_GPIO_PIN_8) 8005b54: 69bb ldr r3, [r7, #24] 8005b56: 2bff cmp r3, #255 ; 0xff 8005b58: d807 bhi.n 8005b6a { LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); 8005b5a: 683b ldr r3, [r7, #0] 8005b5c: 695b ldr r3, [r3, #20] 8005b5e: 461a mov r2, r3 8005b60: 69b9 ldr r1, [r7, #24] 8005b62: 6878 ldr r0, [r7, #4] 8005b64: f7ff ff4e bl 8005a04 8005b68: e006 b.n 8005b78 } else { LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); 8005b6a: 683b ldr r3, [r7, #0] 8005b6c: 695b ldr r3, [r3, #20] 8005b6e: 461a mov r2, r3 8005b70: 69b9 ldr r1, [r7, #24] 8005b72: 6878 ldr r0, [r7, #4] 8005b74: f7ff ff72 bl 8005a5c } } /* Pin Mode configuration */ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); 8005b78: 683b ldr r3, [r7, #0] 8005b7a: 685b ldr r3, [r3, #4] 8005b7c: 461a mov r2, r3 8005b7e: 69b9 ldr r1, [r7, #24] 8005b80: 6878 ldr r0, [r7, #4] 8005b82: f7ff fec7 bl 8005914 } pinpos++; 8005b86: 69fb ldr r3, [r7, #28] 8005b88: 3301 adds r3, #1 8005b8a: 61fb str r3, [r7, #28] while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) 8005b8c: 683b ldr r3, [r7, #0] 8005b8e: 681a ldr r2, [r3, #0] 8005b90: 69fb ldr r3, [r7, #28] 8005b92: fa22 f303 lsr.w r3, r2, r3 8005b96: 2b00 cmp r3, #0 8005b98: d1af bne.n 8005afa } return (SUCCESS); 8005b9a: 2300 movs r3, #0 } 8005b9c: 4618 mov r0, r3 8005b9e: 3720 adds r7, #32 8005ba0: 46bd mov sp, r7 8005ba2: bd80 pop {r7, pc} 08005ba4 : { 8005ba4: b480 push {r7} 8005ba6: b083 sub sp, #12 8005ba8: af00 add r7, sp, #0 8005baa: 6078 str r0, [r7, #4] return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); 8005bac: 687b ldr r3, [r7, #4] 8005bae: 681b ldr r3, [r3, #0] 8005bb0: f003 0301 and.w r3, r3, #1 8005bb4: 2b01 cmp r3, #1 8005bb6: d101 bne.n 8005bbc 8005bb8: 2301 movs r3, #1 8005bba: e000 b.n 8005bbe 8005bbc: 2300 movs r3, #0 } 8005bbe: 4618 mov r0, r3 8005bc0: 370c adds r7, #12 8005bc2: 46bd mov sp, r7 8005bc4: f85d 7b04 ldr.w r7, [sp], #4 8005bc8: 4770 bx lr 08005bca : { 8005bca: b480 push {r7} 8005bcc: b083 sub sp, #12 8005bce: af00 add r7, sp, #0 8005bd0: 6078 str r0, [r7, #4] 8005bd2: 6039 str r1, [r7, #0] MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel); 8005bd4: 687b ldr r3, [r7, #4] 8005bd6: 681b ldr r3, [r3, #0] 8005bd8: f423 5280 bic.w r2, r3, #4096 ; 0x1000 8005bdc: 683b ldr r3, [r7, #0] 8005bde: 431a orrs r2, r3 8005be0: 687b ldr r3, [r7, #4] 8005be2: 601a str r2, [r3, #0] } 8005be4: bf00 nop 8005be6: 370c adds r7, #12 8005be8: 46bd mov sp, r7 8005bea: f85d 7b04 ldr.w r7, [sp], #4 8005bee: 4770 bx lr 08005bf0 : { 8005bf0: b480 push {r7} 8005bf2: b083 sub sp, #12 8005bf4: af00 add r7, sp, #0 8005bf6: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP)); 8005bf8: 687b ldr r3, [r7, #4] 8005bfa: 68db ldr r3, [r3, #12] 8005bfc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 } 8005c00: 4618 mov r0, r3 8005c02: 370c adds r7, #12 8005c04: 46bd mov sp, r7 8005c06: f85d 7b04 ldr.w r7, [sp], #4 8005c0a: 4770 bx lr 08005c0c : * @param SPIx SPI Instance * @param CRCPoly 0..0xFFFFFFFF * @retval None */ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) { 8005c0c: b480 push {r7} 8005c0e: b083 sub sp, #12 8005c10: af00 add r7, sp, #0 8005c12: 6078 str r0, [r7, #4] 8005c14: 6039 str r1, [r7, #0] WRITE_REG(SPIx->CRCPOLY, CRCPoly); 8005c16: 687b ldr r3, [r7, #4] 8005c18: 683a ldr r2, [r7, #0] 8005c1a: 641a str r2, [r3, #64] ; 0x40 } 8005c1c: bf00 nop 8005c1e: 370c adds r7, #12 8005c20: 46bd mov sp, r7 8005c22: f85d 7b04 ldr.w r7, [sp], #4 8005c26: 4770 bx lr 08005c28 : * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) */ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) { 8005c28: b580 push {r7, lr} 8005c2a: b086 sub sp, #24 8005c2c: af00 add r7, sp, #0 8005c2e: 6078 str r0, [r7, #4] 8005c30: 6039 str r1, [r7, #0] ErrorStatus status = ERROR; 8005c32: 2301 movs r3, #1 8005c34: 75fb strb r3, [r7, #23] assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate)); assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); /* Check the SPI instance is not enabled */ if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL) 8005c36: 6878 ldr r0, [r7, #4] 8005c38: f7ff ffb4 bl 8005ba4 8005c3c: 4603 mov r3, r0 8005c3e: 2b00 cmp r3, #0 8005c40: d169 bne.n 8005d16 * Configure SPIx CFG1 with parameters: * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits * - CRC Computation Enable : SPI_CFG1_CRCEN bit * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits */ MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE, 8005c42: 687b ldr r3, [r7, #4] 8005c44: 689a ldr r2, [r3, #8] 8005c46: 4b36 ldr r3, [pc, #216] ; (8005d20 ) 8005c48: 4013 ands r3, r2 8005c4a: 683a ldr r2, [r7, #0] 8005c4c: 6991 ldr r1, [r2, #24] 8005c4e: 683a ldr r2, [r7, #0] 8005c50: 6a12 ldr r2, [r2, #32] 8005c52: 4311 orrs r1, r2 8005c54: 683a ldr r2, [r7, #0] 8005c56: 6892 ldr r2, [r2, #8] 8005c58: 430a orrs r2, r1 8005c5a: 431a orrs r2, r3 8005c5c: 687b ldr r3, [r7, #4] 8005c5e: 609a str r2, [r3, #8] SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth); tmp_nss = SPI_InitStruct->NSS; 8005c60: 683b ldr r3, [r7, #0] 8005c62: 695b ldr r3, [r3, #20] 8005c64: 613b str r3, [r7, #16] tmp_mode = SPI_InitStruct->Mode; 8005c66: 683b ldr r3, [r7, #0] 8005c68: 685b ldr r3, [r3, #4] 8005c6a: 60fb str r3, [r7, #12] /* Checks to setup Internal SS signal level and avoid a MODF Error */ if ((tmp_nss == LL_SPI_NSS_SOFT) && (((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && \ 8005c6c: 693b ldr r3, [r7, #16] 8005c6e: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 8005c72: d118 bne.n 8005ca6 8005c74: 6878 ldr r0, [r7, #4] 8005c76: f7ff ffbb bl 8005bf0 8005c7a: 4603 mov r3, r0 8005c7c: 2b00 cmp r3, #0 8005c7e: d103 bne.n 8005c88 8005c80: 68fb ldr r3, [r7, #12] 8005c82: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8005c86: d009 beq.n 8005c9c (tmp_mode == LL_SPI_MODE_MASTER)) || \ ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && \ 8005c88: 6878 ldr r0, [r7, #4] 8005c8a: f7ff ffb1 bl 8005bf0 8005c8e: 4603 mov r3, r0 (tmp_mode == LL_SPI_MODE_MASTER)) || \ 8005c90: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8005c94: d107 bne.n 8005ca6 ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && \ 8005c96: 68fb ldr r3, [r7, #12] 8005c98: 2b00 cmp r3, #0 8005c9a: d104 bne.n 8005ca6 (tmp_mode == LL_SPI_MODE_SLAVE)))) { LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); 8005c9c: f44f 5180 mov.w r1, #4096 ; 0x1000 8005ca0: 6878 ldr r0, [r7, #4] 8005ca2: f7ff ff92 bl 8005bca * - ClockPhase : SPI_CFG2_CPHA bit * - BitOrder : SPI_CFG2_LSBFRST bit * - Master/Slave Mode : SPI_CFG2_MASTER bit * - SPI Mode : SPI_CFG2_COMM[1:0] bits */ MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE | 8005ca6: 687b ldr r3, [r7, #4] 8005ca8: 68da ldr r2, [r3, #12] 8005caa: 4b1e ldr r3, [pc, #120] ; (8005d24 ) 8005cac: 4013 ands r3, r2 8005cae: 683a ldr r2, [r7, #0] 8005cb0: 6951 ldr r1, [r2, #20] 8005cb2: 683a ldr r2, [r7, #0] 8005cb4: 68d2 ldr r2, [r2, #12] 8005cb6: 4311 orrs r1, r2 8005cb8: 683a ldr r2, [r7, #0] 8005cba: 6912 ldr r2, [r2, #16] 8005cbc: 4311 orrs r1, r2 8005cbe: 683a ldr r2, [r7, #0] 8005cc0: 69d2 ldr r2, [r2, #28] 8005cc2: 4311 orrs r1, r2 8005cc4: 683a ldr r2, [r7, #0] 8005cc6: 6852 ldr r2, [r2, #4] 8005cc8: 4311 orrs r1, r2 8005cca: 683a ldr r2, [r7, #0] 8005ccc: 6812 ldr r2, [r2, #0] 8005cce: f402 22c0 and.w r2, r2, #393216 ; 0x60000 8005cd2: 430a orrs r2, r1 8005cd4: 431a orrs r2, r3 8005cd6: 687b ldr r3, [r7, #4] 8005cd8: 60da str r2, [r3, #12] /*---------------------------- SPIx CR1 Configuration ------------------------ * Configure SPIx CR1 with parameter: * - Half Duplex Direction : SPI_CR1_HDDIR bit */ MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR); 8005cda: 687b ldr r3, [r7, #4] 8005cdc: 681b ldr r3, [r3, #0] 8005cde: f423 6200 bic.w r2, r3, #2048 ; 0x800 8005ce2: 683b ldr r3, [r7, #0] 8005ce4: 681b ldr r3, [r3, #0] 8005ce6: f403 6300 and.w r3, r3, #2048 ; 0x800 8005cea: 431a orrs r2, r3 8005cec: 687b ldr r3, [r7, #4] 8005cee: 601a str r2, [r3, #0] /*---------------------------- SPIx CRCPOLY Configuration ---------------------- * Configure SPIx CRCPOLY with parameter: * - CRCPoly : CRCPOLY[31:0] bits */ if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) 8005cf0: 683b ldr r3, [r7, #0] 8005cf2: 6a1b ldr r3, [r3, #32] 8005cf4: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8005cf8: d105 bne.n 8005d06 { assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); 8005cfa: 683b ldr r3, [r7, #0] 8005cfc: 6a5b ldr r3, [r3, #36] ; 0x24 8005cfe: 4619 mov r1, r3 8005d00: 6878 ldr r0, [r7, #4] 8005d02: f7ff ff83 bl 8005c0c } /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); 8005d06: 687b ldr r3, [r7, #4] 8005d08: 6d1b ldr r3, [r3, #80] ; 0x50 8005d0a: f023 0201 bic.w r2, r3, #1 8005d0e: 687b ldr r3, [r7, #4] 8005d10: 651a str r2, [r3, #80] ; 0x50 status = SUCCESS; 8005d12: 2300 movs r3, #0 8005d14: 75fb strb r3, [r7, #23] } return status; 8005d16: 7dfb ldrb r3, [r7, #23] } 8005d18: 4618 mov r0, r3 8005d1a: 3718 adds r7, #24 8005d1c: 46bd mov sp, r7 8005d1e: bd80 pop {r7, pc} 8005d20: 8fbfffe0 .word 0x8fbfffe0 8005d24: d839ffff .word 0xd839ffff 08005d28 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8005d28: b084 sub sp, #16 8005d2a: b580 push {r7, lr} 8005d2c: b084 sub sp, #16 8005d2e: af00 add r7, sp, #0 8005d30: 6078 str r0, [r7, #4] 8005d32: f107 001c add.w r0, r7, #28 8005d36: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8005d3a: 6b3b ldr r3, [r7, #48] ; 0x30 8005d3c: 2b01 cmp r3, #1 8005d3e: d120 bne.n 8005d82 { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8005d40: 687b ldr r3, [r7, #4] 8005d42: 6b9b ldr r3, [r3, #56] ; 0x38 8005d44: f423 3280 bic.w r2, r3, #65536 ; 0x10000 8005d48: 687b ldr r3, [r7, #4] 8005d4a: 639a str r2, [r3, #56] ; 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 8005d4c: 687b ldr r3, [r7, #4] 8005d4e: 68da ldr r2, [r3, #12] 8005d50: 4b2a ldr r3, [pc, #168] ; (8005dfc ) 8005d52: 4013 ands r3, r2 8005d54: 687a ldr r2, [r7, #4] 8005d56: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 8005d58: 687b ldr r3, [r7, #4] 8005d5a: 68db ldr r3, [r3, #12] 8005d5c: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8005d60: 687b ldr r3, [r7, #4] 8005d62: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 8005d64: 6cfb ldr r3, [r7, #76] ; 0x4c 8005d66: 2b01 cmp r3, #1 8005d68: d105 bne.n 8005d76 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 8005d6a: 687b ldr r3, [r7, #4] 8005d6c: 68db ldr r3, [r3, #12] 8005d6e: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8005d72: 687b ldr r3, [r7, #4] 8005d74: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8005d76: 6878 ldr r0, [r7, #4] 8005d78: f001 fb4e bl 8007418 8005d7c: 4603 mov r3, r0 8005d7e: 73fb strb r3, [r7, #15] 8005d80: e01a b.n 8005db8 } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 8005d82: 687b ldr r3, [r7, #4] 8005d84: 68db ldr r3, [r3, #12] 8005d86: f043 0240 orr.w r2, r3, #64 ; 0x40 8005d8a: 687b ldr r3, [r7, #4] 8005d8c: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8005d8e: 6878 ldr r0, [r7, #4] 8005d90: f001 fb42 bl 8007418 8005d94: 4603 mov r3, r0 8005d96: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 8005d98: 6c3b ldr r3, [r7, #64] ; 0x40 8005d9a: 2b00 cmp r3, #0 8005d9c: d106 bne.n 8005dac { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8005d9e: 687b ldr r3, [r7, #4] 8005da0: 6b9b ldr r3, [r3, #56] ; 0x38 8005da2: f443 3280 orr.w r2, r3, #65536 ; 0x10000 8005da6: 687b ldr r3, [r7, #4] 8005da8: 639a str r2, [r3, #56] ; 0x38 8005daa: e005 b.n 8005db8 } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8005dac: 687b ldr r3, [r7, #4] 8005dae: 6b9b ldr r3, [r3, #56] ; 0x38 8005db0: f423 3280 bic.w r2, r3, #65536 ; 0x10000 8005db4: 687b ldr r3, [r7, #4] 8005db6: 639a str r2, [r3, #56] ; 0x38 } } if (cfg.dma_enable == 1U) 8005db8: 6abb ldr r3, [r7, #40] ; 0x28 8005dba: 2b01 cmp r3, #1 8005dbc: d116 bne.n 8005dec { /* make sure to reserve 18 fifo Locations for DMA buffers */ USBx->GDFIFOCFG &= ~(0xFFFFU << 16); 8005dbe: 687b ldr r3, [r7, #4] 8005dc0: 6ddb ldr r3, [r3, #92] ; 0x5c 8005dc2: b29a uxth r2, r3 8005dc4: 687b ldr r3, [r7, #4] 8005dc6: 65da str r2, [r3, #92] ; 0x5c USBx->GDFIFOCFG |= 0x3EEU << 16; 8005dc8: 687b ldr r3, [r7, #4] 8005dca: 6dda ldr r2, [r3, #92] ; 0x5c 8005dcc: 4b0c ldr r3, [pc, #48] ; (8005e00 ) 8005dce: 4313 orrs r3, r2 8005dd0: 687a ldr r2, [r7, #4] 8005dd2: 65d3 str r3, [r2, #92] ; 0x5c USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 8005dd4: 687b ldr r3, [r7, #4] 8005dd6: 689b ldr r3, [r3, #8] 8005dd8: f043 0206 orr.w r2, r3, #6 8005ddc: 687b ldr r3, [r7, #4] 8005dde: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 8005de0: 687b ldr r3, [r7, #4] 8005de2: 689b ldr r3, [r3, #8] 8005de4: f043 0220 orr.w r2, r3, #32 8005de8: 687b ldr r3, [r7, #4] 8005dea: 609a str r2, [r3, #8] } return ret; 8005dec: 7bfb ldrb r3, [r7, #15] } 8005dee: 4618 mov r0, r3 8005df0: 3710 adds r7, #16 8005df2: 46bd mov sp, r7 8005df4: e8bd 4080 ldmia.w sp!, {r7, lr} 8005df8: b004 add sp, #16 8005dfa: 4770 bx lr 8005dfc: ffbdffbf .word 0xffbdffbf 8005e00: 03ee0000 .word 0x03ee0000 08005e04 : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 8005e04: b480 push {r7} 8005e06: b087 sub sp, #28 8005e08: af00 add r7, sp, #0 8005e0a: 60f8 str r0, [r7, #12] 8005e0c: 60b9 str r1, [r7, #8] 8005e0e: 4613 mov r3, r2 8005e10: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 8005e12: 79fb ldrb r3, [r7, #7] 8005e14: 2b02 cmp r3, #2 8005e16: d165 bne.n 8005ee4 { if ((hclk >= 14200000U) && (hclk < 15000000U)) 8005e18: 68bb ldr r3, [r7, #8] 8005e1a: 4a41 ldr r2, [pc, #260] ; (8005f20 ) 8005e1c: 4293 cmp r3, r2 8005e1e: d906 bls.n 8005e2e 8005e20: 68bb ldr r3, [r7, #8] 8005e22: 4a40 ldr r2, [pc, #256] ; (8005f24 ) 8005e24: 4293 cmp r3, r2 8005e26: d202 bcs.n 8005e2e { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 8005e28: 230f movs r3, #15 8005e2a: 617b str r3, [r7, #20] 8005e2c: e062 b.n 8005ef4 } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 8005e2e: 68bb ldr r3, [r7, #8] 8005e30: 4a3c ldr r2, [pc, #240] ; (8005f24 ) 8005e32: 4293 cmp r3, r2 8005e34: d306 bcc.n 8005e44 8005e36: 68bb ldr r3, [r7, #8] 8005e38: 4a3b ldr r2, [pc, #236] ; (8005f28 ) 8005e3a: 4293 cmp r3, r2 8005e3c: d202 bcs.n 8005e44 { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 8005e3e: 230e movs r3, #14 8005e40: 617b str r3, [r7, #20] 8005e42: e057 b.n 8005ef4 } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 8005e44: 68bb ldr r3, [r7, #8] 8005e46: 4a38 ldr r2, [pc, #224] ; (8005f28 ) 8005e48: 4293 cmp r3, r2 8005e4a: d306 bcc.n 8005e5a 8005e4c: 68bb ldr r3, [r7, #8] 8005e4e: 4a37 ldr r2, [pc, #220] ; (8005f2c ) 8005e50: 4293 cmp r3, r2 8005e52: d202 bcs.n 8005e5a { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 8005e54: 230d movs r3, #13 8005e56: 617b str r3, [r7, #20] 8005e58: e04c b.n 8005ef4 } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 8005e5a: 68bb ldr r3, [r7, #8] 8005e5c: 4a33 ldr r2, [pc, #204] ; (8005f2c ) 8005e5e: 4293 cmp r3, r2 8005e60: d306 bcc.n 8005e70 8005e62: 68bb ldr r3, [r7, #8] 8005e64: 4a32 ldr r2, [pc, #200] ; (8005f30 ) 8005e66: 4293 cmp r3, r2 8005e68: d802 bhi.n 8005e70 { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 8005e6a: 230c movs r3, #12 8005e6c: 617b str r3, [r7, #20] 8005e6e: e041 b.n 8005ef4 } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 8005e70: 68bb ldr r3, [r7, #8] 8005e72: 4a2f ldr r2, [pc, #188] ; (8005f30 ) 8005e74: 4293 cmp r3, r2 8005e76: d906 bls.n 8005e86 8005e78: 68bb ldr r3, [r7, #8] 8005e7a: 4a2e ldr r2, [pc, #184] ; (8005f34 ) 8005e7c: 4293 cmp r3, r2 8005e7e: d802 bhi.n 8005e86 { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 8005e80: 230b movs r3, #11 8005e82: 617b str r3, [r7, #20] 8005e84: e036 b.n 8005ef4 } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 8005e86: 68bb ldr r3, [r7, #8] 8005e88: 4a2a ldr r2, [pc, #168] ; (8005f34 ) 8005e8a: 4293 cmp r3, r2 8005e8c: d906 bls.n 8005e9c 8005e8e: 68bb ldr r3, [r7, #8] 8005e90: 4a29 ldr r2, [pc, #164] ; (8005f38 ) 8005e92: 4293 cmp r3, r2 8005e94: d802 bhi.n 8005e9c { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 8005e96: 230a movs r3, #10 8005e98: 617b str r3, [r7, #20] 8005e9a: e02b b.n 8005ef4 } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 8005e9c: 68bb ldr r3, [r7, #8] 8005e9e: 4a26 ldr r2, [pc, #152] ; (8005f38 ) 8005ea0: 4293 cmp r3, r2 8005ea2: d906 bls.n 8005eb2 8005ea4: 68bb ldr r3, [r7, #8] 8005ea6: 4a25 ldr r2, [pc, #148] ; (8005f3c ) 8005ea8: 4293 cmp r3, r2 8005eaa: d202 bcs.n 8005eb2 { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 8005eac: 2309 movs r3, #9 8005eae: 617b str r3, [r7, #20] 8005eb0: e020 b.n 8005ef4 } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 8005eb2: 68bb ldr r3, [r7, #8] 8005eb4: 4a21 ldr r2, [pc, #132] ; (8005f3c ) 8005eb6: 4293 cmp r3, r2 8005eb8: d306 bcc.n 8005ec8 8005eba: 68bb ldr r3, [r7, #8] 8005ebc: 4a20 ldr r2, [pc, #128] ; (8005f40 ) 8005ebe: 4293 cmp r3, r2 8005ec0: d802 bhi.n 8005ec8 { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 8005ec2: 2308 movs r3, #8 8005ec4: 617b str r3, [r7, #20] 8005ec6: e015 b.n 8005ef4 } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 8005ec8: 68bb ldr r3, [r7, #8] 8005eca: 4a1d ldr r2, [pc, #116] ; (8005f40 ) 8005ecc: 4293 cmp r3, r2 8005ece: d906 bls.n 8005ede 8005ed0: 68bb ldr r3, [r7, #8] 8005ed2: 4a1c ldr r2, [pc, #112] ; (8005f44 ) 8005ed4: 4293 cmp r3, r2 8005ed6: d202 bcs.n 8005ede { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 8005ed8: 2307 movs r3, #7 8005eda: 617b str r3, [r7, #20] 8005edc: e00a b.n 8005ef4 } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 8005ede: 2306 movs r3, #6 8005ee0: 617b str r3, [r7, #20] 8005ee2: e007 b.n 8005ef4 } } else if (speed == USBD_HS_SPEED) 8005ee4: 79fb ldrb r3, [r7, #7] 8005ee6: 2b00 cmp r3, #0 8005ee8: d102 bne.n 8005ef0 { UsbTrd = USBD_HS_TRDT_VALUE; 8005eea: 2309 movs r3, #9 8005eec: 617b str r3, [r7, #20] 8005eee: e001 b.n 8005ef4 } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 8005ef0: 2309 movs r3, #9 8005ef2: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 8005ef4: 68fb ldr r3, [r7, #12] 8005ef6: 68db ldr r3, [r3, #12] 8005ef8: f423 5270 bic.w r2, r3, #15360 ; 0x3c00 8005efc: 68fb ldr r3, [r7, #12] 8005efe: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 8005f00: 68fb ldr r3, [r7, #12] 8005f02: 68da ldr r2, [r3, #12] 8005f04: 697b ldr r3, [r7, #20] 8005f06: 029b lsls r3, r3, #10 8005f08: f403 5370 and.w r3, r3, #15360 ; 0x3c00 8005f0c: 431a orrs r2, r3 8005f0e: 68fb ldr r3, [r7, #12] 8005f10: 60da str r2, [r3, #12] return HAL_OK; 8005f12: 2300 movs r3, #0 } 8005f14: 4618 mov r0, r3 8005f16: 371c adds r7, #28 8005f18: 46bd mov sp, r7 8005f1a: f85d 7b04 ldr.w r7, [sp], #4 8005f1e: 4770 bx lr 8005f20: 00d8acbf .word 0x00d8acbf 8005f24: 00e4e1c0 .word 0x00e4e1c0 8005f28: 00f42400 .word 0x00f42400 8005f2c: 01067380 .word 0x01067380 8005f30: 011a499f .word 0x011a499f 8005f34: 01312cff .word 0x01312cff 8005f38: 014ca43f .word 0x014ca43f 8005f3c: 016e3600 .word 0x016e3600 8005f40: 01a6ab1f .word 0x01a6ab1f 8005f44: 01e84800 .word 0x01e84800 08005f48 : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8005f48: b480 push {r7} 8005f4a: b083 sub sp, #12 8005f4c: af00 add r7, sp, #0 8005f4e: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 8005f50: 687b ldr r3, [r7, #4] 8005f52: 689b ldr r3, [r3, #8] 8005f54: f043 0201 orr.w r2, r3, #1 8005f58: 687b ldr r3, [r7, #4] 8005f5a: 609a str r2, [r3, #8] return HAL_OK; 8005f5c: 2300 movs r3, #0 } 8005f5e: 4618 mov r0, r3 8005f60: 370c adds r7, #12 8005f62: 46bd mov sp, r7 8005f64: f85d 7b04 ldr.w r7, [sp], #4 8005f68: 4770 bx lr 08005f6a : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8005f6a: b480 push {r7} 8005f6c: b083 sub sp, #12 8005f6e: af00 add r7, sp, #0 8005f70: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 8005f72: 687b ldr r3, [r7, #4] 8005f74: 689b ldr r3, [r3, #8] 8005f76: f023 0201 bic.w r2, r3, #1 8005f7a: 687b ldr r3, [r7, #4] 8005f7c: 609a str r2, [r3, #8] return HAL_OK; 8005f7e: 2300 movs r3, #0 } 8005f80: 4618 mov r0, r3 8005f82: 370c adds r7, #12 8005f84: 46bd mov sp, r7 8005f86: f85d 7b04 ldr.w r7, [sp], #4 8005f8a: 4770 bx lr 08005f8c : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 8005f8c: b580 push {r7, lr} 8005f8e: b084 sub sp, #16 8005f90: af00 add r7, sp, #0 8005f92: 6078 str r0, [r7, #4] 8005f94: 460b mov r3, r1 8005f96: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 8005f98: 2300 movs r3, #0 8005f9a: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 8005f9c: 687b ldr r3, [r7, #4] 8005f9e: 68db ldr r3, [r3, #12] 8005fa0: f023 42c0 bic.w r2, r3, #1610612736 ; 0x60000000 8005fa4: 687b ldr r3, [r7, #4] 8005fa6: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 8005fa8: 78fb ldrb r3, [r7, #3] 8005faa: 2b01 cmp r3, #1 8005fac: d115 bne.n 8005fda { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 8005fae: 687b ldr r3, [r7, #4] 8005fb0: 68db ldr r3, [r3, #12] 8005fb2: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000 8005fb6: 687b ldr r3, [r7, #4] 8005fb8: 60da str r2, [r3, #12] do { HAL_Delay(1U); 8005fba: 2001 movs r0, #1 8005fbc: f7fb fafc bl 80015b8 ms++; 8005fc0: 68fb ldr r3, [r7, #12] 8005fc2: 3301 adds r3, #1 8005fc4: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); 8005fc6: 6878 ldr r0, [r7, #4] 8005fc8: f001 f995 bl 80072f6 8005fcc: 4603 mov r3, r0 8005fce: 2b01 cmp r3, #1 8005fd0: d01e beq.n 8006010 8005fd2: 68fb ldr r3, [r7, #12] 8005fd4: 2b31 cmp r3, #49 ; 0x31 8005fd6: d9f0 bls.n 8005fba 8005fd8: e01a b.n 8006010 } else if (mode == USB_DEVICE_MODE) 8005fda: 78fb ldrb r3, [r7, #3] 8005fdc: 2b00 cmp r3, #0 8005fde: d115 bne.n 800600c { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 8005fe0: 687b ldr r3, [r7, #4] 8005fe2: 68db ldr r3, [r3, #12] 8005fe4: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000 8005fe8: 687b ldr r3, [r7, #4] 8005fea: 60da str r2, [r3, #12] do { HAL_Delay(1U); 8005fec: 2001 movs r0, #1 8005fee: f7fb fae3 bl 80015b8 ms++; 8005ff2: 68fb ldr r3, [r7, #12] 8005ff4: 3301 adds r3, #1 8005ff6: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); 8005ff8: 6878 ldr r0, [r7, #4] 8005ffa: f001 f97c bl 80072f6 8005ffe: 4603 mov r3, r0 8006000: 2b00 cmp r3, #0 8006002: d005 beq.n 8006010 8006004: 68fb ldr r3, [r7, #12] 8006006: 2b31 cmp r3, #49 ; 0x31 8006008: d9f0 bls.n 8005fec 800600a: e001 b.n 8006010 } else { return HAL_ERROR; 800600c: 2301 movs r3, #1 800600e: e005 b.n 800601c } if (ms == 50U) 8006010: 68fb ldr r3, [r7, #12] 8006012: 2b32 cmp r3, #50 ; 0x32 8006014: d101 bne.n 800601a { return HAL_ERROR; 8006016: 2301 movs r3, #1 8006018: e000 b.n 800601c } return HAL_OK; 800601a: 2300 movs r3, #0 } 800601c: 4618 mov r0, r3 800601e: 3710 adds r7, #16 8006020: 46bd mov sp, r7 8006022: bd80 pop {r7, pc} 08006024 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8006024: b084 sub sp, #16 8006026: b580 push {r7, lr} 8006028: b086 sub sp, #24 800602a: af00 add r7, sp, #0 800602c: 6078 str r0, [r7, #4] 800602e: f107 0024 add.w r0, r7, #36 ; 0x24 8006032: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 8006036: 2300 movs r3, #0 8006038: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 800603a: 687b ldr r3, [r7, #4] 800603c: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 800603e: 2300 movs r3, #0 8006040: 613b str r3, [r7, #16] 8006042: e009 b.n 8006058 { USBx->DIEPTXF[i] = 0U; 8006044: 687a ldr r2, [r7, #4] 8006046: 693b ldr r3, [r7, #16] 8006048: 3340 adds r3, #64 ; 0x40 800604a: 009b lsls r3, r3, #2 800604c: 4413 add r3, r2 800604e: 2200 movs r2, #0 8006050: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 8006052: 693b ldr r3, [r7, #16] 8006054: 3301 adds r3, #1 8006056: 613b str r3, [r7, #16] 8006058: 693b ldr r3, [r7, #16] 800605a: 2b0e cmp r3, #14 800605c: d9f2 bls.n 8006044 } /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 800605e: 6cfb ldr r3, [r7, #76] ; 0x4c 8006060: 2b00 cmp r3, #0 8006062: d11c bne.n 800609e { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8006064: 68fb ldr r3, [r7, #12] 8006066: f503 6300 add.w r3, r3, #2048 ; 0x800 800606a: 685b ldr r3, [r3, #4] 800606c: 68fa ldr r2, [r7, #12] 800606e: f502 6200 add.w r2, r2, #2048 ; 0x800 8006072: f043 0302 orr.w r3, r3, #2 8006076: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 8006078: 687b ldr r3, [r7, #4] 800607a: 6b9b ldr r3, [r3, #56] ; 0x38 800607c: f423 1200 bic.w r2, r3, #2097152 ; 0x200000 8006080: 687b ldr r3, [r7, #4] 8006082: 639a str r2, [r3, #56] ; 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 8006084: 687b ldr r3, [r7, #4] 8006086: 681b ldr r3, [r3, #0] 8006088: f043 0240 orr.w r2, r3, #64 ; 0x40 800608c: 687b ldr r3, [r7, #4] 800608e: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 8006090: 687b ldr r3, [r7, #4] 8006092: 681b ldr r3, [r3, #0] 8006094: f043 0280 orr.w r2, r3, #128 ; 0x80 8006098: 687b ldr r3, [r7, #4] 800609a: 601a str r2, [r3, #0] 800609c: e005 b.n 80060aa } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 800609e: 687b ldr r3, [r7, #4] 80060a0: 6b9b ldr r3, [r3, #56] ; 0x38 80060a2: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 80060a6: 687b ldr r3, [r7, #4] 80060a8: 639a str r2, [r3, #56] ; 0x38 } /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 80060aa: 68fb ldr r3, [r7, #12] 80060ac: f503 6360 add.w r3, r3, #3584 ; 0xe00 80060b0: 461a mov r2, r3 80060b2: 2300 movs r3, #0 80060b4: 6013 str r3, [r2, #0] /* Device mode configuration */ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; 80060b6: 68fb ldr r3, [r7, #12] 80060b8: f503 6300 add.w r3, r3, #2048 ; 0x800 80060bc: 4619 mov r1, r3 80060be: 68fb ldr r3, [r7, #12] 80060c0: f503 6300 add.w r3, r3, #2048 ; 0x800 80060c4: 461a mov r2, r3 80060c6: 680b ldr r3, [r1, #0] 80060c8: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 80060ca: 6bbb ldr r3, [r7, #56] ; 0x38 80060cc: 2b01 cmp r3, #1 80060ce: d10c bne.n 80060ea { if (cfg.speed == USBD_HS_SPEED) 80060d0: 6afb ldr r3, [r7, #44] ; 0x2c 80060d2: 2b00 cmp r3, #0 80060d4: d104 bne.n 80060e0 { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 80060d6: 2100 movs r1, #0 80060d8: 6878 ldr r0, [r7, #4] 80060da: f000 f961 bl 80063a0 80060de: e008 b.n 80060f2 } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 80060e0: 2101 movs r1, #1 80060e2: 6878 ldr r0, [r7, #4] 80060e4: f000 f95c bl 80063a0 80060e8: e003 b.n 80060f2 } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 80060ea: 2103 movs r1, #3 80060ec: 6878 ldr r0, [r7, #4] 80060ee: f000 f957 bl 80063a0 } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 80060f2: 2110 movs r1, #16 80060f4: 6878 ldr r0, [r7, #4] 80060f6: f000 f8f3 bl 80062e0 80060fa: 4603 mov r3, r0 80060fc: 2b00 cmp r3, #0 80060fe: d001 beq.n 8006104 { ret = HAL_ERROR; 8006100: 2301 movs r3, #1 8006102: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 8006104: 6878 ldr r0, [r7, #4] 8006106: f000 f91d bl 8006344 800610a: 4603 mov r3, r0 800610c: 2b00 cmp r3, #0 800610e: d001 beq.n 8006114 { ret = HAL_ERROR; 8006110: 2301 movs r3, #1 8006112: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 8006114: 68fb ldr r3, [r7, #12] 8006116: f503 6300 add.w r3, r3, #2048 ; 0x800 800611a: 461a mov r2, r3 800611c: 2300 movs r3, #0 800611e: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 8006120: 68fb ldr r3, [r7, #12] 8006122: f503 6300 add.w r3, r3, #2048 ; 0x800 8006126: 461a mov r2, r3 8006128: 2300 movs r3, #0 800612a: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 800612c: 68fb ldr r3, [r7, #12] 800612e: f503 6300 add.w r3, r3, #2048 ; 0x800 8006132: 461a mov r2, r3 8006134: 2300 movs r3, #0 8006136: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 8006138: 2300 movs r3, #0 800613a: 613b str r3, [r7, #16] 800613c: e043 b.n 80061c6 { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 800613e: 693b ldr r3, [r7, #16] 8006140: 015a lsls r2, r3, #5 8006142: 68fb ldr r3, [r7, #12] 8006144: 4413 add r3, r2 8006146: f503 6310 add.w r3, r3, #2304 ; 0x900 800614a: 681b ldr r3, [r3, #0] 800614c: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8006150: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8006154: d118 bne.n 8006188 { if (i == 0U) 8006156: 693b ldr r3, [r7, #16] 8006158: 2b00 cmp r3, #0 800615a: d10a bne.n 8006172 { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 800615c: 693b ldr r3, [r7, #16] 800615e: 015a lsls r2, r3, #5 8006160: 68fb ldr r3, [r7, #12] 8006162: 4413 add r3, r2 8006164: f503 6310 add.w r3, r3, #2304 ; 0x900 8006168: 461a mov r2, r3 800616a: f04f 6300 mov.w r3, #134217728 ; 0x8000000 800616e: 6013 str r3, [r2, #0] 8006170: e013 b.n 800619a } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 8006172: 693b ldr r3, [r7, #16] 8006174: 015a lsls r2, r3, #5 8006176: 68fb ldr r3, [r7, #12] 8006178: 4413 add r3, r2 800617a: f503 6310 add.w r3, r3, #2304 ; 0x900 800617e: 461a mov r2, r3 8006180: f04f 4390 mov.w r3, #1207959552 ; 0x48000000 8006184: 6013 str r3, [r2, #0] 8006186: e008 b.n 800619a } } else { USBx_INEP(i)->DIEPCTL = 0U; 8006188: 693b ldr r3, [r7, #16] 800618a: 015a lsls r2, r3, #5 800618c: 68fb ldr r3, [r7, #12] 800618e: 4413 add r3, r2 8006190: f503 6310 add.w r3, r3, #2304 ; 0x900 8006194: 461a mov r2, r3 8006196: 2300 movs r3, #0 8006198: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 800619a: 693b ldr r3, [r7, #16] 800619c: 015a lsls r2, r3, #5 800619e: 68fb ldr r3, [r7, #12] 80061a0: 4413 add r3, r2 80061a2: f503 6310 add.w r3, r3, #2304 ; 0x900 80061a6: 461a mov r2, r3 80061a8: 2300 movs r3, #0 80061aa: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 80061ac: 693b ldr r3, [r7, #16] 80061ae: 015a lsls r2, r3, #5 80061b0: 68fb ldr r3, [r7, #12] 80061b2: 4413 add r3, r2 80061b4: f503 6310 add.w r3, r3, #2304 ; 0x900 80061b8: 461a mov r2, r3 80061ba: f64f 337f movw r3, #64383 ; 0xfb7f 80061be: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 80061c0: 693b ldr r3, [r7, #16] 80061c2: 3301 adds r3, #1 80061c4: 613b str r3, [r7, #16] 80061c6: 6a7b ldr r3, [r7, #36] ; 0x24 80061c8: 693a ldr r2, [r7, #16] 80061ca: 429a cmp r2, r3 80061cc: d3b7 bcc.n 800613e } for (i = 0U; i < cfg.dev_endpoints; i++) 80061ce: 2300 movs r3, #0 80061d0: 613b str r3, [r7, #16] 80061d2: e043 b.n 800625c { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80061d4: 693b ldr r3, [r7, #16] 80061d6: 015a lsls r2, r3, #5 80061d8: 68fb ldr r3, [r7, #12] 80061da: 4413 add r3, r2 80061dc: f503 6330 add.w r3, r3, #2816 ; 0xb00 80061e0: 681b ldr r3, [r3, #0] 80061e2: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 80061e6: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 80061ea: d118 bne.n 800621e { if (i == 0U) 80061ec: 693b ldr r3, [r7, #16] 80061ee: 2b00 cmp r3, #0 80061f0: d10a bne.n 8006208 { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 80061f2: 693b ldr r3, [r7, #16] 80061f4: 015a lsls r2, r3, #5 80061f6: 68fb ldr r3, [r7, #12] 80061f8: 4413 add r3, r2 80061fa: f503 6330 add.w r3, r3, #2816 ; 0xb00 80061fe: 461a mov r2, r3 8006200: f04f 6300 mov.w r3, #134217728 ; 0x8000000 8006204: 6013 str r3, [r2, #0] 8006206: e013 b.n 8006230 } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 8006208: 693b ldr r3, [r7, #16] 800620a: 015a lsls r2, r3, #5 800620c: 68fb ldr r3, [r7, #12] 800620e: 4413 add r3, r2 8006210: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006214: 461a mov r2, r3 8006216: f04f 4390 mov.w r3, #1207959552 ; 0x48000000 800621a: 6013 str r3, [r2, #0] 800621c: e008 b.n 8006230 } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 800621e: 693b ldr r3, [r7, #16] 8006220: 015a lsls r2, r3, #5 8006222: 68fb ldr r3, [r7, #12] 8006224: 4413 add r3, r2 8006226: f503 6330 add.w r3, r3, #2816 ; 0xb00 800622a: 461a mov r2, r3 800622c: 2300 movs r3, #0 800622e: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 8006230: 693b ldr r3, [r7, #16] 8006232: 015a lsls r2, r3, #5 8006234: 68fb ldr r3, [r7, #12] 8006236: 4413 add r3, r2 8006238: f503 6330 add.w r3, r3, #2816 ; 0xb00 800623c: 461a mov r2, r3 800623e: 2300 movs r3, #0 8006240: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8006242: 693b ldr r3, [r7, #16] 8006244: 015a lsls r2, r3, #5 8006246: 68fb ldr r3, [r7, #12] 8006248: 4413 add r3, r2 800624a: f503 6330 add.w r3, r3, #2816 ; 0xb00 800624e: 461a mov r2, r3 8006250: f64f 337f movw r3, #64383 ; 0xfb7f 8006254: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8006256: 693b ldr r3, [r7, #16] 8006258: 3301 adds r3, #1 800625a: 613b str r3, [r7, #16] 800625c: 6a7b ldr r3, [r7, #36] ; 0x24 800625e: 693a ldr r2, [r7, #16] 8006260: 429a cmp r2, r3 8006262: d3b7 bcc.n 80061d4 } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 8006264: 68fb ldr r3, [r7, #12] 8006266: f503 6300 add.w r3, r3, #2048 ; 0x800 800626a: 691b ldr r3, [r3, #16] 800626c: 68fa ldr r2, [r7, #12] 800626e: f502 6200 add.w r2, r2, #2048 ; 0x800 8006272: f423 7380 bic.w r3, r3, #256 ; 0x100 8006276: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 8006278: 687b ldr r3, [r7, #4] 800627a: 2200 movs r2, #0 800627c: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 800627e: 687b ldr r3, [r7, #4] 8006280: f06f 4280 mvn.w r2, #1073741824 ; 0x40000000 8006284: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 8006286: 6b3b ldr r3, [r7, #48] ; 0x30 8006288: 2b00 cmp r3, #0 800628a: d105 bne.n 8006298 { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 800628c: 687b ldr r3, [r7, #4] 800628e: 699b ldr r3, [r3, #24] 8006290: f043 0210 orr.w r2, r3, #16 8006294: 687b ldr r3, [r7, #4] 8006296: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 8006298: 687b ldr r3, [r7, #4] 800629a: 699a ldr r2, [r3, #24] 800629c: 4b0e ldr r3, [pc, #56] ; (80062d8 ) 800629e: 4313 orrs r3, r2 80062a0: 687a ldr r2, [r7, #4] 80062a2: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 80062a4: 6bfb ldr r3, [r7, #60] ; 0x3c 80062a6: 2b00 cmp r3, #0 80062a8: d005 beq.n 80062b6 { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 80062aa: 687b ldr r3, [r7, #4] 80062ac: 699b ldr r3, [r3, #24] 80062ae: f043 0208 orr.w r2, r3, #8 80062b2: 687b ldr r3, [r7, #4] 80062b4: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 80062b6: 6cfb ldr r3, [r7, #76] ; 0x4c 80062b8: 2b01 cmp r3, #1 80062ba: d105 bne.n 80062c8 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 80062bc: 687b ldr r3, [r7, #4] 80062be: 699a ldr r2, [r3, #24] 80062c0: 4b06 ldr r3, [pc, #24] ; (80062dc ) 80062c2: 4313 orrs r3, r2 80062c4: 687a ldr r2, [r7, #4] 80062c6: 6193 str r3, [r2, #24] } return ret; 80062c8: 7dfb ldrb r3, [r7, #23] } 80062ca: 4618 mov r0, r3 80062cc: 3718 adds r7, #24 80062ce: 46bd mov sp, r7 80062d0: e8bd 4080 ldmia.w sp!, {r7, lr} 80062d4: b004 add sp, #16 80062d6: 4770 bx lr 80062d8: 803c3800 .word 0x803c3800 80062dc: 40000004 .word 0x40000004 080062e0 : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 80062e0: b480 push {r7} 80062e2: b085 sub sp, #20 80062e4: af00 add r7, sp, #0 80062e6: 6078 str r0, [r7, #4] 80062e8: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 80062ea: 2300 movs r3, #0 80062ec: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { if (++count > 200000U) 80062ee: 68fb ldr r3, [r7, #12] 80062f0: 3301 adds r3, #1 80062f2: 60fb str r3, [r7, #12] 80062f4: 4a12 ldr r2, [pc, #72] ; (8006340 ) 80062f6: 4293 cmp r3, r2 80062f8: d901 bls.n 80062fe { return HAL_TIMEOUT; 80062fa: 2303 movs r3, #3 80062fc: e01a b.n 8006334 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80062fe: 687b ldr r3, [r7, #4] 8006300: 691b ldr r3, [r3, #16] 8006302: 2b00 cmp r3, #0 8006304: daf3 bge.n 80062ee /* Flush TX Fifo */ count = 0U; 8006306: 2300 movs r3, #0 8006308: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 800630a: 683b ldr r3, [r7, #0] 800630c: 019b lsls r3, r3, #6 800630e: f043 0220 orr.w r2, r3, #32 8006312: 687b ldr r3, [r7, #4] 8006314: 611a str r2, [r3, #16] do { if (++count > 200000U) 8006316: 68fb ldr r3, [r7, #12] 8006318: 3301 adds r3, #1 800631a: 60fb str r3, [r7, #12] 800631c: 4a08 ldr r2, [pc, #32] ; (8006340 ) 800631e: 4293 cmp r3, r2 8006320: d901 bls.n 8006326 { return HAL_TIMEOUT; 8006322: 2303 movs r3, #3 8006324: e006 b.n 8006334 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 8006326: 687b ldr r3, [r7, #4] 8006328: 691b ldr r3, [r3, #16] 800632a: f003 0320 and.w r3, r3, #32 800632e: 2b20 cmp r3, #32 8006330: d0f1 beq.n 8006316 return HAL_OK; 8006332: 2300 movs r3, #0 } 8006334: 4618 mov r0, r3 8006336: 3714 adds r7, #20 8006338: 46bd mov sp, r7 800633a: f85d 7b04 ldr.w r7, [sp], #4 800633e: 4770 bx lr 8006340: 00030d40 .word 0x00030d40 08006344 : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 8006344: b480 push {r7} 8006346: b085 sub sp, #20 8006348: af00 add r7, sp, #0 800634a: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 800634c: 2300 movs r3, #0 800634e: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { if (++count > 200000U) 8006350: 68fb ldr r3, [r7, #12] 8006352: 3301 adds r3, #1 8006354: 60fb str r3, [r7, #12] 8006356: 4a11 ldr r2, [pc, #68] ; (800639c ) 8006358: 4293 cmp r3, r2 800635a: d901 bls.n 8006360 { return HAL_TIMEOUT; 800635c: 2303 movs r3, #3 800635e: e017 b.n 8006390 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8006360: 687b ldr r3, [r7, #4] 8006362: 691b ldr r3, [r3, #16] 8006364: 2b00 cmp r3, #0 8006366: daf3 bge.n 8006350 /* Flush RX Fifo */ count = 0U; 8006368: 2300 movs r3, #0 800636a: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 800636c: 687b ldr r3, [r7, #4] 800636e: 2210 movs r2, #16 8006370: 611a str r2, [r3, #16] do { if (++count > 200000U) 8006372: 68fb ldr r3, [r7, #12] 8006374: 3301 adds r3, #1 8006376: 60fb str r3, [r7, #12] 8006378: 4a08 ldr r2, [pc, #32] ; (800639c ) 800637a: 4293 cmp r3, r2 800637c: d901 bls.n 8006382 { return HAL_TIMEOUT; 800637e: 2303 movs r3, #3 8006380: e006 b.n 8006390 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 8006382: 687b ldr r3, [r7, #4] 8006384: 691b ldr r3, [r3, #16] 8006386: f003 0310 and.w r3, r3, #16 800638a: 2b10 cmp r3, #16 800638c: d0f1 beq.n 8006372 return HAL_OK; 800638e: 2300 movs r3, #0 } 8006390: 4618 mov r0, r3 8006392: 3714 adds r7, #20 8006394: 46bd mov sp, r7 8006396: f85d 7b04 ldr.w r7, [sp], #4 800639a: 4770 bx lr 800639c: 00030d40 .word 0x00030d40 080063a0 : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 80063a0: b480 push {r7} 80063a2: b085 sub sp, #20 80063a4: af00 add r7, sp, #0 80063a6: 6078 str r0, [r7, #4] 80063a8: 460b mov r3, r1 80063aa: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80063ac: 687b ldr r3, [r7, #4] 80063ae: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 80063b0: 68fb ldr r3, [r7, #12] 80063b2: f503 6300 add.w r3, r3, #2048 ; 0x800 80063b6: 681a ldr r2, [r3, #0] 80063b8: 78fb ldrb r3, [r7, #3] 80063ba: 68f9 ldr r1, [r7, #12] 80063bc: f501 6100 add.w r1, r1, #2048 ; 0x800 80063c0: 4313 orrs r3, r2 80063c2: 600b str r3, [r1, #0] return HAL_OK; 80063c4: 2300 movs r3, #0 } 80063c6: 4618 mov r0, r3 80063c8: 3714 adds r7, #20 80063ca: 46bd mov sp, r7 80063cc: f85d 7b04 ldr.w r7, [sp], #4 80063d0: 4770 bx lr 080063d2 : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { 80063d2: b480 push {r7} 80063d4: b087 sub sp, #28 80063d6: af00 add r7, sp, #0 80063d8: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80063da: 687b ldr r3, [r7, #4] 80063dc: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 80063de: 693b ldr r3, [r7, #16] 80063e0: f503 6300 add.w r3, r3, #2048 ; 0x800 80063e4: 689b ldr r3, [r3, #8] 80063e6: f003 0306 and.w r3, r3, #6 80063ea: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 80063ec: 68fb ldr r3, [r7, #12] 80063ee: 2b00 cmp r3, #0 80063f0: d102 bne.n 80063f8 { speed = USBD_HS_SPEED; 80063f2: 2300 movs r3, #0 80063f4: 75fb strb r3, [r7, #23] 80063f6: e00a b.n 800640e } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 80063f8: 68fb ldr r3, [r7, #12] 80063fa: 2b02 cmp r3, #2 80063fc: d002 beq.n 8006404 80063fe: 68fb ldr r3, [r7, #12] 8006400: 2b06 cmp r3, #6 8006402: d102 bne.n 800640a (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 8006404: 2302 movs r3, #2 8006406: 75fb strb r3, [r7, #23] 8006408: e001 b.n 800640e } else { speed = 0xFU; 800640a: 230f movs r3, #15 800640c: 75fb strb r3, [r7, #23] } return speed; 800640e: 7dfb ldrb r3, [r7, #23] } 8006410: 4618 mov r0, r3 8006412: 371c adds r7, #28 8006414: 46bd mov sp, r7 8006416: f85d 7b04 ldr.w r7, [sp], #4 800641a: 4770 bx lr 0800641c : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 800641c: b480 push {r7} 800641e: b085 sub sp, #20 8006420: af00 add r7, sp, #0 8006422: 6078 str r0, [r7, #4] 8006424: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8006426: 687b ldr r3, [r7, #4] 8006428: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 800642a: 683b ldr r3, [r7, #0] 800642c: 781b ldrb r3, [r3, #0] 800642e: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8006430: 683b ldr r3, [r7, #0] 8006432: 785b ldrb r3, [r3, #1] 8006434: 2b01 cmp r3, #1 8006436: d139 bne.n 80064ac { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 8006438: 68fb ldr r3, [r7, #12] 800643a: f503 6300 add.w r3, r3, #2048 ; 0x800 800643e: 69da ldr r2, [r3, #28] 8006440: 683b ldr r3, [r7, #0] 8006442: 781b ldrb r3, [r3, #0] 8006444: f003 030f and.w r3, r3, #15 8006448: 2101 movs r1, #1 800644a: fa01 f303 lsl.w r3, r1, r3 800644e: b29b uxth r3, r3 8006450: 68f9 ldr r1, [r7, #12] 8006452: f501 6100 add.w r1, r1, #2048 ; 0x800 8006456: 4313 orrs r3, r2 8006458: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 800645a: 68bb ldr r3, [r7, #8] 800645c: 015a lsls r2, r3, #5 800645e: 68fb ldr r3, [r7, #12] 8006460: 4413 add r3, r2 8006462: f503 6310 add.w r3, r3, #2304 ; 0x900 8006466: 681b ldr r3, [r3, #0] 8006468: f403 4300 and.w r3, r3, #32768 ; 0x8000 800646c: 2b00 cmp r3, #0 800646e: d153 bne.n 8006518 { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8006470: 68bb ldr r3, [r7, #8] 8006472: 015a lsls r2, r3, #5 8006474: 68fb ldr r3, [r7, #12] 8006476: 4413 add r3, r2 8006478: f503 6310 add.w r3, r3, #2304 ; 0x900 800647c: 681a ldr r2, [r3, #0] 800647e: 683b ldr r3, [r7, #0] 8006480: 689b ldr r3, [r3, #8] 8006482: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 8006486: 683b ldr r3, [r7, #0] 8006488: 78db ldrb r3, [r3, #3] 800648a: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 800648c: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 800648e: 68bb ldr r3, [r7, #8] 8006490: 059b lsls r3, r3, #22 8006492: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8006494: 431a orrs r2, r3 8006496: 68bb ldr r3, [r7, #8] 8006498: 0159 lsls r1, r3, #5 800649a: 68fb ldr r3, [r7, #12] 800649c: 440b add r3, r1 800649e: f503 6310 add.w r3, r3, #2304 ; 0x900 80064a2: 4619 mov r1, r3 80064a4: 4b20 ldr r3, [pc, #128] ; (8006528 ) 80064a6: 4313 orrs r3, r2 80064a8: 600b str r3, [r1, #0] 80064aa: e035 b.n 8006518 USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 80064ac: 68fb ldr r3, [r7, #12] 80064ae: f503 6300 add.w r3, r3, #2048 ; 0x800 80064b2: 69da ldr r2, [r3, #28] 80064b4: 683b ldr r3, [r7, #0] 80064b6: 781b ldrb r3, [r3, #0] 80064b8: f003 030f and.w r3, r3, #15 80064bc: 2101 movs r1, #1 80064be: fa01 f303 lsl.w r3, r1, r3 80064c2: 041b lsls r3, r3, #16 80064c4: 68f9 ldr r1, [r7, #12] 80064c6: f501 6100 add.w r1, r1, #2048 ; 0x800 80064ca: 4313 orrs r3, r2 80064cc: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 80064ce: 68bb ldr r3, [r7, #8] 80064d0: 015a lsls r2, r3, #5 80064d2: 68fb ldr r3, [r7, #12] 80064d4: 4413 add r3, r2 80064d6: f503 6330 add.w r3, r3, #2816 ; 0xb00 80064da: 681b ldr r3, [r3, #0] 80064dc: f403 4300 and.w r3, r3, #32768 ; 0x8000 80064e0: 2b00 cmp r3, #0 80064e2: d119 bne.n 8006518 { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 80064e4: 68bb ldr r3, [r7, #8] 80064e6: 015a lsls r2, r3, #5 80064e8: 68fb ldr r3, [r7, #12] 80064ea: 4413 add r3, r2 80064ec: f503 6330 add.w r3, r3, #2816 ; 0xb00 80064f0: 681a ldr r2, [r3, #0] 80064f2: 683b ldr r3, [r7, #0] 80064f4: 689b ldr r3, [r3, #8] 80064f6: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 80064fa: 683b ldr r3, [r7, #0] 80064fc: 78db ldrb r3, [r3, #3] 80064fe: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 8006500: 430b orrs r3, r1 8006502: 431a orrs r2, r3 8006504: 68bb ldr r3, [r7, #8] 8006506: 0159 lsls r1, r3, #5 8006508: 68fb ldr r3, [r7, #12] 800650a: 440b add r3, r1 800650c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006510: 4619 mov r1, r3 8006512: 4b05 ldr r3, [pc, #20] ; (8006528 ) 8006514: 4313 orrs r3, r2 8006516: 600b str r3, [r1, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 8006518: 2300 movs r3, #0 } 800651a: 4618 mov r0, r3 800651c: 3714 adds r7, #20 800651e: 46bd mov sp, r7 8006520: f85d 7b04 ldr.w r7, [sp], #4 8006524: 4770 bx lr 8006526: bf00 nop 8006528: 10008000 .word 0x10008000 0800652c : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 800652c: b480 push {r7} 800652e: b085 sub sp, #20 8006530: af00 add r7, sp, #0 8006532: 6078 str r0, [r7, #4] 8006534: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8006536: 687b ldr r3, [r7, #4] 8006538: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 800653a: 683b ldr r3, [r7, #0] 800653c: 781b ldrb r3, [r3, #0] 800653e: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 8006540: 683b ldr r3, [r7, #0] 8006542: 785b ldrb r3, [r3, #1] 8006544: 2b01 cmp r3, #1 8006546: d161 bne.n 800660c { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8006548: 68bb ldr r3, [r7, #8] 800654a: 015a lsls r2, r3, #5 800654c: 68fb ldr r3, [r7, #12] 800654e: 4413 add r3, r2 8006550: f503 6310 add.w r3, r3, #2304 ; 0x900 8006554: 681b ldr r3, [r3, #0] 8006556: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 800655a: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 800655e: d11f bne.n 80065a0 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 8006560: 68bb ldr r3, [r7, #8] 8006562: 015a lsls r2, r3, #5 8006564: 68fb ldr r3, [r7, #12] 8006566: 4413 add r3, r2 8006568: f503 6310 add.w r3, r3, #2304 ; 0x900 800656c: 681b ldr r3, [r3, #0] 800656e: 68ba ldr r2, [r7, #8] 8006570: 0151 lsls r1, r2, #5 8006572: 68fa ldr r2, [r7, #12] 8006574: 440a add r2, r1 8006576: f502 6210 add.w r2, r2, #2304 ; 0x900 800657a: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 800657e: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 8006580: 68bb ldr r3, [r7, #8] 8006582: 015a lsls r2, r3, #5 8006584: 68fb ldr r3, [r7, #12] 8006586: 4413 add r3, r2 8006588: f503 6310 add.w r3, r3, #2304 ; 0x900 800658c: 681b ldr r3, [r3, #0] 800658e: 68ba ldr r2, [r7, #8] 8006590: 0151 lsls r1, r2, #5 8006592: 68fa ldr r2, [r7, #12] 8006594: 440a add r2, r1 8006596: f502 6210 add.w r2, r2, #2304 ; 0x900 800659a: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 800659e: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80065a0: 68fb ldr r3, [r7, #12] 80065a2: f503 6300 add.w r3, r3, #2048 ; 0x800 80065a6: 6bda ldr r2, [r3, #60] ; 0x3c 80065a8: 683b ldr r3, [r7, #0] 80065aa: 781b ldrb r3, [r3, #0] 80065ac: f003 030f and.w r3, r3, #15 80065b0: 2101 movs r1, #1 80065b2: fa01 f303 lsl.w r3, r1, r3 80065b6: b29b uxth r3, r3 80065b8: 43db mvns r3, r3 80065ba: 68f9 ldr r1, [r7, #12] 80065bc: f501 6100 add.w r1, r1, #2048 ; 0x800 80065c0: 4013 ands r3, r2 80065c2: 63cb str r3, [r1, #60] ; 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80065c4: 68fb ldr r3, [r7, #12] 80065c6: f503 6300 add.w r3, r3, #2048 ; 0x800 80065ca: 69da ldr r2, [r3, #28] 80065cc: 683b ldr r3, [r7, #0] 80065ce: 781b ldrb r3, [r3, #0] 80065d0: f003 030f and.w r3, r3, #15 80065d4: 2101 movs r1, #1 80065d6: fa01 f303 lsl.w r3, r1, r3 80065da: b29b uxth r3, r3 80065dc: 43db mvns r3, r3 80065de: 68f9 ldr r1, [r7, #12] 80065e0: f501 6100 add.w r1, r1, #2048 ; 0x800 80065e4: 4013 ands r3, r2 80065e6: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 80065e8: 68bb ldr r3, [r7, #8] 80065ea: 015a lsls r2, r3, #5 80065ec: 68fb ldr r3, [r7, #12] 80065ee: 4413 add r3, r2 80065f0: f503 6310 add.w r3, r3, #2304 ; 0x900 80065f4: 681a ldr r2, [r3, #0] 80065f6: 68bb ldr r3, [r7, #8] 80065f8: 0159 lsls r1, r3, #5 80065fa: 68fb ldr r3, [r7, #12] 80065fc: 440b add r3, r1 80065fe: f503 6310 add.w r3, r3, #2304 ; 0x900 8006602: 4619 mov r1, r3 8006604: 4b35 ldr r3, [pc, #212] ; (80066dc ) 8006606: 4013 ands r3, r2 8006608: 600b str r3, [r1, #0] 800660a: e060 b.n 80066ce USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 800660c: 68bb ldr r3, [r7, #8] 800660e: 015a lsls r2, r3, #5 8006610: 68fb ldr r3, [r7, #12] 8006612: 4413 add r3, r2 8006614: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006618: 681b ldr r3, [r3, #0] 800661a: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 800661e: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8006622: d11f bne.n 8006664 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 8006624: 68bb ldr r3, [r7, #8] 8006626: 015a lsls r2, r3, #5 8006628: 68fb ldr r3, [r7, #12] 800662a: 4413 add r3, r2 800662c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006630: 681b ldr r3, [r3, #0] 8006632: 68ba ldr r2, [r7, #8] 8006634: 0151 lsls r1, r2, #5 8006636: 68fa ldr r2, [r7, #12] 8006638: 440a add r2, r1 800663a: f502 6230 add.w r2, r2, #2816 ; 0xb00 800663e: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 8006642: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 8006644: 68bb ldr r3, [r7, #8] 8006646: 015a lsls r2, r3, #5 8006648: 68fb ldr r3, [r7, #12] 800664a: 4413 add r3, r2 800664c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006650: 681b ldr r3, [r3, #0] 8006652: 68ba ldr r2, [r7, #8] 8006654: 0151 lsls r1, r2, #5 8006656: 68fa ldr r2, [r7, #12] 8006658: 440a add r2, r1 800665a: f502 6230 add.w r2, r2, #2816 ; 0xb00 800665e: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 8006662: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 8006664: 68fb ldr r3, [r7, #12] 8006666: f503 6300 add.w r3, r3, #2048 ; 0x800 800666a: 6bda ldr r2, [r3, #60] ; 0x3c 800666c: 683b ldr r3, [r7, #0] 800666e: 781b ldrb r3, [r3, #0] 8006670: f003 030f and.w r3, r3, #15 8006674: 2101 movs r1, #1 8006676: fa01 f303 lsl.w r3, r1, r3 800667a: 041b lsls r3, r3, #16 800667c: 43db mvns r3, r3 800667e: 68f9 ldr r1, [r7, #12] 8006680: f501 6100 add.w r1, r1, #2048 ; 0x800 8006684: 4013 ands r3, r2 8006686: 63cb str r3, [r1, #60] ; 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 8006688: 68fb ldr r3, [r7, #12] 800668a: f503 6300 add.w r3, r3, #2048 ; 0x800 800668e: 69da ldr r2, [r3, #28] 8006690: 683b ldr r3, [r7, #0] 8006692: 781b ldrb r3, [r3, #0] 8006694: f003 030f and.w r3, r3, #15 8006698: 2101 movs r1, #1 800669a: fa01 f303 lsl.w r3, r1, r3 800669e: 041b lsls r3, r3, #16 80066a0: 43db mvns r3, r3 80066a2: 68f9 ldr r1, [r7, #12] 80066a4: f501 6100 add.w r1, r1, #2048 ; 0x800 80066a8: 4013 ands r3, r2 80066aa: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 80066ac: 68bb ldr r3, [r7, #8] 80066ae: 015a lsls r2, r3, #5 80066b0: 68fb ldr r3, [r7, #12] 80066b2: 4413 add r3, r2 80066b4: f503 6330 add.w r3, r3, #2816 ; 0xb00 80066b8: 681a ldr r2, [r3, #0] 80066ba: 68bb ldr r3, [r7, #8] 80066bc: 0159 lsls r1, r3, #5 80066be: 68fb ldr r3, [r7, #12] 80066c0: 440b add r3, r1 80066c2: f503 6330 add.w r3, r3, #2816 ; 0xb00 80066c6: 4619 mov r1, r3 80066c8: 4b05 ldr r3, [pc, #20] ; (80066e0 ) 80066ca: 4013 ands r3, r2 80066cc: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 80066ce: 2300 movs r3, #0 } 80066d0: 4618 mov r0, r3 80066d2: 3714 adds r7, #20 80066d4: 46bd mov sp, r7 80066d6: f85d 7b04 ldr.w r7, [sp], #4 80066da: 4770 bx lr 80066dc: ec337800 .word 0xec337800 80066e0: eff37800 .word 0xeff37800 080066e4 : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 80066e4: b580 push {r7, lr} 80066e6: b08a sub sp, #40 ; 0x28 80066e8: af02 add r7, sp, #8 80066ea: 60f8 str r0, [r7, #12] 80066ec: 60b9 str r1, [r7, #8] 80066ee: 4613 mov r3, r2 80066f0: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 80066f2: 68fb ldr r3, [r7, #12] 80066f4: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 80066f6: 68bb ldr r3, [r7, #8] 80066f8: 781b ldrb r3, [r3, #0] 80066fa: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 80066fc: 68bb ldr r3, [r7, #8] 80066fe: 785b ldrb r3, [r3, #1] 8006700: 2b01 cmp r3, #1 8006702: f040 8163 bne.w 80069cc { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 8006706: 68bb ldr r3, [r7, #8] 8006708: 695b ldr r3, [r3, #20] 800670a: 2b00 cmp r3, #0 800670c: d132 bne.n 8006774 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 800670e: 69bb ldr r3, [r7, #24] 8006710: 015a lsls r2, r3, #5 8006712: 69fb ldr r3, [r7, #28] 8006714: 4413 add r3, r2 8006716: f503 6310 add.w r3, r3, #2304 ; 0x900 800671a: 691a ldr r2, [r3, #16] 800671c: 69bb ldr r3, [r7, #24] 800671e: 0159 lsls r1, r3, #5 8006720: 69fb ldr r3, [r7, #28] 8006722: 440b add r3, r1 8006724: f503 6310 add.w r3, r3, #2304 ; 0x900 8006728: 4619 mov r1, r3 800672a: 4ba5 ldr r3, [pc, #660] ; (80069c0 ) 800672c: 4013 ands r3, r2 800672e: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8006730: 69bb ldr r3, [r7, #24] 8006732: 015a lsls r2, r3, #5 8006734: 69fb ldr r3, [r7, #28] 8006736: 4413 add r3, r2 8006738: f503 6310 add.w r3, r3, #2304 ; 0x900 800673c: 691b ldr r3, [r3, #16] 800673e: 69ba ldr r2, [r7, #24] 8006740: 0151 lsls r1, r2, #5 8006742: 69fa ldr r2, [r7, #28] 8006744: 440a add r2, r1 8006746: f502 6210 add.w r2, r2, #2304 ; 0x900 800674a: f443 2300 orr.w r3, r3, #524288 ; 0x80000 800674e: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8006750: 69bb ldr r3, [r7, #24] 8006752: 015a lsls r2, r3, #5 8006754: 69fb ldr r3, [r7, #28] 8006756: 4413 add r3, r2 8006758: f503 6310 add.w r3, r3, #2304 ; 0x900 800675c: 691a ldr r2, [r3, #16] 800675e: 69bb ldr r3, [r7, #24] 8006760: 0159 lsls r1, r3, #5 8006762: 69fb ldr r3, [r7, #28] 8006764: 440b add r3, r1 8006766: f503 6310 add.w r3, r3, #2304 ; 0x900 800676a: 4619 mov r1, r3 800676c: 4b95 ldr r3, [pc, #596] ; (80069c4 ) 800676e: 4013 ands r3, r2 8006770: 610b str r3, [r1, #16] 8006772: e074 b.n 800685e /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8006774: 69bb ldr r3, [r7, #24] 8006776: 015a lsls r2, r3, #5 8006778: 69fb ldr r3, [r7, #28] 800677a: 4413 add r3, r2 800677c: f503 6310 add.w r3, r3, #2304 ; 0x900 8006780: 691a ldr r2, [r3, #16] 8006782: 69bb ldr r3, [r7, #24] 8006784: 0159 lsls r1, r3, #5 8006786: 69fb ldr r3, [r7, #28] 8006788: 440b add r3, r1 800678a: f503 6310 add.w r3, r3, #2304 ; 0x900 800678e: 4619 mov r1, r3 8006790: 4b8c ldr r3, [pc, #560] ; (80069c4 ) 8006792: 4013 ands r3, r2 8006794: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8006796: 69bb ldr r3, [r7, #24] 8006798: 015a lsls r2, r3, #5 800679a: 69fb ldr r3, [r7, #28] 800679c: 4413 add r3, r2 800679e: f503 6310 add.w r3, r3, #2304 ; 0x900 80067a2: 691a ldr r2, [r3, #16] 80067a4: 69bb ldr r3, [r7, #24] 80067a6: 0159 lsls r1, r3, #5 80067a8: 69fb ldr r3, [r7, #28] 80067aa: 440b add r3, r1 80067ac: f503 6310 add.w r3, r3, #2304 ; 0x900 80067b0: 4619 mov r1, r3 80067b2: 4b83 ldr r3, [pc, #524] ; (80069c0 ) 80067b4: 4013 ands r3, r2 80067b6: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & 80067b8: 69bb ldr r3, [r7, #24] 80067ba: 015a lsls r2, r3, #5 80067bc: 69fb ldr r3, [r7, #28] 80067be: 4413 add r3, r2 80067c0: f503 6310 add.w r3, r3, #2304 ; 0x900 80067c4: 691a ldr r2, [r3, #16] (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); 80067c6: 68bb ldr r3, [r7, #8] 80067c8: 6959 ldr r1, [r3, #20] 80067ca: 68bb ldr r3, [r7, #8] 80067cc: 689b ldr r3, [r3, #8] 80067ce: 440b add r3, r1 80067d0: 1e59 subs r1, r3, #1 80067d2: 68bb ldr r3, [r7, #8] 80067d4: 689b ldr r3, [r3, #8] 80067d6: fbb1 f3f3 udiv r3, r1, r3 80067da: 04d9 lsls r1, r3, #19 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & 80067dc: 4b7a ldr r3, [pc, #488] ; (80069c8 ) 80067de: 400b ands r3, r1 80067e0: 69b9 ldr r1, [r7, #24] 80067e2: 0148 lsls r0, r1, #5 80067e4: 69f9 ldr r1, [r7, #28] 80067e6: 4401 add r1, r0 80067e8: f501 6110 add.w r1, r1, #2304 ; 0x900 80067ec: 4313 orrs r3, r2 80067ee: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 80067f0: 69bb ldr r3, [r7, #24] 80067f2: 015a lsls r2, r3, #5 80067f4: 69fb ldr r3, [r7, #28] 80067f6: 4413 add r3, r2 80067f8: f503 6310 add.w r3, r3, #2304 ; 0x900 80067fc: 691a ldr r2, [r3, #16] 80067fe: 68bb ldr r3, [r7, #8] 8006800: 695b ldr r3, [r3, #20] 8006802: f3c3 0312 ubfx r3, r3, #0, #19 8006806: 69b9 ldr r1, [r7, #24] 8006808: 0148 lsls r0, r1, #5 800680a: 69f9 ldr r1, [r7, #28] 800680c: 4401 add r1, r0 800680e: f501 6110 add.w r1, r1, #2304 ; 0x900 8006812: 4313 orrs r3, r2 8006814: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 8006816: 68bb ldr r3, [r7, #8] 8006818: 78db ldrb r3, [r3, #3] 800681a: 2b01 cmp r3, #1 800681c: d11f bne.n 800685e { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 800681e: 69bb ldr r3, [r7, #24] 8006820: 015a lsls r2, r3, #5 8006822: 69fb ldr r3, [r7, #28] 8006824: 4413 add r3, r2 8006826: f503 6310 add.w r3, r3, #2304 ; 0x900 800682a: 691b ldr r3, [r3, #16] 800682c: 69ba ldr r2, [r7, #24] 800682e: 0151 lsls r1, r2, #5 8006830: 69fa ldr r2, [r7, #28] 8006832: 440a add r2, r1 8006834: f502 6210 add.w r2, r2, #2304 ; 0x900 8006838: f023 43c0 bic.w r3, r3, #1610612736 ; 0x60000000 800683c: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); 800683e: 69bb ldr r3, [r7, #24] 8006840: 015a lsls r2, r3, #5 8006842: 69fb ldr r3, [r7, #28] 8006844: 4413 add r3, r2 8006846: f503 6310 add.w r3, r3, #2304 ; 0x900 800684a: 691b ldr r3, [r3, #16] 800684c: 69ba ldr r2, [r7, #24] 800684e: 0151 lsls r1, r2, #5 8006850: 69fa ldr r2, [r7, #28] 8006852: 440a add r2, r1 8006854: f502 6210 add.w r2, r2, #2304 ; 0x900 8006858: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 800685c: 6113 str r3, [r2, #16] } } if (dma == 1U) 800685e: 79fb ldrb r3, [r7, #7] 8006860: 2b01 cmp r3, #1 8006862: d14b bne.n 80068fc { if ((uint32_t)ep->dma_addr != 0U) 8006864: 68bb ldr r3, [r7, #8] 8006866: 691b ldr r3, [r3, #16] 8006868: 2b00 cmp r3, #0 800686a: d009 beq.n 8006880 { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 800686c: 69bb ldr r3, [r7, #24] 800686e: 015a lsls r2, r3, #5 8006870: 69fb ldr r3, [r7, #28] 8006872: 4413 add r3, r2 8006874: f503 6310 add.w r3, r3, #2304 ; 0x900 8006878: 461a mov r2, r3 800687a: 68bb ldr r3, [r7, #8] 800687c: 691b ldr r3, [r3, #16] 800687e: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 8006880: 68bb ldr r3, [r7, #8] 8006882: 78db ldrb r3, [r3, #3] 8006884: 2b01 cmp r3, #1 8006886: d128 bne.n 80068da { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8006888: 69fb ldr r3, [r7, #28] 800688a: f503 6300 add.w r3, r3, #2048 ; 0x800 800688e: 689b ldr r3, [r3, #8] 8006890: f403 7380 and.w r3, r3, #256 ; 0x100 8006894: 2b00 cmp r3, #0 8006896: d110 bne.n 80068ba { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8006898: 69bb ldr r3, [r7, #24] 800689a: 015a lsls r2, r3, #5 800689c: 69fb ldr r3, [r7, #28] 800689e: 4413 add r3, r2 80068a0: f503 6310 add.w r3, r3, #2304 ; 0x900 80068a4: 681b ldr r3, [r3, #0] 80068a6: 69ba ldr r2, [r7, #24] 80068a8: 0151 lsls r1, r2, #5 80068aa: 69fa ldr r2, [r7, #28] 80068ac: 440a add r2, r1 80068ae: f502 6210 add.w r2, r2, #2304 ; 0x900 80068b2: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 80068b6: 6013 str r3, [r2, #0] 80068b8: e00f b.n 80068da } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 80068ba: 69bb ldr r3, [r7, #24] 80068bc: 015a lsls r2, r3, #5 80068be: 69fb ldr r3, [r7, #28] 80068c0: 4413 add r3, r2 80068c2: f503 6310 add.w r3, r3, #2304 ; 0x900 80068c6: 681b ldr r3, [r3, #0] 80068c8: 69ba ldr r2, [r7, #24] 80068ca: 0151 lsls r1, r2, #5 80068cc: 69fa ldr r2, [r7, #28] 80068ce: 440a add r2, r1 80068d0: f502 6210 add.w r2, r2, #2304 ; 0x900 80068d4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80068d8: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 80068da: 69bb ldr r3, [r7, #24] 80068dc: 015a lsls r2, r3, #5 80068de: 69fb ldr r3, [r7, #28] 80068e0: 4413 add r3, r2 80068e2: f503 6310 add.w r3, r3, #2304 ; 0x900 80068e6: 681b ldr r3, [r3, #0] 80068e8: 69ba ldr r2, [r7, #24] 80068ea: 0151 lsls r1, r2, #5 80068ec: 69fa ldr r2, [r7, #28] 80068ee: 440a add r2, r1 80068f0: f502 6210 add.w r2, r2, #2304 ; 0x900 80068f4: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 80068f8: 6013 str r3, [r2, #0] 80068fa: e133 b.n 8006b64 } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 80068fc: 69bb ldr r3, [r7, #24] 80068fe: 015a lsls r2, r3, #5 8006900: 69fb ldr r3, [r7, #28] 8006902: 4413 add r3, r2 8006904: f503 6310 add.w r3, r3, #2304 ; 0x900 8006908: 681b ldr r3, [r3, #0] 800690a: 69ba ldr r2, [r7, #24] 800690c: 0151 lsls r1, r2, #5 800690e: 69fa ldr r2, [r7, #28] 8006910: 440a add r2, r1 8006912: f502 6210 add.w r2, r2, #2304 ; 0x900 8006916: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 800691a: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 800691c: 68bb ldr r3, [r7, #8] 800691e: 78db ldrb r3, [r3, #3] 8006920: 2b01 cmp r3, #1 8006922: d015 beq.n 8006950 { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 8006924: 68bb ldr r3, [r7, #8] 8006926: 695b ldr r3, [r3, #20] 8006928: 2b00 cmp r3, #0 800692a: f000 811b beq.w 8006b64 { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 800692e: 69fb ldr r3, [r7, #28] 8006930: f503 6300 add.w r3, r3, #2048 ; 0x800 8006934: 6b5a ldr r2, [r3, #52] ; 0x34 8006936: 68bb ldr r3, [r7, #8] 8006938: 781b ldrb r3, [r3, #0] 800693a: f003 030f and.w r3, r3, #15 800693e: 2101 movs r1, #1 8006940: fa01 f303 lsl.w r3, r1, r3 8006944: 69f9 ldr r1, [r7, #28] 8006946: f501 6100 add.w r1, r1, #2048 ; 0x800 800694a: 4313 orrs r3, r2 800694c: 634b str r3, [r1, #52] ; 0x34 800694e: e109 b.n 8006b64 } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8006950: 69fb ldr r3, [r7, #28] 8006952: f503 6300 add.w r3, r3, #2048 ; 0x800 8006956: 689b ldr r3, [r3, #8] 8006958: f403 7380 and.w r3, r3, #256 ; 0x100 800695c: 2b00 cmp r3, #0 800695e: d110 bne.n 8006982 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8006960: 69bb ldr r3, [r7, #24] 8006962: 015a lsls r2, r3, #5 8006964: 69fb ldr r3, [r7, #28] 8006966: 4413 add r3, r2 8006968: f503 6310 add.w r3, r3, #2304 ; 0x900 800696c: 681b ldr r3, [r3, #0] 800696e: 69ba ldr r2, [r7, #24] 8006970: 0151 lsls r1, r2, #5 8006972: 69fa ldr r2, [r7, #28] 8006974: 440a add r2, r1 8006976: f502 6210 add.w r2, r2, #2304 ; 0x900 800697a: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 800697e: 6013 str r3, [r2, #0] 8006980: e00f b.n 80069a2 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8006982: 69bb ldr r3, [r7, #24] 8006984: 015a lsls r2, r3, #5 8006986: 69fb ldr r3, [r7, #28] 8006988: 4413 add r3, r2 800698a: f503 6310 add.w r3, r3, #2304 ; 0x900 800698e: 681b ldr r3, [r3, #0] 8006990: 69ba ldr r2, [r7, #24] 8006992: 0151 lsls r1, r2, #5 8006994: 69fa ldr r2, [r7, #28] 8006996: 440a add r2, r1 8006998: f502 6210 add.w r2, r2, #2304 ; 0x900 800699c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80069a0: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 80069a2: 68bb ldr r3, [r7, #8] 80069a4: 68d9 ldr r1, [r3, #12] 80069a6: 68bb ldr r3, [r7, #8] 80069a8: 781a ldrb r2, [r3, #0] 80069aa: 68bb ldr r3, [r7, #8] 80069ac: 695b ldr r3, [r3, #20] 80069ae: b298 uxth r0, r3 80069b0: 79fb ldrb r3, [r7, #7] 80069b2: 9300 str r3, [sp, #0] 80069b4: 4603 mov r3, r0 80069b6: 68f8 ldr r0, [r7, #12] 80069b8: f000 fa38 bl 8006e2c 80069bc: e0d2 b.n 8006b64 80069be: bf00 nop 80069c0: e007ffff .word 0xe007ffff 80069c4: fff80000 .word 0xfff80000 80069c8: 1ff80000 .word 0x1ff80000 { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 80069cc: 69bb ldr r3, [r7, #24] 80069ce: 015a lsls r2, r3, #5 80069d0: 69fb ldr r3, [r7, #28] 80069d2: 4413 add r3, r2 80069d4: f503 6330 add.w r3, r3, #2816 ; 0xb00 80069d8: 691a ldr r2, [r3, #16] 80069da: 69bb ldr r3, [r7, #24] 80069dc: 0159 lsls r1, r3, #5 80069de: 69fb ldr r3, [r7, #28] 80069e0: 440b add r3, r1 80069e2: f503 6330 add.w r3, r3, #2816 ; 0xb00 80069e6: 4619 mov r1, r3 80069e8: 4b61 ldr r3, [pc, #388] ; (8006b70 ) 80069ea: 4013 ands r3, r2 80069ec: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 80069ee: 69bb ldr r3, [r7, #24] 80069f0: 015a lsls r2, r3, #5 80069f2: 69fb ldr r3, [r7, #28] 80069f4: 4413 add r3, r2 80069f6: f503 6330 add.w r3, r3, #2816 ; 0xb00 80069fa: 691a ldr r2, [r3, #16] 80069fc: 69bb ldr r3, [r7, #24] 80069fe: 0159 lsls r1, r3, #5 8006a00: 69fb ldr r3, [r7, #28] 8006a02: 440b add r3, r1 8006a04: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a08: 4619 mov r1, r3 8006a0a: 4b5a ldr r3, [pc, #360] ; (8006b74 ) 8006a0c: 4013 ands r3, r2 8006a0e: 610b str r3, [r1, #16] if (ep->xfer_len == 0U) 8006a10: 68bb ldr r3, [r7, #8] 8006a12: 695b ldr r3, [r3, #20] 8006a14: 2b00 cmp r3, #0 8006a16: d123 bne.n 8006a60 { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 8006a18: 69bb ldr r3, [r7, #24] 8006a1a: 015a lsls r2, r3, #5 8006a1c: 69fb ldr r3, [r7, #28] 8006a1e: 4413 add r3, r2 8006a20: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a24: 691a ldr r2, [r3, #16] 8006a26: 68bb ldr r3, [r7, #8] 8006a28: 689b ldr r3, [r3, #8] 8006a2a: f3c3 0312 ubfx r3, r3, #0, #19 8006a2e: 69b9 ldr r1, [r7, #24] 8006a30: 0148 lsls r0, r1, #5 8006a32: 69f9 ldr r1, [r7, #28] 8006a34: 4401 add r1, r0 8006a36: f501 6130 add.w r1, r1, #2816 ; 0xb00 8006a3a: 4313 orrs r3, r2 8006a3c: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8006a3e: 69bb ldr r3, [r7, #24] 8006a40: 015a lsls r2, r3, #5 8006a42: 69fb ldr r3, [r7, #28] 8006a44: 4413 add r3, r2 8006a46: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a4a: 691b ldr r3, [r3, #16] 8006a4c: 69ba ldr r2, [r7, #24] 8006a4e: 0151 lsls r1, r2, #5 8006a50: 69fa ldr r2, [r7, #28] 8006a52: 440a add r2, r1 8006a54: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006a58: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006a5c: 6113 str r3, [r2, #16] 8006a5e: e033 b.n 8006ac8 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8006a60: 68bb ldr r3, [r7, #8] 8006a62: 695a ldr r2, [r3, #20] 8006a64: 68bb ldr r3, [r7, #8] 8006a66: 689b ldr r3, [r3, #8] 8006a68: 4413 add r3, r2 8006a6a: 1e5a subs r2, r3, #1 8006a6c: 68bb ldr r3, [r7, #8] 8006a6e: 689b ldr r3, [r3, #8] 8006a70: fbb2 f3f3 udiv r3, r2, r3 8006a74: 82fb strh r3, [r7, #22] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 8006a76: 69bb ldr r3, [r7, #24] 8006a78: 015a lsls r2, r3, #5 8006a7a: 69fb ldr r3, [r7, #28] 8006a7c: 4413 add r3, r2 8006a7e: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a82: 691a ldr r2, [r3, #16] 8006a84: 8afb ldrh r3, [r7, #22] 8006a86: 04d9 lsls r1, r3, #19 8006a88: 4b3b ldr r3, [pc, #236] ; (8006b78 ) 8006a8a: 400b ands r3, r1 8006a8c: 69b9 ldr r1, [r7, #24] 8006a8e: 0148 lsls r0, r1, #5 8006a90: 69f9 ldr r1, [r7, #28] 8006a92: 4401 add r1, r0 8006a94: f501 6130 add.w r1, r1, #2816 ; 0xb00 8006a98: 4313 orrs r3, r2 8006a9a: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); 8006a9c: 69bb ldr r3, [r7, #24] 8006a9e: 015a lsls r2, r3, #5 8006aa0: 69fb ldr r3, [r7, #28] 8006aa2: 4413 add r3, r2 8006aa4: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006aa8: 691a ldr r2, [r3, #16] 8006aaa: 68bb ldr r3, [r7, #8] 8006aac: 689b ldr r3, [r3, #8] 8006aae: 8af9 ldrh r1, [r7, #22] 8006ab0: fb01 f303 mul.w r3, r1, r3 8006ab4: f3c3 0312 ubfx r3, r3, #0, #19 8006ab8: 69b9 ldr r1, [r7, #24] 8006aba: 0148 lsls r0, r1, #5 8006abc: 69f9 ldr r1, [r7, #28] 8006abe: 4401 add r1, r0 8006ac0: f501 6130 add.w r1, r1, #2816 ; 0xb00 8006ac4: 4313 orrs r3, r2 8006ac6: 610b str r3, [r1, #16] } if (dma == 1U) 8006ac8: 79fb ldrb r3, [r7, #7] 8006aca: 2b01 cmp r3, #1 8006acc: d10d bne.n 8006aea { if ((uint32_t)ep->xfer_buff != 0U) 8006ace: 68bb ldr r3, [r7, #8] 8006ad0: 68db ldr r3, [r3, #12] 8006ad2: 2b00 cmp r3, #0 8006ad4: d009 beq.n 8006aea { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8006ad6: 68bb ldr r3, [r7, #8] 8006ad8: 68d9 ldr r1, [r3, #12] 8006ada: 69bb ldr r3, [r7, #24] 8006adc: 015a lsls r2, r3, #5 8006ade: 69fb ldr r3, [r7, #28] 8006ae0: 4413 add r3, r2 8006ae2: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006ae6: 460a mov r2, r1 8006ae8: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 8006aea: 68bb ldr r3, [r7, #8] 8006aec: 78db ldrb r3, [r3, #3] 8006aee: 2b01 cmp r3, #1 8006af0: d128 bne.n 8006b44 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8006af2: 69fb ldr r3, [r7, #28] 8006af4: f503 6300 add.w r3, r3, #2048 ; 0x800 8006af8: 689b ldr r3, [r3, #8] 8006afa: f403 7380 and.w r3, r3, #256 ; 0x100 8006afe: 2b00 cmp r3, #0 8006b00: d110 bne.n 8006b24 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 8006b02: 69bb ldr r3, [r7, #24] 8006b04: 015a lsls r2, r3, #5 8006b06: 69fb ldr r3, [r7, #28] 8006b08: 4413 add r3, r2 8006b0a: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006b0e: 681b ldr r3, [r3, #0] 8006b10: 69ba ldr r2, [r7, #24] 8006b12: 0151 lsls r1, r2, #5 8006b14: 69fa ldr r2, [r7, #28] 8006b16: 440a add r2, r1 8006b18: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006b1c: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 8006b20: 6013 str r3, [r2, #0] 8006b22: e00f b.n 8006b44 } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 8006b24: 69bb ldr r3, [r7, #24] 8006b26: 015a lsls r2, r3, #5 8006b28: 69fb ldr r3, [r7, #28] 8006b2a: 4413 add r3, r2 8006b2c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006b30: 681b ldr r3, [r3, #0] 8006b32: 69ba ldr r2, [r7, #24] 8006b34: 0151 lsls r1, r2, #5 8006b36: 69fa ldr r2, [r7, #28] 8006b38: 440a add r2, r1 8006b3a: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006b3e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8006b42: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8006b44: 69bb ldr r3, [r7, #24] 8006b46: 015a lsls r2, r3, #5 8006b48: 69fb ldr r3, [r7, #28] 8006b4a: 4413 add r3, r2 8006b4c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006b50: 681b ldr r3, [r3, #0] 8006b52: 69ba ldr r2, [r7, #24] 8006b54: 0151 lsls r1, r2, #5 8006b56: 69fa ldr r2, [r7, #28] 8006b58: 440a add r2, r1 8006b5a: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006b5e: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 8006b62: 6013 str r3, [r2, #0] } return HAL_OK; 8006b64: 2300 movs r3, #0 } 8006b66: 4618 mov r0, r3 8006b68: 3720 adds r7, #32 8006b6a: 46bd mov sp, r7 8006b6c: bd80 pop {r7, pc} 8006b6e: bf00 nop 8006b70: fff80000 .word 0xfff80000 8006b74: e007ffff .word 0xe007ffff 8006b78: 1ff80000 .word 0x1ff80000 08006b7c : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 8006b7c: b480 push {r7} 8006b7e: b087 sub sp, #28 8006b80: af00 add r7, sp, #0 8006b82: 60f8 str r0, [r7, #12] 8006b84: 60b9 str r1, [r7, #8] 8006b86: 4613 mov r3, r2 8006b88: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 8006b8a: 68fb ldr r3, [r7, #12] 8006b8c: 617b str r3, [r7, #20] uint32_t epnum = (uint32_t)ep->num; 8006b8e: 68bb ldr r3, [r7, #8] 8006b90: 781b ldrb r3, [r3, #0] 8006b92: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 8006b94: 68bb ldr r3, [r7, #8] 8006b96: 785b ldrb r3, [r3, #1] 8006b98: 2b01 cmp r3, #1 8006b9a: f040 80cd bne.w 8006d38 { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 8006b9e: 68bb ldr r3, [r7, #8] 8006ba0: 695b ldr r3, [r3, #20] 8006ba2: 2b00 cmp r3, #0 8006ba4: d132 bne.n 8006c0c { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8006ba6: 693b ldr r3, [r7, #16] 8006ba8: 015a lsls r2, r3, #5 8006baa: 697b ldr r3, [r7, #20] 8006bac: 4413 add r3, r2 8006bae: f503 6310 add.w r3, r3, #2304 ; 0x900 8006bb2: 691a ldr r2, [r3, #16] 8006bb4: 693b ldr r3, [r7, #16] 8006bb6: 0159 lsls r1, r3, #5 8006bb8: 697b ldr r3, [r7, #20] 8006bba: 440b add r3, r1 8006bbc: f503 6310 add.w r3, r3, #2304 ; 0x900 8006bc0: 4619 mov r1, r3 8006bc2: 4b98 ldr r3, [pc, #608] ; (8006e24 ) 8006bc4: 4013 ands r3, r2 8006bc6: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8006bc8: 693b ldr r3, [r7, #16] 8006bca: 015a lsls r2, r3, #5 8006bcc: 697b ldr r3, [r7, #20] 8006bce: 4413 add r3, r2 8006bd0: f503 6310 add.w r3, r3, #2304 ; 0x900 8006bd4: 691b ldr r3, [r3, #16] 8006bd6: 693a ldr r2, [r7, #16] 8006bd8: 0151 lsls r1, r2, #5 8006bda: 697a ldr r2, [r7, #20] 8006bdc: 440a add r2, r1 8006bde: f502 6210 add.w r2, r2, #2304 ; 0x900 8006be2: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006be6: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8006be8: 693b ldr r3, [r7, #16] 8006bea: 015a lsls r2, r3, #5 8006bec: 697b ldr r3, [r7, #20] 8006bee: 4413 add r3, r2 8006bf0: f503 6310 add.w r3, r3, #2304 ; 0x900 8006bf4: 691a ldr r2, [r3, #16] 8006bf6: 693b ldr r3, [r7, #16] 8006bf8: 0159 lsls r1, r3, #5 8006bfa: 697b ldr r3, [r7, #20] 8006bfc: 440b add r3, r1 8006bfe: f503 6310 add.w r3, r3, #2304 ; 0x900 8006c02: 4619 mov r1, r3 8006c04: 4b88 ldr r3, [pc, #544] ; (8006e28 ) 8006c06: 4013 ands r3, r2 8006c08: 610b str r3, [r1, #16] 8006c0a: e04e b.n 8006caa /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8006c0c: 693b ldr r3, [r7, #16] 8006c0e: 015a lsls r2, r3, #5 8006c10: 697b ldr r3, [r7, #20] 8006c12: 4413 add r3, r2 8006c14: f503 6310 add.w r3, r3, #2304 ; 0x900 8006c18: 691a ldr r2, [r3, #16] 8006c1a: 693b ldr r3, [r7, #16] 8006c1c: 0159 lsls r1, r3, #5 8006c1e: 697b ldr r3, [r7, #20] 8006c20: 440b add r3, r1 8006c22: f503 6310 add.w r3, r3, #2304 ; 0x900 8006c26: 4619 mov r1, r3 8006c28: 4b7f ldr r3, [pc, #508] ; (8006e28 ) 8006c2a: 4013 ands r3, r2 8006c2c: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8006c2e: 693b ldr r3, [r7, #16] 8006c30: 015a lsls r2, r3, #5 8006c32: 697b ldr r3, [r7, #20] 8006c34: 4413 add r3, r2 8006c36: f503 6310 add.w r3, r3, #2304 ; 0x900 8006c3a: 691a ldr r2, [r3, #16] 8006c3c: 693b ldr r3, [r7, #16] 8006c3e: 0159 lsls r1, r3, #5 8006c40: 697b ldr r3, [r7, #20] 8006c42: 440b add r3, r1 8006c44: f503 6310 add.w r3, r3, #2304 ; 0x900 8006c48: 4619 mov r1, r3 8006c4a: 4b76 ldr r3, [pc, #472] ; (8006e24 ) 8006c4c: 4013 ands r3, r2 8006c4e: 610b str r3, [r1, #16] if (ep->xfer_len > ep->maxpacket) 8006c50: 68bb ldr r3, [r7, #8] 8006c52: 695a ldr r2, [r3, #20] 8006c54: 68bb ldr r3, [r7, #8] 8006c56: 689b ldr r3, [r3, #8] 8006c58: 429a cmp r2, r3 8006c5a: d903 bls.n 8006c64 { ep->xfer_len = ep->maxpacket; 8006c5c: 68bb ldr r3, [r7, #8] 8006c5e: 689a ldr r2, [r3, #8] 8006c60: 68bb ldr r3, [r7, #8] 8006c62: 615a str r2, [r3, #20] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8006c64: 693b ldr r3, [r7, #16] 8006c66: 015a lsls r2, r3, #5 8006c68: 697b ldr r3, [r7, #20] 8006c6a: 4413 add r3, r2 8006c6c: f503 6310 add.w r3, r3, #2304 ; 0x900 8006c70: 691b ldr r3, [r3, #16] 8006c72: 693a ldr r2, [r7, #16] 8006c74: 0151 lsls r1, r2, #5 8006c76: 697a ldr r2, [r7, #20] 8006c78: 440a add r2, r1 8006c7a: f502 6210 add.w r2, r2, #2304 ; 0x900 8006c7e: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006c82: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 8006c84: 693b ldr r3, [r7, #16] 8006c86: 015a lsls r2, r3, #5 8006c88: 697b ldr r3, [r7, #20] 8006c8a: 4413 add r3, r2 8006c8c: f503 6310 add.w r3, r3, #2304 ; 0x900 8006c90: 691a ldr r2, [r3, #16] 8006c92: 68bb ldr r3, [r7, #8] 8006c94: 695b ldr r3, [r3, #20] 8006c96: f3c3 0312 ubfx r3, r3, #0, #19 8006c9a: 6939 ldr r1, [r7, #16] 8006c9c: 0148 lsls r0, r1, #5 8006c9e: 6979 ldr r1, [r7, #20] 8006ca0: 4401 add r1, r0 8006ca2: f501 6110 add.w r1, r1, #2304 ; 0x900 8006ca6: 4313 orrs r3, r2 8006ca8: 610b str r3, [r1, #16] } if (dma == 1U) 8006caa: 79fb ldrb r3, [r7, #7] 8006cac: 2b01 cmp r3, #1 8006cae: d11e bne.n 8006cee { if ((uint32_t)ep->dma_addr != 0U) 8006cb0: 68bb ldr r3, [r7, #8] 8006cb2: 691b ldr r3, [r3, #16] 8006cb4: 2b00 cmp r3, #0 8006cb6: d009 beq.n 8006ccc { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 8006cb8: 693b ldr r3, [r7, #16] 8006cba: 015a lsls r2, r3, #5 8006cbc: 697b ldr r3, [r7, #20] 8006cbe: 4413 add r3, r2 8006cc0: f503 6310 add.w r3, r3, #2304 ; 0x900 8006cc4: 461a mov r2, r3 8006cc6: 68bb ldr r3, [r7, #8] 8006cc8: 691b ldr r3, [r3, #16] 8006cca: 6153 str r3, [r2, #20] } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8006ccc: 693b ldr r3, [r7, #16] 8006cce: 015a lsls r2, r3, #5 8006cd0: 697b ldr r3, [r7, #20] 8006cd2: 4413 add r3, r2 8006cd4: f503 6310 add.w r3, r3, #2304 ; 0x900 8006cd8: 681b ldr r3, [r3, #0] 8006cda: 693a ldr r2, [r7, #16] 8006cdc: 0151 lsls r1, r2, #5 8006cde: 697a ldr r2, [r7, #20] 8006ce0: 440a add r2, r1 8006ce2: f502 6210 add.w r2, r2, #2304 ; 0x900 8006ce6: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 8006cea: 6013 str r3, [r2, #0] 8006cec: e092 b.n 8006e14 } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8006cee: 693b ldr r3, [r7, #16] 8006cf0: 015a lsls r2, r3, #5 8006cf2: 697b ldr r3, [r7, #20] 8006cf4: 4413 add r3, r2 8006cf6: f503 6310 add.w r3, r3, #2304 ; 0x900 8006cfa: 681b ldr r3, [r3, #0] 8006cfc: 693a ldr r2, [r7, #16] 8006cfe: 0151 lsls r1, r2, #5 8006d00: 697a ldr r2, [r7, #20] 8006d02: 440a add r2, r1 8006d04: f502 6210 add.w r2, r2, #2304 ; 0x900 8006d08: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 8006d0c: 6013 str r3, [r2, #0] /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 8006d0e: 68bb ldr r3, [r7, #8] 8006d10: 695b ldr r3, [r3, #20] 8006d12: 2b00 cmp r3, #0 8006d14: d07e beq.n 8006e14 { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 8006d16: 697b ldr r3, [r7, #20] 8006d18: f503 6300 add.w r3, r3, #2048 ; 0x800 8006d1c: 6b5a ldr r2, [r3, #52] ; 0x34 8006d1e: 68bb ldr r3, [r7, #8] 8006d20: 781b ldrb r3, [r3, #0] 8006d22: f003 030f and.w r3, r3, #15 8006d26: 2101 movs r1, #1 8006d28: fa01 f303 lsl.w r3, r1, r3 8006d2c: 6979 ldr r1, [r7, #20] 8006d2e: f501 6100 add.w r1, r1, #2048 ; 0x800 8006d32: 4313 orrs r3, r2 8006d34: 634b str r3, [r1, #52] ; 0x34 8006d36: e06d b.n 8006e14 { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 8006d38: 693b ldr r3, [r7, #16] 8006d3a: 015a lsls r2, r3, #5 8006d3c: 697b ldr r3, [r7, #20] 8006d3e: 4413 add r3, r2 8006d40: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006d44: 691a ldr r2, [r3, #16] 8006d46: 693b ldr r3, [r7, #16] 8006d48: 0159 lsls r1, r3, #5 8006d4a: 697b ldr r3, [r7, #20] 8006d4c: 440b add r3, r1 8006d4e: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006d52: 4619 mov r1, r3 8006d54: 4b34 ldr r3, [pc, #208] ; (8006e28 ) 8006d56: 4013 ands r3, r2 8006d58: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 8006d5a: 693b ldr r3, [r7, #16] 8006d5c: 015a lsls r2, r3, #5 8006d5e: 697b ldr r3, [r7, #20] 8006d60: 4413 add r3, r2 8006d62: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006d66: 691a ldr r2, [r3, #16] 8006d68: 693b ldr r3, [r7, #16] 8006d6a: 0159 lsls r1, r3, #5 8006d6c: 697b ldr r3, [r7, #20] 8006d6e: 440b add r3, r1 8006d70: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006d74: 4619 mov r1, r3 8006d76: 4b2b ldr r3, [pc, #172] ; (8006e24 ) 8006d78: 4013 ands r3, r2 8006d7a: 610b str r3, [r1, #16] if (ep->xfer_len > 0U) 8006d7c: 68bb ldr r3, [r7, #8] 8006d7e: 695b ldr r3, [r3, #20] 8006d80: 2b00 cmp r3, #0 8006d82: d003 beq.n 8006d8c { ep->xfer_len = ep->maxpacket; 8006d84: 68bb ldr r3, [r7, #8] 8006d86: 689a ldr r2, [r3, #8] 8006d88: 68bb ldr r3, [r7, #8] 8006d8a: 615a str r2, [r3, #20] } USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8006d8c: 693b ldr r3, [r7, #16] 8006d8e: 015a lsls r2, r3, #5 8006d90: 697b ldr r3, [r7, #20] 8006d92: 4413 add r3, r2 8006d94: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006d98: 691b ldr r3, [r3, #16] 8006d9a: 693a ldr r2, [r7, #16] 8006d9c: 0151 lsls r1, r2, #5 8006d9e: 697a ldr r2, [r7, #20] 8006da0: 440a add r2, r1 8006da2: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006da6: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006daa: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); 8006dac: 693b ldr r3, [r7, #16] 8006dae: 015a lsls r2, r3, #5 8006db0: 697b ldr r3, [r7, #20] 8006db2: 4413 add r3, r2 8006db4: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006db8: 691a ldr r2, [r3, #16] 8006dba: 68bb ldr r3, [r7, #8] 8006dbc: 689b ldr r3, [r3, #8] 8006dbe: f3c3 0312 ubfx r3, r3, #0, #19 8006dc2: 6939 ldr r1, [r7, #16] 8006dc4: 0148 lsls r0, r1, #5 8006dc6: 6979 ldr r1, [r7, #20] 8006dc8: 4401 add r1, r0 8006dca: f501 6130 add.w r1, r1, #2816 ; 0xb00 8006dce: 4313 orrs r3, r2 8006dd0: 610b str r3, [r1, #16] if (dma == 1U) 8006dd2: 79fb ldrb r3, [r7, #7] 8006dd4: 2b01 cmp r3, #1 8006dd6: d10d bne.n 8006df4 { if ((uint32_t)ep->xfer_buff != 0U) 8006dd8: 68bb ldr r3, [r7, #8] 8006dda: 68db ldr r3, [r3, #12] 8006ddc: 2b00 cmp r3, #0 8006dde: d009 beq.n 8006df4 { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8006de0: 68bb ldr r3, [r7, #8] 8006de2: 68d9 ldr r1, [r3, #12] 8006de4: 693b ldr r3, [r7, #16] 8006de6: 015a lsls r2, r3, #5 8006de8: 697b ldr r3, [r7, #20] 8006dea: 4413 add r3, r2 8006dec: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006df0: 460a mov r2, r1 8006df2: 615a str r2, [r3, #20] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8006df4: 693b ldr r3, [r7, #16] 8006df6: 015a lsls r2, r3, #5 8006df8: 697b ldr r3, [r7, #20] 8006dfa: 4413 add r3, r2 8006dfc: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006e00: 681b ldr r3, [r3, #0] 8006e02: 693a ldr r2, [r7, #16] 8006e04: 0151 lsls r1, r2, #5 8006e06: 697a ldr r2, [r7, #20] 8006e08: 440a add r2, r1 8006e0a: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006e0e: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 8006e12: 6013 str r3, [r2, #0] } return HAL_OK; 8006e14: 2300 movs r3, #0 } 8006e16: 4618 mov r0, r3 8006e18: 371c adds r7, #28 8006e1a: 46bd mov sp, r7 8006e1c: f85d 7b04 ldr.w r7, [sp], #4 8006e20: 4770 bx lr 8006e22: bf00 nop 8006e24: e007ffff .word 0xe007ffff 8006e28: fff80000 .word 0xfff80000 08006e2c : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 8006e2c: b480 push {r7} 8006e2e: b089 sub sp, #36 ; 0x24 8006e30: af00 add r7, sp, #0 8006e32: 60f8 str r0, [r7, #12] 8006e34: 60b9 str r1, [r7, #8] 8006e36: 4611 mov r1, r2 8006e38: 461a mov r2, r3 8006e3a: 460b mov r3, r1 8006e3c: 71fb strb r3, [r7, #7] 8006e3e: 4613 mov r3, r2 8006e40: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8006e42: 68fb ldr r3, [r7, #12] 8006e44: 617b str r3, [r7, #20] uint8_t *pSrc = src; 8006e46: 68bb ldr r3, [r7, #8] 8006e48: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 8006e4a: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 8006e4e: 2b00 cmp r3, #0 8006e50: d123 bne.n 8006e9a { count32b = ((uint32_t)len + 3U) / 4U; 8006e52: 88bb ldrh r3, [r7, #4] 8006e54: 3303 adds r3, #3 8006e56: 089b lsrs r3, r3, #2 8006e58: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 8006e5a: 2300 movs r3, #0 8006e5c: 61bb str r3, [r7, #24] 8006e5e: e018 b.n 8006e92 { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 8006e60: 79fb ldrb r3, [r7, #7] 8006e62: 031a lsls r2, r3, #12 8006e64: 697b ldr r3, [r7, #20] 8006e66: 4413 add r3, r2 8006e68: f503 5380 add.w r3, r3, #4096 ; 0x1000 8006e6c: 461a mov r2, r3 8006e6e: 69fb ldr r3, [r7, #28] 8006e70: 681b ldr r3, [r3, #0] 8006e72: 6013 str r3, [r2, #0] pSrc++; 8006e74: 69fb ldr r3, [r7, #28] 8006e76: 3301 adds r3, #1 8006e78: 61fb str r3, [r7, #28] pSrc++; 8006e7a: 69fb ldr r3, [r7, #28] 8006e7c: 3301 adds r3, #1 8006e7e: 61fb str r3, [r7, #28] pSrc++; 8006e80: 69fb ldr r3, [r7, #28] 8006e82: 3301 adds r3, #1 8006e84: 61fb str r3, [r7, #28] pSrc++; 8006e86: 69fb ldr r3, [r7, #28] 8006e88: 3301 adds r3, #1 8006e8a: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 8006e8c: 69bb ldr r3, [r7, #24] 8006e8e: 3301 adds r3, #1 8006e90: 61bb str r3, [r7, #24] 8006e92: 69ba ldr r2, [r7, #24] 8006e94: 693b ldr r3, [r7, #16] 8006e96: 429a cmp r2, r3 8006e98: d3e2 bcc.n 8006e60 } } return HAL_OK; 8006e9a: 2300 movs r3, #0 } 8006e9c: 4618 mov r0, r3 8006e9e: 3724 adds r7, #36 ; 0x24 8006ea0: 46bd mov sp, r7 8006ea2: f85d 7b04 ldr.w r7, [sp], #4 8006ea6: 4770 bx lr 08006ea8 : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 8006ea8: b480 push {r7} 8006eaa: b08b sub sp, #44 ; 0x2c 8006eac: af00 add r7, sp, #0 8006eae: 60f8 str r0, [r7, #12] 8006eb0: 60b9 str r1, [r7, #8] 8006eb2: 4613 mov r3, r2 8006eb4: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 8006eb6: 68fb ldr r3, [r7, #12] 8006eb8: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 8006eba: 68bb ldr r3, [r7, #8] 8006ebc: 627b str r3, [r7, #36] ; 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 8006ebe: 88fb ldrh r3, [r7, #6] 8006ec0: 089b lsrs r3, r3, #2 8006ec2: b29b uxth r3, r3 8006ec4: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 8006ec6: 88fb ldrh r3, [r7, #6] 8006ec8: f003 0303 and.w r3, r3, #3 8006ecc: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 8006ece: 2300 movs r3, #0 8006ed0: 623b str r3, [r7, #32] 8006ed2: e014 b.n 8006efe { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 8006ed4: 69bb ldr r3, [r7, #24] 8006ed6: f503 5380 add.w r3, r3, #4096 ; 0x1000 8006eda: 681a ldr r2, [r3, #0] 8006edc: 6a7b ldr r3, [r7, #36] ; 0x24 8006ede: 601a str r2, [r3, #0] pDest++; 8006ee0: 6a7b ldr r3, [r7, #36] ; 0x24 8006ee2: 3301 adds r3, #1 8006ee4: 627b str r3, [r7, #36] ; 0x24 pDest++; 8006ee6: 6a7b ldr r3, [r7, #36] ; 0x24 8006ee8: 3301 adds r3, #1 8006eea: 627b str r3, [r7, #36] ; 0x24 pDest++; 8006eec: 6a7b ldr r3, [r7, #36] ; 0x24 8006eee: 3301 adds r3, #1 8006ef0: 627b str r3, [r7, #36] ; 0x24 pDest++; 8006ef2: 6a7b ldr r3, [r7, #36] ; 0x24 8006ef4: 3301 adds r3, #1 8006ef6: 627b str r3, [r7, #36] ; 0x24 for (i = 0U; i < count32b; i++) 8006ef8: 6a3b ldr r3, [r7, #32] 8006efa: 3301 adds r3, #1 8006efc: 623b str r3, [r7, #32] 8006efe: 6a3a ldr r2, [r7, #32] 8006f00: 697b ldr r3, [r7, #20] 8006f02: 429a cmp r2, r3 8006f04: d3e6 bcc.n 8006ed4 } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 8006f06: 8bfb ldrh r3, [r7, #30] 8006f08: 2b00 cmp r3, #0 8006f0a: d01e beq.n 8006f4a { i = 0U; 8006f0c: 2300 movs r3, #0 8006f0e: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 8006f10: 69bb ldr r3, [r7, #24] 8006f12: f503 5380 add.w r3, r3, #4096 ; 0x1000 8006f16: 461a mov r2, r3 8006f18: f107 0310 add.w r3, r7, #16 8006f1c: 6812 ldr r2, [r2, #0] 8006f1e: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 8006f20: 693a ldr r2, [r7, #16] 8006f22: 6a3b ldr r3, [r7, #32] 8006f24: b2db uxtb r3, r3 8006f26: 00db lsls r3, r3, #3 8006f28: fa22 f303 lsr.w r3, r2, r3 8006f2c: b2da uxtb r2, r3 8006f2e: 6a7b ldr r3, [r7, #36] ; 0x24 8006f30: 701a strb r2, [r3, #0] i++; 8006f32: 6a3b ldr r3, [r7, #32] 8006f34: 3301 adds r3, #1 8006f36: 623b str r3, [r7, #32] pDest++; 8006f38: 6a7b ldr r3, [r7, #36] ; 0x24 8006f3a: 3301 adds r3, #1 8006f3c: 627b str r3, [r7, #36] ; 0x24 remaining_bytes--; 8006f3e: 8bfb ldrh r3, [r7, #30] 8006f40: 3b01 subs r3, #1 8006f42: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 8006f44: 8bfb ldrh r3, [r7, #30] 8006f46: 2b00 cmp r3, #0 8006f48: d1ea bne.n 8006f20 } return ((void *)pDest); 8006f4a: 6a7b ldr r3, [r7, #36] ; 0x24 } 8006f4c: 4618 mov r0, r3 8006f4e: 372c adds r7, #44 ; 0x2c 8006f50: 46bd mov sp, r7 8006f52: f85d 7b04 ldr.w r7, [sp], #4 8006f56: 4770 bx lr 08006f58 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8006f58: b480 push {r7} 8006f5a: b085 sub sp, #20 8006f5c: af00 add r7, sp, #0 8006f5e: 6078 str r0, [r7, #4] 8006f60: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8006f62: 687b ldr r3, [r7, #4] 8006f64: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8006f66: 683b ldr r3, [r7, #0] 8006f68: 781b ldrb r3, [r3, #0] 8006f6a: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8006f6c: 683b ldr r3, [r7, #0] 8006f6e: 785b ldrb r3, [r3, #1] 8006f70: 2b01 cmp r3, #1 8006f72: d12c bne.n 8006fce { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 8006f74: 68bb ldr r3, [r7, #8] 8006f76: 015a lsls r2, r3, #5 8006f78: 68fb ldr r3, [r7, #12] 8006f7a: 4413 add r3, r2 8006f7c: f503 6310 add.w r3, r3, #2304 ; 0x900 8006f80: 681b ldr r3, [r3, #0] 8006f82: 2b00 cmp r3, #0 8006f84: db12 blt.n 8006fac 8006f86: 68bb ldr r3, [r7, #8] 8006f88: 2b00 cmp r3, #0 8006f8a: d00f beq.n 8006fac { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 8006f8c: 68bb ldr r3, [r7, #8] 8006f8e: 015a lsls r2, r3, #5 8006f90: 68fb ldr r3, [r7, #12] 8006f92: 4413 add r3, r2 8006f94: f503 6310 add.w r3, r3, #2304 ; 0x900 8006f98: 681b ldr r3, [r3, #0] 8006f9a: 68ba ldr r2, [r7, #8] 8006f9c: 0151 lsls r1, r2, #5 8006f9e: 68fa ldr r2, [r7, #12] 8006fa0: 440a add r2, r1 8006fa2: f502 6210 add.w r2, r2, #2304 ; 0x900 8006fa6: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 8006faa: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 8006fac: 68bb ldr r3, [r7, #8] 8006fae: 015a lsls r2, r3, #5 8006fb0: 68fb ldr r3, [r7, #12] 8006fb2: 4413 add r3, r2 8006fb4: f503 6310 add.w r3, r3, #2304 ; 0x900 8006fb8: 681b ldr r3, [r3, #0] 8006fba: 68ba ldr r2, [r7, #8] 8006fbc: 0151 lsls r1, r2, #5 8006fbe: 68fa ldr r2, [r7, #12] 8006fc0: 440a add r2, r1 8006fc2: f502 6210 add.w r2, r2, #2304 ; 0x900 8006fc6: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8006fca: 6013 str r3, [r2, #0] 8006fcc: e02b b.n 8007026 } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 8006fce: 68bb ldr r3, [r7, #8] 8006fd0: 015a lsls r2, r3, #5 8006fd2: 68fb ldr r3, [r7, #12] 8006fd4: 4413 add r3, r2 8006fd6: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006fda: 681b ldr r3, [r3, #0] 8006fdc: 2b00 cmp r3, #0 8006fde: db12 blt.n 8007006 8006fe0: 68bb ldr r3, [r7, #8] 8006fe2: 2b00 cmp r3, #0 8006fe4: d00f beq.n 8007006 { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 8006fe6: 68bb ldr r3, [r7, #8] 8006fe8: 015a lsls r2, r3, #5 8006fea: 68fb ldr r3, [r7, #12] 8006fec: 4413 add r3, r2 8006fee: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006ff2: 681b ldr r3, [r3, #0] 8006ff4: 68ba ldr r2, [r7, #8] 8006ff6: 0151 lsls r1, r2, #5 8006ff8: 68fa ldr r2, [r7, #12] 8006ffa: 440a add r2, r1 8006ffc: f502 6230 add.w r2, r2, #2816 ; 0xb00 8007000: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 8007004: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 8007006: 68bb ldr r3, [r7, #8] 8007008: 015a lsls r2, r3, #5 800700a: 68fb ldr r3, [r7, #12] 800700c: 4413 add r3, r2 800700e: f503 6330 add.w r3, r3, #2816 ; 0xb00 8007012: 681b ldr r3, [r3, #0] 8007014: 68ba ldr r2, [r7, #8] 8007016: 0151 lsls r1, r2, #5 8007018: 68fa ldr r2, [r7, #12] 800701a: 440a add r2, r1 800701c: f502 6230 add.w r2, r2, #2816 ; 0xb00 8007020: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8007024: 6013 str r3, [r2, #0] } return HAL_OK; 8007026: 2300 movs r3, #0 } 8007028: 4618 mov r0, r3 800702a: 3714 adds r7, #20 800702c: 46bd mov sp, r7 800702e: f85d 7b04 ldr.w r7, [sp], #4 8007032: 4770 bx lr 08007034 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8007034: b480 push {r7} 8007036: b085 sub sp, #20 8007038: af00 add r7, sp, #0 800703a: 6078 str r0, [r7, #4] 800703c: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800703e: 687b ldr r3, [r7, #4] 8007040: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007042: 683b ldr r3, [r7, #0] 8007044: 781b ldrb r3, [r3, #0] 8007046: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8007048: 683b ldr r3, [r7, #0] 800704a: 785b ldrb r3, [r3, #1] 800704c: 2b01 cmp r3, #1 800704e: d128 bne.n 80070a2 { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8007050: 68bb ldr r3, [r7, #8] 8007052: 015a lsls r2, r3, #5 8007054: 68fb ldr r3, [r7, #12] 8007056: 4413 add r3, r2 8007058: f503 6310 add.w r3, r3, #2304 ; 0x900 800705c: 681b ldr r3, [r3, #0] 800705e: 68ba ldr r2, [r7, #8] 8007060: 0151 lsls r1, r2, #5 8007062: 68fa ldr r2, [r7, #12] 8007064: 440a add r2, r1 8007066: f502 6210 add.w r2, r2, #2304 ; 0x900 800706a: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 800706e: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8007070: 683b ldr r3, [r7, #0] 8007072: 78db ldrb r3, [r3, #3] 8007074: 2b03 cmp r3, #3 8007076: d003 beq.n 8007080 8007078: 683b ldr r3, [r7, #0] 800707a: 78db ldrb r3, [r3, #3] 800707c: 2b02 cmp r3, #2 800707e: d138 bne.n 80070f2 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8007080: 68bb ldr r3, [r7, #8] 8007082: 015a lsls r2, r3, #5 8007084: 68fb ldr r3, [r7, #12] 8007086: 4413 add r3, r2 8007088: f503 6310 add.w r3, r3, #2304 ; 0x900 800708c: 681b ldr r3, [r3, #0] 800708e: 68ba ldr r2, [r7, #8] 8007090: 0151 lsls r1, r2, #5 8007092: 68fa ldr r2, [r7, #12] 8007094: 440a add r2, r1 8007096: f502 6210 add.w r2, r2, #2304 ; 0x900 800709a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 800709e: 6013 str r3, [r2, #0] 80070a0: e027 b.n 80070f2 } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 80070a2: 68bb ldr r3, [r7, #8] 80070a4: 015a lsls r2, r3, #5 80070a6: 68fb ldr r3, [r7, #12] 80070a8: 4413 add r3, r2 80070aa: f503 6330 add.w r3, r3, #2816 ; 0xb00 80070ae: 681b ldr r3, [r3, #0] 80070b0: 68ba ldr r2, [r7, #8] 80070b2: 0151 lsls r1, r2, #5 80070b4: 68fa ldr r2, [r7, #12] 80070b6: 440a add r2, r1 80070b8: f502 6230 add.w r2, r2, #2816 ; 0xb00 80070bc: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 80070c0: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 80070c2: 683b ldr r3, [r7, #0] 80070c4: 78db ldrb r3, [r3, #3] 80070c6: 2b03 cmp r3, #3 80070c8: d003 beq.n 80070d2 80070ca: 683b ldr r3, [r7, #0] 80070cc: 78db ldrb r3, [r3, #3] 80070ce: 2b02 cmp r3, #2 80070d0: d10f bne.n 80070f2 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 80070d2: 68bb ldr r3, [r7, #8] 80070d4: 015a lsls r2, r3, #5 80070d6: 68fb ldr r3, [r7, #12] 80070d8: 4413 add r3, r2 80070da: f503 6330 add.w r3, r3, #2816 ; 0xb00 80070de: 681b ldr r3, [r3, #0] 80070e0: 68ba ldr r2, [r7, #8] 80070e2: 0151 lsls r1, r2, #5 80070e4: 68fa ldr r2, [r7, #12] 80070e6: 440a add r2, r1 80070e8: f502 6230 add.w r2, r2, #2816 ; 0xb00 80070ec: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80070f0: 6013 str r3, [r2, #0] } } return HAL_OK; 80070f2: 2300 movs r3, #0 } 80070f4: 4618 mov r0, r3 80070f6: 3714 adds r7, #20 80070f8: 46bd mov sp, r7 80070fa: f85d 7b04 ldr.w r7, [sp], #4 80070fe: 4770 bx lr 08007100 : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 8007100: b480 push {r7} 8007102: b085 sub sp, #20 8007104: af00 add r7, sp, #0 8007106: 6078 str r0, [r7, #4] 8007108: 460b mov r3, r1 800710a: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 800710c: 687b ldr r3, [r7, #4] 800710e: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 8007110: 68fb ldr r3, [r7, #12] 8007112: f503 6300 add.w r3, r3, #2048 ; 0x800 8007116: 681b ldr r3, [r3, #0] 8007118: 68fa ldr r2, [r7, #12] 800711a: f502 6200 add.w r2, r2, #2048 ; 0x800 800711e: f423 63fe bic.w r3, r3, #2032 ; 0x7f0 8007122: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 8007124: 68fb ldr r3, [r7, #12] 8007126: f503 6300 add.w r3, r3, #2048 ; 0x800 800712a: 681a ldr r2, [r3, #0] 800712c: 78fb ldrb r3, [r7, #3] 800712e: 011b lsls r3, r3, #4 8007130: f403 63fe and.w r3, r3, #2032 ; 0x7f0 8007134: 68f9 ldr r1, [r7, #12] 8007136: f501 6100 add.w r1, r1, #2048 ; 0x800 800713a: 4313 orrs r3, r2 800713c: 600b str r3, [r1, #0] return HAL_OK; 800713e: 2300 movs r3, #0 } 8007140: 4618 mov r0, r3 8007142: 3714 adds r7, #20 8007144: 46bd mov sp, r7 8007146: f85d 7b04 ldr.w r7, [sp], #4 800714a: 4770 bx lr 0800714c : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) { 800714c: b480 push {r7} 800714e: b085 sub sp, #20 8007150: af00 add r7, sp, #0 8007152: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007154: 687b ldr r3, [r7, #4] 8007156: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8007158: 68fb ldr r3, [r7, #12] 800715a: f503 6360 add.w r3, r3, #3584 ; 0xe00 800715e: 681b ldr r3, [r3, #0] 8007160: 68fa ldr r2, [r7, #12] 8007162: f502 6260 add.w r2, r2, #3584 ; 0xe00 8007166: f023 0303 bic.w r3, r3, #3 800716a: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 800716c: 68fb ldr r3, [r7, #12] 800716e: f503 6300 add.w r3, r3, #2048 ; 0x800 8007172: 685b ldr r3, [r3, #4] 8007174: 68fa ldr r2, [r7, #12] 8007176: f502 6200 add.w r2, r2, #2048 ; 0x800 800717a: f023 0302 bic.w r3, r3, #2 800717e: 6053 str r3, [r2, #4] return HAL_OK; 8007180: 2300 movs r3, #0 } 8007182: 4618 mov r0, r3 8007184: 3714 adds r7, #20 8007186: 46bd mov sp, r7 8007188: f85d 7b04 ldr.w r7, [sp], #4 800718c: 4770 bx lr 0800718e : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) { 800718e: b480 push {r7} 8007190: b085 sub sp, #20 8007192: af00 add r7, sp, #0 8007194: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007196: 687b ldr r3, [r7, #4] 8007198: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 800719a: 68fb ldr r3, [r7, #12] 800719c: f503 6360 add.w r3, r3, #3584 ; 0xe00 80071a0: 681b ldr r3, [r3, #0] 80071a2: 68fa ldr r2, [r7, #12] 80071a4: f502 6260 add.w r2, r2, #3584 ; 0xe00 80071a8: f023 0303 bic.w r3, r3, #3 80071ac: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 80071ae: 68fb ldr r3, [r7, #12] 80071b0: f503 6300 add.w r3, r3, #2048 ; 0x800 80071b4: 685b ldr r3, [r3, #4] 80071b6: 68fa ldr r2, [r7, #12] 80071b8: f502 6200 add.w r2, r2, #2048 ; 0x800 80071bc: f043 0302 orr.w r3, r3, #2 80071c0: 6053 str r3, [r2, #4] return HAL_OK; 80071c2: 2300 movs r3, #0 } 80071c4: 4618 mov r0, r3 80071c6: 3714 adds r7, #20 80071c8: 46bd mov sp, r7 80071ca: f85d 7b04 ldr.w r7, [sp], #4 80071ce: 4770 bx lr 080071d0 : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) { 80071d0: b480 push {r7} 80071d2: b085 sub sp, #20 80071d4: af00 add r7, sp, #0 80071d6: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 80071d8: 687b ldr r3, [r7, #4] 80071da: 695b ldr r3, [r3, #20] 80071dc: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 80071de: 687b ldr r3, [r7, #4] 80071e0: 699b ldr r3, [r3, #24] 80071e2: 68fa ldr r2, [r7, #12] 80071e4: 4013 ands r3, r2 80071e6: 60fb str r3, [r7, #12] return tmpreg; 80071e8: 68fb ldr r3, [r7, #12] } 80071ea: 4618 mov r0, r3 80071ec: 3714 adds r7, #20 80071ee: 46bd mov sp, r7 80071f0: f85d 7b04 ldr.w r7, [sp], #4 80071f4: 4770 bx lr 080071f6 : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { 80071f6: b480 push {r7} 80071f8: b085 sub sp, #20 80071fa: af00 add r7, sp, #0 80071fc: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80071fe: 687b ldr r3, [r7, #4] 8007200: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8007202: 68fb ldr r3, [r7, #12] 8007204: f503 6300 add.w r3, r3, #2048 ; 0x800 8007208: 699b ldr r3, [r3, #24] 800720a: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 800720c: 68fb ldr r3, [r7, #12] 800720e: f503 6300 add.w r3, r3, #2048 ; 0x800 8007212: 69db ldr r3, [r3, #28] 8007214: 68ba ldr r2, [r7, #8] 8007216: 4013 ands r3, r2 8007218: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 800721a: 68bb ldr r3, [r7, #8] 800721c: 0c1b lsrs r3, r3, #16 } 800721e: 4618 mov r0, r3 8007220: 3714 adds r7, #20 8007222: 46bd mov sp, r7 8007224: f85d 7b04 ldr.w r7, [sp], #4 8007228: 4770 bx lr 0800722a : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { 800722a: b480 push {r7} 800722c: b085 sub sp, #20 800722e: af00 add r7, sp, #0 8007230: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007232: 687b ldr r3, [r7, #4] 8007234: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8007236: 68fb ldr r3, [r7, #12] 8007238: f503 6300 add.w r3, r3, #2048 ; 0x800 800723c: 699b ldr r3, [r3, #24] 800723e: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8007240: 68fb ldr r3, [r7, #12] 8007242: f503 6300 add.w r3, r3, #2048 ; 0x800 8007246: 69db ldr r3, [r3, #28] 8007248: 68ba ldr r2, [r7, #8] 800724a: 4013 ands r3, r2 800724c: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 800724e: 68bb ldr r3, [r7, #8] 8007250: b29b uxth r3, r3 } 8007252: 4618 mov r0, r3 8007254: 3714 adds r7, #20 8007256: 46bd mov sp, r7 8007258: f85d 7b04 ldr.w r7, [sp], #4 800725c: 4770 bx lr 0800725e : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 800725e: b480 push {r7} 8007260: b085 sub sp, #20 8007262: af00 add r7, sp, #0 8007264: 6078 str r0, [r7, #4] 8007266: 460b mov r3, r1 8007268: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 800726a: 687b ldr r3, [r7, #4] 800726c: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 800726e: 78fb ldrb r3, [r7, #3] 8007270: 015a lsls r2, r3, #5 8007272: 68fb ldr r3, [r7, #12] 8007274: 4413 add r3, r2 8007276: f503 6330 add.w r3, r3, #2816 ; 0xb00 800727a: 689b ldr r3, [r3, #8] 800727c: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 800727e: 68fb ldr r3, [r7, #12] 8007280: f503 6300 add.w r3, r3, #2048 ; 0x800 8007284: 695b ldr r3, [r3, #20] 8007286: 68ba ldr r2, [r7, #8] 8007288: 4013 ands r3, r2 800728a: 60bb str r3, [r7, #8] return tmpreg; 800728c: 68bb ldr r3, [r7, #8] } 800728e: 4618 mov r0, r3 8007290: 3714 adds r7, #20 8007292: 46bd mov sp, r7 8007294: f85d 7b04 ldr.w r7, [sp], #4 8007298: 4770 bx lr 0800729a : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 800729a: b480 push {r7} 800729c: b087 sub sp, #28 800729e: af00 add r7, sp, #0 80072a0: 6078 str r0, [r7, #4] 80072a2: 460b mov r3, r1 80072a4: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80072a6: 687b ldr r3, [r7, #4] 80072a8: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 80072aa: 697b ldr r3, [r7, #20] 80072ac: f503 6300 add.w r3, r3, #2048 ; 0x800 80072b0: 691b ldr r3, [r3, #16] 80072b2: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 80072b4: 697b ldr r3, [r7, #20] 80072b6: f503 6300 add.w r3, r3, #2048 ; 0x800 80072ba: 6b5b ldr r3, [r3, #52] ; 0x34 80072bc: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 80072be: 78fb ldrb r3, [r7, #3] 80072c0: f003 030f and.w r3, r3, #15 80072c4: 68fa ldr r2, [r7, #12] 80072c6: fa22 f303 lsr.w r3, r2, r3 80072ca: 01db lsls r3, r3, #7 80072cc: b2db uxtb r3, r3 80072ce: 693a ldr r2, [r7, #16] 80072d0: 4313 orrs r3, r2 80072d2: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 80072d4: 78fb ldrb r3, [r7, #3] 80072d6: 015a lsls r2, r3, #5 80072d8: 697b ldr r3, [r7, #20] 80072da: 4413 add r3, r2 80072dc: f503 6310 add.w r3, r3, #2304 ; 0x900 80072e0: 689b ldr r3, [r3, #8] 80072e2: 693a ldr r2, [r7, #16] 80072e4: 4013 ands r3, r2 80072e6: 60bb str r3, [r7, #8] return tmpreg; 80072e8: 68bb ldr r3, [r7, #8] } 80072ea: 4618 mov r0, r3 80072ec: 371c adds r7, #28 80072ee: 46bd mov sp, r7 80072f0: f85d 7b04 ldr.w r7, [sp], #4 80072f4: 4770 bx lr 080072f6 : * This parameter can be one of these values: * 0 : Host * 1 : Device */ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) { 80072f6: b480 push {r7} 80072f8: b083 sub sp, #12 80072fa: af00 add r7, sp, #0 80072fc: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 80072fe: 687b ldr r3, [r7, #4] 8007300: 695b ldr r3, [r3, #20] 8007302: f003 0301 and.w r3, r3, #1 } 8007306: 4618 mov r0, r3 8007308: 370c adds r7, #12 800730a: 46bd mov sp, r7 800730c: f85d 7b04 ldr.w r7, [sp], #4 8007310: 4770 bx lr ... 08007314 : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) { 8007314: b480 push {r7} 8007316: b085 sub sp, #20 8007318: af00 add r7, sp, #0 800731a: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800731c: 687b ldr r3, [r7, #4] 800731e: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 8007320: 68fb ldr r3, [r7, #12] 8007322: f503 6310 add.w r3, r3, #2304 ; 0x900 8007326: 681a ldr r2, [r3, #0] 8007328: 68fb ldr r3, [r7, #12] 800732a: f503 6310 add.w r3, r3, #2304 ; 0x900 800732e: 4619 mov r1, r3 8007330: 4b09 ldr r3, [pc, #36] ; (8007358 ) 8007332: 4013 ands r3, r2 8007334: 600b str r3, [r1, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 8007336: 68fb ldr r3, [r7, #12] 8007338: f503 6300 add.w r3, r3, #2048 ; 0x800 800733c: 685b ldr r3, [r3, #4] 800733e: 68fa ldr r2, [r7, #12] 8007340: f502 6200 add.w r2, r2, #2048 ; 0x800 8007344: f443 7380 orr.w r3, r3, #256 ; 0x100 8007348: 6053 str r3, [r2, #4] return HAL_OK; 800734a: 2300 movs r3, #0 } 800734c: 4618 mov r0, r3 800734e: 3714 adds r7, #20 8007350: 46bd mov sp, r7 8007352: f85d 7b04 ldr.w r7, [sp], #4 8007356: 4770 bx lr 8007358: fffff800 .word 0xfffff800 0800735c : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) { 800735c: b480 push {r7} 800735e: b087 sub sp, #28 8007360: af00 add r7, sp, #0 8007362: 60f8 str r0, [r7, #12] 8007364: 460b mov r3, r1 8007366: 607a str r2, [r7, #4] 8007368: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 800736a: 68fb ldr r3, [r7, #12] 800736c: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); 800736e: 68fb ldr r3, [r7, #12] 8007370: 333c adds r3, #60 ; 0x3c 8007372: 3304 adds r3, #4 8007374: 681b ldr r3, [r3, #0] 8007376: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 8007378: 693b ldr r3, [r7, #16] 800737a: 4a26 ldr r2, [pc, #152] ; (8007414 ) 800737c: 4293 cmp r3, r2 800737e: d90a bls.n 8007396 { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007380: 697b ldr r3, [r7, #20] 8007382: f503 6330 add.w r3, r3, #2816 ; 0xb00 8007386: 681b ldr r3, [r3, #0] 8007388: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 800738c: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8007390: d101 bne.n 8007396 { return HAL_OK; 8007392: 2300 movs r3, #0 8007394: e037 b.n 8007406 } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 8007396: 697b ldr r3, [r7, #20] 8007398: f503 6330 add.w r3, r3, #2816 ; 0xb00 800739c: 461a mov r2, r3 800739e: 2300 movs r3, #0 80073a0: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 80073a2: 697b ldr r3, [r7, #20] 80073a4: f503 6330 add.w r3, r3, #2816 ; 0xb00 80073a8: 691b ldr r3, [r3, #16] 80073aa: 697a ldr r2, [r7, #20] 80073ac: f502 6230 add.w r2, r2, #2816 ; 0xb00 80073b0: f443 2300 orr.w r3, r3, #524288 ; 0x80000 80073b4: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 80073b6: 697b ldr r3, [r7, #20] 80073b8: f503 6330 add.w r3, r3, #2816 ; 0xb00 80073bc: 691b ldr r3, [r3, #16] 80073be: 697a ldr r2, [r7, #20] 80073c0: f502 6230 add.w r2, r2, #2816 ; 0xb00 80073c4: f043 0318 orr.w r3, r3, #24 80073c8: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 80073ca: 697b ldr r3, [r7, #20] 80073cc: f503 6330 add.w r3, r3, #2816 ; 0xb00 80073d0: 691b ldr r3, [r3, #16] 80073d2: 697a ldr r2, [r7, #20] 80073d4: f502 6230 add.w r2, r2, #2816 ; 0xb00 80073d8: f043 43c0 orr.w r3, r3, #1610612736 ; 0x60000000 80073dc: 6113 str r3, [r2, #16] if (dma == 1U) 80073de: 7afb ldrb r3, [r7, #11] 80073e0: 2b01 cmp r3, #1 80073e2: d10f bne.n 8007404 { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 80073e4: 697b ldr r3, [r7, #20] 80073e6: f503 6330 add.w r3, r3, #2816 ; 0xb00 80073ea: 461a mov r2, r3 80073ec: 687b ldr r3, [r7, #4] 80073ee: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 80073f0: 697b ldr r3, [r7, #20] 80073f2: f503 6330 add.w r3, r3, #2816 ; 0xb00 80073f6: 681b ldr r3, [r3, #0] 80073f8: 697a ldr r2, [r7, #20] 80073fa: f502 6230 add.w r2, r2, #2816 ; 0xb00 80073fe: f043 2380 orr.w r3, r3, #2147516416 ; 0x80008000 8007402: 6013 str r3, [r2, #0] } return HAL_OK; 8007404: 2300 movs r3, #0 } 8007406: 4618 mov r0, r3 8007408: 371c adds r7, #28 800740a: 46bd mov sp, r7 800740c: f85d 7b04 ldr.w r7, [sp], #4 8007410: 4770 bx lr 8007412: bf00 nop 8007414: 4f54300a .word 0x4f54300a 08007418 : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 8007418: b480 push {r7} 800741a: b085 sub sp, #20 800741c: af00 add r7, sp, #0 800741e: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8007420: 2300 movs r3, #0 8007422: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { if (++count > 200000U) 8007424: 68fb ldr r3, [r7, #12] 8007426: 3301 adds r3, #1 8007428: 60fb str r3, [r7, #12] 800742a: 4a13 ldr r2, [pc, #76] ; (8007478 ) 800742c: 4293 cmp r3, r2 800742e: d901 bls.n 8007434 { return HAL_TIMEOUT; 8007430: 2303 movs r3, #3 8007432: e01a b.n 800746a } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8007434: 687b ldr r3, [r7, #4] 8007436: 691b ldr r3, [r3, #16] 8007438: 2b00 cmp r3, #0 800743a: daf3 bge.n 8007424 /* Core Soft Reset */ count = 0U; 800743c: 2300 movs r3, #0 800743e: 60fb str r3, [r7, #12] USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 8007440: 687b ldr r3, [r7, #4] 8007442: 691b ldr r3, [r3, #16] 8007444: f043 0201 orr.w r2, r3, #1 8007448: 687b ldr r3, [r7, #4] 800744a: 611a str r2, [r3, #16] do { if (++count > 200000U) 800744c: 68fb ldr r3, [r7, #12] 800744e: 3301 adds r3, #1 8007450: 60fb str r3, [r7, #12] 8007452: 4a09 ldr r2, [pc, #36] ; (8007478 ) 8007454: 4293 cmp r3, r2 8007456: d901 bls.n 800745c { return HAL_TIMEOUT; 8007458: 2303 movs r3, #3 800745a: e006 b.n 800746a } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 800745c: 687b ldr r3, [r7, #4] 800745e: 691b ldr r3, [r3, #16] 8007460: f003 0301 and.w r3, r3, #1 8007464: 2b01 cmp r3, #1 8007466: d0f1 beq.n 800744c return HAL_OK; 8007468: 2300 movs r3, #0 } 800746a: 4618 mov r0, r3 800746c: 3714 adds r7, #20 800746e: 46bd mov sp, r7 8007470: f85d 7b04 ldr.w r7, [sp], #4 8007474: 4770 bx lr 8007476: bf00 nop 8007478: 00030d40 .word 0x00030d40 0800747c : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 800747c: b580 push {r7, lr} 800747e: b084 sub sp, #16 8007480: af00 add r7, sp, #0 8007482: 6078 str r0, [r7, #4] 8007484: 460b mov r3, r1 8007486: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_CDC_HandleTypeDef *hcdc; hcdc = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); 8007488: f44f 7007 mov.w r0, #540 ; 0x21c 800748c: f002 f986 bl 800979c 8007490: 60f8 str r0, [r7, #12] if (hcdc == NULL) 8007492: 68fb ldr r3, [r7, #12] 8007494: 2b00 cmp r3, #0 8007496: d105 bne.n 80074a4 { pdev->pClassData = NULL; 8007498: 687b ldr r3, [r7, #4] 800749a: 2200 movs r2, #0 800749c: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc return (uint8_t)USBD_EMEM; 80074a0: 2302 movs r3, #2 80074a2: e066 b.n 8007572 } pdev->pClassData = (void *)hcdc; 80074a4: 687b ldr r3, [r7, #4] 80074a6: 68fa ldr r2, [r7, #12] 80074a8: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc if (pdev->dev_speed == USBD_SPEED_HIGH) 80074ac: 687b ldr r3, [r7, #4] 80074ae: 7c1b ldrb r3, [r3, #16] 80074b0: 2b00 cmp r3, #0 80074b2: d119 bne.n 80074e8 { /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, 80074b4: f44f 7300 mov.w r3, #512 ; 0x200 80074b8: 2202 movs r2, #2 80074ba: 2181 movs r1, #129 ; 0x81 80074bc: 6878 ldr r0, [r7, #4] 80074be: f002 f84a bl 8009556 CDC_DATA_HS_IN_PACKET_SIZE); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; 80074c2: 687b ldr r3, [r7, #4] 80074c4: 2201 movs r2, #1 80074c6: 871a strh r2, [r3, #56] ; 0x38 /* Open EP OUT */ (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, 80074c8: f44f 7300 mov.w r3, #512 ; 0x200 80074cc: 2202 movs r2, #2 80074ce: 2101 movs r1, #1 80074d0: 6878 ldr r0, [r7, #4] 80074d2: f002 f840 bl 8009556 CDC_DATA_HS_OUT_PACKET_SIZE); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; 80074d6: 687b ldr r3, [r7, #4] 80074d8: 2201 movs r2, #1 80074da: f8a3 2178 strh.w r2, [r3, #376] ; 0x178 /* Set bInterval for CDC CMD Endpoint */ pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_HS_BINTERVAL; 80074de: 687b ldr r3, [r7, #4] 80074e0: 2210 movs r2, #16 80074e2: f8a3 204e strh.w r2, [r3, #78] ; 0x4e 80074e6: e016 b.n 8007516 } else { /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, 80074e8: 2340 movs r3, #64 ; 0x40 80074ea: 2202 movs r2, #2 80074ec: 2181 movs r1, #129 ; 0x81 80074ee: 6878 ldr r0, [r7, #4] 80074f0: f002 f831 bl 8009556 CDC_DATA_FS_IN_PACKET_SIZE); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; 80074f4: 687b ldr r3, [r7, #4] 80074f6: 2201 movs r2, #1 80074f8: 871a strh r2, [r3, #56] ; 0x38 /* Open EP OUT */ (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, 80074fa: 2340 movs r3, #64 ; 0x40 80074fc: 2202 movs r2, #2 80074fe: 2101 movs r1, #1 8007500: 6878 ldr r0, [r7, #4] 8007502: f002 f828 bl 8009556 CDC_DATA_FS_OUT_PACKET_SIZE); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; 8007506: 687b ldr r3, [r7, #4] 8007508: 2201 movs r2, #1 800750a: f8a3 2178 strh.w r2, [r3, #376] ; 0x178 /* Set bInterval for CMD Endpoint */ pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_FS_BINTERVAL; 800750e: 687b ldr r3, [r7, #4] 8007510: 2210 movs r2, #16 8007512: f8a3 204e strh.w r2, [r3, #78] ; 0x4e } /* Open Command IN EP */ (void)USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); 8007516: 2308 movs r3, #8 8007518: 2203 movs r2, #3 800751a: 2182 movs r1, #130 ; 0x82 800751c: 6878 ldr r0, [r7, #4] 800751e: f002 f81a bl 8009556 pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U; 8007522: 687b ldr r3, [r7, #4] 8007524: 2201 movs r2, #1 8007526: f8a3 204c strh.w r2, [r3, #76] ; 0x4c /* Init physical Interface components */ ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); 800752a: 687b ldr r3, [r7, #4] 800752c: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8007530: 681b ldr r3, [r3, #0] 8007532: 4798 blx r3 /* Init Xfer states */ hcdc->TxState = 0U; 8007534: 68fb ldr r3, [r7, #12] 8007536: 2200 movs r2, #0 8007538: f8c3 2214 str.w r2, [r3, #532] ; 0x214 hcdc->RxState = 0U; 800753c: 68fb ldr r3, [r7, #12] 800753e: 2200 movs r2, #0 8007540: f8c3 2218 str.w r2, [r3, #536] ; 0x218 if (pdev->dev_speed == USBD_SPEED_HIGH) 8007544: 687b ldr r3, [r7, #4] 8007546: 7c1b ldrb r3, [r3, #16] 8007548: 2b00 cmp r3, #0 800754a: d109 bne.n 8007560 { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 800754c: 68fb ldr r3, [r7, #12] 800754e: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 8007552: f44f 7300 mov.w r3, #512 ; 0x200 8007556: 2101 movs r1, #1 8007558: 6878 ldr r0, [r7, #4] 800755a: f002 f8eb bl 8009734 800755e: e007 b.n 8007570 CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 8007560: 68fb ldr r3, [r7, #12] 8007562: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 8007566: 2340 movs r3, #64 ; 0x40 8007568: 2101 movs r1, #1 800756a: 6878 ldr r0, [r7, #4] 800756c: f002 f8e2 bl 8009734 CDC_DATA_FS_OUT_PACKET_SIZE); } return (uint8_t)USBD_OK; 8007570: 2300 movs r3, #0 } 8007572: 4618 mov r0, r3 8007574: 3710 adds r7, #16 8007576: 46bd mov sp, r7 8007578: bd80 pop {r7, pc} 0800757a : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 800757a: b580 push {r7, lr} 800757c: b082 sub sp, #8 800757e: af00 add r7, sp, #0 8007580: 6078 str r0, [r7, #4] 8007582: 460b mov r3, r1 8007584: 70fb strb r3, [r7, #3] UNUSED(cfgidx); /* Close EP IN */ (void)USBD_LL_CloseEP(pdev, CDC_IN_EP); 8007586: 2181 movs r1, #129 ; 0x81 8007588: 6878 ldr r0, [r7, #4] 800758a: f002 f80a bl 80095a2 pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U; 800758e: 687b ldr r3, [r7, #4] 8007590: 2200 movs r2, #0 8007592: 871a strh r2, [r3, #56] ; 0x38 /* Close EP OUT */ (void)USBD_LL_CloseEP(pdev, CDC_OUT_EP); 8007594: 2101 movs r1, #1 8007596: 6878 ldr r0, [r7, #4] 8007598: f002 f803 bl 80095a2 pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U; 800759c: 687b ldr r3, [r7, #4] 800759e: 2200 movs r2, #0 80075a0: f8a3 2178 strh.w r2, [r3, #376] ; 0x178 /* Close Command IN EP */ (void)USBD_LL_CloseEP(pdev, CDC_CMD_EP); 80075a4: 2182 movs r1, #130 ; 0x82 80075a6: 6878 ldr r0, [r7, #4] 80075a8: f001 fffb bl 80095a2 pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U; 80075ac: 687b ldr r3, [r7, #4] 80075ae: 2200 movs r2, #0 80075b0: f8a3 204c strh.w r2, [r3, #76] ; 0x4c pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = 0U; 80075b4: 687b ldr r3, [r7, #4] 80075b6: 2200 movs r2, #0 80075b8: f8a3 204e strh.w r2, [r3, #78] ; 0x4e /* DeInit physical Interface components */ if (pdev->pClassData != NULL) 80075bc: 687b ldr r3, [r7, #4] 80075be: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 80075c2: 2b00 cmp r3, #0 80075c4: d00e beq.n 80075e4 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); 80075c6: 687b ldr r3, [r7, #4] 80075c8: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 80075cc: 685b ldr r3, [r3, #4] 80075ce: 4798 blx r3 (void)USBD_free(pdev->pClassData); 80075d0: 687b ldr r3, [r7, #4] 80075d2: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 80075d6: 4618 mov r0, r3 80075d8: f002 f8ee bl 80097b8 pdev->pClassData = NULL; 80075dc: 687b ldr r3, [r7, #4] 80075de: 2200 movs r2, #0 80075e0: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc } return (uint8_t)USBD_OK; 80075e4: 2300 movs r3, #0 } 80075e6: 4618 mov r0, r3 80075e8: 3708 adds r7, #8 80075ea: 46bd mov sp, r7 80075ec: bd80 pop {r7, pc} ... 080075f0 : * @param req: usb requests * @retval status */ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80075f0: b580 push {r7, lr} 80075f2: b086 sub sp, #24 80075f4: af00 add r7, sp, #0 80075f6: 6078 str r0, [r7, #4] 80075f8: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 80075fa: 687b ldr r3, [r7, #4] 80075fc: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007600: 613b str r3, [r7, #16] uint16_t len; uint8_t ifalt = 0U; 8007602: 2300 movs r3, #0 8007604: 737b strb r3, [r7, #13] uint16_t status_info = 0U; 8007606: 2300 movs r3, #0 8007608: 817b strh r3, [r7, #10] USBD_StatusTypeDef ret = USBD_OK; 800760a: 2300 movs r3, #0 800760c: 75fb strb r3, [r7, #23] if (hcdc == NULL) 800760e: 693b ldr r3, [r7, #16] 8007610: 2b00 cmp r3, #0 8007612: d101 bne.n 8007618 { return (uint8_t)USBD_FAIL; 8007614: 2303 movs r3, #3 8007616: e0af b.n 8007778 } switch (req->bmRequest & USB_REQ_TYPE_MASK) 8007618: 683b ldr r3, [r7, #0] 800761a: 781b ldrb r3, [r3, #0] 800761c: f003 0360 and.w r3, r3, #96 ; 0x60 8007620: 2b00 cmp r3, #0 8007622: d03f beq.n 80076a4 8007624: 2b20 cmp r3, #32 8007626: f040 809f bne.w 8007768 { case USB_REQ_TYPE_CLASS: if (req->wLength != 0U) 800762a: 683b ldr r3, [r7, #0] 800762c: 88db ldrh r3, [r3, #6] 800762e: 2b00 cmp r3, #0 8007630: d02e beq.n 8007690 { if ((req->bmRequest & 0x80U) != 0U) 8007632: 683b ldr r3, [r7, #0] 8007634: 781b ldrb r3, [r3, #0] 8007636: b25b sxtb r3, r3 8007638: 2b00 cmp r3, #0 800763a: da16 bge.n 800766a { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 800763c: 687b ldr r3, [r7, #4] 800763e: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8007642: 689b ldr r3, [r3, #8] 8007644: 683a ldr r2, [r7, #0] 8007646: 7850 ldrb r0, [r2, #1] (uint8_t *)hcdc->data, 8007648: 6939 ldr r1, [r7, #16] ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 800764a: 683a ldr r2, [r7, #0] 800764c: 88d2 ldrh r2, [r2, #6] 800764e: 4798 blx r3 req->wLength); len = MIN(CDC_REQ_MAX_DATA_SIZE, req->wLength); 8007650: 683b ldr r3, [r7, #0] 8007652: 88db ldrh r3, [r3, #6] 8007654: 2b07 cmp r3, #7 8007656: bf28 it cs 8007658: 2307 movcs r3, #7 800765a: 81fb strh r3, [r7, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, len); 800765c: 693b ldr r3, [r7, #16] 800765e: 89fa ldrh r2, [r7, #14] 8007660: 4619 mov r1, r3 8007662: 6878 ldr r0, [r7, #4] 8007664: f001 fb19 bl 8008c9a else { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, (uint8_t *)req, 0U); } break; 8007668: e085 b.n 8007776 hcdc->CmdOpCode = req->bRequest; 800766a: 683b ldr r3, [r7, #0] 800766c: 785a ldrb r2, [r3, #1] 800766e: 693b ldr r3, [r7, #16] 8007670: f883 2200 strb.w r2, [r3, #512] ; 0x200 hcdc->CmdLength = (uint8_t)req->wLength; 8007674: 683b ldr r3, [r7, #0] 8007676: 88db ldrh r3, [r3, #6] 8007678: b2da uxtb r2, r3 800767a: 693b ldr r3, [r7, #16] 800767c: f883 2201 strb.w r2, [r3, #513] ; 0x201 (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, req->wLength); 8007680: 6939 ldr r1, [r7, #16] 8007682: 683b ldr r3, [r7, #0] 8007684: 88db ldrh r3, [r3, #6] 8007686: 461a mov r2, r3 8007688: 6878 ldr r0, [r7, #4] 800768a: f001 fb32 bl 8008cf2 break; 800768e: e072 b.n 8007776 ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 8007690: 687b ldr r3, [r7, #4] 8007692: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8007696: 689b ldr r3, [r3, #8] 8007698: 683a ldr r2, [r7, #0] 800769a: 7850 ldrb r0, [r2, #1] 800769c: 2200 movs r2, #0 800769e: 6839 ldr r1, [r7, #0] 80076a0: 4798 blx r3 break; 80076a2: e068 b.n 8007776 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80076a4: 683b ldr r3, [r7, #0] 80076a6: 785b ldrb r3, [r3, #1] 80076a8: 2b0b cmp r3, #11 80076aa: d852 bhi.n 8007752 80076ac: a201 add r2, pc, #4 ; (adr r2, 80076b4 ) 80076ae: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80076b2: bf00 nop 80076b4: 080076e5 .word 0x080076e5 80076b8: 08007761 .word 0x08007761 80076bc: 08007753 .word 0x08007753 80076c0: 08007753 .word 0x08007753 80076c4: 08007753 .word 0x08007753 80076c8: 08007753 .word 0x08007753 80076cc: 08007753 .word 0x08007753 80076d0: 08007753 .word 0x08007753 80076d4: 08007753 .word 0x08007753 80076d8: 08007753 .word 0x08007753 80076dc: 0800770f .word 0x0800770f 80076e0: 08007739 .word 0x08007739 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 80076e4: 687b ldr r3, [r7, #4] 80076e6: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80076ea: b2db uxtb r3, r3 80076ec: 2b03 cmp r3, #3 80076ee: d107 bne.n 8007700 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 80076f0: f107 030a add.w r3, r7, #10 80076f4: 2202 movs r2, #2 80076f6: 4619 mov r1, r3 80076f8: 6878 ldr r0, [r7, #4] 80076fa: f001 face bl 8008c9a else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80076fe: e032 b.n 8007766 USBD_CtlError(pdev, req); 8007700: 6839 ldr r1, [r7, #0] 8007702: 6878 ldr r0, [r7, #4] 8007704: f001 fa58 bl 8008bb8 ret = USBD_FAIL; 8007708: 2303 movs r3, #3 800770a: 75fb strb r3, [r7, #23] break; 800770c: e02b b.n 8007766 case USB_REQ_GET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 800770e: 687b ldr r3, [r7, #4] 8007710: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007714: b2db uxtb r3, r3 8007716: 2b03 cmp r3, #3 8007718: d107 bne.n 800772a { (void)USBD_CtlSendData(pdev, &ifalt, 1U); 800771a: f107 030d add.w r3, r7, #13 800771e: 2201 movs r2, #1 8007720: 4619 mov r1, r3 8007722: 6878 ldr r0, [r7, #4] 8007724: f001 fab9 bl 8008c9a else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8007728: e01d b.n 8007766 USBD_CtlError(pdev, req); 800772a: 6839 ldr r1, [r7, #0] 800772c: 6878 ldr r0, [r7, #4] 800772e: f001 fa43 bl 8008bb8 ret = USBD_FAIL; 8007732: 2303 movs r3, #3 8007734: 75fb strb r3, [r7, #23] break; 8007736: e016 b.n 8007766 case USB_REQ_SET_INTERFACE: if (pdev->dev_state != USBD_STATE_CONFIGURED) 8007738: 687b ldr r3, [r7, #4] 800773a: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 800773e: b2db uxtb r3, r3 8007740: 2b03 cmp r3, #3 8007742: d00f beq.n 8007764 { USBD_CtlError(pdev, req); 8007744: 6839 ldr r1, [r7, #0] 8007746: 6878 ldr r0, [r7, #4] 8007748: f001 fa36 bl 8008bb8 ret = USBD_FAIL; 800774c: 2303 movs r3, #3 800774e: 75fb strb r3, [r7, #23] } break; 8007750: e008 b.n 8007764 case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 8007752: 6839 ldr r1, [r7, #0] 8007754: 6878 ldr r0, [r7, #4] 8007756: f001 fa2f bl 8008bb8 ret = USBD_FAIL; 800775a: 2303 movs r3, #3 800775c: 75fb strb r3, [r7, #23] break; 800775e: e002 b.n 8007766 break; 8007760: bf00 nop 8007762: e008 b.n 8007776 break; 8007764: bf00 nop } break; 8007766: e006 b.n 8007776 default: USBD_CtlError(pdev, req); 8007768: 6839 ldr r1, [r7, #0] 800776a: 6878 ldr r0, [r7, #4] 800776c: f001 fa24 bl 8008bb8 ret = USBD_FAIL; 8007770: 2303 movs r3, #3 8007772: 75fb strb r3, [r7, #23] break; 8007774: bf00 nop } return (uint8_t)ret; 8007776: 7dfb ldrb r3, [r7, #23] } 8007778: 4618 mov r0, r3 800777a: 3718 adds r7, #24 800777c: 46bd mov sp, r7 800777e: bd80 pop {r7, pc} 08007780 : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8007780: b580 push {r7, lr} 8007782: b084 sub sp, #16 8007784: af00 add r7, sp, #0 8007786: 6078 str r0, [r7, #4] 8007788: 460b mov r3, r1 800778a: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc; PCD_HandleTypeDef *hpcd = pdev->pData; 800778c: 687b ldr r3, [r7, #4] 800778e: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8007792: 60fb str r3, [r7, #12] if (pdev->pClassData == NULL) 8007794: 687b ldr r3, [r7, #4] 8007796: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 800779a: 2b00 cmp r3, #0 800779c: d101 bne.n 80077a2 { return (uint8_t)USBD_FAIL; 800779e: 2303 movs r3, #3 80077a0: e04f b.n 8007842 } hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 80077a2: 687b ldr r3, [r7, #4] 80077a4: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 80077a8: 60bb str r3, [r7, #8] if ((pdev->ep_in[epnum].total_length > 0U) && 80077aa: 78fa ldrb r2, [r7, #3] 80077ac: 6879 ldr r1, [r7, #4] 80077ae: 4613 mov r3, r2 80077b0: 009b lsls r3, r3, #2 80077b2: 4413 add r3, r2 80077b4: 009b lsls r3, r3, #2 80077b6: 440b add r3, r1 80077b8: 3318 adds r3, #24 80077ba: 681b ldr r3, [r3, #0] 80077bc: 2b00 cmp r3, #0 80077be: d029 beq.n 8007814 ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U)) 80077c0: 78fa ldrb r2, [r7, #3] 80077c2: 6879 ldr r1, [r7, #4] 80077c4: 4613 mov r3, r2 80077c6: 009b lsls r3, r3, #2 80077c8: 4413 add r3, r2 80077ca: 009b lsls r3, r3, #2 80077cc: 440b add r3, r1 80077ce: 3318 adds r3, #24 80077d0: 681a ldr r2, [r3, #0] 80077d2: 78f9 ldrb r1, [r7, #3] 80077d4: 68f8 ldr r0, [r7, #12] 80077d6: 460b mov r3, r1 80077d8: 00db lsls r3, r3, #3 80077da: 1a5b subs r3, r3, r1 80077dc: 009b lsls r3, r3, #2 80077de: 4403 add r3, r0 80077e0: 3344 adds r3, #68 ; 0x44 80077e2: 681b ldr r3, [r3, #0] 80077e4: fbb2 f1f3 udiv r1, r2, r3 80077e8: fb03 f301 mul.w r3, r3, r1 80077ec: 1ad3 subs r3, r2, r3 if ((pdev->ep_in[epnum].total_length > 0U) && 80077ee: 2b00 cmp r3, #0 80077f0: d110 bne.n 8007814 { /* Update the packet total length */ pdev->ep_in[epnum].total_length = 0U; 80077f2: 78fa ldrb r2, [r7, #3] 80077f4: 6879 ldr r1, [r7, #4] 80077f6: 4613 mov r3, r2 80077f8: 009b lsls r3, r3, #2 80077fa: 4413 add r3, r2 80077fc: 009b lsls r3, r3, #2 80077fe: 440b add r3, r1 8007800: 3318 adds r3, #24 8007802: 2200 movs r2, #0 8007804: 601a str r2, [r3, #0] /* Send ZLP */ (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U); 8007806: 78f9 ldrb r1, [r7, #3] 8007808: 2300 movs r3, #0 800780a: 2200 movs r2, #0 800780c: 6878 ldr r0, [r7, #4] 800780e: f001 ff70 bl 80096f2 8007812: e015 b.n 8007840 } else { hcdc->TxState = 0U; 8007814: 68bb ldr r3, [r7, #8] 8007816: 2200 movs r2, #0 8007818: f8c3 2214 str.w r2, [r3, #532] ; 0x214 if (((USBD_CDC_ItfTypeDef *)pdev->pUserData)->TransmitCplt != NULL) 800781c: 687b ldr r3, [r7, #4] 800781e: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8007822: 691b ldr r3, [r3, #16] 8007824: 2b00 cmp r3, #0 8007826: d00b beq.n 8007840 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum); 8007828: 687b ldr r3, [r7, #4] 800782a: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 800782e: 691b ldr r3, [r3, #16] 8007830: 68ba ldr r2, [r7, #8] 8007832: f8d2 0208 ldr.w r0, [r2, #520] ; 0x208 8007836: 68ba ldr r2, [r7, #8] 8007838: f502 7104 add.w r1, r2, #528 ; 0x210 800783c: 78fa ldrb r2, [r7, #3] 800783e: 4798 blx r3 } } return (uint8_t)USBD_OK; 8007840: 2300 movs r3, #0 } 8007842: 4618 mov r0, r3 8007844: 3710 adds r7, #16 8007846: 46bd mov sp, r7 8007848: bd80 pop {r7, pc} 0800784a : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { 800784a: b580 push {r7, lr} 800784c: b084 sub sp, #16 800784e: af00 add r7, sp, #0 8007850: 6078 str r0, [r7, #4] 8007852: 460b mov r3, r1 8007854: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8007856: 687b ldr r3, [r7, #4] 8007858: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 800785c: 60fb str r3, [r7, #12] if (pdev->pClassData == NULL) 800785e: 687b ldr r3, [r7, #4] 8007860: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007864: 2b00 cmp r3, #0 8007866: d101 bne.n 800786c { return (uint8_t)USBD_FAIL; 8007868: 2303 movs r3, #3 800786a: e015 b.n 8007898 } /* Get the received data length */ hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); 800786c: 78fb ldrb r3, [r7, #3] 800786e: 4619 mov r1, r3 8007870: 6878 ldr r0, [r7, #4] 8007872: f001 ff80 bl 8009776 8007876: 4602 mov r2, r0 8007878: 68fb ldr r3, [r7, #12] 800787a: f8c3 220c str.w r2, [r3, #524] ; 0x20c /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); 800787e: 687b ldr r3, [r7, #4] 8007880: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8007884: 68db ldr r3, [r3, #12] 8007886: 68fa ldr r2, [r7, #12] 8007888: f8d2 0204 ldr.w r0, [r2, #516] ; 0x204 800788c: 68fa ldr r2, [r7, #12] 800788e: f502 7203 add.w r2, r2, #524 ; 0x20c 8007892: 4611 mov r1, r2 8007894: 4798 blx r3 return (uint8_t)USBD_OK; 8007896: 2300 movs r3, #0 } 8007898: 4618 mov r0, r3 800789a: 3710 adds r7, #16 800789c: 46bd mov sp, r7 800789e: bd80 pop {r7, pc} 080078a0 : * Handle EP0 Rx Ready event * @param pdev: device instance * @retval status */ static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) { 80078a0: b580 push {r7, lr} 80078a2: b084 sub sp, #16 80078a4: af00 add r7, sp, #0 80078a6: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 80078a8: 687b ldr r3, [r7, #4] 80078aa: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 80078ae: 60fb str r3, [r7, #12] if (hcdc == NULL) 80078b0: 68fb ldr r3, [r7, #12] 80078b2: 2b00 cmp r3, #0 80078b4: d101 bne.n 80078ba { return (uint8_t)USBD_FAIL; 80078b6: 2303 movs r3, #3 80078b8: e01b b.n 80078f2 } if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU)) 80078ba: 687b ldr r3, [r7, #4] 80078bc: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 80078c0: 2b00 cmp r3, #0 80078c2: d015 beq.n 80078f0 80078c4: 68fb ldr r3, [r7, #12] 80078c6: f893 3200 ldrb.w r3, [r3, #512] ; 0x200 80078ca: 2bff cmp r3, #255 ; 0xff 80078cc: d010 beq.n 80078f0 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, 80078ce: 687b ldr r3, [r7, #4] 80078d0: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 80078d4: 689b ldr r3, [r3, #8] 80078d6: 68fa ldr r2, [r7, #12] 80078d8: f892 0200 ldrb.w r0, [r2, #512] ; 0x200 (uint8_t *)hcdc->data, 80078dc: 68f9 ldr r1, [r7, #12] (uint16_t)hcdc->CmdLength); 80078de: 68fa ldr r2, [r7, #12] 80078e0: f892 2201 ldrb.w r2, [r2, #513] ; 0x201 ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, 80078e4: b292 uxth r2, r2 80078e6: 4798 blx r3 hcdc->CmdOpCode = 0xFFU; 80078e8: 68fb ldr r3, [r7, #12] 80078ea: 22ff movs r2, #255 ; 0xff 80078ec: f883 2200 strb.w r2, [r3, #512] ; 0x200 } return (uint8_t)USBD_OK; 80078f0: 2300 movs r3, #0 } 80078f2: 4618 mov r0, r3 80078f4: 3710 adds r7, #16 80078f6: 46bd mov sp, r7 80078f8: bd80 pop {r7, pc} ... 080078fc : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) { 80078fc: b480 push {r7} 80078fe: b083 sub sp, #12 8007900: af00 add r7, sp, #0 8007902: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_CfgFSDesc); 8007904: 687b ldr r3, [r7, #4] 8007906: 2243 movs r2, #67 ; 0x43 8007908: 801a strh r2, [r3, #0] return USBD_CDC_CfgFSDesc; 800790a: 4b03 ldr r3, [pc, #12] ; (8007918 ) } 800790c: 4618 mov r0, r3 800790e: 370c adds r7, #12 8007910: 46bd mov sp, r7 8007912: f85d 7b04 ldr.w r7, [sp], #4 8007916: 4770 bx lr 8007918: 24000098 .word 0x24000098 0800791c : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) { 800791c: b480 push {r7} 800791e: b083 sub sp, #12 8007920: af00 add r7, sp, #0 8007922: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_CfgHSDesc); 8007924: 687b ldr r3, [r7, #4] 8007926: 2243 movs r2, #67 ; 0x43 8007928: 801a strh r2, [r3, #0] return USBD_CDC_CfgHSDesc; 800792a: 4b03 ldr r3, [pc, #12] ; (8007938 ) } 800792c: 4618 mov r0, r3 800792e: 370c adds r7, #12 8007930: 46bd mov sp, r7 8007932: f85d 7b04 ldr.w r7, [sp], #4 8007936: 4770 bx lr 8007938: 24000054 .word 0x24000054 0800793c : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) { 800793c: b480 push {r7} 800793e: b083 sub sp, #12 8007940: af00 add r7, sp, #0 8007942: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_OtherSpeedCfgDesc); 8007944: 687b ldr r3, [r7, #4] 8007946: 2243 movs r2, #67 ; 0x43 8007948: 801a strh r2, [r3, #0] return USBD_CDC_OtherSpeedCfgDesc; 800794a: 4b03 ldr r3, [pc, #12] ; (8007958 ) } 800794c: 4618 mov r0, r3 800794e: 370c adds r7, #12 8007950: 46bd mov sp, r7 8007952: f85d 7b04 ldr.w r7, [sp], #4 8007956: 4770 bx lr 8007958: 240000dc .word 0x240000dc 0800795c : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) { 800795c: b480 push {r7} 800795e: b083 sub sp, #12 8007960: af00 add r7, sp, #0 8007962: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc); 8007964: 687b ldr r3, [r7, #4] 8007966: 220a movs r2, #10 8007968: 801a strh r2, [r3, #0] return USBD_CDC_DeviceQualifierDesc; 800796a: 4b03 ldr r3, [pc, #12] ; (8007978 ) } 800796c: 4618 mov r0, r3 800796e: 370c adds r7, #12 8007970: 46bd mov sp, r7 8007972: f85d 7b04 ldr.w r7, [sp], #4 8007976: 4770 bx lr 8007978: 24000010 .word 0x24000010 0800797c : * @param fops: CD Interface callback * @retval status */ uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, USBD_CDC_ItfTypeDef *fops) { 800797c: b480 push {r7} 800797e: b083 sub sp, #12 8007980: af00 add r7, sp, #0 8007982: 6078 str r0, [r7, #4] 8007984: 6039 str r1, [r7, #0] if (fops == NULL) 8007986: 683b ldr r3, [r7, #0] 8007988: 2b00 cmp r3, #0 800798a: d101 bne.n 8007990 { return (uint8_t)USBD_FAIL; 800798c: 2303 movs r3, #3 800798e: e004 b.n 800799a } pdev->pUserData = fops; 8007990: 687b ldr r3, [r7, #4] 8007992: 683a ldr r2, [r7, #0] 8007994: f8c3 22c0 str.w r2, [r3, #704] ; 0x2c0 return (uint8_t)USBD_OK; 8007998: 2300 movs r3, #0 } 800799a: 4618 mov r0, r3 800799c: 370c adds r7, #12 800799e: 46bd mov sp, r7 80079a0: f85d 7b04 ldr.w r7, [sp], #4 80079a4: 4770 bx lr 080079a6 : * @param pbuff: Tx Buffer * @retval status */ uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, uint32_t length) { 80079a6: b480 push {r7} 80079a8: b087 sub sp, #28 80079aa: af00 add r7, sp, #0 80079ac: 60f8 str r0, [r7, #12] 80079ae: 60b9 str r1, [r7, #8] 80079b0: 607a str r2, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 80079b2: 68fb ldr r3, [r7, #12] 80079b4: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 80079b8: 617b str r3, [r7, #20] if (hcdc == NULL) 80079ba: 697b ldr r3, [r7, #20] 80079bc: 2b00 cmp r3, #0 80079be: d101 bne.n 80079c4 { return (uint8_t)USBD_FAIL; 80079c0: 2303 movs r3, #3 80079c2: e008 b.n 80079d6 } hcdc->TxBuffer = pbuff; 80079c4: 697b ldr r3, [r7, #20] 80079c6: 68ba ldr r2, [r7, #8] 80079c8: f8c3 2208 str.w r2, [r3, #520] ; 0x208 hcdc->TxLength = length; 80079cc: 697b ldr r3, [r7, #20] 80079ce: 687a ldr r2, [r7, #4] 80079d0: f8c3 2210 str.w r2, [r3, #528] ; 0x210 return (uint8_t)USBD_OK; 80079d4: 2300 movs r3, #0 } 80079d6: 4618 mov r0, r3 80079d8: 371c adds r7, #28 80079da: 46bd mov sp, r7 80079dc: f85d 7b04 ldr.w r7, [sp], #4 80079e0: 4770 bx lr 080079e2 : * @param pdev: device instance * @param pbuff: Rx Buffer * @retval status */ uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) { 80079e2: b480 push {r7} 80079e4: b085 sub sp, #20 80079e6: af00 add r7, sp, #0 80079e8: 6078 str r0, [r7, #4] 80079ea: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 80079ec: 687b ldr r3, [r7, #4] 80079ee: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 80079f2: 60fb str r3, [r7, #12] if (hcdc == NULL) 80079f4: 68fb ldr r3, [r7, #12] 80079f6: 2b00 cmp r3, #0 80079f8: d101 bne.n 80079fe { return (uint8_t)USBD_FAIL; 80079fa: 2303 movs r3, #3 80079fc: e004 b.n 8007a08 } hcdc->RxBuffer = pbuff; 80079fe: 68fb ldr r3, [r7, #12] 8007a00: 683a ldr r2, [r7, #0] 8007a02: f8c3 2204 str.w r2, [r3, #516] ; 0x204 return (uint8_t)USBD_OK; 8007a06: 2300 movs r3, #0 } 8007a08: 4618 mov r0, r3 8007a0a: 3714 adds r7, #20 8007a0c: 46bd mov sp, r7 8007a0e: f85d 7b04 ldr.w r7, [sp], #4 8007a12: 4770 bx lr 08007a14 : * Transmit packet on IN endpoint * @param pdev: device instance * @retval status */ uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) { 8007a14: b580 push {r7, lr} 8007a16: b084 sub sp, #16 8007a18: af00 add r7, sp, #0 8007a1a: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8007a1c: 687b ldr r3, [r7, #4] 8007a1e: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007a22: 60bb str r3, [r7, #8] USBD_StatusTypeDef ret = USBD_BUSY; 8007a24: 2301 movs r3, #1 8007a26: 73fb strb r3, [r7, #15] if (pdev->pClassData == NULL) 8007a28: 687b ldr r3, [r7, #4] 8007a2a: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007a2e: 2b00 cmp r3, #0 8007a30: d101 bne.n 8007a36 { return (uint8_t)USBD_FAIL; 8007a32: 2303 movs r3, #3 8007a34: e01a b.n 8007a6c } if (hcdc->TxState == 0U) 8007a36: 68bb ldr r3, [r7, #8] 8007a38: f8d3 3214 ldr.w r3, [r3, #532] ; 0x214 8007a3c: 2b00 cmp r3, #0 8007a3e: d114 bne.n 8007a6a { /* Tx Transfer in progress */ hcdc->TxState = 1U; 8007a40: 68bb ldr r3, [r7, #8] 8007a42: 2201 movs r2, #1 8007a44: f8c3 2214 str.w r2, [r3, #532] ; 0x214 /* Update the packet total length */ pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength; 8007a48: 68bb ldr r3, [r7, #8] 8007a4a: f8d3 2210 ldr.w r2, [r3, #528] ; 0x210 8007a4e: 687b ldr r3, [r7, #4] 8007a50: 62da str r2, [r3, #44] ; 0x2c /* Transmit next packet */ (void)USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer, hcdc->TxLength); 8007a52: 68bb ldr r3, [r7, #8] 8007a54: f8d3 2208 ldr.w r2, [r3, #520] ; 0x208 8007a58: 68bb ldr r3, [r7, #8] 8007a5a: f8d3 3210 ldr.w r3, [r3, #528] ; 0x210 8007a5e: 2181 movs r1, #129 ; 0x81 8007a60: 6878 ldr r0, [r7, #4] 8007a62: f001 fe46 bl 80096f2 ret = USBD_OK; 8007a66: 2300 movs r3, #0 8007a68: 73fb strb r3, [r7, #15] } return (uint8_t)ret; 8007a6a: 7bfb ldrb r3, [r7, #15] } 8007a6c: 4618 mov r0, r3 8007a6e: 3710 adds r7, #16 8007a70: 46bd mov sp, r7 8007a72: bd80 pop {r7, pc} 08007a74 : * prepare OUT Endpoint for reception * @param pdev: device instance * @retval status */ uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) { 8007a74: b580 push {r7, lr} 8007a76: b084 sub sp, #16 8007a78: af00 add r7, sp, #0 8007a7a: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8007a7c: 687b ldr r3, [r7, #4] 8007a7e: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007a82: 60fb str r3, [r7, #12] if (pdev->pClassData == NULL) 8007a84: 687b ldr r3, [r7, #4] 8007a86: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007a8a: 2b00 cmp r3, #0 8007a8c: d101 bne.n 8007a92 { return (uint8_t)USBD_FAIL; 8007a8e: 2303 movs r3, #3 8007a90: e016 b.n 8007ac0 } if (pdev->dev_speed == USBD_SPEED_HIGH) 8007a92: 687b ldr r3, [r7, #4] 8007a94: 7c1b ldrb r3, [r3, #16] 8007a96: 2b00 cmp r3, #0 8007a98: d109 bne.n 8007aae { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 8007a9a: 68fb ldr r3, [r7, #12] 8007a9c: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 8007aa0: f44f 7300 mov.w r3, #512 ; 0x200 8007aa4: 2101 movs r1, #1 8007aa6: 6878 ldr r0, [r7, #4] 8007aa8: f001 fe44 bl 8009734 8007aac: e007 b.n 8007abe CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 8007aae: 68fb ldr r3, [r7, #12] 8007ab0: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 8007ab4: 2340 movs r3, #64 ; 0x40 8007ab6: 2101 movs r1, #1 8007ab8: 6878 ldr r0, [r7, #4] 8007aba: f001 fe3b bl 8009734 CDC_DATA_FS_OUT_PACKET_SIZE); } return (uint8_t)USBD_OK; 8007abe: 2300 movs r3, #0 } 8007ac0: 4618 mov r0, r3 8007ac2: 3710 adds r7, #16 8007ac4: 46bd mov sp, r7 8007ac6: bd80 pop {r7, pc} 08007ac8 : * @param id: Low level core index * @retval None */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 8007ac8: b580 push {r7, lr} 8007aca: b086 sub sp, #24 8007acc: af00 add r7, sp, #0 8007ace: 60f8 str r0, [r7, #12] 8007ad0: 60b9 str r1, [r7, #8] 8007ad2: 4613 mov r3, r2 8007ad4: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 8007ad6: 68fb ldr r3, [r7, #12] 8007ad8: 2b00 cmp r3, #0 8007ada: d101 bne.n 8007ae0 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif return USBD_FAIL; 8007adc: 2303 movs r3, #3 8007ade: e01f b.n 8007b20 } /* Unlink previous class resources */ pdev->pClass = NULL; 8007ae0: 68fb ldr r3, [r7, #12] 8007ae2: 2200 movs r2, #0 8007ae4: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 pdev->pUserData = NULL; 8007ae8: 68fb ldr r3, [r7, #12] 8007aea: 2200 movs r2, #0 8007aec: f8c3 22c0 str.w r2, [r3, #704] ; 0x2c0 pdev->pConfDesc = NULL; 8007af0: 68fb ldr r3, [r7, #12] 8007af2: 2200 movs r2, #0 8007af4: f8c3 22cc str.w r2, [r3, #716] ; 0x2cc /* Assign USBD Descriptors */ if (pdesc != NULL) 8007af8: 68bb ldr r3, [r7, #8] 8007afa: 2b00 cmp r3, #0 8007afc: d003 beq.n 8007b06 { pdev->pDesc = pdesc; 8007afe: 68fb ldr r3, [r7, #12] 8007b00: 68ba ldr r2, [r7, #8] 8007b02: f8c3 22b4 str.w r2, [r3, #692] ; 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 8007b06: 68fb ldr r3, [r7, #12] 8007b08: 2201 movs r2, #1 8007b0a: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->id = id; 8007b0e: 68fb ldr r3, [r7, #12] 8007b10: 79fa ldrb r2, [r7, #7] 8007b12: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 8007b14: 68f8 ldr r0, [r7, #12] 8007b16: f001 fcad bl 8009474 8007b1a: 4603 mov r3, r0 8007b1c: 75fb strb r3, [r7, #23] return ret; 8007b1e: 7dfb ldrb r3, [r7, #23] } 8007b20: 4618 mov r0, r3 8007b22: 3718 adds r7, #24 8007b24: 46bd mov sp, r7 8007b26: bd80 pop {r7, pc} 08007b28 : * @param pDevice : Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 8007b28: b580 push {r7, lr} 8007b2a: b084 sub sp, #16 8007b2c: af00 add r7, sp, #0 8007b2e: 6078 str r0, [r7, #4] 8007b30: 6039 str r1, [r7, #0] uint16_t len = 0U; 8007b32: 2300 movs r3, #0 8007b34: 81fb strh r3, [r7, #14] if (pclass == NULL) 8007b36: 683b ldr r3, [r7, #0] 8007b38: 2b00 cmp r3, #0 8007b3a: d101 bne.n 8007b40 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif return USBD_FAIL; 8007b3c: 2303 movs r3, #3 8007b3e: e016 b.n 8007b6e } /* link the class to the USB Device handle */ pdev->pClass = pclass; 8007b40: 687b ldr r3, [r7, #4] 8007b42: 683a ldr r2, [r7, #0] 8007b44: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 if (pdev->pClass->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass->GetFSConfigDescriptor != NULL) 8007b48: 687b ldr r3, [r7, #4] 8007b4a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007b4e: 6adb ldr r3, [r3, #44] ; 0x2c 8007b50: 2b00 cmp r3, #0 8007b52: d00b beq.n 8007b6c { pdev->pConfDesc = (void *)pdev->pClass->GetFSConfigDescriptor(&len); 8007b54: 687b ldr r3, [r7, #4] 8007b56: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007b5a: 6adb ldr r3, [r3, #44] ; 0x2c 8007b5c: f107 020e add.w r2, r7, #14 8007b60: 4610 mov r0, r2 8007b62: 4798 blx r3 8007b64: 4602 mov r2, r0 8007b66: 687b ldr r3, [r7, #4] 8007b68: f8c3 22cc str.w r2, [r3, #716] ; 0x2cc } #endif /* USE_USB_FS */ return USBD_OK; 8007b6c: 2300 movs r3, #0 } 8007b6e: 4618 mov r0, r3 8007b70: 3710 adds r7, #16 8007b72: 46bd mov sp, r7 8007b74: bd80 pop {r7, pc} 08007b76 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8007b76: b580 push {r7, lr} 8007b78: b082 sub sp, #8 8007b7a: af00 add r7, sp, #0 8007b7c: 6078 str r0, [r7, #4] /* Start the low level driver */ return USBD_LL_Start(pdev); 8007b7e: 6878 ldr r0, [r7, #4] 8007b80: f001 fcce bl 8009520 8007b84: 4603 mov r3, r0 } 8007b86: 4618 mov r0, r3 8007b88: 3708 adds r7, #8 8007b8a: 46bd mov sp, r7 8007b8c: bd80 pop {r7, pc} 08007b8e : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 8007b8e: b480 push {r7} 8007b90: b083 sub sp, #12 8007b92: af00 add r7, sp, #0 8007b94: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8007b96: 2300 movs r3, #0 } 8007b98: 4618 mov r0, r3 8007b9a: 370c adds r7, #12 8007b9c: 46bd mov sp, r7 8007b9e: f85d 7b04 ldr.w r7, [sp], #4 8007ba2: 4770 bx lr 08007ba4 : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8007ba4: b580 push {r7, lr} 8007ba6: b084 sub sp, #16 8007ba8: af00 add r7, sp, #0 8007baa: 6078 str r0, [r7, #4] 8007bac: 460b mov r3, r1 8007bae: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_FAIL; 8007bb0: 2303 movs r3, #3 8007bb2: 73fb strb r3, [r7, #15] if (pdev->pClass != NULL) 8007bb4: 687b ldr r3, [r7, #4] 8007bb6: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007bba: 2b00 cmp r3, #0 8007bbc: d009 beq.n 8007bd2 { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass->Init(pdev, cfgidx); 8007bbe: 687b ldr r3, [r7, #4] 8007bc0: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007bc4: 681b ldr r3, [r3, #0] 8007bc6: 78fa ldrb r2, [r7, #3] 8007bc8: 4611 mov r1, r2 8007bca: 6878 ldr r0, [r7, #4] 8007bcc: 4798 blx r3 8007bce: 4603 mov r3, r0 8007bd0: 73fb strb r3, [r7, #15] } return ret; 8007bd2: 7bfb ldrb r3, [r7, #15] } 8007bd4: 4618 mov r0, r3 8007bd6: 3710 adds r7, #16 8007bd8: 46bd mov sp, r7 8007bda: bd80 pop {r7, pc} 08007bdc : * @param pdev: device instance * @param cfgidx: configuration index * @retval status: USBD_StatusTypeDef */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8007bdc: b580 push {r7, lr} 8007bde: b082 sub sp, #8 8007be0: af00 add r7, sp, #0 8007be2: 6078 str r0, [r7, #4] 8007be4: 460b mov r3, r1 8007be6: 70fb strb r3, [r7, #3] /* Clear configuration and De-initialize the Class process */ if (pdev->pClass != NULL) 8007be8: 687b ldr r3, [r7, #4] 8007bea: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007bee: 2b00 cmp r3, #0 8007bf0: d007 beq.n 8007c02 { pdev->pClass->DeInit(pdev, cfgidx); 8007bf2: 687b ldr r3, [r7, #4] 8007bf4: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007bf8: 685b ldr r3, [r3, #4] 8007bfa: 78fa ldrb r2, [r7, #3] 8007bfc: 4611 mov r1, r2 8007bfe: 6878 ldr r0, [r7, #4] 8007c00: 4798 blx r3 } return USBD_OK; 8007c02: 2300 movs r3, #0 } 8007c04: 4618 mov r0, r3 8007c06: 3708 adds r7, #8 8007c08: 46bd mov sp, r7 8007c0a: bd80 pop {r7, pc} 08007c0c : * Handle the setup stage * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 8007c0c: b580 push {r7, lr} 8007c0e: b084 sub sp, #16 8007c10: af00 add r7, sp, #0 8007c12: 6078 str r0, [r7, #4] 8007c14: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 8007c16: 687b ldr r3, [r7, #4] 8007c18: f203 23aa addw r3, r3, #682 ; 0x2aa 8007c1c: 6839 ldr r1, [r7, #0] 8007c1e: 4618 mov r0, r3 8007c20: f000 ff90 bl 8008b44 pdev->ep0_state = USBD_EP0_SETUP; 8007c24: 687b ldr r3, [r7, #4] 8007c26: 2201 movs r2, #1 8007c28: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->ep0_data_len = pdev->request.wLength; 8007c2c: 687b ldr r3, [r7, #4] 8007c2e: f8b3 32b0 ldrh.w r3, [r3, #688] ; 0x2b0 8007c32: 461a mov r2, r3 8007c34: 687b ldr r3, [r7, #4] 8007c36: f8c3 2298 str.w r2, [r3, #664] ; 0x298 switch (pdev->request.bmRequest & 0x1FU) 8007c3a: 687b ldr r3, [r7, #4] 8007c3c: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa 8007c40: f003 031f and.w r3, r3, #31 8007c44: 2b02 cmp r3, #2 8007c46: d01a beq.n 8007c7e 8007c48: 2b02 cmp r3, #2 8007c4a: d822 bhi.n 8007c92 8007c4c: 2b00 cmp r3, #0 8007c4e: d002 beq.n 8007c56 8007c50: 2b01 cmp r3, #1 8007c52: d00a beq.n 8007c6a 8007c54: e01d b.n 8007c92 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 8007c56: 687b ldr r3, [r7, #4] 8007c58: f203 23aa addw r3, r3, #682 ; 0x2aa 8007c5c: 4619 mov r1, r3 8007c5e: 6878 ldr r0, [r7, #4] 8007c60: f000 fa62 bl 8008128 8007c64: 4603 mov r3, r0 8007c66: 73fb strb r3, [r7, #15] break; 8007c68: e020 b.n 8007cac case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 8007c6a: 687b ldr r3, [r7, #4] 8007c6c: f203 23aa addw r3, r3, #682 ; 0x2aa 8007c70: 4619 mov r1, r3 8007c72: 6878 ldr r0, [r7, #4] 8007c74: f000 fac6 bl 8008204 8007c78: 4603 mov r3, r0 8007c7a: 73fb strb r3, [r7, #15] break; 8007c7c: e016 b.n 8007cac case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8007c7e: 687b ldr r3, [r7, #4] 8007c80: f203 23aa addw r3, r3, #682 ; 0x2aa 8007c84: 4619 mov r1, r3 8007c86: 6878 ldr r0, [r7, #4] 8007c88: f000 fb05 bl 8008296 8007c8c: 4603 mov r3, r0 8007c8e: 73fb strb r3, [r7, #15] break; 8007c90: e00c b.n 8007cac default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8007c92: 687b ldr r3, [r7, #4] 8007c94: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa 8007c98: f023 037f bic.w r3, r3, #127 ; 0x7f 8007c9c: b2db uxtb r3, r3 8007c9e: 4619 mov r1, r3 8007ca0: 6878 ldr r0, [r7, #4] 8007ca2: f001 fc9d bl 80095e0 8007ca6: 4603 mov r3, r0 8007ca8: 73fb strb r3, [r7, #15] break; 8007caa: bf00 nop } return ret; 8007cac: 7bfb ldrb r3, [r7, #15] } 8007cae: 4618 mov r0, r3 8007cb0: 3710 adds r7, #16 8007cb2: 46bd mov sp, r7 8007cb4: bd80 pop {r7, pc} 08007cb6 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8007cb6: b580 push {r7, lr} 8007cb8: b086 sub sp, #24 8007cba: af00 add r7, sp, #0 8007cbc: 60f8 str r0, [r7, #12] 8007cbe: 460b mov r3, r1 8007cc0: 607a str r2, [r7, #4] 8007cc2: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret; if (epnum == 0U) 8007cc4: 7afb ldrb r3, [r7, #11] 8007cc6: 2b00 cmp r3, #0 8007cc8: d138 bne.n 8007d3c { pep = &pdev->ep_out[0]; 8007cca: 68fb ldr r3, [r7, #12] 8007ccc: f503 73aa add.w r3, r3, #340 ; 0x154 8007cd0: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 8007cd2: 68fb ldr r3, [r7, #12] 8007cd4: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 8007cd8: 2b03 cmp r3, #3 8007cda: d14a bne.n 8007d72 { if (pep->rem_length > pep->maxpacket) 8007cdc: 693b ldr r3, [r7, #16] 8007cde: 689a ldr r2, [r3, #8] 8007ce0: 693b ldr r3, [r7, #16] 8007ce2: 68db ldr r3, [r3, #12] 8007ce4: 429a cmp r2, r3 8007ce6: d913 bls.n 8007d10 { pep->rem_length -= pep->maxpacket; 8007ce8: 693b ldr r3, [r7, #16] 8007cea: 689a ldr r2, [r3, #8] 8007cec: 693b ldr r3, [r7, #16] 8007cee: 68db ldr r3, [r3, #12] 8007cf0: 1ad2 subs r2, r2, r3 8007cf2: 693b ldr r3, [r7, #16] 8007cf4: 609a str r2, [r3, #8] (void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket)); 8007cf6: 693b ldr r3, [r7, #16] 8007cf8: 68da ldr r2, [r3, #12] 8007cfa: 693b ldr r3, [r7, #16] 8007cfc: 689b ldr r3, [r3, #8] 8007cfe: 4293 cmp r3, r2 8007d00: bf28 it cs 8007d02: 4613 movcs r3, r2 8007d04: 461a mov r2, r3 8007d06: 6879 ldr r1, [r7, #4] 8007d08: 68f8 ldr r0, [r7, #12] 8007d0a: f001 f80f bl 8008d2c 8007d0e: e030 b.n 8007d72 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007d10: 68fb ldr r3, [r7, #12] 8007d12: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007d16: b2db uxtb r3, r3 8007d18: 2b03 cmp r3, #3 8007d1a: d10b bne.n 8007d34 { if (pdev->pClass->EP0_RxReady != NULL) 8007d1c: 68fb ldr r3, [r7, #12] 8007d1e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007d22: 691b ldr r3, [r3, #16] 8007d24: 2b00 cmp r3, #0 8007d26: d005 beq.n 8007d34 { pdev->pClass->EP0_RxReady(pdev); 8007d28: 68fb ldr r3, [r7, #12] 8007d2a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007d2e: 691b ldr r3, [r3, #16] 8007d30: 68f8 ldr r0, [r7, #12] 8007d32: 4798 blx r3 } } (void)USBD_CtlSendStatus(pdev); 8007d34: 68f8 ldr r0, [r7, #12] 8007d36: f001 f80a bl 8008d4e 8007d3a: e01a b.n 8007d72 #endif } } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007d3c: 68fb ldr r3, [r7, #12] 8007d3e: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007d42: b2db uxtb r3, r3 8007d44: 2b03 cmp r3, #3 8007d46: d114 bne.n 8007d72 { if (pdev->pClass->DataOut != NULL) 8007d48: 68fb ldr r3, [r7, #12] 8007d4a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007d4e: 699b ldr r3, [r3, #24] 8007d50: 2b00 cmp r3, #0 8007d52: d00e beq.n 8007d72 { ret = (USBD_StatusTypeDef)pdev->pClass->DataOut(pdev, epnum); 8007d54: 68fb ldr r3, [r7, #12] 8007d56: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007d5a: 699b ldr r3, [r3, #24] 8007d5c: 7afa ldrb r2, [r7, #11] 8007d5e: 4611 mov r1, r2 8007d60: 68f8 ldr r0, [r7, #12] 8007d62: 4798 blx r3 8007d64: 4603 mov r3, r0 8007d66: 75fb strb r3, [r7, #23] if (ret != USBD_OK) 8007d68: 7dfb ldrb r3, [r7, #23] 8007d6a: 2b00 cmp r3, #0 8007d6c: d001 beq.n 8007d72 { return ret; 8007d6e: 7dfb ldrb r3, [r7, #23] 8007d70: e000 b.n 8007d74 } } } } return USBD_OK; 8007d72: 2300 movs r3, #0 } 8007d74: 4618 mov r0, r3 8007d76: 3718 adds r7, #24 8007d78: 46bd mov sp, r7 8007d7a: bd80 pop {r7, pc} 08007d7c : * @param epnum: endpoint index * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8007d7c: b580 push {r7, lr} 8007d7e: b086 sub sp, #24 8007d80: af00 add r7, sp, #0 8007d82: 60f8 str r0, [r7, #12] 8007d84: 460b mov r3, r1 8007d86: 607a str r2, [r7, #4] 8007d88: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret; if (epnum == 0U) 8007d8a: 7afb ldrb r3, [r7, #11] 8007d8c: 2b00 cmp r3, #0 8007d8e: d16b bne.n 8007e68 { pep = &pdev->ep_in[0]; 8007d90: 68fb ldr r3, [r7, #12] 8007d92: 3314 adds r3, #20 8007d94: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 8007d96: 68fb ldr r3, [r7, #12] 8007d98: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 8007d9c: 2b02 cmp r3, #2 8007d9e: d156 bne.n 8007e4e { if (pep->rem_length > pep->maxpacket) 8007da0: 693b ldr r3, [r7, #16] 8007da2: 689a ldr r2, [r3, #8] 8007da4: 693b ldr r3, [r7, #16] 8007da6: 68db ldr r3, [r3, #12] 8007da8: 429a cmp r2, r3 8007daa: d914 bls.n 8007dd6 { pep->rem_length -= pep->maxpacket; 8007dac: 693b ldr r3, [r7, #16] 8007dae: 689a ldr r2, [r3, #8] 8007db0: 693b ldr r3, [r7, #16] 8007db2: 68db ldr r3, [r3, #12] 8007db4: 1ad2 subs r2, r2, r3 8007db6: 693b ldr r3, [r7, #16] 8007db8: 609a str r2, [r3, #8] (void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length); 8007dba: 693b ldr r3, [r7, #16] 8007dbc: 689b ldr r3, [r3, #8] 8007dbe: 461a mov r2, r3 8007dc0: 6879 ldr r1, [r7, #4] 8007dc2: 68f8 ldr r0, [r7, #12] 8007dc4: f000 ff84 bl 8008cd0 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8007dc8: 2300 movs r3, #0 8007dca: 2200 movs r2, #0 8007dcc: 2100 movs r1, #0 8007dce: 68f8 ldr r0, [r7, #12] 8007dd0: f001 fcb0 bl 8009734 8007dd4: e03b b.n 8007e4e } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 8007dd6: 693b ldr r3, [r7, #16] 8007dd8: 68da ldr r2, [r3, #12] 8007dda: 693b ldr r3, [r7, #16] 8007ddc: 689b ldr r3, [r3, #8] 8007dde: 429a cmp r2, r3 8007de0: d11c bne.n 8007e1c (pep->total_length >= pep->maxpacket) && 8007de2: 693b ldr r3, [r7, #16] 8007de4: 685a ldr r2, [r3, #4] 8007de6: 693b ldr r3, [r7, #16] 8007de8: 68db ldr r3, [r3, #12] if ((pep->maxpacket == pep->rem_length) && 8007dea: 429a cmp r2, r3 8007dec: d316 bcc.n 8007e1c (pep->total_length < pdev->ep0_data_len)) 8007dee: 693b ldr r3, [r7, #16] 8007df0: 685a ldr r2, [r3, #4] 8007df2: 68fb ldr r3, [r7, #12] 8007df4: f8d3 3298 ldr.w r3, [r3, #664] ; 0x298 (pep->total_length >= pep->maxpacket) && 8007df8: 429a cmp r2, r3 8007dfa: d20f bcs.n 8007e1c { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 8007dfc: 2200 movs r2, #0 8007dfe: 2100 movs r1, #0 8007e00: 68f8 ldr r0, [r7, #12] 8007e02: f000 ff65 bl 8008cd0 pdev->ep0_data_len = 0U; 8007e06: 68fb ldr r3, [r7, #12] 8007e08: 2200 movs r2, #0 8007e0a: f8c3 2298 str.w r2, [r3, #664] ; 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8007e0e: 2300 movs r3, #0 8007e10: 2200 movs r2, #0 8007e12: 2100 movs r1, #0 8007e14: 68f8 ldr r0, [r7, #12] 8007e16: f001 fc8d bl 8009734 8007e1a: e018 b.n 8007e4e } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007e1c: 68fb ldr r3, [r7, #12] 8007e1e: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007e22: b2db uxtb r3, r3 8007e24: 2b03 cmp r3, #3 8007e26: d10b bne.n 8007e40 { if (pdev->pClass->EP0_TxSent != NULL) 8007e28: 68fb ldr r3, [r7, #12] 8007e2a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007e2e: 68db ldr r3, [r3, #12] 8007e30: 2b00 cmp r3, #0 8007e32: d005 beq.n 8007e40 { pdev->pClass->EP0_TxSent(pdev); 8007e34: 68fb ldr r3, [r7, #12] 8007e36: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007e3a: 68db ldr r3, [r3, #12] 8007e3c: 68f8 ldr r0, [r7, #12] 8007e3e: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 8007e40: 2180 movs r1, #128 ; 0x80 8007e42: 68f8 ldr r0, [r7, #12] 8007e44: f001 fbcc bl 80095e0 (void)USBD_CtlReceiveStatus(pdev); 8007e48: 68f8 ldr r0, [r7, #12] 8007e4a: f000 ff93 bl 8008d74 (void)USBD_LL_StallEP(pdev, 0x80U); } #endif } if (pdev->dev_test_mode == 1U) 8007e4e: 68fb ldr r3, [r7, #12] 8007e50: f893 32a0 ldrb.w r3, [r3, #672] ; 0x2a0 8007e54: 2b01 cmp r3, #1 8007e56: d122 bne.n 8007e9e { (void)USBD_RunTestMode(pdev); 8007e58: 68f8 ldr r0, [r7, #12] 8007e5a: f7ff fe98 bl 8007b8e pdev->dev_test_mode = 0U; 8007e5e: 68fb ldr r3, [r7, #12] 8007e60: 2200 movs r2, #0 8007e62: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0 8007e66: e01a b.n 8007e9e } } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007e68: 68fb ldr r3, [r7, #12] 8007e6a: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007e6e: b2db uxtb r3, r3 8007e70: 2b03 cmp r3, #3 8007e72: d114 bne.n 8007e9e { if (pdev->pClass->DataIn != NULL) 8007e74: 68fb ldr r3, [r7, #12] 8007e76: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007e7a: 695b ldr r3, [r3, #20] 8007e7c: 2b00 cmp r3, #0 8007e7e: d00e beq.n 8007e9e { ret = (USBD_StatusTypeDef)pdev->pClass->DataIn(pdev, epnum); 8007e80: 68fb ldr r3, [r7, #12] 8007e82: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007e86: 695b ldr r3, [r3, #20] 8007e88: 7afa ldrb r2, [r7, #11] 8007e8a: 4611 mov r1, r2 8007e8c: 68f8 ldr r0, [r7, #12] 8007e8e: 4798 blx r3 8007e90: 4603 mov r3, r0 8007e92: 75fb strb r3, [r7, #23] if (ret != USBD_OK) 8007e94: 7dfb ldrb r3, [r7, #23] 8007e96: 2b00 cmp r3, #0 8007e98: d001 beq.n 8007e9e { return ret; 8007e9a: 7dfb ldrb r3, [r7, #23] 8007e9c: e000 b.n 8007ea0 } } } } return USBD_OK; 8007e9e: 2300 movs r3, #0 } 8007ea0: 4618 mov r0, r3 8007ea2: 3718 adds r7, #24 8007ea4: 46bd mov sp, r7 8007ea6: bd80 pop {r7, pc} 08007ea8 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 8007ea8: b580 push {r7, lr} 8007eaa: b082 sub sp, #8 8007eac: af00 add r7, sp, #0 8007eae: 6078 str r0, [r7, #4] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 8007eb0: 687b ldr r3, [r7, #4] 8007eb2: 2201 movs r2, #1 8007eb4: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->ep0_state = USBD_EP0_IDLE; 8007eb8: 687b ldr r3, [r7, #4] 8007eba: 2200 movs r2, #0 8007ebc: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->dev_config = 0U; 8007ec0: 687b ldr r3, [r7, #4] 8007ec2: 2200 movs r2, #0 8007ec4: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 8007ec6: 687b ldr r3, [r7, #4] 8007ec8: 2200 movs r2, #0 8007eca: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 if (pdev->pClass == NULL) 8007ece: 687b ldr r3, [r7, #4] 8007ed0: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007ed4: 2b00 cmp r3, #0 8007ed6: d101 bne.n 8007edc { return USBD_FAIL; 8007ed8: 2303 movs r3, #3 8007eda: e02f b.n 8007f3c } if (pdev->pClassData != NULL) 8007edc: 687b ldr r3, [r7, #4] 8007ede: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007ee2: 2b00 cmp r3, #0 8007ee4: d00f beq.n 8007f06 { if (pdev->pClass->DeInit != NULL) 8007ee6: 687b ldr r3, [r7, #4] 8007ee8: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007eec: 685b ldr r3, [r3, #4] 8007eee: 2b00 cmp r3, #0 8007ef0: d009 beq.n 8007f06 { (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); 8007ef2: 687b ldr r3, [r7, #4] 8007ef4: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007ef8: 685b ldr r3, [r3, #4] 8007efa: 687a ldr r2, [r7, #4] 8007efc: 6852 ldr r2, [r2, #4] 8007efe: b2d2 uxtb r2, r2 8007f00: 4611 mov r1, r2 8007f02: 6878 ldr r0, [r7, #4] 8007f04: 4798 blx r3 } } /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8007f06: 2340 movs r3, #64 ; 0x40 8007f08: 2200 movs r2, #0 8007f0a: 2100 movs r1, #0 8007f0c: 6878 ldr r0, [r7, #4] 8007f0e: f001 fb22 bl 8009556 pdev->ep_out[0x00U & 0xFU].is_used = 1U; 8007f12: 687b ldr r3, [r7, #4] 8007f14: 2201 movs r2, #1 8007f16: f8a3 2164 strh.w r2, [r3, #356] ; 0x164 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 8007f1a: 687b ldr r3, [r7, #4] 8007f1c: 2240 movs r2, #64 ; 0x40 8007f1e: f8c3 2160 str.w r2, [r3, #352] ; 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8007f22: 2340 movs r3, #64 ; 0x40 8007f24: 2200 movs r2, #0 8007f26: 2180 movs r1, #128 ; 0x80 8007f28: 6878 ldr r0, [r7, #4] 8007f2a: f001 fb14 bl 8009556 pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8007f2e: 687b ldr r3, [r7, #4] 8007f30: 2201 movs r2, #1 8007f32: 849a strh r2, [r3, #36] ; 0x24 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8007f34: 687b ldr r3, [r7, #4] 8007f36: 2240 movs r2, #64 ; 0x40 8007f38: 621a str r2, [r3, #32] return USBD_OK; 8007f3a: 2300 movs r3, #0 } 8007f3c: 4618 mov r0, r3 8007f3e: 3708 adds r7, #8 8007f40: 46bd mov sp, r7 8007f42: bd80 pop {r7, pc} 08007f44 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8007f44: b480 push {r7} 8007f46: b083 sub sp, #12 8007f48: af00 add r7, sp, #0 8007f4a: 6078 str r0, [r7, #4] 8007f4c: 460b mov r3, r1 8007f4e: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 8007f50: 687b ldr r3, [r7, #4] 8007f52: 78fa ldrb r2, [r7, #3] 8007f54: 741a strb r2, [r3, #16] return USBD_OK; 8007f56: 2300 movs r3, #0 } 8007f58: 4618 mov r0, r3 8007f5a: 370c adds r7, #12 8007f5c: 46bd mov sp, r7 8007f5e: f85d 7b04 ldr.w r7, [sp], #4 8007f62: 4770 bx lr 08007f64 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 8007f64: b480 push {r7} 8007f66: b083 sub sp, #12 8007f68: af00 add r7, sp, #0 8007f6a: 6078 str r0, [r7, #4] pdev->dev_old_state = pdev->dev_state; 8007f6c: 687b ldr r3, [r7, #4] 8007f6e: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007f72: b2da uxtb r2, r3 8007f74: 687b ldr r3, [r7, #4] 8007f76: f883 229d strb.w r2, [r3, #669] ; 0x29d pdev->dev_state = USBD_STATE_SUSPENDED; 8007f7a: 687b ldr r3, [r7, #4] 8007f7c: 2204 movs r2, #4 8007f7e: f883 229c strb.w r2, [r3, #668] ; 0x29c return USBD_OK; 8007f82: 2300 movs r3, #0 } 8007f84: 4618 mov r0, r3 8007f86: 370c adds r7, #12 8007f88: 46bd mov sp, r7 8007f8a: f85d 7b04 ldr.w r7, [sp], #4 8007f8e: 4770 bx lr 08007f90 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 8007f90: b480 push {r7} 8007f92: b083 sub sp, #12 8007f94: af00 add r7, sp, #0 8007f96: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 8007f98: 687b ldr r3, [r7, #4] 8007f9a: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007f9e: b2db uxtb r3, r3 8007fa0: 2b04 cmp r3, #4 8007fa2: d106 bne.n 8007fb2 { pdev->dev_state = pdev->dev_old_state; 8007fa4: 687b ldr r3, [r7, #4] 8007fa6: f893 329d ldrb.w r3, [r3, #669] ; 0x29d 8007faa: b2da uxtb r2, r3 8007fac: 687b ldr r3, [r7, #4] 8007fae: f883 229c strb.w r2, [r3, #668] ; 0x29c } return USBD_OK; 8007fb2: 2300 movs r3, #0 } 8007fb4: 4618 mov r0, r3 8007fb6: 370c adds r7, #12 8007fb8: 46bd mov sp, r7 8007fba: f85d 7b04 ldr.w r7, [sp], #4 8007fbe: 4770 bx lr 08007fc0 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 8007fc0: b580 push {r7, lr} 8007fc2: b082 sub sp, #8 8007fc4: af00 add r7, sp, #0 8007fc6: 6078 str r0, [r7, #4] if (pdev->pClass == NULL) 8007fc8: 687b ldr r3, [r7, #4] 8007fca: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007fce: 2b00 cmp r3, #0 8007fd0: d101 bne.n 8007fd6 { return USBD_FAIL; 8007fd2: 2303 movs r3, #3 8007fd4: e012 b.n 8007ffc } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007fd6: 687b ldr r3, [r7, #4] 8007fd8: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007fdc: b2db uxtb r3, r3 8007fde: 2b03 cmp r3, #3 8007fe0: d10b bne.n 8007ffa { if (pdev->pClass->SOF != NULL) 8007fe2: 687b ldr r3, [r7, #4] 8007fe4: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007fe8: 69db ldr r3, [r3, #28] 8007fea: 2b00 cmp r3, #0 8007fec: d005 beq.n 8007ffa { (void)pdev->pClass->SOF(pdev); 8007fee: 687b ldr r3, [r7, #4] 8007ff0: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007ff4: 69db ldr r3, [r3, #28] 8007ff6: 6878 ldr r0, [r7, #4] 8007ff8: 4798 blx r3 } } return USBD_OK; 8007ffa: 2300 movs r3, #0 } 8007ffc: 4618 mov r0, r3 8007ffe: 3708 adds r7, #8 8008000: 46bd mov sp, r7 8008002: bd80 pop {r7, pc} 08008004 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8008004: b580 push {r7, lr} 8008006: b082 sub sp, #8 8008008: af00 add r7, sp, #0 800800a: 6078 str r0, [r7, #4] 800800c: 460b mov r3, r1 800800e: 70fb strb r3, [r7, #3] if (pdev->pClass == NULL) 8008010: 687b ldr r3, [r7, #4] 8008012: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008016: 2b00 cmp r3, #0 8008018: d101 bne.n 800801e { return USBD_FAIL; 800801a: 2303 movs r3, #3 800801c: e014 b.n 8008048 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 800801e: 687b ldr r3, [r7, #4] 8008020: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008024: b2db uxtb r3, r3 8008026: 2b03 cmp r3, #3 8008028: d10d bne.n 8008046 { if (pdev->pClass->IsoINIncomplete != NULL) 800802a: 687b ldr r3, [r7, #4] 800802c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008030: 6a1b ldr r3, [r3, #32] 8008032: 2b00 cmp r3, #0 8008034: d007 beq.n 8008046 { (void)pdev->pClass->IsoINIncomplete(pdev, epnum); 8008036: 687b ldr r3, [r7, #4] 8008038: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800803c: 6a1b ldr r3, [r3, #32] 800803e: 78fa ldrb r2, [r7, #3] 8008040: 4611 mov r1, r2 8008042: 6878 ldr r0, [r7, #4] 8008044: 4798 blx r3 } } return USBD_OK; 8008046: 2300 movs r3, #0 } 8008048: 4618 mov r0, r3 800804a: 3708 adds r7, #8 800804c: 46bd mov sp, r7 800804e: bd80 pop {r7, pc} 08008050 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8008050: b580 push {r7, lr} 8008052: b082 sub sp, #8 8008054: af00 add r7, sp, #0 8008056: 6078 str r0, [r7, #4] 8008058: 460b mov r3, r1 800805a: 70fb strb r3, [r7, #3] if (pdev->pClass == NULL) 800805c: 687b ldr r3, [r7, #4] 800805e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008062: 2b00 cmp r3, #0 8008064: d101 bne.n 800806a { return USBD_FAIL; 8008066: 2303 movs r3, #3 8008068: e014 b.n 8008094 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 800806a: 687b ldr r3, [r7, #4] 800806c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008070: b2db uxtb r3, r3 8008072: 2b03 cmp r3, #3 8008074: d10d bne.n 8008092 { if (pdev->pClass->IsoOUTIncomplete != NULL) 8008076: 687b ldr r3, [r7, #4] 8008078: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800807c: 6a5b ldr r3, [r3, #36] ; 0x24 800807e: 2b00 cmp r3, #0 8008080: d007 beq.n 8008092 { (void)pdev->pClass->IsoOUTIncomplete(pdev, epnum); 8008082: 687b ldr r3, [r7, #4] 8008084: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008088: 6a5b ldr r3, [r3, #36] ; 0x24 800808a: 78fa ldrb r2, [r7, #3] 800808c: 4611 mov r1, r2 800808e: 6878 ldr r0, [r7, #4] 8008090: 4798 blx r3 } } return USBD_OK; 8008092: 2300 movs r3, #0 } 8008094: 4618 mov r0, r3 8008096: 3708 adds r7, #8 8008098: 46bd mov sp, r7 800809a: bd80 pop {r7, pc} 0800809c : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 800809c: b480 push {r7} 800809e: b083 sub sp, #12 80080a0: af00 add r7, sp, #0 80080a2: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 80080a4: 2300 movs r3, #0 } 80080a6: 4618 mov r0, r3 80080a8: 370c adds r7, #12 80080aa: 46bd mov sp, r7 80080ac: f85d 7b04 ldr.w r7, [sp], #4 80080b0: 4770 bx lr 080080b2 : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 80080b2: b580 push {r7, lr} 80080b4: b082 sub sp, #8 80080b6: af00 add r7, sp, #0 80080b8: 6078 str r0, [r7, #4] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 80080ba: 687b ldr r3, [r7, #4] 80080bc: 2201 movs r2, #1 80080be: f883 229c strb.w r2, [r3, #668] ; 0x29c if (pdev->pClass != NULL) 80080c2: 687b ldr r3, [r7, #4] 80080c4: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80080c8: 2b00 cmp r3, #0 80080ca: d009 beq.n 80080e0 { (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); 80080cc: 687b ldr r3, [r7, #4] 80080ce: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80080d2: 685b ldr r3, [r3, #4] 80080d4: 687a ldr r2, [r7, #4] 80080d6: 6852 ldr r2, [r2, #4] 80080d8: b2d2 uxtb r2, r2 80080da: 4611 mov r1, r2 80080dc: 6878 ldr r0, [r7, #4] 80080de: 4798 blx r3 } return USBD_OK; 80080e0: 2300 movs r3, #0 } 80080e2: 4618 mov r0, r3 80080e4: 3708 adds r7, #8 80080e6: 46bd mov sp, r7 80080e8: bd80 pop {r7, pc} 080080ea : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 80080ea: b480 push {r7} 80080ec: b087 sub sp, #28 80080ee: af00 add r7, sp, #0 80080f0: 6078 str r0, [r7, #4] uint16_t _SwapVal, _Byte1, _Byte2; uint8_t *_pbuff = addr; 80080f2: 687b ldr r3, [r7, #4] 80080f4: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 80080f6: 697b ldr r3, [r7, #20] 80080f8: 781b ldrb r3, [r3, #0] 80080fa: 827b strh r3, [r7, #18] _pbuff++; 80080fc: 697b ldr r3, [r7, #20] 80080fe: 3301 adds r3, #1 8008100: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 8008102: 697b ldr r3, [r7, #20] 8008104: 781b ldrb r3, [r3, #0] 8008106: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 8008108: 8a3b ldrh r3, [r7, #16] 800810a: 021b lsls r3, r3, #8 800810c: b21a sxth r2, r3 800810e: f9b7 3012 ldrsh.w r3, [r7, #18] 8008112: 4313 orrs r3, r2 8008114: b21b sxth r3, r3 8008116: 81fb strh r3, [r7, #14] return _SwapVal; 8008118: 89fb ldrh r3, [r7, #14] } 800811a: 4618 mov r0, r3 800811c: 371c adds r7, #28 800811e: 46bd mov sp, r7 8008120: f85d 7b04 ldr.w r7, [sp], #4 8008124: 4770 bx lr ... 08008128 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008128: b580 push {r7, lr} 800812a: b084 sub sp, #16 800812c: af00 add r7, sp, #0 800812e: 6078 str r0, [r7, #4] 8008130: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8008132: 2300 movs r3, #0 8008134: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8008136: 683b ldr r3, [r7, #0] 8008138: 781b ldrb r3, [r3, #0] 800813a: f003 0360 and.w r3, r3, #96 ; 0x60 800813e: 2b40 cmp r3, #64 ; 0x40 8008140: d005 beq.n 800814e 8008142: 2b40 cmp r3, #64 ; 0x40 8008144: d853 bhi.n 80081ee 8008146: 2b00 cmp r3, #0 8008148: d00b beq.n 8008162 800814a: 2b20 cmp r3, #32 800814c: d14f bne.n 80081ee { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 800814e: 687b ldr r3, [r7, #4] 8008150: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008154: 689b ldr r3, [r3, #8] 8008156: 6839 ldr r1, [r7, #0] 8008158: 6878 ldr r0, [r7, #4] 800815a: 4798 blx r3 800815c: 4603 mov r3, r0 800815e: 73fb strb r3, [r7, #15] break; 8008160: e04a b.n 80081f8 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8008162: 683b ldr r3, [r7, #0] 8008164: 785b ldrb r3, [r3, #1] 8008166: 2b09 cmp r3, #9 8008168: d83b bhi.n 80081e2 800816a: a201 add r2, pc, #4 ; (adr r2, 8008170 ) 800816c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008170: 080081c5 .word 0x080081c5 8008174: 080081d9 .word 0x080081d9 8008178: 080081e3 .word 0x080081e3 800817c: 080081cf .word 0x080081cf 8008180: 080081e3 .word 0x080081e3 8008184: 080081a3 .word 0x080081a3 8008188: 08008199 .word 0x08008199 800818c: 080081e3 .word 0x080081e3 8008190: 080081bb .word 0x080081bb 8008194: 080081ad .word 0x080081ad { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 8008198: 6839 ldr r1, [r7, #0] 800819a: 6878 ldr r0, [r7, #4] 800819c: f000 f9de bl 800855c break; 80081a0: e024 b.n 80081ec case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 80081a2: 6839 ldr r1, [r7, #0] 80081a4: 6878 ldr r0, [r7, #4] 80081a6: f000 fb43 bl 8008830 break; 80081aa: e01f b.n 80081ec case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 80081ac: 6839 ldr r1, [r7, #0] 80081ae: 6878 ldr r0, [r7, #4] 80081b0: f000 fb82 bl 80088b8 80081b4: 4603 mov r3, r0 80081b6: 73fb strb r3, [r7, #15] break; 80081b8: e018 b.n 80081ec case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 80081ba: 6839 ldr r1, [r7, #0] 80081bc: 6878 ldr r0, [r7, #4] 80081be: f000 fc21 bl 8008a04 break; 80081c2: e013 b.n 80081ec case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 80081c4: 6839 ldr r1, [r7, #0] 80081c6: 6878 ldr r0, [r7, #4] 80081c8: f000 fc52 bl 8008a70 break; 80081cc: e00e b.n 80081ec case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 80081ce: 6839 ldr r1, [r7, #0] 80081d0: 6878 ldr r0, [r7, #4] 80081d2: f000 fc81 bl 8008ad8 break; 80081d6: e009 b.n 80081ec case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 80081d8: 6839 ldr r1, [r7, #0] 80081da: 6878 ldr r0, [r7, #4] 80081dc: f000 fc90 bl 8008b00 break; 80081e0: e004 b.n 80081ec default: USBD_CtlError(pdev, req); 80081e2: 6839 ldr r1, [r7, #0] 80081e4: 6878 ldr r0, [r7, #4] 80081e6: f000 fce7 bl 8008bb8 break; 80081ea: bf00 nop } break; 80081ec: e004 b.n 80081f8 default: USBD_CtlError(pdev, req); 80081ee: 6839 ldr r1, [r7, #0] 80081f0: 6878 ldr r0, [r7, #4] 80081f2: f000 fce1 bl 8008bb8 break; 80081f6: bf00 nop } return ret; 80081f8: 7bfb ldrb r3, [r7, #15] } 80081fa: 4618 mov r0, r3 80081fc: 3710 adds r7, #16 80081fe: 46bd mov sp, r7 8008200: bd80 pop {r7, pc} 8008202: bf00 nop 08008204 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008204: b580 push {r7, lr} 8008206: b084 sub sp, #16 8008208: af00 add r7, sp, #0 800820a: 6078 str r0, [r7, #4] 800820c: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800820e: 2300 movs r3, #0 8008210: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8008212: 683b ldr r3, [r7, #0] 8008214: 781b ldrb r3, [r3, #0] 8008216: f003 0360 and.w r3, r3, #96 ; 0x60 800821a: 2b40 cmp r3, #64 ; 0x40 800821c: d005 beq.n 800822a 800821e: 2b40 cmp r3, #64 ; 0x40 8008220: d82f bhi.n 8008282 8008222: 2b00 cmp r3, #0 8008224: d001 beq.n 800822a 8008226: 2b20 cmp r3, #32 8008228: d12b bne.n 8008282 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 800822a: 687b ldr r3, [r7, #4] 800822c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008230: b2db uxtb r3, r3 8008232: 3b01 subs r3, #1 8008234: 2b02 cmp r3, #2 8008236: d81d bhi.n 8008274 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 8008238: 683b ldr r3, [r7, #0] 800823a: 889b ldrh r3, [r3, #4] 800823c: b2db uxtb r3, r3 800823e: 2b01 cmp r3, #1 8008240: d813 bhi.n 800826a { ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 8008242: 687b ldr r3, [r7, #4] 8008244: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008248: 689b ldr r3, [r3, #8] 800824a: 6839 ldr r1, [r7, #0] 800824c: 6878 ldr r0, [r7, #4] 800824e: 4798 blx r3 8008250: 4603 mov r3, r0 8008252: 73fb strb r3, [r7, #15] if ((req->wLength == 0U) && (ret == USBD_OK)) 8008254: 683b ldr r3, [r7, #0] 8008256: 88db ldrh r3, [r3, #6] 8008258: 2b00 cmp r3, #0 800825a: d110 bne.n 800827e 800825c: 7bfb ldrb r3, [r7, #15] 800825e: 2b00 cmp r3, #0 8008260: d10d bne.n 800827e { (void)USBD_CtlSendStatus(pdev); 8008262: 6878 ldr r0, [r7, #4] 8008264: f000 fd73 bl 8008d4e } else { USBD_CtlError(pdev, req); } break; 8008268: e009 b.n 800827e USBD_CtlError(pdev, req); 800826a: 6839 ldr r1, [r7, #0] 800826c: 6878 ldr r0, [r7, #4] 800826e: f000 fca3 bl 8008bb8 break; 8008272: e004 b.n 800827e default: USBD_CtlError(pdev, req); 8008274: 6839 ldr r1, [r7, #0] 8008276: 6878 ldr r0, [r7, #4] 8008278: f000 fc9e bl 8008bb8 break; 800827c: e000 b.n 8008280 break; 800827e: bf00 nop } break; 8008280: e004 b.n 800828c default: USBD_CtlError(pdev, req); 8008282: 6839 ldr r1, [r7, #0] 8008284: 6878 ldr r0, [r7, #4] 8008286: f000 fc97 bl 8008bb8 break; 800828a: bf00 nop } return ret; 800828c: 7bfb ldrb r3, [r7, #15] } 800828e: 4618 mov r0, r3 8008290: 3710 adds r7, #16 8008292: 46bd mov sp, r7 8008294: bd80 pop {r7, pc} 08008296 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008296: b580 push {r7, lr} 8008298: b084 sub sp, #16 800829a: af00 add r7, sp, #0 800829c: 6078 str r0, [r7, #4] 800829e: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; USBD_StatusTypeDef ret = USBD_OK; 80082a0: 2300 movs r3, #0 80082a2: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 80082a4: 683b ldr r3, [r7, #0] 80082a6: 889b ldrh r3, [r3, #4] 80082a8: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 80082aa: 683b ldr r3, [r7, #0] 80082ac: 781b ldrb r3, [r3, #0] 80082ae: f003 0360 and.w r3, r3, #96 ; 0x60 80082b2: 2b40 cmp r3, #64 ; 0x40 80082b4: d007 beq.n 80082c6 80082b6: 2b40 cmp r3, #64 ; 0x40 80082b8: f200 8145 bhi.w 8008546 80082bc: 2b00 cmp r3, #0 80082be: d00c beq.n 80082da 80082c0: 2b20 cmp r3, #32 80082c2: f040 8140 bne.w 8008546 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 80082c6: 687b ldr r3, [r7, #4] 80082c8: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80082cc: 689b ldr r3, [r3, #8] 80082ce: 6839 ldr r1, [r7, #0] 80082d0: 6878 ldr r0, [r7, #4] 80082d2: 4798 blx r3 80082d4: 4603 mov r3, r0 80082d6: 73fb strb r3, [r7, #15] break; 80082d8: e13a b.n 8008550 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80082da: 683b ldr r3, [r7, #0] 80082dc: 785b ldrb r3, [r3, #1] 80082de: 2b03 cmp r3, #3 80082e0: d007 beq.n 80082f2 80082e2: 2b03 cmp r3, #3 80082e4: f300 8129 bgt.w 800853a 80082e8: 2b00 cmp r3, #0 80082ea: d07f beq.n 80083ec 80082ec: 2b01 cmp r3, #1 80082ee: d03c beq.n 800836a 80082f0: e123 b.n 800853a { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 80082f2: 687b ldr r3, [r7, #4] 80082f4: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80082f8: b2db uxtb r3, r3 80082fa: 2b02 cmp r3, #2 80082fc: d002 beq.n 8008304 80082fe: 2b03 cmp r3, #3 8008300: d016 beq.n 8008330 8008302: e02c b.n 800835e { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8008304: 7bbb ldrb r3, [r7, #14] 8008306: 2b00 cmp r3, #0 8008308: d00d beq.n 8008326 800830a: 7bbb ldrb r3, [r7, #14] 800830c: 2b80 cmp r3, #128 ; 0x80 800830e: d00a beq.n 8008326 { (void)USBD_LL_StallEP(pdev, ep_addr); 8008310: 7bbb ldrb r3, [r7, #14] 8008312: 4619 mov r1, r3 8008314: 6878 ldr r0, [r7, #4] 8008316: f001 f963 bl 80095e0 (void)USBD_LL_StallEP(pdev, 0x80U); 800831a: 2180 movs r1, #128 ; 0x80 800831c: 6878 ldr r0, [r7, #4] 800831e: f001 f95f bl 80095e0 8008322: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8008324: e020 b.n 8008368 USBD_CtlError(pdev, req); 8008326: 6839 ldr r1, [r7, #0] 8008328: 6878 ldr r0, [r7, #4] 800832a: f000 fc45 bl 8008bb8 break; 800832e: e01b b.n 8008368 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8008330: 683b ldr r3, [r7, #0] 8008332: 885b ldrh r3, [r3, #2] 8008334: 2b00 cmp r3, #0 8008336: d10e bne.n 8008356 { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 8008338: 7bbb ldrb r3, [r7, #14] 800833a: 2b00 cmp r3, #0 800833c: d00b beq.n 8008356 800833e: 7bbb ldrb r3, [r7, #14] 8008340: 2b80 cmp r3, #128 ; 0x80 8008342: d008 beq.n 8008356 8008344: 683b ldr r3, [r7, #0] 8008346: 88db ldrh r3, [r3, #6] 8008348: 2b00 cmp r3, #0 800834a: d104 bne.n 8008356 { (void)USBD_LL_StallEP(pdev, ep_addr); 800834c: 7bbb ldrb r3, [r7, #14] 800834e: 4619 mov r1, r3 8008350: 6878 ldr r0, [r7, #4] 8008352: f001 f945 bl 80095e0 } } (void)USBD_CtlSendStatus(pdev); 8008356: 6878 ldr r0, [r7, #4] 8008358: f000 fcf9 bl 8008d4e break; 800835c: e004 b.n 8008368 default: USBD_CtlError(pdev, req); 800835e: 6839 ldr r1, [r7, #0] 8008360: 6878 ldr r0, [r7, #4] 8008362: f000 fc29 bl 8008bb8 break; 8008366: bf00 nop } break; 8008368: e0ec b.n 8008544 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 800836a: 687b ldr r3, [r7, #4] 800836c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008370: b2db uxtb r3, r3 8008372: 2b02 cmp r3, #2 8008374: d002 beq.n 800837c 8008376: 2b03 cmp r3, #3 8008378: d016 beq.n 80083a8 800837a: e030 b.n 80083de { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 800837c: 7bbb ldrb r3, [r7, #14] 800837e: 2b00 cmp r3, #0 8008380: d00d beq.n 800839e 8008382: 7bbb ldrb r3, [r7, #14] 8008384: 2b80 cmp r3, #128 ; 0x80 8008386: d00a beq.n 800839e { (void)USBD_LL_StallEP(pdev, ep_addr); 8008388: 7bbb ldrb r3, [r7, #14] 800838a: 4619 mov r1, r3 800838c: 6878 ldr r0, [r7, #4] 800838e: f001 f927 bl 80095e0 (void)USBD_LL_StallEP(pdev, 0x80U); 8008392: 2180 movs r1, #128 ; 0x80 8008394: 6878 ldr r0, [r7, #4] 8008396: f001 f923 bl 80095e0 800839a: bf00 nop } else { USBD_CtlError(pdev, req); } break; 800839c: e025 b.n 80083ea USBD_CtlError(pdev, req); 800839e: 6839 ldr r1, [r7, #0] 80083a0: 6878 ldr r0, [r7, #4] 80083a2: f000 fc09 bl 8008bb8 break; 80083a6: e020 b.n 80083ea case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 80083a8: 683b ldr r3, [r7, #0] 80083aa: 885b ldrh r3, [r3, #2] 80083ac: 2b00 cmp r3, #0 80083ae: d11b bne.n 80083e8 { if ((ep_addr & 0x7FU) != 0x00U) 80083b0: 7bbb ldrb r3, [r7, #14] 80083b2: f003 037f and.w r3, r3, #127 ; 0x7f 80083b6: 2b00 cmp r3, #0 80083b8: d004 beq.n 80083c4 { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 80083ba: 7bbb ldrb r3, [r7, #14] 80083bc: 4619 mov r1, r3 80083be: 6878 ldr r0, [r7, #4] 80083c0: f001 f92d bl 800961e } (void)USBD_CtlSendStatus(pdev); 80083c4: 6878 ldr r0, [r7, #4] 80083c6: f000 fcc2 bl 8008d4e ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 80083ca: 687b ldr r3, [r7, #4] 80083cc: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80083d0: 689b ldr r3, [r3, #8] 80083d2: 6839 ldr r1, [r7, #0] 80083d4: 6878 ldr r0, [r7, #4] 80083d6: 4798 blx r3 80083d8: 4603 mov r3, r0 80083da: 73fb strb r3, [r7, #15] } break; 80083dc: e004 b.n 80083e8 default: USBD_CtlError(pdev, req); 80083de: 6839 ldr r1, [r7, #0] 80083e0: 6878 ldr r0, [r7, #4] 80083e2: f000 fbe9 bl 8008bb8 break; 80083e6: e000 b.n 80083ea break; 80083e8: bf00 nop } break; 80083ea: e0ab b.n 8008544 case USB_REQ_GET_STATUS: switch (pdev->dev_state) 80083ec: 687b ldr r3, [r7, #4] 80083ee: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80083f2: b2db uxtb r3, r3 80083f4: 2b02 cmp r3, #2 80083f6: d002 beq.n 80083fe 80083f8: 2b03 cmp r3, #3 80083fa: d032 beq.n 8008462 80083fc: e097 b.n 800852e { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80083fe: 7bbb ldrb r3, [r7, #14] 8008400: 2b00 cmp r3, #0 8008402: d007 beq.n 8008414 8008404: 7bbb ldrb r3, [r7, #14] 8008406: 2b80 cmp r3, #128 ; 0x80 8008408: d004 beq.n 8008414 { USBD_CtlError(pdev, req); 800840a: 6839 ldr r1, [r7, #0] 800840c: 6878 ldr r0, [r7, #4] 800840e: f000 fbd3 bl 8008bb8 break; 8008412: e091 b.n 8008538 } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8008414: f997 300e ldrsb.w r3, [r7, #14] 8008418: 2b00 cmp r3, #0 800841a: da0b bge.n 8008434 800841c: 7bbb ldrb r3, [r7, #14] 800841e: f003 027f and.w r2, r3, #127 ; 0x7f 8008422: 4613 mov r3, r2 8008424: 009b lsls r3, r3, #2 8008426: 4413 add r3, r2 8008428: 009b lsls r3, r3, #2 800842a: 3310 adds r3, #16 800842c: 687a ldr r2, [r7, #4] 800842e: 4413 add r3, r2 8008430: 3304 adds r3, #4 8008432: e00b b.n 800844c &pdev->ep_out[ep_addr & 0x7FU]; 8008434: 7bbb ldrb r3, [r7, #14] 8008436: f003 027f and.w r2, r3, #127 ; 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800843a: 4613 mov r3, r2 800843c: 009b lsls r3, r3, #2 800843e: 4413 add r3, r2 8008440: 009b lsls r3, r3, #2 8008442: f503 73a8 add.w r3, r3, #336 ; 0x150 8008446: 687a ldr r2, [r7, #4] 8008448: 4413 add r3, r2 800844a: 3304 adds r3, #4 800844c: 60bb str r3, [r7, #8] pep->status = 0x0000U; 800844e: 68bb ldr r3, [r7, #8] 8008450: 2200 movs r2, #0 8008452: 601a str r2, [r3, #0] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8008454: 68bb ldr r3, [r7, #8] 8008456: 2202 movs r2, #2 8008458: 4619 mov r1, r3 800845a: 6878 ldr r0, [r7, #4] 800845c: f000 fc1d bl 8008c9a break; 8008460: e06a b.n 8008538 case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 8008462: f997 300e ldrsb.w r3, [r7, #14] 8008466: 2b00 cmp r3, #0 8008468: da11 bge.n 800848e { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 800846a: 7bbb ldrb r3, [r7, #14] 800846c: f003 020f and.w r2, r3, #15 8008470: 6879 ldr r1, [r7, #4] 8008472: 4613 mov r3, r2 8008474: 009b lsls r3, r3, #2 8008476: 4413 add r3, r2 8008478: 009b lsls r3, r3, #2 800847a: 440b add r3, r1 800847c: 3324 adds r3, #36 ; 0x24 800847e: 881b ldrh r3, [r3, #0] 8008480: 2b00 cmp r3, #0 8008482: d117 bne.n 80084b4 { USBD_CtlError(pdev, req); 8008484: 6839 ldr r1, [r7, #0] 8008486: 6878 ldr r0, [r7, #4] 8008488: f000 fb96 bl 8008bb8 break; 800848c: e054 b.n 8008538 } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 800848e: 7bbb ldrb r3, [r7, #14] 8008490: f003 020f and.w r2, r3, #15 8008494: 6879 ldr r1, [r7, #4] 8008496: 4613 mov r3, r2 8008498: 009b lsls r3, r3, #2 800849a: 4413 add r3, r2 800849c: 009b lsls r3, r3, #2 800849e: 440b add r3, r1 80084a0: f503 73b2 add.w r3, r3, #356 ; 0x164 80084a4: 881b ldrh r3, [r3, #0] 80084a6: 2b00 cmp r3, #0 80084a8: d104 bne.n 80084b4 { USBD_CtlError(pdev, req); 80084aa: 6839 ldr r1, [r7, #0] 80084ac: 6878 ldr r0, [r7, #4] 80084ae: f000 fb83 bl 8008bb8 break; 80084b2: e041 b.n 8008538 } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80084b4: f997 300e ldrsb.w r3, [r7, #14] 80084b8: 2b00 cmp r3, #0 80084ba: da0b bge.n 80084d4 80084bc: 7bbb ldrb r3, [r7, #14] 80084be: f003 027f and.w r2, r3, #127 ; 0x7f 80084c2: 4613 mov r3, r2 80084c4: 009b lsls r3, r3, #2 80084c6: 4413 add r3, r2 80084c8: 009b lsls r3, r3, #2 80084ca: 3310 adds r3, #16 80084cc: 687a ldr r2, [r7, #4] 80084ce: 4413 add r3, r2 80084d0: 3304 adds r3, #4 80084d2: e00b b.n 80084ec &pdev->ep_out[ep_addr & 0x7FU]; 80084d4: 7bbb ldrb r3, [r7, #14] 80084d6: f003 027f and.w r2, r3, #127 ; 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80084da: 4613 mov r3, r2 80084dc: 009b lsls r3, r3, #2 80084de: 4413 add r3, r2 80084e0: 009b lsls r3, r3, #2 80084e2: f503 73a8 add.w r3, r3, #336 ; 0x150 80084e6: 687a ldr r2, [r7, #4] 80084e8: 4413 add r3, r2 80084ea: 3304 adds r3, #4 80084ec: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 80084ee: 7bbb ldrb r3, [r7, #14] 80084f0: 2b00 cmp r3, #0 80084f2: d002 beq.n 80084fa 80084f4: 7bbb ldrb r3, [r7, #14] 80084f6: 2b80 cmp r3, #128 ; 0x80 80084f8: d103 bne.n 8008502 { pep->status = 0x0000U; 80084fa: 68bb ldr r3, [r7, #8] 80084fc: 2200 movs r2, #0 80084fe: 601a str r2, [r3, #0] 8008500: e00e b.n 8008520 } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 8008502: 7bbb ldrb r3, [r7, #14] 8008504: 4619 mov r1, r3 8008506: 6878 ldr r0, [r7, #4] 8008508: f001 f8a8 bl 800965c 800850c: 4603 mov r3, r0 800850e: 2b00 cmp r3, #0 8008510: d003 beq.n 800851a { pep->status = 0x0001U; 8008512: 68bb ldr r3, [r7, #8] 8008514: 2201 movs r2, #1 8008516: 601a str r2, [r3, #0] 8008518: e002 b.n 8008520 } else { pep->status = 0x0000U; 800851a: 68bb ldr r3, [r7, #8] 800851c: 2200 movs r2, #0 800851e: 601a str r2, [r3, #0] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8008520: 68bb ldr r3, [r7, #8] 8008522: 2202 movs r2, #2 8008524: 4619 mov r1, r3 8008526: 6878 ldr r0, [r7, #4] 8008528: f000 fbb7 bl 8008c9a break; 800852c: e004 b.n 8008538 default: USBD_CtlError(pdev, req); 800852e: 6839 ldr r1, [r7, #0] 8008530: 6878 ldr r0, [r7, #4] 8008532: f000 fb41 bl 8008bb8 break; 8008536: bf00 nop } break; 8008538: e004 b.n 8008544 default: USBD_CtlError(pdev, req); 800853a: 6839 ldr r1, [r7, #0] 800853c: 6878 ldr r0, [r7, #4] 800853e: f000 fb3b bl 8008bb8 break; 8008542: bf00 nop } break; 8008544: e004 b.n 8008550 default: USBD_CtlError(pdev, req); 8008546: 6839 ldr r1, [r7, #0] 8008548: 6878 ldr r0, [r7, #4] 800854a: f000 fb35 bl 8008bb8 break; 800854e: bf00 nop } return ret; 8008550: 7bfb ldrb r3, [r7, #15] } 8008552: 4618 mov r0, r3 8008554: 3710 adds r7, #16 8008556: 46bd mov sp, r7 8008558: bd80 pop {r7, pc} ... 0800855c : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800855c: b580 push {r7, lr} 800855e: b084 sub sp, #16 8008560: af00 add r7, sp, #0 8008562: 6078 str r0, [r7, #4] 8008564: 6039 str r1, [r7, #0] uint16_t len = 0U; 8008566: 2300 movs r3, #0 8008568: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 800856a: 2300 movs r3, #0 800856c: 60fb str r3, [r7, #12] uint8_t err = 0U; 800856e: 2300 movs r3, #0 8008570: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 8008572: 683b ldr r3, [r7, #0] 8008574: 885b ldrh r3, [r3, #2] 8008576: 0a1b lsrs r3, r3, #8 8008578: b29b uxth r3, r3 800857a: 3b01 subs r3, #1 800857c: 2b06 cmp r3, #6 800857e: f200 8128 bhi.w 80087d2 8008582: a201 add r2, pc, #4 ; (adr r2, 8008588 ) 8008584: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008588: 080085a5 .word 0x080085a5 800858c: 080085bd .word 0x080085bd 8008590: 080085fd .word 0x080085fd 8008594: 080087d3 .word 0x080087d3 8008598: 080087d3 .word 0x080087d3 800859c: 08008773 .word 0x08008773 80085a0: 0800879f .word 0x0800879f err++; } break; #endif case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 80085a4: 687b ldr r3, [r7, #4] 80085a6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 80085aa: 681b ldr r3, [r3, #0] 80085ac: 687a ldr r2, [r7, #4] 80085ae: 7c12 ldrb r2, [r2, #16] 80085b0: f107 0108 add.w r1, r7, #8 80085b4: 4610 mov r0, r2 80085b6: 4798 blx r3 80085b8: 60f8 str r0, [r7, #12] break; 80085ba: e112 b.n 80087e2 case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 80085bc: 687b ldr r3, [r7, #4] 80085be: 7c1b ldrb r3, [r3, #16] 80085c0: 2b00 cmp r3, #0 80085c2: d10d bne.n 80085e0 { pbuf = pdev->pClass->GetHSConfigDescriptor(&len); 80085c4: 687b ldr r3, [r7, #4] 80085c6: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80085ca: 6a9b ldr r3, [r3, #40] ; 0x28 80085cc: f107 0208 add.w r2, r7, #8 80085d0: 4610 mov r0, r2 80085d2: 4798 blx r3 80085d4: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 80085d6: 68fb ldr r3, [r7, #12] 80085d8: 3301 adds r3, #1 80085da: 2202 movs r2, #2 80085dc: 701a strb r2, [r3, #0] else { pbuf = pdev->pClass->GetFSConfigDescriptor(&len); pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 80085de: e100 b.n 80087e2 pbuf = pdev->pClass->GetFSConfigDescriptor(&len); 80085e0: 687b ldr r3, [r7, #4] 80085e2: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80085e6: 6adb ldr r3, [r3, #44] ; 0x2c 80085e8: f107 0208 add.w r2, r7, #8 80085ec: 4610 mov r0, r2 80085ee: 4798 blx r3 80085f0: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 80085f2: 68fb ldr r3, [r7, #12] 80085f4: 3301 adds r3, #1 80085f6: 2202 movs r2, #2 80085f8: 701a strb r2, [r3, #0] break; 80085fa: e0f2 b.n 80087e2 case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 80085fc: 683b ldr r3, [r7, #0] 80085fe: 885b ldrh r3, [r3, #2] 8008600: b2db uxtb r3, r3 8008602: 2b05 cmp r3, #5 8008604: f200 80ac bhi.w 8008760 8008608: a201 add r2, pc, #4 ; (adr r2, 8008610 ) 800860a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800860e: bf00 nop 8008610: 08008629 .word 0x08008629 8008614: 0800865d .word 0x0800865d 8008618: 08008691 .word 0x08008691 800861c: 080086c5 .word 0x080086c5 8008620: 080086f9 .word 0x080086f9 8008624: 0800872d .word 0x0800872d { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 8008628: 687b ldr r3, [r7, #4] 800862a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 800862e: 685b ldr r3, [r3, #4] 8008630: 2b00 cmp r3, #0 8008632: d00b beq.n 800864c { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 8008634: 687b ldr r3, [r7, #4] 8008636: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 800863a: 685b ldr r3, [r3, #4] 800863c: 687a ldr r2, [r7, #4] 800863e: 7c12 ldrb r2, [r2, #16] 8008640: f107 0108 add.w r1, r7, #8 8008644: 4610 mov r0, r2 8008646: 4798 blx r3 8008648: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800864a: e091 b.n 8008770 USBD_CtlError(pdev, req); 800864c: 6839 ldr r1, [r7, #0] 800864e: 6878 ldr r0, [r7, #4] 8008650: f000 fab2 bl 8008bb8 err++; 8008654: 7afb ldrb r3, [r7, #11] 8008656: 3301 adds r3, #1 8008658: 72fb strb r3, [r7, #11] break; 800865a: e089 b.n 8008770 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 800865c: 687b ldr r3, [r7, #4] 800865e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8008662: 689b ldr r3, [r3, #8] 8008664: 2b00 cmp r3, #0 8008666: d00b beq.n 8008680 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 8008668: 687b ldr r3, [r7, #4] 800866a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 800866e: 689b ldr r3, [r3, #8] 8008670: 687a ldr r2, [r7, #4] 8008672: 7c12 ldrb r2, [r2, #16] 8008674: f107 0108 add.w r1, r7, #8 8008678: 4610 mov r0, r2 800867a: 4798 blx r3 800867c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800867e: e077 b.n 8008770 USBD_CtlError(pdev, req); 8008680: 6839 ldr r1, [r7, #0] 8008682: 6878 ldr r0, [r7, #4] 8008684: f000 fa98 bl 8008bb8 err++; 8008688: 7afb ldrb r3, [r7, #11] 800868a: 3301 adds r3, #1 800868c: 72fb strb r3, [r7, #11] break; 800868e: e06f b.n 8008770 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 8008690: 687b ldr r3, [r7, #4] 8008692: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8008696: 68db ldr r3, [r3, #12] 8008698: 2b00 cmp r3, #0 800869a: d00b beq.n 80086b4 { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 800869c: 687b ldr r3, [r7, #4] 800869e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 80086a2: 68db ldr r3, [r3, #12] 80086a4: 687a ldr r2, [r7, #4] 80086a6: 7c12 ldrb r2, [r2, #16] 80086a8: f107 0108 add.w r1, r7, #8 80086ac: 4610 mov r0, r2 80086ae: 4798 blx r3 80086b0: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80086b2: e05d b.n 8008770 USBD_CtlError(pdev, req); 80086b4: 6839 ldr r1, [r7, #0] 80086b6: 6878 ldr r0, [r7, #4] 80086b8: f000 fa7e bl 8008bb8 err++; 80086bc: 7afb ldrb r3, [r7, #11] 80086be: 3301 adds r3, #1 80086c0: 72fb strb r3, [r7, #11] break; 80086c2: e055 b.n 8008770 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 80086c4: 687b ldr r3, [r7, #4] 80086c6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 80086ca: 691b ldr r3, [r3, #16] 80086cc: 2b00 cmp r3, #0 80086ce: d00b beq.n 80086e8 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 80086d0: 687b ldr r3, [r7, #4] 80086d2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 80086d6: 691b ldr r3, [r3, #16] 80086d8: 687a ldr r2, [r7, #4] 80086da: 7c12 ldrb r2, [r2, #16] 80086dc: f107 0108 add.w r1, r7, #8 80086e0: 4610 mov r0, r2 80086e2: 4798 blx r3 80086e4: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80086e6: e043 b.n 8008770 USBD_CtlError(pdev, req); 80086e8: 6839 ldr r1, [r7, #0] 80086ea: 6878 ldr r0, [r7, #4] 80086ec: f000 fa64 bl 8008bb8 err++; 80086f0: 7afb ldrb r3, [r7, #11] 80086f2: 3301 adds r3, #1 80086f4: 72fb strb r3, [r7, #11] break; 80086f6: e03b b.n 8008770 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 80086f8: 687b ldr r3, [r7, #4] 80086fa: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 80086fe: 695b ldr r3, [r3, #20] 8008700: 2b00 cmp r3, #0 8008702: d00b beq.n 800871c { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 8008704: 687b ldr r3, [r7, #4] 8008706: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 800870a: 695b ldr r3, [r3, #20] 800870c: 687a ldr r2, [r7, #4] 800870e: 7c12 ldrb r2, [r2, #16] 8008710: f107 0108 add.w r1, r7, #8 8008714: 4610 mov r0, r2 8008716: 4798 blx r3 8008718: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800871a: e029 b.n 8008770 USBD_CtlError(pdev, req); 800871c: 6839 ldr r1, [r7, #0] 800871e: 6878 ldr r0, [r7, #4] 8008720: f000 fa4a bl 8008bb8 err++; 8008724: 7afb ldrb r3, [r7, #11] 8008726: 3301 adds r3, #1 8008728: 72fb strb r3, [r7, #11] break; 800872a: e021 b.n 8008770 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 800872c: 687b ldr r3, [r7, #4] 800872e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8008732: 699b ldr r3, [r3, #24] 8008734: 2b00 cmp r3, #0 8008736: d00b beq.n 8008750 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 8008738: 687b ldr r3, [r7, #4] 800873a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 800873e: 699b ldr r3, [r3, #24] 8008740: 687a ldr r2, [r7, #4] 8008742: 7c12 ldrb r2, [r2, #16] 8008744: f107 0108 add.w r1, r7, #8 8008748: 4610 mov r0, r2 800874a: 4798 blx r3 800874c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800874e: e00f b.n 8008770 USBD_CtlError(pdev, req); 8008750: 6839 ldr r1, [r7, #0] 8008752: 6878 ldr r0, [r7, #4] 8008754: f000 fa30 bl 8008bb8 err++; 8008758: 7afb ldrb r3, [r7, #11] 800875a: 3301 adds r3, #1 800875c: 72fb strb r3, [r7, #11] break; 800875e: e007 b.n 8008770 err++; } #endif #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 8008760: 6839 ldr r1, [r7, #0] 8008762: 6878 ldr r0, [r7, #4] 8008764: f000 fa28 bl 8008bb8 err++; 8008768: 7afb ldrb r3, [r7, #11] 800876a: 3301 adds r3, #1 800876c: 72fb strb r3, [r7, #11] #endif break; 800876e: bf00 nop } break; 8008770: e037 b.n 80087e2 case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 8008772: 687b ldr r3, [r7, #4] 8008774: 7c1b ldrb r3, [r3, #16] 8008776: 2b00 cmp r3, #0 8008778: d109 bne.n 800878e { pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len); 800877a: 687b ldr r3, [r7, #4] 800877c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008780: 6b5b ldr r3, [r3, #52] ; 0x34 8008782: f107 0208 add.w r2, r7, #8 8008786: 4610 mov r0, r2 8008788: 4798 blx r3 800878a: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800878c: e029 b.n 80087e2 USBD_CtlError(pdev, req); 800878e: 6839 ldr r1, [r7, #0] 8008790: 6878 ldr r0, [r7, #4] 8008792: f000 fa11 bl 8008bb8 err++; 8008796: 7afb ldrb r3, [r7, #11] 8008798: 3301 adds r3, #1 800879a: 72fb strb r3, [r7, #11] break; 800879c: e021 b.n 80087e2 case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 800879e: 687b ldr r3, [r7, #4] 80087a0: 7c1b ldrb r3, [r3, #16] 80087a2: 2b00 cmp r3, #0 80087a4: d10d bne.n 80087c2 { pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len); 80087a6: 687b ldr r3, [r7, #4] 80087a8: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80087ac: 6b1b ldr r3, [r3, #48] ; 0x30 80087ae: f107 0208 add.w r2, r7, #8 80087b2: 4610 mov r0, r2 80087b4: 4798 blx r3 80087b6: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 80087b8: 68fb ldr r3, [r7, #12] 80087ba: 3301 adds r3, #1 80087bc: 2207 movs r2, #7 80087be: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 80087c0: e00f b.n 80087e2 USBD_CtlError(pdev, req); 80087c2: 6839 ldr r1, [r7, #0] 80087c4: 6878 ldr r0, [r7, #4] 80087c6: f000 f9f7 bl 8008bb8 err++; 80087ca: 7afb ldrb r3, [r7, #11] 80087cc: 3301 adds r3, #1 80087ce: 72fb strb r3, [r7, #11] break; 80087d0: e007 b.n 80087e2 default: USBD_CtlError(pdev, req); 80087d2: 6839 ldr r1, [r7, #0] 80087d4: 6878 ldr r0, [r7, #4] 80087d6: f000 f9ef bl 8008bb8 err++; 80087da: 7afb ldrb r3, [r7, #11] 80087dc: 3301 adds r3, #1 80087de: 72fb strb r3, [r7, #11] break; 80087e0: bf00 nop } if (err != 0U) 80087e2: 7afb ldrb r3, [r7, #11] 80087e4: 2b00 cmp r3, #0 80087e6: d11e bne.n 8008826 { return; } if (req->wLength != 0U) 80087e8: 683b ldr r3, [r7, #0] 80087ea: 88db ldrh r3, [r3, #6] 80087ec: 2b00 cmp r3, #0 80087ee: d016 beq.n 800881e { if (len != 0U) 80087f0: 893b ldrh r3, [r7, #8] 80087f2: 2b00 cmp r3, #0 80087f4: d00e beq.n 8008814 { len = MIN(len, req->wLength); 80087f6: 683b ldr r3, [r7, #0] 80087f8: 88da ldrh r2, [r3, #6] 80087fa: 893b ldrh r3, [r7, #8] 80087fc: 4293 cmp r3, r2 80087fe: bf28 it cs 8008800: 4613 movcs r3, r2 8008802: b29b uxth r3, r3 8008804: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 8008806: 893b ldrh r3, [r7, #8] 8008808: 461a mov r2, r3 800880a: 68f9 ldr r1, [r7, #12] 800880c: 6878 ldr r0, [r7, #4] 800880e: f000 fa44 bl 8008c9a 8008812: e009 b.n 8008828 } else { USBD_CtlError(pdev, req); 8008814: 6839 ldr r1, [r7, #0] 8008816: 6878 ldr r0, [r7, #4] 8008818: f000 f9ce bl 8008bb8 800881c: e004 b.n 8008828 } } else { (void)USBD_CtlSendStatus(pdev); 800881e: 6878 ldr r0, [r7, #4] 8008820: f000 fa95 bl 8008d4e 8008824: e000 b.n 8008828 return; 8008826: bf00 nop } } 8008828: 3710 adds r7, #16 800882a: 46bd mov sp, r7 800882c: bd80 pop {r7, pc} 800882e: bf00 nop 08008830 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008830: b580 push {r7, lr} 8008832: b084 sub sp, #16 8008834: af00 add r7, sp, #0 8008836: 6078 str r0, [r7, #4] 8008838: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 800883a: 683b ldr r3, [r7, #0] 800883c: 889b ldrh r3, [r3, #4] 800883e: 2b00 cmp r3, #0 8008840: d131 bne.n 80088a6 8008842: 683b ldr r3, [r7, #0] 8008844: 88db ldrh r3, [r3, #6] 8008846: 2b00 cmp r3, #0 8008848: d12d bne.n 80088a6 800884a: 683b ldr r3, [r7, #0] 800884c: 885b ldrh r3, [r3, #2] 800884e: 2b7f cmp r3, #127 ; 0x7f 8008850: d829 bhi.n 80088a6 { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 8008852: 683b ldr r3, [r7, #0] 8008854: 885b ldrh r3, [r3, #2] 8008856: b2db uxtb r3, r3 8008858: f003 037f and.w r3, r3, #127 ; 0x7f 800885c: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 800885e: 687b ldr r3, [r7, #4] 8008860: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008864: b2db uxtb r3, r3 8008866: 2b03 cmp r3, #3 8008868: d104 bne.n 8008874 { USBD_CtlError(pdev, req); 800886a: 6839 ldr r1, [r7, #0] 800886c: 6878 ldr r0, [r7, #4] 800886e: f000 f9a3 bl 8008bb8 if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008872: e01d b.n 80088b0 } else { pdev->dev_address = dev_addr; 8008874: 687b ldr r3, [r7, #4] 8008876: 7bfa ldrb r2, [r7, #15] 8008878: f883 229e strb.w r2, [r3, #670] ; 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 800887c: 7bfb ldrb r3, [r7, #15] 800887e: 4619 mov r1, r3 8008880: 6878 ldr r0, [r7, #4] 8008882: f000 ff17 bl 80096b4 (void)USBD_CtlSendStatus(pdev); 8008886: 6878 ldr r0, [r7, #4] 8008888: f000 fa61 bl 8008d4e if (dev_addr != 0U) 800888c: 7bfb ldrb r3, [r7, #15] 800888e: 2b00 cmp r3, #0 8008890: d004 beq.n 800889c { pdev->dev_state = USBD_STATE_ADDRESSED; 8008892: 687b ldr r3, [r7, #4] 8008894: 2202 movs r2, #2 8008896: f883 229c strb.w r2, [r3, #668] ; 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 800889a: e009 b.n 80088b0 } else { pdev->dev_state = USBD_STATE_DEFAULT; 800889c: 687b ldr r3, [r7, #4] 800889e: 2201 movs r2, #1 80088a0: f883 229c strb.w r2, [r3, #668] ; 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 80088a4: e004 b.n 80088b0 } } } else { USBD_CtlError(pdev, req); 80088a6: 6839 ldr r1, [r7, #0] 80088a8: 6878 ldr r0, [r7, #4] 80088aa: f000 f985 bl 8008bb8 } } 80088ae: bf00 nop 80088b0: bf00 nop 80088b2: 3710 adds r7, #16 80088b4: 46bd mov sp, r7 80088b6: bd80 pop {r7, pc} 080088b8 : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80088b8: b580 push {r7, lr} 80088ba: b084 sub sp, #16 80088bc: af00 add r7, sp, #0 80088be: 6078 str r0, [r7, #4] 80088c0: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 80088c2: 2300 movs r3, #0 80088c4: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 80088c6: 683b ldr r3, [r7, #0] 80088c8: 885b ldrh r3, [r3, #2] 80088ca: b2da uxtb r2, r3 80088cc: 4b4c ldr r3, [pc, #304] ; (8008a00 ) 80088ce: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 80088d0: 4b4b ldr r3, [pc, #300] ; (8008a00 ) 80088d2: 781b ldrb r3, [r3, #0] 80088d4: 2b01 cmp r3, #1 80088d6: d905 bls.n 80088e4 { USBD_CtlError(pdev, req); 80088d8: 6839 ldr r1, [r7, #0] 80088da: 6878 ldr r0, [r7, #4] 80088dc: f000 f96c bl 8008bb8 return USBD_FAIL; 80088e0: 2303 movs r3, #3 80088e2: e088 b.n 80089f6 } switch (pdev->dev_state) 80088e4: 687b ldr r3, [r7, #4] 80088e6: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80088ea: b2db uxtb r3, r3 80088ec: 2b02 cmp r3, #2 80088ee: d002 beq.n 80088f6 80088f0: 2b03 cmp r3, #3 80088f2: d025 beq.n 8008940 80088f4: e071 b.n 80089da { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 80088f6: 4b42 ldr r3, [pc, #264] ; (8008a00 ) 80088f8: 781b ldrb r3, [r3, #0] 80088fa: 2b00 cmp r3, #0 80088fc: d01c beq.n 8008938 { pdev->dev_config = cfgidx; 80088fe: 4b40 ldr r3, [pc, #256] ; (8008a00 ) 8008900: 781b ldrb r3, [r3, #0] 8008902: 461a mov r2, r3 8008904: 687b ldr r3, [r7, #4] 8008906: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8008908: 4b3d ldr r3, [pc, #244] ; (8008a00 ) 800890a: 781b ldrb r3, [r3, #0] 800890c: 4619 mov r1, r3 800890e: 6878 ldr r0, [r7, #4] 8008910: f7ff f948 bl 8007ba4 8008914: 4603 mov r3, r0 8008916: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8008918: 7bfb ldrb r3, [r7, #15] 800891a: 2b00 cmp r3, #0 800891c: d004 beq.n 8008928 { USBD_CtlError(pdev, req); 800891e: 6839 ldr r1, [r7, #0] 8008920: 6878 ldr r0, [r7, #4] 8008922: f000 f949 bl 8008bb8 } else { (void)USBD_CtlSendStatus(pdev); } break; 8008926: e065 b.n 80089f4 (void)USBD_CtlSendStatus(pdev); 8008928: 6878 ldr r0, [r7, #4] 800892a: f000 fa10 bl 8008d4e pdev->dev_state = USBD_STATE_CONFIGURED; 800892e: 687b ldr r3, [r7, #4] 8008930: 2203 movs r2, #3 8008932: f883 229c strb.w r2, [r3, #668] ; 0x29c break; 8008936: e05d b.n 80089f4 (void)USBD_CtlSendStatus(pdev); 8008938: 6878 ldr r0, [r7, #4] 800893a: f000 fa08 bl 8008d4e break; 800893e: e059 b.n 80089f4 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 8008940: 4b2f ldr r3, [pc, #188] ; (8008a00 ) 8008942: 781b ldrb r3, [r3, #0] 8008944: 2b00 cmp r3, #0 8008946: d112 bne.n 800896e { pdev->dev_state = USBD_STATE_ADDRESSED; 8008948: 687b ldr r3, [r7, #4] 800894a: 2202 movs r2, #2 800894c: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->dev_config = cfgidx; 8008950: 4b2b ldr r3, [pc, #172] ; (8008a00 ) 8008952: 781b ldrb r3, [r3, #0] 8008954: 461a mov r2, r3 8008956: 687b ldr r3, [r7, #4] 8008958: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 800895a: 4b29 ldr r3, [pc, #164] ; (8008a00 ) 800895c: 781b ldrb r3, [r3, #0] 800895e: 4619 mov r1, r3 8008960: 6878 ldr r0, [r7, #4] 8008962: f7ff f93b bl 8007bdc (void)USBD_CtlSendStatus(pdev); 8008966: 6878 ldr r0, [r7, #4] 8008968: f000 f9f1 bl 8008d4e } else { (void)USBD_CtlSendStatus(pdev); } break; 800896c: e042 b.n 80089f4 else if (cfgidx != pdev->dev_config) 800896e: 4b24 ldr r3, [pc, #144] ; (8008a00 ) 8008970: 781b ldrb r3, [r3, #0] 8008972: 461a mov r2, r3 8008974: 687b ldr r3, [r7, #4] 8008976: 685b ldr r3, [r3, #4] 8008978: 429a cmp r2, r3 800897a: d02a beq.n 80089d2 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 800897c: 687b ldr r3, [r7, #4] 800897e: 685b ldr r3, [r3, #4] 8008980: b2db uxtb r3, r3 8008982: 4619 mov r1, r3 8008984: 6878 ldr r0, [r7, #4] 8008986: f7ff f929 bl 8007bdc pdev->dev_config = cfgidx; 800898a: 4b1d ldr r3, [pc, #116] ; (8008a00 ) 800898c: 781b ldrb r3, [r3, #0] 800898e: 461a mov r2, r3 8008990: 687b ldr r3, [r7, #4] 8008992: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8008994: 4b1a ldr r3, [pc, #104] ; (8008a00 ) 8008996: 781b ldrb r3, [r3, #0] 8008998: 4619 mov r1, r3 800899a: 6878 ldr r0, [r7, #4] 800899c: f7ff f902 bl 8007ba4 80089a0: 4603 mov r3, r0 80089a2: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 80089a4: 7bfb ldrb r3, [r7, #15] 80089a6: 2b00 cmp r3, #0 80089a8: d00f beq.n 80089ca USBD_CtlError(pdev, req); 80089aa: 6839 ldr r1, [r7, #0] 80089ac: 6878 ldr r0, [r7, #4] 80089ae: f000 f903 bl 8008bb8 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 80089b2: 687b ldr r3, [r7, #4] 80089b4: 685b ldr r3, [r3, #4] 80089b6: b2db uxtb r3, r3 80089b8: 4619 mov r1, r3 80089ba: 6878 ldr r0, [r7, #4] 80089bc: f7ff f90e bl 8007bdc pdev->dev_state = USBD_STATE_ADDRESSED; 80089c0: 687b ldr r3, [r7, #4] 80089c2: 2202 movs r2, #2 80089c4: f883 229c strb.w r2, [r3, #668] ; 0x29c break; 80089c8: e014 b.n 80089f4 (void)USBD_CtlSendStatus(pdev); 80089ca: 6878 ldr r0, [r7, #4] 80089cc: f000 f9bf bl 8008d4e break; 80089d0: e010 b.n 80089f4 (void)USBD_CtlSendStatus(pdev); 80089d2: 6878 ldr r0, [r7, #4] 80089d4: f000 f9bb bl 8008d4e break; 80089d8: e00c b.n 80089f4 default: USBD_CtlError(pdev, req); 80089da: 6839 ldr r1, [r7, #0] 80089dc: 6878 ldr r0, [r7, #4] 80089de: f000 f8eb bl 8008bb8 (void)USBD_ClrClassConfig(pdev, cfgidx); 80089e2: 4b07 ldr r3, [pc, #28] ; (8008a00 ) 80089e4: 781b ldrb r3, [r3, #0] 80089e6: 4619 mov r1, r3 80089e8: 6878 ldr r0, [r7, #4] 80089ea: f7ff f8f7 bl 8007bdc ret = USBD_FAIL; 80089ee: 2303 movs r3, #3 80089f0: 73fb strb r3, [r7, #15] break; 80089f2: bf00 nop } return ret; 80089f4: 7bfb ldrb r3, [r7, #15] } 80089f6: 4618 mov r0, r3 80089f8: 3710 adds r7, #16 80089fa: 46bd mov sp, r7 80089fc: bd80 pop {r7, pc} 80089fe: bf00 nop 8008a00: 24000210 .word 0x24000210 08008a04 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008a04: b580 push {r7, lr} 8008a06: b082 sub sp, #8 8008a08: af00 add r7, sp, #0 8008a0a: 6078 str r0, [r7, #4] 8008a0c: 6039 str r1, [r7, #0] if (req->wLength != 1U) 8008a0e: 683b ldr r3, [r7, #0] 8008a10: 88db ldrh r3, [r3, #6] 8008a12: 2b01 cmp r3, #1 8008a14: d004 beq.n 8008a20 { USBD_CtlError(pdev, req); 8008a16: 6839 ldr r1, [r7, #0] 8008a18: 6878 ldr r0, [r7, #4] 8008a1a: f000 f8cd bl 8008bb8 default: USBD_CtlError(pdev, req); break; } } } 8008a1e: e023 b.n 8008a68 switch (pdev->dev_state) 8008a20: 687b ldr r3, [r7, #4] 8008a22: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008a26: b2db uxtb r3, r3 8008a28: 2b02 cmp r3, #2 8008a2a: dc02 bgt.n 8008a32 8008a2c: 2b00 cmp r3, #0 8008a2e: dc03 bgt.n 8008a38 8008a30: e015 b.n 8008a5e 8008a32: 2b03 cmp r3, #3 8008a34: d00b beq.n 8008a4e 8008a36: e012 b.n 8008a5e pdev->dev_default_config = 0U; 8008a38: 687b ldr r3, [r7, #4] 8008a3a: 2200 movs r2, #0 8008a3c: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 8008a3e: 687b ldr r3, [r7, #4] 8008a40: 3308 adds r3, #8 8008a42: 2201 movs r2, #1 8008a44: 4619 mov r1, r3 8008a46: 6878 ldr r0, [r7, #4] 8008a48: f000 f927 bl 8008c9a break; 8008a4c: e00c b.n 8008a68 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 8008a4e: 687b ldr r3, [r7, #4] 8008a50: 3304 adds r3, #4 8008a52: 2201 movs r2, #1 8008a54: 4619 mov r1, r3 8008a56: 6878 ldr r0, [r7, #4] 8008a58: f000 f91f bl 8008c9a break; 8008a5c: e004 b.n 8008a68 USBD_CtlError(pdev, req); 8008a5e: 6839 ldr r1, [r7, #0] 8008a60: 6878 ldr r0, [r7, #4] 8008a62: f000 f8a9 bl 8008bb8 break; 8008a66: bf00 nop } 8008a68: bf00 nop 8008a6a: 3708 adds r7, #8 8008a6c: 46bd mov sp, r7 8008a6e: bd80 pop {r7, pc} 08008a70 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008a70: b580 push {r7, lr} 8008a72: b082 sub sp, #8 8008a74: af00 add r7, sp, #0 8008a76: 6078 str r0, [r7, #4] 8008a78: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8008a7a: 687b ldr r3, [r7, #4] 8008a7c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008a80: b2db uxtb r3, r3 8008a82: 3b01 subs r3, #1 8008a84: 2b02 cmp r3, #2 8008a86: d81e bhi.n 8008ac6 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 8008a88: 683b ldr r3, [r7, #0] 8008a8a: 88db ldrh r3, [r3, #6] 8008a8c: 2b02 cmp r3, #2 8008a8e: d004 beq.n 8008a9a { USBD_CtlError(pdev, req); 8008a90: 6839 ldr r1, [r7, #0] 8008a92: 6878 ldr r0, [r7, #4] 8008a94: f000 f890 bl 8008bb8 break; 8008a98: e01a b.n 8008ad0 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 8008a9a: 687b ldr r3, [r7, #4] 8008a9c: 2201 movs r2, #1 8008a9e: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif if (pdev->dev_remote_wakeup != 0U) 8008aa0: 687b ldr r3, [r7, #4] 8008aa2: f8d3 32a4 ldr.w r3, [r3, #676] ; 0x2a4 8008aa6: 2b00 cmp r3, #0 8008aa8: d005 beq.n 8008ab6 { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 8008aaa: 687b ldr r3, [r7, #4] 8008aac: 68db ldr r3, [r3, #12] 8008aae: f043 0202 orr.w r2, r3, #2 8008ab2: 687b ldr r3, [r7, #4] 8008ab4: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 8008ab6: 687b ldr r3, [r7, #4] 8008ab8: 330c adds r3, #12 8008aba: 2202 movs r2, #2 8008abc: 4619 mov r1, r3 8008abe: 6878 ldr r0, [r7, #4] 8008ac0: f000 f8eb bl 8008c9a break; 8008ac4: e004 b.n 8008ad0 default: USBD_CtlError(pdev, req); 8008ac6: 6839 ldr r1, [r7, #0] 8008ac8: 6878 ldr r0, [r7, #4] 8008aca: f000 f875 bl 8008bb8 break; 8008ace: bf00 nop } } 8008ad0: bf00 nop 8008ad2: 3708 adds r7, #8 8008ad4: 46bd mov sp, r7 8008ad6: bd80 pop {r7, pc} 08008ad8 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008ad8: b580 push {r7, lr} 8008ada: b082 sub sp, #8 8008adc: af00 add r7, sp, #0 8008ade: 6078 str r0, [r7, #4] 8008ae0: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8008ae2: 683b ldr r3, [r7, #0] 8008ae4: 885b ldrh r3, [r3, #2] 8008ae6: 2b01 cmp r3, #1 8008ae8: d106 bne.n 8008af8 { pdev->dev_remote_wakeup = 1U; 8008aea: 687b ldr r3, [r7, #4] 8008aec: 2201 movs r2, #1 8008aee: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 (void)USBD_CtlSendStatus(pdev); 8008af2: 6878 ldr r0, [r7, #4] 8008af4: f000 f92b bl 8008d4e } } 8008af8: bf00 nop 8008afa: 3708 adds r7, #8 8008afc: 46bd mov sp, r7 8008afe: bd80 pop {r7, pc} 08008b00 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008b00: b580 push {r7, lr} 8008b02: b082 sub sp, #8 8008b04: af00 add r7, sp, #0 8008b06: 6078 str r0, [r7, #4] 8008b08: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8008b0a: 687b ldr r3, [r7, #4] 8008b0c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008b10: b2db uxtb r3, r3 8008b12: 3b01 subs r3, #1 8008b14: 2b02 cmp r3, #2 8008b16: d80b bhi.n 8008b30 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8008b18: 683b ldr r3, [r7, #0] 8008b1a: 885b ldrh r3, [r3, #2] 8008b1c: 2b01 cmp r3, #1 8008b1e: d10c bne.n 8008b3a { pdev->dev_remote_wakeup = 0U; 8008b20: 687b ldr r3, [r7, #4] 8008b22: 2200 movs r2, #0 8008b24: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 (void)USBD_CtlSendStatus(pdev); 8008b28: 6878 ldr r0, [r7, #4] 8008b2a: f000 f910 bl 8008d4e } break; 8008b2e: e004 b.n 8008b3a default: USBD_CtlError(pdev, req); 8008b30: 6839 ldr r1, [r7, #0] 8008b32: 6878 ldr r0, [r7, #4] 8008b34: f000 f840 bl 8008bb8 break; 8008b38: e000 b.n 8008b3c break; 8008b3a: bf00 nop } } 8008b3c: bf00 nop 8008b3e: 3708 adds r7, #8 8008b40: 46bd mov sp, r7 8008b42: bd80 pop {r7, pc} 08008b44 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 8008b44: b580 push {r7, lr} 8008b46: b084 sub sp, #16 8008b48: af00 add r7, sp, #0 8008b4a: 6078 str r0, [r7, #4] 8008b4c: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 8008b4e: 683b ldr r3, [r7, #0] 8008b50: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 8008b52: 68fb ldr r3, [r7, #12] 8008b54: 781a ldrb r2, [r3, #0] 8008b56: 687b ldr r3, [r7, #4] 8008b58: 701a strb r2, [r3, #0] pbuff++; 8008b5a: 68fb ldr r3, [r7, #12] 8008b5c: 3301 adds r3, #1 8008b5e: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 8008b60: 68fb ldr r3, [r7, #12] 8008b62: 781a ldrb r2, [r3, #0] 8008b64: 687b ldr r3, [r7, #4] 8008b66: 705a strb r2, [r3, #1] pbuff++; 8008b68: 68fb ldr r3, [r7, #12] 8008b6a: 3301 adds r3, #1 8008b6c: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 8008b6e: 68f8 ldr r0, [r7, #12] 8008b70: f7ff fabb bl 80080ea 8008b74: 4603 mov r3, r0 8008b76: 461a mov r2, r3 8008b78: 687b ldr r3, [r7, #4] 8008b7a: 805a strh r2, [r3, #2] pbuff++; 8008b7c: 68fb ldr r3, [r7, #12] 8008b7e: 3301 adds r3, #1 8008b80: 60fb str r3, [r7, #12] pbuff++; 8008b82: 68fb ldr r3, [r7, #12] 8008b84: 3301 adds r3, #1 8008b86: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 8008b88: 68f8 ldr r0, [r7, #12] 8008b8a: f7ff faae bl 80080ea 8008b8e: 4603 mov r3, r0 8008b90: 461a mov r2, r3 8008b92: 687b ldr r3, [r7, #4] 8008b94: 809a strh r2, [r3, #4] pbuff++; 8008b96: 68fb ldr r3, [r7, #12] 8008b98: 3301 adds r3, #1 8008b9a: 60fb str r3, [r7, #12] pbuff++; 8008b9c: 68fb ldr r3, [r7, #12] 8008b9e: 3301 adds r3, #1 8008ba0: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 8008ba2: 68f8 ldr r0, [r7, #12] 8008ba4: f7ff faa1 bl 80080ea 8008ba8: 4603 mov r3, r0 8008baa: 461a mov r2, r3 8008bac: 687b ldr r3, [r7, #4] 8008bae: 80da strh r2, [r3, #6] } 8008bb0: bf00 nop 8008bb2: 3710 adds r7, #16 8008bb4: 46bd mov sp, r7 8008bb6: bd80 pop {r7, pc} 08008bb8 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008bb8: b580 push {r7, lr} 8008bba: b082 sub sp, #8 8008bbc: af00 add r7, sp, #0 8008bbe: 6078 str r0, [r7, #4] 8008bc0: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 8008bc2: 2180 movs r1, #128 ; 0x80 8008bc4: 6878 ldr r0, [r7, #4] 8008bc6: f000 fd0b bl 80095e0 (void)USBD_LL_StallEP(pdev, 0U); 8008bca: 2100 movs r1, #0 8008bcc: 6878 ldr r0, [r7, #4] 8008bce: f000 fd07 bl 80095e0 } 8008bd2: bf00 nop 8008bd4: 3708 adds r7, #8 8008bd6: 46bd mov sp, r7 8008bd8: bd80 pop {r7, pc} 08008bda : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 8008bda: b580 push {r7, lr} 8008bdc: b086 sub sp, #24 8008bde: af00 add r7, sp, #0 8008be0: 60f8 str r0, [r7, #12] 8008be2: 60b9 str r1, [r7, #8] 8008be4: 607a str r2, [r7, #4] uint8_t idx = 0U; 8008be6: 2300 movs r3, #0 8008be8: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 8008bea: 68fb ldr r3, [r7, #12] 8008bec: 2b00 cmp r3, #0 8008bee: d036 beq.n 8008c5e { return; } pdesc = desc; 8008bf0: 68fb ldr r3, [r7, #12] 8008bf2: 613b str r3, [r7, #16] *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U; 8008bf4: 6938 ldr r0, [r7, #16] 8008bf6: f000 f836 bl 8008c66 8008bfa: 4603 mov r3, r0 8008bfc: 3301 adds r3, #1 8008bfe: b29b uxth r3, r3 8008c00: 005b lsls r3, r3, #1 8008c02: b29a uxth r2, r3 8008c04: 687b ldr r3, [r7, #4] 8008c06: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 8008c08: 7dfb ldrb r3, [r7, #23] 8008c0a: 68ba ldr r2, [r7, #8] 8008c0c: 4413 add r3, r2 8008c0e: 687a ldr r2, [r7, #4] 8008c10: 7812 ldrb r2, [r2, #0] 8008c12: 701a strb r2, [r3, #0] idx++; 8008c14: 7dfb ldrb r3, [r7, #23] 8008c16: 3301 adds r3, #1 8008c18: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 8008c1a: 7dfb ldrb r3, [r7, #23] 8008c1c: 68ba ldr r2, [r7, #8] 8008c1e: 4413 add r3, r2 8008c20: 2203 movs r2, #3 8008c22: 701a strb r2, [r3, #0] idx++; 8008c24: 7dfb ldrb r3, [r7, #23] 8008c26: 3301 adds r3, #1 8008c28: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8008c2a: e013 b.n 8008c54 { unicode[idx] = *pdesc; 8008c2c: 7dfb ldrb r3, [r7, #23] 8008c2e: 68ba ldr r2, [r7, #8] 8008c30: 4413 add r3, r2 8008c32: 693a ldr r2, [r7, #16] 8008c34: 7812 ldrb r2, [r2, #0] 8008c36: 701a strb r2, [r3, #0] pdesc++; 8008c38: 693b ldr r3, [r7, #16] 8008c3a: 3301 adds r3, #1 8008c3c: 613b str r3, [r7, #16] idx++; 8008c3e: 7dfb ldrb r3, [r7, #23] 8008c40: 3301 adds r3, #1 8008c42: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 8008c44: 7dfb ldrb r3, [r7, #23] 8008c46: 68ba ldr r2, [r7, #8] 8008c48: 4413 add r3, r2 8008c4a: 2200 movs r2, #0 8008c4c: 701a strb r2, [r3, #0] idx++; 8008c4e: 7dfb ldrb r3, [r7, #23] 8008c50: 3301 adds r3, #1 8008c52: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8008c54: 693b ldr r3, [r7, #16] 8008c56: 781b ldrb r3, [r3, #0] 8008c58: 2b00 cmp r3, #0 8008c5a: d1e7 bne.n 8008c2c 8008c5c: e000 b.n 8008c60 return; 8008c5e: bf00 nop } } 8008c60: 3718 adds r7, #24 8008c62: 46bd mov sp, r7 8008c64: bd80 pop {r7, pc} 08008c66 : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 8008c66: b480 push {r7} 8008c68: b085 sub sp, #20 8008c6a: af00 add r7, sp, #0 8008c6c: 6078 str r0, [r7, #4] uint8_t len = 0U; 8008c6e: 2300 movs r3, #0 8008c70: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 8008c72: 687b ldr r3, [r7, #4] 8008c74: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 8008c76: e005 b.n 8008c84 { len++; 8008c78: 7bfb ldrb r3, [r7, #15] 8008c7a: 3301 adds r3, #1 8008c7c: 73fb strb r3, [r7, #15] pbuff++; 8008c7e: 68bb ldr r3, [r7, #8] 8008c80: 3301 adds r3, #1 8008c82: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 8008c84: 68bb ldr r3, [r7, #8] 8008c86: 781b ldrb r3, [r3, #0] 8008c88: 2b00 cmp r3, #0 8008c8a: d1f5 bne.n 8008c78 } return len; 8008c8c: 7bfb ldrb r3, [r7, #15] } 8008c8e: 4618 mov r0, r3 8008c90: 3714 adds r7, #20 8008c92: 46bd mov sp, r7 8008c94: f85d 7b04 ldr.w r7, [sp], #4 8008c98: 4770 bx lr 08008c9a : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8008c9a: b580 push {r7, lr} 8008c9c: b084 sub sp, #16 8008c9e: af00 add r7, sp, #0 8008ca0: 60f8 str r0, [r7, #12] 8008ca2: 60b9 str r1, [r7, #8] 8008ca4: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 8008ca6: 68fb ldr r3, [r7, #12] 8008ca8: 2202 movs r2, #2 8008caa: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->ep_in[0].total_length = len; 8008cae: 68fb ldr r3, [r7, #12] 8008cb0: 687a ldr r2, [r7, #4] 8008cb2: 619a str r2, [r3, #24] #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 8008cb4: 68fb ldr r3, [r7, #12] 8008cb6: 687a ldr r2, [r7, #4] 8008cb8: 61da str r2, [r3, #28] #endif /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8008cba: 687b ldr r3, [r7, #4] 8008cbc: 68ba ldr r2, [r7, #8] 8008cbe: 2100 movs r1, #0 8008cc0: 68f8 ldr r0, [r7, #12] 8008cc2: f000 fd16 bl 80096f2 return USBD_OK; 8008cc6: 2300 movs r3, #0 } 8008cc8: 4618 mov r0, r3 8008cca: 3710 adds r7, #16 8008ccc: 46bd mov sp, r7 8008cce: bd80 pop {r7, pc} 08008cd0 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8008cd0: b580 push {r7, lr} 8008cd2: b084 sub sp, #16 8008cd4: af00 add r7, sp, #0 8008cd6: 60f8 str r0, [r7, #12] 8008cd8: 60b9 str r1, [r7, #8] 8008cda: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8008cdc: 687b ldr r3, [r7, #4] 8008cde: 68ba ldr r2, [r7, #8] 8008ce0: 2100 movs r1, #0 8008ce2: 68f8 ldr r0, [r7, #12] 8008ce4: f000 fd05 bl 80096f2 return USBD_OK; 8008ce8: 2300 movs r3, #0 } 8008cea: 4618 mov r0, r3 8008cec: 3710 adds r7, #16 8008cee: 46bd mov sp, r7 8008cf0: bd80 pop {r7, pc} 08008cf2 : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8008cf2: b580 push {r7, lr} 8008cf4: b084 sub sp, #16 8008cf6: af00 add r7, sp, #0 8008cf8: 60f8 str r0, [r7, #12] 8008cfa: 60b9 str r1, [r7, #8] 8008cfc: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_OUT; 8008cfe: 68fb ldr r3, [r7, #12] 8008d00: 2203 movs r2, #3 8008d02: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->ep_out[0].total_length = len; 8008d06: 68fb ldr r3, [r7, #12] 8008d08: 687a ldr r2, [r7, #4] 8008d0a: f8c3 2158 str.w r2, [r3, #344] ; 0x158 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_out[0].rem_length = 0U; #else pdev->ep_out[0].rem_length = len; 8008d0e: 68fb ldr r3, [r7, #12] 8008d10: 687a ldr r2, [r7, #4] 8008d12: f8c3 215c str.w r2, [r3, #348] ; 0x15c #endif /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 8008d16: 687b ldr r3, [r7, #4] 8008d18: 68ba ldr r2, [r7, #8] 8008d1a: 2100 movs r1, #0 8008d1c: 68f8 ldr r0, [r7, #12] 8008d1e: f000 fd09 bl 8009734 return USBD_OK; 8008d22: 2300 movs r3, #0 } 8008d24: 4618 mov r0, r3 8008d26: 3710 adds r7, #16 8008d28: 46bd mov sp, r7 8008d2a: bd80 pop {r7, pc} 08008d2c : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8008d2c: b580 push {r7, lr} 8008d2e: b084 sub sp, #16 8008d30: af00 add r7, sp, #0 8008d32: 60f8 str r0, [r7, #12] 8008d34: 60b9 str r1, [r7, #8] 8008d36: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 8008d38: 687b ldr r3, [r7, #4] 8008d3a: 68ba ldr r2, [r7, #8] 8008d3c: 2100 movs r1, #0 8008d3e: 68f8 ldr r0, [r7, #12] 8008d40: f000 fcf8 bl 8009734 return USBD_OK; 8008d44: 2300 movs r3, #0 } 8008d46: 4618 mov r0, r3 8008d48: 3710 adds r7, #16 8008d4a: 46bd mov sp, r7 8008d4c: bd80 pop {r7, pc} 08008d4e : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 8008d4e: b580 push {r7, lr} 8008d50: b082 sub sp, #8 8008d52: af00 add r7, sp, #0 8008d54: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 8008d56: 687b ldr r3, [r7, #4] 8008d58: 2204 movs r2, #4 8008d5a: f8c3 2294 str.w r2, [r3, #660] ; 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 8008d5e: 2300 movs r3, #0 8008d60: 2200 movs r2, #0 8008d62: 2100 movs r1, #0 8008d64: 6878 ldr r0, [r7, #4] 8008d66: f000 fcc4 bl 80096f2 return USBD_OK; 8008d6a: 2300 movs r3, #0 } 8008d6c: 4618 mov r0, r3 8008d6e: 3708 adds r7, #8 8008d70: 46bd mov sp, r7 8008d72: bd80 pop {r7, pc} 08008d74 : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 8008d74: b580 push {r7, lr} 8008d76: b082 sub sp, #8 8008d78: af00 add r7, sp, #0 8008d7a: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 8008d7c: 687b ldr r3, [r7, #4] 8008d7e: 2205 movs r2, #5 8008d80: f8c3 2294 str.w r2, [r3, #660] ; 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008d84: 2300 movs r3, #0 8008d86: 2200 movs r2, #0 8008d88: 2100 movs r1, #0 8008d8a: 6878 ldr r0, [r7, #4] 8008d8c: f000 fcd2 bl 8009734 return USBD_OK; 8008d90: 2300 movs r3, #0 } 8008d92: 4618 mov r0, r3 8008d94: 3708 adds r7, #8 8008d96: 46bd mov sp, r7 8008d98: bd80 pop {r7, pc} ... 08008d9c : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 8008d9c: b580 push {r7, lr} 8008d9e: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceHS, &HS_Desc, DEVICE_HS) != USBD_OK) 8008da0: 2201 movs r2, #1 8008da2: 4913 ldr r1, [pc, #76] ; (8008df0 ) 8008da4: 4813 ldr r0, [pc, #76] ; (8008df4 ) 8008da6: f7fe fe8f bl 8007ac8 8008daa: 4603 mov r3, r0 8008dac: 2b00 cmp r3, #0 8008dae: d001 beq.n 8008db4 { Error_Handler(); 8008db0: f7f8 f982 bl 80010b8 } if (USBD_RegisterClass(&hUsbDeviceHS, &USBD_CDC) != USBD_OK) 8008db4: 4910 ldr r1, [pc, #64] ; (8008df8 ) 8008db6: 480f ldr r0, [pc, #60] ; (8008df4 ) 8008db8: f7fe feb6 bl 8007b28 8008dbc: 4603 mov r3, r0 8008dbe: 2b00 cmp r3, #0 8008dc0: d001 beq.n 8008dc6 { Error_Handler(); 8008dc2: f7f8 f979 bl 80010b8 } if (USBD_CDC_RegisterInterface(&hUsbDeviceHS, &USBD_Interface_fops_HS) != USBD_OK) 8008dc6: 490d ldr r1, [pc, #52] ; (8008dfc ) 8008dc8: 480a ldr r0, [pc, #40] ; (8008df4 ) 8008dca: f7fe fdd7 bl 800797c 8008dce: 4603 mov r3, r0 8008dd0: 2b00 cmp r3, #0 8008dd2: d001 beq.n 8008dd8 { Error_Handler(); 8008dd4: f7f8 f970 bl 80010b8 } if (USBD_Start(&hUsbDeviceHS) != USBD_OK) 8008dd8: 4806 ldr r0, [pc, #24] ; (8008df4 ) 8008dda: f7fe fecc bl 8007b76 8008dde: 4603 mov r3, r0 8008de0: 2b00 cmp r3, #0 8008de2: d001 beq.n 8008de8 { Error_Handler(); 8008de4: f7f8 f968 bl 80010b8 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ HAL_PWREx_EnableUSBVoltageDetector(); 8008de8: f7fa f8fe bl 8002fe8 /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 8008dec: bf00 nop 8008dee: bd80 pop {r7, pc} 8008df0: 24000134 .word 0x24000134 8008df4: 2400048c .word 0x2400048c 8008df8: 2400001c .word 0x2400001c 8008dfc: 24000120 .word 0x24000120 08008e00 : /** * @brief Initializes the CDC media low layer over the USB HS IP * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Init_HS(void) { 8008e00: b580 push {r7, lr} 8008e02: af00 add r7, sp, #0 /* USER CODE BEGIN 8 */ /* Set Application Buffers */ USBD_CDC_SetTxBuffer(&hUsbDeviceHS, UserTxBufferHS, 0); 8008e04: 2200 movs r2, #0 8008e06: 4905 ldr r1, [pc, #20] ; (8008e1c ) 8008e08: 4805 ldr r0, [pc, #20] ; (8008e20 ) 8008e0a: f7fe fdcc bl 80079a6 USBD_CDC_SetRxBuffer(&hUsbDeviceHS, UserRxBufferHS); 8008e0e: 4905 ldr r1, [pc, #20] ; (8008e24 ) 8008e10: 4803 ldr r0, [pc, #12] ; (8008e20 ) 8008e12: f7fe fde6 bl 80079e2 return (USBD_OK); 8008e16: 2300 movs r3, #0 /* USER CODE END 8 */ } 8008e18: 4618 mov r0, r3 8008e1a: bd80 pop {r7, pc} 8008e1c: 24000f5c .word 0x24000f5c 8008e20: 2400048c .word 0x2400048c 8008e24: 2400075c .word 0x2400075c 08008e28 : * @brief DeInitializes the CDC media low layer * @param None * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_DeInit_HS(void) { 8008e28: b480 push {r7} 8008e2a: af00 add r7, sp, #0 /* USER CODE BEGIN 9 */ return (USBD_OK); 8008e2c: 2300 movs r3, #0 /* USER CODE END 9 */ } 8008e2e: 4618 mov r0, r3 8008e30: 46bd mov sp, r7 8008e32: f85d 7b04 ldr.w r7, [sp], #4 8008e36: 4770 bx lr 08008e38 : * @param pbuf: Buffer containing command data (request parameters) * @param length: Number of data to be sent (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Control_HS(uint8_t cmd, uint8_t* pbuf, uint16_t length) { 8008e38: b480 push {r7} 8008e3a: b083 sub sp, #12 8008e3c: af00 add r7, sp, #0 8008e3e: 4603 mov r3, r0 8008e40: 6039 str r1, [r7, #0] 8008e42: 71fb strb r3, [r7, #7] 8008e44: 4613 mov r3, r2 8008e46: 80bb strh r3, [r7, #4] /* USER CODE BEGIN 10 */ switch(cmd) 8008e48: 79fb ldrb r3, [r7, #7] 8008e4a: 2b23 cmp r3, #35 ; 0x23 8008e4c: d84a bhi.n 8008ee4 8008e4e: a201 add r2, pc, #4 ; (adr r2, 8008e54 ) 8008e50: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008e54: 08008ee5 .word 0x08008ee5 8008e58: 08008ee5 .word 0x08008ee5 8008e5c: 08008ee5 .word 0x08008ee5 8008e60: 08008ee5 .word 0x08008ee5 8008e64: 08008ee5 .word 0x08008ee5 8008e68: 08008ee5 .word 0x08008ee5 8008e6c: 08008ee5 .word 0x08008ee5 8008e70: 08008ee5 .word 0x08008ee5 8008e74: 08008ee5 .word 0x08008ee5 8008e78: 08008ee5 .word 0x08008ee5 8008e7c: 08008ee5 .word 0x08008ee5 8008e80: 08008ee5 .word 0x08008ee5 8008e84: 08008ee5 .word 0x08008ee5 8008e88: 08008ee5 .word 0x08008ee5 8008e8c: 08008ee5 .word 0x08008ee5 8008e90: 08008ee5 .word 0x08008ee5 8008e94: 08008ee5 .word 0x08008ee5 8008e98: 08008ee5 .word 0x08008ee5 8008e9c: 08008ee5 .word 0x08008ee5 8008ea0: 08008ee5 .word 0x08008ee5 8008ea4: 08008ee5 .word 0x08008ee5 8008ea8: 08008ee5 .word 0x08008ee5 8008eac: 08008ee5 .word 0x08008ee5 8008eb0: 08008ee5 .word 0x08008ee5 8008eb4: 08008ee5 .word 0x08008ee5 8008eb8: 08008ee5 .word 0x08008ee5 8008ebc: 08008ee5 .word 0x08008ee5 8008ec0: 08008ee5 .word 0x08008ee5 8008ec4: 08008ee5 .word 0x08008ee5 8008ec8: 08008ee5 .word 0x08008ee5 8008ecc: 08008ee5 .word 0x08008ee5 8008ed0: 08008ee5 .word 0x08008ee5 8008ed4: 08008ee5 .word 0x08008ee5 8008ed8: 08008ee5 .word 0x08008ee5 8008edc: 08008ee5 .word 0x08008ee5 8008ee0: 08008ee5 .word 0x08008ee5 case CDC_SEND_BREAK: break; default: break; 8008ee4: bf00 nop } return (USBD_OK); 8008ee6: 2300 movs r3, #0 /* USER CODE END 10 */ } 8008ee8: 4618 mov r0, r3 8008eea: 370c adds r7, #12 8008eec: 46bd mov sp, r7 8008eee: f85d 7b04 ldr.w r7, [sp], #4 8008ef2: 4770 bx lr 08008ef4 : * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAILL */ static int8_t CDC_Receive_HS(uint8_t* Buf, uint32_t *Len) { 8008ef4: b580 push {r7, lr} 8008ef6: b082 sub sp, #8 8008ef8: af00 add r7, sp, #0 8008efa: 6078 str r0, [r7, #4] 8008efc: 6039 str r1, [r7, #0] /* USER CODE BEGIN 11 */ USBD_CDC_SetRxBuffer(&hUsbDeviceHS, &Buf[0]); 8008efe: 6879 ldr r1, [r7, #4] 8008f00: 4805 ldr r0, [pc, #20] ; (8008f18 ) 8008f02: f7fe fd6e bl 80079e2 USBD_CDC_ReceivePacket(&hUsbDeviceHS); 8008f06: 4804 ldr r0, [pc, #16] ; (8008f18 ) 8008f08: f7fe fdb4 bl 8007a74 return (USBD_OK); 8008f0c: 2300 movs r3, #0 /* USER CODE END 11 */ } 8008f0e: 4618 mov r0, r3 8008f10: 3708 adds r7, #8 8008f12: 46bd mov sp, r7 8008f14: bd80 pop {r7, pc} 8008f16: bf00 nop 8008f18: 2400048c .word 0x2400048c 08008f1c : * @param Buf: Buffer of data to be sent * @param Len: Number of data to be sent (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY */ uint8_t CDC_Transmit_HS(uint8_t* Buf, uint16_t Len) { 8008f1c: b580 push {r7, lr} 8008f1e: b084 sub sp, #16 8008f20: af00 add r7, sp, #0 8008f22: 6078 str r0, [r7, #4] 8008f24: 460b mov r3, r1 8008f26: 807b strh r3, [r7, #2] uint8_t result = USBD_OK; 8008f28: 2300 movs r3, #0 8008f2a: 73fb strb r3, [r7, #15] /* USER CODE BEGIN 12 */ USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceHS.pClassData; 8008f2c: 4b0d ldr r3, [pc, #52] ; (8008f64 ) 8008f2e: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8008f32: 60bb str r3, [r7, #8] if (hcdc->TxState != 0){ 8008f34: 68bb ldr r3, [r7, #8] 8008f36: f8d3 3214 ldr.w r3, [r3, #532] ; 0x214 8008f3a: 2b00 cmp r3, #0 8008f3c: d001 beq.n 8008f42 return USBD_BUSY; 8008f3e: 2301 movs r3, #1 8008f40: e00b b.n 8008f5a } USBD_CDC_SetTxBuffer(&hUsbDeviceHS, Buf, Len); 8008f42: 887b ldrh r3, [r7, #2] 8008f44: 461a mov r2, r3 8008f46: 6879 ldr r1, [r7, #4] 8008f48: 4806 ldr r0, [pc, #24] ; (8008f64 ) 8008f4a: f7fe fd2c bl 80079a6 result = USBD_CDC_TransmitPacket(&hUsbDeviceHS); 8008f4e: 4805 ldr r0, [pc, #20] ; (8008f64 ) 8008f50: f7fe fd60 bl 8007a14 8008f54: 4603 mov r3, r0 8008f56: 73fb strb r3, [r7, #15] /* USER CODE END 12 */ return result; 8008f58: 7bfb ldrb r3, [r7, #15] } 8008f5a: 4618 mov r0, r3 8008f5c: 3710 adds r7, #16 8008f5e: 46bd mov sp, r7 8008f60: bd80 pop {r7, pc} 8008f62: bf00 nop 8008f64: 2400048c .word 0x2400048c 08008f68 : * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_TransmitCplt_HS(uint8_t *Buf, uint32_t *Len, uint8_t epnum) { 8008f68: b480 push {r7} 8008f6a: b087 sub sp, #28 8008f6c: af00 add r7, sp, #0 8008f6e: 60f8 str r0, [r7, #12] 8008f70: 60b9 str r1, [r7, #8] 8008f72: 4613 mov r3, r2 8008f74: 71fb strb r3, [r7, #7] uint8_t result = USBD_OK; 8008f76: 2300 movs r3, #0 8008f78: 75fb strb r3, [r7, #23] /* USER CODE BEGIN 14 */ UNUSED(Buf); UNUSED(Len); UNUSED(epnum); /* USER CODE END 14 */ return result; 8008f7a: f997 3017 ldrsb.w r3, [r7, #23] } 8008f7e: 4618 mov r0, r3 8008f80: 371c adds r7, #28 8008f82: 46bd mov sp, r7 8008f84: f85d 7b04 ldr.w r7, [sp], #4 8008f88: 4770 bx lr ... 08008f8c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8008f8c: b480 push {r7} 8008f8e: b083 sub sp, #12 8008f90: af00 add r7, sp, #0 8008f92: 4603 mov r3, r0 8008f94: 6039 str r1, [r7, #0] 8008f96: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_HS_DeviceDesc); 8008f98: 683b ldr r3, [r7, #0] 8008f9a: 2212 movs r2, #18 8008f9c: 801a strh r2, [r3, #0] return USBD_HS_DeviceDesc; 8008f9e: 4b03 ldr r3, [pc, #12] ; (8008fac ) } 8008fa0: 4618 mov r0, r3 8008fa2: 370c adds r7, #12 8008fa4: 46bd mov sp, r7 8008fa6: f85d 7b04 ldr.w r7, [sp], #4 8008faa: 4770 bx lr 8008fac: 24000150 .word 0x24000150 08008fb0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8008fb0: b480 push {r7} 8008fb2: b083 sub sp, #12 8008fb4: af00 add r7, sp, #0 8008fb6: 4603 mov r3, r0 8008fb8: 6039 str r1, [r7, #0] 8008fba: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 8008fbc: 683b ldr r3, [r7, #0] 8008fbe: 2204 movs r2, #4 8008fc0: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 8008fc2: 4b03 ldr r3, [pc, #12] ; (8008fd0 ) } 8008fc4: 4618 mov r0, r3 8008fc6: 370c adds r7, #12 8008fc8: 46bd mov sp, r7 8008fca: f85d 7b04 ldr.w r7, [sp], #4 8008fce: 4770 bx lr 8008fd0: 24000164 .word 0x24000164 08008fd4 : * @param speed : current device speed * @param length : pointer to data length variable * @retval pointer to descriptor buffer */ uint8_t * USBD_HS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8008fd4: b580 push {r7, lr} 8008fd6: b082 sub sp, #8 8008fd8: af00 add r7, sp, #0 8008fda: 4603 mov r3, r0 8008fdc: 6039 str r1, [r7, #0] 8008fde: 71fb strb r3, [r7, #7] if(speed == 0) 8008fe0: 79fb ldrb r3, [r7, #7] 8008fe2: 2b00 cmp r3, #0 8008fe4: d105 bne.n 8008ff2 { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_HS, USBD_StrDesc, length); 8008fe6: 683a ldr r2, [r7, #0] 8008fe8: 4907 ldr r1, [pc, #28] ; (8009008 ) 8008fea: 4808 ldr r0, [pc, #32] ; (800900c ) 8008fec: f7ff fdf5 bl 8008bda 8008ff0: e004 b.n 8008ffc } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_HS, USBD_StrDesc, length); 8008ff2: 683a ldr r2, [r7, #0] 8008ff4: 4904 ldr r1, [pc, #16] ; (8009008 ) 8008ff6: 4805 ldr r0, [pc, #20] ; (800900c ) 8008ff8: f7ff fdef bl 8008bda } return USBD_StrDesc; 8008ffc: 4b02 ldr r3, [pc, #8] ; (8009008 ) } 8008ffe: 4618 mov r0, r3 8009000: 3708 adds r7, #8 8009002: 46bd mov sp, r7 8009004: bd80 pop {r7, pc} 8009006: bf00 nop 8009008: 2400175c .word 0x2400175c 800900c: 0800a830 .word 0x0800a830 08009010 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009010: b580 push {r7, lr} 8009012: b082 sub sp, #8 8009014: af00 add r7, sp, #0 8009016: 4603 mov r3, r0 8009018: 6039 str r1, [r7, #0] 800901a: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 800901c: 683a ldr r2, [r7, #0] 800901e: 4904 ldr r1, [pc, #16] ; (8009030 ) 8009020: 4804 ldr r0, [pc, #16] ; (8009034 ) 8009022: f7ff fdda bl 8008bda return USBD_StrDesc; 8009026: 4b02 ldr r3, [pc, #8] ; (8009030 ) } 8009028: 4618 mov r0, r3 800902a: 3708 adds r7, #8 800902c: 46bd mov sp, r7 800902e: bd80 pop {r7, pc} 8009030: 2400175c .word 0x2400175c 8009034: 0800a848 .word 0x0800a848 08009038 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009038: b580 push {r7, lr} 800903a: b082 sub sp, #8 800903c: af00 add r7, sp, #0 800903e: 4603 mov r3, r0 8009040: 6039 str r1, [r7, #0] 8009042: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 8009044: 683b ldr r3, [r7, #0] 8009046: 221a movs r2, #26 8009048: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 800904a: f000 f843 bl 80090d4 /* USER CODE BEGIN USBD_HS_SerialStrDescriptor */ /* USER CODE END USBD_HS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 800904e: 4b02 ldr r3, [pc, #8] ; (8009058 ) } 8009050: 4618 mov r0, r3 8009052: 3708 adds r7, #8 8009054: 46bd mov sp, r7 8009056: bd80 pop {r7, pc} 8009058: 24000168 .word 0x24000168 0800905c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800905c: b580 push {r7, lr} 800905e: b082 sub sp, #8 8009060: af00 add r7, sp, #0 8009062: 4603 mov r3, r0 8009064: 6039 str r1, [r7, #0] 8009066: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 8009068: 79fb ldrb r3, [r7, #7] 800906a: 2b00 cmp r3, #0 800906c: d105 bne.n 800907a { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_HS, USBD_StrDesc, length); 800906e: 683a ldr r2, [r7, #0] 8009070: 4907 ldr r1, [pc, #28] ; (8009090 ) 8009072: 4808 ldr r0, [pc, #32] ; (8009094 ) 8009074: f7ff fdb1 bl 8008bda 8009078: e004 b.n 8009084 } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_HS, USBD_StrDesc, length); 800907a: 683a ldr r2, [r7, #0] 800907c: 4904 ldr r1, [pc, #16] ; (8009090 ) 800907e: 4805 ldr r0, [pc, #20] ; (8009094 ) 8009080: f7ff fdab bl 8008bda } return USBD_StrDesc; 8009084: 4b02 ldr r3, [pc, #8] ; (8009090 ) } 8009086: 4618 mov r0, r3 8009088: 3708 adds r7, #8 800908a: 46bd mov sp, r7 800908c: bd80 pop {r7, pc} 800908e: bf00 nop 8009090: 2400175c .word 0x2400175c 8009094: 0800a85c .word 0x0800a85c 08009098 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009098: b580 push {r7, lr} 800909a: b082 sub sp, #8 800909c: af00 add r7, sp, #0 800909e: 4603 mov r3, r0 80090a0: 6039 str r1, [r7, #0] 80090a2: 71fb strb r3, [r7, #7] if(speed == 0) 80090a4: 79fb ldrb r3, [r7, #7] 80090a6: 2b00 cmp r3, #0 80090a8: d105 bne.n 80090b6 { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_HS, USBD_StrDesc, length); 80090aa: 683a ldr r2, [r7, #0] 80090ac: 4907 ldr r1, [pc, #28] ; (80090cc ) 80090ae: 4808 ldr r0, [pc, #32] ; (80090d0 ) 80090b0: f7ff fd93 bl 8008bda 80090b4: e004 b.n 80090c0 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_HS, USBD_StrDesc, length); 80090b6: 683a ldr r2, [r7, #0] 80090b8: 4904 ldr r1, [pc, #16] ; (80090cc ) 80090ba: 4805 ldr r0, [pc, #20] ; (80090d0 ) 80090bc: f7ff fd8d bl 8008bda } return USBD_StrDesc; 80090c0: 4b02 ldr r3, [pc, #8] ; (80090cc ) } 80090c2: 4618 mov r0, r3 80090c4: 3708 adds r7, #8 80090c6: 46bd mov sp, r7 80090c8: bd80 pop {r7, pc} 80090ca: bf00 nop 80090cc: 2400175c .word 0x2400175c 80090d0: 0800a868 .word 0x0800a868 080090d4 : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 80090d4: b580 push {r7, lr} 80090d6: b084 sub sp, #16 80090d8: af00 add r7, sp, #0 uint32_t deviceserial0, deviceserial1, deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 80090da: 4b0f ldr r3, [pc, #60] ; (8009118 ) 80090dc: 681b ldr r3, [r3, #0] 80090de: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 80090e0: 4b0e ldr r3, [pc, #56] ; (800911c ) 80090e2: 681b ldr r3, [r3, #0] 80090e4: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 80090e6: 4b0e ldr r3, [pc, #56] ; (8009120 ) 80090e8: 681b ldr r3, [r3, #0] 80090ea: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 80090ec: 68fa ldr r2, [r7, #12] 80090ee: 687b ldr r3, [r7, #4] 80090f0: 4413 add r3, r2 80090f2: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 80090f4: 68fb ldr r3, [r7, #12] 80090f6: 2b00 cmp r3, #0 80090f8: d009 beq.n 800910e { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 80090fa: 2208 movs r2, #8 80090fc: 4909 ldr r1, [pc, #36] ; (8009124 ) 80090fe: 68f8 ldr r0, [r7, #12] 8009100: f000 f814 bl 800912c IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 8009104: 2204 movs r2, #4 8009106: 4908 ldr r1, [pc, #32] ; (8009128 ) 8009108: 68b8 ldr r0, [r7, #8] 800910a: f000 f80f bl 800912c } } 800910e: bf00 nop 8009110: 3710 adds r7, #16 8009112: 46bd mov sp, r7 8009114: bd80 pop {r7, pc} 8009116: bf00 nop 8009118: 1ff1e800 .word 0x1ff1e800 800911c: 1ff1e804 .word 0x1ff1e804 8009120: 1ff1e808 .word 0x1ff1e808 8009124: 2400016a .word 0x2400016a 8009128: 2400017a .word 0x2400017a 0800912c : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 800912c: b480 push {r7} 800912e: b087 sub sp, #28 8009130: af00 add r7, sp, #0 8009132: 60f8 str r0, [r7, #12] 8009134: 60b9 str r1, [r7, #8] 8009136: 4613 mov r3, r2 8009138: 71fb strb r3, [r7, #7] uint8_t idx = 0; 800913a: 2300 movs r3, #0 800913c: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 800913e: 2300 movs r3, #0 8009140: 75fb strb r3, [r7, #23] 8009142: e027 b.n 8009194 { if (((value >> 28)) < 0xA) 8009144: 68fb ldr r3, [r7, #12] 8009146: 0f1b lsrs r3, r3, #28 8009148: 2b09 cmp r3, #9 800914a: d80b bhi.n 8009164 { pbuf[2 * idx] = (value >> 28) + '0'; 800914c: 68fb ldr r3, [r7, #12] 800914e: 0f1b lsrs r3, r3, #28 8009150: b2da uxtb r2, r3 8009152: 7dfb ldrb r3, [r7, #23] 8009154: 005b lsls r3, r3, #1 8009156: 4619 mov r1, r3 8009158: 68bb ldr r3, [r7, #8] 800915a: 440b add r3, r1 800915c: 3230 adds r2, #48 ; 0x30 800915e: b2d2 uxtb r2, r2 8009160: 701a strb r2, [r3, #0] 8009162: e00a b.n 800917a } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 8009164: 68fb ldr r3, [r7, #12] 8009166: 0f1b lsrs r3, r3, #28 8009168: b2da uxtb r2, r3 800916a: 7dfb ldrb r3, [r7, #23] 800916c: 005b lsls r3, r3, #1 800916e: 4619 mov r1, r3 8009170: 68bb ldr r3, [r7, #8] 8009172: 440b add r3, r1 8009174: 3237 adds r2, #55 ; 0x37 8009176: b2d2 uxtb r2, r2 8009178: 701a strb r2, [r3, #0] } value = value << 4; 800917a: 68fb ldr r3, [r7, #12] 800917c: 011b lsls r3, r3, #4 800917e: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 8009180: 7dfb ldrb r3, [r7, #23] 8009182: 005b lsls r3, r3, #1 8009184: 3301 adds r3, #1 8009186: 68ba ldr r2, [r7, #8] 8009188: 4413 add r3, r2 800918a: 2200 movs r2, #0 800918c: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 800918e: 7dfb ldrb r3, [r7, #23] 8009190: 3301 adds r3, #1 8009192: 75fb strb r3, [r7, #23] 8009194: 7dfa ldrb r2, [r7, #23] 8009196: 79fb ldrb r3, [r7, #7] 8009198: 429a cmp r2, r3 800919a: d3d3 bcc.n 8009144 } } 800919c: bf00 nop 800919e: bf00 nop 80091a0: 371c adds r7, #28 80091a2: 46bd mov sp, r7 80091a4: f85d 7b04 ldr.w r7, [sp], #4 80091a8: 4770 bx lr ... 080091ac : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 80091ac: b580 push {r7, lr} 80091ae: b0b6 sub sp, #216 ; 0xd8 80091b0: af00 add r7, sp, #0 80091b2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80091b4: f107 03c4 add.w r3, r7, #196 ; 0xc4 80091b8: 2200 movs r2, #0 80091ba: 601a str r2, [r3, #0] 80091bc: 605a str r2, [r3, #4] 80091be: 609a str r2, [r3, #8] 80091c0: 60da str r2, [r3, #12] 80091c2: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80091c4: f107 0310 add.w r3, r7, #16 80091c8: 22b4 movs r2, #180 ; 0xb4 80091ca: 2100 movs r1, #0 80091cc: 4618 mov r0, r3 80091ce: f000 fb83 bl 80098d8 if(pcdHandle->Instance==USB_OTG_HS) 80091d2: 687b ldr r3, [r7, #4] 80091d4: 681b ldr r3, [r3, #0] 80091d6: 4a2b ldr r2, [pc, #172] ; (8009284 ) 80091d8: 4293 cmp r3, r2 80091da: d14e bne.n 800927a /* USER CODE BEGIN USB_OTG_HS_MspInit 0 */ /* USER CODE END USB_OTG_HS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; 80091dc: f44f 2380 mov.w r3, #262144 ; 0x40000 80091e0: 613b str r3, [r7, #16] PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; 80091e2: f44f 1340 mov.w r3, #3145728 ; 0x300000 80091e6: f8c7 3090 str.w r3, [r7, #144] ; 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80091ea: f107 0310 add.w r3, r7, #16 80091ee: 4618 mov r0, r3 80091f0: f7fa fe16 bl 8003e20 80091f4: 4603 mov r3, r0 80091f6: 2b00 cmp r3, #0 80091f8: d001 beq.n 80091fe { Error_Handler(); 80091fa: f7f7 ff5d bl 80010b8 } /** Enable USB Voltage detector */ HAL_PWREx_EnableUSBVoltageDetector(); 80091fe: f7f9 fef3 bl 8002fe8 __HAL_RCC_GPIOA_CLK_ENABLE(); 8009202: 4b21 ldr r3, [pc, #132] ; (8009288 ) 8009204: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8009208: 4a1f ldr r2, [pc, #124] ; (8009288 ) 800920a: f043 0301 orr.w r3, r3, #1 800920e: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8009212: 4b1d ldr r3, [pc, #116] ; (8009288 ) 8009214: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8009218: f003 0301 and.w r3, r3, #1 800921c: 60fb str r3, [r7, #12] 800921e: 68fb ldr r3, [r7, #12] /**USB_OTG_HS GPIO Configuration PA10 ------> USB_OTG_HS_ID */ GPIO_InitStruct.Pin = USB_FS_ID_Pin; 8009220: f44f 6380 mov.w r3, #1024 ; 0x400 8009224: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009228: 2302 movs r3, #2 800922a: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 GPIO_InitStruct.Pull = GPIO_NOPULL; 800922e: 2300 movs r3, #0 8009230: f8c7 30cc str.w r3, [r7, #204] ; 0xcc GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8009234: 2300 movs r3, #0 8009236: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_HS; 800923a: 230a movs r3, #10 800923c: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 HAL_GPIO_Init(USB_FS_ID_GPIO_Port, &GPIO_InitStruct); 8009240: f107 03c4 add.w r3, r7, #196 ; 0xc4 8009244: 4619 mov r1, r3 8009246: 4811 ldr r0, [pc, #68] ; (800928c ) 8009248: f7f8 faea bl 8001820 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); 800924c: 4b0e ldr r3, [pc, #56] ; (8009288 ) 800924e: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 8009252: 4a0d ldr r2, [pc, #52] ; (8009288 ) 8009254: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8009258: f8c2 30d8 str.w r3, [r2, #216] ; 0xd8 800925c: 4b0a ldr r3, [pc, #40] ; (8009288 ) 800925e: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 8009262: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8009266: 60bb str r3, [r7, #8] 8009268: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_HS_IRQn, 0, 0); 800926a: 2200 movs r2, #0 800926c: 2100 movs r1, #0 800926e: 204d movs r0, #77 ; 0x4d 8009270: f7f8 faa1 bl 80017b6 HAL_NVIC_EnableIRQ(OTG_HS_IRQn); 8009274: 204d movs r0, #77 ; 0x4d 8009276: f7f8 fab8 bl 80017ea /* USER CODE BEGIN USB_OTG_HS_MspInit 1 */ /* USER CODE END USB_OTG_HS_MspInit 1 */ } } 800927a: bf00 nop 800927c: 37d8 adds r7, #216 ; 0xd8 800927e: 46bd mov sp, r7 8009280: bd80 pop {r7, pc} 8009282: bf00 nop 8009284: 40040000 .word 0x40040000 8009288: 58024400 .word 0x58024400 800928c: 58020000 .word 0x58020000 08009290 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009290: b580 push {r7, lr} 8009292: b082 sub sp, #8 8009294: af00 add r7, sp, #0 8009296: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 8009298: 687b ldr r3, [r7, #4] 800929a: f8d3 2404 ldr.w r2, [r3, #1028] ; 0x404 800929e: 687b ldr r3, [r7, #4] 80092a0: f503 7371 add.w r3, r3, #964 ; 0x3c4 80092a4: 4619 mov r1, r3 80092a6: 4610 mov r0, r2 80092a8: f7fe fcb0 bl 8007c0c } 80092ac: bf00 nop 80092ae: 3708 adds r7, #8 80092b0: 46bd mov sp, r7 80092b2: bd80 pop {r7, pc} 080092b4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80092b4: b580 push {r7, lr} 80092b6: b082 sub sp, #8 80092b8: af00 add r7, sp, #0 80092ba: 6078 str r0, [r7, #4] 80092bc: 460b mov r3, r1 80092be: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 80092c0: 687b ldr r3, [r7, #4] 80092c2: f8d3 0404 ldr.w r0, [r3, #1028] ; 0x404 80092c6: 78fa ldrb r2, [r7, #3] 80092c8: 6879 ldr r1, [r7, #4] 80092ca: 4613 mov r3, r2 80092cc: 00db lsls r3, r3, #3 80092ce: 1a9b subs r3, r3, r2 80092d0: 009b lsls r3, r3, #2 80092d2: 440b add r3, r1 80092d4: f503 7302 add.w r3, r3, #520 ; 0x208 80092d8: 681a ldr r2, [r3, #0] 80092da: 78fb ldrb r3, [r7, #3] 80092dc: 4619 mov r1, r3 80092de: f7fe fcea bl 8007cb6 } 80092e2: bf00 nop 80092e4: 3708 adds r7, #8 80092e6: 46bd mov sp, r7 80092e8: bd80 pop {r7, pc} 080092ea : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80092ea: b580 push {r7, lr} 80092ec: b082 sub sp, #8 80092ee: af00 add r7, sp, #0 80092f0: 6078 str r0, [r7, #4] 80092f2: 460b mov r3, r1 80092f4: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 80092f6: 687b ldr r3, [r7, #4] 80092f8: f8d3 0404 ldr.w r0, [r3, #1028] ; 0x404 80092fc: 78fa ldrb r2, [r7, #3] 80092fe: 6879 ldr r1, [r7, #4] 8009300: 4613 mov r3, r2 8009302: 00db lsls r3, r3, #3 8009304: 1a9b subs r3, r3, r2 8009306: 009b lsls r3, r3, #2 8009308: 440b add r3, r1 800930a: 3348 adds r3, #72 ; 0x48 800930c: 681a ldr r2, [r3, #0] 800930e: 78fb ldrb r3, [r7, #3] 8009310: 4619 mov r1, r3 8009312: f7fe fd33 bl 8007d7c } 8009316: bf00 nop 8009318: 3708 adds r7, #8 800931a: 46bd mov sp, r7 800931c: bd80 pop {r7, pc} 0800931e : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800931e: b580 push {r7, lr} 8009320: b082 sub sp, #8 8009322: af00 add r7, sp, #0 8009324: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 8009326: 687b ldr r3, [r7, #4] 8009328: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 800932c: 4618 mov r0, r3 800932e: f7fe fe47 bl 8007fc0 } 8009332: bf00 nop 8009334: 3708 adds r7, #8 8009336: 46bd mov sp, r7 8009338: bd80 pop {r7, pc} 0800933a : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800933a: b580 push {r7, lr} 800933c: b084 sub sp, #16 800933e: af00 add r7, sp, #0 8009340: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 8009342: 2301 movs r3, #1 8009344: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 8009346: 687b ldr r3, [r7, #4] 8009348: 68db ldr r3, [r3, #12] 800934a: 2b00 cmp r3, #0 800934c: d102 bne.n 8009354 { speed = USBD_SPEED_HIGH; 800934e: 2300 movs r3, #0 8009350: 73fb strb r3, [r7, #15] 8009352: e008 b.n 8009366 } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 8009354: 687b ldr r3, [r7, #4] 8009356: 68db ldr r3, [r3, #12] 8009358: 2b02 cmp r3, #2 800935a: d102 bne.n 8009362 { speed = USBD_SPEED_FULL; 800935c: 2301 movs r3, #1 800935e: 73fb strb r3, [r7, #15] 8009360: e001 b.n 8009366 } else { Error_Handler(); 8009362: f7f7 fea9 bl 80010b8 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 8009366: 687b ldr r3, [r7, #4] 8009368: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 800936c: 7bfa ldrb r2, [r7, #15] 800936e: 4611 mov r1, r2 8009370: 4618 mov r0, r3 8009372: f7fe fde7 bl 8007f44 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 8009376: 687b ldr r3, [r7, #4] 8009378: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 800937c: 4618 mov r0, r3 800937e: f7fe fd93 bl 8007ea8 } 8009382: bf00 nop 8009384: 3710 adds r7, #16 8009386: 46bd mov sp, r7 8009388: bd80 pop {r7, pc} ... 0800938c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800938c: b580 push {r7, lr} 800938e: b082 sub sp, #8 8009390: af00 add r7, sp, #0 8009392: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 8009394: 687b ldr r3, [r7, #4] 8009396: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 800939a: 4618 mov r0, r3 800939c: f7fe fde2 bl 8007f64 __HAL_PCD_GATE_PHYCLOCK(hpcd); 80093a0: 687b ldr r3, [r7, #4] 80093a2: 681b ldr r3, [r3, #0] 80093a4: f503 6360 add.w r3, r3, #3584 ; 0xe00 80093a8: 681b ldr r3, [r3, #0] 80093aa: 687a ldr r2, [r7, #4] 80093ac: 6812 ldr r2, [r2, #0] 80093ae: f502 6260 add.w r2, r2, #3584 ; 0xe00 80093b2: f043 0301 orr.w r3, r3, #1 80093b6: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 80093b8: 687b ldr r3, [r7, #4] 80093ba: 6a1b ldr r3, [r3, #32] 80093bc: 2b00 cmp r3, #0 80093be: d005 beq.n 80093cc { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 80093c0: 4b04 ldr r3, [pc, #16] ; (80093d4 ) 80093c2: 691b ldr r3, [r3, #16] 80093c4: 4a03 ldr r2, [pc, #12] ; (80093d4 ) 80093c6: f043 0306 orr.w r3, r3, #6 80093ca: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 80093cc: bf00 nop 80093ce: 3708 adds r7, #8 80093d0: 46bd mov sp, r7 80093d2: bd80 pop {r7, pc} 80093d4: e000ed00 .word 0xe000ed00 080093d8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80093d8: b580 push {r7, lr} 80093da: b082 sub sp, #8 80093dc: af00 add r7, sp, #0 80093de: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 80093e0: 687b ldr r3, [r7, #4] 80093e2: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 80093e6: 4618 mov r0, r3 80093e8: f7fe fdd2 bl 8007f90 } 80093ec: bf00 nop 80093ee: 3708 adds r7, #8 80093f0: 46bd mov sp, r7 80093f2: bd80 pop {r7, pc} 080093f4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80093f4: b580 push {r7, lr} 80093f6: b082 sub sp, #8 80093f8: af00 add r7, sp, #0 80093fa: 6078 str r0, [r7, #4] 80093fc: 460b mov r3, r1 80093fe: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 8009400: 687b ldr r3, [r7, #4] 8009402: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8009406: 78fa ldrb r2, [r7, #3] 8009408: 4611 mov r1, r2 800940a: 4618 mov r0, r3 800940c: f7fe fe20 bl 8008050 } 8009410: bf00 nop 8009412: 3708 adds r7, #8 8009414: 46bd mov sp, r7 8009416: bd80 pop {r7, pc} 08009418 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009418: b580 push {r7, lr} 800941a: b082 sub sp, #8 800941c: af00 add r7, sp, #0 800941e: 6078 str r0, [r7, #4] 8009420: 460b mov r3, r1 8009422: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 8009424: 687b ldr r3, [r7, #4] 8009426: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 800942a: 78fa ldrb r2, [r7, #3] 800942c: 4611 mov r1, r2 800942e: 4618 mov r0, r3 8009430: f7fe fde8 bl 8008004 } 8009434: bf00 nop 8009436: 3708 adds r7, #8 8009438: 46bd mov sp, r7 800943a: bd80 pop {r7, pc} 0800943c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800943c: b580 push {r7, lr} 800943e: b082 sub sp, #8 8009440: af00 add r7, sp, #0 8009442: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 8009444: 687b ldr r3, [r7, #4] 8009446: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 800944a: 4618 mov r0, r3 800944c: f7fe fe26 bl 800809c } 8009450: bf00 nop 8009452: 3708 adds r7, #8 8009454: 46bd mov sp, r7 8009456: bd80 pop {r7, pc} 08009458 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009458: b580 push {r7, lr} 800945a: b082 sub sp, #8 800945c: af00 add r7, sp, #0 800945e: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 8009460: 687b ldr r3, [r7, #4] 8009462: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8009466: 4618 mov r0, r3 8009468: f7fe fe23 bl 80080b2 } 800946c: bf00 nop 800946e: 3708 adds r7, #8 8009470: 46bd mov sp, r7 8009472: bd80 pop {r7, pc} 08009474 : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 8009474: b580 push {r7, lr} 8009476: b082 sub sp, #8 8009478: af00 add r7, sp, #0 800947a: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_HS) { 800947c: 687b ldr r3, [r7, #4] 800947e: 781b ldrb r3, [r3, #0] 8009480: 2b01 cmp r3, #1 8009482: d143 bne.n 800950c /* Link the driver to the stack. */ hpcd_USB_OTG_HS.pData = pdev; 8009484: 4a24 ldr r2, [pc, #144] ; (8009518 ) 8009486: 687b ldr r3, [r7, #4] 8009488: f8c2 3404 str.w r3, [r2, #1028] ; 0x404 pdev->pData = &hpcd_USB_OTG_HS; 800948c: 687b ldr r3, [r7, #4] 800948e: 4a22 ldr r2, [pc, #136] ; (8009518 ) 8009490: f8c3 22c4 str.w r2, [r3, #708] ; 0x2c4 hpcd_USB_OTG_HS.Instance = USB_OTG_HS; 8009494: 4b20 ldr r3, [pc, #128] ; (8009518 ) 8009496: 4a21 ldr r2, [pc, #132] ; (800951c ) 8009498: 601a str r2, [r3, #0] hpcd_USB_OTG_HS.Init.dev_endpoints = 9; 800949a: 4b1f ldr r3, [pc, #124] ; (8009518 ) 800949c: 2209 movs r2, #9 800949e: 605a str r2, [r3, #4] hpcd_USB_OTG_HS.Init.speed = PCD_SPEED_FULL; 80094a0: 4b1d ldr r3, [pc, #116] ; (8009518 ) 80094a2: 2202 movs r2, #2 80094a4: 60da str r2, [r3, #12] hpcd_USB_OTG_HS.Init.dma_enable = DISABLE; 80094a6: 4b1c ldr r3, [pc, #112] ; (8009518 ) 80094a8: 2200 movs r2, #0 80094aa: 611a str r2, [r3, #16] hpcd_USB_OTG_HS.Init.phy_itface = USB_OTG_EMBEDDED_PHY; 80094ac: 4b1a ldr r3, [pc, #104] ; (8009518 ) 80094ae: 2202 movs r2, #2 80094b0: 619a str r2, [r3, #24] hpcd_USB_OTG_HS.Init.Sof_enable = DISABLE; 80094b2: 4b19 ldr r3, [pc, #100] ; (8009518 ) 80094b4: 2200 movs r2, #0 80094b6: 61da str r2, [r3, #28] hpcd_USB_OTG_HS.Init.low_power_enable = DISABLE; 80094b8: 4b17 ldr r3, [pc, #92] ; (8009518 ) 80094ba: 2200 movs r2, #0 80094bc: 621a str r2, [r3, #32] hpcd_USB_OTG_HS.Init.lpm_enable = DISABLE; 80094be: 4b16 ldr r3, [pc, #88] ; (8009518 ) 80094c0: 2200 movs r2, #0 80094c2: 625a str r2, [r3, #36] ; 0x24 hpcd_USB_OTG_HS.Init.battery_charging_enable = ENABLE; 80094c4: 4b14 ldr r3, [pc, #80] ; (8009518 ) 80094c6: 2201 movs r2, #1 80094c8: 629a str r2, [r3, #40] ; 0x28 hpcd_USB_OTG_HS.Init.vbus_sensing_enable = DISABLE; 80094ca: 4b13 ldr r3, [pc, #76] ; (8009518 ) 80094cc: 2200 movs r2, #0 80094ce: 62da str r2, [r3, #44] ; 0x2c hpcd_USB_OTG_HS.Init.use_dedicated_ep1 = DISABLE; 80094d0: 4b11 ldr r3, [pc, #68] ; (8009518 ) 80094d2: 2200 movs r2, #0 80094d4: 631a str r2, [r3, #48] ; 0x30 hpcd_USB_OTG_HS.Init.use_external_vbus = DISABLE; 80094d6: 4b10 ldr r3, [pc, #64] ; (8009518 ) 80094d8: 2200 movs r2, #0 80094da: 635a str r2, [r3, #52] ; 0x34 if (HAL_PCD_Init(&hpcd_USB_OTG_HS) != HAL_OK) 80094dc: 480e ldr r0, [pc, #56] ; (8009518 ) 80094de: f7f8 fb7a bl 8001bd6 80094e2: 4603 mov r3, r0 80094e4: 2b00 cmp r3, #0 80094e6: d001 beq.n 80094ec { Error_Handler( ); 80094e8: f7f7 fde6 bl 80010b8 HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_HS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /* USER CODE BEGIN TxRx_Configuration */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_HS, 0x200); 80094ec: f44f 7100 mov.w r1, #512 ; 0x200 80094f0: 4809 ldr r0, [pc, #36] ; (8009518 ) 80094f2: f7f9 fcfe bl 8002ef2 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x80); 80094f6: 2280 movs r2, #128 ; 0x80 80094f8: 2100 movs r1, #0 80094fa: 4807 ldr r0, [pc, #28] ; (8009518 ) 80094fc: f7f9 fcb2 bl 8002e64 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x174); 8009500: f44f 72ba mov.w r2, #372 ; 0x174 8009504: 2101 movs r1, #1 8009506: 4804 ldr r0, [pc, #16] ; (8009518 ) 8009508: f7f9 fcac bl 8002e64 /* USER CODE END TxRx_Configuration */ } return USBD_OK; 800950c: 2300 movs r3, #0 } 800950e: 4618 mov r0, r3 8009510: 3708 adds r7, #8 8009512: 46bd mov sp, r7 8009514: bd80 pop {r7, pc} 8009516: bf00 nop 8009518: 2400195c .word 0x2400195c 800951c: 40040000 .word 0x40040000 08009520 : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 8009520: b580 push {r7, lr} 8009522: b084 sub sp, #16 8009524: af00 add r7, sp, #0 8009526: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 8009528: 2300 movs r3, #0 800952a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800952c: 2300 movs r3, #0 800952e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 8009530: 687b ldr r3, [r7, #4] 8009532: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8009536: 4618 mov r0, r3 8009538: f7f8 fc71 bl 8001e1e 800953c: 4603 mov r3, r0 800953e: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8009540: 7bfb ldrb r3, [r7, #15] 8009542: 4618 mov r0, r3 8009544: f000 f942 bl 80097cc 8009548: 4603 mov r3, r0 800954a: 73bb strb r3, [r7, #14] return usb_status; 800954c: 7bbb ldrb r3, [r7, #14] } 800954e: 4618 mov r0, r3 8009550: 3710 adds r7, #16 8009552: 46bd mov sp, r7 8009554: bd80 pop {r7, pc} 08009556 : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 8009556: b580 push {r7, lr} 8009558: b084 sub sp, #16 800955a: af00 add r7, sp, #0 800955c: 6078 str r0, [r7, #4] 800955e: 4608 mov r0, r1 8009560: 4611 mov r1, r2 8009562: 461a mov r2, r3 8009564: 4603 mov r3, r0 8009566: 70fb strb r3, [r7, #3] 8009568: 460b mov r3, r1 800956a: 70bb strb r3, [r7, #2] 800956c: 4613 mov r3, r2 800956e: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 8009570: 2300 movs r3, #0 8009572: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8009574: 2300 movs r3, #0 8009576: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 8009578: 687b ldr r3, [r7, #4] 800957a: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4 800957e: 78bb ldrb r3, [r7, #2] 8009580: 883a ldrh r2, [r7, #0] 8009582: 78f9 ldrb r1, [r7, #3] 8009584: f7f9 f876 bl 8002674 8009588: 4603 mov r3, r0 800958a: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800958c: 7bfb ldrb r3, [r7, #15] 800958e: 4618 mov r0, r3 8009590: f000 f91c bl 80097cc 8009594: 4603 mov r3, r0 8009596: 73bb strb r3, [r7, #14] return usb_status; 8009598: 7bbb ldrb r3, [r7, #14] } 800959a: 4618 mov r0, r3 800959c: 3710 adds r7, #16 800959e: 46bd mov sp, r7 80095a0: bd80 pop {r7, pc} 080095a2 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 80095a2: b580 push {r7, lr} 80095a4: b084 sub sp, #16 80095a6: af00 add r7, sp, #0 80095a8: 6078 str r0, [r7, #4] 80095aa: 460b mov r3, r1 80095ac: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 80095ae: 2300 movs r3, #0 80095b0: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 80095b2: 2300 movs r3, #0 80095b4: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 80095b6: 687b ldr r3, [r7, #4] 80095b8: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 80095bc: 78fa ldrb r2, [r7, #3] 80095be: 4611 mov r1, r2 80095c0: 4618 mov r0, r3 80095c2: f7f9 f8bf bl 8002744 80095c6: 4603 mov r3, r0 80095c8: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 80095ca: 7bfb ldrb r3, [r7, #15] 80095cc: 4618 mov r0, r3 80095ce: f000 f8fd bl 80097cc 80095d2: 4603 mov r3, r0 80095d4: 73bb strb r3, [r7, #14] return usb_status; 80095d6: 7bbb ldrb r3, [r7, #14] } 80095d8: 4618 mov r0, r3 80095da: 3710 adds r7, #16 80095dc: 46bd mov sp, r7 80095de: bd80 pop {r7, pc} 080095e0 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 80095e0: b580 push {r7, lr} 80095e2: b084 sub sp, #16 80095e4: af00 add r7, sp, #0 80095e6: 6078 str r0, [r7, #4] 80095e8: 460b mov r3, r1 80095ea: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 80095ec: 2300 movs r3, #0 80095ee: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 80095f0: 2300 movs r3, #0 80095f2: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 80095f4: 687b ldr r3, [r7, #4] 80095f6: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 80095fa: 78fa ldrb r2, [r7, #3] 80095fc: 4611 mov r1, r2 80095fe: 4618 mov r0, r3 8009600: f7f9 f997 bl 8002932 8009604: 4603 mov r3, r0 8009606: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8009608: 7bfb ldrb r3, [r7, #15] 800960a: 4618 mov r0, r3 800960c: f000 f8de bl 80097cc 8009610: 4603 mov r3, r0 8009612: 73bb strb r3, [r7, #14] return usb_status; 8009614: 7bbb ldrb r3, [r7, #14] } 8009616: 4618 mov r0, r3 8009618: 3710 adds r7, #16 800961a: 46bd mov sp, r7 800961c: bd80 pop {r7, pc} 0800961e : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800961e: b580 push {r7, lr} 8009620: b084 sub sp, #16 8009622: af00 add r7, sp, #0 8009624: 6078 str r0, [r7, #4] 8009626: 460b mov r3, r1 8009628: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800962a: 2300 movs r3, #0 800962c: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800962e: 2300 movs r3, #0 8009630: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 8009632: 687b ldr r3, [r7, #4] 8009634: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8009638: 78fa ldrb r2, [r7, #3] 800963a: 4611 mov r1, r2 800963c: 4618 mov r0, r3 800963e: f7f9 f9dc bl 80029fa 8009642: 4603 mov r3, r0 8009644: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8009646: 7bfb ldrb r3, [r7, #15] 8009648: 4618 mov r0, r3 800964a: f000 f8bf bl 80097cc 800964e: 4603 mov r3, r0 8009650: 73bb strb r3, [r7, #14] return usb_status; 8009652: 7bbb ldrb r3, [r7, #14] } 8009654: 4618 mov r0, r3 8009656: 3710 adds r7, #16 8009658: 46bd mov sp, r7 800965a: bd80 pop {r7, pc} 0800965c : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800965c: b480 push {r7} 800965e: b085 sub sp, #20 8009660: af00 add r7, sp, #0 8009662: 6078 str r0, [r7, #4] 8009664: 460b mov r3, r1 8009666: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 8009668: 687b ldr r3, [r7, #4] 800966a: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 800966e: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 8009670: f997 3003 ldrsb.w r3, [r7, #3] 8009674: 2b00 cmp r3, #0 8009676: da0b bge.n 8009690 { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 8009678: 78fb ldrb r3, [r7, #3] 800967a: f003 027f and.w r2, r3, #127 ; 0x7f 800967e: 68f9 ldr r1, [r7, #12] 8009680: 4613 mov r3, r2 8009682: 00db lsls r3, r3, #3 8009684: 1a9b subs r3, r3, r2 8009686: 009b lsls r3, r3, #2 8009688: 440b add r3, r1 800968a: 333e adds r3, #62 ; 0x3e 800968c: 781b ldrb r3, [r3, #0] 800968e: e00b b.n 80096a8 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 8009690: 78fb ldrb r3, [r7, #3] 8009692: f003 027f and.w r2, r3, #127 ; 0x7f 8009696: 68f9 ldr r1, [r7, #12] 8009698: 4613 mov r3, r2 800969a: 00db lsls r3, r3, #3 800969c: 1a9b subs r3, r3, r2 800969e: 009b lsls r3, r3, #2 80096a0: 440b add r3, r1 80096a2: f503 73ff add.w r3, r3, #510 ; 0x1fe 80096a6: 781b ldrb r3, [r3, #0] } } 80096a8: 4618 mov r0, r3 80096aa: 3714 adds r7, #20 80096ac: 46bd mov sp, r7 80096ae: f85d 7b04 ldr.w r7, [sp], #4 80096b2: 4770 bx lr 080096b4 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 80096b4: b580 push {r7, lr} 80096b6: b084 sub sp, #16 80096b8: af00 add r7, sp, #0 80096ba: 6078 str r0, [r7, #4] 80096bc: 460b mov r3, r1 80096be: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 80096c0: 2300 movs r3, #0 80096c2: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 80096c4: 2300 movs r3, #0 80096c6: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 80096c8: 687b ldr r3, [r7, #4] 80096ca: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 80096ce: 78fa ldrb r2, [r7, #3] 80096d0: 4611 mov r1, r2 80096d2: 4618 mov r0, r3 80096d4: f7f8 ffa9 bl 800262a 80096d8: 4603 mov r3, r0 80096da: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 80096dc: 7bfb ldrb r3, [r7, #15] 80096de: 4618 mov r0, r3 80096e0: f000 f874 bl 80097cc 80096e4: 4603 mov r3, r0 80096e6: 73bb strb r3, [r7, #14] return usb_status; 80096e8: 7bbb ldrb r3, [r7, #14] } 80096ea: 4618 mov r0, r3 80096ec: 3710 adds r7, #16 80096ee: 46bd mov sp, r7 80096f0: bd80 pop {r7, pc} 080096f2 : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 80096f2: b580 push {r7, lr} 80096f4: b086 sub sp, #24 80096f6: af00 add r7, sp, #0 80096f8: 60f8 str r0, [r7, #12] 80096fa: 607a str r2, [r7, #4] 80096fc: 603b str r3, [r7, #0] 80096fe: 460b mov r3, r1 8009700: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 8009702: 2300 movs r3, #0 8009704: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 8009706: 2300 movs r3, #0 8009708: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 800970a: 68fb ldr r3, [r7, #12] 800970c: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4 8009710: 7af9 ldrb r1, [r7, #11] 8009712: 683b ldr r3, [r7, #0] 8009714: 687a ldr r2, [r7, #4] 8009716: f7f9 f8c2 bl 800289e 800971a: 4603 mov r3, r0 800971c: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800971e: 7dfb ldrb r3, [r7, #23] 8009720: 4618 mov r0, r3 8009722: f000 f853 bl 80097cc 8009726: 4603 mov r3, r0 8009728: 75bb strb r3, [r7, #22] return usb_status; 800972a: 7dbb ldrb r3, [r7, #22] } 800972c: 4618 mov r0, r3 800972e: 3718 adds r7, #24 8009730: 46bd mov sp, r7 8009732: bd80 pop {r7, pc} 08009734 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 8009734: b580 push {r7, lr} 8009736: b086 sub sp, #24 8009738: af00 add r7, sp, #0 800973a: 60f8 str r0, [r7, #12] 800973c: 607a str r2, [r7, #4] 800973e: 603b str r3, [r7, #0] 8009740: 460b mov r3, r1 8009742: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 8009744: 2300 movs r3, #0 8009746: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 8009748: 2300 movs r3, #0 800974a: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 800974c: 68fb ldr r3, [r7, #12] 800974e: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4 8009752: 7af9 ldrb r1, [r7, #11] 8009754: 683b ldr r3, [r7, #0] 8009756: 687a ldr r2, [r7, #4] 8009758: f7f9 f83e bl 80027d8 800975c: 4603 mov r3, r0 800975e: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 8009760: 7dfb ldrb r3, [r7, #23] 8009762: 4618 mov r0, r3 8009764: f000 f832 bl 80097cc 8009768: 4603 mov r3, r0 800976a: 75bb strb r3, [r7, #22] return usb_status; 800976c: 7dbb ldrb r3, [r7, #22] } 800976e: 4618 mov r0, r3 8009770: 3718 adds r7, #24 8009772: 46bd mov sp, r7 8009774: bd80 pop {r7, pc} 08009776 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Received Data Size */ uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 8009776: b580 push {r7, lr} 8009778: b082 sub sp, #8 800977a: af00 add r7, sp, #0 800977c: 6078 str r0, [r7, #4] 800977e: 460b mov r3, r1 8009780: 70fb strb r3, [r7, #3] return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); 8009782: 687b ldr r3, [r7, #4] 8009784: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8009788: 78fa ldrb r2, [r7, #3] 800978a: 4611 mov r1, r2 800978c: 4618 mov r0, r3 800978e: f7f9 f86e bl 800286e 8009792: 4603 mov r3, r0 } 8009794: 4618 mov r0, r3 8009796: 3708 adds r7, #8 8009798: 46bd mov sp, r7 800979a: bd80 pop {r7, pc} 0800979c : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 800979c: b480 push {r7} 800979e: b083 sub sp, #12 80097a0: af00 add r7, sp, #0 80097a2: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 80097a4: 4b03 ldr r3, [pc, #12] ; (80097b4 ) } 80097a6: 4618 mov r0, r3 80097a8: 370c adds r7, #12 80097aa: 46bd mov sp, r7 80097ac: f85d 7b04 ldr.w r7, [sp], #4 80097b0: 4770 bx lr 80097b2: bf00 nop 80097b4: 24000214 .word 0x24000214 080097b8 : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 80097b8: b480 push {r7} 80097ba: b083 sub sp, #12 80097bc: af00 add r7, sp, #0 80097be: 6078 str r0, [r7, #4] } 80097c0: bf00 nop 80097c2: 370c adds r7, #12 80097c4: 46bd mov sp, r7 80097c6: f85d 7b04 ldr.w r7, [sp], #4 80097ca: 4770 bx lr 080097cc : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 80097cc: b480 push {r7} 80097ce: b085 sub sp, #20 80097d0: af00 add r7, sp, #0 80097d2: 4603 mov r3, r0 80097d4: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 80097d6: 2300 movs r3, #0 80097d8: 73fb strb r3, [r7, #15] switch (hal_status) 80097da: 79fb ldrb r3, [r7, #7] 80097dc: 2b03 cmp r3, #3 80097de: d817 bhi.n 8009810 80097e0: a201 add r2, pc, #4 ; (adr r2, 80097e8 ) 80097e2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80097e6: bf00 nop 80097e8: 080097f9 .word 0x080097f9 80097ec: 080097ff .word 0x080097ff 80097f0: 08009805 .word 0x08009805 80097f4: 0800980b .word 0x0800980b { case HAL_OK : usb_status = USBD_OK; 80097f8: 2300 movs r3, #0 80097fa: 73fb strb r3, [r7, #15] break; 80097fc: e00b b.n 8009816 case HAL_ERROR : usb_status = USBD_FAIL; 80097fe: 2303 movs r3, #3 8009800: 73fb strb r3, [r7, #15] break; 8009802: e008 b.n 8009816 case HAL_BUSY : usb_status = USBD_BUSY; 8009804: 2301 movs r3, #1 8009806: 73fb strb r3, [r7, #15] break; 8009808: e005 b.n 8009816 case HAL_TIMEOUT : usb_status = USBD_FAIL; 800980a: 2303 movs r3, #3 800980c: 73fb strb r3, [r7, #15] break; 800980e: e002 b.n 8009816 default : usb_status = USBD_FAIL; 8009810: 2303 movs r3, #3 8009812: 73fb strb r3, [r7, #15] break; 8009814: bf00 nop } return usb_status; 8009816: 7bfb ldrb r3, [r7, #15] } 8009818: 4618 mov r0, r3 800981a: 3714 adds r7, #20 800981c: 46bd mov sp, r7 800981e: f85d 7b04 ldr.w r7, [sp], #4 8009822: 4770 bx lr 08009824 <__assert_func>: 8009824: b51f push {r0, r1, r2, r3, r4, lr} 8009826: 4614 mov r4, r2 8009828: 461a mov r2, r3 800982a: 4b09 ldr r3, [pc, #36] ; (8009850 <__assert_func+0x2c>) 800982c: 681b ldr r3, [r3, #0] 800982e: 4605 mov r5, r0 8009830: 68d8 ldr r0, [r3, #12] 8009832: b14c cbz r4, 8009848 <__assert_func+0x24> 8009834: 4b07 ldr r3, [pc, #28] ; (8009854 <__assert_func+0x30>) 8009836: 9100 str r1, [sp, #0] 8009838: e9cd 3401 strd r3, r4, [sp, #4] 800983c: 4906 ldr r1, [pc, #24] ; (8009858 <__assert_func+0x34>) 800983e: 462b mov r3, r5 8009840: f000 f814 bl 800986c 8009844: f000 fbfe bl 800a044 8009848: 4b04 ldr r3, [pc, #16] ; (800985c <__assert_func+0x38>) 800984a: 461c mov r4, r3 800984c: e7f3 b.n 8009836 <__assert_func+0x12> 800984e: bf00 nop 8009850: 24000184 .word 0x24000184 8009854: 0800a968 .word 0x0800a968 8009858: 0800a975 .word 0x0800a975 800985c: 0800a9a3 .word 0x0800a9a3 08009860 <__errno>: 8009860: 4b01 ldr r3, [pc, #4] ; (8009868 <__errno+0x8>) 8009862: 6818 ldr r0, [r3, #0] 8009864: 4770 bx lr 8009866: bf00 nop 8009868: 24000184 .word 0x24000184 0800986c : 800986c: b40e push {r1, r2, r3} 800986e: b503 push {r0, r1, lr} 8009870: 4601 mov r1, r0 8009872: ab03 add r3, sp, #12 8009874: 4805 ldr r0, [pc, #20] ; (800988c ) 8009876: f853 2b04 ldr.w r2, [r3], #4 800987a: 6800 ldr r0, [r0, #0] 800987c: 9301 str r3, [sp, #4] 800987e: f000 f85d bl 800993c <_vfiprintf_r> 8009882: b002 add sp, #8 8009884: f85d eb04 ldr.w lr, [sp], #4 8009888: b003 add sp, #12 800988a: 4770 bx lr 800988c: 24000184 .word 0x24000184 08009890 <__libc_init_array>: 8009890: b570 push {r4, r5, r6, lr} 8009892: 4d0d ldr r5, [pc, #52] ; (80098c8 <__libc_init_array+0x38>) 8009894: 4c0d ldr r4, [pc, #52] ; (80098cc <__libc_init_array+0x3c>) 8009896: 1b64 subs r4, r4, r5 8009898: 10a4 asrs r4, r4, #2 800989a: 2600 movs r6, #0 800989c: 42a6 cmp r6, r4 800989e: d109 bne.n 80098b4 <__libc_init_array+0x24> 80098a0: 4d0b ldr r5, [pc, #44] ; (80098d0 <__libc_init_array+0x40>) 80098a2: 4c0c ldr r4, [pc, #48] ; (80098d4 <__libc_init_array+0x44>) 80098a4: f000 ffaa bl 800a7fc <_init> 80098a8: 1b64 subs r4, r4, r5 80098aa: 10a4 asrs r4, r4, #2 80098ac: 2600 movs r6, #0 80098ae: 42a6 cmp r6, r4 80098b0: d105 bne.n 80098be <__libc_init_array+0x2e> 80098b2: bd70 pop {r4, r5, r6, pc} 80098b4: f855 3b04 ldr.w r3, [r5], #4 80098b8: 4798 blx r3 80098ba: 3601 adds r6, #1 80098bc: e7ee b.n 800989c <__libc_init_array+0xc> 80098be: f855 3b04 ldr.w r3, [r5], #4 80098c2: 4798 blx r3 80098c4: 3601 adds r6, #1 80098c6: e7f2 b.n 80098ae <__libc_init_array+0x1e> 80098c8: 0800aa3c .word 0x0800aa3c 80098cc: 0800aa3c .word 0x0800aa3c 80098d0: 0800aa3c .word 0x0800aa3c 80098d4: 0800aa40 .word 0x0800aa40 080098d8 : 80098d8: 4402 add r2, r0 80098da: 4603 mov r3, r0 80098dc: 4293 cmp r3, r2 80098de: d100 bne.n 80098e2 80098e0: 4770 bx lr 80098e2: f803 1b01 strb.w r1, [r3], #1 80098e6: e7f9 b.n 80098dc 080098e8 <__sfputc_r>: 80098e8: 6893 ldr r3, [r2, #8] 80098ea: 3b01 subs r3, #1 80098ec: 2b00 cmp r3, #0 80098ee: b410 push {r4} 80098f0: 6093 str r3, [r2, #8] 80098f2: da08 bge.n 8009906 <__sfputc_r+0x1e> 80098f4: 6994 ldr r4, [r2, #24] 80098f6: 42a3 cmp r3, r4 80098f8: db01 blt.n 80098fe <__sfputc_r+0x16> 80098fa: 290a cmp r1, #10 80098fc: d103 bne.n 8009906 <__sfputc_r+0x1e> 80098fe: f85d 4b04 ldr.w r4, [sp], #4 8009902: f000 badf b.w 8009ec4 <__swbuf_r> 8009906: 6813 ldr r3, [r2, #0] 8009908: 1c58 adds r0, r3, #1 800990a: 6010 str r0, [r2, #0] 800990c: 7019 strb r1, [r3, #0] 800990e: 4608 mov r0, r1 8009910: f85d 4b04 ldr.w r4, [sp], #4 8009914: 4770 bx lr 08009916 <__sfputs_r>: 8009916: b5f8 push {r3, r4, r5, r6, r7, lr} 8009918: 4606 mov r6, r0 800991a: 460f mov r7, r1 800991c: 4614 mov r4, r2 800991e: 18d5 adds r5, r2, r3 8009920: 42ac cmp r4, r5 8009922: d101 bne.n 8009928 <__sfputs_r+0x12> 8009924: 2000 movs r0, #0 8009926: e007 b.n 8009938 <__sfputs_r+0x22> 8009928: f814 1b01 ldrb.w r1, [r4], #1 800992c: 463a mov r2, r7 800992e: 4630 mov r0, r6 8009930: f7ff ffda bl 80098e8 <__sfputc_r> 8009934: 1c43 adds r3, r0, #1 8009936: d1f3 bne.n 8009920 <__sfputs_r+0xa> 8009938: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 0800993c <_vfiprintf_r>: 800993c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8009940: 460d mov r5, r1 8009942: b09d sub sp, #116 ; 0x74 8009944: 4614 mov r4, r2 8009946: 4698 mov r8, r3 8009948: 4606 mov r6, r0 800994a: b118 cbz r0, 8009954 <_vfiprintf_r+0x18> 800994c: 6983 ldr r3, [r0, #24] 800994e: b90b cbnz r3, 8009954 <_vfiprintf_r+0x18> 8009950: f000 fc9a bl 800a288 <__sinit> 8009954: 4b89 ldr r3, [pc, #548] ; (8009b7c <_vfiprintf_r+0x240>) 8009956: 429d cmp r5, r3 8009958: d11b bne.n 8009992 <_vfiprintf_r+0x56> 800995a: 6875 ldr r5, [r6, #4] 800995c: 6e6b ldr r3, [r5, #100] ; 0x64 800995e: 07d9 lsls r1, r3, #31 8009960: d405 bmi.n 800996e <_vfiprintf_r+0x32> 8009962: 89ab ldrh r3, [r5, #12] 8009964: 059a lsls r2, r3, #22 8009966: d402 bmi.n 800996e <_vfiprintf_r+0x32> 8009968: 6da8 ldr r0, [r5, #88] ; 0x58 800996a: f000 fd2b bl 800a3c4 <__retarget_lock_acquire_recursive> 800996e: 89ab ldrh r3, [r5, #12] 8009970: 071b lsls r3, r3, #28 8009972: d501 bpl.n 8009978 <_vfiprintf_r+0x3c> 8009974: 692b ldr r3, [r5, #16] 8009976: b9eb cbnz r3, 80099b4 <_vfiprintf_r+0x78> 8009978: 4629 mov r1, r5 800997a: 4630 mov r0, r6 800997c: f000 faf4 bl 8009f68 <__swsetup_r> 8009980: b1c0 cbz r0, 80099b4 <_vfiprintf_r+0x78> 8009982: 6e6b ldr r3, [r5, #100] ; 0x64 8009984: 07dc lsls r4, r3, #31 8009986: d50e bpl.n 80099a6 <_vfiprintf_r+0x6a> 8009988: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800998c: b01d add sp, #116 ; 0x74 800998e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8009992: 4b7b ldr r3, [pc, #492] ; (8009b80 <_vfiprintf_r+0x244>) 8009994: 429d cmp r5, r3 8009996: d101 bne.n 800999c <_vfiprintf_r+0x60> 8009998: 68b5 ldr r5, [r6, #8] 800999a: e7df b.n 800995c <_vfiprintf_r+0x20> 800999c: 4b79 ldr r3, [pc, #484] ; (8009b84 <_vfiprintf_r+0x248>) 800999e: 429d cmp r5, r3 80099a0: bf08 it eq 80099a2: 68f5 ldreq r5, [r6, #12] 80099a4: e7da b.n 800995c <_vfiprintf_r+0x20> 80099a6: 89ab ldrh r3, [r5, #12] 80099a8: 0598 lsls r0, r3, #22 80099aa: d4ed bmi.n 8009988 <_vfiprintf_r+0x4c> 80099ac: 6da8 ldr r0, [r5, #88] ; 0x58 80099ae: f000 fd0a bl 800a3c6 <__retarget_lock_release_recursive> 80099b2: e7e9 b.n 8009988 <_vfiprintf_r+0x4c> 80099b4: 2300 movs r3, #0 80099b6: 9309 str r3, [sp, #36] ; 0x24 80099b8: 2320 movs r3, #32 80099ba: f88d 3029 strb.w r3, [sp, #41] ; 0x29 80099be: f8cd 800c str.w r8, [sp, #12] 80099c2: 2330 movs r3, #48 ; 0x30 80099c4: f8df 81c0 ldr.w r8, [pc, #448] ; 8009b88 <_vfiprintf_r+0x24c> 80099c8: f88d 302a strb.w r3, [sp, #42] ; 0x2a 80099cc: f04f 0901 mov.w r9, #1 80099d0: 4623 mov r3, r4 80099d2: 469a mov sl, r3 80099d4: f813 2b01 ldrb.w r2, [r3], #1 80099d8: b10a cbz r2, 80099de <_vfiprintf_r+0xa2> 80099da: 2a25 cmp r2, #37 ; 0x25 80099dc: d1f9 bne.n 80099d2 <_vfiprintf_r+0x96> 80099de: ebba 0b04 subs.w fp, sl, r4 80099e2: d00b beq.n 80099fc <_vfiprintf_r+0xc0> 80099e4: 465b mov r3, fp 80099e6: 4622 mov r2, r4 80099e8: 4629 mov r1, r5 80099ea: 4630 mov r0, r6 80099ec: f7ff ff93 bl 8009916 <__sfputs_r> 80099f0: 3001 adds r0, #1 80099f2: f000 80aa beq.w 8009b4a <_vfiprintf_r+0x20e> 80099f6: 9a09 ldr r2, [sp, #36] ; 0x24 80099f8: 445a add r2, fp 80099fa: 9209 str r2, [sp, #36] ; 0x24 80099fc: f89a 3000 ldrb.w r3, [sl] 8009a00: 2b00 cmp r3, #0 8009a02: f000 80a2 beq.w 8009b4a <_vfiprintf_r+0x20e> 8009a06: 2300 movs r3, #0 8009a08: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8009a0c: e9cd 2305 strd r2, r3, [sp, #20] 8009a10: f10a 0a01 add.w sl, sl, #1 8009a14: 9304 str r3, [sp, #16] 8009a16: 9307 str r3, [sp, #28] 8009a18: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8009a1c: 931a str r3, [sp, #104] ; 0x68 8009a1e: 4654 mov r4, sl 8009a20: 2205 movs r2, #5 8009a22: f814 1b01 ldrb.w r1, [r4], #1 8009a26: 4858 ldr r0, [pc, #352] ; (8009b88 <_vfiprintf_r+0x24c>) 8009a28: f7f6 fc72 bl 8000310 8009a2c: 9a04 ldr r2, [sp, #16] 8009a2e: b9d8 cbnz r0, 8009a68 <_vfiprintf_r+0x12c> 8009a30: 06d1 lsls r1, r2, #27 8009a32: bf44 itt mi 8009a34: 2320 movmi r3, #32 8009a36: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8009a3a: 0713 lsls r3, r2, #28 8009a3c: bf44 itt mi 8009a3e: 232b movmi r3, #43 ; 0x2b 8009a40: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8009a44: f89a 3000 ldrb.w r3, [sl] 8009a48: 2b2a cmp r3, #42 ; 0x2a 8009a4a: d015 beq.n 8009a78 <_vfiprintf_r+0x13c> 8009a4c: 9a07 ldr r2, [sp, #28] 8009a4e: 4654 mov r4, sl 8009a50: 2000 movs r0, #0 8009a52: f04f 0c0a mov.w ip, #10 8009a56: 4621 mov r1, r4 8009a58: f811 3b01 ldrb.w r3, [r1], #1 8009a5c: 3b30 subs r3, #48 ; 0x30 8009a5e: 2b09 cmp r3, #9 8009a60: d94e bls.n 8009b00 <_vfiprintf_r+0x1c4> 8009a62: b1b0 cbz r0, 8009a92 <_vfiprintf_r+0x156> 8009a64: 9207 str r2, [sp, #28] 8009a66: e014 b.n 8009a92 <_vfiprintf_r+0x156> 8009a68: eba0 0308 sub.w r3, r0, r8 8009a6c: fa09 f303 lsl.w r3, r9, r3 8009a70: 4313 orrs r3, r2 8009a72: 9304 str r3, [sp, #16] 8009a74: 46a2 mov sl, r4 8009a76: e7d2 b.n 8009a1e <_vfiprintf_r+0xe2> 8009a78: 9b03 ldr r3, [sp, #12] 8009a7a: 1d19 adds r1, r3, #4 8009a7c: 681b ldr r3, [r3, #0] 8009a7e: 9103 str r1, [sp, #12] 8009a80: 2b00 cmp r3, #0 8009a82: bfbb ittet lt 8009a84: 425b neglt r3, r3 8009a86: f042 0202 orrlt.w r2, r2, #2 8009a8a: 9307 strge r3, [sp, #28] 8009a8c: 9307 strlt r3, [sp, #28] 8009a8e: bfb8 it lt 8009a90: 9204 strlt r2, [sp, #16] 8009a92: 7823 ldrb r3, [r4, #0] 8009a94: 2b2e cmp r3, #46 ; 0x2e 8009a96: d10c bne.n 8009ab2 <_vfiprintf_r+0x176> 8009a98: 7863 ldrb r3, [r4, #1] 8009a9a: 2b2a cmp r3, #42 ; 0x2a 8009a9c: d135 bne.n 8009b0a <_vfiprintf_r+0x1ce> 8009a9e: 9b03 ldr r3, [sp, #12] 8009aa0: 1d1a adds r2, r3, #4 8009aa2: 681b ldr r3, [r3, #0] 8009aa4: 9203 str r2, [sp, #12] 8009aa6: 2b00 cmp r3, #0 8009aa8: bfb8 it lt 8009aaa: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff 8009aae: 3402 adds r4, #2 8009ab0: 9305 str r3, [sp, #20] 8009ab2: f8df a0e4 ldr.w sl, [pc, #228] ; 8009b98 <_vfiprintf_r+0x25c> 8009ab6: 7821 ldrb r1, [r4, #0] 8009ab8: 2203 movs r2, #3 8009aba: 4650 mov r0, sl 8009abc: f7f6 fc28 bl 8000310 8009ac0: b140 cbz r0, 8009ad4 <_vfiprintf_r+0x198> 8009ac2: 2340 movs r3, #64 ; 0x40 8009ac4: eba0 000a sub.w r0, r0, sl 8009ac8: fa03 f000 lsl.w r0, r3, r0 8009acc: 9b04 ldr r3, [sp, #16] 8009ace: 4303 orrs r3, r0 8009ad0: 3401 adds r4, #1 8009ad2: 9304 str r3, [sp, #16] 8009ad4: f814 1b01 ldrb.w r1, [r4], #1 8009ad8: 482c ldr r0, [pc, #176] ; (8009b8c <_vfiprintf_r+0x250>) 8009ada: f88d 1028 strb.w r1, [sp, #40] ; 0x28 8009ade: 2206 movs r2, #6 8009ae0: f7f6 fc16 bl 8000310 8009ae4: 2800 cmp r0, #0 8009ae6: d03f beq.n 8009b68 <_vfiprintf_r+0x22c> 8009ae8: 4b29 ldr r3, [pc, #164] ; (8009b90 <_vfiprintf_r+0x254>) 8009aea: bb1b cbnz r3, 8009b34 <_vfiprintf_r+0x1f8> 8009aec: 9b03 ldr r3, [sp, #12] 8009aee: 3307 adds r3, #7 8009af0: f023 0307 bic.w r3, r3, #7 8009af4: 3308 adds r3, #8 8009af6: 9303 str r3, [sp, #12] 8009af8: 9b09 ldr r3, [sp, #36] ; 0x24 8009afa: 443b add r3, r7 8009afc: 9309 str r3, [sp, #36] ; 0x24 8009afe: e767 b.n 80099d0 <_vfiprintf_r+0x94> 8009b00: fb0c 3202 mla r2, ip, r2, r3 8009b04: 460c mov r4, r1 8009b06: 2001 movs r0, #1 8009b08: e7a5 b.n 8009a56 <_vfiprintf_r+0x11a> 8009b0a: 2300 movs r3, #0 8009b0c: 3401 adds r4, #1 8009b0e: 9305 str r3, [sp, #20] 8009b10: 4619 mov r1, r3 8009b12: f04f 0c0a mov.w ip, #10 8009b16: 4620 mov r0, r4 8009b18: f810 2b01 ldrb.w r2, [r0], #1 8009b1c: 3a30 subs r2, #48 ; 0x30 8009b1e: 2a09 cmp r2, #9 8009b20: d903 bls.n 8009b2a <_vfiprintf_r+0x1ee> 8009b22: 2b00 cmp r3, #0 8009b24: d0c5 beq.n 8009ab2 <_vfiprintf_r+0x176> 8009b26: 9105 str r1, [sp, #20] 8009b28: e7c3 b.n 8009ab2 <_vfiprintf_r+0x176> 8009b2a: fb0c 2101 mla r1, ip, r1, r2 8009b2e: 4604 mov r4, r0 8009b30: 2301 movs r3, #1 8009b32: e7f0 b.n 8009b16 <_vfiprintf_r+0x1da> 8009b34: ab03 add r3, sp, #12 8009b36: 9300 str r3, [sp, #0] 8009b38: 462a mov r2, r5 8009b3a: 4b16 ldr r3, [pc, #88] ; (8009b94 <_vfiprintf_r+0x258>) 8009b3c: a904 add r1, sp, #16 8009b3e: 4630 mov r0, r6 8009b40: f3af 8000 nop.w 8009b44: 4607 mov r7, r0 8009b46: 1c78 adds r0, r7, #1 8009b48: d1d6 bne.n 8009af8 <_vfiprintf_r+0x1bc> 8009b4a: 6e6b ldr r3, [r5, #100] ; 0x64 8009b4c: 07d9 lsls r1, r3, #31 8009b4e: d405 bmi.n 8009b5c <_vfiprintf_r+0x220> 8009b50: 89ab ldrh r3, [r5, #12] 8009b52: 059a lsls r2, r3, #22 8009b54: d402 bmi.n 8009b5c <_vfiprintf_r+0x220> 8009b56: 6da8 ldr r0, [r5, #88] ; 0x58 8009b58: f000 fc35 bl 800a3c6 <__retarget_lock_release_recursive> 8009b5c: 89ab ldrh r3, [r5, #12] 8009b5e: 065b lsls r3, r3, #25 8009b60: f53f af12 bmi.w 8009988 <_vfiprintf_r+0x4c> 8009b64: 9809 ldr r0, [sp, #36] ; 0x24 8009b66: e711 b.n 800998c <_vfiprintf_r+0x50> 8009b68: ab03 add r3, sp, #12 8009b6a: 9300 str r3, [sp, #0] 8009b6c: 462a mov r2, r5 8009b6e: 4b09 ldr r3, [pc, #36] ; (8009b94 <_vfiprintf_r+0x258>) 8009b70: a904 add r1, sp, #16 8009b72: 4630 mov r0, r6 8009b74: f000 f880 bl 8009c78 <_printf_i> 8009b78: e7e4 b.n 8009b44 <_vfiprintf_r+0x208> 8009b7a: bf00 nop 8009b7c: 0800a9fc .word 0x0800a9fc 8009b80: 0800aa1c .word 0x0800aa1c 8009b84: 0800a9dc .word 0x0800a9dc 8009b88: 0800a9a8 .word 0x0800a9a8 8009b8c: 0800a9b2 .word 0x0800a9b2 8009b90: 00000000 .word 0x00000000 8009b94: 08009917 .word 0x08009917 8009b98: 0800a9ae .word 0x0800a9ae 08009b9c <_printf_common>: 8009b9c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009ba0: 4616 mov r6, r2 8009ba2: 4699 mov r9, r3 8009ba4: 688a ldr r2, [r1, #8] 8009ba6: 690b ldr r3, [r1, #16] 8009ba8: f8dd 8020 ldr.w r8, [sp, #32] 8009bac: 4293 cmp r3, r2 8009bae: bfb8 it lt 8009bb0: 4613 movlt r3, r2 8009bb2: 6033 str r3, [r6, #0] 8009bb4: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8009bb8: 4607 mov r7, r0 8009bba: 460c mov r4, r1 8009bbc: b10a cbz r2, 8009bc2 <_printf_common+0x26> 8009bbe: 3301 adds r3, #1 8009bc0: 6033 str r3, [r6, #0] 8009bc2: 6823 ldr r3, [r4, #0] 8009bc4: 0699 lsls r1, r3, #26 8009bc6: bf42 ittt mi 8009bc8: 6833 ldrmi r3, [r6, #0] 8009bca: 3302 addmi r3, #2 8009bcc: 6033 strmi r3, [r6, #0] 8009bce: 6825 ldr r5, [r4, #0] 8009bd0: f015 0506 ands.w r5, r5, #6 8009bd4: d106 bne.n 8009be4 <_printf_common+0x48> 8009bd6: f104 0a19 add.w sl, r4, #25 8009bda: 68e3 ldr r3, [r4, #12] 8009bdc: 6832 ldr r2, [r6, #0] 8009bde: 1a9b subs r3, r3, r2 8009be0: 42ab cmp r3, r5 8009be2: dc26 bgt.n 8009c32 <_printf_common+0x96> 8009be4: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 8009be8: 1e13 subs r3, r2, #0 8009bea: 6822 ldr r2, [r4, #0] 8009bec: bf18 it ne 8009bee: 2301 movne r3, #1 8009bf0: 0692 lsls r2, r2, #26 8009bf2: d42b bmi.n 8009c4c <_printf_common+0xb0> 8009bf4: f104 0243 add.w r2, r4, #67 ; 0x43 8009bf8: 4649 mov r1, r9 8009bfa: 4638 mov r0, r7 8009bfc: 47c0 blx r8 8009bfe: 3001 adds r0, #1 8009c00: d01e beq.n 8009c40 <_printf_common+0xa4> 8009c02: 6823 ldr r3, [r4, #0] 8009c04: 68e5 ldr r5, [r4, #12] 8009c06: 6832 ldr r2, [r6, #0] 8009c08: f003 0306 and.w r3, r3, #6 8009c0c: 2b04 cmp r3, #4 8009c0e: bf08 it eq 8009c10: 1aad subeq r5, r5, r2 8009c12: 68a3 ldr r3, [r4, #8] 8009c14: 6922 ldr r2, [r4, #16] 8009c16: bf0c ite eq 8009c18: ea25 75e5 biceq.w r5, r5, r5, asr #31 8009c1c: 2500 movne r5, #0 8009c1e: 4293 cmp r3, r2 8009c20: bfc4 itt gt 8009c22: 1a9b subgt r3, r3, r2 8009c24: 18ed addgt r5, r5, r3 8009c26: 2600 movs r6, #0 8009c28: 341a adds r4, #26 8009c2a: 42b5 cmp r5, r6 8009c2c: d11a bne.n 8009c64 <_printf_common+0xc8> 8009c2e: 2000 movs r0, #0 8009c30: e008 b.n 8009c44 <_printf_common+0xa8> 8009c32: 2301 movs r3, #1 8009c34: 4652 mov r2, sl 8009c36: 4649 mov r1, r9 8009c38: 4638 mov r0, r7 8009c3a: 47c0 blx r8 8009c3c: 3001 adds r0, #1 8009c3e: d103 bne.n 8009c48 <_printf_common+0xac> 8009c40: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8009c44: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8009c48: 3501 adds r5, #1 8009c4a: e7c6 b.n 8009bda <_printf_common+0x3e> 8009c4c: 18e1 adds r1, r4, r3 8009c4e: 1c5a adds r2, r3, #1 8009c50: 2030 movs r0, #48 ; 0x30 8009c52: f881 0043 strb.w r0, [r1, #67] ; 0x43 8009c56: 4422 add r2, r4 8009c58: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 8009c5c: f882 1043 strb.w r1, [r2, #67] ; 0x43 8009c60: 3302 adds r3, #2 8009c62: e7c7 b.n 8009bf4 <_printf_common+0x58> 8009c64: 2301 movs r3, #1 8009c66: 4622 mov r2, r4 8009c68: 4649 mov r1, r9 8009c6a: 4638 mov r0, r7 8009c6c: 47c0 blx r8 8009c6e: 3001 adds r0, #1 8009c70: d0e6 beq.n 8009c40 <_printf_common+0xa4> 8009c72: 3601 adds r6, #1 8009c74: e7d9 b.n 8009c2a <_printf_common+0x8e> ... 08009c78 <_printf_i>: 8009c78: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8009c7c: 460c mov r4, r1 8009c7e: 4691 mov r9, r2 8009c80: 7e27 ldrb r7, [r4, #24] 8009c82: 990c ldr r1, [sp, #48] ; 0x30 8009c84: 2f78 cmp r7, #120 ; 0x78 8009c86: 4680 mov r8, r0 8009c88: 469a mov sl, r3 8009c8a: f104 0243 add.w r2, r4, #67 ; 0x43 8009c8e: d807 bhi.n 8009ca0 <_printf_i+0x28> 8009c90: 2f62 cmp r7, #98 ; 0x62 8009c92: d80a bhi.n 8009caa <_printf_i+0x32> 8009c94: 2f00 cmp r7, #0 8009c96: f000 80d8 beq.w 8009e4a <_printf_i+0x1d2> 8009c9a: 2f58 cmp r7, #88 ; 0x58 8009c9c: f000 80a3 beq.w 8009de6 <_printf_i+0x16e> 8009ca0: f104 0642 add.w r6, r4, #66 ; 0x42 8009ca4: f884 7042 strb.w r7, [r4, #66] ; 0x42 8009ca8: e03a b.n 8009d20 <_printf_i+0xa8> 8009caa: f1a7 0363 sub.w r3, r7, #99 ; 0x63 8009cae: 2b15 cmp r3, #21 8009cb0: d8f6 bhi.n 8009ca0 <_printf_i+0x28> 8009cb2: a001 add r0, pc, #4 ; (adr r0, 8009cb8 <_printf_i+0x40>) 8009cb4: f850 f023 ldr.w pc, [r0, r3, lsl #2] 8009cb8: 08009d11 .word 0x08009d11 8009cbc: 08009d25 .word 0x08009d25 8009cc0: 08009ca1 .word 0x08009ca1 8009cc4: 08009ca1 .word 0x08009ca1 8009cc8: 08009ca1 .word 0x08009ca1 8009ccc: 08009ca1 .word 0x08009ca1 8009cd0: 08009d25 .word 0x08009d25 8009cd4: 08009ca1 .word 0x08009ca1 8009cd8: 08009ca1 .word 0x08009ca1 8009cdc: 08009ca1 .word 0x08009ca1 8009ce0: 08009ca1 .word 0x08009ca1 8009ce4: 08009e31 .word 0x08009e31 8009ce8: 08009d55 .word 0x08009d55 8009cec: 08009e13 .word 0x08009e13 8009cf0: 08009ca1 .word 0x08009ca1 8009cf4: 08009ca1 .word 0x08009ca1 8009cf8: 08009e53 .word 0x08009e53 8009cfc: 08009ca1 .word 0x08009ca1 8009d00: 08009d55 .word 0x08009d55 8009d04: 08009ca1 .word 0x08009ca1 8009d08: 08009ca1 .word 0x08009ca1 8009d0c: 08009e1b .word 0x08009e1b 8009d10: 680b ldr r3, [r1, #0] 8009d12: 1d1a adds r2, r3, #4 8009d14: 681b ldr r3, [r3, #0] 8009d16: 600a str r2, [r1, #0] 8009d18: f104 0642 add.w r6, r4, #66 ; 0x42 8009d1c: f884 3042 strb.w r3, [r4, #66] ; 0x42 8009d20: 2301 movs r3, #1 8009d22: e0a3 b.n 8009e6c <_printf_i+0x1f4> 8009d24: 6825 ldr r5, [r4, #0] 8009d26: 6808 ldr r0, [r1, #0] 8009d28: 062e lsls r6, r5, #24 8009d2a: f100 0304 add.w r3, r0, #4 8009d2e: d50a bpl.n 8009d46 <_printf_i+0xce> 8009d30: 6805 ldr r5, [r0, #0] 8009d32: 600b str r3, [r1, #0] 8009d34: 2d00 cmp r5, #0 8009d36: da03 bge.n 8009d40 <_printf_i+0xc8> 8009d38: 232d movs r3, #45 ; 0x2d 8009d3a: 426d negs r5, r5 8009d3c: f884 3043 strb.w r3, [r4, #67] ; 0x43 8009d40: 485e ldr r0, [pc, #376] ; (8009ebc <_printf_i+0x244>) 8009d42: 230a movs r3, #10 8009d44: e019 b.n 8009d7a <_printf_i+0x102> 8009d46: f015 0f40 tst.w r5, #64 ; 0x40 8009d4a: 6805 ldr r5, [r0, #0] 8009d4c: 600b str r3, [r1, #0] 8009d4e: bf18 it ne 8009d50: b22d sxthne r5, r5 8009d52: e7ef b.n 8009d34 <_printf_i+0xbc> 8009d54: 680b ldr r3, [r1, #0] 8009d56: 6825 ldr r5, [r4, #0] 8009d58: 1d18 adds r0, r3, #4 8009d5a: 6008 str r0, [r1, #0] 8009d5c: 0628 lsls r0, r5, #24 8009d5e: d501 bpl.n 8009d64 <_printf_i+0xec> 8009d60: 681d ldr r5, [r3, #0] 8009d62: e002 b.n 8009d6a <_printf_i+0xf2> 8009d64: 0669 lsls r1, r5, #25 8009d66: d5fb bpl.n 8009d60 <_printf_i+0xe8> 8009d68: 881d ldrh r5, [r3, #0] 8009d6a: 4854 ldr r0, [pc, #336] ; (8009ebc <_printf_i+0x244>) 8009d6c: 2f6f cmp r7, #111 ; 0x6f 8009d6e: bf0c ite eq 8009d70: 2308 moveq r3, #8 8009d72: 230a movne r3, #10 8009d74: 2100 movs r1, #0 8009d76: f884 1043 strb.w r1, [r4, #67] ; 0x43 8009d7a: 6866 ldr r6, [r4, #4] 8009d7c: 60a6 str r6, [r4, #8] 8009d7e: 2e00 cmp r6, #0 8009d80: bfa2 ittt ge 8009d82: 6821 ldrge r1, [r4, #0] 8009d84: f021 0104 bicge.w r1, r1, #4 8009d88: 6021 strge r1, [r4, #0] 8009d8a: b90d cbnz r5, 8009d90 <_printf_i+0x118> 8009d8c: 2e00 cmp r6, #0 8009d8e: d04d beq.n 8009e2c <_printf_i+0x1b4> 8009d90: 4616 mov r6, r2 8009d92: fbb5 f1f3 udiv r1, r5, r3 8009d96: fb03 5711 mls r7, r3, r1, r5 8009d9a: 5dc7 ldrb r7, [r0, r7] 8009d9c: f806 7d01 strb.w r7, [r6, #-1]! 8009da0: 462f mov r7, r5 8009da2: 42bb cmp r3, r7 8009da4: 460d mov r5, r1 8009da6: d9f4 bls.n 8009d92 <_printf_i+0x11a> 8009da8: 2b08 cmp r3, #8 8009daa: d10b bne.n 8009dc4 <_printf_i+0x14c> 8009dac: 6823 ldr r3, [r4, #0] 8009dae: 07df lsls r7, r3, #31 8009db0: d508 bpl.n 8009dc4 <_printf_i+0x14c> 8009db2: 6923 ldr r3, [r4, #16] 8009db4: 6861 ldr r1, [r4, #4] 8009db6: 4299 cmp r1, r3 8009db8: bfde ittt le 8009dba: 2330 movle r3, #48 ; 0x30 8009dbc: f806 3c01 strble.w r3, [r6, #-1] 8009dc0: f106 36ff addle.w r6, r6, #4294967295 ; 0xffffffff 8009dc4: 1b92 subs r2, r2, r6 8009dc6: 6122 str r2, [r4, #16] 8009dc8: f8cd a000 str.w sl, [sp] 8009dcc: 464b mov r3, r9 8009dce: aa03 add r2, sp, #12 8009dd0: 4621 mov r1, r4 8009dd2: 4640 mov r0, r8 8009dd4: f7ff fee2 bl 8009b9c <_printf_common> 8009dd8: 3001 adds r0, #1 8009dda: d14c bne.n 8009e76 <_printf_i+0x1fe> 8009ddc: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8009de0: b004 add sp, #16 8009de2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8009de6: 4835 ldr r0, [pc, #212] ; (8009ebc <_printf_i+0x244>) 8009de8: f884 7045 strb.w r7, [r4, #69] ; 0x45 8009dec: 6823 ldr r3, [r4, #0] 8009dee: 680e ldr r6, [r1, #0] 8009df0: 061f lsls r7, r3, #24 8009df2: f856 5b04 ldr.w r5, [r6], #4 8009df6: 600e str r6, [r1, #0] 8009df8: d514 bpl.n 8009e24 <_printf_i+0x1ac> 8009dfa: 07d9 lsls r1, r3, #31 8009dfc: bf44 itt mi 8009dfe: f043 0320 orrmi.w r3, r3, #32 8009e02: 6023 strmi r3, [r4, #0] 8009e04: b91d cbnz r5, 8009e0e <_printf_i+0x196> 8009e06: 6823 ldr r3, [r4, #0] 8009e08: f023 0320 bic.w r3, r3, #32 8009e0c: 6023 str r3, [r4, #0] 8009e0e: 2310 movs r3, #16 8009e10: e7b0 b.n 8009d74 <_printf_i+0xfc> 8009e12: 6823 ldr r3, [r4, #0] 8009e14: f043 0320 orr.w r3, r3, #32 8009e18: 6023 str r3, [r4, #0] 8009e1a: 2378 movs r3, #120 ; 0x78 8009e1c: 4828 ldr r0, [pc, #160] ; (8009ec0 <_printf_i+0x248>) 8009e1e: f884 3045 strb.w r3, [r4, #69] ; 0x45 8009e22: e7e3 b.n 8009dec <_printf_i+0x174> 8009e24: 065e lsls r6, r3, #25 8009e26: bf48 it mi 8009e28: b2ad uxthmi r5, r5 8009e2a: e7e6 b.n 8009dfa <_printf_i+0x182> 8009e2c: 4616 mov r6, r2 8009e2e: e7bb b.n 8009da8 <_printf_i+0x130> 8009e30: 680b ldr r3, [r1, #0] 8009e32: 6826 ldr r6, [r4, #0] 8009e34: 6960 ldr r0, [r4, #20] 8009e36: 1d1d adds r5, r3, #4 8009e38: 600d str r5, [r1, #0] 8009e3a: 0635 lsls r5, r6, #24 8009e3c: 681b ldr r3, [r3, #0] 8009e3e: d501 bpl.n 8009e44 <_printf_i+0x1cc> 8009e40: 6018 str r0, [r3, #0] 8009e42: e002 b.n 8009e4a <_printf_i+0x1d2> 8009e44: 0671 lsls r1, r6, #25 8009e46: d5fb bpl.n 8009e40 <_printf_i+0x1c8> 8009e48: 8018 strh r0, [r3, #0] 8009e4a: 2300 movs r3, #0 8009e4c: 6123 str r3, [r4, #16] 8009e4e: 4616 mov r6, r2 8009e50: e7ba b.n 8009dc8 <_printf_i+0x150> 8009e52: 680b ldr r3, [r1, #0] 8009e54: 1d1a adds r2, r3, #4 8009e56: 600a str r2, [r1, #0] 8009e58: 681e ldr r6, [r3, #0] 8009e5a: 6862 ldr r2, [r4, #4] 8009e5c: 2100 movs r1, #0 8009e5e: 4630 mov r0, r6 8009e60: f7f6 fa56 bl 8000310 8009e64: b108 cbz r0, 8009e6a <_printf_i+0x1f2> 8009e66: 1b80 subs r0, r0, r6 8009e68: 6060 str r0, [r4, #4] 8009e6a: 6863 ldr r3, [r4, #4] 8009e6c: 6123 str r3, [r4, #16] 8009e6e: 2300 movs r3, #0 8009e70: f884 3043 strb.w r3, [r4, #67] ; 0x43 8009e74: e7a8 b.n 8009dc8 <_printf_i+0x150> 8009e76: 6923 ldr r3, [r4, #16] 8009e78: 4632 mov r2, r6 8009e7a: 4649 mov r1, r9 8009e7c: 4640 mov r0, r8 8009e7e: 47d0 blx sl 8009e80: 3001 adds r0, #1 8009e82: d0ab beq.n 8009ddc <_printf_i+0x164> 8009e84: 6823 ldr r3, [r4, #0] 8009e86: 079b lsls r3, r3, #30 8009e88: d413 bmi.n 8009eb2 <_printf_i+0x23a> 8009e8a: 68e0 ldr r0, [r4, #12] 8009e8c: 9b03 ldr r3, [sp, #12] 8009e8e: 4298 cmp r0, r3 8009e90: bfb8 it lt 8009e92: 4618 movlt r0, r3 8009e94: e7a4 b.n 8009de0 <_printf_i+0x168> 8009e96: 2301 movs r3, #1 8009e98: 4632 mov r2, r6 8009e9a: 4649 mov r1, r9 8009e9c: 4640 mov r0, r8 8009e9e: 47d0 blx sl 8009ea0: 3001 adds r0, #1 8009ea2: d09b beq.n 8009ddc <_printf_i+0x164> 8009ea4: 3501 adds r5, #1 8009ea6: 68e3 ldr r3, [r4, #12] 8009ea8: 9903 ldr r1, [sp, #12] 8009eaa: 1a5b subs r3, r3, r1 8009eac: 42ab cmp r3, r5 8009eae: dcf2 bgt.n 8009e96 <_printf_i+0x21e> 8009eb0: e7eb b.n 8009e8a <_printf_i+0x212> 8009eb2: 2500 movs r5, #0 8009eb4: f104 0619 add.w r6, r4, #25 8009eb8: e7f5 b.n 8009ea6 <_printf_i+0x22e> 8009eba: bf00 nop 8009ebc: 0800a9b9 .word 0x0800a9b9 8009ec0: 0800a9ca .word 0x0800a9ca 08009ec4 <__swbuf_r>: 8009ec4: b5f8 push {r3, r4, r5, r6, r7, lr} 8009ec6: 460e mov r6, r1 8009ec8: 4614 mov r4, r2 8009eca: 4605 mov r5, r0 8009ecc: b118 cbz r0, 8009ed6 <__swbuf_r+0x12> 8009ece: 6983 ldr r3, [r0, #24] 8009ed0: b90b cbnz r3, 8009ed6 <__swbuf_r+0x12> 8009ed2: f000 f9d9 bl 800a288 <__sinit> 8009ed6: 4b21 ldr r3, [pc, #132] ; (8009f5c <__swbuf_r+0x98>) 8009ed8: 429c cmp r4, r3 8009eda: d12b bne.n 8009f34 <__swbuf_r+0x70> 8009edc: 686c ldr r4, [r5, #4] 8009ede: 69a3 ldr r3, [r4, #24] 8009ee0: 60a3 str r3, [r4, #8] 8009ee2: 89a3 ldrh r3, [r4, #12] 8009ee4: 071a lsls r2, r3, #28 8009ee6: d52f bpl.n 8009f48 <__swbuf_r+0x84> 8009ee8: 6923 ldr r3, [r4, #16] 8009eea: b36b cbz r3, 8009f48 <__swbuf_r+0x84> 8009eec: 6923 ldr r3, [r4, #16] 8009eee: 6820 ldr r0, [r4, #0] 8009ef0: 1ac0 subs r0, r0, r3 8009ef2: 6963 ldr r3, [r4, #20] 8009ef4: b2f6 uxtb r6, r6 8009ef6: 4283 cmp r3, r0 8009ef8: 4637 mov r7, r6 8009efa: dc04 bgt.n 8009f06 <__swbuf_r+0x42> 8009efc: 4621 mov r1, r4 8009efe: 4628 mov r0, r5 8009f00: f000 f92e bl 800a160 <_fflush_r> 8009f04: bb30 cbnz r0, 8009f54 <__swbuf_r+0x90> 8009f06: 68a3 ldr r3, [r4, #8] 8009f08: 3b01 subs r3, #1 8009f0a: 60a3 str r3, [r4, #8] 8009f0c: 6823 ldr r3, [r4, #0] 8009f0e: 1c5a adds r2, r3, #1 8009f10: 6022 str r2, [r4, #0] 8009f12: 701e strb r6, [r3, #0] 8009f14: 6963 ldr r3, [r4, #20] 8009f16: 3001 adds r0, #1 8009f18: 4283 cmp r3, r0 8009f1a: d004 beq.n 8009f26 <__swbuf_r+0x62> 8009f1c: 89a3 ldrh r3, [r4, #12] 8009f1e: 07db lsls r3, r3, #31 8009f20: d506 bpl.n 8009f30 <__swbuf_r+0x6c> 8009f22: 2e0a cmp r6, #10 8009f24: d104 bne.n 8009f30 <__swbuf_r+0x6c> 8009f26: 4621 mov r1, r4 8009f28: 4628 mov r0, r5 8009f2a: f000 f919 bl 800a160 <_fflush_r> 8009f2e: b988 cbnz r0, 8009f54 <__swbuf_r+0x90> 8009f30: 4638 mov r0, r7 8009f32: bdf8 pop {r3, r4, r5, r6, r7, pc} 8009f34: 4b0a ldr r3, [pc, #40] ; (8009f60 <__swbuf_r+0x9c>) 8009f36: 429c cmp r4, r3 8009f38: d101 bne.n 8009f3e <__swbuf_r+0x7a> 8009f3a: 68ac ldr r4, [r5, #8] 8009f3c: e7cf b.n 8009ede <__swbuf_r+0x1a> 8009f3e: 4b09 ldr r3, [pc, #36] ; (8009f64 <__swbuf_r+0xa0>) 8009f40: 429c cmp r4, r3 8009f42: bf08 it eq 8009f44: 68ec ldreq r4, [r5, #12] 8009f46: e7ca b.n 8009ede <__swbuf_r+0x1a> 8009f48: 4621 mov r1, r4 8009f4a: 4628 mov r0, r5 8009f4c: f000 f80c bl 8009f68 <__swsetup_r> 8009f50: 2800 cmp r0, #0 8009f52: d0cb beq.n 8009eec <__swbuf_r+0x28> 8009f54: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff 8009f58: e7ea b.n 8009f30 <__swbuf_r+0x6c> 8009f5a: bf00 nop 8009f5c: 0800a9fc .word 0x0800a9fc 8009f60: 0800aa1c .word 0x0800aa1c 8009f64: 0800a9dc .word 0x0800a9dc 08009f68 <__swsetup_r>: 8009f68: 4b32 ldr r3, [pc, #200] ; (800a034 <__swsetup_r+0xcc>) 8009f6a: b570 push {r4, r5, r6, lr} 8009f6c: 681d ldr r5, [r3, #0] 8009f6e: 4606 mov r6, r0 8009f70: 460c mov r4, r1 8009f72: b125 cbz r5, 8009f7e <__swsetup_r+0x16> 8009f74: 69ab ldr r3, [r5, #24] 8009f76: b913 cbnz r3, 8009f7e <__swsetup_r+0x16> 8009f78: 4628 mov r0, r5 8009f7a: f000 f985 bl 800a288 <__sinit> 8009f7e: 4b2e ldr r3, [pc, #184] ; (800a038 <__swsetup_r+0xd0>) 8009f80: 429c cmp r4, r3 8009f82: d10f bne.n 8009fa4 <__swsetup_r+0x3c> 8009f84: 686c ldr r4, [r5, #4] 8009f86: 89a3 ldrh r3, [r4, #12] 8009f88: f9b4 200c ldrsh.w r2, [r4, #12] 8009f8c: 0719 lsls r1, r3, #28 8009f8e: d42c bmi.n 8009fea <__swsetup_r+0x82> 8009f90: 06dd lsls r5, r3, #27 8009f92: d411 bmi.n 8009fb8 <__swsetup_r+0x50> 8009f94: 2309 movs r3, #9 8009f96: 6033 str r3, [r6, #0] 8009f98: f042 0340 orr.w r3, r2, #64 ; 0x40 8009f9c: 81a3 strh r3, [r4, #12] 8009f9e: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8009fa2: e03e b.n 800a022 <__swsetup_r+0xba> 8009fa4: 4b25 ldr r3, [pc, #148] ; (800a03c <__swsetup_r+0xd4>) 8009fa6: 429c cmp r4, r3 8009fa8: d101 bne.n 8009fae <__swsetup_r+0x46> 8009faa: 68ac ldr r4, [r5, #8] 8009fac: e7eb b.n 8009f86 <__swsetup_r+0x1e> 8009fae: 4b24 ldr r3, [pc, #144] ; (800a040 <__swsetup_r+0xd8>) 8009fb0: 429c cmp r4, r3 8009fb2: bf08 it eq 8009fb4: 68ec ldreq r4, [r5, #12] 8009fb6: e7e6 b.n 8009f86 <__swsetup_r+0x1e> 8009fb8: 0758 lsls r0, r3, #29 8009fba: d512 bpl.n 8009fe2 <__swsetup_r+0x7a> 8009fbc: 6b61 ldr r1, [r4, #52] ; 0x34 8009fbe: b141 cbz r1, 8009fd2 <__swsetup_r+0x6a> 8009fc0: f104 0344 add.w r3, r4, #68 ; 0x44 8009fc4: 4299 cmp r1, r3 8009fc6: d002 beq.n 8009fce <__swsetup_r+0x66> 8009fc8: 4630 mov r0, r6 8009fca: f000 fa61 bl 800a490 <_free_r> 8009fce: 2300 movs r3, #0 8009fd0: 6363 str r3, [r4, #52] ; 0x34 8009fd2: 89a3 ldrh r3, [r4, #12] 8009fd4: f023 0324 bic.w r3, r3, #36 ; 0x24 8009fd8: 81a3 strh r3, [r4, #12] 8009fda: 2300 movs r3, #0 8009fdc: 6063 str r3, [r4, #4] 8009fde: 6923 ldr r3, [r4, #16] 8009fe0: 6023 str r3, [r4, #0] 8009fe2: 89a3 ldrh r3, [r4, #12] 8009fe4: f043 0308 orr.w r3, r3, #8 8009fe8: 81a3 strh r3, [r4, #12] 8009fea: 6923 ldr r3, [r4, #16] 8009fec: b94b cbnz r3, 800a002 <__swsetup_r+0x9a> 8009fee: 89a3 ldrh r3, [r4, #12] 8009ff0: f403 7320 and.w r3, r3, #640 ; 0x280 8009ff4: f5b3 7f00 cmp.w r3, #512 ; 0x200 8009ff8: d003 beq.n 800a002 <__swsetup_r+0x9a> 8009ffa: 4621 mov r1, r4 8009ffc: 4630 mov r0, r6 8009ffe: f000 fa07 bl 800a410 <__smakebuf_r> 800a002: 89a0 ldrh r0, [r4, #12] 800a004: f9b4 200c ldrsh.w r2, [r4, #12] 800a008: f010 0301 ands.w r3, r0, #1 800a00c: d00a beq.n 800a024 <__swsetup_r+0xbc> 800a00e: 2300 movs r3, #0 800a010: 60a3 str r3, [r4, #8] 800a012: 6963 ldr r3, [r4, #20] 800a014: 425b negs r3, r3 800a016: 61a3 str r3, [r4, #24] 800a018: 6923 ldr r3, [r4, #16] 800a01a: b943 cbnz r3, 800a02e <__swsetup_r+0xc6> 800a01c: f010 0080 ands.w r0, r0, #128 ; 0x80 800a020: d1ba bne.n 8009f98 <__swsetup_r+0x30> 800a022: bd70 pop {r4, r5, r6, pc} 800a024: 0781 lsls r1, r0, #30 800a026: bf58 it pl 800a028: 6963 ldrpl r3, [r4, #20] 800a02a: 60a3 str r3, [r4, #8] 800a02c: e7f4 b.n 800a018 <__swsetup_r+0xb0> 800a02e: 2000 movs r0, #0 800a030: e7f7 b.n 800a022 <__swsetup_r+0xba> 800a032: bf00 nop 800a034: 24000184 .word 0x24000184 800a038: 0800a9fc .word 0x0800a9fc 800a03c: 0800aa1c .word 0x0800aa1c 800a040: 0800a9dc .word 0x0800a9dc 0800a044 : 800a044: b508 push {r3, lr} 800a046: 2006 movs r0, #6 800a048: f000 fb04 bl 800a654 800a04c: 2001 movs r0, #1 800a04e: f7f7 f8d1 bl 80011f4 <_exit> ... 0800a054 <__sflush_r>: 800a054: 898a ldrh r2, [r1, #12] 800a056: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800a05a: 4605 mov r5, r0 800a05c: 0710 lsls r0, r2, #28 800a05e: 460c mov r4, r1 800a060: d458 bmi.n 800a114 <__sflush_r+0xc0> 800a062: 684b ldr r3, [r1, #4] 800a064: 2b00 cmp r3, #0 800a066: dc05 bgt.n 800a074 <__sflush_r+0x20> 800a068: 6c0b ldr r3, [r1, #64] ; 0x40 800a06a: 2b00 cmp r3, #0 800a06c: dc02 bgt.n 800a074 <__sflush_r+0x20> 800a06e: 2000 movs r0, #0 800a070: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800a074: 6ae6 ldr r6, [r4, #44] ; 0x2c 800a076: 2e00 cmp r6, #0 800a078: d0f9 beq.n 800a06e <__sflush_r+0x1a> 800a07a: 2300 movs r3, #0 800a07c: f412 5280 ands.w r2, r2, #4096 ; 0x1000 800a080: 682f ldr r7, [r5, #0] 800a082: 602b str r3, [r5, #0] 800a084: d032 beq.n 800a0ec <__sflush_r+0x98> 800a086: 6d60 ldr r0, [r4, #84] ; 0x54 800a088: 89a3 ldrh r3, [r4, #12] 800a08a: 075a lsls r2, r3, #29 800a08c: d505 bpl.n 800a09a <__sflush_r+0x46> 800a08e: 6863 ldr r3, [r4, #4] 800a090: 1ac0 subs r0, r0, r3 800a092: 6b63 ldr r3, [r4, #52] ; 0x34 800a094: b10b cbz r3, 800a09a <__sflush_r+0x46> 800a096: 6c23 ldr r3, [r4, #64] ; 0x40 800a098: 1ac0 subs r0, r0, r3 800a09a: 2300 movs r3, #0 800a09c: 4602 mov r2, r0 800a09e: 6ae6 ldr r6, [r4, #44] ; 0x2c 800a0a0: 6a21 ldr r1, [r4, #32] 800a0a2: 4628 mov r0, r5 800a0a4: 47b0 blx r6 800a0a6: 1c43 adds r3, r0, #1 800a0a8: 89a3 ldrh r3, [r4, #12] 800a0aa: d106 bne.n 800a0ba <__sflush_r+0x66> 800a0ac: 6829 ldr r1, [r5, #0] 800a0ae: 291d cmp r1, #29 800a0b0: d82c bhi.n 800a10c <__sflush_r+0xb8> 800a0b2: 4a2a ldr r2, [pc, #168] ; (800a15c <__sflush_r+0x108>) 800a0b4: 40ca lsrs r2, r1 800a0b6: 07d6 lsls r6, r2, #31 800a0b8: d528 bpl.n 800a10c <__sflush_r+0xb8> 800a0ba: 2200 movs r2, #0 800a0bc: 6062 str r2, [r4, #4] 800a0be: 04d9 lsls r1, r3, #19 800a0c0: 6922 ldr r2, [r4, #16] 800a0c2: 6022 str r2, [r4, #0] 800a0c4: d504 bpl.n 800a0d0 <__sflush_r+0x7c> 800a0c6: 1c42 adds r2, r0, #1 800a0c8: d101 bne.n 800a0ce <__sflush_r+0x7a> 800a0ca: 682b ldr r3, [r5, #0] 800a0cc: b903 cbnz r3, 800a0d0 <__sflush_r+0x7c> 800a0ce: 6560 str r0, [r4, #84] ; 0x54 800a0d0: 6b61 ldr r1, [r4, #52] ; 0x34 800a0d2: 602f str r7, [r5, #0] 800a0d4: 2900 cmp r1, #0 800a0d6: d0ca beq.n 800a06e <__sflush_r+0x1a> 800a0d8: f104 0344 add.w r3, r4, #68 ; 0x44 800a0dc: 4299 cmp r1, r3 800a0de: d002 beq.n 800a0e6 <__sflush_r+0x92> 800a0e0: 4628 mov r0, r5 800a0e2: f000 f9d5 bl 800a490 <_free_r> 800a0e6: 2000 movs r0, #0 800a0e8: 6360 str r0, [r4, #52] ; 0x34 800a0ea: e7c1 b.n 800a070 <__sflush_r+0x1c> 800a0ec: 6a21 ldr r1, [r4, #32] 800a0ee: 2301 movs r3, #1 800a0f0: 4628 mov r0, r5 800a0f2: 47b0 blx r6 800a0f4: 1c41 adds r1, r0, #1 800a0f6: d1c7 bne.n 800a088 <__sflush_r+0x34> 800a0f8: 682b ldr r3, [r5, #0] 800a0fa: 2b00 cmp r3, #0 800a0fc: d0c4 beq.n 800a088 <__sflush_r+0x34> 800a0fe: 2b1d cmp r3, #29 800a100: d001 beq.n 800a106 <__sflush_r+0xb2> 800a102: 2b16 cmp r3, #22 800a104: d101 bne.n 800a10a <__sflush_r+0xb6> 800a106: 602f str r7, [r5, #0] 800a108: e7b1 b.n 800a06e <__sflush_r+0x1a> 800a10a: 89a3 ldrh r3, [r4, #12] 800a10c: f043 0340 orr.w r3, r3, #64 ; 0x40 800a110: 81a3 strh r3, [r4, #12] 800a112: e7ad b.n 800a070 <__sflush_r+0x1c> 800a114: 690f ldr r7, [r1, #16] 800a116: 2f00 cmp r7, #0 800a118: d0a9 beq.n 800a06e <__sflush_r+0x1a> 800a11a: 0793 lsls r3, r2, #30 800a11c: 680e ldr r6, [r1, #0] 800a11e: bf08 it eq 800a120: 694b ldreq r3, [r1, #20] 800a122: 600f str r7, [r1, #0] 800a124: bf18 it ne 800a126: 2300 movne r3, #0 800a128: eba6 0807 sub.w r8, r6, r7 800a12c: 608b str r3, [r1, #8] 800a12e: f1b8 0f00 cmp.w r8, #0 800a132: dd9c ble.n 800a06e <__sflush_r+0x1a> 800a134: 6a21 ldr r1, [r4, #32] 800a136: 6aa6 ldr r6, [r4, #40] ; 0x28 800a138: 4643 mov r3, r8 800a13a: 463a mov r2, r7 800a13c: 4628 mov r0, r5 800a13e: 47b0 blx r6 800a140: 2800 cmp r0, #0 800a142: dc06 bgt.n 800a152 <__sflush_r+0xfe> 800a144: 89a3 ldrh r3, [r4, #12] 800a146: f043 0340 orr.w r3, r3, #64 ; 0x40 800a14a: 81a3 strh r3, [r4, #12] 800a14c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800a150: e78e b.n 800a070 <__sflush_r+0x1c> 800a152: 4407 add r7, r0 800a154: eba8 0800 sub.w r8, r8, r0 800a158: e7e9 b.n 800a12e <__sflush_r+0xda> 800a15a: bf00 nop 800a15c: 20400001 .word 0x20400001 0800a160 <_fflush_r>: 800a160: b538 push {r3, r4, r5, lr} 800a162: 690b ldr r3, [r1, #16] 800a164: 4605 mov r5, r0 800a166: 460c mov r4, r1 800a168: b913 cbnz r3, 800a170 <_fflush_r+0x10> 800a16a: 2500 movs r5, #0 800a16c: 4628 mov r0, r5 800a16e: bd38 pop {r3, r4, r5, pc} 800a170: b118 cbz r0, 800a17a <_fflush_r+0x1a> 800a172: 6983 ldr r3, [r0, #24] 800a174: b90b cbnz r3, 800a17a <_fflush_r+0x1a> 800a176: f000 f887 bl 800a288 <__sinit> 800a17a: 4b14 ldr r3, [pc, #80] ; (800a1cc <_fflush_r+0x6c>) 800a17c: 429c cmp r4, r3 800a17e: d11b bne.n 800a1b8 <_fflush_r+0x58> 800a180: 686c ldr r4, [r5, #4] 800a182: f9b4 300c ldrsh.w r3, [r4, #12] 800a186: 2b00 cmp r3, #0 800a188: d0ef beq.n 800a16a <_fflush_r+0xa> 800a18a: 6e62 ldr r2, [r4, #100] ; 0x64 800a18c: 07d0 lsls r0, r2, #31 800a18e: d404 bmi.n 800a19a <_fflush_r+0x3a> 800a190: 0599 lsls r1, r3, #22 800a192: d402 bmi.n 800a19a <_fflush_r+0x3a> 800a194: 6da0 ldr r0, [r4, #88] ; 0x58 800a196: f000 f915 bl 800a3c4 <__retarget_lock_acquire_recursive> 800a19a: 4628 mov r0, r5 800a19c: 4621 mov r1, r4 800a19e: f7ff ff59 bl 800a054 <__sflush_r> 800a1a2: 6e63 ldr r3, [r4, #100] ; 0x64 800a1a4: 07da lsls r2, r3, #31 800a1a6: 4605 mov r5, r0 800a1a8: d4e0 bmi.n 800a16c <_fflush_r+0xc> 800a1aa: 89a3 ldrh r3, [r4, #12] 800a1ac: 059b lsls r3, r3, #22 800a1ae: d4dd bmi.n 800a16c <_fflush_r+0xc> 800a1b0: 6da0 ldr r0, [r4, #88] ; 0x58 800a1b2: f000 f908 bl 800a3c6 <__retarget_lock_release_recursive> 800a1b6: e7d9 b.n 800a16c <_fflush_r+0xc> 800a1b8: 4b05 ldr r3, [pc, #20] ; (800a1d0 <_fflush_r+0x70>) 800a1ba: 429c cmp r4, r3 800a1bc: d101 bne.n 800a1c2 <_fflush_r+0x62> 800a1be: 68ac ldr r4, [r5, #8] 800a1c0: e7df b.n 800a182 <_fflush_r+0x22> 800a1c2: 4b04 ldr r3, [pc, #16] ; (800a1d4 <_fflush_r+0x74>) 800a1c4: 429c cmp r4, r3 800a1c6: bf08 it eq 800a1c8: 68ec ldreq r4, [r5, #12] 800a1ca: e7da b.n 800a182 <_fflush_r+0x22> 800a1cc: 0800a9fc .word 0x0800a9fc 800a1d0: 0800aa1c .word 0x0800aa1c 800a1d4: 0800a9dc .word 0x0800a9dc 0800a1d8 : 800a1d8: 2300 movs r3, #0 800a1da: b510 push {r4, lr} 800a1dc: 4604 mov r4, r0 800a1de: e9c0 3300 strd r3, r3, [r0] 800a1e2: e9c0 3304 strd r3, r3, [r0, #16] 800a1e6: 6083 str r3, [r0, #8] 800a1e8: 8181 strh r1, [r0, #12] 800a1ea: 6643 str r3, [r0, #100] ; 0x64 800a1ec: 81c2 strh r2, [r0, #14] 800a1ee: 6183 str r3, [r0, #24] 800a1f0: 4619 mov r1, r3 800a1f2: 2208 movs r2, #8 800a1f4: 305c adds r0, #92 ; 0x5c 800a1f6: f7ff fb6f bl 80098d8 800a1fa: 4b05 ldr r3, [pc, #20] ; (800a210 ) 800a1fc: 6263 str r3, [r4, #36] ; 0x24 800a1fe: 4b05 ldr r3, [pc, #20] ; (800a214 ) 800a200: 62a3 str r3, [r4, #40] ; 0x28 800a202: 4b05 ldr r3, [pc, #20] ; (800a218 ) 800a204: 62e3 str r3, [r4, #44] ; 0x2c 800a206: 4b05 ldr r3, [pc, #20] ; (800a21c ) 800a208: 6224 str r4, [r4, #32] 800a20a: 6323 str r3, [r4, #48] ; 0x30 800a20c: bd10 pop {r4, pc} 800a20e: bf00 nop 800a210: 0800a68d .word 0x0800a68d 800a214: 0800a6af .word 0x0800a6af 800a218: 0800a6e7 .word 0x0800a6e7 800a21c: 0800a70b .word 0x0800a70b 0800a220 <_cleanup_r>: 800a220: 4901 ldr r1, [pc, #4] ; (800a228 <_cleanup_r+0x8>) 800a222: f000 b8af b.w 800a384 <_fwalk_reent> 800a226: bf00 nop 800a228: 0800a161 .word 0x0800a161 0800a22c <__sfmoreglue>: 800a22c: b570 push {r4, r5, r6, lr} 800a22e: 1e4a subs r2, r1, #1 800a230: 2568 movs r5, #104 ; 0x68 800a232: 4355 muls r5, r2 800a234: 460e mov r6, r1 800a236: f105 0174 add.w r1, r5, #116 ; 0x74 800a23a: f000 f979 bl 800a530 <_malloc_r> 800a23e: 4604 mov r4, r0 800a240: b140 cbz r0, 800a254 <__sfmoreglue+0x28> 800a242: 2100 movs r1, #0 800a244: e9c0 1600 strd r1, r6, [r0] 800a248: 300c adds r0, #12 800a24a: 60a0 str r0, [r4, #8] 800a24c: f105 0268 add.w r2, r5, #104 ; 0x68 800a250: f7ff fb42 bl 80098d8 800a254: 4620 mov r0, r4 800a256: bd70 pop {r4, r5, r6, pc} 0800a258 <__sfp_lock_acquire>: 800a258: 4801 ldr r0, [pc, #4] ; (800a260 <__sfp_lock_acquire+0x8>) 800a25a: f000 b8b3 b.w 800a3c4 <__retarget_lock_acquire_recursive> 800a25e: bf00 nop 800a260: 24001d6c .word 0x24001d6c 0800a264 <__sfp_lock_release>: 800a264: 4801 ldr r0, [pc, #4] ; (800a26c <__sfp_lock_release+0x8>) 800a266: f000 b8ae b.w 800a3c6 <__retarget_lock_release_recursive> 800a26a: bf00 nop 800a26c: 24001d6c .word 0x24001d6c 0800a270 <__sinit_lock_acquire>: 800a270: 4801 ldr r0, [pc, #4] ; (800a278 <__sinit_lock_acquire+0x8>) 800a272: f000 b8a7 b.w 800a3c4 <__retarget_lock_acquire_recursive> 800a276: bf00 nop 800a278: 24001d67 .word 0x24001d67 0800a27c <__sinit_lock_release>: 800a27c: 4801 ldr r0, [pc, #4] ; (800a284 <__sinit_lock_release+0x8>) 800a27e: f000 b8a2 b.w 800a3c6 <__retarget_lock_release_recursive> 800a282: bf00 nop 800a284: 24001d67 .word 0x24001d67 0800a288 <__sinit>: 800a288: b510 push {r4, lr} 800a28a: 4604 mov r4, r0 800a28c: f7ff fff0 bl 800a270 <__sinit_lock_acquire> 800a290: 69a3 ldr r3, [r4, #24] 800a292: b11b cbz r3, 800a29c <__sinit+0x14> 800a294: e8bd 4010 ldmia.w sp!, {r4, lr} 800a298: f7ff bff0 b.w 800a27c <__sinit_lock_release> 800a29c: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 800a2a0: 6523 str r3, [r4, #80] ; 0x50 800a2a2: 4b13 ldr r3, [pc, #76] ; (800a2f0 <__sinit+0x68>) 800a2a4: 4a13 ldr r2, [pc, #76] ; (800a2f4 <__sinit+0x6c>) 800a2a6: 681b ldr r3, [r3, #0] 800a2a8: 62a2 str r2, [r4, #40] ; 0x28 800a2aa: 42a3 cmp r3, r4 800a2ac: bf04 itt eq 800a2ae: 2301 moveq r3, #1 800a2b0: 61a3 streq r3, [r4, #24] 800a2b2: 4620 mov r0, r4 800a2b4: f000 f820 bl 800a2f8 <__sfp> 800a2b8: 6060 str r0, [r4, #4] 800a2ba: 4620 mov r0, r4 800a2bc: f000 f81c bl 800a2f8 <__sfp> 800a2c0: 60a0 str r0, [r4, #8] 800a2c2: 4620 mov r0, r4 800a2c4: f000 f818 bl 800a2f8 <__sfp> 800a2c8: 2200 movs r2, #0 800a2ca: 60e0 str r0, [r4, #12] 800a2cc: 2104 movs r1, #4 800a2ce: 6860 ldr r0, [r4, #4] 800a2d0: f7ff ff82 bl 800a1d8 800a2d4: 68a0 ldr r0, [r4, #8] 800a2d6: 2201 movs r2, #1 800a2d8: 2109 movs r1, #9 800a2da: f7ff ff7d bl 800a1d8 800a2de: 68e0 ldr r0, [r4, #12] 800a2e0: 2202 movs r2, #2 800a2e2: 2112 movs r1, #18 800a2e4: f7ff ff78 bl 800a1d8 800a2e8: 2301 movs r3, #1 800a2ea: 61a3 str r3, [r4, #24] 800a2ec: e7d2 b.n 800a294 <__sinit+0xc> 800a2ee: bf00 nop 800a2f0: 0800a9a4 .word 0x0800a9a4 800a2f4: 0800a221 .word 0x0800a221 0800a2f8 <__sfp>: 800a2f8: b5f8 push {r3, r4, r5, r6, r7, lr} 800a2fa: 4607 mov r7, r0 800a2fc: f7ff ffac bl 800a258 <__sfp_lock_acquire> 800a300: 4b1e ldr r3, [pc, #120] ; (800a37c <__sfp+0x84>) 800a302: 681e ldr r6, [r3, #0] 800a304: 69b3 ldr r3, [r6, #24] 800a306: b913 cbnz r3, 800a30e <__sfp+0x16> 800a308: 4630 mov r0, r6 800a30a: f7ff ffbd bl 800a288 <__sinit> 800a30e: 3648 adds r6, #72 ; 0x48 800a310: e9d6 3401 ldrd r3, r4, [r6, #4] 800a314: 3b01 subs r3, #1 800a316: d503 bpl.n 800a320 <__sfp+0x28> 800a318: 6833 ldr r3, [r6, #0] 800a31a: b30b cbz r3, 800a360 <__sfp+0x68> 800a31c: 6836 ldr r6, [r6, #0] 800a31e: e7f7 b.n 800a310 <__sfp+0x18> 800a320: f9b4 500c ldrsh.w r5, [r4, #12] 800a324: b9d5 cbnz r5, 800a35c <__sfp+0x64> 800a326: 4b16 ldr r3, [pc, #88] ; (800a380 <__sfp+0x88>) 800a328: 60e3 str r3, [r4, #12] 800a32a: f104 0058 add.w r0, r4, #88 ; 0x58 800a32e: 6665 str r5, [r4, #100] ; 0x64 800a330: f000 f847 bl 800a3c2 <__retarget_lock_init_recursive> 800a334: f7ff ff96 bl 800a264 <__sfp_lock_release> 800a338: e9c4 5501 strd r5, r5, [r4, #4] 800a33c: e9c4 5504 strd r5, r5, [r4, #16] 800a340: 6025 str r5, [r4, #0] 800a342: 61a5 str r5, [r4, #24] 800a344: 2208 movs r2, #8 800a346: 4629 mov r1, r5 800a348: f104 005c add.w r0, r4, #92 ; 0x5c 800a34c: f7ff fac4 bl 80098d8 800a350: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 800a354: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 800a358: 4620 mov r0, r4 800a35a: bdf8 pop {r3, r4, r5, r6, r7, pc} 800a35c: 3468 adds r4, #104 ; 0x68 800a35e: e7d9 b.n 800a314 <__sfp+0x1c> 800a360: 2104 movs r1, #4 800a362: 4638 mov r0, r7 800a364: f7ff ff62 bl 800a22c <__sfmoreglue> 800a368: 4604 mov r4, r0 800a36a: 6030 str r0, [r6, #0] 800a36c: 2800 cmp r0, #0 800a36e: d1d5 bne.n 800a31c <__sfp+0x24> 800a370: f7ff ff78 bl 800a264 <__sfp_lock_release> 800a374: 230c movs r3, #12 800a376: 603b str r3, [r7, #0] 800a378: e7ee b.n 800a358 <__sfp+0x60> 800a37a: bf00 nop 800a37c: 0800a9a4 .word 0x0800a9a4 800a380: ffff0001 .word 0xffff0001 0800a384 <_fwalk_reent>: 800a384: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800a388: 4606 mov r6, r0 800a38a: 4688 mov r8, r1 800a38c: f100 0448 add.w r4, r0, #72 ; 0x48 800a390: 2700 movs r7, #0 800a392: e9d4 9501 ldrd r9, r5, [r4, #4] 800a396: f1b9 0901 subs.w r9, r9, #1 800a39a: d505 bpl.n 800a3a8 <_fwalk_reent+0x24> 800a39c: 6824 ldr r4, [r4, #0] 800a39e: 2c00 cmp r4, #0 800a3a0: d1f7 bne.n 800a392 <_fwalk_reent+0xe> 800a3a2: 4638 mov r0, r7 800a3a4: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800a3a8: 89ab ldrh r3, [r5, #12] 800a3aa: 2b01 cmp r3, #1 800a3ac: d907 bls.n 800a3be <_fwalk_reent+0x3a> 800a3ae: f9b5 300e ldrsh.w r3, [r5, #14] 800a3b2: 3301 adds r3, #1 800a3b4: d003 beq.n 800a3be <_fwalk_reent+0x3a> 800a3b6: 4629 mov r1, r5 800a3b8: 4630 mov r0, r6 800a3ba: 47c0 blx r8 800a3bc: 4307 orrs r7, r0 800a3be: 3568 adds r5, #104 ; 0x68 800a3c0: e7e9 b.n 800a396 <_fwalk_reent+0x12> 0800a3c2 <__retarget_lock_init_recursive>: 800a3c2: 4770 bx lr 0800a3c4 <__retarget_lock_acquire_recursive>: 800a3c4: 4770 bx lr 0800a3c6 <__retarget_lock_release_recursive>: 800a3c6: 4770 bx lr 0800a3c8 <__swhatbuf_r>: 800a3c8: b570 push {r4, r5, r6, lr} 800a3ca: 460e mov r6, r1 800a3cc: f9b1 100e ldrsh.w r1, [r1, #14] 800a3d0: 2900 cmp r1, #0 800a3d2: b096 sub sp, #88 ; 0x58 800a3d4: 4614 mov r4, r2 800a3d6: 461d mov r5, r3 800a3d8: da07 bge.n 800a3ea <__swhatbuf_r+0x22> 800a3da: 2300 movs r3, #0 800a3dc: 602b str r3, [r5, #0] 800a3de: 89b3 ldrh r3, [r6, #12] 800a3e0: 061a lsls r2, r3, #24 800a3e2: d410 bmi.n 800a406 <__swhatbuf_r+0x3e> 800a3e4: f44f 6380 mov.w r3, #1024 ; 0x400 800a3e8: e00e b.n 800a408 <__swhatbuf_r+0x40> 800a3ea: 466a mov r2, sp 800a3ec: f000 f9b4 bl 800a758 <_fstat_r> 800a3f0: 2800 cmp r0, #0 800a3f2: dbf2 blt.n 800a3da <__swhatbuf_r+0x12> 800a3f4: 9a01 ldr r2, [sp, #4] 800a3f6: f402 4270 and.w r2, r2, #61440 ; 0xf000 800a3fa: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 800a3fe: 425a negs r2, r3 800a400: 415a adcs r2, r3 800a402: 602a str r2, [r5, #0] 800a404: e7ee b.n 800a3e4 <__swhatbuf_r+0x1c> 800a406: 2340 movs r3, #64 ; 0x40 800a408: 2000 movs r0, #0 800a40a: 6023 str r3, [r4, #0] 800a40c: b016 add sp, #88 ; 0x58 800a40e: bd70 pop {r4, r5, r6, pc} 0800a410 <__smakebuf_r>: 800a410: 898b ldrh r3, [r1, #12] 800a412: b573 push {r0, r1, r4, r5, r6, lr} 800a414: 079d lsls r5, r3, #30 800a416: 4606 mov r6, r0 800a418: 460c mov r4, r1 800a41a: d507 bpl.n 800a42c <__smakebuf_r+0x1c> 800a41c: f104 0347 add.w r3, r4, #71 ; 0x47 800a420: 6023 str r3, [r4, #0] 800a422: 6123 str r3, [r4, #16] 800a424: 2301 movs r3, #1 800a426: 6163 str r3, [r4, #20] 800a428: b002 add sp, #8 800a42a: bd70 pop {r4, r5, r6, pc} 800a42c: ab01 add r3, sp, #4 800a42e: 466a mov r2, sp 800a430: f7ff ffca bl 800a3c8 <__swhatbuf_r> 800a434: 9900 ldr r1, [sp, #0] 800a436: 4605 mov r5, r0 800a438: 4630 mov r0, r6 800a43a: f000 f879 bl 800a530 <_malloc_r> 800a43e: b948 cbnz r0, 800a454 <__smakebuf_r+0x44> 800a440: f9b4 300c ldrsh.w r3, [r4, #12] 800a444: 059a lsls r2, r3, #22 800a446: d4ef bmi.n 800a428 <__smakebuf_r+0x18> 800a448: f023 0303 bic.w r3, r3, #3 800a44c: f043 0302 orr.w r3, r3, #2 800a450: 81a3 strh r3, [r4, #12] 800a452: e7e3 b.n 800a41c <__smakebuf_r+0xc> 800a454: 4b0d ldr r3, [pc, #52] ; (800a48c <__smakebuf_r+0x7c>) 800a456: 62b3 str r3, [r6, #40] ; 0x28 800a458: 89a3 ldrh r3, [r4, #12] 800a45a: 6020 str r0, [r4, #0] 800a45c: f043 0380 orr.w r3, r3, #128 ; 0x80 800a460: 81a3 strh r3, [r4, #12] 800a462: 9b00 ldr r3, [sp, #0] 800a464: 6163 str r3, [r4, #20] 800a466: 9b01 ldr r3, [sp, #4] 800a468: 6120 str r0, [r4, #16] 800a46a: b15b cbz r3, 800a484 <__smakebuf_r+0x74> 800a46c: f9b4 100e ldrsh.w r1, [r4, #14] 800a470: 4630 mov r0, r6 800a472: f000 f983 bl 800a77c <_isatty_r> 800a476: b128 cbz r0, 800a484 <__smakebuf_r+0x74> 800a478: 89a3 ldrh r3, [r4, #12] 800a47a: f023 0303 bic.w r3, r3, #3 800a47e: f043 0301 orr.w r3, r3, #1 800a482: 81a3 strh r3, [r4, #12] 800a484: 89a0 ldrh r0, [r4, #12] 800a486: 4305 orrs r5, r0 800a488: 81a5 strh r5, [r4, #12] 800a48a: e7cd b.n 800a428 <__smakebuf_r+0x18> 800a48c: 0800a221 .word 0x0800a221 0800a490 <_free_r>: 800a490: b537 push {r0, r1, r2, r4, r5, lr} 800a492: 2900 cmp r1, #0 800a494: d048 beq.n 800a528 <_free_r+0x98> 800a496: f851 3c04 ldr.w r3, [r1, #-4] 800a49a: 9001 str r0, [sp, #4] 800a49c: 2b00 cmp r3, #0 800a49e: f1a1 0404 sub.w r4, r1, #4 800a4a2: bfb8 it lt 800a4a4: 18e4 addlt r4, r4, r3 800a4a6: f000 f98b bl 800a7c0 <__malloc_lock> 800a4aa: 4a20 ldr r2, [pc, #128] ; (800a52c <_free_r+0x9c>) 800a4ac: 9801 ldr r0, [sp, #4] 800a4ae: 6813 ldr r3, [r2, #0] 800a4b0: 4615 mov r5, r2 800a4b2: b933 cbnz r3, 800a4c2 <_free_r+0x32> 800a4b4: 6063 str r3, [r4, #4] 800a4b6: 6014 str r4, [r2, #0] 800a4b8: b003 add sp, #12 800a4ba: e8bd 4030 ldmia.w sp!, {r4, r5, lr} 800a4be: f000 b985 b.w 800a7cc <__malloc_unlock> 800a4c2: 42a3 cmp r3, r4 800a4c4: d90b bls.n 800a4de <_free_r+0x4e> 800a4c6: 6821 ldr r1, [r4, #0] 800a4c8: 1862 adds r2, r4, r1 800a4ca: 4293 cmp r3, r2 800a4cc: bf04 itt eq 800a4ce: 681a ldreq r2, [r3, #0] 800a4d0: 685b ldreq r3, [r3, #4] 800a4d2: 6063 str r3, [r4, #4] 800a4d4: bf04 itt eq 800a4d6: 1852 addeq r2, r2, r1 800a4d8: 6022 streq r2, [r4, #0] 800a4da: 602c str r4, [r5, #0] 800a4dc: e7ec b.n 800a4b8 <_free_r+0x28> 800a4de: 461a mov r2, r3 800a4e0: 685b ldr r3, [r3, #4] 800a4e2: b10b cbz r3, 800a4e8 <_free_r+0x58> 800a4e4: 42a3 cmp r3, r4 800a4e6: d9fa bls.n 800a4de <_free_r+0x4e> 800a4e8: 6811 ldr r1, [r2, #0] 800a4ea: 1855 adds r5, r2, r1 800a4ec: 42a5 cmp r5, r4 800a4ee: d10b bne.n 800a508 <_free_r+0x78> 800a4f0: 6824 ldr r4, [r4, #0] 800a4f2: 4421 add r1, r4 800a4f4: 1854 adds r4, r2, r1 800a4f6: 42a3 cmp r3, r4 800a4f8: 6011 str r1, [r2, #0] 800a4fa: d1dd bne.n 800a4b8 <_free_r+0x28> 800a4fc: 681c ldr r4, [r3, #0] 800a4fe: 685b ldr r3, [r3, #4] 800a500: 6053 str r3, [r2, #4] 800a502: 4421 add r1, r4 800a504: 6011 str r1, [r2, #0] 800a506: e7d7 b.n 800a4b8 <_free_r+0x28> 800a508: d902 bls.n 800a510 <_free_r+0x80> 800a50a: 230c movs r3, #12 800a50c: 6003 str r3, [r0, #0] 800a50e: e7d3 b.n 800a4b8 <_free_r+0x28> 800a510: 6825 ldr r5, [r4, #0] 800a512: 1961 adds r1, r4, r5 800a514: 428b cmp r3, r1 800a516: bf04 itt eq 800a518: 6819 ldreq r1, [r3, #0] 800a51a: 685b ldreq r3, [r3, #4] 800a51c: 6063 str r3, [r4, #4] 800a51e: bf04 itt eq 800a520: 1949 addeq r1, r1, r5 800a522: 6021 streq r1, [r4, #0] 800a524: 6054 str r4, [r2, #4] 800a526: e7c7 b.n 800a4b8 <_free_r+0x28> 800a528: b003 add sp, #12 800a52a: bd30 pop {r4, r5, pc} 800a52c: 24000434 .word 0x24000434 0800a530 <_malloc_r>: 800a530: b5f8 push {r3, r4, r5, r6, r7, lr} 800a532: 1ccd adds r5, r1, #3 800a534: f025 0503 bic.w r5, r5, #3 800a538: 3508 adds r5, #8 800a53a: 2d0c cmp r5, #12 800a53c: bf38 it cc 800a53e: 250c movcc r5, #12 800a540: 2d00 cmp r5, #0 800a542: 4606 mov r6, r0 800a544: db01 blt.n 800a54a <_malloc_r+0x1a> 800a546: 42a9 cmp r1, r5 800a548: d903 bls.n 800a552 <_malloc_r+0x22> 800a54a: 230c movs r3, #12 800a54c: 6033 str r3, [r6, #0] 800a54e: 2000 movs r0, #0 800a550: bdf8 pop {r3, r4, r5, r6, r7, pc} 800a552: f000 f935 bl 800a7c0 <__malloc_lock> 800a556: 4921 ldr r1, [pc, #132] ; (800a5dc <_malloc_r+0xac>) 800a558: 680a ldr r2, [r1, #0] 800a55a: 4614 mov r4, r2 800a55c: b99c cbnz r4, 800a586 <_malloc_r+0x56> 800a55e: 4f20 ldr r7, [pc, #128] ; (800a5e0 <_malloc_r+0xb0>) 800a560: 683b ldr r3, [r7, #0] 800a562: b923 cbnz r3, 800a56e <_malloc_r+0x3e> 800a564: 4621 mov r1, r4 800a566: 4630 mov r0, r6 800a568: f000 f83c bl 800a5e4 <_sbrk_r> 800a56c: 6038 str r0, [r7, #0] 800a56e: 4629 mov r1, r5 800a570: 4630 mov r0, r6 800a572: f000 f837 bl 800a5e4 <_sbrk_r> 800a576: 1c43 adds r3, r0, #1 800a578: d123 bne.n 800a5c2 <_malloc_r+0x92> 800a57a: 230c movs r3, #12 800a57c: 6033 str r3, [r6, #0] 800a57e: 4630 mov r0, r6 800a580: f000 f924 bl 800a7cc <__malloc_unlock> 800a584: e7e3 b.n 800a54e <_malloc_r+0x1e> 800a586: 6823 ldr r3, [r4, #0] 800a588: 1b5b subs r3, r3, r5 800a58a: d417 bmi.n 800a5bc <_malloc_r+0x8c> 800a58c: 2b0b cmp r3, #11 800a58e: d903 bls.n 800a598 <_malloc_r+0x68> 800a590: 6023 str r3, [r4, #0] 800a592: 441c add r4, r3 800a594: 6025 str r5, [r4, #0] 800a596: e004 b.n 800a5a2 <_malloc_r+0x72> 800a598: 6863 ldr r3, [r4, #4] 800a59a: 42a2 cmp r2, r4 800a59c: bf0c ite eq 800a59e: 600b streq r3, [r1, #0] 800a5a0: 6053 strne r3, [r2, #4] 800a5a2: 4630 mov r0, r6 800a5a4: f000 f912 bl 800a7cc <__malloc_unlock> 800a5a8: f104 000b add.w r0, r4, #11 800a5ac: 1d23 adds r3, r4, #4 800a5ae: f020 0007 bic.w r0, r0, #7 800a5b2: 1ac2 subs r2, r0, r3 800a5b4: d0cc beq.n 800a550 <_malloc_r+0x20> 800a5b6: 1a1b subs r3, r3, r0 800a5b8: 50a3 str r3, [r4, r2] 800a5ba: e7c9 b.n 800a550 <_malloc_r+0x20> 800a5bc: 4622 mov r2, r4 800a5be: 6864 ldr r4, [r4, #4] 800a5c0: e7cc b.n 800a55c <_malloc_r+0x2c> 800a5c2: 1cc4 adds r4, r0, #3 800a5c4: f024 0403 bic.w r4, r4, #3 800a5c8: 42a0 cmp r0, r4 800a5ca: d0e3 beq.n 800a594 <_malloc_r+0x64> 800a5cc: 1a21 subs r1, r4, r0 800a5ce: 4630 mov r0, r6 800a5d0: f000 f808 bl 800a5e4 <_sbrk_r> 800a5d4: 3001 adds r0, #1 800a5d6: d1dd bne.n 800a594 <_malloc_r+0x64> 800a5d8: e7cf b.n 800a57a <_malloc_r+0x4a> 800a5da: bf00 nop 800a5dc: 24000434 .word 0x24000434 800a5e0: 24000438 .word 0x24000438 0800a5e4 <_sbrk_r>: 800a5e4: b538 push {r3, r4, r5, lr} 800a5e6: 4d06 ldr r5, [pc, #24] ; (800a600 <_sbrk_r+0x1c>) 800a5e8: 2300 movs r3, #0 800a5ea: 4604 mov r4, r0 800a5ec: 4608 mov r0, r1 800a5ee: 602b str r3, [r5, #0] 800a5f0: f7f6 fe78 bl 80012e4 <_sbrk> 800a5f4: 1c43 adds r3, r0, #1 800a5f6: d102 bne.n 800a5fe <_sbrk_r+0x1a> 800a5f8: 682b ldr r3, [r5, #0] 800a5fa: b103 cbz r3, 800a5fe <_sbrk_r+0x1a> 800a5fc: 6023 str r3, [r4, #0] 800a5fe: bd38 pop {r3, r4, r5, pc} 800a600: 24001d70 .word 0x24001d70 0800a604 <_raise_r>: 800a604: 291f cmp r1, #31 800a606: b538 push {r3, r4, r5, lr} 800a608: 4604 mov r4, r0 800a60a: 460d mov r5, r1 800a60c: d904 bls.n 800a618 <_raise_r+0x14> 800a60e: 2316 movs r3, #22 800a610: 6003 str r3, [r0, #0] 800a612: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800a616: bd38 pop {r3, r4, r5, pc} 800a618: 6c42 ldr r2, [r0, #68] ; 0x44 800a61a: b112 cbz r2, 800a622 <_raise_r+0x1e> 800a61c: f852 3021 ldr.w r3, [r2, r1, lsl #2] 800a620: b94b cbnz r3, 800a636 <_raise_r+0x32> 800a622: 4620 mov r0, r4 800a624: f000 f830 bl 800a688 <_getpid_r> 800a628: 462a mov r2, r5 800a62a: 4601 mov r1, r0 800a62c: 4620 mov r0, r4 800a62e: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800a632: f000 b817 b.w 800a664 <_kill_r> 800a636: 2b01 cmp r3, #1 800a638: d00a beq.n 800a650 <_raise_r+0x4c> 800a63a: 1c59 adds r1, r3, #1 800a63c: d103 bne.n 800a646 <_raise_r+0x42> 800a63e: 2316 movs r3, #22 800a640: 6003 str r3, [r0, #0] 800a642: 2001 movs r0, #1 800a644: e7e7 b.n 800a616 <_raise_r+0x12> 800a646: 2400 movs r4, #0 800a648: f842 4025 str.w r4, [r2, r5, lsl #2] 800a64c: 4628 mov r0, r5 800a64e: 4798 blx r3 800a650: 2000 movs r0, #0 800a652: e7e0 b.n 800a616 <_raise_r+0x12> 0800a654 : 800a654: 4b02 ldr r3, [pc, #8] ; (800a660 ) 800a656: 4601 mov r1, r0 800a658: 6818 ldr r0, [r3, #0] 800a65a: f7ff bfd3 b.w 800a604 <_raise_r> 800a65e: bf00 nop 800a660: 24000184 .word 0x24000184 0800a664 <_kill_r>: 800a664: b538 push {r3, r4, r5, lr} 800a666: 4d07 ldr r5, [pc, #28] ; (800a684 <_kill_r+0x20>) 800a668: 2300 movs r3, #0 800a66a: 4604 mov r4, r0 800a66c: 4608 mov r0, r1 800a66e: 4611 mov r1, r2 800a670: 602b str r3, [r5, #0] 800a672: f7f6 fdaf bl 80011d4 <_kill> 800a676: 1c43 adds r3, r0, #1 800a678: d102 bne.n 800a680 <_kill_r+0x1c> 800a67a: 682b ldr r3, [r5, #0] 800a67c: b103 cbz r3, 800a680 <_kill_r+0x1c> 800a67e: 6023 str r3, [r4, #0] 800a680: bd38 pop {r3, r4, r5, pc} 800a682: bf00 nop 800a684: 24001d70 .word 0x24001d70 0800a688 <_getpid_r>: 800a688: f7f6 bd9c b.w 80011c4 <_getpid> 0800a68c <__sread>: 800a68c: b510 push {r4, lr} 800a68e: 460c mov r4, r1 800a690: f9b1 100e ldrsh.w r1, [r1, #14] 800a694: f000 f8a0 bl 800a7d8 <_read_r> 800a698: 2800 cmp r0, #0 800a69a: bfab itete ge 800a69c: 6d63 ldrge r3, [r4, #84] ; 0x54 800a69e: 89a3 ldrhlt r3, [r4, #12] 800a6a0: 181b addge r3, r3, r0 800a6a2: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 800a6a6: bfac ite ge 800a6a8: 6563 strge r3, [r4, #84] ; 0x54 800a6aa: 81a3 strhlt r3, [r4, #12] 800a6ac: bd10 pop {r4, pc} 0800a6ae <__swrite>: 800a6ae: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800a6b2: 461f mov r7, r3 800a6b4: 898b ldrh r3, [r1, #12] 800a6b6: 05db lsls r3, r3, #23 800a6b8: 4605 mov r5, r0 800a6ba: 460c mov r4, r1 800a6bc: 4616 mov r6, r2 800a6be: d505 bpl.n 800a6cc <__swrite+0x1e> 800a6c0: f9b1 100e ldrsh.w r1, [r1, #14] 800a6c4: 2302 movs r3, #2 800a6c6: 2200 movs r2, #0 800a6c8: f000 f868 bl 800a79c <_lseek_r> 800a6cc: 89a3 ldrh r3, [r4, #12] 800a6ce: f9b4 100e ldrsh.w r1, [r4, #14] 800a6d2: f423 5380 bic.w r3, r3, #4096 ; 0x1000 800a6d6: 81a3 strh r3, [r4, #12] 800a6d8: 4632 mov r2, r6 800a6da: 463b mov r3, r7 800a6dc: 4628 mov r0, r5 800a6de: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800a6e2: f000 b817 b.w 800a714 <_write_r> 0800a6e6 <__sseek>: 800a6e6: b510 push {r4, lr} 800a6e8: 460c mov r4, r1 800a6ea: f9b1 100e ldrsh.w r1, [r1, #14] 800a6ee: f000 f855 bl 800a79c <_lseek_r> 800a6f2: 1c43 adds r3, r0, #1 800a6f4: 89a3 ldrh r3, [r4, #12] 800a6f6: bf15 itete ne 800a6f8: 6560 strne r0, [r4, #84] ; 0x54 800a6fa: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 800a6fe: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 800a702: 81a3 strheq r3, [r4, #12] 800a704: bf18 it ne 800a706: 81a3 strhne r3, [r4, #12] 800a708: bd10 pop {r4, pc} 0800a70a <__sclose>: 800a70a: f9b1 100e ldrsh.w r1, [r1, #14] 800a70e: f000 b813 b.w 800a738 <_close_r> ... 0800a714 <_write_r>: 800a714: b538 push {r3, r4, r5, lr} 800a716: 4d07 ldr r5, [pc, #28] ; (800a734 <_write_r+0x20>) 800a718: 4604 mov r4, r0 800a71a: 4608 mov r0, r1 800a71c: 4611 mov r1, r2 800a71e: 2200 movs r2, #0 800a720: 602a str r2, [r5, #0] 800a722: 461a mov r2, r3 800a724: f7f6 fd8d bl 8001242 <_write> 800a728: 1c43 adds r3, r0, #1 800a72a: d102 bne.n 800a732 <_write_r+0x1e> 800a72c: 682b ldr r3, [r5, #0] 800a72e: b103 cbz r3, 800a732 <_write_r+0x1e> 800a730: 6023 str r3, [r4, #0] 800a732: bd38 pop {r3, r4, r5, pc} 800a734: 24001d70 .word 0x24001d70 0800a738 <_close_r>: 800a738: b538 push {r3, r4, r5, lr} 800a73a: 4d06 ldr r5, [pc, #24] ; (800a754 <_close_r+0x1c>) 800a73c: 2300 movs r3, #0 800a73e: 4604 mov r4, r0 800a740: 4608 mov r0, r1 800a742: 602b str r3, [r5, #0] 800a744: f7f6 fd99 bl 800127a <_close> 800a748: 1c43 adds r3, r0, #1 800a74a: d102 bne.n 800a752 <_close_r+0x1a> 800a74c: 682b ldr r3, [r5, #0] 800a74e: b103 cbz r3, 800a752 <_close_r+0x1a> 800a750: 6023 str r3, [r4, #0] 800a752: bd38 pop {r3, r4, r5, pc} 800a754: 24001d70 .word 0x24001d70 0800a758 <_fstat_r>: 800a758: b538 push {r3, r4, r5, lr} 800a75a: 4d07 ldr r5, [pc, #28] ; (800a778 <_fstat_r+0x20>) 800a75c: 2300 movs r3, #0 800a75e: 4604 mov r4, r0 800a760: 4608 mov r0, r1 800a762: 4611 mov r1, r2 800a764: 602b str r3, [r5, #0] 800a766: f7f6 fd94 bl 8001292 <_fstat> 800a76a: 1c43 adds r3, r0, #1 800a76c: d102 bne.n 800a774 <_fstat_r+0x1c> 800a76e: 682b ldr r3, [r5, #0] 800a770: b103 cbz r3, 800a774 <_fstat_r+0x1c> 800a772: 6023 str r3, [r4, #0] 800a774: bd38 pop {r3, r4, r5, pc} 800a776: bf00 nop 800a778: 24001d70 .word 0x24001d70 0800a77c <_isatty_r>: 800a77c: b538 push {r3, r4, r5, lr} 800a77e: 4d06 ldr r5, [pc, #24] ; (800a798 <_isatty_r+0x1c>) 800a780: 2300 movs r3, #0 800a782: 4604 mov r4, r0 800a784: 4608 mov r0, r1 800a786: 602b str r3, [r5, #0] 800a788: f7f6 fd93 bl 80012b2 <_isatty> 800a78c: 1c43 adds r3, r0, #1 800a78e: d102 bne.n 800a796 <_isatty_r+0x1a> 800a790: 682b ldr r3, [r5, #0] 800a792: b103 cbz r3, 800a796 <_isatty_r+0x1a> 800a794: 6023 str r3, [r4, #0] 800a796: bd38 pop {r3, r4, r5, pc} 800a798: 24001d70 .word 0x24001d70 0800a79c <_lseek_r>: 800a79c: b538 push {r3, r4, r5, lr} 800a79e: 4d07 ldr r5, [pc, #28] ; (800a7bc <_lseek_r+0x20>) 800a7a0: 4604 mov r4, r0 800a7a2: 4608 mov r0, r1 800a7a4: 4611 mov r1, r2 800a7a6: 2200 movs r2, #0 800a7a8: 602a str r2, [r5, #0] 800a7aa: 461a mov r2, r3 800a7ac: f7f6 fd8c bl 80012c8 <_lseek> 800a7b0: 1c43 adds r3, r0, #1 800a7b2: d102 bne.n 800a7ba <_lseek_r+0x1e> 800a7b4: 682b ldr r3, [r5, #0] 800a7b6: b103 cbz r3, 800a7ba <_lseek_r+0x1e> 800a7b8: 6023 str r3, [r4, #0] 800a7ba: bd38 pop {r3, r4, r5, pc} 800a7bc: 24001d70 .word 0x24001d70 0800a7c0 <__malloc_lock>: 800a7c0: 4801 ldr r0, [pc, #4] ; (800a7c8 <__malloc_lock+0x8>) 800a7c2: f7ff bdff b.w 800a3c4 <__retarget_lock_acquire_recursive> 800a7c6: bf00 nop 800a7c8: 24001d68 .word 0x24001d68 0800a7cc <__malloc_unlock>: 800a7cc: 4801 ldr r0, [pc, #4] ; (800a7d4 <__malloc_unlock+0x8>) 800a7ce: f7ff bdfa b.w 800a3c6 <__retarget_lock_release_recursive> 800a7d2: bf00 nop 800a7d4: 24001d68 .word 0x24001d68 0800a7d8 <_read_r>: 800a7d8: b538 push {r3, r4, r5, lr} 800a7da: 4d07 ldr r5, [pc, #28] ; (800a7f8 <_read_r+0x20>) 800a7dc: 4604 mov r4, r0 800a7de: 4608 mov r0, r1 800a7e0: 4611 mov r1, r2 800a7e2: 2200 movs r2, #0 800a7e4: 602a str r2, [r5, #0] 800a7e6: 461a mov r2, r3 800a7e8: f7f6 fd0e bl 8001208 <_read> 800a7ec: 1c43 adds r3, r0, #1 800a7ee: d102 bne.n 800a7f6 <_read_r+0x1e> 800a7f0: 682b ldr r3, [r5, #0] 800a7f2: b103 cbz r3, 800a7f6 <_read_r+0x1e> 800a7f4: 6023 str r3, [r4, #0] 800a7f6: bd38 pop {r3, r4, r5, pc} 800a7f8: 24001d70 .word 0x24001d70 0800a7fc <_init>: 800a7fc: b5f8 push {r3, r4, r5, r6, r7, lr} 800a7fe: bf00 nop 800a800: bcf8 pop {r3, r4, r5, r6, r7} 800a802: bc08 pop {r3} 800a804: 469e mov lr, r3 800a806: 4770 bx lr 0800a808 <_fini>: 800a808: b5f8 push {r3, r4, r5, r6, r7, lr} 800a80a: bf00 nop 800a80c: bcf8 pop {r3, r4, r5, r6, r7} 800a80e: bc08 pop {r3} 800a810: 469e mov lr, r3 800a812: 4770 bx lr