cc1200_spi_ripper.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000002cc 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000a5fc 080002d0 080002d0 000102d0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000228 0800a8cc 0800a8cc 0001a8cc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .init_array 00000004 0800aaf4 0800aaf4 0001aaf4 2**2 CONTENTS, ALLOC, LOAD, DATA 4 .fini_array 00000004 0800aaf8 0800aaf8 0001aaf8 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .data 000001e8 24000000 0800aafc 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 6 .bss 00002b30 240001e8 0800ace4 000201e8 2**2 ALLOC 7 ._user_heap_stack 00000600 24002d18 0800ace4 00022d18 2**0 ALLOC 8 .ARM.attributes 0000002e 00000000 00000000 000201e8 2**0 CONTENTS, READONLY 9 .debug_info 0002d6e4 00000000 00000000 00020216 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 10 .debug_abbrev 000052e3 00000000 00000000 0004d8fa 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_aranges 00001740 00000000 00000000 00052be0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_ranges 00001578 00000000 00000000 00054320 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0003a87c 00000000 00000000 00055898 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 0001cbe9 00000000 00000000 00090114 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 001622b1 00000000 00000000 000accfd 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000053 00000000 00000000 0020efae 2**0 CONTENTS, READONLY 17 .debug_frame 00006a14 00000000 00000000 0020f004 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002d0 <__do_global_dtors_aux>: 80002d0: b510 push {r4, lr} 80002d2: 4c05 ldr r4, [pc, #20] ; (80002e8 <__do_global_dtors_aux+0x18>) 80002d4: 7823 ldrb r3, [r4, #0] 80002d6: b933 cbnz r3, 80002e6 <__do_global_dtors_aux+0x16> 80002d8: 4b04 ldr r3, [pc, #16] ; (80002ec <__do_global_dtors_aux+0x1c>) 80002da: b113 cbz r3, 80002e2 <__do_global_dtors_aux+0x12> 80002dc: 4804 ldr r0, [pc, #16] ; (80002f0 <__do_global_dtors_aux+0x20>) 80002de: f3af 8000 nop.w 80002e2: 2301 movs r3, #1 80002e4: 7023 strb r3, [r4, #0] 80002e6: bd10 pop {r4, pc} 80002e8: 240001e8 .word 0x240001e8 80002ec: 00000000 .word 0x00000000 80002f0: 0800a8b4 .word 0x0800a8b4 080002f4 : 80002f4: b508 push {r3, lr} 80002f6: 4b03 ldr r3, [pc, #12] ; (8000304 ) 80002f8: b11b cbz r3, 8000302 80002fa: 4903 ldr r1, [pc, #12] ; (8000308 ) 80002fc: 4803 ldr r0, [pc, #12] ; (800030c ) 80002fe: f3af 8000 nop.w 8000302: bd08 pop {r3, pc} 8000304: 00000000 .word 0x00000000 8000308: 240001ec .word 0x240001ec 800030c: 0800a8b4 .word 0x0800a8b4 08000310 : 8000310: f001 01ff and.w r1, r1, #255 ; 0xff 8000314: 2a10 cmp r2, #16 8000316: db2b blt.n 8000370 8000318: f010 0f07 tst.w r0, #7 800031c: d008 beq.n 8000330 800031e: f810 3b01 ldrb.w r3, [r0], #1 8000322: 3a01 subs r2, #1 8000324: 428b cmp r3, r1 8000326: d02d beq.n 8000384 8000328: f010 0f07 tst.w r0, #7 800032c: b342 cbz r2, 8000380 800032e: d1f6 bne.n 800031e 8000330: b4f0 push {r4, r5, r6, r7} 8000332: ea41 2101 orr.w r1, r1, r1, lsl #8 8000336: ea41 4101 orr.w r1, r1, r1, lsl #16 800033a: f022 0407 bic.w r4, r2, #7 800033e: f07f 0700 mvns.w r7, #0 8000342: 2300 movs r3, #0 8000344: e8f0 5602 ldrd r5, r6, [r0], #8 8000348: 3c08 subs r4, #8 800034a: ea85 0501 eor.w r5, r5, r1 800034e: ea86 0601 eor.w r6, r6, r1 8000352: fa85 f547 uadd8 r5, r5, r7 8000356: faa3 f587 sel r5, r3, r7 800035a: fa86 f647 uadd8 r6, r6, r7 800035e: faa5 f687 sel r6, r5, r7 8000362: b98e cbnz r6, 8000388 8000364: d1ee bne.n 8000344 8000366: bcf0 pop {r4, r5, r6, r7} 8000368: f001 01ff and.w r1, r1, #255 ; 0xff 800036c: f002 0207 and.w r2, r2, #7 8000370: b132 cbz r2, 8000380 8000372: f810 3b01 ldrb.w r3, [r0], #1 8000376: 3a01 subs r2, #1 8000378: ea83 0301 eor.w r3, r3, r1 800037c: b113 cbz r3, 8000384 800037e: d1f8 bne.n 8000372 8000380: 2000 movs r0, #0 8000382: 4770 bx lr 8000384: 3801 subs r0, #1 8000386: 4770 bx lr 8000388: 2d00 cmp r5, #0 800038a: bf06 itte eq 800038c: 4635 moveq r5, r6 800038e: 3803 subeq r0, #3 8000390: 3807 subne r0, #7 8000392: f015 0f01 tst.w r5, #1 8000396: d107 bne.n 80003a8 8000398: 3001 adds r0, #1 800039a: f415 7f80 tst.w r5, #256 ; 0x100 800039e: bf02 ittt eq 80003a0: 3001 addeq r0, #1 80003a2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000 80003a6: 3001 addeq r0, #1 80003a8: bcf0 pop {r4, r5, r6, r7} 80003aa: 3801 subs r0, #1 80003ac: 4770 bx lr 80003ae: bf00 nop 080003b0 : * @rmtoll CR1 SPE LL_SPI_Enable * @param SPIx SPI Instance * @retval None */ __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) { 80003b0: b480 push {r7} 80003b2: b083 sub sp, #12 80003b4: af00 add r7, sp, #0 80003b6: 6078 str r0, [r7, #4] SET_BIT(SPIx->CR1, SPI_CR1_SPE); 80003b8: 687b ldr r3, [r7, #4] 80003ba: 681b ldr r3, [r3, #0] 80003bc: f043 0201 orr.w r2, r3, #1 80003c0: 687b ldr r3, [r7, #4] 80003c2: 601a str r2, [r3, #0] } 80003c4: bf00 nop 80003c6: 370c adds r7, #12 80003c8: 46bd mov sp, r7 80003ca: f85d 7b04 ldr.w r7, [sp], #4 80003ce: 4770 bx lr 080003d0 : * @rmtoll CR1 SPE LL_SPI_Disable * @param SPIx SPI Instance * @retval None */ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) { 80003d0: b480 push {r7} 80003d2: b083 sub sp, #12 80003d4: af00 add r7, sp, #0 80003d6: 6078 str r0, [r7, #4] CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 80003d8: 687b ldr r3, [r7, #4] 80003da: 681b ldr r3, [r3, #0] 80003dc: f023 0201 bic.w r2, r3, #1 80003e0: 687b ldr r3, [r7, #4] 80003e2: 601a str r2, [r3, #0] } 80003e4: bf00 nop 80003e6: 370c adds r7, #12 80003e8: 46bd mov sp, r7 80003ea: f85d 7b04 ldr.w r7, [sp], #4 80003ee: 4770 bx lr 080003f0 : * @param SPIx SPI Instance * @param Count 0..0xFFFF * @retval None */ __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count) { 80003f0: b480 push {r7} 80003f2: b083 sub sp, #12 80003f4: af00 add r7, sp, #0 80003f6: 6078 str r0, [r7, #4] 80003f8: 6039 str r1, [r7, #0] MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count); 80003fa: 687b ldr r3, [r7, #4] 80003fc: 685a ldr r2, [r3, #4] 80003fe: 4b06 ldr r3, [pc, #24] ; (8000418 ) 8000400: 4013 ands r3, r2 8000402: 683a ldr r2, [r7, #0] 8000404: 431a orrs r2, r3 8000406: 687b ldr r3, [r7, #4] 8000408: 605a str r2, [r3, #4] } 800040a: bf00 nop 800040c: 370c adds r7, #12 800040e: 46bd mov sp, r7 8000410: f85d 7b04 ldr.w r7, [sp], #4 8000414: 4770 bx lr 8000416: bf00 nop 8000418: ffff0000 .word 0xffff0000 0800041c : * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer * @param SPIx SPI Instance * @retval None */ __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx) { 800041c: b480 push {r7} 800041e: b083 sub sp, #12 8000420: af00 add r7, sp, #0 8000422: 6078 str r0, [r7, #4] SET_BIT(SPIx->CR1, SPI_CR1_CSTART); 8000424: 687b ldr r3, [r7, #4] 8000426: 681b ldr r3, [r3, #0] 8000428: f443 7200 orr.w r2, r3, #512 ; 0x200 800042c: 687b ldr r3, [r7, #4] 800042e: 601a str r2, [r3, #0] } 8000430: bf00 nop 8000432: 370c adds r7, #12 8000434: 46bd mov sp, r7 8000436: f85d 7b04 ldr.w r7, [sp], #4 800043a: 4770 bx lr 0800043c : * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx) { 800043c: b480 push {r7} 800043e: b083 sub sp, #12 8000440: af00 add r7, sp, #0 8000442: 6078 str r0, [r7, #4] return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL); 8000444: 687b ldr r3, [r7, #4] 8000446: 695b ldr r3, [r3, #20] 8000448: f003 0301 and.w r3, r3, #1 800044c: 2b01 cmp r3, #1 800044e: d101 bne.n 8000454 8000450: 2301 movs r3, #1 8000452: e000 b.n 8000456 8000454: 2300 movs r3, #0 } 8000456: 4618 mov r0, r3 8000458: 370c adds r7, #12 800045a: 46bd mov sp, r7 800045c: f85d 7b04 ldr.w r7, [sp], #4 8000460: 4770 bx lr 08000462 : * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx) { 8000462: b480 push {r7} 8000464: b083 sub sp, #12 8000466: af00 add r7, sp, #0 8000468: 6078 str r0, [r7, #4] return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL); 800046a: 687b ldr r3, [r7, #4] 800046c: 695b ldr r3, [r3, #20] 800046e: f003 0308 and.w r3, r3, #8 8000472: 2b08 cmp r3, #8 8000474: d101 bne.n 800047a 8000476: 2301 movs r3, #1 8000478: e000 b.n 800047c 800047a: 2300 movs r3, #0 } 800047c: 4618 mov r0, r3 800047e: 370c adds r7, #12 8000480: 46bd mov sp, r7 8000482: f85d 7b04 ldr.w r7, [sp], #4 8000486: 4770 bx lr 08000488 : * @rmtoll RXDR . LL_SPI_ReceiveData8 * @param SPIx SPI Instance * @retval 0..0xFF */ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) { 8000488: b480 push {r7} 800048a: b083 sub sp, #12 800048c: af00 add r7, sp, #0 800048e: 6078 str r0, [r7, #4] return (*((__IO uint8_t *)&SPIx->RXDR)); 8000490: 687b ldr r3, [r7, #4] 8000492: 3330 adds r3, #48 ; 0x30 8000494: 781b ldrb r3, [r3, #0] 8000496: b2db uxtb r3, r3 } 8000498: 4618 mov r0, r3 800049a: 370c adds r7, #12 800049c: 46bd mov sp, r7 800049e: f85d 7b04 ldr.w r7, [sp], #4 80004a2: 4770 bx lr 080004a4 : * @param SPIx SPI Instance * @param TxData 0..0xFF * @retval None */ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) { 80004a4: b480 push {r7} 80004a6: b083 sub sp, #12 80004a8: af00 add r7, sp, #0 80004aa: 6078 str r0, [r7, #4] 80004ac: 460b mov r3, r1 80004ae: 70fb strb r3, [r7, #3] *((__IO uint8_t *)&SPIx->TXDR) = TxData; 80004b0: 687b ldr r3, [r7, #4] 80004b2: 3320 adds r3, #32 80004b4: 78fa ldrb r2, [r7, #3] 80004b6: 701a strb r2, [r3, #0] } 80004b8: bf00 nop 80004ba: 370c adds r7, #12 80004bc: 46bd mov sp, r7 80004be: f85d 7b04 ldr.w r7, [sp], #4 80004c2: 4770 bx lr 080004c4 : * @param SPIx SPI Instance * @param TxData 0..0xFFFF * @retval None */ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) { 80004c4: b480 push {r7} 80004c6: b085 sub sp, #20 80004c8: af00 add r7, sp, #0 80004ca: 6078 str r0, [r7, #4] 80004cc: 460b mov r3, r1 80004ce: 807b strh r3, [r7, #2] #if defined (__GNUC__) __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR); 80004d0: 687b ldr r3, [r7, #4] 80004d2: 3320 adds r3, #32 80004d4: 60fb str r3, [r7, #12] *spitxdr = TxData; 80004d6: 68fb ldr r3, [r7, #12] 80004d8: 887a ldrh r2, [r7, #2] 80004da: 801a strh r2, [r3, #0] #else SPIx->TXDR = TxData; #endif /* __GNUC__ */ } 80004dc: bf00 nop 80004de: 3714 adds r7, #20 80004e0: 46bd mov sp, r7 80004e2: f85d 7b04 ldr.w r7, [sp], #4 80004e6: 4770 bx lr 080004e8 : * @param SPIx SPI Instance * @param TxData 0..0xFFFFFFFF * @retval None */ __STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) { 80004e8: b480 push {r7} 80004ea: b083 sub sp, #12 80004ec: af00 add r7, sp, #0 80004ee: 6078 str r0, [r7, #4] 80004f0: 6039 str r1, [r7, #0] *((__IO uint32_t *)&SPIx->TXDR) = TxData; 80004f2: 687b ldr r3, [r7, #4] 80004f4: 683a ldr r2, [r7, #0] 80004f6: 621a str r2, [r3, #32] } 80004f8: bf00 nop 80004fa: 370c adds r7, #12 80004fc: 46bd mov sp, r7 80004fe: f85d 7b04 ldr.w r7, [sp], #4 8000502: 4770 bx lr 08000504 : #define CC1200_READ_BIT 0b10000000 #define CC1200_BURST_BIT 0b01000000 void SPI1_TransmitBytes(uint8_t *p_buf, uint8_t len) { 8000504: b580 push {r7, lr} 8000506: b082 sub sp, #8 8000508: af00 add r7, sp, #0 800050a: 6078 str r0, [r7, #4] 800050c: 460b mov r3, r1 800050e: 70fb strb r3, [r7, #3] LL_SPI_SetTransferSize(SPI1, len); 8000510: 78fb ldrb r3, [r7, #3] 8000512: 4619 mov r1, r3 8000514: 481f ldr r0, [pc, #124] ; (8000594 ) 8000516: f7ff ff6b bl 80003f0 LL_SPI_Enable(SPI1); 800051a: 481e ldr r0, [pc, #120] ; (8000594 ) 800051c: f7ff ff48 bl 80003b0 LL_SPI_StartMasterTransfer(SPI1); 8000520: 481c ldr r0, [pc, #112] ; (8000594 ) 8000522: f7ff ff7b bl 800041c switch(len) 8000526: 78fb ldrb r3, [r7, #3] 8000528: 2b03 cmp r3, #3 800052a: d014 beq.n 8000556 800052c: 2b03 cmp r3, #3 800052e: dc19 bgt.n 8000564 8000530: 2b01 cmp r3, #1 8000532: d002 beq.n 800053a 8000534: 2b02 cmp r3, #2 8000536: d007 beq.n 8000548 8000538: e014 b.n 8000564 { case 1: LL_SPI_TransmitData8(SPI1, *p_buf); 800053a: 687b ldr r3, [r7, #4] 800053c: 781b ldrb r3, [r3, #0] 800053e: 4619 mov r1, r3 8000540: 4814 ldr r0, [pc, #80] ; (8000594 ) 8000542: f7ff ffaf bl 80004a4 break; 8000546: e013 b.n 8000570 case 2: LL_SPI_TransmitData16(SPI1, *(uint16_t *)p_buf); 8000548: 687b ldr r3, [r7, #4] 800054a: 881b ldrh r3, [r3, #0] 800054c: 4619 mov r1, r3 800054e: 4811 ldr r0, [pc, #68] ; (8000594 ) 8000550: f7ff ffb8 bl 80004c4 break; 8000554: e00c b.n 8000570 case 3: LL_SPI_TransmitData32(SPI1, *(uint32_t *)p_buf); 8000556: 687b ldr r3, [r7, #4] 8000558: 681b ldr r3, [r3, #0] 800055a: 4619 mov r1, r3 800055c: 480d ldr r0, [pc, #52] ; (8000594 ) 800055e: f7ff ffc3 bl 80004e8 break; 8000562: e005 b.n 8000570 default: assert(0); 8000564: 4b0c ldr r3, [pc, #48] ; (8000598 ) 8000566: 4a0d ldr r2, [pc, #52] ; (800059c ) 8000568: 212f movs r1, #47 ; 0x2f 800056a: 480d ldr r0, [pc, #52] ; (80005a0 ) 800056c: f009 f9b6 bl 80098dc <__assert_func> } // Wait until the transmission is complete while( LL_SPI_IsActiveFlag_EOT(SPI1) == 0); 8000570: bf00 nop 8000572: 4808 ldr r0, [pc, #32] ; (8000594 ) 8000574: f7ff ff75 bl 8000462 8000578: 4603 mov r3, r0 800057a: 2b00 cmp r3, #0 800057c: d0f9 beq.n 8000572 SPI1->IFCR = UINT32_MAX; 800057e: 4b05 ldr r3, [pc, #20] ; (8000594 ) 8000580: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8000584: 619a str r2, [r3, #24] LL_SPI_Disable(SPI1); 8000586: 4803 ldr r0, [pc, #12] ; (8000594 ) 8000588: f7ff ff22 bl 80003d0 } 800058c: bf00 nop 800058e: 3708 adds r7, #8 8000590: 46bd mov sp, r7 8000592: bd80 pop {r7, pc} 8000594: 40013000 .word 0x40013000 8000598: 0800a8cc .word 0x0800a8cc 800059c: 0800a930 .word 0x0800a930 80005a0: 0800a8d0 .word 0x0800a8d0 080005a4 : uint8_t SPI1_ReceiveByte(void) { 80005a4: b580 push {r7, lr} 80005a6: b082 sub sp, #8 80005a8: af00 add r7, sp, #0 uint8_t rxByte; LL_SPI_SetTransferSize(SPI1, 1); 80005aa: 2101 movs r1, #1 80005ac: 4815 ldr r0, [pc, #84] ; (8000604 ) 80005ae: f7ff ff1f bl 80003f0 LL_SPI_Enable(SPI1); 80005b2: 4814 ldr r0, [pc, #80] ; (8000604 ) 80005b4: f7ff fefc bl 80003b0 LL_SPI_StartMasterTransfer(SPI1); 80005b8: 4812 ldr r0, [pc, #72] ; (8000604 ) 80005ba: f7ff ff2f bl 800041c LL_SPI_TransmitData8(SPI1, 0); 80005be: 2100 movs r1, #0 80005c0: 4810 ldr r0, [pc, #64] ; (8000604 ) 80005c2: f7ff ff6f bl 80004a4 while (LL_SPI_IsActiveFlag_RXP(SPI1) == 0); 80005c6: bf00 nop 80005c8: 480e ldr r0, [pc, #56] ; (8000604 ) 80005ca: f7ff ff37 bl 800043c 80005ce: 4603 mov r3, r0 80005d0: 2b00 cmp r3, #0 80005d2: d0f9 beq.n 80005c8 rxByte = LL_SPI_ReceiveData8(SPI1); 80005d4: 480b ldr r0, [pc, #44] ; (8000604 ) 80005d6: f7ff ff57 bl 8000488 80005da: 4603 mov r3, r0 80005dc: 71fb strb r3, [r7, #7] // Wait until the transmission is complete while( LL_SPI_IsActiveFlag_EOT(SPI1) == 0); 80005de: bf00 nop 80005e0: 4808 ldr r0, [pc, #32] ; (8000604 ) 80005e2: f7ff ff3e bl 8000462 80005e6: 4603 mov r3, r0 80005e8: 2b00 cmp r3, #0 80005ea: d0f9 beq.n 80005e0 SPI1->IFCR = UINT32_MAX; 80005ec: 4b05 ldr r3, [pc, #20] ; (8000604 ) 80005ee: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80005f2: 619a str r2, [r3, #24] LL_SPI_Disable(SPI1); 80005f4: 4803 ldr r0, [pc, #12] ; (8000604 ) 80005f6: f7ff feeb bl 80003d0 return rxByte; 80005fa: 79fb ldrb r3, [r7, #7] } 80005fc: 4618 mov r0, r3 80005fe: 3708 adds r7, #8 8000600: 46bd mov sp, r7 8000602: bd80 pop {r7, pc} 8000604: 40013000 .word 0x40013000 08000608 : uint8_t SPI1_TransmitReceive(uint8_t *p_buf, uint8_t len) { 8000608: b580 push {r7, lr} 800060a: b082 sub sp, #8 800060c: af00 add r7, sp, #0 800060e: 6078 str r0, [r7, #4] 8000610: 460b mov r3, r1 8000612: 70fb strb r3, [r7, #3] SPI1_TransmitBytes(p_buf, len); 8000614: 78fb ldrb r3, [r7, #3] 8000616: 4619 mov r1, r3 8000618: 6878 ldr r0, [r7, #4] 800061a: f7ff ff73 bl 8000504 return SPI1_ReceiveByte(); 800061e: f7ff ffc1 bl 80005a4 8000622: 4603 mov r3, r0 } 8000624: 4618 mov r0, r3 8000626: 3708 adds r7, #8 8000628: 46bd mov sp, r7 800062a: bd80 pop {r7, pc} 0800062c : // TODO: Fix to use HAL. static void cc1200_spi_write_byte(uint16_t addr, uint8_t data) { 800062c: b580 push {r7, lr} 800062e: b084 sub sp, #16 8000630: af00 add r7, sp, #0 8000632: 4603 mov r3, r0 8000634: 460a mov r2, r1 8000636: 80fb strh r3, [r7, #6] 8000638: 4613 mov r3, r2 800063a: 717b strb r3, [r7, #5] // set the data field HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 0); 800063c: 2200 movs r2, #0 800063e: 2140 movs r1, #64 ; 0x40 8000640: 4815 ldr r0, [pc, #84] ; (8000698 ) 8000642: f001 faf1 bl 8001c28 if ((addr & 0xFF00) != 0) // send data with extended address in command field 8000646: 88fb ldrh r3, [r7, #6] 8000648: f403 437f and.w r3, r3, #65280 ; 0xff00 800064c: 2b00 cmp r3, #0 800064e: d00f beq.n 8000670 { txBuf[0] = ((uint8_t *)&addr)[1]; 8000650: 79fb ldrb r3, [r7, #7] 8000652: 733b strb r3, [r7, #12] txBuf[1] = ((uint8_t *)&addr)[0]; 8000654: 1dbb adds r3, r7, #6 8000656: 781b ldrb r3, [r3, #0] 8000658: 737b strb r3, [r7, #13] txBuf[0] |= CC1200_WRITE_BIT; 800065a: 7b3b ldrb r3, [r7, #12] 800065c: 733b strb r3, [r7, #12] txBuf[2] = data; 800065e: 797b ldrb r3, [r7, #5] 8000660: 73bb strb r3, [r7, #14] SPI1_TransmitBytes(txBuf, 3); 8000662: f107 030c add.w r3, r7, #12 8000666: 2103 movs r1, #3 8000668: 4618 mov r0, r3 800066a: f7ff ff4b bl 8000504 800066e: e00a b.n 8000686 } else { // correctly configure the addr field. txBuf[0] = (uint8_t)addr | CC1200_WRITE_BIT; 8000670: 88fb ldrh r3, [r7, #6] 8000672: b2db uxtb r3, r3 8000674: 733b strb r3, [r7, #12] txBuf[1] = data; 8000676: 797b ldrb r3, [r7, #5] 8000678: 737b strb r3, [r7, #13] SPI1_TransmitBytes(txBuf, 2); 800067a: f107 030c add.w r3, r7, #12 800067e: 2102 movs r1, #2 8000680: 4618 mov r0, r3 8000682: f7ff ff3f bl 8000504 } HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 1); 8000686: 2201 movs r2, #1 8000688: 2140 movs r1, #64 ; 0x40 800068a: 4803 ldr r0, [pc, #12] ; (8000698 ) 800068c: f001 facc bl 8001c28 } 8000690: bf00 nop 8000692: 3710 adds r7, #16 8000694: 46bd mov sp, r7 8000696: bd80 pop {r7, pc} 8000698: 58020800 .word 0x58020800 0800069c : // ESP_ERROR_CHECK(ret); //} // TODO: Fix to use HAL. static void cc1200_spi_read_byte(uint16_t addr, uint8_t* data) { 800069c: b580 push {r7, lr} 800069e: b084 sub sp, #16 80006a0: af00 add r7, sp, #0 80006a2: 4603 mov r3, r0 80006a4: 6039 str r1, [r7, #0] 80006a6: 80fb strh r3, [r7, #6] uint8_t rxBuf[3]; uint8_t txBuf[3]; // correctly configure the addr field. txBuf[0] = (uint8_t)addr | CC1200_READ_BIT; 80006a8: 88fb ldrh r3, [r7, #6] 80006aa: b2db uxtb r3, r3 80006ac: f063 037f orn r3, r3, #127 ; 0x7f 80006b0: b2db uxtb r3, r3 80006b2: 723b strb r3, [r7, #8] HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 0); 80006b4: 2200 movs r2, #0 80006b6: 2140 movs r1, #64 ; 0x40 80006b8: 4817 ldr r0, [pc, #92] ; (8000718 ) 80006ba: f001 fab5 bl 8001c28 if ((addr & 0xFF00) != 0) // read data with extended address in command field 80006be: 88fb ldrh r3, [r7, #6] 80006c0: f403 437f and.w r3, r3, #65280 ; 0xff00 80006c4: 2b00 cmp r3, #0 80006c6: d014 beq.n 80006f2 { txBuf[0] = ((uint8_t *)&addr)[1]; 80006c8: 79fb ldrb r3, [r7, #7] 80006ca: 723b strb r3, [r7, #8] txBuf[1] = ((uint8_t *)&addr)[0]; 80006cc: 1dbb adds r3, r7, #6 80006ce: 781b ldrb r3, [r3, #0] 80006d0: 727b strb r3, [r7, #9] txBuf[0] |= CC1200_READ_BIT; 80006d2: 7a3b ldrb r3, [r7, #8] 80006d4: f063 037f orn r3, r3, #127 ; 0x7f 80006d8: b2db uxtb r3, r3 80006da: 723b strb r3, [r7, #8] *data = SPI1_TransmitReceive(txBuf, 2); 80006dc: f107 0308 add.w r3, r7, #8 80006e0: 2102 movs r1, #2 80006e2: 4618 mov r0, r3 80006e4: f7ff ff90 bl 8000608 80006e8: 4603 mov r3, r0 80006ea: 461a mov r2, r3 80006ec: 683b ldr r3, [r7, #0] 80006ee: 701a strb r2, [r3, #0] 80006f0: e009 b.n 8000706 } else { *data = SPI1_TransmitReceive(txBuf, 1); 80006f2: f107 0308 add.w r3, r7, #8 80006f6: 2101 movs r1, #1 80006f8: 4618 mov r0, r3 80006fa: f7ff ff85 bl 8000608 80006fe: 4603 mov r3, r0 8000700: 461a mov r2, r3 8000702: 683b ldr r3, [r7, #0] 8000704: 701a strb r2, [r3, #0] } HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 1); 8000706: 2201 movs r2, #1 8000708: 2140 movs r1, #64 ; 0x40 800070a: 4803 ldr r0, [pc, #12] ; (8000718 ) 800070c: f001 fa8c bl 8001c28 } 8000710: bf00 nop 8000712: 3710 adds r7, #16 8000714: 46bd mov sp, r7 8000716: bd80 pop {r7, pc} 8000718: 58020800 .word 0x58020800 0800071c : // ESP_ERROR_CHECK(ret); //} // TODO: Fix to use HAL. rf_status_t cc1200_spi_strobe(uint8_t cmd) { 800071c: b580 push {r7, lr} 800071e: b084 sub sp, #16 8000720: af00 add r7, sp, #0 8000722: 4603 mov r3, r0 8000724: 71fb strb r3, [r7, #7] uint8_t txBuf[2]; txBuf[0] = cmd; 8000726: 79fb ldrb r3, [r7, #7] 8000728: 733b strb r3, [r7, #12] HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 0); 800072a: 2200 movs r2, #0 800072c: 2140 movs r1, #64 ; 0x40 800072e: 481c ldr r0, [pc, #112] ; (80007a0 ) 8000730: f001 fa7a bl 8001c28 uint8_t rxByte; LL_SPI_SetTransferSize(SPI1, 1); 8000734: 2101 movs r1, #1 8000736: 481b ldr r0, [pc, #108] ; (80007a4 ) 8000738: f7ff fe5a bl 80003f0 LL_SPI_Enable(SPI1); 800073c: 4819 ldr r0, [pc, #100] ; (80007a4 ) 800073e: f7ff fe37 bl 80003b0 LL_SPI_StartMasterTransfer(SPI1); 8000742: 4818 ldr r0, [pc, #96] ; (80007a4 ) 8000744: f7ff fe6a bl 800041c LL_SPI_TransmitData8(SPI1, cmd); 8000748: 79fb ldrb r3, [r7, #7] 800074a: 4619 mov r1, r3 800074c: 4815 ldr r0, [pc, #84] ; (80007a4 ) 800074e: f7ff fea9 bl 80004a4 while (LL_SPI_IsActiveFlag_RXP(SPI1) == 0); 8000752: bf00 nop 8000754: 4813 ldr r0, [pc, #76] ; (80007a4 ) 8000756: f7ff fe71 bl 800043c 800075a: 4603 mov r3, r0 800075c: 2b00 cmp r3, #0 800075e: d0f9 beq.n 8000754 rxByte = LL_SPI_ReceiveData8(SPI1); 8000760: 4810 ldr r0, [pc, #64] ; (80007a4 ) 8000762: f7ff fe91 bl 8000488 8000766: 4603 mov r3, r0 8000768: 73fb strb r3, [r7, #15] // Wait until the transmission is complete while( LL_SPI_IsActiveFlag_EOT(SPI1) == 0); 800076a: bf00 nop 800076c: 480d ldr r0, [pc, #52] ; (80007a4 ) 800076e: f7ff fe78 bl 8000462 8000772: 4603 mov r3, r0 8000774: 2b00 cmp r3, #0 8000776: d0f9 beq.n 800076c SPI1->IFCR = UINT32_MAX; 8000778: 4b0a ldr r3, [pc, #40] ; (80007a4 ) 800077a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 800077e: 619a str r2, [r3, #24] LL_SPI_Disable(SPI1); 8000780: 4808 ldr r0, [pc, #32] ; (80007a4 ) 8000782: f7ff fe25 bl 80003d0 HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 1); 8000786: 2201 movs r2, #1 8000788: 2140 movs r1, #64 ; 0x40 800078a: 4805 ldr r0, [pc, #20] ; (80007a0 ) 800078c: f001 fa4c bl 8001c28 return rxByte & 0xF0; 8000790: 7bfb ldrb r3, [r7, #15] 8000792: f023 030f bic.w r3, r3, #15 8000796: b2db uxtb r3, r3 } 8000798: 4618 mov r0, r3 800079a: 3710 adds r7, #16 800079c: 46bd mov sp, r7 800079e: bd80 pop {r7, pc} 80007a0: 58020800 .word 0x58020800 80007a4: 40013000 .word 0x40013000 080007a8 : cc1200_spi_read_byte(CC120X_RSSI1, &data); return data; } uint8_t cc1200_radio_read_CFM(void) { 80007a8: b580 push {r7, lr} 80007aa: b082 sub sp, #8 80007ac: af00 add r7, sp, #0 uint8_t data = 0; 80007ae: 2300 movs r3, #0 80007b0: 71fb strb r3, [r7, #7] cc1200_spi_read_byte(CC120X_CFM_RX_DATA_OUT, &data); 80007b2: 1dfb adds r3, r7, #7 80007b4: 4619 mov r1, r3 80007b6: f642 707d movw r0, #12157 ; 0x2f7d 80007ba: f7ff ff6f bl 800069c return data; 80007be: 79fb ldrb r3, [r7, #7] } 80007c0: 4618 mov r0, r3 80007c2: 3708 adds r7, #8 80007c4: 46bd mov sp, r7 80007c6: bd80 pop {r7, pc} 080007c8 : { cc1200_spi_write_byte(CC120X_CFM_TX_DATA_IN, data); } rf_status_t cc1200_radio_reset(void) { 80007c8: b580 push {r7, lr} 80007ca: b082 sub sp, #8 80007cc: af00 add r7, sp, #0 rf_status_t status; uint8_t retry_count = 0; 80007ce: 2300 movs r3, #0 80007d0: 71bb strb r3, [r7, #6] cc1200_spi_strobe(CC120X_SRES); // soft reset the chip 80007d2: 2030 movs r0, #48 ; 0x30 80007d4: f7ff ffa2 bl 800071c status = cc1200_spi_strobe(CC120X_SNOP); // get chip status 80007d8: 203d movs r0, #61 ; 0x3d 80007da: f7ff ff9f bl 800071c 80007de: 4603 mov r3, r0 80007e0: 71fb strb r3, [r7, #7] HAL_Delay(20); 80007e2: 2014 movs r0, #20 80007e4: f000 ff44 bl 8001670 while((CC120X_RDYn_BIT & (status & 0x80))) // if chip isn't ready, wait 10ms 80007e8: e00d b.n 8000806 { HAL_Delay(10); 80007ea: 200a movs r0, #10 80007ec: f000 ff40 bl 8001670 if (retry_count > 3) 80007f0: 79bb ldrb r3, [r7, #6] 80007f2: 2b03 cmp r3, #3 80007f4: d80c bhi.n 8000810 { break; } status = cc1200_spi_strobe(CC120X_SNOP); 80007f6: 203d movs r0, #61 ; 0x3d 80007f8: f7ff ff90 bl 800071c 80007fc: 4603 mov r3, r0 80007fe: 71fb strb r3, [r7, #7] retry_count++; 8000800: 79bb ldrb r3, [r7, #6] 8000802: 3301 adds r3, #1 8000804: 71bb strb r3, [r7, #6] while((CC120X_RDYn_BIT & (status & 0x80))) // if chip isn't ready, wait 10ms 8000806: f997 3007 ldrsb.w r3, [r7, #7] 800080a: 2b00 cmp r3, #0 800080c: dbed blt.n 80007ea 800080e: e000 b.n 8000812 break; 8000810: bf00 nop } return status; 8000812: 79fb ldrb r3, [r7, #7] } 8000814: 4618 mov r0, r3 8000816: 3708 adds r7, #8 8000818: 46bd mov sp, r7 800081a: bd80 pop {r7, pc} 800081c: 0000 movs r0, r0 ... 08000820 : #define CC1200_LO_DIVIDER 24 // 136.7 - 160 MHz Band #define CC1200_XOSC 40000000 // 40MHz void cc1200_radio_frequency(uint32_t freq) { 8000820: b580 push {r7, lr} 8000822: b084 sub sp, #16 8000824: af00 add r7, sp, #0 8000826: 6078 str r0, [r7, #4] // f_VCO = FREQ / 2^16 * f_XOSX + FREQOFF / 2^18 * F_XOSC double temp_freq; // calculate FREQ0, FREQ, FREQ2 registers temp_freq = ((double) freq * 65536 * CC1200_LO_DIVIDER) / CC1200_XOSC; 8000828: 687b ldr r3, [r7, #4] 800082a: ee07 3a90 vmov s15, r3 800082e: eeb8 7b67 vcvt.f64.u32 d7, s15 8000832: ed9f 6b19 vldr d6, [pc, #100] ; 8000898 8000836: ee27 7b06 vmul.f64 d7, d7, d6 800083a: eeb3 6b08 vmov.f64 d6, #56 ; 0x41c00000 24.0 800083e: ee27 6b06 vmul.f64 d6, d7, d6 8000842: ed9f 5b17 vldr d5, [pc, #92] ; 80008a0 8000846: ee86 7b05 vdiv.f64 d7, d6, d5 800084a: ed87 7b02 vstr d7, [r7, #8] freq = (uint32_t)temp_freq; 800084e: ed97 7b02 vldr d7, [r7, #8] 8000852: eefc 7bc7 vcvt.u32.f64 s15, d7 8000856: ee17 3a90 vmov r3, s15 800085a: 607b str r3, [r7, #4] cc1200_spi_write_byte(CC120X_FREQ0, ((uint8_t *)&freq)[0]); 800085c: 1d3b adds r3, r7, #4 800085e: 781b ldrb r3, [r3, #0] 8000860: 4619 mov r1, r3 8000862: f642 700e movw r0, #12046 ; 0x2f0e 8000866: f7ff fee1 bl 800062c cc1200_spi_write_byte(CC120X_FREQ1, ((uint8_t *)&freq)[1]); 800086a: 1d3b adds r3, r7, #4 800086c: 3301 adds r3, #1 800086e: 781b ldrb r3, [r3, #0] 8000870: 4619 mov r1, r3 8000872: f642 700d movw r0, #12045 ; 0x2f0d 8000876: f7ff fed9 bl 800062c cc1200_spi_write_byte(CC120X_FREQ2, ((uint8_t *)&freq)[2]); 800087a: 1d3b adds r3, r7, #4 800087c: 3302 adds r3, #2 800087e: 781b ldrb r3, [r3, #0] 8000880: 4619 mov r1, r3 8000882: f642 700c movw r0, #12044 ; 0x2f0c 8000886: f7ff fed1 bl 800062c return ; 800088a: bf00 nop } 800088c: 3710 adds r7, #16 800088e: 46bd mov sp, r7 8000890: bd80 pop {r7, pc} 8000892: bf00 nop 8000894: f3af 8000 nop.w 8000898: 00000000 .word 0x00000000 800089c: 40f00000 .word 0x40f00000 80008a0: 00000000 .word 0x00000000 80008a4: 418312d0 .word 0x418312d0 080008a8 : // TODO: Create exception for failure condition while (cc1200_spi_strobe(CC120X_STX) != CC120X_STATE_TX); } void cc1200_radio_rx(void) { 80008a8: b580 push {r7, lr} 80008aa: af00 add r7, sp, #0 // TODO: Create exception for failure condition while (cc1200_spi_strobe(CC120X_SRX) != CC120X_STATE_RX); 80008ac: bf00 nop 80008ae: 2034 movs r0, #52 ; 0x34 80008b0: f7ff ff34 bl 800071c 80008b4: 4603 mov r3, r0 80008b6: 2b10 cmp r3, #16 80008b8: d1f9 bne.n 80008ae } 80008ba: bf00 nop 80008bc: bf00 nop 80008be: bd80 pop {r7, pc} 080008c0 : // TODO: Fix to use HAL. void cc1200_radio_init(const cc1200_reg_settings_t* rf_settings, uint8_t len) { 80008c0: b580 push {r7, lr} 80008c2: b084 sub sp, #16 80008c4: af00 add r7, sp, #0 80008c6: 6078 str r0, [r7, #4] 80008c8: 460b mov r3, r1 80008ca: 70fb strb r3, [r7, #3] //cc1200_gpio_init(); //cc1200_spi_init(); cc1200_radio_reset(); //gpio_set_level(CC1200_RESET, 1); 80008cc: f7ff ff7c bl 80007c8 uint8_t i; for (i=0;i { cc1200_spi_write_byte(rf_settings[i].addr, rf_settings[i].data); 80008d6: 7bfb ldrb r3, [r7, #15] 80008d8: 009b lsls r3, r3, #2 80008da: 687a ldr r2, [r7, #4] 80008dc: 4413 add r3, r2 80008de: 8818 ldrh r0, [r3, #0] 80008e0: 7bfb ldrb r3, [r7, #15] 80008e2: 009b lsls r3, r3, #2 80008e4: 687a ldr r2, [r7, #4] 80008e6: 4413 add r3, r2 80008e8: 789b ldrb r3, [r3, #2] 80008ea: 4619 mov r1, r3 80008ec: f7ff fe9e bl 800062c for (i=0;i } while(cc1200_spi_strobe(CC120X_SIDLE) != CC120X_STATE_IDLE); 80008fe: bf00 nop 8000900: 2036 movs r0, #54 ; 0x36 8000902: f7ff ff0b bl 800071c 8000906: 4603 mov r3, r0 8000908: 2b00 cmp r3, #0 800090a: d1f9 bne.n 8000900 } 800090c: bf00 nop 800090e: bf00 nop 8000910: 3710 adds r7, #16 8000912: 46bd mov sp, r7 8000914: bd80 pop {r7, pc} 08000916 : { 8000916: b480 push {r7} 8000918: b083 sub sp, #12 800091a: af00 add r7, sp, #0 800091c: 6078 str r0, [r7, #4] 800091e: 6039 str r1, [r7, #0] MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard); 8000920: 687b ldr r3, [r7, #4] 8000922: 68db ldr r3, [r3, #12] 8000924: f423 1260 bic.w r2, r3, #3670016 ; 0x380000 8000928: 683b ldr r3, [r7, #0] 800092a: 431a orrs r2, r3 800092c: 687b ldr r3, [r7, #4] 800092e: 60da str r2, [r3, #12] } 8000930: bf00 nop 8000932: 370c adds r7, #12 8000934: 46bd mov sp, r7 8000936: f85d 7b04 ldr.w r7, [sp], #4 800093a: 4770 bx lr 0800093c : { 800093c: b480 push {r7} 800093e: b083 sub sp, #12 8000940: af00 add r7, sp, #0 8000942: 6078 str r0, [r7, #4] SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM); 8000944: 687b ldr r3, [r7, #4] 8000946: 68db ldr r3, [r3, #12] 8000948: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000 800094c: 687b ldr r3, [r7, #4] 800094e: 60da str r2, [r3, #12] } 8000950: bf00 nop 8000952: 370c adds r7, #12 8000954: 46bd mov sp, r7 8000956: f85d 7b04 ldr.w r7, [sp], #4 800095a: 4770 bx lr 0800095c : * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) { 800095c: b480 push {r7} 800095e: b085 sub sp, #20 8000960: af00 add r7, sp, #0 8000962: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB4ENR, Periphs); 8000964: 4b0a ldr r3, [pc, #40] ; (8000990 ) 8000966: f8d3 20e0 ldr.w r2, [r3, #224] ; 0xe0 800096a: 4909 ldr r1, [pc, #36] ; (8000990 ) 800096c: 687b ldr r3, [r7, #4] 800096e: 4313 orrs r3, r2 8000970: f8c1 30e0 str.w r3, [r1, #224] ; 0xe0 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB4ENR, Periphs); 8000974: 4b06 ldr r3, [pc, #24] ; (8000990 ) 8000976: f8d3 20e0 ldr.w r2, [r3, #224] ; 0xe0 800097a: 687b ldr r3, [r7, #4] 800097c: 4013 ands r3, r2 800097e: 60fb str r3, [r7, #12] (void)tmpreg; 8000980: 68fb ldr r3, [r7, #12] } 8000982: bf00 nop 8000984: 3714 adds r7, #20 8000986: 46bd mov sp, r7 8000988: f85d 7b04 ldr.w r7, [sp], #4 800098c: 4770 bx lr 800098e: bf00 nop 8000990: 58024400 .word 0x58024400 08000994 : * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) { 8000994: b480 push {r7} 8000996: b085 sub sp, #20 8000998: af00 add r7, sp, #0 800099a: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, Periphs); 800099c: 4b0a ldr r3, [pc, #40] ; (80009c8 ) 800099e: f8d3 20f0 ldr.w r2, [r3, #240] ; 0xf0 80009a2: 4909 ldr r1, [pc, #36] ; (80009c8 ) 80009a4: 687b ldr r3, [r7, #4] 80009a6: 4313 orrs r3, r2 80009a8: f8c1 30f0 str.w r3, [r1, #240] ; 0xf0 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 80009ac: 4b06 ldr r3, [pc, #24] ; (80009c8 ) 80009ae: f8d3 20f0 ldr.w r2, [r3, #240] ; 0xf0 80009b2: 687b ldr r3, [r7, #4] 80009b4: 4013 ands r3, r2 80009b6: 60fb str r3, [r7, #12] (void)tmpreg; 80009b8: 68fb ldr r3, [r7, #12] } 80009ba: bf00 nop 80009bc: 3714 adds r7, #20 80009be: 46bd mov sp, r7 80009c0: f85d 7b04 ldr.w r7, [sp], #4 80009c4: 4770 bx lr 80009c6: bf00 nop 80009c8: 58024400 .word 0x58024400 080009cc : static uint8_t txBuffer0[2000]; static uint8_t txBuffer1[2000]; static uint32_t i=0, j=0; void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim) { 80009cc: b590 push {r4, r7, lr} 80009ce: b083 sub sp, #12 80009d0: af00 add r7, sp, #0 80009d2: 6078 str r0, [r7, #4] if (i == 2000 && j < 2000) 80009d4: 4b1f ldr r3, [pc, #124] ; (8000a54 ) 80009d6: 681b ldr r3, [r3, #0] 80009d8: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0 80009dc: d110 bne.n 8000a00 80009de: 4b1e ldr r3, [pc, #120] ; (8000a58 ) 80009e0: 681b ldr r3, [r3, #0] 80009e2: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0 80009e6: d20b bcs.n 8000a00 txBuffer1[j++] = cc1200_radio_read_CFM(); 80009e8: 4b1b ldr r3, [pc, #108] ; (8000a58 ) 80009ea: 681c ldr r4, [r3, #0] 80009ec: 1c63 adds r3, r4, #1 80009ee: 4a1a ldr r2, [pc, #104] ; (8000a58 ) 80009f0: 6013 str r3, [r2, #0] 80009f2: f7ff fed9 bl 80007a8 80009f6: 4603 mov r3, r0 80009f8: 461a mov r2, r3 80009fa: 4b18 ldr r3, [pc, #96] ; (8000a5c ) 80009fc: 551a strb r2, [r3, r4] 80009fe: e014 b.n 8000a2a else if (i < 2000) 8000a00: 4b14 ldr r3, [pc, #80] ; (8000a54 ) 8000a02: 681b ldr r3, [r3, #0] 8000a04: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0 8000a08: d20b bcs.n 8000a22 txBuffer0[i++] = cc1200_radio_read_CFM(); 8000a0a: 4b12 ldr r3, [pc, #72] ; (8000a54 ) 8000a0c: 681c ldr r4, [r3, #0] 8000a0e: 1c63 adds r3, r4, #1 8000a10: 4a10 ldr r2, [pc, #64] ; (8000a54 ) 8000a12: 6013 str r3, [r2, #0] 8000a14: f7ff fec8 bl 80007a8 8000a18: 4603 mov r3, r0 8000a1a: 461a mov r2, r3 8000a1c: 4b10 ldr r3, [pc, #64] ; (8000a60 ) 8000a1e: 551a strb r2, [r3, r4] 8000a20: e003 b.n 8000a2a else { HAL_GPIO_TogglePin(LED_YELLOW_GPIO_Port, LED_YELLOW_Pin); 8000a22: 2102 movs r1, #2 8000a24: 480f ldr r0, [pc, #60] ; (8000a64 ) 8000a26: f001 f918 bl 8001c5a //cc1200_radio_write_CFM(0); // Toggle LED as heart beat. static uint32_t toggleCount = 0; if (toggleCount++ == 40000) 8000a2a: 4b0f ldr r3, [pc, #60] ; (8000a68 ) 8000a2c: 681b ldr r3, [r3, #0] 8000a2e: 1c5a adds r2, r3, #1 8000a30: 490d ldr r1, [pc, #52] ; (8000a68 ) 8000a32: 600a str r2, [r1, #0] 8000a34: f649 4240 movw r2, #40000 ; 0x9c40 8000a38: 4293 cmp r3, r2 8000a3a: d106 bne.n 8000a4a { HAL_GPIO_TogglePin(LED_GREEN_GPIO_Port, LED_GREEN_Pin); 8000a3c: 2101 movs r1, #1 8000a3e: 480b ldr r0, [pc, #44] ; (8000a6c ) 8000a40: f001 f90b bl 8001c5a toggleCount = 0; 8000a44: 4b08 ldr r3, [pc, #32] ; (8000a68 ) 8000a46: 2200 movs r2, #0 8000a48: 601a str r2, [r3, #0] } } 8000a4a: bf00 nop 8000a4c: 370c adds r7, #12 8000a4e: 46bd mov sp, r7 8000a50: bd90 pop {r4, r7, pc} 8000a52: bf00 nop 8000a54: 240011a4 .word 0x240011a4 8000a58: 240011a8 .word 0x240011a8 8000a5c: 240009d4 .word 0x240009d4 8000a60: 24000204 .word 0x24000204 8000a64: 58021000 .word 0x58021000 8000a68: 240011ac .word 0x240011ac 8000a6c: 58020400 .word 0x58020400 08000a70
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000a70: b580 push {r7, lr} 8000a72: b084 sub sp, #16 8000a74: af00 add r7, sp, #0 \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 8000a76: 4b5d ldr r3, [pc, #372] ; (8000bec ) 8000a78: 695b ldr r3, [r3, #20] 8000a7a: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000a7e: 2b00 cmp r3, #0 8000a80: d11b bne.n 8000aba \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 8000a82: f3bf 8f4f dsb sy } 8000a86: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000a88: f3bf 8f6f isb sy } 8000a8c: bf00 nop __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 8000a8e: 4b57 ldr r3, [pc, #348] ; (8000bec ) 8000a90: 2200 movs r2, #0 8000a92: f8c3 2250 str.w r2, [r3, #592] ; 0x250 __ASM volatile ("dsb 0xF":::"memory"); 8000a96: f3bf 8f4f dsb sy } 8000a9a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000a9c: f3bf 8f6f isb sy } 8000aa0: bf00 nop __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 8000aa2: 4b52 ldr r3, [pc, #328] ; (8000bec ) 8000aa4: 695b ldr r3, [r3, #20] 8000aa6: 4a51 ldr r2, [pc, #324] ; (8000bec ) 8000aa8: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000aac: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000aae: f3bf 8f4f dsb sy } 8000ab2: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000ab4: f3bf 8f6f isb sy } 8000ab8: e000 b.n 8000abc if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 8000aba: bf00 nop #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000abc: 4b4b ldr r3, [pc, #300] ; (8000bec ) 8000abe: 695b ldr r3, [r3, #20] 8000ac0: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000ac4: 2b00 cmp r3, #0 8000ac6: d138 bne.n 8000b3a SCB->CSSELR = 0U; /* select Level 1 data cache */ 8000ac8: 4b48 ldr r3, [pc, #288] ; (8000bec ) 8000aca: 2200 movs r2, #0 8000acc: f8c3 2084 str.w r2, [r3, #132] ; 0x84 __ASM volatile ("dsb 0xF":::"memory"); 8000ad0: f3bf 8f4f dsb sy } 8000ad4: bf00 nop __DSB(); ccsidr = SCB->CCSIDR; 8000ad6: 4b45 ldr r3, [pc, #276] ; (8000bec ) 8000ad8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8000adc: 60bb str r3, [r7, #8] /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 8000ade: 68bb ldr r3, [r7, #8] 8000ae0: 0b5b lsrs r3, r3, #13 8000ae2: f3c3 030e ubfx r3, r3, #0, #15 8000ae6: 607b str r3, [r7, #4] do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 8000ae8: 68bb ldr r3, [r7, #8] 8000aea: 08db lsrs r3, r3, #3 8000aec: f3c3 0309 ubfx r3, r3, #0, #10 8000af0: 603b str r3, [r7, #0] do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 8000af2: 687b ldr r3, [r7, #4] 8000af4: 015a lsls r2, r3, #5 8000af6: f643 73e0 movw r3, #16352 ; 0x3fe0 8000afa: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 8000afc: 683a ldr r2, [r7, #0] 8000afe: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 8000b00: 493a ldr r1, [pc, #232] ; (8000bec ) 8000b02: 4313 orrs r3, r2 8000b04: f8c1 3260 str.w r3, [r1, #608] ; 0x260 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); 8000b08: 683b ldr r3, [r7, #0] 8000b0a: 1e5a subs r2, r3, #1 8000b0c: 603a str r2, [r7, #0] 8000b0e: 2b00 cmp r3, #0 8000b10: d1ef bne.n 8000af2 } while(sets-- != 0U); 8000b12: 687b ldr r3, [r7, #4] 8000b14: 1e5a subs r2, r3, #1 8000b16: 607a str r2, [r7, #4] 8000b18: 2b00 cmp r3, #0 8000b1a: d1e5 bne.n 8000ae8 __ASM volatile ("dsb 0xF":::"memory"); 8000b1c: f3bf 8f4f dsb sy } 8000b20: bf00 nop __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 8000b22: 4b32 ldr r3, [pc, #200] ; (8000bec ) 8000b24: 695b ldr r3, [r3, #20] 8000b26: 4a31 ldr r2, [pc, #196] ; (8000bec ) 8000b28: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000b2c: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000b2e: f3bf 8f4f dsb sy } 8000b32: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000b34: f3bf 8f6f isb sy } 8000b38: e000 b.n 8000b3c if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000b3a: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000b3c: f000 fd06 bl 800154c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000b40: f000 f866 bl 8000c10 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000b44: f000 f9bc bl 8000ec0 MX_SPI1_Init(); 8000b48: f000 f8d2 bl 8000cf0 MX_TIM3_Init(); 8000b4c: f000 f96a bl 8000e24 MX_USB_DEVICE_Init(); 8000b50: f008 f980 bl 8008e54 /* USER CODE BEGIN 2 */ HAL_StatusTypeDef errCode; // Manually reset the CC1200. HAL_GPIO_WritePin(CC1200_RESET_GPIO_Port, CC1200_RESET_Pin, 0); 8000b54: 2200 movs r2, #0 8000b56: f44f 5180 mov.w r1, #4096 ; 0x1000 8000b5a: 4825 ldr r0, [pc, #148] ; (8000bf0 ) 8000b5c: f001 f864 bl 8001c28 HAL_Delay(50); 8000b60: 2032 movs r0, #50 ; 0x32 8000b62: f000 fd85 bl 8001670 HAL_GPIO_WritePin(CC1200_RESET_GPIO_Port, CC1200_RESET_Pin, 1); 8000b66: 2201 movs r2, #1 8000b68: f44f 5180 mov.w r1, #4096 ; 0x1000 8000b6c: 4820 ldr r0, [pc, #128] ; (8000bf0 ) 8000b6e: f001 f85b bl 8001c28 HAL_Delay(50); 8000b72: 2032 movs r0, #50 ; 0x32 8000b74: f000 fd7c bl 8001670 // Setup up the 5million registers. cc1200_radio_init((cc1200_reg_settings_t *)AX25_SETTINGS, sizeof(AX25_SETTINGS)/sizeof(cc1200_reg_settings_t)); 8000b78: 2133 movs r1, #51 ; 0x33 8000b7a: 481e ldr r0, [pc, #120] ; (8000bf4 ) 8000b7c: f7ff fea0 bl 80008c0 // Set frequency cc1200_radio_frequency(144390000); 8000b80: 481d ldr r0, [pc, #116] ; (8000bf8 ) 8000b82: f7ff fe4d bl 8000820 // Enable TX/RX cc1200_radio_rx(); 8000b86: f7ff fe8f bl 80008a8 // Start Timer for SPI errCode = HAL_TIM_Base_Start_IT(&htim3); 8000b8a: 481c ldr r0, [pc, #112] ; (8000bfc ) 8000b8c: f004 fa5a bl 8005044 8000b90: 4603 mov r3, r0 8000b92: 73fb strb r3, [r7, #15] /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { if (i >= 2000) 8000b94: 4b1a ldr r3, [pc, #104] ; (8000c00 ) 8000b96: 681b ldr r3, [r3, #0] 8000b98: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0 8000b9c: d30f bcc.n 8000bbe { if(CDC_Transmit_HS(txBuffer0, 2000) != USBD_OK) 8000b9e: f44f 61fa mov.w r1, #2000 ; 0x7d0 8000ba2: 4818 ldr r0, [pc, #96] ; (8000c04 ) 8000ba4: f008 fa16 bl 8008fd4 8000ba8: 4603 mov r3, r0 8000baa: 2b00 cmp r3, #0 8000bac: d004 beq.n 8000bb8 { HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); 8000bae: f44f 4180 mov.w r1, #16384 ; 0x4000 8000bb2: 480f ldr r0, [pc, #60] ; (8000bf0 ) 8000bb4: f001 f851 bl 8001c5a } i = 0; 8000bb8: 4b11 ldr r3, [pc, #68] ; (8000c00 ) 8000bba: 2200 movs r2, #0 8000bbc: 601a str r2, [r3, #0] } if (j >= 2000) 8000bbe: 4b12 ldr r3, [pc, #72] ; (8000c08 ) 8000bc0: 681b ldr r3, [r3, #0] 8000bc2: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0 8000bc6: d3e5 bcc.n 8000b94 { if(CDC_Transmit_HS(txBuffer1, 2000) != USBD_OK) 8000bc8: f44f 61fa mov.w r1, #2000 ; 0x7d0 8000bcc: 480f ldr r0, [pc, #60] ; (8000c0c ) 8000bce: f008 fa01 bl 8008fd4 8000bd2: 4603 mov r3, r0 8000bd4: 2b00 cmp r3, #0 8000bd6: d004 beq.n 8000be2 { HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); 8000bd8: f44f 4180 mov.w r1, #16384 ; 0x4000 8000bdc: 4804 ldr r0, [pc, #16] ; (8000bf0 ) 8000bde: f001 f83c bl 8001c5a } j = 0; 8000be2: 4b09 ldr r3, [pc, #36] ; (8000c08 ) 8000be4: 2200 movs r2, #0 8000be6: 601a str r2, [r3, #0] if (i >= 2000) 8000be8: e7d4 b.n 8000b94 8000bea: bf00 nop 8000bec: e000ed00 .word 0xe000ed00 8000bf0: 58020400 .word 0x58020400 8000bf4: 0800a944 .word 0x0800a944 8000bf8: 089b3770 .word 0x089b3770 8000bfc: 240013e0 .word 0x240013e0 8000c00: 240011a4 .word 0x240011a4 8000c04: 24000204 .word 0x24000204 8000c08: 240011a8 .word 0x240011a8 8000c0c: 240009d4 .word 0x240009d4 08000c10 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000c10: b580 push {r7, lr} 8000c12: b09c sub sp, #112 ; 0x70 8000c14: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000c16: f107 0324 add.w r3, r7, #36 ; 0x24 8000c1a: 224c movs r2, #76 ; 0x4c 8000c1c: 2100 movs r1, #0 8000c1e: 4618 mov r0, r3 8000c20: f008 feb6 bl 8009990 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000c24: 1d3b adds r3, r7, #4 8000c26: 2220 movs r2, #32 8000c28: 2100 movs r1, #0 8000c2a: 4618 mov r0, r3 8000c2c: f008 feb0 bl 8009990 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 8000c30: 2002 movs r0, #2 8000c32: f002 f9fb bl 800302c /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); 8000c36: 2300 movs r3, #0 8000c38: 603b str r3, [r7, #0] 8000c3a: 4b2c ldr r3, [pc, #176] ; (8000cec ) 8000c3c: 699b ldr r3, [r3, #24] 8000c3e: 4a2b ldr r2, [pc, #172] ; (8000cec ) 8000c40: f423 4340 bic.w r3, r3, #49152 ; 0xc000 8000c44: 6193 str r3, [r2, #24] 8000c46: 4b29 ldr r3, [pc, #164] ; (8000cec ) 8000c48: 699b ldr r3, [r3, #24] 8000c4a: f403 4340 and.w r3, r3, #49152 ; 0xc000 8000c4e: 603b str r3, [r7, #0] 8000c50: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 8000c52: bf00 nop 8000c54: 4b25 ldr r3, [pc, #148] ; (8000cec ) 8000c56: 699b ldr r3, [r3, #24] 8000c58: f403 5300 and.w r3, r3, #8192 ; 0x2000 8000c5c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8000c60: d1f8 bne.n 8000c54 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE; 8000c62: 2321 movs r3, #33 ; 0x21 8000c64: 627b str r3, [r7, #36] ; 0x24 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; 8000c66: f44f 23a0 mov.w r3, #327680 ; 0x50000 8000c6a: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 8000c6c: 2301 movs r3, #1 8000c6e: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000c70: 2302 movs r3, #2 8000c72: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000c74: 2302 movs r3, #2 8000c76: 64fb str r3, [r7, #76] ; 0x4c RCC_OscInitStruct.PLL.PLLM = 4; 8000c78: 2304 movs r3, #4 8000c7a: 653b str r3, [r7, #80] ; 0x50 RCC_OscInitStruct.PLL.PLLN = 275; 8000c7c: f240 1313 movw r3, #275 ; 0x113 8000c80: 657b str r3, [r7, #84] ; 0x54 RCC_OscInitStruct.PLL.PLLP = 1; 8000c82: 2301 movs r3, #1 8000c84: 65bb str r3, [r7, #88] ; 0x58 RCC_OscInitStruct.PLL.PLLQ = 4; 8000c86: 2304 movs r3, #4 8000c88: 65fb str r3, [r7, #92] ; 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 8000c8a: 2302 movs r3, #2 8000c8c: 663b str r3, [r7, #96] ; 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; 8000c8e: 2304 movs r3, #4 8000c90: 667b str r3, [r7, #100] ; 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 8000c92: 2300 movs r3, #0 8000c94: 66bb str r3, [r7, #104] ; 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 8000c96: 2300 movs r3, #0 8000c98: 66fb str r3, [r7, #108] ; 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000c9a: f107 0324 add.w r3, r7, #36 ; 0x24 8000c9e: 4618 mov r0, r3 8000ca0: f002 fa0e bl 80030c0 8000ca4: 4603 mov r3, r0 8000ca6: 2b00 cmp r3, #0 8000ca8: d001 beq.n 8000cae { Error_Handler(); 8000caa: f000 fa61 bl 8001170 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000cae: 233f movs r3, #63 ; 0x3f 8000cb0: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000cb2: 2303 movs r3, #3 8000cb4: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 8000cb6: 2300 movs r3, #0 8000cb8: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 8000cba: 2308 movs r3, #8 8000cbc: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 8000cbe: 2340 movs r3, #64 ; 0x40 8000cc0: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 8000cc2: 2340 movs r3, #64 ; 0x40 8000cc4: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000cc6: f44f 6380 mov.w r3, #1024 ; 0x400 8000cca: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000ccc: 2340 movs r3, #64 ; 0x40 8000cce: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) 8000cd0: 1d3b adds r3, r7, #4 8000cd2: 2103 movs r1, #3 8000cd4: 4618 mov r0, r3 8000cd6: f002 fd9f bl 8003818 8000cda: 4603 mov r3, r0 8000cdc: 2b00 cmp r3, #0 8000cde: d001 beq.n 8000ce4 { Error_Handler(); 8000ce0: f000 fa46 bl 8001170 } } 8000ce4: bf00 nop 8000ce6: 3770 adds r7, #112 ; 0x70 8000ce8: 46bd mov sp, r7 8000cea: bd80 pop {r7, pc} 8000cec: 58024800 .word 0x58024800 08000cf0 : * @brief SPI1 Initialization Function * @param None * @retval None */ static void MX_SPI1_Init(void) { 8000cf0: b580 push {r7, lr} 8000cf2: b0be sub sp, #248 ; 0xf8 8000cf4: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_Init 0 */ /* USER CODE END SPI1_Init 0 */ LL_SPI_InitTypeDef SPI_InitStruct = {0}; 8000cf6: f107 03d0 add.w r3, r7, #208 ; 0xd0 8000cfa: 2228 movs r2, #40 ; 0x28 8000cfc: 2100 movs r1, #0 8000cfe: 4618 mov r0, r3 8000d00: f008 fe46 bl 8009990 LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000d04: f107 03b8 add.w r3, r7, #184 ; 0xb8 8000d08: 2200 movs r2, #0 8000d0a: 601a str r2, [r3, #0] 8000d0c: 605a str r2, [r3, #4] 8000d0e: 609a str r2, [r3, #8] 8000d10: 60da str r2, [r3, #12] 8000d12: 611a str r2, [r3, #16] 8000d14: 615a str r2, [r3, #20] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000d16: 1d3b adds r3, r7, #4 8000d18: 22b4 movs r2, #180 ; 0xb4 8000d1a: 2100 movs r1, #0 8000d1c: 4618 mov r0, r3 8000d1e: f008 fe37 bl 8009990 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI1; 8000d22: f44f 5380 mov.w r3, #4096 ; 0x1000 8000d26: 607b str r3, [r7, #4] PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; 8000d28: 2300 movs r3, #0 8000d2a: 65fb str r3, [r7, #92] ; 0x5c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000d2c: 1d3b adds r3, r7, #4 8000d2e: 4618 mov r0, r3 8000d30: f003 f8d2 bl 8003ed8 8000d34: 4603 mov r3, r0 8000d36: 2b00 cmp r3, #0 8000d38: d001 beq.n 8000d3e { Error_Handler(); 8000d3a: f000 fa19 bl 8001170 } /* Peripheral clock enable */ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1); 8000d3e: f44f 5080 mov.w r0, #4096 ; 0x1000 8000d42: f7ff fe27 bl 8000994 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA); 8000d46: 2001 movs r0, #1 8000d48: f7ff fe08 bl 800095c LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD); 8000d4c: 2008 movs r0, #8 8000d4e: f7ff fe05 bl 800095c /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO PD7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = LL_GPIO_PIN_5|LL_GPIO_PIN_6; 8000d52: 2360 movs r3, #96 ; 0x60 8000d54: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 8000d58: 2302 movs r3, #2 8000d5a: f8c7 30bc str.w r3, [r7, #188] ; 0xbc GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 8000d5e: 2303 movs r3, #3 8000d60: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 8000d64: 2300 movs r3, #0 8000d66: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 8000d6a: 2300 movs r3, #0 8000d6c: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 8000d70: 2305 movs r3, #5 8000d72: f8c7 30cc str.w r3, [r7, #204] ; 0xcc LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000d76: f107 03b8 add.w r3, r7, #184 ; 0xb8 8000d7a: 4619 mov r1, r3 8000d7c: 4826 ldr r0, [pc, #152] ; (8000e18 ) 8000d7e: f004 feff bl 8005b80 GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 8000d82: 2380 movs r3, #128 ; 0x80 8000d84: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 8000d88: 2302 movs r3, #2 8000d8a: f8c7 30bc str.w r3, [r7, #188] ; 0xbc GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 8000d8e: 2303 movs r3, #3 8000d90: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 8000d94: 2300 movs r3, #0 8000d96: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 8000d9a: 2300 movs r3, #0 8000d9c: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 8000da0: 2305 movs r3, #5 8000da2: f8c7 30cc str.w r3, [r7, #204] ; 0xcc LL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000da6: f107 03b8 add.w r3, r7, #184 ; 0xb8 8000daa: 4619 mov r1, r3 8000dac: 481b ldr r0, [pc, #108] ; (8000e1c ) 8000dae: f004 fee7 bl 8005b80 /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ /* SPI1 parameter configuration*/ SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; 8000db2: 2300 movs r3, #0 8000db4: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 8000db8: f44f 0380 mov.w r3, #4194304 ; 0x400000 8000dbc: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_8BIT; 8000dc0: 2307 movs r3, #7 8000dc2: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; 8000dc6: 2300 movs r3, #0 8000dc8: f8c7 30dc str.w r3, [r7, #220] ; 0xdc SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 8000dcc: 2300 movs r3, #0 8000dce: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 8000dd2: f04f 6380 mov.w r3, #67108864 ; 0x4000000 8000dd6: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV32; 8000dda: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 8000dde: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 8000de2: 2300 movs r3, #0 8000de4: f8c7 30ec str.w r3, [r7, #236] ; 0xec SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 8000de8: 2300 movs r3, #0 8000dea: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0 SPI_InitStruct.CRCPoly = 0x0; 8000dee: 2300 movs r3, #0 8000df0: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4 LL_SPI_Init(SPI1, &SPI_InitStruct); 8000df4: f107 03d0 add.w r3, r7, #208 ; 0xd0 8000df8: 4619 mov r1, r3 8000dfa: 4809 ldr r0, [pc, #36] ; (8000e20 ) 8000dfc: f004 ff70 bl 8005ce0 LL_SPI_SetStandard(SPI1, LL_SPI_PROTOCOL_MOTOROLA); 8000e00: 2100 movs r1, #0 8000e02: 4807 ldr r0, [pc, #28] ; (8000e20 ) 8000e04: f7ff fd87 bl 8000916 LL_SPI_EnableNSSPulseMgt(SPI1); 8000e08: 4805 ldr r0, [pc, #20] ; (8000e20 ) 8000e0a: f7ff fd97 bl 800093c /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } 8000e0e: bf00 nop 8000e10: 37f8 adds r7, #248 ; 0xf8 8000e12: 46bd mov sp, r7 8000e14: bd80 pop {r7, pc} 8000e16: bf00 nop 8000e18: 58020000 .word 0x58020000 8000e1c: 58020c00 .word 0x58020c00 8000e20: 40013000 .word 0x40013000 08000e24 : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 8000e24: b580 push {r7, lr} 8000e26: b088 sub sp, #32 8000e28: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8000e2a: f107 0310 add.w r3, r7, #16 8000e2e: 2200 movs r2, #0 8000e30: 601a str r2, [r3, #0] 8000e32: 605a str r2, [r3, #4] 8000e34: 609a str r2, [r3, #8] 8000e36: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000e38: 1d3b adds r3, r7, #4 8000e3a: 2200 movs r2, #0 8000e3c: 601a str r2, [r3, #0] 8000e3e: 605a str r2, [r3, #4] 8000e40: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8000e42: 4b1d ldr r3, [pc, #116] ; (8000eb8 ) 8000e44: 4a1d ldr r2, [pc, #116] ; (8000ebc ) 8000e46: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 8000e48: 4b1b ldr r3, [pc, #108] ; (8000eb8 ) 8000e4a: 2200 movs r2, #0 8000e4c: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8000e4e: 4b1a ldr r3, [pc, #104] ; (8000eb8 ) 8000e50: 2200 movs r2, #0 8000e52: 609a str r2, [r3, #8] htim3.Init.Period = 6875; 8000e54: 4b18 ldr r3, [pc, #96] ; (8000eb8 ) 8000e56: f641 22db movw r2, #6875 ; 0x1adb 8000e5a: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000e5c: 4b16 ldr r3, [pc, #88] ; (8000eb8 ) 8000e5e: 2200 movs r2, #0 8000e60: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8000e62: 4b15 ldr r3, [pc, #84] ; (8000eb8 ) 8000e64: 2280 movs r2, #128 ; 0x80 8000e66: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 8000e68: 4813 ldr r0, [pc, #76] ; (8000eb8 ) 8000e6a: f004 f893 bl 8004f94 8000e6e: 4603 mov r3, r0 8000e70: 2b00 cmp r3, #0 8000e72: d001 beq.n 8000e78 { Error_Handler(); 8000e74: f000 f97c bl 8001170 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000e78: f44f 5380 mov.w r3, #4096 ; 0x1000 8000e7c: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 8000e7e: f107 0310 add.w r3, r7, #16 8000e82: 4619 mov r1, r3 8000e84: 480c ldr r0, [pc, #48] ; (8000eb8 ) 8000e86: f004 fa83 bl 8005390 8000e8a: 4603 mov r3, r0 8000e8c: 2b00 cmp r3, #0 8000e8e: d001 beq.n 8000e94 { Error_Handler(); 8000e90: f000 f96e bl 8001170 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000e94: 2300 movs r3, #0 8000e96: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000e98: 2300 movs r3, #0 8000e9a: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8000e9c: 1d3b adds r3, r7, #4 8000e9e: 4619 mov r1, r3 8000ea0: 4805 ldr r0, [pc, #20] ; (8000eb8 ) 8000ea2: f004 fcd9 bl 8005858 8000ea6: 4603 mov r3, r0 8000ea8: 2b00 cmp r3, #0 8000eaa: d001 beq.n 8000eb0 { Error_Handler(); 8000eac: f000 f960 bl 8001170 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8000eb0: bf00 nop 8000eb2: 3720 adds r7, #32 8000eb4: 46bd mov sp, r7 8000eb6: bd80 pop {r7, pc} 8000eb8: 240013e0 .word 0x240013e0 8000ebc: 40000400 .word 0x40000400 08000ec0 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000ec0: b580 push {r7, lr} 8000ec2: b08c sub sp, #48 ; 0x30 8000ec4: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000ec6: f107 031c add.w r3, r7, #28 8000eca: 2200 movs r2, #0 8000ecc: 601a str r2, [r3, #0] 8000ece: 605a str r2, [r3, #4] 8000ed0: 609a str r2, [r3, #8] 8000ed2: 60da str r2, [r3, #12] 8000ed4: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8000ed6: 4b9f ldr r3, [pc, #636] ; (8001154 ) 8000ed8: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000edc: 4a9d ldr r2, [pc, #628] ; (8001154 ) 8000ede: f043 0304 orr.w r3, r3, #4 8000ee2: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000ee6: 4b9b ldr r3, [pc, #620] ; (8001154 ) 8000ee8: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000eec: f003 0304 and.w r3, r3, #4 8000ef0: 61bb str r3, [r7, #24] 8000ef2: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOH_CLK_ENABLE(); 8000ef4: 4b97 ldr r3, [pc, #604] ; (8001154 ) 8000ef6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000efa: 4a96 ldr r2, [pc, #600] ; (8001154 ) 8000efc: f043 0380 orr.w r3, r3, #128 ; 0x80 8000f00: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000f04: 4b93 ldr r3, [pc, #588] ; (8001154 ) 8000f06: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000f0a: f003 0380 and.w r3, r3, #128 ; 0x80 8000f0e: 617b str r3, [r7, #20] 8000f10: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000f12: 4b90 ldr r3, [pc, #576] ; (8001154 ) 8000f14: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000f18: 4a8e ldr r2, [pc, #568] ; (8001154 ) 8000f1a: f043 0301 orr.w r3, r3, #1 8000f1e: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000f22: 4b8c ldr r3, [pc, #560] ; (8001154 ) 8000f24: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000f28: f003 0301 and.w r3, r3, #1 8000f2c: 613b str r3, [r7, #16] 8000f2e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000f30: 4b88 ldr r3, [pc, #544] ; (8001154 ) 8000f32: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000f36: 4a87 ldr r2, [pc, #540] ; (8001154 ) 8000f38: f043 0302 orr.w r3, r3, #2 8000f3c: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000f40: 4b84 ldr r3, [pc, #528] ; (8001154 ) 8000f42: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000f46: f003 0302 and.w r3, r3, #2 8000f4a: 60fb str r3, [r7, #12] 8000f4c: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000f4e: 4b81 ldr r3, [pc, #516] ; (8001154 ) 8000f50: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000f54: 4a7f ldr r2, [pc, #508] ; (8001154 ) 8000f56: f043 0308 orr.w r3, r3, #8 8000f5a: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000f5e: 4b7d ldr r3, [pc, #500] ; (8001154 ) 8000f60: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000f64: f003 0308 and.w r3, r3, #8 8000f68: 60bb str r3, [r7, #8] 8000f6a: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000f6c: 4b79 ldr r3, [pc, #484] ; (8001154 ) 8000f6e: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000f72: 4a78 ldr r2, [pc, #480] ; (8001154 ) 8000f74: f043 0340 orr.w r3, r3, #64 ; 0x40 8000f78: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000f7c: 4b75 ldr r3, [pc, #468] ; (8001154 ) 8000f7e: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000f82: f003 0340 and.w r3, r3, #64 ; 0x40 8000f86: 607b str r3, [r7, #4] 8000f88: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOE_CLK_ENABLE(); 8000f8a: 4b72 ldr r3, [pc, #456] ; (8001154 ) 8000f8c: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000f90: 4a70 ldr r2, [pc, #448] ; (8001154 ) 8000f92: f043 0310 orr.w r3, r3, #16 8000f96: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000f9a: 4b6e ldr r3, [pc, #440] ; (8001154 ) 8000f9c: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000fa0: f003 0310 and.w r3, r3, #16 8000fa4: 603b str r3, [r7, #0] 8000fa6: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LED_GREEN_Pin|CC1200_RESET_Pin|LED_RED_Pin, GPIO_PIN_RESET); 8000fa8: 2200 movs r2, #0 8000faa: f245 0101 movw r1, #20481 ; 0x5001 8000fae: 486a ldr r0, [pc, #424] ; (8001158 ) 8000fb0: f000 fe3a bl 8001c28 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(CC1200_TCXO_ENABLE_GPIO_Port, CC1200_TCXO_ENABLE_Pin, GPIO_PIN_SET); 8000fb4: 2201 movs r2, #1 8000fb6: f44f 4100 mov.w r1, #32768 ; 0x8000 8000fba: 4867 ldr r0, [pc, #412] ; (8001158 ) 8000fbc: f000 fe34 bl 8001c28 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USB_FS_PWR_EN_GPIO_Port, USB_FS_PWR_EN_Pin, GPIO_PIN_RESET); 8000fc0: 2200 movs r2, #0 8000fc2: f44f 6180 mov.w r1, #1024 ; 0x400 8000fc6: 4865 ldr r0, [pc, #404] ; (800115c ) 8000fc8: f000 fe2e bl 8001c28 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, GPIO_PIN_SET); 8000fcc: 2201 movs r2, #1 8000fce: 2140 movs r1, #64 ; 0x40 8000fd0: 4863 ldr r0, [pc, #396] ; (8001160 ) 8000fd2: f000 fe29 bl 8001c28 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LED_YELLOW_GPIO_Port, LED_YELLOW_Pin, GPIO_PIN_RESET); 8000fd6: 2200 movs r2, #0 8000fd8: 2102 movs r1, #2 8000fda: 4862 ldr r0, [pc, #392] ; (8001164 ) 8000fdc: f000 fe24 bl 8001c28 /*Configure GPIO pin : B1_Pin */ GPIO_InitStruct.Pin = B1_Pin; 8000fe0: f44f 5300 mov.w r3, #8192 ; 0x2000 8000fe4: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000fe6: 2300 movs r3, #0 8000fe8: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000fea: 2300 movs r3, #0 8000fec: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); 8000fee: f107 031c add.w r3, r7, #28 8000ff2: 4619 mov r1, r3 8000ff4: 485a ldr r0, [pc, #360] ; (8001160 ) 8000ff6: f000 fc6f bl 80018d8 /*Configure GPIO pins : PC1 PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; 8000ffa: 2332 movs r3, #50 ; 0x32 8000ffc: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000ffe: 2302 movs r3, #2 8001000: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001002: 2300 movs r3, #0 8001004: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001006: 2303 movs r3, #3 8001008: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 800100a: 230b movs r3, #11 800100c: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800100e: f107 031c add.w r3, r7, #28 8001012: 4619 mov r1, r3 8001014: 4852 ldr r0, [pc, #328] ; (8001160 ) 8001016: f000 fc5f bl 80018d8 /*Configure GPIO pins : PA1 PA2 PA7 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; 800101a: 2386 movs r3, #134 ; 0x86 800101c: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800101e: 2302 movs r3, #2 8001020: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001022: 2300 movs r3, #0 8001024: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001026: 2303 movs r3, #3 8001028: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 800102a: 230b movs r3, #11 800102c: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800102e: f107 031c add.w r3, r7, #28 8001032: 4619 mov r1, r3 8001034: 484c ldr r0, [pc, #304] ; (8001168 ) 8001036: f000 fc4f bl 80018d8 /*Configure GPIO pins : LED_GREEN_Pin LED_RED_Pin */ GPIO_InitStruct.Pin = LED_GREEN_Pin|LED_RED_Pin; 800103a: f244 0301 movw r3, #16385 ; 0x4001 800103e: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001040: 2301 movs r3, #1 8001042: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001044: 2300 movs r3, #0 8001046: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001048: 2300 movs r3, #0 800104a: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800104c: f107 031c add.w r3, r7, #28 8001050: 4619 mov r1, r3 8001052: 4841 ldr r0, [pc, #260] ; (8001158 ) 8001054: f000 fc40 bl 80018d8 /*Configure GPIO pins : CC1200_RESET_Pin CC1200_TCXO_ENABLE_Pin */ GPIO_InitStruct.Pin = CC1200_RESET_Pin|CC1200_TCXO_ENABLE_Pin; 8001058: f44f 4310 mov.w r3, #36864 ; 0x9000 800105c: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800105e: 2301 movs r3, #1 8001060: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001062: 2300 movs r3, #0 8001064: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001066: 2303 movs r3, #3 8001068: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800106a: f107 031c add.w r3, r7, #28 800106e: 4619 mov r1, r3 8001070: 4839 ldr r0, [pc, #228] ; (8001158 ) 8001072: f000 fc31 bl 80018d8 /*Configure GPIO pin : PB13 */ GPIO_InitStruct.Pin = GPIO_PIN_13; 8001076: f44f 5300 mov.w r3, #8192 ; 0x2000 800107a: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800107c: 2302 movs r3, #2 800107e: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001080: 2300 movs r3, #0 8001082: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001084: 2303 movs r3, #3 8001086: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8001088: 230b movs r3, #11 800108a: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800108c: f107 031c add.w r3, r7, #28 8001090: 4619 mov r1, r3 8001092: 4831 ldr r0, [pc, #196] ; (8001158 ) 8001094: f000 fc20 bl 80018d8 /*Configure GPIO pins : STLK_VCP_RX_Pin STLK_VCP_TX_Pin */ GPIO_InitStruct.Pin = STLK_VCP_RX_Pin|STLK_VCP_TX_Pin; 8001098: f44f 7340 mov.w r3, #768 ; 0x300 800109c: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800109e: 2302 movs r3, #2 80010a0: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80010a2: 2300 movs r3, #0 80010a4: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80010a6: 2300 movs r3, #0 80010a8: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF7_USART3; 80010aa: 2307 movs r3, #7 80010ac: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80010ae: f107 031c add.w r3, r7, #28 80010b2: 4619 mov r1, r3 80010b4: 4829 ldr r0, [pc, #164] ; (800115c ) 80010b6: f000 fc0f bl 80018d8 /*Configure GPIO pin : USB_FS_PWR_EN_Pin */ GPIO_InitStruct.Pin = USB_FS_PWR_EN_Pin; 80010ba: f44f 6380 mov.w r3, #1024 ; 0x400 80010be: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80010c0: 2301 movs r3, #1 80010c2: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80010c4: 2300 movs r3, #0 80010c6: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80010c8: 2300 movs r3, #0 80010ca: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(USB_FS_PWR_EN_GPIO_Port, &GPIO_InitStruct); 80010cc: f107 031c add.w r3, r7, #28 80010d0: 4619 mov r1, r3 80010d2: 4822 ldr r0, [pc, #136] ; (800115c ) 80010d4: f000 fc00 bl 80018d8 /*Configure GPIO pin : USB_FS_OVCR_Pin */ GPIO_InitStruct.Pin = USB_FS_OVCR_Pin; 80010d8: 2380 movs r3, #128 ; 0x80 80010da: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 80010dc: f44f 1388 mov.w r3, #1114112 ; 0x110000 80010e0: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80010e2: 2300 movs r3, #0 80010e4: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(USB_FS_OVCR_GPIO_Port, &GPIO_InitStruct); 80010e6: f107 031c add.w r3, r7, #28 80010ea: 4619 mov r1, r3 80010ec: 481f ldr r0, [pc, #124] ; (800116c ) 80010ee: f000 fbf3 bl 80018d8 /*Configure GPIO pin : CC1200_CS_Pin */ GPIO_InitStruct.Pin = CC1200_CS_Pin; 80010f2: 2340 movs r3, #64 ; 0x40 80010f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80010f6: 2301 movs r3, #1 80010f8: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80010fa: 2300 movs r3, #0 80010fc: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80010fe: 2303 movs r3, #3 8001100: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(CC1200_CS_GPIO_Port, &GPIO_InitStruct); 8001102: f107 031c add.w r3, r7, #28 8001106: 4619 mov r1, r3 8001108: 4815 ldr r0, [pc, #84] ; (8001160 ) 800110a: f000 fbe5 bl 80018d8 /*Configure GPIO pins : PG11 PG13 */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13; 800110e: f44f 5320 mov.w r3, #10240 ; 0x2800 8001112: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001114: 2302 movs r3, #2 8001116: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001118: 2300 movs r3, #0 800111a: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800111c: 2303 movs r3, #3 800111e: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8001120: 230b movs r3, #11 8001122: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8001124: f107 031c add.w r3, r7, #28 8001128: 4619 mov r1, r3 800112a: 4810 ldr r0, [pc, #64] ; (800116c ) 800112c: f000 fbd4 bl 80018d8 /*Configure GPIO pin : LED_YELLOW_Pin */ GPIO_InitStruct.Pin = LED_YELLOW_Pin; 8001130: 2302 movs r3, #2 8001132: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001134: 2301 movs r3, #1 8001136: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001138: 2300 movs r3, #0 800113a: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800113c: 2300 movs r3, #0 800113e: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(LED_YELLOW_GPIO_Port, &GPIO_InitStruct); 8001140: f107 031c add.w r3, r7, #28 8001144: 4619 mov r1, r3 8001146: 4807 ldr r0, [pc, #28] ; (8001164 ) 8001148: f000 fbc6 bl 80018d8 } 800114c: bf00 nop 800114e: 3730 adds r7, #48 ; 0x30 8001150: 46bd mov sp, r7 8001152: bd80 pop {r7, pc} 8001154: 58024400 .word 0x58024400 8001158: 58020400 .word 0x58020400 800115c: 58020c00 .word 0x58020c00 8001160: 58020800 .word 0x58020800 8001164: 58021000 .word 0x58021000 8001168: 58020000 .word 0x58020000 800116c: 58021800 .word 0x58021800 08001170 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001170: b480 push {r7} 8001172: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8001174: b672 cpsid i } 8001176: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001178: e7fe b.n 8001178 ... 0800117c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800117c: b480 push {r7} 800117e: b083 sub sp, #12 8001180: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001182: 4b0a ldr r3, [pc, #40] ; (80011ac ) 8001184: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 8001188: 4a08 ldr r2, [pc, #32] ; (80011ac ) 800118a: f043 0302 orr.w r3, r3, #2 800118e: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 8001192: 4b06 ldr r3, [pc, #24] ; (80011ac ) 8001194: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 8001198: f003 0302 and.w r3, r3, #2 800119c: 607b str r3, [r7, #4] 800119e: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80011a0: bf00 nop 80011a2: 370c adds r7, #12 80011a4: 46bd mov sp, r7 80011a6: f85d 7b04 ldr.w r7, [sp], #4 80011aa: 4770 bx lr 80011ac: 58024400 .word 0x58024400 080011b0 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 80011b0: b580 push {r7, lr} 80011b2: b084 sub sp, #16 80011b4: af00 add r7, sp, #0 80011b6: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM3) 80011b8: 687b ldr r3, [r7, #4] 80011ba: 681b ldr r3, [r3, #0] 80011bc: 4a0e ldr r2, [pc, #56] ; (80011f8 ) 80011be: 4293 cmp r3, r2 80011c0: d116 bne.n 80011f0 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 80011c2: 4b0e ldr r3, [pc, #56] ; (80011fc ) 80011c4: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 80011c8: 4a0c ldr r2, [pc, #48] ; (80011fc ) 80011ca: f043 0302 orr.w r3, r3, #2 80011ce: f8c2 30e8 str.w r3, [r2, #232] ; 0xe8 80011d2: 4b0a ldr r3, [pc, #40] ; (80011fc ) 80011d4: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8 80011d8: f003 0302 and.w r3, r3, #2 80011dc: 60fb str r3, [r7, #12] 80011de: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 80011e0: 2200 movs r2, #0 80011e2: 2100 movs r1, #0 80011e4: 201d movs r0, #29 80011e6: f000 fb42 bl 800186e HAL_NVIC_EnableIRQ(TIM3_IRQn); 80011ea: 201d movs r0, #29 80011ec: f000 fb59 bl 80018a2 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 80011f0: bf00 nop 80011f2: 3710 adds r7, #16 80011f4: 46bd mov sp, r7 80011f6: bd80 pop {r7, pc} 80011f8: 40000400 .word 0x40000400 80011fc: 58024400 .word 0x58024400 08001200 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001200: b480 push {r7} 8001202: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8001204: e7fe b.n 8001204 08001206 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8001206: b480 push {r7} 8001208: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800120a: e7fe b.n 800120a 0800120c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 800120c: b480 push {r7} 800120e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001210: e7fe b.n 8001210 08001212 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8001212: b480 push {r7} 8001214: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8001216: e7fe b.n 8001216 08001218 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001218: b480 push {r7} 800121a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800121c: e7fe b.n 800121c 0800121e : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800121e: b480 push {r7} 8001220: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8001222: bf00 nop 8001224: 46bd mov sp, r7 8001226: f85d 7b04 ldr.w r7, [sp], #4 800122a: 4770 bx lr 0800122c : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800122c: b480 push {r7} 800122e: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8001230: bf00 nop 8001232: 46bd mov sp, r7 8001234: f85d 7b04 ldr.w r7, [sp], #4 8001238: 4770 bx lr 0800123a : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800123a: b480 push {r7} 800123c: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800123e: bf00 nop 8001240: 46bd mov sp, r7 8001242: f85d 7b04 ldr.w r7, [sp], #4 8001246: 4770 bx lr 08001248 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8001248: b580 push {r7, lr} 800124a: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800124c: f000 f9f0 bl 8001630 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8001250: bf00 nop 8001252: bd80 pop {r7, pc} 08001254 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 8001254: b580 push {r7, lr} 8001256: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 8001258: 4802 ldr r0, [pc, #8] ; (8001264 ) 800125a: f003 ff79 bl 8005150 /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 800125e: bf00 nop 8001260: bd80 pop {r7, pc} 8001262: bf00 nop 8001264: 240013e0 .word 0x240013e0 08001268 : /** * @brief This function handles USB On The Go HS global interrupt. */ void OTG_HS_IRQHandler(void) { 8001268: b580 push {r7, lr} 800126a: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_HS_IRQn 0 */ /* USER CODE END OTG_HS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_HS); 800126c: 4802 ldr r0, [pc, #8] ; (8001278 ) 800126e: f000 fe65 bl 8001f3c /* USER CODE BEGIN OTG_HS_IRQn 1 */ /* USER CODE END OTG_HS_IRQn 1 */ } 8001272: bf00 nop 8001274: bd80 pop {r7, pc} 8001276: bf00 nop 8001278: 24002900 .word 0x24002900 0800127c <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800127c: b480 push {r7} 800127e: af00 add r7, sp, #0 return 1; 8001280: 2301 movs r3, #1 } 8001282: 4618 mov r0, r3 8001284: 46bd mov sp, r7 8001286: f85d 7b04 ldr.w r7, [sp], #4 800128a: 4770 bx lr 0800128c <_kill>: int _kill(int pid, int sig) { 800128c: b580 push {r7, lr} 800128e: b082 sub sp, #8 8001290: af00 add r7, sp, #0 8001292: 6078 str r0, [r7, #4] 8001294: 6039 str r1, [r7, #0] errno = EINVAL; 8001296: f008 fb3f bl 8009918 <__errno> 800129a: 4603 mov r3, r0 800129c: 2216 movs r2, #22 800129e: 601a str r2, [r3, #0] return -1; 80012a0: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 80012a4: 4618 mov r0, r3 80012a6: 3708 adds r7, #8 80012a8: 46bd mov sp, r7 80012aa: bd80 pop {r7, pc} 080012ac <_exit>: void _exit (int status) { 80012ac: b580 push {r7, lr} 80012ae: b082 sub sp, #8 80012b0: af00 add r7, sp, #0 80012b2: 6078 str r0, [r7, #4] _kill(status, -1); 80012b4: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 80012b8: 6878 ldr r0, [r7, #4] 80012ba: f7ff ffe7 bl 800128c <_kill> while (1) {} /* Make sure we hang here */ 80012be: e7fe b.n 80012be <_exit+0x12> 080012c0 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 80012c0: b580 push {r7, lr} 80012c2: b086 sub sp, #24 80012c4: af00 add r7, sp, #0 80012c6: 60f8 str r0, [r7, #12] 80012c8: 60b9 str r1, [r7, #8] 80012ca: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80012cc: 2300 movs r3, #0 80012ce: 617b str r3, [r7, #20] 80012d0: e00a b.n 80012e8 <_read+0x28> { *ptr++ = __io_getchar(); 80012d2: f3af 8000 nop.w 80012d6: 4601 mov r1, r0 80012d8: 68bb ldr r3, [r7, #8] 80012da: 1c5a adds r2, r3, #1 80012dc: 60ba str r2, [r7, #8] 80012de: b2ca uxtb r2, r1 80012e0: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 80012e2: 697b ldr r3, [r7, #20] 80012e4: 3301 adds r3, #1 80012e6: 617b str r3, [r7, #20] 80012e8: 697a ldr r2, [r7, #20] 80012ea: 687b ldr r3, [r7, #4] 80012ec: 429a cmp r2, r3 80012ee: dbf0 blt.n 80012d2 <_read+0x12> } return len; 80012f0: 687b ldr r3, [r7, #4] } 80012f2: 4618 mov r0, r3 80012f4: 3718 adds r7, #24 80012f6: 46bd mov sp, r7 80012f8: bd80 pop {r7, pc} 080012fa <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 80012fa: b580 push {r7, lr} 80012fc: b086 sub sp, #24 80012fe: af00 add r7, sp, #0 8001300: 60f8 str r0, [r7, #12] 8001302: 60b9 str r1, [r7, #8] 8001304: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8001306: 2300 movs r3, #0 8001308: 617b str r3, [r7, #20] 800130a: e009 b.n 8001320 <_write+0x26> { __io_putchar(*ptr++); 800130c: 68bb ldr r3, [r7, #8] 800130e: 1c5a adds r2, r3, #1 8001310: 60ba str r2, [r7, #8] 8001312: 781b ldrb r3, [r3, #0] 8001314: 4618 mov r0, r3 8001316: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) 800131a: 697b ldr r3, [r7, #20] 800131c: 3301 adds r3, #1 800131e: 617b str r3, [r7, #20] 8001320: 697a ldr r2, [r7, #20] 8001322: 687b ldr r3, [r7, #4] 8001324: 429a cmp r2, r3 8001326: dbf1 blt.n 800130c <_write+0x12> } return len; 8001328: 687b ldr r3, [r7, #4] } 800132a: 4618 mov r0, r3 800132c: 3718 adds r7, #24 800132e: 46bd mov sp, r7 8001330: bd80 pop {r7, pc} 08001332 <_close>: int _close(int file) { 8001332: b480 push {r7} 8001334: b083 sub sp, #12 8001336: af00 add r7, sp, #0 8001338: 6078 str r0, [r7, #4] return -1; 800133a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 800133e: 4618 mov r0, r3 8001340: 370c adds r7, #12 8001342: 46bd mov sp, r7 8001344: f85d 7b04 ldr.w r7, [sp], #4 8001348: 4770 bx lr 0800134a <_fstat>: int _fstat(int file, struct stat *st) { 800134a: b480 push {r7} 800134c: b083 sub sp, #12 800134e: af00 add r7, sp, #0 8001350: 6078 str r0, [r7, #4] 8001352: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 8001354: 683b ldr r3, [r7, #0] 8001356: f44f 5200 mov.w r2, #8192 ; 0x2000 800135a: 605a str r2, [r3, #4] return 0; 800135c: 2300 movs r3, #0 } 800135e: 4618 mov r0, r3 8001360: 370c adds r7, #12 8001362: 46bd mov sp, r7 8001364: f85d 7b04 ldr.w r7, [sp], #4 8001368: 4770 bx lr 0800136a <_isatty>: int _isatty(int file) { 800136a: b480 push {r7} 800136c: b083 sub sp, #12 800136e: af00 add r7, sp, #0 8001370: 6078 str r0, [r7, #4] return 1; 8001372: 2301 movs r3, #1 } 8001374: 4618 mov r0, r3 8001376: 370c adds r7, #12 8001378: 46bd mov sp, r7 800137a: f85d 7b04 ldr.w r7, [sp], #4 800137e: 4770 bx lr 08001380 <_lseek>: int _lseek(int file, int ptr, int dir) { 8001380: b480 push {r7} 8001382: b085 sub sp, #20 8001384: af00 add r7, sp, #0 8001386: 60f8 str r0, [r7, #12] 8001388: 60b9 str r1, [r7, #8] 800138a: 607a str r2, [r7, #4] return 0; 800138c: 2300 movs r3, #0 } 800138e: 4618 mov r0, r3 8001390: 3714 adds r7, #20 8001392: 46bd mov sp, r7 8001394: f85d 7b04 ldr.w r7, [sp], #4 8001398: 4770 bx lr ... 0800139c <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 800139c: b580 push {r7, lr} 800139e: b086 sub sp, #24 80013a0: af00 add r7, sp, #0 80013a2: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 80013a4: 4a14 ldr r2, [pc, #80] ; (80013f8 <_sbrk+0x5c>) 80013a6: 4b15 ldr r3, [pc, #84] ; (80013fc <_sbrk+0x60>) 80013a8: 1ad3 subs r3, r2, r3 80013aa: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 80013ac: 697b ldr r3, [r7, #20] 80013ae: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 80013b0: 4b13 ldr r3, [pc, #76] ; (8001400 <_sbrk+0x64>) 80013b2: 681b ldr r3, [r3, #0] 80013b4: 2b00 cmp r3, #0 80013b6: d102 bne.n 80013be <_sbrk+0x22> { __sbrk_heap_end = &_end; 80013b8: 4b11 ldr r3, [pc, #68] ; (8001400 <_sbrk+0x64>) 80013ba: 4a12 ldr r2, [pc, #72] ; (8001404 <_sbrk+0x68>) 80013bc: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 80013be: 4b10 ldr r3, [pc, #64] ; (8001400 <_sbrk+0x64>) 80013c0: 681a ldr r2, [r3, #0] 80013c2: 687b ldr r3, [r7, #4] 80013c4: 4413 add r3, r2 80013c6: 693a ldr r2, [r7, #16] 80013c8: 429a cmp r2, r3 80013ca: d207 bcs.n 80013dc <_sbrk+0x40> { errno = ENOMEM; 80013cc: f008 faa4 bl 8009918 <__errno> 80013d0: 4603 mov r3, r0 80013d2: 220c movs r2, #12 80013d4: 601a str r2, [r3, #0] return (void *)-1; 80013d6: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 80013da: e009 b.n 80013f0 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80013dc: 4b08 ldr r3, [pc, #32] ; (8001400 <_sbrk+0x64>) 80013de: 681b ldr r3, [r3, #0] 80013e0: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80013e2: 4b07 ldr r3, [pc, #28] ; (8001400 <_sbrk+0x64>) 80013e4: 681a ldr r2, [r3, #0] 80013e6: 687b ldr r3, [r7, #4] 80013e8: 4413 add r3, r2 80013ea: 4a05 ldr r2, [pc, #20] ; (8001400 <_sbrk+0x64>) 80013ec: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80013ee: 68fb ldr r3, [r7, #12] } 80013f0: 4618 mov r0, r3 80013f2: 3718 adds r7, #24 80013f4: 46bd mov sp, r7 80013f6: bd80 pop {r7, pc} 80013f8: 24050000 .word 0x24050000 80013fc: 00000400 .word 0x00000400 8001400: 240011b0 .word 0x240011b0 8001404: 24002d18 .word 0x24002d18 08001408 : * configuration. * @param None * @retval None */ void SystemInit (void) { 8001408: b480 push {r7} 800140a: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 800140c: 4b32 ldr r3, [pc, #200] ; (80014d8 ) 800140e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8001412: 4a31 ldr r2, [pc, #196] ; (80014d8 ) 8001414: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8001418: f8c2 3088 str.w r3, [r2, #136] ; 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 800141c: 4b2f ldr r3, [pc, #188] ; (80014dc ) 800141e: 681b ldr r3, [r3, #0] 8001420: f003 030f and.w r3, r3, #15 8001424: 2b06 cmp r3, #6 8001426: d807 bhi.n 8001438 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8001428: 4b2c ldr r3, [pc, #176] ; (80014dc ) 800142a: 681b ldr r3, [r3, #0] 800142c: f023 030f bic.w r3, r3, #15 8001430: 4a2a ldr r2, [pc, #168] ; (80014dc ) 8001432: f043 0307 orr.w r3, r3, #7 8001436: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 8001438: 4b29 ldr r3, [pc, #164] ; (80014e0 ) 800143a: 681b ldr r3, [r3, #0] 800143c: 4a28 ldr r2, [pc, #160] ; (80014e0 ) 800143e: f043 0301 orr.w r3, r3, #1 8001442: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 8001444: 4b26 ldr r3, [pc, #152] ; (80014e0 ) 8001446: 2200 movs r2, #0 8001448: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 800144a: 4b25 ldr r3, [pc, #148] ; (80014e0 ) 800144c: 681a ldr r2, [r3, #0] 800144e: 4924 ldr r1, [pc, #144] ; (80014e0 ) 8001450: 4b24 ldr r3, [pc, #144] ; (80014e4 ) 8001452: 4013 ands r3, r2 8001454: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8001456: 4b21 ldr r3, [pc, #132] ; (80014dc ) 8001458: 681b ldr r3, [r3, #0] 800145a: f003 0308 and.w r3, r3, #8 800145e: 2b00 cmp r3, #0 8001460: d007 beq.n 8001472 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8001462: 4b1e ldr r3, [pc, #120] ; (80014dc ) 8001464: 681b ldr r3, [r3, #0] 8001466: f023 030f bic.w r3, r3, #15 800146a: 4a1c ldr r2, [pc, #112] ; (80014dc ) 800146c: f043 0307 orr.w r3, r3, #7 8001470: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 8001472: 4b1b ldr r3, [pc, #108] ; (80014e0 ) 8001474: 2200 movs r2, #0 8001476: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 8001478: 4b19 ldr r3, [pc, #100] ; (80014e0 ) 800147a: 2200 movs r2, #0 800147c: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 800147e: 4b18 ldr r3, [pc, #96] ; (80014e0 ) 8001480: 2200 movs r2, #0 8001482: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 8001484: 4b16 ldr r3, [pc, #88] ; (80014e0 ) 8001486: 4a18 ldr r2, [pc, #96] ; (80014e8 ) 8001488: 629a str r2, [r3, #40] ; 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 800148a: 4b15 ldr r3, [pc, #84] ; (80014e0 ) 800148c: 4a17 ldr r2, [pc, #92] ; (80014ec ) 800148e: 62da str r2, [r3, #44] ; 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 8001490: 4b13 ldr r3, [pc, #76] ; (80014e0 ) 8001492: 4a17 ldr r2, [pc, #92] ; (80014f0 ) 8001494: 631a str r2, [r3, #48] ; 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 8001496: 4b12 ldr r3, [pc, #72] ; (80014e0 ) 8001498: 2200 movs r2, #0 800149a: 635a str r2, [r3, #52] ; 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 800149c: 4b10 ldr r3, [pc, #64] ; (80014e0 ) 800149e: 4a14 ldr r2, [pc, #80] ; (80014f0 ) 80014a0: 639a str r2, [r3, #56] ; 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 80014a2: 4b0f ldr r3, [pc, #60] ; (80014e0 ) 80014a4: 2200 movs r2, #0 80014a6: 63da str r2, [r3, #60] ; 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 80014a8: 4b0d ldr r3, [pc, #52] ; (80014e0 ) 80014aa: 4a11 ldr r2, [pc, #68] ; (80014f0 ) 80014ac: 641a str r2, [r3, #64] ; 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 80014ae: 4b0c ldr r3, [pc, #48] ; (80014e0 ) 80014b0: 2200 movs r2, #0 80014b2: 645a str r2, [r3, #68] ; 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 80014b4: 4b0a ldr r3, [pc, #40] ; (80014e0 ) 80014b6: 681b ldr r3, [r3, #0] 80014b8: 4a09 ldr r2, [pc, #36] ; (80014e0 ) 80014ba: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80014be: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 80014c0: 4b07 ldr r3, [pc, #28] ; (80014e0 ) 80014c2: 2200 movs r2, #0 80014c4: 661a str r2, [r3, #96] ; 0x60 /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 80014c6: 4b0b ldr r3, [pc, #44] ; (80014f4 ) 80014c8: f243 02d2 movw r2, #12498 ; 0x30d2 80014cc: 601a str r2, [r3, #0] SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 80014ce: bf00 nop 80014d0: 46bd mov sp, r7 80014d2: f85d 7b04 ldr.w r7, [sp], #4 80014d6: 4770 bx lr 80014d8: e000ed00 .word 0xe000ed00 80014dc: 52002000 .word 0x52002000 80014e0: 58024400 .word 0x58024400 80014e4: eaf6ed7f .word 0xeaf6ed7f 80014e8: 02020200 .word 0x02020200 80014ec: 01ff0000 .word 0x01ff0000 80014f0: 01010280 .word 0x01010280 80014f4: 52004000 .word 0x52004000 080014f8 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 80014f8: f8df d034 ldr.w sp, [pc, #52] ; 8001530 /* Call the clock system initialization function.*/ bl SystemInit 80014fc: f7ff ff84 bl 8001408 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001500: 480c ldr r0, [pc, #48] ; (8001534 ) ldr r1, =_edata 8001502: 490d ldr r1, [pc, #52] ; (8001538 ) ldr r2, =_sidata 8001504: 4a0d ldr r2, [pc, #52] ; (800153c ) movs r3, #0 8001506: 2300 movs r3, #0 b LoopCopyDataInit 8001508: e002 b.n 8001510 0800150a : CopyDataInit: ldr r4, [r2, r3] 800150a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800150c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800150e: 3304 adds r3, #4 08001510 : LoopCopyDataInit: adds r4, r0, r3 8001510: 18c4 adds r4, r0, r3 cmp r4, r1 8001512: 428c cmp r4, r1 bcc CopyDataInit 8001514: d3f9 bcc.n 800150a /* Zero fill the bss segment. */ ldr r2, =_sbss 8001516: 4a0a ldr r2, [pc, #40] ; (8001540 ) ldr r4, =_ebss 8001518: 4c0a ldr r4, [pc, #40] ; (8001544 ) movs r3, #0 800151a: 2300 movs r3, #0 b LoopFillZerobss 800151c: e001 b.n 8001522 0800151e : FillZerobss: str r3, [r2] 800151e: 6013 str r3, [r2, #0] adds r2, r2, #4 8001520: 3204 adds r2, #4 08001522 : LoopFillZerobss: cmp r2, r4 8001522: 42a2 cmp r2, r4 bcc FillZerobss 8001524: d3fb bcc.n 800151e /* Call static constructors */ bl __libc_init_array 8001526: f008 fa0f bl 8009948 <__libc_init_array> /* Call the application's entry point.*/ bl main 800152a: f7ff faa1 bl 8000a70
bx lr 800152e: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001530: 24050000 .word 0x24050000 ldr r0, =_sdata 8001534: 24000000 .word 0x24000000 ldr r1, =_edata 8001538: 240001e8 .word 0x240001e8 ldr r2, =_sidata 800153c: 0800aafc .word 0x0800aafc ldr r2, =_sbss 8001540: 240001e8 .word 0x240001e8 ldr r4, =_ebss 8001544: 24002d18 .word 0x24002d18 08001548 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001548: e7fe b.n 8001548 ... 0800154c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800154c: b580 push {r7, lr} 800154e: b082 sub sp, #8 8001550: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001552: 2003 movs r0, #3 8001554: f000 f980 bl 8001858 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8001558: f002 fb14 bl 8003b84 800155c: 4602 mov r2, r0 800155e: 4b15 ldr r3, [pc, #84] ; (80015b4 ) 8001560: 699b ldr r3, [r3, #24] 8001562: 0a1b lsrs r3, r3, #8 8001564: f003 030f and.w r3, r3, #15 8001568: 4913 ldr r1, [pc, #76] ; (80015b8 ) 800156a: 5ccb ldrb r3, [r1, r3] 800156c: f003 031f and.w r3, r3, #31 8001570: fa22 f303 lsr.w r3, r2, r3 8001574: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8001576: 4b0f ldr r3, [pc, #60] ; (80015b4 ) 8001578: 699b ldr r3, [r3, #24] 800157a: f003 030f and.w r3, r3, #15 800157e: 4a0e ldr r2, [pc, #56] ; (80015b8 ) 8001580: 5cd3 ldrb r3, [r2, r3] 8001582: f003 031f and.w r3, r3, #31 8001586: 687a ldr r2, [r7, #4] 8001588: fa22 f303 lsr.w r3, r2, r3 800158c: 4a0b ldr r2, [pc, #44] ; (80015bc ) 800158e: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8001590: 4a0b ldr r2, [pc, #44] ; (80015c0 ) 8001592: 687b ldr r3, [r7, #4] 8001594: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8001596: 2000 movs r0, #0 8001598: f000 f814 bl 80015c4 800159c: 4603 mov r3, r0 800159e: 2b00 cmp r3, #0 80015a0: d001 beq.n 80015a6 { return HAL_ERROR; 80015a2: 2301 movs r3, #1 80015a4: e002 b.n 80015ac } /* Init the low level hardware */ HAL_MspInit(); 80015a6: f7ff fde9 bl 800117c /* Return function status */ return HAL_OK; 80015aa: 2300 movs r3, #0 } 80015ac: 4618 mov r0, r3 80015ae: 3708 adds r7, #8 80015b0: 46bd mov sp, r7 80015b2: bd80 pop {r7, pc} 80015b4: 58024400 .word 0x58024400 80015b8: 0800aa10 .word 0x0800aa10 80015bc: 24000004 .word 0x24000004 80015c0: 24000000 .word 0x24000000 080015c4 : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80015c4: b580 push {r7, lr} 80015c6: b082 sub sp, #8 80015c8: af00 add r7, sp, #0 80015ca: 6078 str r0, [r7, #4] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if((uint32_t)uwTickFreq == 0UL) 80015cc: 4b15 ldr r3, [pc, #84] ; (8001624 ) 80015ce: 781b ldrb r3, [r3, #0] 80015d0: 2b00 cmp r3, #0 80015d2: d101 bne.n 80015d8 { return HAL_ERROR; 80015d4: 2301 movs r3, #1 80015d6: e021 b.n 800161c } /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) 80015d8: 4b13 ldr r3, [pc, #76] ; (8001628 ) 80015da: 681a ldr r2, [r3, #0] 80015dc: 4b11 ldr r3, [pc, #68] ; (8001624 ) 80015de: 781b ldrb r3, [r3, #0] 80015e0: 4619 mov r1, r3 80015e2: f44f 737a mov.w r3, #1000 ; 0x3e8 80015e6: fbb3 f3f1 udiv r3, r3, r1 80015ea: fbb2 f3f3 udiv r3, r2, r3 80015ee: 4618 mov r0, r3 80015f0: f000 f965 bl 80018be 80015f4: 4603 mov r3, r0 80015f6: 2b00 cmp r3, #0 80015f8: d001 beq.n 80015fe { return HAL_ERROR; 80015fa: 2301 movs r3, #1 80015fc: e00e b.n 800161c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80015fe: 687b ldr r3, [r7, #4] 8001600: 2b0f cmp r3, #15 8001602: d80a bhi.n 800161a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001604: 2200 movs r2, #0 8001606: 6879 ldr r1, [r7, #4] 8001608: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800160c: f000 f92f bl 800186e uwTickPrio = TickPriority; 8001610: 4a06 ldr r2, [pc, #24] ; (800162c ) 8001612: 687b ldr r3, [r7, #4] 8001614: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8001616: 2300 movs r3, #0 8001618: e000 b.n 800161c return HAL_ERROR; 800161a: 2301 movs r3, #1 } 800161c: 4618 mov r0, r3 800161e: 3708 adds r7, #8 8001620: 46bd mov sp, r7 8001622: bd80 pop {r7, pc} 8001624: 2400000c .word 0x2400000c 8001628: 24000000 .word 0x24000000 800162c: 24000008 .word 0x24000008 08001630 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001630: b480 push {r7} 8001632: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8001634: 4b06 ldr r3, [pc, #24] ; (8001650 ) 8001636: 781b ldrb r3, [r3, #0] 8001638: 461a mov r2, r3 800163a: 4b06 ldr r3, [pc, #24] ; (8001654 ) 800163c: 681b ldr r3, [r3, #0] 800163e: 4413 add r3, r2 8001640: 4a04 ldr r2, [pc, #16] ; (8001654 ) 8001642: 6013 str r3, [r2, #0] } 8001644: bf00 nop 8001646: 46bd mov sp, r7 8001648: f85d 7b04 ldr.w r7, [sp], #4 800164c: 4770 bx lr 800164e: bf00 nop 8001650: 2400000c .word 0x2400000c 8001654: 2400142c .word 0x2400142c 08001658 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001658: b480 push {r7} 800165a: af00 add r7, sp, #0 return uwTick; 800165c: 4b03 ldr r3, [pc, #12] ; (800166c ) 800165e: 681b ldr r3, [r3, #0] } 8001660: 4618 mov r0, r3 8001662: 46bd mov sp, r7 8001664: f85d 7b04 ldr.w r7, [sp], #4 8001668: 4770 bx lr 800166a: bf00 nop 800166c: 2400142c .word 0x2400142c 08001670 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001670: b580 push {r7, lr} 8001672: b084 sub sp, #16 8001674: af00 add r7, sp, #0 8001676: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001678: f7ff ffee bl 8001658 800167c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800167e: 687b ldr r3, [r7, #4] 8001680: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001682: 68fb ldr r3, [r7, #12] 8001684: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8001688: d005 beq.n 8001696 { wait += (uint32_t)(uwTickFreq); 800168a: 4b0a ldr r3, [pc, #40] ; (80016b4 ) 800168c: 781b ldrb r3, [r3, #0] 800168e: 461a mov r2, r3 8001690: 68fb ldr r3, [r7, #12] 8001692: 4413 add r3, r2 8001694: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8001696: bf00 nop 8001698: f7ff ffde bl 8001658 800169c: 4602 mov r2, r0 800169e: 68bb ldr r3, [r7, #8] 80016a0: 1ad3 subs r3, r2, r3 80016a2: 68fa ldr r2, [r7, #12] 80016a4: 429a cmp r2, r3 80016a6: d8f7 bhi.n 8001698 { } } 80016a8: bf00 nop 80016aa: bf00 nop 80016ac: 3710 adds r7, #16 80016ae: 46bd mov sp, r7 80016b0: bd80 pop {r7, pc} 80016b2: bf00 nop 80016b4: 2400000c .word 0x2400000c 080016b8 <__NVIC_SetPriorityGrouping>: { 80016b8: b480 push {r7} 80016ba: b085 sub sp, #20 80016bc: af00 add r7, sp, #0 80016be: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80016c0: 687b ldr r3, [r7, #4] 80016c2: f003 0307 and.w r3, r3, #7 80016c6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80016c8: 4b0b ldr r3, [pc, #44] ; (80016f8 <__NVIC_SetPriorityGrouping+0x40>) 80016ca: 68db ldr r3, [r3, #12] 80016cc: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80016ce: 68ba ldr r2, [r7, #8] 80016d0: f64f 03ff movw r3, #63743 ; 0xf8ff 80016d4: 4013 ands r3, r2 80016d6: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80016d8: 68fb ldr r3, [r7, #12] 80016da: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80016dc: 68bb ldr r3, [r7, #8] 80016de: 431a orrs r2, r3 reg_value = (reg_value | 80016e0: 4b06 ldr r3, [pc, #24] ; (80016fc <__NVIC_SetPriorityGrouping+0x44>) 80016e2: 4313 orrs r3, r2 80016e4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80016e6: 4a04 ldr r2, [pc, #16] ; (80016f8 <__NVIC_SetPriorityGrouping+0x40>) 80016e8: 68bb ldr r3, [r7, #8] 80016ea: 60d3 str r3, [r2, #12] } 80016ec: bf00 nop 80016ee: 3714 adds r7, #20 80016f0: 46bd mov sp, r7 80016f2: f85d 7b04 ldr.w r7, [sp], #4 80016f6: 4770 bx lr 80016f8: e000ed00 .word 0xe000ed00 80016fc: 05fa0000 .word 0x05fa0000 08001700 <__NVIC_GetPriorityGrouping>: { 8001700: b480 push {r7} 8001702: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001704: 4b04 ldr r3, [pc, #16] ; (8001718 <__NVIC_GetPriorityGrouping+0x18>) 8001706: 68db ldr r3, [r3, #12] 8001708: 0a1b lsrs r3, r3, #8 800170a: f003 0307 and.w r3, r3, #7 } 800170e: 4618 mov r0, r3 8001710: 46bd mov sp, r7 8001712: f85d 7b04 ldr.w r7, [sp], #4 8001716: 4770 bx lr 8001718: e000ed00 .word 0xe000ed00 0800171c <__NVIC_EnableIRQ>: { 800171c: b480 push {r7} 800171e: b083 sub sp, #12 8001720: af00 add r7, sp, #0 8001722: 4603 mov r3, r0 8001724: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8001726: f9b7 3006 ldrsh.w r3, [r7, #6] 800172a: 2b00 cmp r3, #0 800172c: db0b blt.n 8001746 <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800172e: 88fb ldrh r3, [r7, #6] 8001730: f003 021f and.w r2, r3, #31 8001734: 4907 ldr r1, [pc, #28] ; (8001754 <__NVIC_EnableIRQ+0x38>) 8001736: f9b7 3006 ldrsh.w r3, [r7, #6] 800173a: 095b lsrs r3, r3, #5 800173c: 2001 movs r0, #1 800173e: fa00 f202 lsl.w r2, r0, r2 8001742: f841 2023 str.w r2, [r1, r3, lsl #2] } 8001746: bf00 nop 8001748: 370c adds r7, #12 800174a: 46bd mov sp, r7 800174c: f85d 7b04 ldr.w r7, [sp], #4 8001750: 4770 bx lr 8001752: bf00 nop 8001754: e000e100 .word 0xe000e100 08001758 <__NVIC_SetPriority>: { 8001758: b480 push {r7} 800175a: b083 sub sp, #12 800175c: af00 add r7, sp, #0 800175e: 4603 mov r3, r0 8001760: 6039 str r1, [r7, #0] 8001762: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8001764: f9b7 3006 ldrsh.w r3, [r7, #6] 8001768: 2b00 cmp r3, #0 800176a: db0a blt.n 8001782 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800176c: 683b ldr r3, [r7, #0] 800176e: b2da uxtb r2, r3 8001770: 490c ldr r1, [pc, #48] ; (80017a4 <__NVIC_SetPriority+0x4c>) 8001772: f9b7 3006 ldrsh.w r3, [r7, #6] 8001776: 0112 lsls r2, r2, #4 8001778: b2d2 uxtb r2, r2 800177a: 440b add r3, r1 800177c: f883 2300 strb.w r2, [r3, #768] ; 0x300 } 8001780: e00a b.n 8001798 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001782: 683b ldr r3, [r7, #0] 8001784: b2da uxtb r2, r3 8001786: 4908 ldr r1, [pc, #32] ; (80017a8 <__NVIC_SetPriority+0x50>) 8001788: 88fb ldrh r3, [r7, #6] 800178a: f003 030f and.w r3, r3, #15 800178e: 3b04 subs r3, #4 8001790: 0112 lsls r2, r2, #4 8001792: b2d2 uxtb r2, r2 8001794: 440b add r3, r1 8001796: 761a strb r2, [r3, #24] } 8001798: bf00 nop 800179a: 370c adds r7, #12 800179c: 46bd mov sp, r7 800179e: f85d 7b04 ldr.w r7, [sp], #4 80017a2: 4770 bx lr 80017a4: e000e100 .word 0xe000e100 80017a8: e000ed00 .word 0xe000ed00 080017ac : { 80017ac: b480 push {r7} 80017ae: b089 sub sp, #36 ; 0x24 80017b0: af00 add r7, sp, #0 80017b2: 60f8 str r0, [r7, #12] 80017b4: 60b9 str r1, [r7, #8] 80017b6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80017b8: 68fb ldr r3, [r7, #12] 80017ba: f003 0307 and.w r3, r3, #7 80017be: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80017c0: 69fb ldr r3, [r7, #28] 80017c2: f1c3 0307 rsb r3, r3, #7 80017c6: 2b04 cmp r3, #4 80017c8: bf28 it cs 80017ca: 2304 movcs r3, #4 80017cc: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80017ce: 69fb ldr r3, [r7, #28] 80017d0: 3304 adds r3, #4 80017d2: 2b06 cmp r3, #6 80017d4: d902 bls.n 80017dc 80017d6: 69fb ldr r3, [r7, #28] 80017d8: 3b03 subs r3, #3 80017da: e000 b.n 80017de 80017dc: 2300 movs r3, #0 80017de: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80017e0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80017e4: 69bb ldr r3, [r7, #24] 80017e6: fa02 f303 lsl.w r3, r2, r3 80017ea: 43da mvns r2, r3 80017ec: 68bb ldr r3, [r7, #8] 80017ee: 401a ands r2, r3 80017f0: 697b ldr r3, [r7, #20] 80017f2: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80017f4: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 80017f8: 697b ldr r3, [r7, #20] 80017fa: fa01 f303 lsl.w r3, r1, r3 80017fe: 43d9 mvns r1, r3 8001800: 687b ldr r3, [r7, #4] 8001802: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001804: 4313 orrs r3, r2 } 8001806: 4618 mov r0, r3 8001808: 3724 adds r7, #36 ; 0x24 800180a: 46bd mov sp, r7 800180c: f85d 7b04 ldr.w r7, [sp], #4 8001810: 4770 bx lr ... 08001814 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001814: b580 push {r7, lr} 8001816: b082 sub sp, #8 8001818: af00 add r7, sp, #0 800181a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800181c: 687b ldr r3, [r7, #4] 800181e: 3b01 subs r3, #1 8001820: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8001824: d301 bcc.n 800182a { return (1UL); /* Reload value impossible */ 8001826: 2301 movs r3, #1 8001828: e00f b.n 800184a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800182a: 4a0a ldr r2, [pc, #40] ; (8001854 ) 800182c: 687b ldr r3, [r7, #4] 800182e: 3b01 subs r3, #1 8001830: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001832: 210f movs r1, #15 8001834: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001838: f7ff ff8e bl 8001758 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800183c: 4b05 ldr r3, [pc, #20] ; (8001854 ) 800183e: 2200 movs r2, #0 8001840: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001842: 4b04 ldr r3, [pc, #16] ; (8001854 ) 8001844: 2207 movs r2, #7 8001846: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001848: 2300 movs r3, #0 } 800184a: 4618 mov r0, r3 800184c: 3708 adds r7, #8 800184e: 46bd mov sp, r7 8001850: bd80 pop {r7, pc} 8001852: bf00 nop 8001854: e000e010 .word 0xe000e010 08001858 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001858: b580 push {r7, lr} 800185a: b082 sub sp, #8 800185c: af00 add r7, sp, #0 800185e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001860: 6878 ldr r0, [r7, #4] 8001862: f7ff ff29 bl 80016b8 <__NVIC_SetPriorityGrouping> } 8001866: bf00 nop 8001868: 3708 adds r7, #8 800186a: 46bd mov sp, r7 800186c: bd80 pop {r7, pc} 0800186e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800186e: b580 push {r7, lr} 8001870: b086 sub sp, #24 8001872: af00 add r7, sp, #0 8001874: 4603 mov r3, r0 8001876: 60b9 str r1, [r7, #8] 8001878: 607a str r2, [r7, #4] 800187a: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800187c: f7ff ff40 bl 8001700 <__NVIC_GetPriorityGrouping> 8001880: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001882: 687a ldr r2, [r7, #4] 8001884: 68b9 ldr r1, [r7, #8] 8001886: 6978 ldr r0, [r7, #20] 8001888: f7ff ff90 bl 80017ac 800188c: 4602 mov r2, r0 800188e: f9b7 300e ldrsh.w r3, [r7, #14] 8001892: 4611 mov r1, r2 8001894: 4618 mov r0, r3 8001896: f7ff ff5f bl 8001758 <__NVIC_SetPriority> } 800189a: bf00 nop 800189c: 3718 adds r7, #24 800189e: 46bd mov sp, r7 80018a0: bd80 pop {r7, pc} 080018a2 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80018a2: b580 push {r7, lr} 80018a4: b082 sub sp, #8 80018a6: af00 add r7, sp, #0 80018a8: 4603 mov r3, r0 80018aa: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80018ac: f9b7 3006 ldrsh.w r3, [r7, #6] 80018b0: 4618 mov r0, r3 80018b2: f7ff ff33 bl 800171c <__NVIC_EnableIRQ> } 80018b6: bf00 nop 80018b8: 3708 adds r7, #8 80018ba: 46bd mov sp, r7 80018bc: bd80 pop {r7, pc} 080018be : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80018be: b580 push {r7, lr} 80018c0: b082 sub sp, #8 80018c2: af00 add r7, sp, #0 80018c4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80018c6: 6878 ldr r0, [r7, #4] 80018c8: f7ff ffa4 bl 8001814 80018cc: 4603 mov r3, r0 } 80018ce: 4618 mov r0, r3 80018d0: 3708 adds r7, #8 80018d2: 46bd mov sp, r7 80018d4: bd80 pop {r7, pc} ... 080018d8 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80018d8: b480 push {r7} 80018da: b089 sub sp, #36 ; 0x24 80018dc: af00 add r7, sp, #0 80018de: 6078 str r0, [r7, #4] 80018e0: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 80018e2: 2300 movs r3, #0 80018e4: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 80018e6: 4b86 ldr r3, [pc, #536] ; (8001b00 ) 80018e8: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 80018ea: e18c b.n 8001c06 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 80018ec: 683b ldr r3, [r7, #0] 80018ee: 681a ldr r2, [r3, #0] 80018f0: 2101 movs r1, #1 80018f2: 69fb ldr r3, [r7, #28] 80018f4: fa01 f303 lsl.w r3, r1, r3 80018f8: 4013 ands r3, r2 80018fa: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 80018fc: 693b ldr r3, [r7, #16] 80018fe: 2b00 cmp r3, #0 8001900: f000 817e beq.w 8001c00 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8001904: 683b ldr r3, [r7, #0] 8001906: 685b ldr r3, [r3, #4] 8001908: f003 0303 and.w r3, r3, #3 800190c: 2b01 cmp r3, #1 800190e: d005 beq.n 800191c 8001910: 683b ldr r3, [r7, #0] 8001912: 685b ldr r3, [r3, #4] 8001914: f003 0303 and.w r3, r3, #3 8001918: 2b02 cmp r3, #2 800191a: d130 bne.n 800197e { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800191c: 687b ldr r3, [r7, #4] 800191e: 689b ldr r3, [r3, #8] 8001920: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8001922: 69fb ldr r3, [r7, #28] 8001924: 005b lsls r3, r3, #1 8001926: 2203 movs r2, #3 8001928: fa02 f303 lsl.w r3, r2, r3 800192c: 43db mvns r3, r3 800192e: 69ba ldr r2, [r7, #24] 8001930: 4013 ands r3, r2 8001932: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8001934: 683b ldr r3, [r7, #0] 8001936: 68da ldr r2, [r3, #12] 8001938: 69fb ldr r3, [r7, #28] 800193a: 005b lsls r3, r3, #1 800193c: fa02 f303 lsl.w r3, r2, r3 8001940: 69ba ldr r2, [r7, #24] 8001942: 4313 orrs r3, r2 8001944: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8001946: 687b ldr r3, [r7, #4] 8001948: 69ba ldr r2, [r7, #24] 800194a: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800194c: 687b ldr r3, [r7, #4] 800194e: 685b ldr r3, [r3, #4] 8001950: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8001952: 2201 movs r2, #1 8001954: 69fb ldr r3, [r7, #28] 8001956: fa02 f303 lsl.w r3, r2, r3 800195a: 43db mvns r3, r3 800195c: 69ba ldr r2, [r7, #24] 800195e: 4013 ands r3, r2 8001960: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8001962: 683b ldr r3, [r7, #0] 8001964: 685b ldr r3, [r3, #4] 8001966: 091b lsrs r3, r3, #4 8001968: f003 0201 and.w r2, r3, #1 800196c: 69fb ldr r3, [r7, #28] 800196e: fa02 f303 lsl.w r3, r2, r3 8001972: 69ba ldr r2, [r7, #24] 8001974: 4313 orrs r3, r2 8001976: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8001978: 687b ldr r3, [r7, #4] 800197a: 69ba ldr r2, [r7, #24] 800197c: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800197e: 683b ldr r3, [r7, #0] 8001980: 685b ldr r3, [r3, #4] 8001982: f003 0303 and.w r3, r3, #3 8001986: 2b03 cmp r3, #3 8001988: d017 beq.n 80019ba { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800198a: 687b ldr r3, [r7, #4] 800198c: 68db ldr r3, [r3, #12] 800198e: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8001990: 69fb ldr r3, [r7, #28] 8001992: 005b lsls r3, r3, #1 8001994: 2203 movs r2, #3 8001996: fa02 f303 lsl.w r3, r2, r3 800199a: 43db mvns r3, r3 800199c: 69ba ldr r2, [r7, #24] 800199e: 4013 ands r3, r2 80019a0: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 80019a2: 683b ldr r3, [r7, #0] 80019a4: 689a ldr r2, [r3, #8] 80019a6: 69fb ldr r3, [r7, #28] 80019a8: 005b lsls r3, r3, #1 80019aa: fa02 f303 lsl.w r3, r2, r3 80019ae: 69ba ldr r2, [r7, #24] 80019b0: 4313 orrs r3, r2 80019b2: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 80019b4: 687b ldr r3, [r7, #4] 80019b6: 69ba ldr r2, [r7, #24] 80019b8: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80019ba: 683b ldr r3, [r7, #0] 80019bc: 685b ldr r3, [r3, #4] 80019be: f003 0303 and.w r3, r3, #3 80019c2: 2b02 cmp r3, #2 80019c4: d123 bne.n 8001a0e /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 80019c6: 69fb ldr r3, [r7, #28] 80019c8: 08da lsrs r2, r3, #3 80019ca: 687b ldr r3, [r7, #4] 80019cc: 3208 adds r2, #8 80019ce: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80019d2: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 80019d4: 69fb ldr r3, [r7, #28] 80019d6: f003 0307 and.w r3, r3, #7 80019da: 009b lsls r3, r3, #2 80019dc: 220f movs r2, #15 80019de: fa02 f303 lsl.w r3, r2, r3 80019e2: 43db mvns r3, r3 80019e4: 69ba ldr r2, [r7, #24] 80019e6: 4013 ands r3, r2 80019e8: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 80019ea: 683b ldr r3, [r7, #0] 80019ec: 691a ldr r2, [r3, #16] 80019ee: 69fb ldr r3, [r7, #28] 80019f0: f003 0307 and.w r3, r3, #7 80019f4: 009b lsls r3, r3, #2 80019f6: fa02 f303 lsl.w r3, r2, r3 80019fa: 69ba ldr r2, [r7, #24] 80019fc: 4313 orrs r3, r2 80019fe: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8001a00: 69fb ldr r3, [r7, #28] 8001a02: 08da lsrs r2, r3, #3 8001a04: 687b ldr r3, [r7, #4] 8001a06: 3208 adds r2, #8 8001a08: 69b9 ldr r1, [r7, #24] 8001a0a: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001a0e: 687b ldr r3, [r7, #4] 8001a10: 681b ldr r3, [r3, #0] 8001a12: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 8001a14: 69fb ldr r3, [r7, #28] 8001a16: 005b lsls r3, r3, #1 8001a18: 2203 movs r2, #3 8001a1a: fa02 f303 lsl.w r3, r2, r3 8001a1e: 43db mvns r3, r3 8001a20: 69ba ldr r2, [r7, #24] 8001a22: 4013 ands r3, r2 8001a24: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8001a26: 683b ldr r3, [r7, #0] 8001a28: 685b ldr r3, [r3, #4] 8001a2a: f003 0203 and.w r2, r3, #3 8001a2e: 69fb ldr r3, [r7, #28] 8001a30: 005b lsls r3, r3, #1 8001a32: fa02 f303 lsl.w r3, r2, r3 8001a36: 69ba ldr r2, [r7, #24] 8001a38: 4313 orrs r3, r2 8001a3a: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8001a3c: 687b ldr r3, [r7, #4] 8001a3e: 69ba ldr r2, [r7, #24] 8001a40: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8001a42: 683b ldr r3, [r7, #0] 8001a44: 685b ldr r3, [r3, #4] 8001a46: f403 3340 and.w r3, r3, #196608 ; 0x30000 8001a4a: 2b00 cmp r3, #0 8001a4c: f000 80d8 beq.w 8001c00 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001a50: 4b2c ldr r3, [pc, #176] ; (8001b04 ) 8001a52: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 8001a56: 4a2b ldr r2, [pc, #172] ; (8001b04 ) 8001a58: f043 0302 orr.w r3, r3, #2 8001a5c: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 8001a60: 4b28 ldr r3, [pc, #160] ; (8001b04 ) 8001a62: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 8001a66: f003 0302 and.w r3, r3, #2 8001a6a: 60fb str r3, [r7, #12] 8001a6c: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8001a6e: 4a26 ldr r2, [pc, #152] ; (8001b08 ) 8001a70: 69fb ldr r3, [r7, #28] 8001a72: 089b lsrs r3, r3, #2 8001a74: 3302 adds r3, #2 8001a76: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001a7a: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8001a7c: 69fb ldr r3, [r7, #28] 8001a7e: f003 0303 and.w r3, r3, #3 8001a82: 009b lsls r3, r3, #2 8001a84: 220f movs r2, #15 8001a86: fa02 f303 lsl.w r3, r2, r3 8001a8a: 43db mvns r3, r3 8001a8c: 69ba ldr r2, [r7, #24] 8001a8e: 4013 ands r3, r2 8001a90: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8001a92: 687b ldr r3, [r7, #4] 8001a94: 4a1d ldr r2, [pc, #116] ; (8001b0c ) 8001a96: 4293 cmp r3, r2 8001a98: d04a beq.n 8001b30 8001a9a: 687b ldr r3, [r7, #4] 8001a9c: 4a1c ldr r2, [pc, #112] ; (8001b10 ) 8001a9e: 4293 cmp r3, r2 8001aa0: d02b beq.n 8001afa 8001aa2: 687b ldr r3, [r7, #4] 8001aa4: 4a1b ldr r2, [pc, #108] ; (8001b14 ) 8001aa6: 4293 cmp r3, r2 8001aa8: d025 beq.n 8001af6 8001aaa: 687b ldr r3, [r7, #4] 8001aac: 4a1a ldr r2, [pc, #104] ; (8001b18 ) 8001aae: 4293 cmp r3, r2 8001ab0: d01f beq.n 8001af2 8001ab2: 687b ldr r3, [r7, #4] 8001ab4: 4a19 ldr r2, [pc, #100] ; (8001b1c ) 8001ab6: 4293 cmp r3, r2 8001ab8: d019 beq.n 8001aee 8001aba: 687b ldr r3, [r7, #4] 8001abc: 4a18 ldr r2, [pc, #96] ; (8001b20 ) 8001abe: 4293 cmp r3, r2 8001ac0: d013 beq.n 8001aea 8001ac2: 687b ldr r3, [r7, #4] 8001ac4: 4a17 ldr r2, [pc, #92] ; (8001b24 ) 8001ac6: 4293 cmp r3, r2 8001ac8: d00d beq.n 8001ae6 8001aca: 687b ldr r3, [r7, #4] 8001acc: 4a16 ldr r2, [pc, #88] ; (8001b28 ) 8001ace: 4293 cmp r3, r2 8001ad0: d007 beq.n 8001ae2 8001ad2: 687b ldr r3, [r7, #4] 8001ad4: 4a15 ldr r2, [pc, #84] ; (8001b2c ) 8001ad6: 4293 cmp r3, r2 8001ad8: d101 bne.n 8001ade 8001ada: 2309 movs r3, #9 8001adc: e029 b.n 8001b32 8001ade: 230a movs r3, #10 8001ae0: e027 b.n 8001b32 8001ae2: 2307 movs r3, #7 8001ae4: e025 b.n 8001b32 8001ae6: 2306 movs r3, #6 8001ae8: e023 b.n 8001b32 8001aea: 2305 movs r3, #5 8001aec: e021 b.n 8001b32 8001aee: 2304 movs r3, #4 8001af0: e01f b.n 8001b32 8001af2: 2303 movs r3, #3 8001af4: e01d b.n 8001b32 8001af6: 2302 movs r3, #2 8001af8: e01b b.n 8001b32 8001afa: 2301 movs r3, #1 8001afc: e019 b.n 8001b32 8001afe: bf00 nop 8001b00: 58000080 .word 0x58000080 8001b04: 58024400 .word 0x58024400 8001b08: 58000400 .word 0x58000400 8001b0c: 58020000 .word 0x58020000 8001b10: 58020400 .word 0x58020400 8001b14: 58020800 .word 0x58020800 8001b18: 58020c00 .word 0x58020c00 8001b1c: 58021000 .word 0x58021000 8001b20: 58021400 .word 0x58021400 8001b24: 58021800 .word 0x58021800 8001b28: 58021c00 .word 0x58021c00 8001b2c: 58022400 .word 0x58022400 8001b30: 2300 movs r3, #0 8001b32: 69fa ldr r2, [r7, #28] 8001b34: f002 0203 and.w r2, r2, #3 8001b38: 0092 lsls r2, r2, #2 8001b3a: 4093 lsls r3, r2 8001b3c: 69ba ldr r2, [r7, #24] 8001b3e: 4313 orrs r3, r2 8001b40: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8001b42: 4938 ldr r1, [pc, #224] ; (8001c24 ) 8001b44: 69fb ldr r3, [r7, #28] 8001b46: 089b lsrs r3, r3, #2 8001b48: 3302 adds r3, #2 8001b4a: 69ba ldr r2, [r7, #24] 8001b4c: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8001b50: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 8001b54: 681b ldr r3, [r3, #0] 8001b56: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001b58: 693b ldr r3, [r7, #16] 8001b5a: 43db mvns r3, r3 8001b5c: 69ba ldr r2, [r7, #24] 8001b5e: 4013 ands r3, r2 8001b60: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8001b62: 683b ldr r3, [r7, #0] 8001b64: 685b ldr r3, [r3, #4] 8001b66: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8001b6a: 2b00 cmp r3, #0 8001b6c: d003 beq.n 8001b76 { temp |= iocurrent; 8001b6e: 69ba ldr r2, [r7, #24] 8001b70: 693b ldr r3, [r7, #16] 8001b72: 4313 orrs r3, r2 8001b74: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 8001b76: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 8001b7a: 69bb ldr r3, [r7, #24] 8001b7c: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 8001b7e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 8001b82: 685b ldr r3, [r3, #4] 8001b84: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001b86: 693b ldr r3, [r7, #16] 8001b88: 43db mvns r3, r3 8001b8a: 69ba ldr r2, [r7, #24] 8001b8c: 4013 ands r3, r2 8001b8e: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8001b90: 683b ldr r3, [r7, #0] 8001b92: 685b ldr r3, [r3, #4] 8001b94: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001b98: 2b00 cmp r3, #0 8001b9a: d003 beq.n 8001ba4 { temp |= iocurrent; 8001b9c: 69ba ldr r2, [r7, #24] 8001b9e: 693b ldr r3, [r7, #16] 8001ba0: 4313 orrs r3, r2 8001ba2: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 8001ba4: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 8001ba8: 69bb ldr r3, [r7, #24] 8001baa: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 8001bac: 697b ldr r3, [r7, #20] 8001bae: 685b ldr r3, [r3, #4] 8001bb0: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001bb2: 693b ldr r3, [r7, #16] 8001bb4: 43db mvns r3, r3 8001bb6: 69ba ldr r2, [r7, #24] 8001bb8: 4013 ands r3, r2 8001bba: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8001bbc: 683b ldr r3, [r7, #0] 8001bbe: 685b ldr r3, [r3, #4] 8001bc0: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001bc4: 2b00 cmp r3, #0 8001bc6: d003 beq.n 8001bd0 { temp |= iocurrent; 8001bc8: 69ba ldr r2, [r7, #24] 8001bca: 693b ldr r3, [r7, #16] 8001bcc: 4313 orrs r3, r2 8001bce: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 8001bd0: 697b ldr r3, [r7, #20] 8001bd2: 69ba ldr r2, [r7, #24] 8001bd4: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 8001bd6: 697b ldr r3, [r7, #20] 8001bd8: 681b ldr r3, [r3, #0] 8001bda: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001bdc: 693b ldr r3, [r7, #16] 8001bde: 43db mvns r3, r3 8001be0: 69ba ldr r2, [r7, #24] 8001be2: 4013 ands r3, r2 8001be4: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8001be6: 683b ldr r3, [r7, #0] 8001be8: 685b ldr r3, [r3, #4] 8001bea: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001bee: 2b00 cmp r3, #0 8001bf0: d003 beq.n 8001bfa { temp |= iocurrent; 8001bf2: 69ba ldr r2, [r7, #24] 8001bf4: 693b ldr r3, [r7, #16] 8001bf6: 4313 orrs r3, r2 8001bf8: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 8001bfa: 697b ldr r3, [r7, #20] 8001bfc: 69ba ldr r2, [r7, #24] 8001bfe: 601a str r2, [r3, #0] } } position++; 8001c00: 69fb ldr r3, [r7, #28] 8001c02: 3301 adds r3, #1 8001c04: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 8001c06: 683b ldr r3, [r7, #0] 8001c08: 681a ldr r2, [r3, #0] 8001c0a: 69fb ldr r3, [r7, #28] 8001c0c: fa22 f303 lsr.w r3, r2, r3 8001c10: 2b00 cmp r3, #0 8001c12: f47f ae6b bne.w 80018ec } } 8001c16: bf00 nop 8001c18: bf00 nop 8001c1a: 3724 adds r7, #36 ; 0x24 8001c1c: 46bd mov sp, r7 8001c1e: f85d 7b04 ldr.w r7, [sp], #4 8001c22: 4770 bx lr 8001c24: 58000400 .word 0x58000400 08001c28 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001c28: b480 push {r7} 8001c2a: b083 sub sp, #12 8001c2c: af00 add r7, sp, #0 8001c2e: 6078 str r0, [r7, #4] 8001c30: 460b mov r3, r1 8001c32: 807b strh r3, [r7, #2] 8001c34: 4613 mov r3, r2 8001c36: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001c38: 787b ldrb r3, [r7, #1] 8001c3a: 2b00 cmp r3, #0 8001c3c: d003 beq.n 8001c46 { GPIOx->BSRR = GPIO_Pin; 8001c3e: 887a ldrh r2, [r7, #2] 8001c40: 687b ldr r3, [r7, #4] 8001c42: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 8001c44: e003 b.n 8001c4e GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 8001c46: 887b ldrh r3, [r7, #2] 8001c48: 041a lsls r2, r3, #16 8001c4a: 687b ldr r3, [r7, #4] 8001c4c: 619a str r2, [r3, #24] } 8001c4e: bf00 nop 8001c50: 370c adds r7, #12 8001c52: 46bd mov sp, r7 8001c54: f85d 7b04 ldr.w r7, [sp], #4 8001c58: 4770 bx lr 08001c5a : * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8001c5a: b480 push {r7} 8001c5c: b085 sub sp, #20 8001c5e: af00 add r7, sp, #0 8001c60: 6078 str r0, [r7, #4] 8001c62: 460b mov r3, r1 8001c64: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 8001c66: 687b ldr r3, [r7, #4] 8001c68: 695b ldr r3, [r3, #20] 8001c6a: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 8001c6c: 887a ldrh r2, [r7, #2] 8001c6e: 68fb ldr r3, [r7, #12] 8001c70: 4013 ands r3, r2 8001c72: 041a lsls r2, r3, #16 8001c74: 68fb ldr r3, [r7, #12] 8001c76: 43d9 mvns r1, r3 8001c78: 887b ldrh r3, [r7, #2] 8001c7a: 400b ands r3, r1 8001c7c: 431a orrs r2, r3 8001c7e: 687b ldr r3, [r7, #4] 8001c80: 619a str r2, [r3, #24] } 8001c82: bf00 nop 8001c84: 3714 adds r7, #20 8001c86: 46bd mov sp, r7 8001c88: f85d 7b04 ldr.w r7, [sp], #4 8001c8c: 4770 bx lr 08001c8e : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8001c8e: b5f0 push {r4, r5, r6, r7, lr} 8001c90: b08f sub sp, #60 ; 0x3c 8001c92: af0a add r7, sp, #40 ; 0x28 8001c94: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx; uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8001c96: 687b ldr r3, [r7, #4] 8001c98: 2b00 cmp r3, #0 8001c9a: d101 bne.n 8001ca0 { return HAL_ERROR; 8001c9c: 2301 movs r3, #1 8001c9e: e116 b.n 8001ece } /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); USBx = hpcd->Instance; 8001ca0: 687b ldr r3, [r7, #4] 8001ca2: 681b ldr r3, [r3, #0] 8001ca4: 60bb str r3, [r7, #8] if (hpcd->State == HAL_PCD_STATE_RESET) 8001ca6: 687b ldr r3, [r7, #4] 8001ca8: f893 33bd ldrb.w r3, [r3, #957] ; 0x3bd 8001cac: b2db uxtb r3, r3 8001cae: 2b00 cmp r3, #0 8001cb0: d106 bne.n 8001cc0 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8001cb2: 687b ldr r3, [r7, #4] 8001cb4: 2200 movs r2, #0 8001cb6: f883 23bc strb.w r2, [r3, #956] ; 0x3bc /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8001cba: 6878 ldr r0, [r7, #4] 8001cbc: f007 fad2 bl 8009264 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8001cc0: 687b ldr r3, [r7, #4] 8001cc2: 2203 movs r2, #3 8001cc4: f883 23bd strb.w r2, [r3, #957] ; 0x3bd /* Disable DMA mode for FS instance */ if ((USBx->CID & (0x1U << 8)) == 0U) 8001cc8: 68bb ldr r3, [r7, #8] 8001cca: 6bdb ldr r3, [r3, #60] ; 0x3c 8001ccc: f403 7380 and.w r3, r3, #256 ; 0x100 8001cd0: 2b00 cmp r3, #0 8001cd2: d102 bne.n 8001cda { hpcd->Init.dma_enable = 0U; 8001cd4: 687b ldr r3, [r7, #4] 8001cd6: 2200 movs r2, #0 8001cd8: 611a str r2, [r3, #16] } /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8001cda: 687b ldr r3, [r7, #4] 8001cdc: 681b ldr r3, [r3, #0] 8001cde: 4618 mov r0, r3 8001ce0: f004 f99f bl 8006022 /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8001ce4: 687b ldr r3, [r7, #4] 8001ce6: 681b ldr r3, [r3, #0] 8001ce8: 603b str r3, [r7, #0] 8001cea: 687e ldr r6, [r7, #4] 8001cec: 466d mov r5, sp 8001cee: f106 0410 add.w r4, r6, #16 8001cf2: cc0f ldmia r4!, {r0, r1, r2, r3} 8001cf4: c50f stmia r5!, {r0, r1, r2, r3} 8001cf6: cc0f ldmia r4!, {r0, r1, r2, r3} 8001cf8: c50f stmia r5!, {r0, r1, r2, r3} 8001cfa: e894 0003 ldmia.w r4, {r0, r1} 8001cfe: e885 0003 stmia.w r5, {r0, r1} 8001d02: 1d33 adds r3, r6, #4 8001d04: cb0e ldmia r3, {r1, r2, r3} 8001d06: 6838 ldr r0, [r7, #0] 8001d08: f004 f86a bl 8005de0 8001d0c: 4603 mov r3, r0 8001d0e: 2b00 cmp r3, #0 8001d10: d005 beq.n 8001d1e { hpcd->State = HAL_PCD_STATE_ERROR; 8001d12: 687b ldr r3, [r7, #4] 8001d14: 2202 movs r2, #2 8001d16: f883 23bd strb.w r2, [r3, #957] ; 0x3bd return HAL_ERROR; 8001d1a: 2301 movs r3, #1 8001d1c: e0d7 b.n 8001ece } /* Force Device Mode*/ (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); 8001d1e: 687b ldr r3, [r7, #4] 8001d20: 681b ldr r3, [r3, #0] 8001d22: 2100 movs r1, #0 8001d24: 4618 mov r0, r3 8001d26: f004 f98d bl 8006044 /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8001d2a: 2300 movs r3, #0 8001d2c: 73fb strb r3, [r7, #15] 8001d2e: e04a b.n 8001dc6 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8001d30: 7bfa ldrb r2, [r7, #15] 8001d32: 6879 ldr r1, [r7, #4] 8001d34: 4613 mov r3, r2 8001d36: 00db lsls r3, r3, #3 8001d38: 1a9b subs r3, r3, r2 8001d3a: 009b lsls r3, r3, #2 8001d3c: 440b add r3, r1 8001d3e: 333d adds r3, #61 ; 0x3d 8001d40: 2201 movs r2, #1 8001d42: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8001d44: 7bfa ldrb r2, [r7, #15] 8001d46: 6879 ldr r1, [r7, #4] 8001d48: 4613 mov r3, r2 8001d4a: 00db lsls r3, r3, #3 8001d4c: 1a9b subs r3, r3, r2 8001d4e: 009b lsls r3, r3, #2 8001d50: 440b add r3, r1 8001d52: 333c adds r3, #60 ; 0x3c 8001d54: 7bfa ldrb r2, [r7, #15] 8001d56: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 8001d58: 7bfa ldrb r2, [r7, #15] 8001d5a: 7bfb ldrb r3, [r7, #15] 8001d5c: b298 uxth r0, r3 8001d5e: 6879 ldr r1, [r7, #4] 8001d60: 4613 mov r3, r2 8001d62: 00db lsls r3, r3, #3 8001d64: 1a9b subs r3, r3, r2 8001d66: 009b lsls r3, r3, #2 8001d68: 440b add r3, r1 8001d6a: 3342 adds r3, #66 ; 0x42 8001d6c: 4602 mov r2, r0 8001d6e: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 8001d70: 7bfa ldrb r2, [r7, #15] 8001d72: 6879 ldr r1, [r7, #4] 8001d74: 4613 mov r3, r2 8001d76: 00db lsls r3, r3, #3 8001d78: 1a9b subs r3, r3, r2 8001d7a: 009b lsls r3, r3, #2 8001d7c: 440b add r3, r1 8001d7e: 333f adds r3, #63 ; 0x3f 8001d80: 2200 movs r2, #0 8001d82: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8001d84: 7bfa ldrb r2, [r7, #15] 8001d86: 6879 ldr r1, [r7, #4] 8001d88: 4613 mov r3, r2 8001d8a: 00db lsls r3, r3, #3 8001d8c: 1a9b subs r3, r3, r2 8001d8e: 009b lsls r3, r3, #2 8001d90: 440b add r3, r1 8001d92: 3344 adds r3, #68 ; 0x44 8001d94: 2200 movs r2, #0 8001d96: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 8001d98: 7bfa ldrb r2, [r7, #15] 8001d9a: 6879 ldr r1, [r7, #4] 8001d9c: 4613 mov r3, r2 8001d9e: 00db lsls r3, r3, #3 8001da0: 1a9b subs r3, r3, r2 8001da2: 009b lsls r3, r3, #2 8001da4: 440b add r3, r1 8001da6: 3348 adds r3, #72 ; 0x48 8001da8: 2200 movs r2, #0 8001daa: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8001dac: 7bfa ldrb r2, [r7, #15] 8001dae: 6879 ldr r1, [r7, #4] 8001db0: 4613 mov r3, r2 8001db2: 00db lsls r3, r3, #3 8001db4: 1a9b subs r3, r3, r2 8001db6: 009b lsls r3, r3, #2 8001db8: 440b add r3, r1 8001dba: 3350 adds r3, #80 ; 0x50 8001dbc: 2200 movs r2, #0 8001dbe: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8001dc0: 7bfb ldrb r3, [r7, #15] 8001dc2: 3301 adds r3, #1 8001dc4: 73fb strb r3, [r7, #15] 8001dc6: 7bfa ldrb r2, [r7, #15] 8001dc8: 687b ldr r3, [r7, #4] 8001dca: 685b ldr r3, [r3, #4] 8001dcc: 429a cmp r2, r3 8001dce: d3af bcc.n 8001d30 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8001dd0: 2300 movs r3, #0 8001dd2: 73fb strb r3, [r7, #15] 8001dd4: e044 b.n 8001e60 { hpcd->OUT_ep[i].is_in = 0U; 8001dd6: 7bfa ldrb r2, [r7, #15] 8001dd8: 6879 ldr r1, [r7, #4] 8001dda: 4613 mov r3, r2 8001ddc: 00db lsls r3, r3, #3 8001dde: 1a9b subs r3, r3, r2 8001de0: 009b lsls r3, r3, #2 8001de2: 440b add r3, r1 8001de4: f203 13fd addw r3, r3, #509 ; 0x1fd 8001de8: 2200 movs r2, #0 8001dea: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8001dec: 7bfa ldrb r2, [r7, #15] 8001dee: 6879 ldr r1, [r7, #4] 8001df0: 4613 mov r3, r2 8001df2: 00db lsls r3, r3, #3 8001df4: 1a9b subs r3, r3, r2 8001df6: 009b lsls r3, r3, #2 8001df8: 440b add r3, r1 8001dfa: f503 73fe add.w r3, r3, #508 ; 0x1fc 8001dfe: 7bfa ldrb r2, [r7, #15] 8001e00: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8001e02: 7bfa ldrb r2, [r7, #15] 8001e04: 6879 ldr r1, [r7, #4] 8001e06: 4613 mov r3, r2 8001e08: 00db lsls r3, r3, #3 8001e0a: 1a9b subs r3, r3, r2 8001e0c: 009b lsls r3, r3, #2 8001e0e: 440b add r3, r1 8001e10: f203 13ff addw r3, r3, #511 ; 0x1ff 8001e14: 2200 movs r2, #0 8001e16: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8001e18: 7bfa ldrb r2, [r7, #15] 8001e1a: 6879 ldr r1, [r7, #4] 8001e1c: 4613 mov r3, r2 8001e1e: 00db lsls r3, r3, #3 8001e20: 1a9b subs r3, r3, r2 8001e22: 009b lsls r3, r3, #2 8001e24: 440b add r3, r1 8001e26: f503 7301 add.w r3, r3, #516 ; 0x204 8001e2a: 2200 movs r2, #0 8001e2c: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 8001e2e: 7bfa ldrb r2, [r7, #15] 8001e30: 6879 ldr r1, [r7, #4] 8001e32: 4613 mov r3, r2 8001e34: 00db lsls r3, r3, #3 8001e36: 1a9b subs r3, r3, r2 8001e38: 009b lsls r3, r3, #2 8001e3a: 440b add r3, r1 8001e3c: f503 7302 add.w r3, r3, #520 ; 0x208 8001e40: 2200 movs r2, #0 8001e42: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8001e44: 7bfa ldrb r2, [r7, #15] 8001e46: 6879 ldr r1, [r7, #4] 8001e48: 4613 mov r3, r2 8001e4a: 00db lsls r3, r3, #3 8001e4c: 1a9b subs r3, r3, r2 8001e4e: 009b lsls r3, r3, #2 8001e50: 440b add r3, r1 8001e52: f503 7304 add.w r3, r3, #528 ; 0x210 8001e56: 2200 movs r2, #0 8001e58: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8001e5a: 7bfb ldrb r3, [r7, #15] 8001e5c: 3301 adds r3, #1 8001e5e: 73fb strb r3, [r7, #15] 8001e60: 7bfa ldrb r2, [r7, #15] 8001e62: 687b ldr r3, [r7, #4] 8001e64: 685b ldr r3, [r3, #4] 8001e66: 429a cmp r2, r3 8001e68: d3b5 bcc.n 8001dd6 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8001e6a: 687b ldr r3, [r7, #4] 8001e6c: 681b ldr r3, [r3, #0] 8001e6e: 603b str r3, [r7, #0] 8001e70: 687e ldr r6, [r7, #4] 8001e72: 466d mov r5, sp 8001e74: f106 0410 add.w r4, r6, #16 8001e78: cc0f ldmia r4!, {r0, r1, r2, r3} 8001e7a: c50f stmia r5!, {r0, r1, r2, r3} 8001e7c: cc0f ldmia r4!, {r0, r1, r2, r3} 8001e7e: c50f stmia r5!, {r0, r1, r2, r3} 8001e80: e894 0003 ldmia.w r4, {r0, r1} 8001e84: e885 0003 stmia.w r5, {r0, r1} 8001e88: 1d33 adds r3, r6, #4 8001e8a: cb0e ldmia r3, {r1, r2, r3} 8001e8c: 6838 ldr r0, [r7, #0] 8001e8e: f004 f925 bl 80060dc 8001e92: 4603 mov r3, r0 8001e94: 2b00 cmp r3, #0 8001e96: d005 beq.n 8001ea4 { hpcd->State = HAL_PCD_STATE_ERROR; 8001e98: 687b ldr r3, [r7, #4] 8001e9a: 2202 movs r2, #2 8001e9c: f883 23bd strb.w r2, [r3, #957] ; 0x3bd return HAL_ERROR; 8001ea0: 2301 movs r3, #1 8001ea2: e014 b.n 8001ece } hpcd->USB_Address = 0U; 8001ea4: 687b ldr r3, [r7, #4] 8001ea6: 2200 movs r2, #0 8001ea8: f883 2038 strb.w r2, [r3, #56] ; 0x38 hpcd->State = HAL_PCD_STATE_READY; 8001eac: 687b ldr r3, [r7, #4] 8001eae: 2201 movs r2, #1 8001eb0: f883 23bd strb.w r2, [r3, #957] ; 0x3bd /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8001eb4: 687b ldr r3, [r7, #4] 8001eb6: 6a5b ldr r3, [r3, #36] ; 0x24 8001eb8: 2b01 cmp r3, #1 8001eba: d102 bne.n 8001ec2 { (void)HAL_PCDEx_ActivateLPM(hpcd); 8001ebc: 6878 ldr r0, [r7, #4] 8001ebe: f001 f885 bl 8002fcc } (void)USB_DevDisconnect(hpcd->Instance); 8001ec2: 687b ldr r3, [r7, #4] 8001ec4: 681b ldr r3, [r3, #0] 8001ec6: 4618 mov r0, r3 8001ec8: f005 f9bd bl 8007246 return HAL_OK; 8001ecc: 2300 movs r3, #0 } 8001ece: 4618 mov r0, r3 8001ed0: 3714 adds r7, #20 8001ed2: 46bd mov sp, r7 8001ed4: bdf0 pop {r4, r5, r6, r7, pc} 08001ed6 : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 8001ed6: b580 push {r7, lr} 8001ed8: b084 sub sp, #16 8001eda: af00 add r7, sp, #0 8001edc: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8001ede: 687b ldr r3, [r7, #4] 8001ee0: 681b ldr r3, [r3, #0] 8001ee2: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 8001ee4: 687b ldr r3, [r7, #4] 8001ee6: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 8001eea: 2b01 cmp r3, #1 8001eec: d101 bne.n 8001ef2 8001eee: 2302 movs r3, #2 8001ef0: e020 b.n 8001f34 8001ef2: 687b ldr r3, [r7, #4] 8001ef4: 2201 movs r2, #1 8001ef6: f883 23bc strb.w r2, [r3, #956] ; 0x3bc if ((hpcd->Init.battery_charging_enable == 1U) && 8001efa: 687b ldr r3, [r7, #4] 8001efc: 6a9b ldr r3, [r3, #40] ; 0x28 8001efe: 2b01 cmp r3, #1 8001f00: d109 bne.n 8001f16 (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) 8001f02: 687b ldr r3, [r7, #4] 8001f04: 699b ldr r3, [r3, #24] if ((hpcd->Init.battery_charging_enable == 1U) && 8001f06: 2b01 cmp r3, #1 8001f08: d005 beq.n 8001f16 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8001f0a: 68fb ldr r3, [r7, #12] 8001f0c: 6b9b ldr r3, [r3, #56] ; 0x38 8001f0e: f443 3280 orr.w r2, r3, #65536 ; 0x10000 8001f12: 68fb ldr r3, [r7, #12] 8001f14: 639a str r2, [r3, #56] ; 0x38 } __HAL_PCD_ENABLE(hpcd); 8001f16: 687b ldr r3, [r7, #4] 8001f18: 681b ldr r3, [r3, #0] 8001f1a: 4618 mov r0, r3 8001f1c: f004 f870 bl 8006000 (void)USB_DevConnect(hpcd->Instance); 8001f20: 687b ldr r3, [r7, #4] 8001f22: 681b ldr r3, [r3, #0] 8001f24: 4618 mov r0, r3 8001f26: f005 f96d bl 8007204 __HAL_UNLOCK(hpcd); 8001f2a: 687b ldr r3, [r7, #4] 8001f2c: 2200 movs r2, #0 8001f2e: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 8001f32: 2300 movs r3, #0 } 8001f34: 4618 mov r0, r3 8001f36: 3710 adds r7, #16 8001f38: 46bd mov sp, r7 8001f3a: bd80 pop {r7, pc} 08001f3c : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 8001f3c: b590 push {r4, r7, lr} 8001f3e: b08d sub sp, #52 ; 0x34 8001f40: af00 add r7, sp, #0 8001f42: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8001f44: 687b ldr r3, [r7, #4] 8001f46: 681b ldr r3, [r3, #0] 8001f48: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 8001f4a: 6a3b ldr r3, [r7, #32] 8001f4c: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t temp; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 8001f4e: 687b ldr r3, [r7, #4] 8001f50: 681b ldr r3, [r3, #0] 8001f52: 4618 mov r0, r3 8001f54: f005 fa2b bl 80073ae 8001f58: 4603 mov r3, r0 8001f5a: 2b00 cmp r3, #0 8001f5c: f040 83be bne.w 80026dc { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 8001f60: 687b ldr r3, [r7, #4] 8001f62: 681b ldr r3, [r3, #0] 8001f64: 4618 mov r0, r3 8001f66: f005 f98f bl 8007288 8001f6a: 4603 mov r3, r0 8001f6c: 2b00 cmp r3, #0 8001f6e: f000 83b4 beq.w 80026da { return; } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 8001f72: 687b ldr r3, [r7, #4] 8001f74: 681b ldr r3, [r3, #0] 8001f76: 4618 mov r0, r3 8001f78: f005 f986 bl 8007288 8001f7c: 4603 mov r3, r0 8001f7e: f003 0302 and.w r3, r3, #2 8001f82: 2b02 cmp r3, #2 8001f84: d107 bne.n 8001f96 { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 8001f86: 687b ldr r3, [r7, #4] 8001f88: 681b ldr r3, [r3, #0] 8001f8a: 695a ldr r2, [r3, #20] 8001f8c: 687b ldr r3, [r7, #4] 8001f8e: 681b ldr r3, [r3, #0] 8001f90: f002 0202 and.w r2, r2, #2 8001f94: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 8001f96: 687b ldr r3, [r7, #4] 8001f98: 681b ldr r3, [r3, #0] 8001f9a: 4618 mov r0, r3 8001f9c: f005 f974 bl 8007288 8001fa0: 4603 mov r3, r0 8001fa2: f003 0310 and.w r3, r3, #16 8001fa6: 2b10 cmp r3, #16 8001fa8: d161 bne.n 800206e { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8001faa: 687b ldr r3, [r7, #4] 8001fac: 681b ldr r3, [r3, #0] 8001fae: 699a ldr r2, [r3, #24] 8001fb0: 687b ldr r3, [r7, #4] 8001fb2: 681b ldr r3, [r3, #0] 8001fb4: f022 0210 bic.w r2, r2, #16 8001fb8: 619a str r2, [r3, #24] temp = USBx->GRXSTSP; 8001fba: 6a3b ldr r3, [r7, #32] 8001fbc: 6a1b ldr r3, [r3, #32] 8001fbe: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; 8001fc0: 69bb ldr r3, [r7, #24] 8001fc2: f003 020f and.w r2, r3, #15 8001fc6: 4613 mov r3, r2 8001fc8: 00db lsls r3, r3, #3 8001fca: 1a9b subs r3, r3, r2 8001fcc: 009b lsls r3, r3, #2 8001fce: f503 73fc add.w r3, r3, #504 ; 0x1f8 8001fd2: 687a ldr r2, [r7, #4] 8001fd4: 4413 add r3, r2 8001fd6: 3304 adds r3, #4 8001fd8: 617b str r3, [r7, #20] if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 8001fda: 69bb ldr r3, [r7, #24] 8001fdc: 0c5b lsrs r3, r3, #17 8001fde: f003 030f and.w r3, r3, #15 8001fe2: 2b02 cmp r3, #2 8001fe4: d124 bne.n 8002030 { if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) 8001fe6: 69ba ldr r2, [r7, #24] 8001fe8: f647 73f0 movw r3, #32752 ; 0x7ff0 8001fec: 4013 ands r3, r2 8001fee: 2b00 cmp r3, #0 8001ff0: d035 beq.n 800205e { (void)USB_ReadPacket(USBx, ep->xfer_buff, 8001ff2: 697b ldr r3, [r7, #20] 8001ff4: 68d9 ldr r1, [r3, #12] (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); 8001ff6: 69bb ldr r3, [r7, #24] 8001ff8: 091b lsrs r3, r3, #4 8001ffa: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 8001ffc: f3c3 030a ubfx r3, r3, #0, #11 8002000: b29b uxth r3, r3 8002002: 461a mov r2, r3 8002004: 6a38 ldr r0, [r7, #32] 8002006: f004 ffab bl 8006f60 ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; 800200a: 697b ldr r3, [r7, #20] 800200c: 68da ldr r2, [r3, #12] 800200e: 69bb ldr r3, [r7, #24] 8002010: 091b lsrs r3, r3, #4 8002012: f3c3 030a ubfx r3, r3, #0, #11 8002016: 441a add r2, r3 8002018: 697b ldr r3, [r7, #20] 800201a: 60da str r2, [r3, #12] ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; 800201c: 697b ldr r3, [r7, #20] 800201e: 699a ldr r2, [r3, #24] 8002020: 69bb ldr r3, [r7, #24] 8002022: 091b lsrs r3, r3, #4 8002024: f3c3 030a ubfx r3, r3, #0, #11 8002028: 441a add r2, r3 800202a: 697b ldr r3, [r7, #20] 800202c: 619a str r2, [r3, #24] 800202e: e016 b.n 800205e } } else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 8002030: 69bb ldr r3, [r7, #24] 8002032: 0c5b lsrs r3, r3, #17 8002034: f003 030f and.w r3, r3, #15 8002038: 2b06 cmp r3, #6 800203a: d110 bne.n 800205e { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 800203c: 687b ldr r3, [r7, #4] 800203e: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002042: 2208 movs r2, #8 8002044: 4619 mov r1, r3 8002046: 6a38 ldr r0, [r7, #32] 8002048: f004 ff8a bl 8006f60 ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; 800204c: 697b ldr r3, [r7, #20] 800204e: 699a ldr r2, [r3, #24] 8002050: 69bb ldr r3, [r7, #24] 8002052: 091b lsrs r3, r3, #4 8002054: f3c3 030a ubfx r3, r3, #0, #11 8002058: 441a add r2, r3 800205a: 697b ldr r3, [r7, #20] 800205c: 619a str r2, [r3, #24] else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 800205e: 687b ldr r3, [r7, #4] 8002060: 681b ldr r3, [r3, #0] 8002062: 699a ldr r2, [r3, #24] 8002064: 687b ldr r3, [r7, #4] 8002066: 681b ldr r3, [r3, #0] 8002068: f042 0210 orr.w r2, r2, #16 800206c: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 800206e: 687b ldr r3, [r7, #4] 8002070: 681b ldr r3, [r3, #0] 8002072: 4618 mov r0, r3 8002074: f005 f908 bl 8007288 8002078: 4603 mov r3, r0 800207a: f403 2300 and.w r3, r3, #524288 ; 0x80000 800207e: f5b3 2f00 cmp.w r3, #524288 ; 0x80000 8002082: d16e bne.n 8002162 { epnum = 0U; 8002084: 2300 movs r3, #0 8002086: 627b str r3, [r7, #36] ; 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 8002088: 687b ldr r3, [r7, #4] 800208a: 681b ldr r3, [r3, #0] 800208c: 4618 mov r0, r3 800208e: f005 f90e bl 80072ae 8002092: 62b8 str r0, [r7, #40] ; 0x28 while (ep_intr != 0U) 8002094: e062 b.n 800215c { if ((ep_intr & 0x1U) != 0U) 8002096: 6abb ldr r3, [r7, #40] ; 0x28 8002098: f003 0301 and.w r3, r3, #1 800209c: 2b00 cmp r3, #0 800209e: d057 beq.n 8002150 { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 80020a0: 687b ldr r3, [r7, #4] 80020a2: 681b ldr r3, [r3, #0] 80020a4: 6a7a ldr r2, [r7, #36] ; 0x24 80020a6: b2d2 uxtb r2, r2 80020a8: 4611 mov r1, r2 80020aa: 4618 mov r0, r3 80020ac: f005 f933 bl 8007316 80020b0: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 80020b2: 693b ldr r3, [r7, #16] 80020b4: f003 0301 and.w r3, r3, #1 80020b8: 2b00 cmp r3, #0 80020ba: d00c beq.n 80020d6 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 80020bc: 6a7b ldr r3, [r7, #36] ; 0x24 80020be: 015a lsls r2, r3, #5 80020c0: 69fb ldr r3, [r7, #28] 80020c2: 4413 add r3, r2 80020c4: f503 6330 add.w r3, r3, #2816 ; 0xb00 80020c8: 461a mov r2, r3 80020ca: 2301 movs r3, #1 80020cc: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 80020ce: 6a79 ldr r1, [r7, #36] ; 0x24 80020d0: 6878 ldr r0, [r7, #4] 80020d2: f000 fdd1 bl 8002c78 } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 80020d6: 693b ldr r3, [r7, #16] 80020d8: f003 0308 and.w r3, r3, #8 80020dc: 2b00 cmp r3, #0 80020de: d00c beq.n 80020fa { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 80020e0: 6a7b ldr r3, [r7, #36] ; 0x24 80020e2: 015a lsls r2, r3, #5 80020e4: 69fb ldr r3, [r7, #28] 80020e6: 4413 add r3, r2 80020e8: f503 6330 add.w r3, r3, #2816 ; 0xb00 80020ec: 461a mov r2, r3 80020ee: 2308 movs r3, #8 80020f0: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 80020f2: 6a79 ldr r1, [r7, #36] ; 0x24 80020f4: 6878 ldr r0, [r7, #4] 80020f6: f000 fecb bl 8002e90 } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 80020fa: 693b ldr r3, [r7, #16] 80020fc: f003 0310 and.w r3, r3, #16 8002100: 2b00 cmp r3, #0 8002102: d008 beq.n 8002116 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 8002104: 6a7b ldr r3, [r7, #36] ; 0x24 8002106: 015a lsls r2, r3, #5 8002108: 69fb ldr r3, [r7, #28] 800210a: 4413 add r3, r2 800210c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002110: 461a mov r2, r3 8002112: 2310 movs r3, #16 8002114: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8002116: 693b ldr r3, [r7, #16] 8002118: f003 0320 and.w r3, r3, #32 800211c: 2b00 cmp r3, #0 800211e: d008 beq.n 8002132 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8002120: 6a7b ldr r3, [r7, #36] ; 0x24 8002122: 015a lsls r2, r3, #5 8002124: 69fb ldr r3, [r7, #28] 8002126: 4413 add r3, r2 8002128: f503 6330 add.w r3, r3, #2816 ; 0xb00 800212c: 461a mov r2, r3 800212e: 2320 movs r3, #32 8002130: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 8002132: 693b ldr r3, [r7, #16] 8002134: f403 5300 and.w r3, r3, #8192 ; 0x2000 8002138: 2b00 cmp r3, #0 800213a: d009 beq.n 8002150 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 800213c: 6a7b ldr r3, [r7, #36] ; 0x24 800213e: 015a lsls r2, r3, #5 8002140: 69fb ldr r3, [r7, #28] 8002142: 4413 add r3, r2 8002144: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002148: 461a mov r2, r3 800214a: f44f 5300 mov.w r3, #8192 ; 0x2000 800214e: 6093 str r3, [r2, #8] } } epnum++; 8002150: 6a7b ldr r3, [r7, #36] ; 0x24 8002152: 3301 adds r3, #1 8002154: 627b str r3, [r7, #36] ; 0x24 ep_intr >>= 1U; 8002156: 6abb ldr r3, [r7, #40] ; 0x28 8002158: 085b lsrs r3, r3, #1 800215a: 62bb str r3, [r7, #40] ; 0x28 while (ep_intr != 0U) 800215c: 6abb ldr r3, [r7, #40] ; 0x28 800215e: 2b00 cmp r3, #0 8002160: d199 bne.n 8002096 } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 8002162: 687b ldr r3, [r7, #4] 8002164: 681b ldr r3, [r3, #0] 8002166: 4618 mov r0, r3 8002168: f005 f88e bl 8007288 800216c: 4603 mov r3, r0 800216e: f403 2380 and.w r3, r3, #262144 ; 0x40000 8002172: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 8002176: f040 80c4 bne.w 8002302 { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 800217a: 687b ldr r3, [r7, #4] 800217c: 681b ldr r3, [r3, #0] 800217e: 4618 mov r0, r3 8002180: f005 f8af bl 80072e2 8002184: 62b8 str r0, [r7, #40] ; 0x28 epnum = 0U; 8002186: 2300 movs r3, #0 8002188: 627b str r3, [r7, #36] ; 0x24 while (ep_intr != 0U) 800218a: e0b6 b.n 80022fa { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 800218c: 6abb ldr r3, [r7, #40] ; 0x28 800218e: f003 0301 and.w r3, r3, #1 8002192: 2b00 cmp r3, #0 8002194: f000 80ab beq.w 80022ee { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8002198: 687b ldr r3, [r7, #4] 800219a: 681b ldr r3, [r3, #0] 800219c: 6a7a ldr r2, [r7, #36] ; 0x24 800219e: b2d2 uxtb r2, r2 80021a0: 4611 mov r1, r2 80021a2: 4618 mov r0, r3 80021a4: f005 f8d5 bl 8007352 80021a8: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 80021aa: 693b ldr r3, [r7, #16] 80021ac: f003 0301 and.w r3, r3, #1 80021b0: 2b00 cmp r3, #0 80021b2: d057 beq.n 8002264 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 80021b4: 6a7b ldr r3, [r7, #36] ; 0x24 80021b6: f003 030f and.w r3, r3, #15 80021ba: 2201 movs r2, #1 80021bc: fa02 f303 lsl.w r3, r2, r3 80021c0: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 80021c2: 69fb ldr r3, [r7, #28] 80021c4: f503 6300 add.w r3, r3, #2048 ; 0x800 80021c8: 6b5a ldr r2, [r3, #52] ; 0x34 80021ca: 68fb ldr r3, [r7, #12] 80021cc: 43db mvns r3, r3 80021ce: 69f9 ldr r1, [r7, #28] 80021d0: f501 6100 add.w r1, r1, #2048 ; 0x800 80021d4: 4013 ands r3, r2 80021d6: 634b str r3, [r1, #52] ; 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 80021d8: 6a7b ldr r3, [r7, #36] ; 0x24 80021da: 015a lsls r2, r3, #5 80021dc: 69fb ldr r3, [r7, #28] 80021de: 4413 add r3, r2 80021e0: f503 6310 add.w r3, r3, #2304 ; 0x900 80021e4: 461a mov r2, r3 80021e6: 2301 movs r3, #1 80021e8: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 80021ea: 687b ldr r3, [r7, #4] 80021ec: 691b ldr r3, [r3, #16] 80021ee: 2b01 cmp r3, #1 80021f0: d132 bne.n 8002258 { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 80021f2: 6879 ldr r1, [r7, #4] 80021f4: 6a7a ldr r2, [r7, #36] ; 0x24 80021f6: 4613 mov r3, r2 80021f8: 00db lsls r3, r3, #3 80021fa: 1a9b subs r3, r3, r2 80021fc: 009b lsls r3, r3, #2 80021fe: 440b add r3, r1 8002200: 3348 adds r3, #72 ; 0x48 8002202: 6819 ldr r1, [r3, #0] 8002204: 6878 ldr r0, [r7, #4] 8002206: 6a7a ldr r2, [r7, #36] ; 0x24 8002208: 4613 mov r3, r2 800220a: 00db lsls r3, r3, #3 800220c: 1a9b subs r3, r3, r2 800220e: 009b lsls r3, r3, #2 8002210: 4403 add r3, r0 8002212: 3344 adds r3, #68 ; 0x44 8002214: 681b ldr r3, [r3, #0] 8002216: 4419 add r1, r3 8002218: 6878 ldr r0, [r7, #4] 800221a: 6a7a ldr r2, [r7, #36] ; 0x24 800221c: 4613 mov r3, r2 800221e: 00db lsls r3, r3, #3 8002220: 1a9b subs r3, r3, r2 8002222: 009b lsls r3, r3, #2 8002224: 4403 add r3, r0 8002226: 3348 adds r3, #72 ; 0x48 8002228: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 800222a: 6a7b ldr r3, [r7, #36] ; 0x24 800222c: 2b00 cmp r3, #0 800222e: d113 bne.n 8002258 8002230: 6879 ldr r1, [r7, #4] 8002232: 6a7a ldr r2, [r7, #36] ; 0x24 8002234: 4613 mov r3, r2 8002236: 00db lsls r3, r3, #3 8002238: 1a9b subs r3, r3, r2 800223a: 009b lsls r3, r3, #2 800223c: 440b add r3, r1 800223e: 3350 adds r3, #80 ; 0x50 8002240: 681b ldr r3, [r3, #0] 8002242: 2b00 cmp r3, #0 8002244: d108 bne.n 8002258 { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8002246: 687b ldr r3, [r7, #4] 8002248: 6818 ldr r0, [r3, #0] 800224a: 687b ldr r3, [r7, #4] 800224c: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002250: 461a mov r2, r3 8002252: 2101 movs r1, #1 8002254: f005 f8de bl 8007414 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 8002258: 6a7b ldr r3, [r7, #36] ; 0x24 800225a: b2db uxtb r3, r3 800225c: 4619 mov r1, r3 800225e: 6878 ldr r0, [r7, #4] 8002260: f007 f89f bl 80093a2 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 8002264: 693b ldr r3, [r7, #16] 8002266: f003 0308 and.w r3, r3, #8 800226a: 2b00 cmp r3, #0 800226c: d008 beq.n 8002280 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 800226e: 6a7b ldr r3, [r7, #36] ; 0x24 8002270: 015a lsls r2, r3, #5 8002272: 69fb ldr r3, [r7, #28] 8002274: 4413 add r3, r2 8002276: f503 6310 add.w r3, r3, #2304 ; 0x900 800227a: 461a mov r2, r3 800227c: 2308 movs r3, #8 800227e: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 8002280: 693b ldr r3, [r7, #16] 8002282: f003 0310 and.w r3, r3, #16 8002286: 2b00 cmp r3, #0 8002288: d008 beq.n 800229c { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 800228a: 6a7b ldr r3, [r7, #36] ; 0x24 800228c: 015a lsls r2, r3, #5 800228e: 69fb ldr r3, [r7, #28] 8002290: 4413 add r3, r2 8002292: f503 6310 add.w r3, r3, #2304 ; 0x900 8002296: 461a mov r2, r3 8002298: 2310 movs r3, #16 800229a: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 800229c: 693b ldr r3, [r7, #16] 800229e: f003 0340 and.w r3, r3, #64 ; 0x40 80022a2: 2b00 cmp r3, #0 80022a4: d008 beq.n 80022b8 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 80022a6: 6a7b ldr r3, [r7, #36] ; 0x24 80022a8: 015a lsls r2, r3, #5 80022aa: 69fb ldr r3, [r7, #28] 80022ac: 4413 add r3, r2 80022ae: f503 6310 add.w r3, r3, #2304 ; 0x900 80022b2: 461a mov r2, r3 80022b4: 2340 movs r3, #64 ; 0x40 80022b6: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 80022b8: 693b ldr r3, [r7, #16] 80022ba: f003 0302 and.w r3, r3, #2 80022be: 2b00 cmp r3, #0 80022c0: d00c beq.n 80022dc { (void)USB_FlushTxFifo(USBx, epnum); 80022c2: 6a79 ldr r1, [r7, #36] ; 0x24 80022c4: 6a38 ldr r0, [r7, #32] 80022c6: f004 f867 bl 8006398 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 80022ca: 6a7b ldr r3, [r7, #36] ; 0x24 80022cc: 015a lsls r2, r3, #5 80022ce: 69fb ldr r3, [r7, #28] 80022d0: 4413 add r3, r2 80022d2: f503 6310 add.w r3, r3, #2304 ; 0x900 80022d6: 461a mov r2, r3 80022d8: 2302 movs r3, #2 80022da: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 80022dc: 693b ldr r3, [r7, #16] 80022de: f003 0380 and.w r3, r3, #128 ; 0x80 80022e2: 2b00 cmp r3, #0 80022e4: d003 beq.n 80022ee { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 80022e6: 6a79 ldr r1, [r7, #36] ; 0x24 80022e8: 6878 ldr r0, [r7, #4] 80022ea: f000 fc38 bl 8002b5e } } epnum++; 80022ee: 6a7b ldr r3, [r7, #36] ; 0x24 80022f0: 3301 adds r3, #1 80022f2: 627b str r3, [r7, #36] ; 0x24 ep_intr >>= 1U; 80022f4: 6abb ldr r3, [r7, #40] ; 0x28 80022f6: 085b lsrs r3, r3, #1 80022f8: 62bb str r3, [r7, #40] ; 0x28 while (ep_intr != 0U) 80022fa: 6abb ldr r3, [r7, #40] ; 0x28 80022fc: 2b00 cmp r3, #0 80022fe: f47f af45 bne.w 800218c } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 8002302: 687b ldr r3, [r7, #4] 8002304: 681b ldr r3, [r3, #0] 8002306: 4618 mov r0, r3 8002308: f004 ffbe bl 8007288 800230c: 4603 mov r3, r0 800230e: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8002312: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8002316: d122 bne.n 800235e { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 8002318: 69fb ldr r3, [r7, #28] 800231a: f503 6300 add.w r3, r3, #2048 ; 0x800 800231e: 685b ldr r3, [r3, #4] 8002320: 69fa ldr r2, [r7, #28] 8002322: f502 6200 add.w r2, r2, #2048 ; 0x800 8002326: f023 0301 bic.w r3, r3, #1 800232a: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 800232c: 687b ldr r3, [r7, #4] 800232e: f893 33f4 ldrb.w r3, [r3, #1012] ; 0x3f4 8002332: 2b01 cmp r3, #1 8002334: d108 bne.n 8002348 { hpcd->LPM_State = LPM_L0; 8002336: 687b ldr r3, [r7, #4] 8002338: 2200 movs r2, #0 800233a: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 800233e: 2100 movs r1, #0 8002340: 6878 ldr r0, [r7, #4] 8002342: f000 fe67 bl 8003014 8002346: e002 b.n 800234e else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 8002348: 6878 ldr r0, [r7, #4] 800234a: f007 f8a1 bl 8009490 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 800234e: 687b ldr r3, [r7, #4] 8002350: 681b ldr r3, [r3, #0] 8002352: 695a ldr r2, [r3, #20] 8002354: 687b ldr r3, [r7, #4] 8002356: 681b ldr r3, [r3, #0] 8002358: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000 800235c: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 800235e: 687b ldr r3, [r7, #4] 8002360: 681b ldr r3, [r3, #0] 8002362: 4618 mov r0, r3 8002364: f004 ff90 bl 8007288 8002368: 4603 mov r3, r0 800236a: f403 6300 and.w r3, r3, #2048 ; 0x800 800236e: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8002372: d112 bne.n 800239a { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 8002374: 69fb ldr r3, [r7, #28] 8002376: f503 6300 add.w r3, r3, #2048 ; 0x800 800237a: 689b ldr r3, [r3, #8] 800237c: f003 0301 and.w r3, r3, #1 8002380: 2b01 cmp r3, #1 8002382: d102 bne.n 800238a { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8002384: 6878 ldr r0, [r7, #4] 8002386: f007 f85d bl 8009444 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 800238a: 687b ldr r3, [r7, #4] 800238c: 681b ldr r3, [r3, #0] 800238e: 695a ldr r2, [r3, #20] 8002390: 687b ldr r3, [r7, #4] 8002392: 681b ldr r3, [r3, #0] 8002394: f402 6200 and.w r2, r2, #2048 ; 0x800 8002398: 615a str r2, [r3, #20] } /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 800239a: 687b ldr r3, [r7, #4] 800239c: 681b ldr r3, [r3, #0] 800239e: 4618 mov r0, r3 80023a0: f004 ff72 bl 8007288 80023a4: 4603 mov r3, r0 80023a6: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80023aa: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 80023ae: d121 bne.n 80023f4 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 80023b0: 687b ldr r3, [r7, #4] 80023b2: 681b ldr r3, [r3, #0] 80023b4: 695a ldr r2, [r3, #20] 80023b6: 687b ldr r3, [r7, #4] 80023b8: 681b ldr r3, [r3, #0] 80023ba: f002 6200 and.w r2, r2, #134217728 ; 0x8000000 80023be: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 80023c0: 687b ldr r3, [r7, #4] 80023c2: f893 33f4 ldrb.w r3, [r3, #1012] ; 0x3f4 80023c6: 2b00 cmp r3, #0 80023c8: d111 bne.n 80023ee { hpcd->LPM_State = LPM_L1; 80023ca: 687b ldr r3, [r7, #4] 80023cc: 2201 movs r2, #1 80023ce: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4 hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 80023d2: 687b ldr r3, [r7, #4] 80023d4: 681b ldr r3, [r3, #0] 80023d6: 6d5b ldr r3, [r3, #84] ; 0x54 80023d8: 089b lsrs r3, r3, #2 80023da: f003 020f and.w r2, r3, #15 80023de: 687b ldr r3, [r7, #4] 80023e0: f8c3 23f8 str.w r2, [r3, #1016] ; 0x3f8 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 80023e4: 2101 movs r1, #1 80023e6: 6878 ldr r0, [r7, #4] 80023e8: f000 fe14 bl 8003014 80023ec: e002 b.n 80023f4 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 80023ee: 6878 ldr r0, [r7, #4] 80023f0: f007 f828 bl 8009444 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 80023f4: 687b ldr r3, [r7, #4] 80023f6: 681b ldr r3, [r3, #0] 80023f8: 4618 mov r0, r3 80023fa: f004 ff45 bl 8007288 80023fe: 4603 mov r3, r0 8002400: f403 5380 and.w r3, r3, #4096 ; 0x1000 8002404: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8002408: f040 80b7 bne.w 800257a { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 800240c: 69fb ldr r3, [r7, #28] 800240e: f503 6300 add.w r3, r3, #2048 ; 0x800 8002412: 685b ldr r3, [r3, #4] 8002414: 69fa ldr r2, [r7, #28] 8002416: f502 6200 add.w r2, r2, #2048 ; 0x800 800241a: f023 0301 bic.w r3, r3, #1 800241e: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 8002420: 687b ldr r3, [r7, #4] 8002422: 681b ldr r3, [r3, #0] 8002424: 2110 movs r1, #16 8002426: 4618 mov r0, r3 8002428: f003 ffb6 bl 8006398 for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800242c: 2300 movs r3, #0 800242e: 62fb str r3, [r7, #44] ; 0x2c 8002430: e046 b.n 80024c0 { USBx_INEP(i)->DIEPINT = 0xFB7FU; 8002432: 6afb ldr r3, [r7, #44] ; 0x2c 8002434: 015a lsls r2, r3, #5 8002436: 69fb ldr r3, [r7, #28] 8002438: 4413 add r3, r2 800243a: f503 6310 add.w r3, r3, #2304 ; 0x900 800243e: 461a mov r2, r3 8002440: f64f 337f movw r3, #64383 ; 0xfb7f 8002444: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8002446: 6afb ldr r3, [r7, #44] ; 0x2c 8002448: 015a lsls r2, r3, #5 800244a: 69fb ldr r3, [r7, #28] 800244c: 4413 add r3, r2 800244e: f503 6310 add.w r3, r3, #2304 ; 0x900 8002452: 681b ldr r3, [r3, #0] 8002454: 6afa ldr r2, [r7, #44] ; 0x2c 8002456: 0151 lsls r1, r2, #5 8002458: 69fa ldr r2, [r7, #28] 800245a: 440a add r2, r1 800245c: f502 6210 add.w r2, r2, #2304 ; 0x900 8002460: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 8002464: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8002466: 6afb ldr r3, [r7, #44] ; 0x2c 8002468: 015a lsls r2, r3, #5 800246a: 69fb ldr r3, [r7, #28] 800246c: 4413 add r3, r2 800246e: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002472: 461a mov r2, r3 8002474: f64f 337f movw r3, #64383 ; 0xfb7f 8002478: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 800247a: 6afb ldr r3, [r7, #44] ; 0x2c 800247c: 015a lsls r2, r3, #5 800247e: 69fb ldr r3, [r7, #28] 8002480: 4413 add r3, r2 8002482: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002486: 681b ldr r3, [r3, #0] 8002488: 6afa ldr r2, [r7, #44] ; 0x2c 800248a: 0151 lsls r1, r2, #5 800248c: 69fa ldr r2, [r7, #28] 800248e: 440a add r2, r1 8002490: f502 6230 add.w r2, r2, #2816 ; 0xb00 8002494: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 8002498: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 800249a: 6afb ldr r3, [r7, #44] ; 0x2c 800249c: 015a lsls r2, r3, #5 800249e: 69fb ldr r3, [r7, #28] 80024a0: 4413 add r3, r2 80024a2: f503 6330 add.w r3, r3, #2816 ; 0xb00 80024a6: 681b ldr r3, [r3, #0] 80024a8: 6afa ldr r2, [r7, #44] ; 0x2c 80024aa: 0151 lsls r1, r2, #5 80024ac: 69fa ldr r2, [r7, #28] 80024ae: 440a add r2, r1 80024b0: f502 6230 add.w r2, r2, #2816 ; 0xb00 80024b4: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 80024b8: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80024ba: 6afb ldr r3, [r7, #44] ; 0x2c 80024bc: 3301 adds r3, #1 80024be: 62fb str r3, [r7, #44] ; 0x2c 80024c0: 687b ldr r3, [r7, #4] 80024c2: 685b ldr r3, [r3, #4] 80024c4: 6afa ldr r2, [r7, #44] ; 0x2c 80024c6: 429a cmp r2, r3 80024c8: d3b3 bcc.n 8002432 } USBx_DEVICE->DAINTMSK |= 0x10001U; 80024ca: 69fb ldr r3, [r7, #28] 80024cc: f503 6300 add.w r3, r3, #2048 ; 0x800 80024d0: 69db ldr r3, [r3, #28] 80024d2: 69fa ldr r2, [r7, #28] 80024d4: f502 6200 add.w r2, r2, #2048 ; 0x800 80024d8: f043 1301 orr.w r3, r3, #65537 ; 0x10001 80024dc: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 80024de: 687b ldr r3, [r7, #4] 80024e0: 6b1b ldr r3, [r3, #48] ; 0x30 80024e2: 2b00 cmp r3, #0 80024e4: d016 beq.n 8002514 { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 80024e6: 69fb ldr r3, [r7, #28] 80024e8: f503 6300 add.w r3, r3, #2048 ; 0x800 80024ec: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80024f0: 69fa ldr r2, [r7, #28] 80024f2: f502 6200 add.w r2, r2, #2048 ; 0x800 80024f6: f043 030b orr.w r3, r3, #11 80024fa: f8c2 3084 str.w r3, [r2, #132] ; 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 80024fe: 69fb ldr r3, [r7, #28] 8002500: f503 6300 add.w r3, r3, #2048 ; 0x800 8002504: 6c5b ldr r3, [r3, #68] ; 0x44 8002506: 69fa ldr r2, [r7, #28] 8002508: f502 6200 add.w r2, r2, #2048 ; 0x800 800250c: f043 030b orr.w r3, r3, #11 8002510: 6453 str r3, [r2, #68] ; 0x44 8002512: e015 b.n 8002540 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 8002514: 69fb ldr r3, [r7, #28] 8002516: f503 6300 add.w r3, r3, #2048 ; 0x800 800251a: 695a ldr r2, [r3, #20] 800251c: 69fb ldr r3, [r7, #28] 800251e: f503 6300 add.w r3, r3, #2048 ; 0x800 8002522: 4619 mov r1, r3 8002524: f242 032b movw r3, #8235 ; 0x202b 8002528: 4313 orrs r3, r2 800252a: 614b str r3, [r1, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 800252c: 69fb ldr r3, [r7, #28] 800252e: f503 6300 add.w r3, r3, #2048 ; 0x800 8002532: 691b ldr r3, [r3, #16] 8002534: 69fa ldr r2, [r7, #28] 8002536: f502 6200 add.w r2, r2, #2048 ; 0x800 800253a: f043 030b orr.w r3, r3, #11 800253e: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 8002540: 69fb ldr r3, [r7, #28] 8002542: f503 6300 add.w r3, r3, #2048 ; 0x800 8002546: 681b ldr r3, [r3, #0] 8002548: 69fa ldr r2, [r7, #28] 800254a: f502 6200 add.w r2, r2, #2048 ; 0x800 800254e: f423 63fe bic.w r3, r3, #2032 ; 0x7f0 8002552: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8002554: 687b ldr r3, [r7, #4] 8002556: 6818 ldr r0, [r3, #0] 8002558: 687b ldr r3, [r7, #4] 800255a: 691b ldr r3, [r3, #16] 800255c: b2d9 uxtb r1, r3 (uint8_t *)hpcd->Setup); 800255e: 687b ldr r3, [r7, #4] 8002560: f503 7371 add.w r3, r3, #964 ; 0x3c4 (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8002564: 461a mov r2, r3 8002566: f004 ff55 bl 8007414 __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 800256a: 687b ldr r3, [r7, #4] 800256c: 681b ldr r3, [r3, #0] 800256e: 695a ldr r2, [r3, #20] 8002570: 687b ldr r3, [r7, #4] 8002572: 681b ldr r3, [r3, #0] 8002574: f402 5280 and.w r2, r2, #4096 ; 0x1000 8002578: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 800257a: 687b ldr r3, [r7, #4] 800257c: 681b ldr r3, [r3, #0] 800257e: 4618 mov r0, r3 8002580: f004 fe82 bl 8007288 8002584: 4603 mov r3, r0 8002586: f403 5300 and.w r3, r3, #8192 ; 0x2000 800258a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800258e: d124 bne.n 80025da { (void)USB_ActivateSetup(hpcd->Instance); 8002590: 687b ldr r3, [r7, #4] 8002592: 681b ldr r3, [r3, #0] 8002594: 4618 mov r0, r3 8002596: f004 ff19 bl 80073cc hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 800259a: 687b ldr r3, [r7, #4] 800259c: 681b ldr r3, [r3, #0] 800259e: 4618 mov r0, r3 80025a0: f003 ff73 bl 800648a 80025a4: 4603 mov r3, r0 80025a6: 461a mov r2, r3 80025a8: 687b ldr r3, [r7, #4] 80025aa: 60da str r2, [r3, #12] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 80025ac: 687b ldr r3, [r7, #4] 80025ae: 681c ldr r4, [r3, #0] 80025b0: f001 fc62 bl 8003e78 80025b4: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 80025b6: 687b ldr r3, [r7, #4] 80025b8: 68db ldr r3, [r3, #12] (void)USB_SetTurnaroundTime(hpcd->Instance, 80025ba: b2db uxtb r3, r3 80025bc: 461a mov r2, r3 80025be: 4620 mov r0, r4 80025c0: f003 fc7c bl 8005ebc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 80025c4: 6878 ldr r0, [r7, #4] 80025c6: f006 ff14 bl 80093f2 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 80025ca: 687b ldr r3, [r7, #4] 80025cc: 681b ldr r3, [r3, #0] 80025ce: 695a ldr r2, [r3, #20] 80025d0: 687b ldr r3, [r7, #4] 80025d2: 681b ldr r3, [r3, #0] 80025d4: f402 5200 and.w r2, r2, #8192 ; 0x2000 80025d8: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 80025da: 687b ldr r3, [r7, #4] 80025dc: 681b ldr r3, [r3, #0] 80025de: 4618 mov r0, r3 80025e0: f004 fe52 bl 8007288 80025e4: 4603 mov r3, r0 80025e6: f003 0308 and.w r3, r3, #8 80025ea: 2b08 cmp r3, #8 80025ec: d10a bne.n 8002604 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 80025ee: 6878 ldr r0, [r7, #4] 80025f0: f006 fef1 bl 80093d6 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 80025f4: 687b ldr r3, [r7, #4] 80025f6: 681b ldr r3, [r3, #0] 80025f8: 695a ldr r2, [r3, #20] 80025fa: 687b ldr r3, [r7, #4] 80025fc: 681b ldr r3, [r3, #0] 80025fe: f002 0208 and.w r2, r2, #8 8002602: 615a str r2, [r3, #20] } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 8002604: 687b ldr r3, [r7, #4] 8002606: 681b ldr r3, [r3, #0] 8002608: 4618 mov r0, r3 800260a: f004 fe3d bl 8007288 800260e: 4603 mov r3, r0 8002610: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8002614: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8002618: d10f bne.n 800263a { /* Keep application checking the corresponding Iso IN endpoint causing the incomplete Interrupt */ epnum = 0U; 800261a: 2300 movs r3, #0 800261c: 627b str r3, [r7, #36] ; 0x24 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 800261e: 6a7b ldr r3, [r7, #36] ; 0x24 8002620: b2db uxtb r3, r3 8002622: 4619 mov r1, r3 8002624: 6878 ldr r0, [r7, #4] 8002626: f006 ff53 bl 80094d0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 800262a: 687b ldr r3, [r7, #4] 800262c: 681b ldr r3, [r3, #0] 800262e: 695a ldr r2, [r3, #20] 8002630: 687b ldr r3, [r7, #4] 8002632: 681b ldr r3, [r3, #0] 8002634: f402 1280 and.w r2, r2, #1048576 ; 0x100000 8002638: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 800263a: 687b ldr r3, [r7, #4] 800263c: 681b ldr r3, [r3, #0] 800263e: 4618 mov r0, r3 8002640: f004 fe22 bl 8007288 8002644: 4603 mov r3, r0 8002646: f403 1300 and.w r3, r3, #2097152 ; 0x200000 800264a: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 800264e: d10f bne.n 8002670 { /* Keep application checking the corresponding Iso OUT endpoint causing the incomplete Interrupt */ epnum = 0U; 8002650: 2300 movs r3, #0 8002652: 627b str r3, [r7, #36] ; 0x24 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 8002654: 6a7b ldr r3, [r7, #36] ; 0x24 8002656: b2db uxtb r3, r3 8002658: 4619 mov r1, r3 800265a: 6878 ldr r0, [r7, #4] 800265c: f006 ff26 bl 80094ac #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 8002660: 687b ldr r3, [r7, #4] 8002662: 681b ldr r3, [r3, #0] 8002664: 695a ldr r2, [r3, #20] 8002666: 687b ldr r3, [r7, #4] 8002668: 681b ldr r3, [r3, #0] 800266a: f402 1200 and.w r2, r2, #2097152 ; 0x200000 800266e: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 8002670: 687b ldr r3, [r7, #4] 8002672: 681b ldr r3, [r3, #0] 8002674: 4618 mov r0, r3 8002676: f004 fe07 bl 8007288 800267a: 4603 mov r3, r0 800267c: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 8002680: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8002684: d10a bne.n 800269c { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 8002686: 6878 ldr r0, [r7, #4] 8002688: f006 ff34 bl 80094f4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 800268c: 687b ldr r3, [r7, #4] 800268e: 681b ldr r3, [r3, #0] 8002690: 695a ldr r2, [r3, #20] 8002692: 687b ldr r3, [r7, #4] 8002694: 681b ldr r3, [r3, #0] 8002696: f002 4280 and.w r2, r2, #1073741824 ; 0x40000000 800269a: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 800269c: 687b ldr r3, [r7, #4] 800269e: 681b ldr r3, [r3, #0] 80026a0: 4618 mov r0, r3 80026a2: f004 fdf1 bl 8007288 80026a6: 4603 mov r3, r0 80026a8: f003 0304 and.w r3, r3, #4 80026ac: 2b04 cmp r3, #4 80026ae: d115 bne.n 80026dc { temp = hpcd->Instance->GOTGINT; 80026b0: 687b ldr r3, [r7, #4] 80026b2: 681b ldr r3, [r3, #0] 80026b4: 685b ldr r3, [r3, #4] 80026b6: 61bb str r3, [r7, #24] if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 80026b8: 69bb ldr r3, [r7, #24] 80026ba: f003 0304 and.w r3, r3, #4 80026be: 2b00 cmp r3, #0 80026c0: d002 beq.n 80026c8 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 80026c2: 6878 ldr r0, [r7, #4] 80026c4: f006 ff24 bl 8009510 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= temp; 80026c8: 687b ldr r3, [r7, #4] 80026ca: 681b ldr r3, [r3, #0] 80026cc: 6859 ldr r1, [r3, #4] 80026ce: 687b ldr r3, [r7, #4] 80026d0: 681b ldr r3, [r3, #0] 80026d2: 69ba ldr r2, [r7, #24] 80026d4: 430a orrs r2, r1 80026d6: 605a str r2, [r3, #4] 80026d8: e000 b.n 80026dc return; 80026da: bf00 nop } } } 80026dc: 3734 adds r7, #52 ; 0x34 80026de: 46bd mov sp, r7 80026e0: bd90 pop {r4, r7, pc} 080026e2 : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 80026e2: b580 push {r7, lr} 80026e4: b082 sub sp, #8 80026e6: af00 add r7, sp, #0 80026e8: 6078 str r0, [r7, #4] 80026ea: 460b mov r3, r1 80026ec: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 80026ee: 687b ldr r3, [r7, #4] 80026f0: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 80026f4: 2b01 cmp r3, #1 80026f6: d101 bne.n 80026fc 80026f8: 2302 movs r3, #2 80026fa: e013 b.n 8002724 80026fc: 687b ldr r3, [r7, #4] 80026fe: 2201 movs r2, #1 8002700: f883 23bc strb.w r2, [r3, #956] ; 0x3bc hpcd->USB_Address = address; 8002704: 687b ldr r3, [r7, #4] 8002706: 78fa ldrb r2, [r7, #3] 8002708: f883 2038 strb.w r2, [r3, #56] ; 0x38 (void)USB_SetDevAddress(hpcd->Instance, address); 800270c: 687b ldr r3, [r7, #4] 800270e: 681b ldr r3, [r3, #0] 8002710: 78fa ldrb r2, [r7, #3] 8002712: 4611 mov r1, r2 8002714: 4618 mov r0, r3 8002716: f004 fd4f bl 80071b8 __HAL_UNLOCK(hpcd); 800271a: 687b ldr r3, [r7, #4] 800271c: 2200 movs r2, #0 800271e: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 8002722: 2300 movs r3, #0 } 8002724: 4618 mov r0, r3 8002726: 3708 adds r7, #8 8002728: 46bd mov sp, r7 800272a: bd80 pop {r7, pc} 0800272c : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 800272c: b580 push {r7, lr} 800272e: b084 sub sp, #16 8002730: af00 add r7, sp, #0 8002732: 6078 str r0, [r7, #4] 8002734: 4608 mov r0, r1 8002736: 4611 mov r1, r2 8002738: 461a mov r2, r3 800273a: 4603 mov r3, r0 800273c: 70fb strb r3, [r7, #3] 800273e: 460b mov r3, r1 8002740: 803b strh r3, [r7, #0] 8002742: 4613 mov r3, r2 8002744: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 8002746: 2300 movs r3, #0 8002748: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 800274a: f997 3003 ldrsb.w r3, [r7, #3] 800274e: 2b00 cmp r3, #0 8002750: da0f bge.n 8002772 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8002752: 78fb ldrb r3, [r7, #3] 8002754: f003 020f and.w r2, r3, #15 8002758: 4613 mov r3, r2 800275a: 00db lsls r3, r3, #3 800275c: 1a9b subs r3, r3, r2 800275e: 009b lsls r3, r3, #2 8002760: 3338 adds r3, #56 ; 0x38 8002762: 687a ldr r2, [r7, #4] 8002764: 4413 add r3, r2 8002766: 3304 adds r3, #4 8002768: 60fb str r3, [r7, #12] ep->is_in = 1U; 800276a: 68fb ldr r3, [r7, #12] 800276c: 2201 movs r2, #1 800276e: 705a strb r2, [r3, #1] 8002770: e00f b.n 8002792 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8002772: 78fb ldrb r3, [r7, #3] 8002774: f003 020f and.w r2, r3, #15 8002778: 4613 mov r3, r2 800277a: 00db lsls r3, r3, #3 800277c: 1a9b subs r3, r3, r2 800277e: 009b lsls r3, r3, #2 8002780: f503 73fc add.w r3, r3, #504 ; 0x1f8 8002784: 687a ldr r2, [r7, #4] 8002786: 4413 add r3, r2 8002788: 3304 adds r3, #4 800278a: 60fb str r3, [r7, #12] ep->is_in = 0U; 800278c: 68fb ldr r3, [r7, #12] 800278e: 2200 movs r2, #0 8002790: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8002792: 78fb ldrb r3, [r7, #3] 8002794: f003 030f and.w r3, r3, #15 8002798: b2da uxtb r2, r3 800279a: 68fb ldr r3, [r7, #12] 800279c: 701a strb r2, [r3, #0] ep->maxpacket = ep_mps; 800279e: 883a ldrh r2, [r7, #0] 80027a0: 68fb ldr r3, [r7, #12] 80027a2: 609a str r2, [r3, #8] ep->type = ep_type; 80027a4: 68fb ldr r3, [r7, #12] 80027a6: 78ba ldrb r2, [r7, #2] 80027a8: 70da strb r2, [r3, #3] if (ep->is_in != 0U) 80027aa: 68fb ldr r3, [r7, #12] 80027ac: 785b ldrb r3, [r3, #1] 80027ae: 2b00 cmp r3, #0 80027b0: d004 beq.n 80027bc { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 80027b2: 68fb ldr r3, [r7, #12] 80027b4: 781b ldrb r3, [r3, #0] 80027b6: b29a uxth r2, r3 80027b8: 68fb ldr r3, [r7, #12] 80027ba: 80da strh r2, [r3, #6] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 80027bc: 78bb ldrb r3, [r7, #2] 80027be: 2b02 cmp r3, #2 80027c0: d102 bne.n 80027c8 { ep->data_pid_start = 0U; 80027c2: 68fb ldr r3, [r7, #12] 80027c4: 2200 movs r2, #0 80027c6: 711a strb r2, [r3, #4] } __HAL_LOCK(hpcd); 80027c8: 687b ldr r3, [r7, #4] 80027ca: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 80027ce: 2b01 cmp r3, #1 80027d0: d101 bne.n 80027d6 80027d2: 2302 movs r3, #2 80027d4: e00e b.n 80027f4 80027d6: 687b ldr r3, [r7, #4] 80027d8: 2201 movs r2, #1 80027da: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_ActivateEndpoint(hpcd->Instance, ep); 80027de: 687b ldr r3, [r7, #4] 80027e0: 681b ldr r3, [r3, #0] 80027e2: 68f9 ldr r1, [r7, #12] 80027e4: 4618 mov r0, r3 80027e6: f003 fe75 bl 80064d4 __HAL_UNLOCK(hpcd); 80027ea: 687b ldr r3, [r7, #4] 80027ec: 2200 movs r2, #0 80027ee: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return ret; 80027f2: 7afb ldrb r3, [r7, #11] } 80027f4: 4618 mov r0, r3 80027f6: 3710 adds r7, #16 80027f8: 46bd mov sp, r7 80027fa: bd80 pop {r7, pc} 080027fc : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 80027fc: b580 push {r7, lr} 80027fe: b084 sub sp, #16 8002800: af00 add r7, sp, #0 8002802: 6078 str r0, [r7, #4] 8002804: 460b mov r3, r1 8002806: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8002808: f997 3003 ldrsb.w r3, [r7, #3] 800280c: 2b00 cmp r3, #0 800280e: da0f bge.n 8002830 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8002810: 78fb ldrb r3, [r7, #3] 8002812: f003 020f and.w r2, r3, #15 8002816: 4613 mov r3, r2 8002818: 00db lsls r3, r3, #3 800281a: 1a9b subs r3, r3, r2 800281c: 009b lsls r3, r3, #2 800281e: 3338 adds r3, #56 ; 0x38 8002820: 687a ldr r2, [r7, #4] 8002822: 4413 add r3, r2 8002824: 3304 adds r3, #4 8002826: 60fb str r3, [r7, #12] ep->is_in = 1U; 8002828: 68fb ldr r3, [r7, #12] 800282a: 2201 movs r2, #1 800282c: 705a strb r2, [r3, #1] 800282e: e00f b.n 8002850 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8002830: 78fb ldrb r3, [r7, #3] 8002832: f003 020f and.w r2, r3, #15 8002836: 4613 mov r3, r2 8002838: 00db lsls r3, r3, #3 800283a: 1a9b subs r3, r3, r2 800283c: 009b lsls r3, r3, #2 800283e: f503 73fc add.w r3, r3, #504 ; 0x1f8 8002842: 687a ldr r2, [r7, #4] 8002844: 4413 add r3, r2 8002846: 3304 adds r3, #4 8002848: 60fb str r3, [r7, #12] ep->is_in = 0U; 800284a: 68fb ldr r3, [r7, #12] 800284c: 2200 movs r2, #0 800284e: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8002850: 78fb ldrb r3, [r7, #3] 8002852: f003 030f and.w r3, r3, #15 8002856: b2da uxtb r2, r3 8002858: 68fb ldr r3, [r7, #12] 800285a: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 800285c: 687b ldr r3, [r7, #4] 800285e: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 8002862: 2b01 cmp r3, #1 8002864: d101 bne.n 800286a 8002866: 2302 movs r3, #2 8002868: e00e b.n 8002888 800286a: 687b ldr r3, [r7, #4] 800286c: 2201 movs r2, #1 800286e: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 8002872: 687b ldr r3, [r7, #4] 8002874: 681b ldr r3, [r3, #0] 8002876: 68f9 ldr r1, [r7, #12] 8002878: 4618 mov r0, r3 800287a: f003 feb3 bl 80065e4 __HAL_UNLOCK(hpcd); 800287e: 687b ldr r3, [r7, #4] 8002880: 2200 movs r2, #0 8002882: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 8002886: 2300 movs r3, #0 } 8002888: 4618 mov r0, r3 800288a: 3710 adds r7, #16 800288c: 46bd mov sp, r7 800288e: bd80 pop {r7, pc} 08002890 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8002890: b580 push {r7, lr} 8002892: b086 sub sp, #24 8002894: af00 add r7, sp, #0 8002896: 60f8 str r0, [r7, #12] 8002898: 607a str r2, [r7, #4] 800289a: 603b str r3, [r7, #0] 800289c: 460b mov r3, r1 800289e: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80028a0: 7afb ldrb r3, [r7, #11] 80028a2: f003 020f and.w r2, r3, #15 80028a6: 4613 mov r3, r2 80028a8: 00db lsls r3, r3, #3 80028aa: 1a9b subs r3, r3, r2 80028ac: 009b lsls r3, r3, #2 80028ae: f503 73fc add.w r3, r3, #504 ; 0x1f8 80028b2: 68fa ldr r2, [r7, #12] 80028b4: 4413 add r3, r2 80028b6: 3304 adds r3, #4 80028b8: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 80028ba: 697b ldr r3, [r7, #20] 80028bc: 687a ldr r2, [r7, #4] 80028be: 60da str r2, [r3, #12] ep->xfer_len = len; 80028c0: 697b ldr r3, [r7, #20] 80028c2: 683a ldr r2, [r7, #0] 80028c4: 615a str r2, [r3, #20] ep->xfer_count = 0U; 80028c6: 697b ldr r3, [r7, #20] 80028c8: 2200 movs r2, #0 80028ca: 619a str r2, [r3, #24] ep->is_in = 0U; 80028cc: 697b ldr r3, [r7, #20] 80028ce: 2200 movs r2, #0 80028d0: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 80028d2: 7afb ldrb r3, [r7, #11] 80028d4: f003 030f and.w r3, r3, #15 80028d8: b2da uxtb r2, r3 80028da: 697b ldr r3, [r7, #20] 80028dc: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 80028de: 68fb ldr r3, [r7, #12] 80028e0: 691b ldr r3, [r3, #16] 80028e2: 2b01 cmp r3, #1 80028e4: d102 bne.n 80028ec { ep->dma_addr = (uint32_t)pBuf; 80028e6: 687a ldr r2, [r7, #4] 80028e8: 697b ldr r3, [r7, #20] 80028ea: 611a str r2, [r3, #16] } if ((ep_addr & EP_ADDR_MSK) == 0U) 80028ec: 7afb ldrb r3, [r7, #11] 80028ee: f003 030f and.w r3, r3, #15 80028f2: 2b00 cmp r3, #0 80028f4: d109 bne.n 800290a { (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 80028f6: 68fb ldr r3, [r7, #12] 80028f8: 6818 ldr r0, [r3, #0] 80028fa: 68fb ldr r3, [r7, #12] 80028fc: 691b ldr r3, [r3, #16] 80028fe: b2db uxtb r3, r3 8002900: 461a mov r2, r3 8002902: 6979 ldr r1, [r7, #20] 8002904: f004 f996 bl 8006c34 8002908: e008 b.n 800291c } else { (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 800290a: 68fb ldr r3, [r7, #12] 800290c: 6818 ldr r0, [r3, #0] 800290e: 68fb ldr r3, [r7, #12] 8002910: 691b ldr r3, [r3, #16] 8002912: b2db uxtb r3, r3 8002914: 461a mov r2, r3 8002916: 6979 ldr r1, [r7, #20] 8002918: f003 ff40 bl 800679c } return HAL_OK; 800291c: 2300 movs r3, #0 } 800291e: 4618 mov r0, r3 8002920: 3718 adds r7, #24 8002922: 46bd mov sp, r7 8002924: bd80 pop {r7, pc} 08002926 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval Data Size */ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8002926: b480 push {r7} 8002928: b083 sub sp, #12 800292a: af00 add r7, sp, #0 800292c: 6078 str r0, [r7, #4] 800292e: 460b mov r3, r1 8002930: 70fb strb r3, [r7, #3] return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; 8002932: 78fb ldrb r3, [r7, #3] 8002934: f003 020f and.w r2, r3, #15 8002938: 6879 ldr r1, [r7, #4] 800293a: 4613 mov r3, r2 800293c: 00db lsls r3, r3, #3 800293e: 1a9b subs r3, r3, r2 8002940: 009b lsls r3, r3, #2 8002942: 440b add r3, r1 8002944: f503 7305 add.w r3, r3, #532 ; 0x214 8002948: 681b ldr r3, [r3, #0] } 800294a: 4618 mov r0, r3 800294c: 370c adds r7, #12 800294e: 46bd mov sp, r7 8002950: f85d 7b04 ldr.w r7, [sp], #4 8002954: 4770 bx lr 08002956 : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8002956: b580 push {r7, lr} 8002958: b086 sub sp, #24 800295a: af00 add r7, sp, #0 800295c: 60f8 str r0, [r7, #12] 800295e: 607a str r2, [r7, #4] 8002960: 603b str r3, [r7, #0] 8002962: 460b mov r3, r1 8002964: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8002966: 7afb ldrb r3, [r7, #11] 8002968: f003 020f and.w r2, r3, #15 800296c: 4613 mov r3, r2 800296e: 00db lsls r3, r3, #3 8002970: 1a9b subs r3, r3, r2 8002972: 009b lsls r3, r3, #2 8002974: 3338 adds r3, #56 ; 0x38 8002976: 68fa ldr r2, [r7, #12] 8002978: 4413 add r3, r2 800297a: 3304 adds r3, #4 800297c: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 800297e: 697b ldr r3, [r7, #20] 8002980: 687a ldr r2, [r7, #4] 8002982: 60da str r2, [r3, #12] ep->xfer_len = len; 8002984: 697b ldr r3, [r7, #20] 8002986: 683a ldr r2, [r7, #0] 8002988: 615a str r2, [r3, #20] ep->xfer_count = 0U; 800298a: 697b ldr r3, [r7, #20] 800298c: 2200 movs r2, #0 800298e: 619a str r2, [r3, #24] ep->is_in = 1U; 8002990: 697b ldr r3, [r7, #20] 8002992: 2201 movs r2, #1 8002994: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8002996: 7afb ldrb r3, [r7, #11] 8002998: f003 030f and.w r3, r3, #15 800299c: b2da uxtb r2, r3 800299e: 697b ldr r3, [r7, #20] 80029a0: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 80029a2: 68fb ldr r3, [r7, #12] 80029a4: 691b ldr r3, [r3, #16] 80029a6: 2b01 cmp r3, #1 80029a8: d102 bne.n 80029b0 { ep->dma_addr = (uint32_t)pBuf; 80029aa: 687a ldr r2, [r7, #4] 80029ac: 697b ldr r3, [r7, #20] 80029ae: 611a str r2, [r3, #16] } if ((ep_addr & EP_ADDR_MSK) == 0U) 80029b0: 7afb ldrb r3, [r7, #11] 80029b2: f003 030f and.w r3, r3, #15 80029b6: 2b00 cmp r3, #0 80029b8: d109 bne.n 80029ce { (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 80029ba: 68fb ldr r3, [r7, #12] 80029bc: 6818 ldr r0, [r3, #0] 80029be: 68fb ldr r3, [r7, #12] 80029c0: 691b ldr r3, [r3, #16] 80029c2: b2db uxtb r3, r3 80029c4: 461a mov r2, r3 80029c6: 6979 ldr r1, [r7, #20] 80029c8: f004 f934 bl 8006c34 80029cc: e008 b.n 80029e0 } else { (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 80029ce: 68fb ldr r3, [r7, #12] 80029d0: 6818 ldr r0, [r3, #0] 80029d2: 68fb ldr r3, [r7, #12] 80029d4: 691b ldr r3, [r3, #16] 80029d6: b2db uxtb r3, r3 80029d8: 461a mov r2, r3 80029da: 6979 ldr r1, [r7, #20] 80029dc: f003 fede bl 800679c } return HAL_OK; 80029e0: 2300 movs r3, #0 } 80029e2: 4618 mov r0, r3 80029e4: 3718 adds r7, #24 80029e6: 46bd mov sp, r7 80029e8: bd80 pop {r7, pc} 080029ea : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 80029ea: b580 push {r7, lr} 80029ec: b084 sub sp, #16 80029ee: af00 add r7, sp, #0 80029f0: 6078 str r0, [r7, #4] 80029f2: 460b mov r3, r1 80029f4: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 80029f6: 78fb ldrb r3, [r7, #3] 80029f8: f003 020f and.w r2, r3, #15 80029fc: 687b ldr r3, [r7, #4] 80029fe: 685b ldr r3, [r3, #4] 8002a00: 429a cmp r2, r3 8002a02: d901 bls.n 8002a08 { return HAL_ERROR; 8002a04: 2301 movs r3, #1 8002a06: e050 b.n 8002aaa } if ((0x80U & ep_addr) == 0x80U) 8002a08: f997 3003 ldrsb.w r3, [r7, #3] 8002a0c: 2b00 cmp r3, #0 8002a0e: da0f bge.n 8002a30 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8002a10: 78fb ldrb r3, [r7, #3] 8002a12: f003 020f and.w r2, r3, #15 8002a16: 4613 mov r3, r2 8002a18: 00db lsls r3, r3, #3 8002a1a: 1a9b subs r3, r3, r2 8002a1c: 009b lsls r3, r3, #2 8002a1e: 3338 adds r3, #56 ; 0x38 8002a20: 687a ldr r2, [r7, #4] 8002a22: 4413 add r3, r2 8002a24: 3304 adds r3, #4 8002a26: 60fb str r3, [r7, #12] ep->is_in = 1U; 8002a28: 68fb ldr r3, [r7, #12] 8002a2a: 2201 movs r2, #1 8002a2c: 705a strb r2, [r3, #1] 8002a2e: e00d b.n 8002a4c } else { ep = &hpcd->OUT_ep[ep_addr]; 8002a30: 78fa ldrb r2, [r7, #3] 8002a32: 4613 mov r3, r2 8002a34: 00db lsls r3, r3, #3 8002a36: 1a9b subs r3, r3, r2 8002a38: 009b lsls r3, r3, #2 8002a3a: f503 73fc add.w r3, r3, #504 ; 0x1f8 8002a3e: 687a ldr r2, [r7, #4] 8002a40: 4413 add r3, r2 8002a42: 3304 adds r3, #4 8002a44: 60fb str r3, [r7, #12] ep->is_in = 0U; 8002a46: 68fb ldr r3, [r7, #12] 8002a48: 2200 movs r2, #0 8002a4a: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8002a4c: 68fb ldr r3, [r7, #12] 8002a4e: 2201 movs r2, #1 8002a50: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8002a52: 78fb ldrb r3, [r7, #3] 8002a54: f003 030f and.w r3, r3, #15 8002a58: b2da uxtb r2, r3 8002a5a: 68fb ldr r3, [r7, #12] 8002a5c: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8002a5e: 687b ldr r3, [r7, #4] 8002a60: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 8002a64: 2b01 cmp r3, #1 8002a66: d101 bne.n 8002a6c 8002a68: 2302 movs r3, #2 8002a6a: e01e b.n 8002aaa 8002a6c: 687b ldr r3, [r7, #4] 8002a6e: 2201 movs r2, #1 8002a70: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_EPSetStall(hpcd->Instance, ep); 8002a74: 687b ldr r3, [r7, #4] 8002a76: 681b ldr r3, [r3, #0] 8002a78: 68f9 ldr r1, [r7, #12] 8002a7a: 4618 mov r0, r3 8002a7c: f004 fac8 bl 8007010 if ((ep_addr & EP_ADDR_MSK) == 0U) 8002a80: 78fb ldrb r3, [r7, #3] 8002a82: f003 030f and.w r3, r3, #15 8002a86: 2b00 cmp r3, #0 8002a88: d10a bne.n 8002aa0 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 8002a8a: 687b ldr r3, [r7, #4] 8002a8c: 6818 ldr r0, [r3, #0] 8002a8e: 687b ldr r3, [r7, #4] 8002a90: 691b ldr r3, [r3, #16] 8002a92: b2d9 uxtb r1, r3 8002a94: 687b ldr r3, [r7, #4] 8002a96: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002a9a: 461a mov r2, r3 8002a9c: f004 fcba bl 8007414 } __HAL_UNLOCK(hpcd); 8002aa0: 687b ldr r3, [r7, #4] 8002aa2: 2200 movs r2, #0 8002aa4: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 8002aa8: 2300 movs r3, #0 } 8002aaa: 4618 mov r0, r3 8002aac: 3710 adds r7, #16 8002aae: 46bd mov sp, r7 8002ab0: bd80 pop {r7, pc} 08002ab2 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8002ab2: b580 push {r7, lr} 8002ab4: b084 sub sp, #16 8002ab6: af00 add r7, sp, #0 8002ab8: 6078 str r0, [r7, #4] 8002aba: 460b mov r3, r1 8002abc: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8002abe: 78fb ldrb r3, [r7, #3] 8002ac0: f003 020f and.w r2, r3, #15 8002ac4: 687b ldr r3, [r7, #4] 8002ac6: 685b ldr r3, [r3, #4] 8002ac8: 429a cmp r2, r3 8002aca: d901 bls.n 8002ad0 { return HAL_ERROR; 8002acc: 2301 movs r3, #1 8002ace: e042 b.n 8002b56 } if ((0x80U & ep_addr) == 0x80U) 8002ad0: f997 3003 ldrsb.w r3, [r7, #3] 8002ad4: 2b00 cmp r3, #0 8002ad6: da0f bge.n 8002af8 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8002ad8: 78fb ldrb r3, [r7, #3] 8002ada: f003 020f and.w r2, r3, #15 8002ade: 4613 mov r3, r2 8002ae0: 00db lsls r3, r3, #3 8002ae2: 1a9b subs r3, r3, r2 8002ae4: 009b lsls r3, r3, #2 8002ae6: 3338 adds r3, #56 ; 0x38 8002ae8: 687a ldr r2, [r7, #4] 8002aea: 4413 add r3, r2 8002aec: 3304 adds r3, #4 8002aee: 60fb str r3, [r7, #12] ep->is_in = 1U; 8002af0: 68fb ldr r3, [r7, #12] 8002af2: 2201 movs r2, #1 8002af4: 705a strb r2, [r3, #1] 8002af6: e00f b.n 8002b18 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8002af8: 78fb ldrb r3, [r7, #3] 8002afa: f003 020f and.w r2, r3, #15 8002afe: 4613 mov r3, r2 8002b00: 00db lsls r3, r3, #3 8002b02: 1a9b subs r3, r3, r2 8002b04: 009b lsls r3, r3, #2 8002b06: f503 73fc add.w r3, r3, #504 ; 0x1f8 8002b0a: 687a ldr r2, [r7, #4] 8002b0c: 4413 add r3, r2 8002b0e: 3304 adds r3, #4 8002b10: 60fb str r3, [r7, #12] ep->is_in = 0U; 8002b12: 68fb ldr r3, [r7, #12] 8002b14: 2200 movs r2, #0 8002b16: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8002b18: 68fb ldr r3, [r7, #12] 8002b1a: 2200 movs r2, #0 8002b1c: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8002b1e: 78fb ldrb r3, [r7, #3] 8002b20: f003 030f and.w r3, r3, #15 8002b24: b2da uxtb r2, r3 8002b26: 68fb ldr r3, [r7, #12] 8002b28: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8002b2a: 687b ldr r3, [r7, #4] 8002b2c: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 8002b30: 2b01 cmp r3, #1 8002b32: d101 bne.n 8002b38 8002b34: 2302 movs r3, #2 8002b36: e00e b.n 8002b56 8002b38: 687b ldr r3, [r7, #4] 8002b3a: 2201 movs r2, #1 8002b3c: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_EPClearStall(hpcd->Instance, ep); 8002b40: 687b ldr r3, [r7, #4] 8002b42: 681b ldr r3, [r3, #0] 8002b44: 68f9 ldr r1, [r7, #12] 8002b46: 4618 mov r0, r3 8002b48: f004 fad0 bl 80070ec __HAL_UNLOCK(hpcd); 8002b4c: 687b ldr r3, [r7, #4] 8002b4e: 2200 movs r2, #0 8002b50: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 8002b54: 2300 movs r3, #0 } 8002b56: 4618 mov r0, r3 8002b58: 3710 adds r7, #16 8002b5a: 46bd mov sp, r7 8002b5c: bd80 pop {r7, pc} 08002b5e : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8002b5e: b580 push {r7, lr} 8002b60: b08a sub sp, #40 ; 0x28 8002b62: af02 add r7, sp, #8 8002b64: 6078 str r0, [r7, #4] 8002b66: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002b68: 687b ldr r3, [r7, #4] 8002b6a: 681b ldr r3, [r3, #0] 8002b6c: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8002b6e: 697b ldr r3, [r7, #20] 8002b70: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 8002b72: 683a ldr r2, [r7, #0] 8002b74: 4613 mov r3, r2 8002b76: 00db lsls r3, r3, #3 8002b78: 1a9b subs r3, r3, r2 8002b7a: 009b lsls r3, r3, #2 8002b7c: 3338 adds r3, #56 ; 0x38 8002b7e: 687a ldr r2, [r7, #4] 8002b80: 4413 add r3, r2 8002b82: 3304 adds r3, #4 8002b84: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 8002b86: 68fb ldr r3, [r7, #12] 8002b88: 699a ldr r2, [r3, #24] 8002b8a: 68fb ldr r3, [r7, #12] 8002b8c: 695b ldr r3, [r3, #20] 8002b8e: 429a cmp r2, r3 8002b90: d901 bls.n 8002b96 { return HAL_ERROR; 8002b92: 2301 movs r3, #1 8002b94: e06c b.n 8002c70 } len = ep->xfer_len - ep->xfer_count; 8002b96: 68fb ldr r3, [r7, #12] 8002b98: 695a ldr r2, [r3, #20] 8002b9a: 68fb ldr r3, [r7, #12] 8002b9c: 699b ldr r3, [r3, #24] 8002b9e: 1ad3 subs r3, r2, r3 8002ba0: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8002ba2: 68fb ldr r3, [r7, #12] 8002ba4: 689b ldr r3, [r3, #8] 8002ba6: 69fa ldr r2, [r7, #28] 8002ba8: 429a cmp r2, r3 8002baa: d902 bls.n 8002bb2 { len = ep->maxpacket; 8002bac: 68fb ldr r3, [r7, #12] 8002bae: 689b ldr r3, [r3, #8] 8002bb0: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8002bb2: 69fb ldr r3, [r7, #28] 8002bb4: 3303 adds r3, #3 8002bb6: 089b lsrs r3, r3, #2 8002bb8: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8002bba: e02b b.n 8002c14 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 8002bbc: 68fb ldr r3, [r7, #12] 8002bbe: 695a ldr r2, [r3, #20] 8002bc0: 68fb ldr r3, [r7, #12] 8002bc2: 699b ldr r3, [r3, #24] 8002bc4: 1ad3 subs r3, r2, r3 8002bc6: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8002bc8: 68fb ldr r3, [r7, #12] 8002bca: 689b ldr r3, [r3, #8] 8002bcc: 69fa ldr r2, [r7, #28] 8002bce: 429a cmp r2, r3 8002bd0: d902 bls.n 8002bd8 { len = ep->maxpacket; 8002bd2: 68fb ldr r3, [r7, #12] 8002bd4: 689b ldr r3, [r3, #8] 8002bd6: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8002bd8: 69fb ldr r3, [r7, #28] 8002bda: 3303 adds r3, #3 8002bdc: 089b lsrs r3, r3, #2 8002bde: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8002be0: 68fb ldr r3, [r7, #12] 8002be2: 68d9 ldr r1, [r3, #12] 8002be4: 683b ldr r3, [r7, #0] 8002be6: b2da uxtb r2, r3 8002be8: 69fb ldr r3, [r7, #28] 8002bea: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 8002bec: 687b ldr r3, [r7, #4] 8002bee: 691b ldr r3, [r3, #16] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8002bf0: b2db uxtb r3, r3 8002bf2: 9300 str r3, [sp, #0] 8002bf4: 4603 mov r3, r0 8002bf6: 6978 ldr r0, [r7, #20] 8002bf8: f004 f974 bl 8006ee4 ep->xfer_buff += len; 8002bfc: 68fb ldr r3, [r7, #12] 8002bfe: 68da ldr r2, [r3, #12] 8002c00: 69fb ldr r3, [r7, #28] 8002c02: 441a add r2, r3 8002c04: 68fb ldr r3, [r7, #12] 8002c06: 60da str r2, [r3, #12] ep->xfer_count += len; 8002c08: 68fb ldr r3, [r7, #12] 8002c0a: 699a ldr r2, [r3, #24] 8002c0c: 69fb ldr r3, [r7, #28] 8002c0e: 441a add r2, r3 8002c10: 68fb ldr r3, [r7, #12] 8002c12: 619a str r2, [r3, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8002c14: 683b ldr r3, [r7, #0] 8002c16: 015a lsls r2, r3, #5 8002c18: 693b ldr r3, [r7, #16] 8002c1a: 4413 add r3, r2 8002c1c: f503 6310 add.w r3, r3, #2304 ; 0x900 8002c20: 699b ldr r3, [r3, #24] 8002c22: b29b uxth r3, r3 8002c24: 69ba ldr r2, [r7, #24] 8002c26: 429a cmp r2, r3 8002c28: d809 bhi.n 8002c3e (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8002c2a: 68fb ldr r3, [r7, #12] 8002c2c: 699a ldr r2, [r3, #24] 8002c2e: 68fb ldr r3, [r7, #12] 8002c30: 695b ldr r3, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8002c32: 429a cmp r2, r3 8002c34: d203 bcs.n 8002c3e (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8002c36: 68fb ldr r3, [r7, #12] 8002c38: 695b ldr r3, [r3, #20] 8002c3a: 2b00 cmp r3, #0 8002c3c: d1be bne.n 8002bbc } if (ep->xfer_len <= ep->xfer_count) 8002c3e: 68fb ldr r3, [r7, #12] 8002c40: 695a ldr r2, [r3, #20] 8002c42: 68fb ldr r3, [r7, #12] 8002c44: 699b ldr r3, [r3, #24] 8002c46: 429a cmp r2, r3 8002c48: d811 bhi.n 8002c6e { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8002c4a: 683b ldr r3, [r7, #0] 8002c4c: f003 030f and.w r3, r3, #15 8002c50: 2201 movs r2, #1 8002c52: fa02 f303 lsl.w r3, r2, r3 8002c56: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8002c58: 693b ldr r3, [r7, #16] 8002c5a: f503 6300 add.w r3, r3, #2048 ; 0x800 8002c5e: 6b5a ldr r2, [r3, #52] ; 0x34 8002c60: 68bb ldr r3, [r7, #8] 8002c62: 43db mvns r3, r3 8002c64: 6939 ldr r1, [r7, #16] 8002c66: f501 6100 add.w r1, r1, #2048 ; 0x800 8002c6a: 4013 ands r3, r2 8002c6c: 634b str r3, [r1, #52] ; 0x34 } return HAL_OK; 8002c6e: 2300 movs r3, #0 } 8002c70: 4618 mov r0, r3 8002c72: 3720 adds r7, #32 8002c74: 46bd mov sp, r7 8002c76: bd80 pop {r7, pc} 08002c78 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8002c78: b580 push {r7, lr} 8002c7a: b086 sub sp, #24 8002c7c: af00 add r7, sp, #0 8002c7e: 6078 str r0, [r7, #4] 8002c80: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002c82: 687b ldr r3, [r7, #4] 8002c84: 681b ldr r3, [r3, #0] 8002c86: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8002c88: 697b ldr r3, [r7, #20] 8002c8a: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); 8002c8c: 697b ldr r3, [r7, #20] 8002c8e: 333c adds r3, #60 ; 0x3c 8002c90: 3304 adds r3, #4 8002c92: 681b ldr r3, [r3, #0] 8002c94: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8002c96: 683b ldr r3, [r7, #0] 8002c98: 015a lsls r2, r3, #5 8002c9a: 693b ldr r3, [r7, #16] 8002c9c: 4413 add r3, r2 8002c9e: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002ca2: 689b ldr r3, [r3, #8] 8002ca4: 60bb str r3, [r7, #8] if (hpcd->Init.dma_enable == 1U) 8002ca6: 687b ldr r3, [r7, #4] 8002ca8: 691b ldr r3, [r3, #16] 8002caa: 2b01 cmp r3, #1 8002cac: f040 80a0 bne.w 8002df0 { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 8002cb0: 68bb ldr r3, [r7, #8] 8002cb2: f003 0308 and.w r3, r3, #8 8002cb6: 2b00 cmp r3, #0 8002cb8: d015 beq.n 8002ce6 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002cba: 68fb ldr r3, [r7, #12] 8002cbc: 4a72 ldr r2, [pc, #456] ; (8002e88 ) 8002cbe: 4293 cmp r3, r2 8002cc0: f240 80dd bls.w 8002e7e ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8002cc4: 68bb ldr r3, [r7, #8] 8002cc6: f403 4300 and.w r3, r3, #32768 ; 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002cca: 2b00 cmp r3, #0 8002ccc: f000 80d7 beq.w 8002e7e { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8002cd0: 683b ldr r3, [r7, #0] 8002cd2: 015a lsls r2, r3, #5 8002cd4: 693b ldr r3, [r7, #16] 8002cd6: 4413 add r3, r2 8002cd8: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002cdc: 461a mov r2, r3 8002cde: f44f 4300 mov.w r3, #32768 ; 0x8000 8002ce2: 6093 str r3, [r2, #8] 8002ce4: e0cb b.n 8002e7e } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 8002ce6: 68bb ldr r3, [r7, #8] 8002ce8: f003 0320 and.w r3, r3, #32 8002cec: 2b00 cmp r3, #0 8002cee: d009 beq.n 8002d04 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8002cf0: 683b ldr r3, [r7, #0] 8002cf2: 015a lsls r2, r3, #5 8002cf4: 693b ldr r3, [r7, #16] 8002cf6: 4413 add r3, r2 8002cf8: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002cfc: 461a mov r2, r3 8002cfe: 2320 movs r3, #32 8002d00: 6093 str r3, [r2, #8] 8002d02: e0bc b.n 8002e7e } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 8002d04: 68bb ldr r3, [r7, #8] 8002d06: f003 0328 and.w r3, r3, #40 ; 0x28 8002d0a: 2b00 cmp r3, #0 8002d0c: f040 80b7 bne.w 8002e7e { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002d10: 68fb ldr r3, [r7, #12] 8002d12: 4a5d ldr r2, [pc, #372] ; (8002e88 ) 8002d14: 4293 cmp r3, r2 8002d16: d90f bls.n 8002d38 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8002d18: 68bb ldr r3, [r7, #8] 8002d1a: f403 4300 and.w r3, r3, #32768 ; 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002d1e: 2b00 cmp r3, #0 8002d20: d00a beq.n 8002d38 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8002d22: 683b ldr r3, [r7, #0] 8002d24: 015a lsls r2, r3, #5 8002d26: 693b ldr r3, [r7, #16] 8002d28: 4413 add r3, r2 8002d2a: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002d2e: 461a mov r2, r3 8002d30: f44f 4300 mov.w r3, #32768 ; 0x8000 8002d34: 6093 str r3, [r2, #8] 8002d36: e0a2 b.n 8002e7e } else { /* out data packet received over EP0 */ hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket - 8002d38: 6879 ldr r1, [r7, #4] 8002d3a: 683a ldr r2, [r7, #0] 8002d3c: 4613 mov r3, r2 8002d3e: 00db lsls r3, r3, #3 8002d40: 1a9b subs r3, r3, r2 8002d42: 009b lsls r3, r3, #2 8002d44: 440b add r3, r1 8002d46: f503 7301 add.w r3, r3, #516 ; 0x204 8002d4a: 681a ldr r2, [r3, #0] (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 8002d4c: 683b ldr r3, [r7, #0] 8002d4e: 0159 lsls r1, r3, #5 8002d50: 693b ldr r3, [r7, #16] 8002d52: 440b add r3, r1 8002d54: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002d58: 691b ldr r3, [r3, #16] 8002d5a: f3c3 0312 ubfx r3, r3, #0, #19 hpcd->OUT_ep[epnum].maxpacket - 8002d5e: 1ad1 subs r1, r2, r3 hpcd->OUT_ep[epnum].xfer_count = 8002d60: 6878 ldr r0, [r7, #4] 8002d62: 683a ldr r2, [r7, #0] 8002d64: 4613 mov r3, r2 8002d66: 00db lsls r3, r3, #3 8002d68: 1a9b subs r3, r3, r2 8002d6a: 009b lsls r3, r3, #2 8002d6c: 4403 add r3, r0 8002d6e: f503 7305 add.w r3, r3, #532 ; 0x214 8002d72: 6019 str r1, [r3, #0] hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; 8002d74: 6879 ldr r1, [r7, #4] 8002d76: 683a ldr r2, [r7, #0] 8002d78: 4613 mov r3, r2 8002d7a: 00db lsls r3, r3, #3 8002d7c: 1a9b subs r3, r3, r2 8002d7e: 009b lsls r3, r3, #2 8002d80: 440b add r3, r1 8002d82: f503 7302 add.w r3, r3, #520 ; 0x208 8002d86: 6819 ldr r1, [r3, #0] 8002d88: 6878 ldr r0, [r7, #4] 8002d8a: 683a ldr r2, [r7, #0] 8002d8c: 4613 mov r3, r2 8002d8e: 00db lsls r3, r3, #3 8002d90: 1a9b subs r3, r3, r2 8002d92: 009b lsls r3, r3, #2 8002d94: 4403 add r3, r0 8002d96: f503 7301 add.w r3, r3, #516 ; 0x204 8002d9a: 681b ldr r3, [r3, #0] 8002d9c: 4419 add r1, r3 8002d9e: 6878 ldr r0, [r7, #4] 8002da0: 683a ldr r2, [r7, #0] 8002da2: 4613 mov r3, r2 8002da4: 00db lsls r3, r3, #3 8002da6: 1a9b subs r3, r3, r2 8002da8: 009b lsls r3, r3, #2 8002daa: 4403 add r3, r0 8002dac: f503 7302 add.w r3, r3, #520 ; 0x208 8002db0: 6019 str r1, [r3, #0] if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8002db2: 683b ldr r3, [r7, #0] 8002db4: 2b00 cmp r3, #0 8002db6: d114 bne.n 8002de2 8002db8: 6879 ldr r1, [r7, #4] 8002dba: 683a ldr r2, [r7, #0] 8002dbc: 4613 mov r3, r2 8002dbe: 00db lsls r3, r3, #3 8002dc0: 1a9b subs r3, r3, r2 8002dc2: 009b lsls r3, r3, #2 8002dc4: 440b add r3, r1 8002dc6: f503 7304 add.w r3, r3, #528 ; 0x210 8002dca: 681b ldr r3, [r3, #0] 8002dcc: 2b00 cmp r3, #0 8002dce: d108 bne.n 8002de2 { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8002dd0: 687b ldr r3, [r7, #4] 8002dd2: 6818 ldr r0, [r3, #0] 8002dd4: 687b ldr r3, [r7, #4] 8002dd6: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002dda: 461a mov r2, r3 8002ddc: 2101 movs r1, #1 8002dde: f004 fb19 bl 8007414 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8002de2: 683b ldr r3, [r7, #0] 8002de4: b2db uxtb r3, r3 8002de6: 4619 mov r1, r3 8002de8: 6878 ldr r0, [r7, #4] 8002dea: f006 fabf bl 800936c 8002dee: e046 b.n 8002e7e /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 8002df0: 68fb ldr r3, [r7, #12] 8002df2: 4a26 ldr r2, [pc, #152] ; (8002e8c ) 8002df4: 4293 cmp r3, r2 8002df6: d124 bne.n 8002e42 { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 8002df8: 68bb ldr r3, [r7, #8] 8002dfa: f403 4300 and.w r3, r3, #32768 ; 0x8000 8002dfe: 2b00 cmp r3, #0 8002e00: d00a beq.n 8002e18 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8002e02: 683b ldr r3, [r7, #0] 8002e04: 015a lsls r2, r3, #5 8002e06: 693b ldr r3, [r7, #16] 8002e08: 4413 add r3, r2 8002e0a: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002e0e: 461a mov r2, r3 8002e10: f44f 4300 mov.w r3, #32768 ; 0x8000 8002e14: 6093 str r3, [r2, #8] 8002e16: e032 b.n 8002e7e } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8002e18: 68bb ldr r3, [r7, #8] 8002e1a: f003 0320 and.w r3, r3, #32 8002e1e: 2b00 cmp r3, #0 8002e20: d008 beq.n 8002e34 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8002e22: 683b ldr r3, [r7, #0] 8002e24: 015a lsls r2, r3, #5 8002e26: 693b ldr r3, [r7, #16] 8002e28: 4413 add r3, r2 8002e2a: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002e2e: 461a mov r2, r3 8002e30: 2320 movs r3, #32 8002e32: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8002e34: 683b ldr r3, [r7, #0] 8002e36: b2db uxtb r3, r3 8002e38: 4619 mov r1, r3 8002e3a: 6878 ldr r0, [r7, #4] 8002e3c: f006 fa96 bl 800936c 8002e40: e01d b.n 8002e7e #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8002e42: 683b ldr r3, [r7, #0] 8002e44: 2b00 cmp r3, #0 8002e46: d114 bne.n 8002e72 8002e48: 6879 ldr r1, [r7, #4] 8002e4a: 683a ldr r2, [r7, #0] 8002e4c: 4613 mov r3, r2 8002e4e: 00db lsls r3, r3, #3 8002e50: 1a9b subs r3, r3, r2 8002e52: 009b lsls r3, r3, #2 8002e54: 440b add r3, r1 8002e56: f503 7304 add.w r3, r3, #528 ; 0x210 8002e5a: 681b ldr r3, [r3, #0] 8002e5c: 2b00 cmp r3, #0 8002e5e: d108 bne.n 8002e72 { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 8002e60: 687b ldr r3, [r7, #4] 8002e62: 6818 ldr r0, [r3, #0] 8002e64: 687b ldr r3, [r7, #4] 8002e66: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002e6a: 461a mov r2, r3 8002e6c: 2100 movs r1, #0 8002e6e: f004 fad1 bl 8007414 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8002e72: 683b ldr r3, [r7, #0] 8002e74: b2db uxtb r3, r3 8002e76: 4619 mov r1, r3 8002e78: 6878 ldr r0, [r7, #4] 8002e7a: f006 fa77 bl 800936c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 8002e7e: 2300 movs r3, #0 } 8002e80: 4618 mov r0, r3 8002e82: 3718 adds r7, #24 8002e84: 46bd mov sp, r7 8002e86: bd80 pop {r7, pc} 8002e88: 4f54300a .word 0x4f54300a 8002e8c: 4f54310a .word 0x4f54310a 08002e90 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8002e90: b580 push {r7, lr} 8002e92: b086 sub sp, #24 8002e94: af00 add r7, sp, #0 8002e96: 6078 str r0, [r7, #4] 8002e98: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002e9a: 687b ldr r3, [r7, #4] 8002e9c: 681b ldr r3, [r3, #0] 8002e9e: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8002ea0: 697b ldr r3, [r7, #20] 8002ea2: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); 8002ea4: 697b ldr r3, [r7, #20] 8002ea6: 333c adds r3, #60 ; 0x3c 8002ea8: 3304 adds r3, #4 8002eaa: 681b ldr r3, [r3, #0] 8002eac: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8002eae: 683b ldr r3, [r7, #0] 8002eb0: 015a lsls r2, r3, #5 8002eb2: 693b ldr r3, [r7, #16] 8002eb4: 4413 add r3, r2 8002eb6: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002eba: 689b ldr r3, [r3, #8] 8002ebc: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002ebe: 68fb ldr r3, [r7, #12] 8002ec0: 4a15 ldr r2, [pc, #84] ; (8002f18 ) 8002ec2: 4293 cmp r3, r2 8002ec4: d90e bls.n 8002ee4 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8002ec6: 68bb ldr r3, [r7, #8] 8002ec8: f403 4300 and.w r3, r3, #32768 ; 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002ecc: 2b00 cmp r3, #0 8002ece: d009 beq.n 8002ee4 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8002ed0: 683b ldr r3, [r7, #0] 8002ed2: 015a lsls r2, r3, #5 8002ed4: 693b ldr r3, [r7, #16] 8002ed6: 4413 add r3, r2 8002ed8: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002edc: 461a mov r2, r3 8002ede: f44f 4300 mov.w r3, #32768 ; 0x8000 8002ee2: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 8002ee4: 6878 ldr r0, [r7, #4] 8002ee6: f006 fa2f bl 8009348 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 8002eea: 68fb ldr r3, [r7, #12] 8002eec: 4a0a ldr r2, [pc, #40] ; (8002f18 ) 8002eee: 4293 cmp r3, r2 8002ef0: d90c bls.n 8002f0c 8002ef2: 687b ldr r3, [r7, #4] 8002ef4: 691b ldr r3, [r3, #16] 8002ef6: 2b01 cmp r3, #1 8002ef8: d108 bne.n 8002f0c { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8002efa: 687b ldr r3, [r7, #4] 8002efc: 6818 ldr r0, [r3, #0] 8002efe: 687b ldr r3, [r7, #4] 8002f00: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002f04: 461a mov r2, r3 8002f06: 2101 movs r1, #1 8002f08: f004 fa84 bl 8007414 } return HAL_OK; 8002f0c: 2300 movs r3, #0 } 8002f0e: 4618 mov r0, r3 8002f10: 3718 adds r7, #24 8002f12: 46bd mov sp, r7 8002f14: bd80 pop {r7, pc} 8002f16: bf00 nop 8002f18: 4f54300a .word 0x4f54300a 08002f1c : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 8002f1c: b480 push {r7} 8002f1e: b085 sub sp, #20 8002f20: af00 add r7, sp, #0 8002f22: 6078 str r0, [r7, #4] 8002f24: 460b mov r3, r1 8002f26: 70fb strb r3, [r7, #3] 8002f28: 4613 mov r3, r2 8002f2a: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 8002f2c: 687b ldr r3, [r7, #4] 8002f2e: 681b ldr r3, [r3, #0] 8002f30: 6a5b ldr r3, [r3, #36] ; 0x24 8002f32: 60bb str r3, [r7, #8] if (fifo == 0U) 8002f34: 78fb ldrb r3, [r7, #3] 8002f36: 2b00 cmp r3, #0 8002f38: d107 bne.n 8002f4a { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 8002f3a: 883b ldrh r3, [r7, #0] 8002f3c: 0419 lsls r1, r3, #16 8002f3e: 687b ldr r3, [r7, #4] 8002f40: 681b ldr r3, [r3, #0] 8002f42: 68ba ldr r2, [r7, #8] 8002f44: 430a orrs r2, r1 8002f46: 629a str r2, [r3, #40] ; 0x28 8002f48: e028 b.n 8002f9c } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 8002f4a: 687b ldr r3, [r7, #4] 8002f4c: 681b ldr r3, [r3, #0] 8002f4e: 6a9b ldr r3, [r3, #40] ; 0x28 8002f50: 0c1b lsrs r3, r3, #16 8002f52: 68ba ldr r2, [r7, #8] 8002f54: 4413 add r3, r2 8002f56: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8002f58: 2300 movs r3, #0 8002f5a: 73fb strb r3, [r7, #15] 8002f5c: e00d b.n 8002f7a { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 8002f5e: 687b ldr r3, [r7, #4] 8002f60: 681a ldr r2, [r3, #0] 8002f62: 7bfb ldrb r3, [r7, #15] 8002f64: 3340 adds r3, #64 ; 0x40 8002f66: 009b lsls r3, r3, #2 8002f68: 4413 add r3, r2 8002f6a: 685b ldr r3, [r3, #4] 8002f6c: 0c1b lsrs r3, r3, #16 8002f6e: 68ba ldr r2, [r7, #8] 8002f70: 4413 add r3, r2 8002f72: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8002f74: 7bfb ldrb r3, [r7, #15] 8002f76: 3301 adds r3, #1 8002f78: 73fb strb r3, [r7, #15] 8002f7a: 7bfa ldrb r2, [r7, #15] 8002f7c: 78fb ldrb r3, [r7, #3] 8002f7e: 3b01 subs r3, #1 8002f80: 429a cmp r2, r3 8002f82: d3ec bcc.n 8002f5e } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 8002f84: 883b ldrh r3, [r7, #0] 8002f86: 0418 lsls r0, r3, #16 8002f88: 687b ldr r3, [r7, #4] 8002f8a: 6819 ldr r1, [r3, #0] 8002f8c: 78fb ldrb r3, [r7, #3] 8002f8e: 3b01 subs r3, #1 8002f90: 68ba ldr r2, [r7, #8] 8002f92: 4302 orrs r2, r0 8002f94: 3340 adds r3, #64 ; 0x40 8002f96: 009b lsls r3, r3, #2 8002f98: 440b add r3, r1 8002f9a: 605a str r2, [r3, #4] } return HAL_OK; 8002f9c: 2300 movs r3, #0 } 8002f9e: 4618 mov r0, r3 8002fa0: 3714 adds r7, #20 8002fa2: 46bd mov sp, r7 8002fa4: f85d 7b04 ldr.w r7, [sp], #4 8002fa8: 4770 bx lr 08002faa : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 8002faa: b480 push {r7} 8002fac: b083 sub sp, #12 8002fae: af00 add r7, sp, #0 8002fb0: 6078 str r0, [r7, #4] 8002fb2: 460b mov r3, r1 8002fb4: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 8002fb6: 687b ldr r3, [r7, #4] 8002fb8: 681b ldr r3, [r3, #0] 8002fba: 887a ldrh r2, [r7, #2] 8002fbc: 625a str r2, [r3, #36] ; 0x24 return HAL_OK; 8002fbe: 2300 movs r3, #0 } 8002fc0: 4618 mov r0, r3 8002fc2: 370c adds r7, #12 8002fc4: 46bd mov sp, r7 8002fc6: f85d 7b04 ldr.w r7, [sp], #4 8002fca: 4770 bx lr 08002fcc : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 8002fcc: b480 push {r7} 8002fce: b085 sub sp, #20 8002fd0: af00 add r7, sp, #0 8002fd2: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002fd4: 687b ldr r3, [r7, #4] 8002fd6: 681b ldr r3, [r3, #0] 8002fd8: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 8002fda: 687b ldr r3, [r7, #4] 8002fdc: 2201 movs r2, #1 8002fde: f8c3 23fc str.w r2, [r3, #1020] ; 0x3fc hpcd->LPM_State = LPM_L0; 8002fe2: 687b ldr r3, [r7, #4] 8002fe4: 2200 movs r2, #0 8002fe6: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4 USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 8002fea: 68fb ldr r3, [r7, #12] 8002fec: 699b ldr r3, [r3, #24] 8002fee: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000 8002ff2: 68fb ldr r3, [r7, #12] 8002ff4: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 8002ff6: 68fb ldr r3, [r7, #12] 8002ff8: 6d5a ldr r2, [r3, #84] ; 0x54 8002ffa: 4b05 ldr r3, [pc, #20] ; (8003010 ) 8002ffc: 4313 orrs r3, r2 8002ffe: 68fa ldr r2, [r7, #12] 8003000: 6553 str r3, [r2, #84] ; 0x54 return HAL_OK; 8003002: 2300 movs r3, #0 } 8003004: 4618 mov r0, r3 8003006: 3714 adds r7, #20 8003008: 46bd mov sp, r7 800300a: f85d 7b04 ldr.w r7, [sp], #4 800300e: 4770 bx lr 8003010: 10000003 .word 0x10000003 08003014 : * @param hpcd PCD handle * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 8003014: b480 push {r7} 8003016: b083 sub sp, #12 8003018: af00 add r7, sp, #0 800301a: 6078 str r0, [r7, #4] 800301c: 460b mov r3, r1 800301e: 70fb strb r3, [r7, #3] UNUSED(msg); /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCDEx_LPM_Callback could be implemented in the user file */ } 8003020: bf00 nop 8003022: 370c adds r7, #12 8003024: 46bd mov sp, r7 8003026: f85d 7b04 ldr.w r7, [sp], #4 800302a: 4770 bx lr 0800302c : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 800302c: b580 push {r7, lr} 800302e: b084 sub sp, #16 8003030: af00 add r7, sp, #0 8003032: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 8003034: 4b19 ldr r3, [pc, #100] ; (800309c ) 8003036: 68db ldr r3, [r3, #12] 8003038: f003 0304 and.w r3, r3, #4 800303c: 2b04 cmp r3, #4 800303e: d00a beq.n 8003056 #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 8003040: 4b16 ldr r3, [pc, #88] ; (800309c ) 8003042: 68db ldr r3, [r3, #12] 8003044: f003 0307 and.w r3, r3, #7 8003048: 687a ldr r2, [r7, #4] 800304a: 429a cmp r2, r3 800304c: d001 beq.n 8003052 { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800304e: 2301 movs r3, #1 8003050: e01f b.n 8003092 else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 8003052: 2300 movs r3, #0 8003054: e01d b.n 8003092 } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 8003056: 4b11 ldr r3, [pc, #68] ; (800309c ) 8003058: 68db ldr r3, [r3, #12] 800305a: f023 0207 bic.w r2, r3, #7 800305e: 490f ldr r1, [pc, #60] ; (800309c ) 8003060: 687b ldr r3, [r7, #4] 8003062: 4313 orrs r3, r2 8003064: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 8003066: f7fe faf7 bl 8001658 800306a: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800306c: e009 b.n 8003082 { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800306e: f7fe faf3 bl 8001658 8003072: 4602 mov r2, r0 8003074: 68fb ldr r3, [r7, #12] 8003076: 1ad3 subs r3, r2, r3 8003078: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 800307c: d901 bls.n 8003082 { return HAL_ERROR; 800307e: 2301 movs r3, #1 8003080: e007 b.n 8003092 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 8003082: 4b06 ldr r3, [pc, #24] ; (800309c ) 8003084: 685b ldr r3, [r3, #4] 8003086: f403 5300 and.w r3, r3, #8192 ; 0x2000 800308a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800308e: d1ee bne.n 800306e } } } #endif /* defined (SMPS) */ return HAL_OK; 8003090: 2300 movs r3, #0 } 8003092: 4618 mov r0, r3 8003094: 3710 adds r7, #16 8003096: 46bd mov sp, r7 8003098: bd80 pop {r7, pc} 800309a: bf00 nop 800309c: 58024800 .word 0x58024800 080030a0 : /** * @brief Enable the USB voltage level detector. * @retval None. */ void HAL_PWREx_EnableUSBVoltageDetector (void) { 80030a0: b480 push {r7} 80030a2: af00 add r7, sp, #0 /* Enable the USB voltage detector */ SET_BIT (PWR->CR3, PWR_CR3_USB33DEN); 80030a4: 4b05 ldr r3, [pc, #20] ; (80030bc ) 80030a6: 68db ldr r3, [r3, #12] 80030a8: 4a04 ldr r2, [pc, #16] ; (80030bc ) 80030aa: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 80030ae: 60d3 str r3, [r2, #12] } 80030b0: bf00 nop 80030b2: 46bd mov sp, r7 80030b4: f85d 7b04 ldr.w r7, [sp], #4 80030b8: 4770 bx lr 80030ba: bf00 nop 80030bc: 58024800 .word 0x58024800 080030c0 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80030c0: b580 push {r7, lr} 80030c2: b08c sub sp, #48 ; 0x30 80030c4: af00 add r7, sp, #0 80030c6: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 80030c8: 687b ldr r3, [r7, #4] 80030ca: 2b00 cmp r3, #0 80030cc: d101 bne.n 80030d2 { return HAL_ERROR; 80030ce: 2301 movs r3, #1 80030d0: e397 b.n 8003802 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80030d2: 687b ldr r3, [r7, #4] 80030d4: 681b ldr r3, [r3, #0] 80030d6: f003 0301 and.w r3, r3, #1 80030da: 2b00 cmp r3, #0 80030dc: f000 8087 beq.w 80031ee { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80030e0: 4b9e ldr r3, [pc, #632] ; (800335c ) 80030e2: 691b ldr r3, [r3, #16] 80030e4: f003 0338 and.w r3, r3, #56 ; 0x38 80030e8: 62fb str r3, [r7, #44] ; 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 80030ea: 4b9c ldr r3, [pc, #624] ; (800335c ) 80030ec: 6a9b ldr r3, [r3, #40] ; 0x28 80030ee: 62bb str r3, [r7, #40] ; 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 80030f0: 6afb ldr r3, [r7, #44] ; 0x2c 80030f2: 2b10 cmp r3, #16 80030f4: d007 beq.n 8003106 80030f6: 6afb ldr r3, [r7, #44] ; 0x2c 80030f8: 2b18 cmp r3, #24 80030fa: d110 bne.n 800311e 80030fc: 6abb ldr r3, [r7, #40] ; 0x28 80030fe: f003 0303 and.w r3, r3, #3 8003102: 2b02 cmp r3, #2 8003104: d10b bne.n 800311e { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003106: 4b95 ldr r3, [pc, #596] ; (800335c ) 8003108: 681b ldr r3, [r3, #0] 800310a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800310e: 2b00 cmp r3, #0 8003110: d06c beq.n 80031ec 8003112: 687b ldr r3, [r7, #4] 8003114: 685b ldr r3, [r3, #4] 8003116: 2b00 cmp r3, #0 8003118: d168 bne.n 80031ec { return HAL_ERROR; 800311a: 2301 movs r3, #1 800311c: e371 b.n 8003802 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800311e: 687b ldr r3, [r7, #4] 8003120: 685b ldr r3, [r3, #4] 8003122: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003126: d106 bne.n 8003136 8003128: 4b8c ldr r3, [pc, #560] ; (800335c ) 800312a: 681b ldr r3, [r3, #0] 800312c: 4a8b ldr r2, [pc, #556] ; (800335c ) 800312e: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003132: 6013 str r3, [r2, #0] 8003134: e02e b.n 8003194 8003136: 687b ldr r3, [r7, #4] 8003138: 685b ldr r3, [r3, #4] 800313a: 2b00 cmp r3, #0 800313c: d10c bne.n 8003158 800313e: 4b87 ldr r3, [pc, #540] ; (800335c ) 8003140: 681b ldr r3, [r3, #0] 8003142: 4a86 ldr r2, [pc, #536] ; (800335c ) 8003144: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8003148: 6013 str r3, [r2, #0] 800314a: 4b84 ldr r3, [pc, #528] ; (800335c ) 800314c: 681b ldr r3, [r3, #0] 800314e: 4a83 ldr r2, [pc, #524] ; (800335c ) 8003150: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003154: 6013 str r3, [r2, #0] 8003156: e01d b.n 8003194 8003158: 687b ldr r3, [r7, #4] 800315a: 685b ldr r3, [r3, #4] 800315c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8003160: d10c bne.n 800317c 8003162: 4b7e ldr r3, [pc, #504] ; (800335c ) 8003164: 681b ldr r3, [r3, #0] 8003166: 4a7d ldr r2, [pc, #500] ; (800335c ) 8003168: f443 2380 orr.w r3, r3, #262144 ; 0x40000 800316c: 6013 str r3, [r2, #0] 800316e: 4b7b ldr r3, [pc, #492] ; (800335c ) 8003170: 681b ldr r3, [r3, #0] 8003172: 4a7a ldr r2, [pc, #488] ; (800335c ) 8003174: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003178: 6013 str r3, [r2, #0] 800317a: e00b b.n 8003194 800317c: 4b77 ldr r3, [pc, #476] ; (800335c ) 800317e: 681b ldr r3, [r3, #0] 8003180: 4a76 ldr r2, [pc, #472] ; (800335c ) 8003182: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8003186: 6013 str r3, [r2, #0] 8003188: 4b74 ldr r3, [pc, #464] ; (800335c ) 800318a: 681b ldr r3, [r3, #0] 800318c: 4a73 ldr r2, [pc, #460] ; (800335c ) 800318e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003192: 6013 str r3, [r2, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8003194: 687b ldr r3, [r7, #4] 8003196: 685b ldr r3, [r3, #4] 8003198: 2b00 cmp r3, #0 800319a: d013 beq.n 80031c4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800319c: f7fe fa5c bl 8001658 80031a0: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80031a2: e008 b.n 80031b6 { if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80031a4: f7fe fa58 bl 8001658 80031a8: 4602 mov r2, r0 80031aa: 6a7b ldr r3, [r7, #36] ; 0x24 80031ac: 1ad3 subs r3, r2, r3 80031ae: 2b64 cmp r3, #100 ; 0x64 80031b0: d901 bls.n 80031b6 { return HAL_TIMEOUT; 80031b2: 2303 movs r3, #3 80031b4: e325 b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80031b6: 4b69 ldr r3, [pc, #420] ; (800335c ) 80031b8: 681b ldr r3, [r3, #0] 80031ba: f403 3300 and.w r3, r3, #131072 ; 0x20000 80031be: 2b00 cmp r3, #0 80031c0: d0f0 beq.n 80031a4 80031c2: e014 b.n 80031ee } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80031c4: f7fe fa48 bl 8001658 80031c8: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 80031ca: e008 b.n 80031de { if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80031cc: f7fe fa44 bl 8001658 80031d0: 4602 mov r2, r0 80031d2: 6a7b ldr r3, [r7, #36] ; 0x24 80031d4: 1ad3 subs r3, r2, r3 80031d6: 2b64 cmp r3, #100 ; 0x64 80031d8: d901 bls.n 80031de { return HAL_TIMEOUT; 80031da: 2303 movs r3, #3 80031dc: e311 b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 80031de: 4b5f ldr r3, [pc, #380] ; (800335c ) 80031e0: 681b ldr r3, [r3, #0] 80031e2: f403 3300 and.w r3, r3, #131072 ; 0x20000 80031e6: 2b00 cmp r3, #0 80031e8: d1f0 bne.n 80031cc 80031ea: e000 b.n 80031ee if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80031ec: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80031ee: 687b ldr r3, [r7, #4] 80031f0: 681b ldr r3, [r3, #0] 80031f2: f003 0302 and.w r3, r3, #2 80031f6: 2b00 cmp r3, #0 80031f8: f000 808a beq.w 8003310 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80031fc: 4b57 ldr r3, [pc, #348] ; (800335c ) 80031fe: 691b ldr r3, [r3, #16] 8003200: f003 0338 and.w r3, r3, #56 ; 0x38 8003204: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8003206: 4b55 ldr r3, [pc, #340] ; (800335c ) 8003208: 6a9b ldr r3, [r3, #40] ; 0x28 800320a: 61fb str r3, [r7, #28] if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 800320c: 6a3b ldr r3, [r7, #32] 800320e: 2b00 cmp r3, #0 8003210: d007 beq.n 8003222 8003212: 6a3b ldr r3, [r7, #32] 8003214: 2b18 cmp r3, #24 8003216: d137 bne.n 8003288 8003218: 69fb ldr r3, [r7, #28] 800321a: f003 0303 and.w r3, r3, #3 800321e: 2b00 cmp r3, #0 8003220: d132 bne.n 8003288 { /* When HSI is used as system clock it will not be disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8003222: 4b4e ldr r3, [pc, #312] ; (800335c ) 8003224: 681b ldr r3, [r3, #0] 8003226: f003 0304 and.w r3, r3, #4 800322a: 2b00 cmp r3, #0 800322c: d005 beq.n 800323a 800322e: 687b ldr r3, [r7, #4] 8003230: 68db ldr r3, [r3, #12] 8003232: 2b00 cmp r3, #0 8003234: d101 bne.n 800323a { return HAL_ERROR; 8003236: 2301 movs r3, #1 8003238: e2e3 b.n 8003802 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800323a: 4b48 ldr r3, [pc, #288] ; (800335c ) 800323c: 681b ldr r3, [r3, #0] 800323e: f023 0219 bic.w r2, r3, #25 8003242: 687b ldr r3, [r7, #4] 8003244: 68db ldr r3, [r3, #12] 8003246: 4945 ldr r1, [pc, #276] ; (800335c ) 8003248: 4313 orrs r3, r2 800324a: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800324c: f7fe fa04 bl 8001658 8003250: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8003252: e008 b.n 8003266 { if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8003254: f7fe fa00 bl 8001658 8003258: 4602 mov r2, r0 800325a: 6a7b ldr r3, [r7, #36] ; 0x24 800325c: 1ad3 subs r3, r2, r3 800325e: 2b02 cmp r3, #2 8003260: d901 bls.n 8003266 { return HAL_TIMEOUT; 8003262: 2303 movs r3, #3 8003264: e2cd b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8003266: 4b3d ldr r3, [pc, #244] ; (800335c ) 8003268: 681b ldr r3, [r3, #0] 800326a: f003 0304 and.w r3, r3, #4 800326e: 2b00 cmp r3, #0 8003270: d0f0 beq.n 8003254 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003272: 4b3a ldr r3, [pc, #232] ; (800335c ) 8003274: 685b ldr r3, [r3, #4] 8003276: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 800327a: 687b ldr r3, [r7, #4] 800327c: 691b ldr r3, [r3, #16] 800327e: 061b lsls r3, r3, #24 8003280: 4936 ldr r1, [pc, #216] ; (800335c ) 8003282: 4313 orrs r3, r2 8003284: 604b str r3, [r1, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8003286: e043 b.n 8003310 } else { /* Check the HSI State */ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) 8003288: 687b ldr r3, [r7, #4] 800328a: 68db ldr r3, [r3, #12] 800328c: 2b00 cmp r3, #0 800328e: d026 beq.n 80032de { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 8003290: 4b32 ldr r3, [pc, #200] ; (800335c ) 8003292: 681b ldr r3, [r3, #0] 8003294: f023 0219 bic.w r2, r3, #25 8003298: 687b ldr r3, [r7, #4] 800329a: 68db ldr r3, [r3, #12] 800329c: 492f ldr r1, [pc, #188] ; (800335c ) 800329e: 4313 orrs r3, r2 80032a0: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80032a2: f7fe f9d9 bl 8001658 80032a6: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80032a8: e008 b.n 80032bc { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 80032aa: f7fe f9d5 bl 8001658 80032ae: 4602 mov r2, r0 80032b0: 6a7b ldr r3, [r7, #36] ; 0x24 80032b2: 1ad3 subs r3, r2, r3 80032b4: 2b02 cmp r3, #2 80032b6: d901 bls.n 80032bc { return HAL_TIMEOUT; 80032b8: 2303 movs r3, #3 80032ba: e2a2 b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80032bc: 4b27 ldr r3, [pc, #156] ; (800335c ) 80032be: 681b ldr r3, [r3, #0] 80032c0: f003 0304 and.w r3, r3, #4 80032c4: 2b00 cmp r3, #0 80032c6: d0f0 beq.n 80032aa } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80032c8: 4b24 ldr r3, [pc, #144] ; (800335c ) 80032ca: 685b ldr r3, [r3, #4] 80032cc: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 80032d0: 687b ldr r3, [r7, #4] 80032d2: 691b ldr r3, [r3, #16] 80032d4: 061b lsls r3, r3, #24 80032d6: 4921 ldr r1, [pc, #132] ; (800335c ) 80032d8: 4313 orrs r3, r2 80032da: 604b str r3, [r1, #4] 80032dc: e018 b.n 8003310 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80032de: 4b1f ldr r3, [pc, #124] ; (800335c ) 80032e0: 681b ldr r3, [r3, #0] 80032e2: 4a1e ldr r2, [pc, #120] ; (800335c ) 80032e4: f023 0301 bic.w r3, r3, #1 80032e8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80032ea: f7fe f9b5 bl 8001658 80032ee: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 80032f0: e008 b.n 8003304 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 80032f2: f7fe f9b1 bl 8001658 80032f6: 4602 mov r2, r0 80032f8: 6a7b ldr r3, [r7, #36] ; 0x24 80032fa: 1ad3 subs r3, r2, r3 80032fc: 2b02 cmp r3, #2 80032fe: d901 bls.n 8003304 { return HAL_TIMEOUT; 8003300: 2303 movs r3, #3 8003302: e27e b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8003304: 4b15 ldr r3, [pc, #84] ; (800335c ) 8003306: 681b ldr r3, [r3, #0] 8003308: f003 0304 and.w r3, r3, #4 800330c: 2b00 cmp r3, #0 800330e: d1f0 bne.n 80032f2 } } } } /*----------------------------- CSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 8003310: 687b ldr r3, [r7, #4] 8003312: 681b ldr r3, [r3, #0] 8003314: f003 0310 and.w r3, r3, #16 8003318: 2b00 cmp r3, #0 800331a: d06d beq.n 80033f8 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800331c: 4b0f ldr r3, [pc, #60] ; (800335c ) 800331e: 691b ldr r3, [r3, #16] 8003320: f003 0338 and.w r3, r3, #56 ; 0x38 8003324: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8003326: 4b0d ldr r3, [pc, #52] ; (800335c ) 8003328: 6a9b ldr r3, [r3, #40] ; 0x28 800332a: 617b str r3, [r7, #20] if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800332c: 69bb ldr r3, [r7, #24] 800332e: 2b08 cmp r3, #8 8003330: d007 beq.n 8003342 8003332: 69bb ldr r3, [r7, #24] 8003334: 2b18 cmp r3, #24 8003336: d11e bne.n 8003376 8003338: 697b ldr r3, [r7, #20] 800333a: f003 0303 and.w r3, r3, #3 800333e: 2b01 cmp r3, #1 8003340: d119 bne.n 8003376 { /* When CSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 8003342: 4b06 ldr r3, [pc, #24] ; (800335c ) 8003344: 681b ldr r3, [r3, #0] 8003346: f403 7380 and.w r3, r3, #256 ; 0x100 800334a: 2b00 cmp r3, #0 800334c: d008 beq.n 8003360 800334e: 687b ldr r3, [r7, #4] 8003350: 69db ldr r3, [r3, #28] 8003352: 2b80 cmp r3, #128 ; 0x80 8003354: d004 beq.n 8003360 { return HAL_ERROR; 8003356: 2301 movs r3, #1 8003358: e253 b.n 8003802 800335a: bf00 nop 800335c: 58024400 .word 0x58024400 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 8003360: 4ba3 ldr r3, [pc, #652] ; (80035f0 ) 8003362: 68db ldr r3, [r3, #12] 8003364: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 8003368: 687b ldr r3, [r7, #4] 800336a: 6a1b ldr r3, [r3, #32] 800336c: 061b lsls r3, r3, #24 800336e: 49a0 ldr r1, [pc, #640] ; (80035f0 ) 8003370: 4313 orrs r3, r2 8003372: 60cb str r3, [r1, #12] if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 8003374: e040 b.n 80033f8 } } else { /* Check the CSI State */ if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF) 8003376: 687b ldr r3, [r7, #4] 8003378: 69db ldr r3, [r3, #28] 800337a: 2b00 cmp r3, #0 800337c: d023 beq.n 80033c6 { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 800337e: 4b9c ldr r3, [pc, #624] ; (80035f0 ) 8003380: 681b ldr r3, [r3, #0] 8003382: 4a9b ldr r2, [pc, #620] ; (80035f0 ) 8003384: f043 0380 orr.w r3, r3, #128 ; 0x80 8003388: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800338a: f7fe f965 bl 8001658 800338e: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8003390: e008 b.n 80033a4 { if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) 8003392: f7fe f961 bl 8001658 8003396: 4602 mov r2, r0 8003398: 6a7b ldr r3, [r7, #36] ; 0x24 800339a: 1ad3 subs r3, r2, r3 800339c: 2b02 cmp r3, #2 800339e: d901 bls.n 80033a4 { return HAL_TIMEOUT; 80033a0: 2303 movs r3, #3 80033a2: e22e b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80033a4: 4b92 ldr r3, [pc, #584] ; (80035f0 ) 80033a6: 681b ldr r3, [r3, #0] 80033a8: f403 7380 and.w r3, r3, #256 ; 0x100 80033ac: 2b00 cmp r3, #0 80033ae: d0f0 beq.n 8003392 } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80033b0: 4b8f ldr r3, [pc, #572] ; (80035f0 ) 80033b2: 68db ldr r3, [r3, #12] 80033b4: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 80033b8: 687b ldr r3, [r7, #4] 80033ba: 6a1b ldr r3, [r3, #32] 80033bc: 061b lsls r3, r3, #24 80033be: 498c ldr r1, [pc, #560] ; (80035f0 ) 80033c0: 4313 orrs r3, r2 80033c2: 60cb str r3, [r1, #12] 80033c4: e018 b.n 80033f8 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 80033c6: 4b8a ldr r3, [pc, #552] ; (80035f0 ) 80033c8: 681b ldr r3, [r3, #0] 80033ca: 4a89 ldr r2, [pc, #548] ; (80035f0 ) 80033cc: f023 0380 bic.w r3, r3, #128 ; 0x80 80033d0: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80033d2: f7fe f941 bl 8001658 80033d6: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 80033d8: e008 b.n 80033ec { if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) 80033da: f7fe f93d bl 8001658 80033de: 4602 mov r2, r0 80033e0: 6a7b ldr r3, [r7, #36] ; 0x24 80033e2: 1ad3 subs r3, r2, r3 80033e4: 2b02 cmp r3, #2 80033e6: d901 bls.n 80033ec { return HAL_TIMEOUT; 80033e8: 2303 movs r3, #3 80033ea: e20a b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 80033ec: 4b80 ldr r3, [pc, #512] ; (80035f0 ) 80033ee: 681b ldr r3, [r3, #0] 80033f0: f403 7380 and.w r3, r3, #256 ; 0x100 80033f4: 2b00 cmp r3, #0 80033f6: d1f0 bne.n 80033da } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80033f8: 687b ldr r3, [r7, #4] 80033fa: 681b ldr r3, [r3, #0] 80033fc: f003 0308 and.w r3, r3, #8 8003400: 2b00 cmp r3, #0 8003402: d036 beq.n 8003472 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) 8003404: 687b ldr r3, [r7, #4] 8003406: 695b ldr r3, [r3, #20] 8003408: 2b00 cmp r3, #0 800340a: d019 beq.n 8003440 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800340c: 4b78 ldr r3, [pc, #480] ; (80035f0 ) 800340e: 6f5b ldr r3, [r3, #116] ; 0x74 8003410: 4a77 ldr r2, [pc, #476] ; (80035f0 ) 8003412: f043 0301 orr.w r3, r3, #1 8003416: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003418: f7fe f91e bl 8001658 800341c: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800341e: e008 b.n 8003432 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8003420: f7fe f91a bl 8001658 8003424: 4602 mov r2, r0 8003426: 6a7b ldr r3, [r7, #36] ; 0x24 8003428: 1ad3 subs r3, r2, r3 800342a: 2b02 cmp r3, #2 800342c: d901 bls.n 8003432 { return HAL_TIMEOUT; 800342e: 2303 movs r3, #3 8003430: e1e7 b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 8003432: 4b6f ldr r3, [pc, #444] ; (80035f0 ) 8003434: 6f5b ldr r3, [r3, #116] ; 0x74 8003436: f003 0302 and.w r3, r3, #2 800343a: 2b00 cmp r3, #0 800343c: d0f0 beq.n 8003420 800343e: e018 b.n 8003472 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8003440: 4b6b ldr r3, [pc, #428] ; (80035f0 ) 8003442: 6f5b ldr r3, [r3, #116] ; 0x74 8003444: 4a6a ldr r2, [pc, #424] ; (80035f0 ) 8003446: f023 0301 bic.w r3, r3, #1 800344a: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800344c: f7fe f904 bl 8001658 8003450: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8003452: e008 b.n 8003466 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8003454: f7fe f900 bl 8001658 8003458: 4602 mov r2, r0 800345a: 6a7b ldr r3, [r7, #36] ; 0x24 800345c: 1ad3 subs r3, r2, r3 800345e: 2b02 cmp r3, #2 8003460: d901 bls.n 8003466 { return HAL_TIMEOUT; 8003462: 2303 movs r3, #3 8003464: e1cd b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8003466: 4b62 ldr r3, [pc, #392] ; (80035f0 ) 8003468: 6f5b ldr r3, [r3, #116] ; 0x74 800346a: f003 0302 and.w r3, r3, #2 800346e: 2b00 cmp r3, #0 8003470: d1f0 bne.n 8003454 } } } /*------------------------------ HSI48 Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 8003472: 687b ldr r3, [r7, #4] 8003474: 681b ldr r3, [r3, #0] 8003476: f003 0320 and.w r3, r3, #32 800347a: 2b00 cmp r3, #0 800347c: d036 beq.n 80034ec { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF) 800347e: 687b ldr r3, [r7, #4] 8003480: 699b ldr r3, [r3, #24] 8003482: 2b00 cmp r3, #0 8003484: d019 beq.n 80034ba { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 8003486: 4b5a ldr r3, [pc, #360] ; (80035f0 ) 8003488: 681b ldr r3, [r3, #0] 800348a: 4a59 ldr r2, [pc, #356] ; (80035f0 ) 800348c: f443 5380 orr.w r3, r3, #4096 ; 0x1000 8003490: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 8003492: f7fe f8e1 bl 8001658 8003496: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 8003498: e008 b.n 80034ac { if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) 800349a: f7fe f8dd bl 8001658 800349e: 4602 mov r2, r0 80034a0: 6a7b ldr r3, [r7, #36] ; 0x24 80034a2: 1ad3 subs r3, r2, r3 80034a4: 2b02 cmp r3, #2 80034a6: d901 bls.n 80034ac { return HAL_TIMEOUT; 80034a8: 2303 movs r3, #3 80034aa: e1aa b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 80034ac: 4b50 ldr r3, [pc, #320] ; (80035f0 ) 80034ae: 681b ldr r3, [r3, #0] 80034b0: f403 5300 and.w r3, r3, #8192 ; 0x2000 80034b4: 2b00 cmp r3, #0 80034b6: d0f0 beq.n 800349a 80034b8: e018 b.n 80034ec } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 80034ba: 4b4d ldr r3, [pc, #308] ; (80035f0 ) 80034bc: 681b ldr r3, [r3, #0] 80034be: 4a4c ldr r2, [pc, #304] ; (80035f0 ) 80034c0: f423 5380 bic.w r3, r3, #4096 ; 0x1000 80034c4: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 80034c6: f7fe f8c7 bl 8001658 80034ca: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 80034cc: e008 b.n 80034e0 { if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) 80034ce: f7fe f8c3 bl 8001658 80034d2: 4602 mov r2, r0 80034d4: 6a7b ldr r3, [r7, #36] ; 0x24 80034d6: 1ad3 subs r3, r2, r3 80034d8: 2b02 cmp r3, #2 80034da: d901 bls.n 80034e0 { return HAL_TIMEOUT; 80034dc: 2303 movs r3, #3 80034de: e190 b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 80034e0: 4b43 ldr r3, [pc, #268] ; (80035f0 ) 80034e2: 681b ldr r3, [r3, #0] 80034e4: f403 5300 and.w r3, r3, #8192 ; 0x2000 80034e8: 2b00 cmp r3, #0 80034ea: d1f0 bne.n 80034ce } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80034ec: 687b ldr r3, [r7, #4] 80034ee: 681b ldr r3, [r3, #0] 80034f0: f003 0304 and.w r3, r3, #4 80034f4: 2b00 cmp r3, #0 80034f6: f000 8085 beq.w 8003604 { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 80034fa: 4b3e ldr r3, [pc, #248] ; (80035f4 ) 80034fc: 681b ldr r3, [r3, #0] 80034fe: 4a3d ldr r2, [pc, #244] ; (80035f4 ) 8003500: f443 7380 orr.w r3, r3, #256 ; 0x100 8003504: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003506: f7fe f8a7 bl 8001658 800350a: 6278 str r0, [r7, #36] ; 0x24 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 800350c: e008 b.n 8003520 { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) 800350e: f7fe f8a3 bl 8001658 8003512: 4602 mov r2, r0 8003514: 6a7b ldr r3, [r7, #36] ; 0x24 8003516: 1ad3 subs r3, r2, r3 8003518: 2b64 cmp r3, #100 ; 0x64 800351a: d901 bls.n 8003520 { return HAL_TIMEOUT; 800351c: 2303 movs r3, #3 800351e: e170 b.n 8003802 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003520: 4b34 ldr r3, [pc, #208] ; (80035f4 ) 8003522: 681b ldr r3, [r3, #0] 8003524: f403 7380 and.w r3, r3, #256 ; 0x100 8003528: 2b00 cmp r3, #0 800352a: d0f0 beq.n 800350e } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800352c: 687b ldr r3, [r7, #4] 800352e: 689b ldr r3, [r3, #8] 8003530: 2b01 cmp r3, #1 8003532: d106 bne.n 8003542 8003534: 4b2e ldr r3, [pc, #184] ; (80035f0 ) 8003536: 6f1b ldr r3, [r3, #112] ; 0x70 8003538: 4a2d ldr r2, [pc, #180] ; (80035f0 ) 800353a: f043 0301 orr.w r3, r3, #1 800353e: 6713 str r3, [r2, #112] ; 0x70 8003540: e02d b.n 800359e 8003542: 687b ldr r3, [r7, #4] 8003544: 689b ldr r3, [r3, #8] 8003546: 2b00 cmp r3, #0 8003548: d10c bne.n 8003564 800354a: 4b29 ldr r3, [pc, #164] ; (80035f0 ) 800354c: 6f1b ldr r3, [r3, #112] ; 0x70 800354e: 4a28 ldr r2, [pc, #160] ; (80035f0 ) 8003550: f023 0301 bic.w r3, r3, #1 8003554: 6713 str r3, [r2, #112] ; 0x70 8003556: 4b26 ldr r3, [pc, #152] ; (80035f0 ) 8003558: 6f1b ldr r3, [r3, #112] ; 0x70 800355a: 4a25 ldr r2, [pc, #148] ; (80035f0 ) 800355c: f023 0304 bic.w r3, r3, #4 8003560: 6713 str r3, [r2, #112] ; 0x70 8003562: e01c b.n 800359e 8003564: 687b ldr r3, [r7, #4] 8003566: 689b ldr r3, [r3, #8] 8003568: 2b05 cmp r3, #5 800356a: d10c bne.n 8003586 800356c: 4b20 ldr r3, [pc, #128] ; (80035f0 ) 800356e: 6f1b ldr r3, [r3, #112] ; 0x70 8003570: 4a1f ldr r2, [pc, #124] ; (80035f0 ) 8003572: f043 0304 orr.w r3, r3, #4 8003576: 6713 str r3, [r2, #112] ; 0x70 8003578: 4b1d ldr r3, [pc, #116] ; (80035f0 ) 800357a: 6f1b ldr r3, [r3, #112] ; 0x70 800357c: 4a1c ldr r2, [pc, #112] ; (80035f0 ) 800357e: f043 0301 orr.w r3, r3, #1 8003582: 6713 str r3, [r2, #112] ; 0x70 8003584: e00b b.n 800359e 8003586: 4b1a ldr r3, [pc, #104] ; (80035f0 ) 8003588: 6f1b ldr r3, [r3, #112] ; 0x70 800358a: 4a19 ldr r2, [pc, #100] ; (80035f0 ) 800358c: f023 0301 bic.w r3, r3, #1 8003590: 6713 str r3, [r2, #112] ; 0x70 8003592: 4b17 ldr r3, [pc, #92] ; (80035f0 ) 8003594: 6f1b ldr r3, [r3, #112] ; 0x70 8003596: 4a16 ldr r2, [pc, #88] ; (80035f0 ) 8003598: f023 0304 bic.w r3, r3, #4 800359c: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800359e: 687b ldr r3, [r7, #4] 80035a0: 689b ldr r3, [r3, #8] 80035a2: 2b00 cmp r3, #0 80035a4: d015 beq.n 80035d2 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80035a6: f7fe f857 bl 8001658 80035aa: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 80035ac: e00a b.n 80035c4 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 80035ae: f7fe f853 bl 8001658 80035b2: 4602 mov r2, r0 80035b4: 6a7b ldr r3, [r7, #36] ; 0x24 80035b6: 1ad3 subs r3, r2, r3 80035b8: f241 3288 movw r2, #5000 ; 0x1388 80035bc: 4293 cmp r3, r2 80035be: d901 bls.n 80035c4 { return HAL_TIMEOUT; 80035c0: 2303 movs r3, #3 80035c2: e11e b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 80035c4: 4b0a ldr r3, [pc, #40] ; (80035f0 ) 80035c6: 6f1b ldr r3, [r3, #112] ; 0x70 80035c8: f003 0302 and.w r3, r3, #2 80035cc: 2b00 cmp r3, #0 80035ce: d0ee beq.n 80035ae 80035d0: e018 b.n 8003604 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80035d2: f7fe f841 bl 8001658 80035d6: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 80035d8: e00e b.n 80035f8 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 80035da: f7fe f83d bl 8001658 80035de: 4602 mov r2, r0 80035e0: 6a7b ldr r3, [r7, #36] ; 0x24 80035e2: 1ad3 subs r3, r2, r3 80035e4: f241 3288 movw r2, #5000 ; 0x1388 80035e8: 4293 cmp r3, r2 80035ea: d905 bls.n 80035f8 { return HAL_TIMEOUT; 80035ec: 2303 movs r3, #3 80035ee: e108 b.n 8003802 80035f0: 58024400 .word 0x58024400 80035f4: 58024800 .word 0x58024800 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 80035f8: 4b84 ldr r3, [pc, #528] ; (800380c ) 80035fa: 6f1b ldr r3, [r3, #112] ; 0x70 80035fc: f003 0302 and.w r3, r3, #2 8003600: 2b00 cmp r3, #0 8003602: d1ea bne.n 80035da } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8003604: 687b ldr r3, [r7, #4] 8003606: 6a5b ldr r3, [r3, #36] ; 0x24 8003608: 2b00 cmp r3, #0 800360a: f000 80f9 beq.w 8003800 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800360e: 4b7f ldr r3, [pc, #508] ; (800380c ) 8003610: 691b ldr r3, [r3, #16] 8003612: f003 0338 and.w r3, r3, #56 ; 0x38 8003616: 2b18 cmp r3, #24 8003618: f000 80b4 beq.w 8003784 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800361c: 687b ldr r3, [r7, #4] 800361e: 6a5b ldr r3, [r3, #36] ; 0x24 8003620: 2b02 cmp r3, #2 8003622: f040 8095 bne.w 8003750 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003626: 4b79 ldr r3, [pc, #484] ; (800380c ) 8003628: 681b ldr r3, [r3, #0] 800362a: 4a78 ldr r2, [pc, #480] ; (800380c ) 800362c: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8003630: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003632: f7fe f811 bl 8001658 8003636: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8003638: e008 b.n 800364c { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 800363a: f7fe f80d bl 8001658 800363e: 4602 mov r2, r0 8003640: 6a7b ldr r3, [r7, #36] ; 0x24 8003642: 1ad3 subs r3, r2, r3 8003644: 2b02 cmp r3, #2 8003646: d901 bls.n 800364c { return HAL_TIMEOUT; 8003648: 2303 movs r3, #3 800364a: e0da b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800364c: 4b6f ldr r3, [pc, #444] ; (800380c ) 800364e: 681b ldr r3, [r3, #0] 8003650: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003654: 2b00 cmp r3, #0 8003656: d1f0 bne.n 800363a } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8003658: 4b6c ldr r3, [pc, #432] ; (800380c ) 800365a: 6a9a ldr r2, [r3, #40] ; 0x28 800365c: 4b6c ldr r3, [pc, #432] ; (8003810 ) 800365e: 4013 ands r3, r2 8003660: 687a ldr r2, [r7, #4] 8003662: 6a91 ldr r1, [r2, #40] ; 0x28 8003664: 687a ldr r2, [r7, #4] 8003666: 6ad2 ldr r2, [r2, #44] ; 0x2c 8003668: 0112 lsls r2, r2, #4 800366a: 430a orrs r2, r1 800366c: 4967 ldr r1, [pc, #412] ; (800380c ) 800366e: 4313 orrs r3, r2 8003670: 628b str r3, [r1, #40] ; 0x28 8003672: 687b ldr r3, [r7, #4] 8003674: 6b1b ldr r3, [r3, #48] ; 0x30 8003676: 3b01 subs r3, #1 8003678: f3c3 0208 ubfx r2, r3, #0, #9 800367c: 687b ldr r3, [r7, #4] 800367e: 6b5b ldr r3, [r3, #52] ; 0x34 8003680: 3b01 subs r3, #1 8003682: 025b lsls r3, r3, #9 8003684: b29b uxth r3, r3 8003686: 431a orrs r2, r3 8003688: 687b ldr r3, [r7, #4] 800368a: 6b9b ldr r3, [r3, #56] ; 0x38 800368c: 3b01 subs r3, #1 800368e: 041b lsls r3, r3, #16 8003690: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8003694: 431a orrs r2, r3 8003696: 687b ldr r3, [r7, #4] 8003698: 6bdb ldr r3, [r3, #60] ; 0x3c 800369a: 3b01 subs r3, #1 800369c: 061b lsls r3, r3, #24 800369e: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 80036a2: 495a ldr r1, [pc, #360] ; (800380c ) 80036a4: 4313 orrs r3, r2 80036a6: 630b str r3, [r1, #48] ; 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 80036a8: 4b58 ldr r3, [pc, #352] ; (800380c ) 80036aa: 6adb ldr r3, [r3, #44] ; 0x2c 80036ac: 4a57 ldr r2, [pc, #348] ; (800380c ) 80036ae: f023 0301 bic.w r3, r3, #1 80036b2: 62d3 str r3, [r2, #44] ; 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 80036b4: 4b55 ldr r3, [pc, #340] ; (800380c ) 80036b6: 6b5a ldr r2, [r3, #52] ; 0x34 80036b8: 4b56 ldr r3, [pc, #344] ; (8003814 ) 80036ba: 4013 ands r3, r2 80036bc: 687a ldr r2, [r7, #4] 80036be: 6c92 ldr r2, [r2, #72] ; 0x48 80036c0: 00d2 lsls r2, r2, #3 80036c2: 4952 ldr r1, [pc, #328] ; (800380c ) 80036c4: 4313 orrs r3, r2 80036c6: 634b str r3, [r1, #52] ; 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 80036c8: 4b50 ldr r3, [pc, #320] ; (800380c ) 80036ca: 6adb ldr r3, [r3, #44] ; 0x2c 80036cc: f023 020c bic.w r2, r3, #12 80036d0: 687b ldr r3, [r7, #4] 80036d2: 6c1b ldr r3, [r3, #64] ; 0x40 80036d4: 494d ldr r1, [pc, #308] ; (800380c ) 80036d6: 4313 orrs r3, r2 80036d8: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 80036da: 4b4c ldr r3, [pc, #304] ; (800380c ) 80036dc: 6adb ldr r3, [r3, #44] ; 0x2c 80036de: f023 0202 bic.w r2, r3, #2 80036e2: 687b ldr r3, [r7, #4] 80036e4: 6c5b ldr r3, [r3, #68] ; 0x44 80036e6: 4949 ldr r1, [pc, #292] ; (800380c ) 80036e8: 4313 orrs r3, r2 80036ea: 62cb str r3, [r1, #44] ; 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 80036ec: 4b47 ldr r3, [pc, #284] ; (800380c ) 80036ee: 6adb ldr r3, [r3, #44] ; 0x2c 80036f0: 4a46 ldr r2, [pc, #280] ; (800380c ) 80036f2: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80036f6: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80036f8: 4b44 ldr r3, [pc, #272] ; (800380c ) 80036fa: 6adb ldr r3, [r3, #44] ; 0x2c 80036fc: 4a43 ldr r2, [pc, #268] ; (800380c ) 80036fe: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003702: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 8003704: 4b41 ldr r3, [pc, #260] ; (800380c ) 8003706: 6adb ldr r3, [r3, #44] ; 0x2c 8003708: 4a40 ldr r2, [pc, #256] ; (800380c ) 800370a: f443 2380 orr.w r3, r3, #262144 ; 0x40000 800370e: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 8003710: 4b3e ldr r3, [pc, #248] ; (800380c ) 8003712: 6adb ldr r3, [r3, #44] ; 0x2c 8003714: 4a3d ldr r2, [pc, #244] ; (800380c ) 8003716: f043 0301 orr.w r3, r3, #1 800371a: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800371c: 4b3b ldr r3, [pc, #236] ; (800380c ) 800371e: 681b ldr r3, [r3, #0] 8003720: 4a3a ldr r2, [pc, #232] ; (800380c ) 8003722: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8003726: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003728: f7fd ff96 bl 8001658 800372c: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800372e: e008 b.n 8003742 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8003730: f7fd ff92 bl 8001658 8003734: 4602 mov r2, r0 8003736: 6a7b ldr r3, [r7, #36] ; 0x24 8003738: 1ad3 subs r3, r2, r3 800373a: 2b02 cmp r3, #2 800373c: d901 bls.n 8003742 { return HAL_TIMEOUT; 800373e: 2303 movs r3, #3 8003740: e05f b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8003742: 4b32 ldr r3, [pc, #200] ; (800380c ) 8003744: 681b ldr r3, [r3, #0] 8003746: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800374a: 2b00 cmp r3, #0 800374c: d0f0 beq.n 8003730 800374e: e057 b.n 8003800 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003750: 4b2e ldr r3, [pc, #184] ; (800380c ) 8003752: 681b ldr r3, [r3, #0] 8003754: 4a2d ldr r2, [pc, #180] ; (800380c ) 8003756: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 800375a: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800375c: f7fd ff7c bl 8001658 8003760: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8003762: e008 b.n 8003776 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8003764: f7fd ff78 bl 8001658 8003768: 4602 mov r2, r0 800376a: 6a7b ldr r3, [r7, #36] ; 0x24 800376c: 1ad3 subs r3, r2, r3 800376e: 2b02 cmp r3, #2 8003770: d901 bls.n 8003776 { return HAL_TIMEOUT; 8003772: 2303 movs r3, #3 8003774: e045 b.n 8003802 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8003776: 4b25 ldr r3, [pc, #148] ; (800380c ) 8003778: 681b ldr r3, [r3, #0] 800377a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800377e: 2b00 cmp r3, #0 8003780: d1f0 bne.n 8003764 8003782: e03d b.n 8003800 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 8003784: 4b21 ldr r3, [pc, #132] ; (800380c ) 8003786: 6a9b ldr r3, [r3, #40] ; 0x28 8003788: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 800378a: 4b20 ldr r3, [pc, #128] ; (800380c ) 800378c: 6b1b ldr r3, [r3, #48] ; 0x30 800378e: 60fb str r3, [r7, #12] if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8003790: 687b ldr r3, [r7, #4] 8003792: 6a5b ldr r3, [r3, #36] ; 0x24 8003794: 2b01 cmp r3, #1 8003796: d031 beq.n 80037fc (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003798: 693b ldr r3, [r7, #16] 800379a: f003 0203 and.w r2, r3, #3 800379e: 687b ldr r3, [r7, #4] 80037a0: 6a9b ldr r3, [r3, #40] ; 0x28 if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80037a2: 429a cmp r2, r3 80037a4: d12a bne.n 80037fc ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 80037a6: 693b ldr r3, [r7, #16] 80037a8: 091b lsrs r3, r3, #4 80037aa: f003 023f and.w r2, r3, #63 ; 0x3f 80037ae: 687b ldr r3, [r7, #4] 80037b0: 6adb ldr r3, [r3, #44] ; 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80037b2: 429a cmp r2, r3 80037b4: d122 bne.n 80037fc (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 80037b6: 68fb ldr r3, [r7, #12] 80037b8: f3c3 0208 ubfx r2, r3, #0, #9 80037bc: 687b ldr r3, [r7, #4] 80037be: 6b1b ldr r3, [r3, #48] ; 0x30 80037c0: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 80037c2: 429a cmp r2, r3 80037c4: d11a bne.n 80037fc ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 80037c6: 68fb ldr r3, [r7, #12] 80037c8: 0a5b lsrs r3, r3, #9 80037ca: f003 027f and.w r2, r3, #127 ; 0x7f 80037ce: 687b ldr r3, [r7, #4] 80037d0: 6b5b ldr r3, [r3, #52] ; 0x34 80037d2: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 80037d4: 429a cmp r2, r3 80037d6: d111 bne.n 80037fc ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 80037d8: 68fb ldr r3, [r7, #12] 80037da: 0c1b lsrs r3, r3, #16 80037dc: f003 027f and.w r2, r3, #127 ; 0x7f 80037e0: 687b ldr r3, [r7, #4] 80037e2: 6b9b ldr r3, [r3, #56] ; 0x38 80037e4: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 80037e6: 429a cmp r2, r3 80037e8: d108 bne.n 80037fc ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 80037ea: 68fb ldr r3, [r7, #12] 80037ec: 0e1b lsrs r3, r3, #24 80037ee: f003 027f and.w r2, r3, #127 ; 0x7f 80037f2: 687b ldr r3, [r7, #4] 80037f4: 6bdb ldr r3, [r3, #60] ; 0x3c 80037f6: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 80037f8: 429a cmp r2, r3 80037fa: d001 beq.n 8003800 { return HAL_ERROR; 80037fc: 2301 movs r3, #1 80037fe: e000 b.n 8003802 } } } return HAL_OK; 8003800: 2300 movs r3, #0 } 8003802: 4618 mov r0, r3 8003804: 3730 adds r7, #48 ; 0x30 8003806: 46bd mov sp, r7 8003808: bd80 pop {r7, pc} 800380a: bf00 nop 800380c: 58024400 .word 0x58024400 8003810: fffffc0c .word 0xfffffc0c 8003814: ffff0007 .word 0xffff0007 08003818 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003818: b580 push {r7, lr} 800381a: b086 sub sp, #24 800381c: af00 add r7, sp, #0 800381e: 6078 str r0, [r7, #4] 8003820: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8003822: 687b ldr r3, [r7, #4] 8003824: 2b00 cmp r3, #0 8003826: d101 bne.n 800382c { return HAL_ERROR; 8003828: 2301 movs r3, #1 800382a: e19c b.n 8003b66 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 800382c: 4b8a ldr r3, [pc, #552] ; (8003a58 ) 800382e: 681b ldr r3, [r3, #0] 8003830: f003 030f and.w r3, r3, #15 8003834: 683a ldr r2, [r7, #0] 8003836: 429a cmp r2, r3 8003838: d910 bls.n 800385c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800383a: 4b87 ldr r3, [pc, #540] ; (8003a58 ) 800383c: 681b ldr r3, [r3, #0] 800383e: f023 020f bic.w r2, r3, #15 8003842: 4985 ldr r1, [pc, #532] ; (8003a58 ) 8003844: 683b ldr r3, [r7, #0] 8003846: 4313 orrs r3, r2 8003848: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 800384a: 4b83 ldr r3, [pc, #524] ; (8003a58 ) 800384c: 681b ldr r3, [r3, #0] 800384e: f003 030f and.w r3, r3, #15 8003852: 683a ldr r2, [r7, #0] 8003854: 429a cmp r2, r3 8003856: d001 beq.n 800385c { return HAL_ERROR; 8003858: 2301 movs r3, #1 800385a: e184 b.n 8003b66 } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800385c: 687b ldr r3, [r7, #4] 800385e: 681b ldr r3, [r3, #0] 8003860: f003 0304 and.w r3, r3, #4 8003864: 2b00 cmp r3, #0 8003866: d010 beq.n 800388a { #if defined (RCC_D1CFGR_D1PPRE) if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 8003868: 687b ldr r3, [r7, #4] 800386a: 691a ldr r2, [r3, #16] 800386c: 4b7b ldr r3, [pc, #492] ; (8003a5c ) 800386e: 699b ldr r3, [r3, #24] 8003870: f003 0370 and.w r3, r3, #112 ; 0x70 8003874: 429a cmp r2, r3 8003876: d908 bls.n 800388a { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8003878: 4b78 ldr r3, [pc, #480] ; (8003a5c ) 800387a: 699b ldr r3, [r3, #24] 800387c: f023 0270 bic.w r2, r3, #112 ; 0x70 8003880: 687b ldr r3, [r7, #4] 8003882: 691b ldr r3, [r3, #16] 8003884: 4975 ldr r1, [pc, #468] ; (8003a5c ) 8003886: 4313 orrs r3, r2 8003888: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800388a: 687b ldr r3, [r7, #4] 800388c: 681b ldr r3, [r3, #0] 800388e: f003 0308 and.w r3, r3, #8 8003892: 2b00 cmp r3, #0 8003894: d010 beq.n 80038b8 { #if defined (RCC_D2CFGR_D2PPRE1) if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 8003896: 687b ldr r3, [r7, #4] 8003898: 695a ldr r2, [r3, #20] 800389a: 4b70 ldr r3, [pc, #448] ; (8003a5c ) 800389c: 69db ldr r3, [r3, #28] 800389e: f003 0370 and.w r3, r3, #112 ; 0x70 80038a2: 429a cmp r2, r3 80038a4: d908 bls.n 80038b8 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 80038a6: 4b6d ldr r3, [pc, #436] ; (8003a5c ) 80038a8: 69db ldr r3, [r3, #28] 80038aa: f023 0270 bic.w r2, r3, #112 ; 0x70 80038ae: 687b ldr r3, [r7, #4] 80038b0: 695b ldr r3, [r3, #20] 80038b2: 496a ldr r1, [pc, #424] ; (8003a5c ) 80038b4: 4313 orrs r3, r2 80038b6: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80038b8: 687b ldr r3, [r7, #4] 80038ba: 681b ldr r3, [r3, #0] 80038bc: f003 0310 and.w r3, r3, #16 80038c0: 2b00 cmp r3, #0 80038c2: d010 beq.n 80038e6 { #if defined(RCC_D2CFGR_D2PPRE2) if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 80038c4: 687b ldr r3, [r7, #4] 80038c6: 699a ldr r2, [r3, #24] 80038c8: 4b64 ldr r3, [pc, #400] ; (8003a5c ) 80038ca: 69db ldr r3, [r3, #28] 80038cc: f403 63e0 and.w r3, r3, #1792 ; 0x700 80038d0: 429a cmp r2, r3 80038d2: d908 bls.n 80038e6 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 80038d4: 4b61 ldr r3, [pc, #388] ; (8003a5c ) 80038d6: 69db ldr r3, [r3, #28] 80038d8: f423 62e0 bic.w r2, r3, #1792 ; 0x700 80038dc: 687b ldr r3, [r7, #4] 80038de: 699b ldr r3, [r3, #24] 80038e0: 495e ldr r1, [pc, #376] ; (8003a5c ) 80038e2: 4313 orrs r3, r2 80038e4: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 80038e6: 687b ldr r3, [r7, #4] 80038e8: 681b ldr r3, [r3, #0] 80038ea: f003 0320 and.w r3, r3, #32 80038ee: 2b00 cmp r3, #0 80038f0: d010 beq.n 8003914 { #if defined(RCC_D3CFGR_D3PPRE) if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 80038f2: 687b ldr r3, [r7, #4] 80038f4: 69da ldr r2, [r3, #28] 80038f6: 4b59 ldr r3, [pc, #356] ; (8003a5c ) 80038f8: 6a1b ldr r3, [r3, #32] 80038fa: f003 0370 and.w r3, r3, #112 ; 0x70 80038fe: 429a cmp r2, r3 8003900: d908 bls.n 8003914 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); 8003902: 4b56 ldr r3, [pc, #344] ; (8003a5c ) 8003904: 6a1b ldr r3, [r3, #32] 8003906: f023 0270 bic.w r2, r3, #112 ; 0x70 800390a: 687b ldr r3, [r7, #4] 800390c: 69db ldr r3, [r3, #28] 800390e: 4953 ldr r1, [pc, #332] ; (8003a5c ) 8003910: 4313 orrs r3, r2 8003912: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003914: 687b ldr r3, [r7, #4] 8003916: 681b ldr r3, [r3, #0] 8003918: f003 0302 and.w r3, r3, #2 800391c: 2b00 cmp r3, #0 800391e: d010 beq.n 8003942 { #if defined (RCC_D1CFGR_HPRE) if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 8003920: 687b ldr r3, [r7, #4] 8003922: 68da ldr r2, [r3, #12] 8003924: 4b4d ldr r3, [pc, #308] ; (8003a5c ) 8003926: 699b ldr r3, [r3, #24] 8003928: f003 030f and.w r3, r3, #15 800392c: 429a cmp r2, r3 800392e: d908 bls.n 8003942 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003930: 4b4a ldr r3, [pc, #296] ; (8003a5c ) 8003932: 699b ldr r3, [r3, #24] 8003934: f023 020f bic.w r2, r3, #15 8003938: 687b ldr r3, [r7, #4] 800393a: 68db ldr r3, [r3, #12] 800393c: 4947 ldr r1, [pc, #284] ; (8003a5c ) 800393e: 4313 orrs r3, r2 8003940: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003942: 687b ldr r3, [r7, #4] 8003944: 681b ldr r3, [r3, #0] 8003946: f003 0301 and.w r3, r3, #1 800394a: 2b00 cmp r3, #0 800394c: d055 beq.n 80039fa { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 800394e: 4b43 ldr r3, [pc, #268] ; (8003a5c ) 8003950: 699b ldr r3, [r3, #24] 8003952: f423 6270 bic.w r2, r3, #3840 ; 0xf00 8003956: 687b ldr r3, [r7, #4] 8003958: 689b ldr r3, [r3, #8] 800395a: 4940 ldr r1, [pc, #256] ; (8003a5c ) 800395c: 4313 orrs r3, r2 800395e: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8003960: 687b ldr r3, [r7, #4] 8003962: 685b ldr r3, [r3, #4] 8003964: 2b02 cmp r3, #2 8003966: d107 bne.n 8003978 { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8003968: 4b3c ldr r3, [pc, #240] ; (8003a5c ) 800396a: 681b ldr r3, [r3, #0] 800396c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003970: 2b00 cmp r3, #0 8003972: d121 bne.n 80039b8 { return HAL_ERROR; 8003974: 2301 movs r3, #1 8003976: e0f6 b.n 8003b66 } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8003978: 687b ldr r3, [r7, #4] 800397a: 685b ldr r3, [r3, #4] 800397c: 2b03 cmp r3, #3 800397e: d107 bne.n 8003990 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8003980: 4b36 ldr r3, [pc, #216] ; (8003a5c ) 8003982: 681b ldr r3, [r3, #0] 8003984: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003988: 2b00 cmp r3, #0 800398a: d115 bne.n 80039b8 { return HAL_ERROR; 800398c: 2301 movs r3, #1 800398e: e0ea b.n 8003b66 } } /* CSI is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 8003990: 687b ldr r3, [r7, #4] 8003992: 685b ldr r3, [r3, #4] 8003994: 2b01 cmp r3, #1 8003996: d107 bne.n 80039a8 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8003998: 4b30 ldr r3, [pc, #192] ; (8003a5c ) 800399a: 681b ldr r3, [r3, #0] 800399c: f403 7380 and.w r3, r3, #256 ; 0x100 80039a0: 2b00 cmp r3, #0 80039a2: d109 bne.n 80039b8 { return HAL_ERROR; 80039a4: 2301 movs r3, #1 80039a6: e0de b.n 8003b66 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80039a8: 4b2c ldr r3, [pc, #176] ; (8003a5c ) 80039aa: 681b ldr r3, [r3, #0] 80039ac: f003 0304 and.w r3, r3, #4 80039b0: 2b00 cmp r3, #0 80039b2: d101 bne.n 80039b8 { return HAL_ERROR; 80039b4: 2301 movs r3, #1 80039b6: e0d6 b.n 8003b66 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 80039b8: 4b28 ldr r3, [pc, #160] ; (8003a5c ) 80039ba: 691b ldr r3, [r3, #16] 80039bc: f023 0207 bic.w r2, r3, #7 80039c0: 687b ldr r3, [r7, #4] 80039c2: 685b ldr r3, [r3, #4] 80039c4: 4925 ldr r1, [pc, #148] ; (8003a5c ) 80039c6: 4313 orrs r3, r2 80039c8: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80039ca: f7fd fe45 bl 8001658 80039ce: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80039d0: e00a b.n 80039e8 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 80039d2: f7fd fe41 bl 8001658 80039d6: 4602 mov r2, r0 80039d8: 697b ldr r3, [r7, #20] 80039da: 1ad3 subs r3, r2, r3 80039dc: f241 3288 movw r2, #5000 ; 0x1388 80039e0: 4293 cmp r3, r2 80039e2: d901 bls.n 80039e8 { return HAL_TIMEOUT; 80039e4: 2303 movs r3, #3 80039e6: e0be b.n 8003b66 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80039e8: 4b1c ldr r3, [pc, #112] ; (8003a5c ) 80039ea: 691b ldr r3, [r3, #16] 80039ec: f003 0238 and.w r2, r3, #56 ; 0x38 80039f0: 687b ldr r3, [r7, #4] 80039f2: 685b ldr r3, [r3, #4] 80039f4: 00db lsls r3, r3, #3 80039f6: 429a cmp r2, r3 80039f8: d1eb bne.n 80039d2 } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80039fa: 687b ldr r3, [r7, #4] 80039fc: 681b ldr r3, [r3, #0] 80039fe: f003 0302 and.w r3, r3, #2 8003a02: 2b00 cmp r3, #0 8003a04: d010 beq.n 8003a28 { #if defined(RCC_D1CFGR_HPRE) if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 8003a06: 687b ldr r3, [r7, #4] 8003a08: 68da ldr r2, [r3, #12] 8003a0a: 4b14 ldr r3, [pc, #80] ; (8003a5c ) 8003a0c: 699b ldr r3, [r3, #24] 8003a0e: f003 030f and.w r3, r3, #15 8003a12: 429a cmp r2, r3 8003a14: d208 bcs.n 8003a28 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003a16: 4b11 ldr r3, [pc, #68] ; (8003a5c ) 8003a18: 699b ldr r3, [r3, #24] 8003a1a: f023 020f bic.w r2, r3, #15 8003a1e: 687b ldr r3, [r7, #4] 8003a20: 68db ldr r3, [r3, #12] 8003a22: 490e ldr r1, [pc, #56] ; (8003a5c ) 8003a24: 4313 orrs r3, r2 8003a26: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8003a28: 4b0b ldr r3, [pc, #44] ; (8003a58 ) 8003a2a: 681b ldr r3, [r3, #0] 8003a2c: f003 030f and.w r3, r3, #15 8003a30: 683a ldr r2, [r7, #0] 8003a32: 429a cmp r2, r3 8003a34: d214 bcs.n 8003a60 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003a36: 4b08 ldr r3, [pc, #32] ; (8003a58 ) 8003a38: 681b ldr r3, [r3, #0] 8003a3a: f023 020f bic.w r2, r3, #15 8003a3e: 4906 ldr r1, [pc, #24] ; (8003a58 ) 8003a40: 683b ldr r3, [r7, #0] 8003a42: 4313 orrs r3, r2 8003a44: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8003a46: 4b04 ldr r3, [pc, #16] ; (8003a58 ) 8003a48: 681b ldr r3, [r3, #0] 8003a4a: f003 030f and.w r3, r3, #15 8003a4e: 683a ldr r2, [r7, #0] 8003a50: 429a cmp r2, r3 8003a52: d005 beq.n 8003a60 { return HAL_ERROR; 8003a54: 2301 movs r3, #1 8003a56: e086 b.n 8003b66 8003a58: 52002000 .word 0x52002000 8003a5c: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8003a60: 687b ldr r3, [r7, #4] 8003a62: 681b ldr r3, [r3, #0] 8003a64: f003 0304 and.w r3, r3, #4 8003a68: 2b00 cmp r3, #0 8003a6a: d010 beq.n 8003a8e { #if defined(RCC_D1CFGR_D1PPRE) if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 8003a6c: 687b ldr r3, [r7, #4] 8003a6e: 691a ldr r2, [r3, #16] 8003a70: 4b3f ldr r3, [pc, #252] ; (8003b70 ) 8003a72: 699b ldr r3, [r3, #24] 8003a74: f003 0370 and.w r3, r3, #112 ; 0x70 8003a78: 429a cmp r2, r3 8003a7a: d208 bcs.n 8003a8e { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8003a7c: 4b3c ldr r3, [pc, #240] ; (8003b70 ) 8003a7e: 699b ldr r3, [r3, #24] 8003a80: f023 0270 bic.w r2, r3, #112 ; 0x70 8003a84: 687b ldr r3, [r7, #4] 8003a86: 691b ldr r3, [r3, #16] 8003a88: 4939 ldr r1, [pc, #228] ; (8003b70 ) 8003a8a: 4313 orrs r3, r2 8003a8c: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003a8e: 687b ldr r3, [r7, #4] 8003a90: 681b ldr r3, [r3, #0] 8003a92: f003 0308 and.w r3, r3, #8 8003a96: 2b00 cmp r3, #0 8003a98: d010 beq.n 8003abc { #if defined(RCC_D2CFGR_D2PPRE1) if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 8003a9a: 687b ldr r3, [r7, #4] 8003a9c: 695a ldr r2, [r3, #20] 8003a9e: 4b34 ldr r3, [pc, #208] ; (8003b70 ) 8003aa0: 69db ldr r3, [r3, #28] 8003aa2: f003 0370 and.w r3, r3, #112 ; 0x70 8003aa6: 429a cmp r2, r3 8003aa8: d208 bcs.n 8003abc { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8003aaa: 4b31 ldr r3, [pc, #196] ; (8003b70 ) 8003aac: 69db ldr r3, [r3, #28] 8003aae: f023 0270 bic.w r2, r3, #112 ; 0x70 8003ab2: 687b ldr r3, [r7, #4] 8003ab4: 695b ldr r3, [r3, #20] 8003ab6: 492e ldr r1, [pc, #184] ; (8003b70 ) 8003ab8: 4313 orrs r3, r2 8003aba: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003abc: 687b ldr r3, [r7, #4] 8003abe: 681b ldr r3, [r3, #0] 8003ac0: f003 0310 and.w r3, r3, #16 8003ac4: 2b00 cmp r3, #0 8003ac6: d010 beq.n 8003aea { #if defined (RCC_D2CFGR_D2PPRE2) if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 8003ac8: 687b ldr r3, [r7, #4] 8003aca: 699a ldr r2, [r3, #24] 8003acc: 4b28 ldr r3, [pc, #160] ; (8003b70 ) 8003ace: 69db ldr r3, [r3, #28] 8003ad0: f403 63e0 and.w r3, r3, #1792 ; 0x700 8003ad4: 429a cmp r2, r3 8003ad6: d208 bcs.n 8003aea { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8003ad8: 4b25 ldr r3, [pc, #148] ; (8003b70 ) 8003ada: 69db ldr r3, [r3, #28] 8003adc: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8003ae0: 687b ldr r3, [r7, #4] 8003ae2: 699b ldr r3, [r3, #24] 8003ae4: 4922 ldr r1, [pc, #136] ; (8003b70 ) 8003ae6: 4313 orrs r3, r2 8003ae8: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8003aea: 687b ldr r3, [r7, #4] 8003aec: 681b ldr r3, [r3, #0] 8003aee: f003 0320 and.w r3, r3, #32 8003af2: 2b00 cmp r3, #0 8003af4: d010 beq.n 8003b18 { #if defined(RCC_D3CFGR_D3PPRE) if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 8003af6: 687b ldr r3, [r7, #4] 8003af8: 69da ldr r2, [r3, #28] 8003afa: 4b1d ldr r3, [pc, #116] ; (8003b70 ) 8003afc: 6a1b ldr r3, [r3, #32] 8003afe: f003 0370 and.w r3, r3, #112 ; 0x70 8003b02: 429a cmp r2, r3 8003b04: d208 bcs.n 8003b18 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); 8003b06: 4b1a ldr r3, [pc, #104] ; (8003b70 ) 8003b08: 6a1b ldr r3, [r3, #32] 8003b0a: f023 0270 bic.w r2, r3, #112 ; 0x70 8003b0e: 687b ldr r3, [r7, #4] 8003b10: 69db ldr r3, [r3, #28] 8003b12: 4917 ldr r1, [pc, #92] ; (8003b70 ) 8003b14: 4313 orrs r3, r2 8003b16: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8003b18: f000 f834 bl 8003b84 8003b1c: 4602 mov r2, r0 8003b1e: 4b14 ldr r3, [pc, #80] ; (8003b70 ) 8003b20: 699b ldr r3, [r3, #24] 8003b22: 0a1b lsrs r3, r3, #8 8003b24: f003 030f and.w r3, r3, #15 8003b28: 4912 ldr r1, [pc, #72] ; (8003b74 ) 8003b2a: 5ccb ldrb r3, [r1, r3] 8003b2c: f003 031f and.w r3, r3, #31 8003b30: fa22 f303 lsr.w r3, r2, r3 8003b34: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8003b36: 4b0e ldr r3, [pc, #56] ; (8003b70 ) 8003b38: 699b ldr r3, [r3, #24] 8003b3a: f003 030f and.w r3, r3, #15 8003b3e: 4a0d ldr r2, [pc, #52] ; (8003b74 ) 8003b40: 5cd3 ldrb r3, [r2, r3] 8003b42: f003 031f and.w r3, r3, #31 8003b46: 693a ldr r2, [r7, #16] 8003b48: fa22 f303 lsr.w r3, r2, r3 8003b4c: 4a0a ldr r2, [pc, #40] ; (8003b78 ) 8003b4e: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8003b50: 4a0a ldr r2, [pc, #40] ; (8003b7c ) 8003b52: 693b ldr r3, [r7, #16] 8003b54: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick (uwTickPrio); 8003b56: 4b0a ldr r3, [pc, #40] ; (8003b80 ) 8003b58: 681b ldr r3, [r3, #0] 8003b5a: 4618 mov r0, r3 8003b5c: f7fd fd32 bl 80015c4 8003b60: 4603 mov r3, r0 8003b62: 73fb strb r3, [r7, #15] return halstatus; 8003b64: 7bfb ldrb r3, [r7, #15] } 8003b66: 4618 mov r0, r3 8003b68: 3718 adds r7, #24 8003b6a: 46bd mov sp, r7 8003b6c: bd80 pop {r7, pc} 8003b6e: bf00 nop 8003b70: 58024400 .word 0x58024400 8003b74: 0800aa10 .word 0x0800aa10 8003b78: 24000004 .word 0x24000004 8003b7c: 24000000 .word 0x24000000 8003b80: 24000008 .word 0x24000008 08003b84 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8003b84: b480 push {r7} 8003b86: b089 sub sp, #36 ; 0x24 8003b88: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8003b8a: 4bb3 ldr r3, [pc, #716] ; (8003e58 ) 8003b8c: 691b ldr r3, [r3, #16] 8003b8e: f003 0338 and.w r3, r3, #56 ; 0x38 8003b92: 2b18 cmp r3, #24 8003b94: f200 8155 bhi.w 8003e42 8003b98: a201 add r2, pc, #4 ; (adr r2, 8003ba0 ) 8003b9a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003b9e: bf00 nop 8003ba0: 08003c05 .word 0x08003c05 8003ba4: 08003e43 .word 0x08003e43 8003ba8: 08003e43 .word 0x08003e43 8003bac: 08003e43 .word 0x08003e43 8003bb0: 08003e43 .word 0x08003e43 8003bb4: 08003e43 .word 0x08003e43 8003bb8: 08003e43 .word 0x08003e43 8003bbc: 08003e43 .word 0x08003e43 8003bc0: 08003c2b .word 0x08003c2b 8003bc4: 08003e43 .word 0x08003e43 8003bc8: 08003e43 .word 0x08003e43 8003bcc: 08003e43 .word 0x08003e43 8003bd0: 08003e43 .word 0x08003e43 8003bd4: 08003e43 .word 0x08003e43 8003bd8: 08003e43 .word 0x08003e43 8003bdc: 08003e43 .word 0x08003e43 8003be0: 08003c31 .word 0x08003c31 8003be4: 08003e43 .word 0x08003e43 8003be8: 08003e43 .word 0x08003e43 8003bec: 08003e43 .word 0x08003e43 8003bf0: 08003e43 .word 0x08003e43 8003bf4: 08003e43 .word 0x08003e43 8003bf8: 08003e43 .word 0x08003e43 8003bfc: 08003e43 .word 0x08003e43 8003c00: 08003c37 .word 0x08003c37 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8003c04: 4b94 ldr r3, [pc, #592] ; (8003e58 ) 8003c06: 681b ldr r3, [r3, #0] 8003c08: f003 0320 and.w r3, r3, #32 8003c0c: 2b00 cmp r3, #0 8003c0e: d009 beq.n 8003c24 { sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8003c10: 4b91 ldr r3, [pc, #580] ; (8003e58 ) 8003c12: 681b ldr r3, [r3, #0] 8003c14: 08db lsrs r3, r3, #3 8003c16: f003 0303 and.w r3, r3, #3 8003c1a: 4a90 ldr r2, [pc, #576] ; (8003e5c ) 8003c1c: fa22 f303 lsr.w r3, r2, r3 8003c20: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 8003c22: e111 b.n 8003e48 sysclockfreq = (uint32_t) HSI_VALUE; 8003c24: 4b8d ldr r3, [pc, #564] ; (8003e5c ) 8003c26: 61bb str r3, [r7, #24] break; 8003c28: e10e b.n 8003e48 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 8003c2a: 4b8d ldr r3, [pc, #564] ; (8003e60 ) 8003c2c: 61bb str r3, [r7, #24] break; 8003c2e: e10b b.n 8003e48 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8003c30: 4b8c ldr r3, [pc, #560] ; (8003e64 ) 8003c32: 61bb str r3, [r7, #24] break; 8003c34: e108 b.n 8003e48 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8003c36: 4b88 ldr r3, [pc, #544] ; (8003e58 ) 8003c38: 6a9b ldr r3, [r3, #40] ; 0x28 8003c3a: f003 0303 and.w r3, r3, #3 8003c3e: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; 8003c40: 4b85 ldr r3, [pc, #532] ; (8003e58 ) 8003c42: 6a9b ldr r3, [r3, #40] ; 0x28 8003c44: 091b lsrs r3, r3, #4 8003c46: f003 033f and.w r3, r3, #63 ; 0x3f 8003c4a: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); 8003c4c: 4b82 ldr r3, [pc, #520] ; (8003e58 ) 8003c4e: 6adb ldr r3, [r3, #44] ; 0x2c 8003c50: f003 0301 and.w r3, r3, #1 8003c54: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); 8003c56: 4b80 ldr r3, [pc, #512] ; (8003e58 ) 8003c58: 6b5b ldr r3, [r3, #52] ; 0x34 8003c5a: 08db lsrs r3, r3, #3 8003c5c: f3c3 030c ubfx r3, r3, #0, #13 8003c60: 68fa ldr r2, [r7, #12] 8003c62: fb02 f303 mul.w r3, r2, r3 8003c66: ee07 3a90 vmov s15, r3 8003c6a: eef8 7a67 vcvt.f32.u32 s15, s15 8003c6e: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 8003c72: 693b ldr r3, [r7, #16] 8003c74: 2b00 cmp r3, #0 8003c76: f000 80e1 beq.w 8003e3c 8003c7a: 697b ldr r3, [r7, #20] 8003c7c: 2b02 cmp r3, #2 8003c7e: f000 8083 beq.w 8003d88 8003c82: 697b ldr r3, [r7, #20] 8003c84: 2b02 cmp r3, #2 8003c86: f200 80a1 bhi.w 8003dcc 8003c8a: 697b ldr r3, [r7, #20] 8003c8c: 2b00 cmp r3, #0 8003c8e: d003 beq.n 8003c98 8003c90: 697b ldr r3, [r7, #20] 8003c92: 2b01 cmp r3, #1 8003c94: d056 beq.n 8003d44 8003c96: e099 b.n 8003dcc { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8003c98: 4b6f ldr r3, [pc, #444] ; (8003e58 ) 8003c9a: 681b ldr r3, [r3, #0] 8003c9c: f003 0320 and.w r3, r3, #32 8003ca0: 2b00 cmp r3, #0 8003ca2: d02d beq.n 8003d00 { hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8003ca4: 4b6c ldr r3, [pc, #432] ; (8003e58 ) 8003ca6: 681b ldr r3, [r3, #0] 8003ca8: 08db lsrs r3, r3, #3 8003caa: f003 0303 and.w r3, r3, #3 8003cae: 4a6b ldr r2, [pc, #428] ; (8003e5c ) 8003cb0: fa22 f303 lsr.w r3, r2, r3 8003cb4: 607b str r3, [r7, #4] pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8003cb6: 687b ldr r3, [r7, #4] 8003cb8: ee07 3a90 vmov s15, r3 8003cbc: eef8 6a67 vcvt.f32.u32 s13, s15 8003cc0: 693b ldr r3, [r7, #16] 8003cc2: ee07 3a90 vmov s15, r3 8003cc6: eef8 7a67 vcvt.f32.u32 s15, s15 8003cca: ee86 7aa7 vdiv.f32 s14, s13, s15 8003cce: 4b62 ldr r3, [pc, #392] ; (8003e58 ) 8003cd0: 6b1b ldr r3, [r3, #48] ; 0x30 8003cd2: f3c3 0308 ubfx r3, r3, #0, #9 8003cd6: ee07 3a90 vmov s15, r3 8003cda: eef8 6a67 vcvt.f32.u32 s13, s15 8003cde: ed97 6a02 vldr s12, [r7, #8] 8003ce2: eddf 5a61 vldr s11, [pc, #388] ; 8003e68 8003ce6: eec6 7a25 vdiv.f32 s15, s12, s11 8003cea: ee76 7aa7 vadd.f32 s15, s13, s15 8003cee: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003cf2: ee77 7aa6 vadd.f32 s15, s15, s13 8003cf6: ee67 7a27 vmul.f32 s15, s14, s15 8003cfa: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); } break; 8003cfe: e087 b.n 8003e10 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8003d00: 693b ldr r3, [r7, #16] 8003d02: ee07 3a90 vmov s15, r3 8003d06: eef8 7a67 vcvt.f32.u32 s15, s15 8003d0a: eddf 6a58 vldr s13, [pc, #352] ; 8003e6c 8003d0e: ee86 7aa7 vdiv.f32 s14, s13, s15 8003d12: 4b51 ldr r3, [pc, #324] ; (8003e58 ) 8003d14: 6b1b ldr r3, [r3, #48] ; 0x30 8003d16: f3c3 0308 ubfx r3, r3, #0, #9 8003d1a: ee07 3a90 vmov s15, r3 8003d1e: eef8 6a67 vcvt.f32.u32 s13, s15 8003d22: ed97 6a02 vldr s12, [r7, #8] 8003d26: eddf 5a50 vldr s11, [pc, #320] ; 8003e68 8003d2a: eec6 7a25 vdiv.f32 s15, s12, s11 8003d2e: ee76 7aa7 vadd.f32 s15, s13, s15 8003d32: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003d36: ee77 7aa6 vadd.f32 s15, s15, s13 8003d3a: ee67 7a27 vmul.f32 s15, s14, s15 8003d3e: edc7 7a07 vstr s15, [r7, #28] break; 8003d42: e065 b.n 8003e10 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8003d44: 693b ldr r3, [r7, #16] 8003d46: ee07 3a90 vmov s15, r3 8003d4a: eef8 7a67 vcvt.f32.u32 s15, s15 8003d4e: eddf 6a48 vldr s13, [pc, #288] ; 8003e70 8003d52: ee86 7aa7 vdiv.f32 s14, s13, s15 8003d56: 4b40 ldr r3, [pc, #256] ; (8003e58 ) 8003d58: 6b1b ldr r3, [r3, #48] ; 0x30 8003d5a: f3c3 0308 ubfx r3, r3, #0, #9 8003d5e: ee07 3a90 vmov s15, r3 8003d62: eef8 6a67 vcvt.f32.u32 s13, s15 8003d66: ed97 6a02 vldr s12, [r7, #8] 8003d6a: eddf 5a3f vldr s11, [pc, #252] ; 8003e68 8003d6e: eec6 7a25 vdiv.f32 s15, s12, s11 8003d72: ee76 7aa7 vadd.f32 s15, s13, s15 8003d76: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003d7a: ee77 7aa6 vadd.f32 s15, s15, s13 8003d7e: ee67 7a27 vmul.f32 s15, s14, s15 8003d82: edc7 7a07 vstr s15, [r7, #28] break; 8003d86: e043 b.n 8003e10 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8003d88: 693b ldr r3, [r7, #16] 8003d8a: ee07 3a90 vmov s15, r3 8003d8e: eef8 7a67 vcvt.f32.u32 s15, s15 8003d92: eddf 6a38 vldr s13, [pc, #224] ; 8003e74 8003d96: ee86 7aa7 vdiv.f32 s14, s13, s15 8003d9a: 4b2f ldr r3, [pc, #188] ; (8003e58 ) 8003d9c: 6b1b ldr r3, [r3, #48] ; 0x30 8003d9e: f3c3 0308 ubfx r3, r3, #0, #9 8003da2: ee07 3a90 vmov s15, r3 8003da6: eef8 6a67 vcvt.f32.u32 s13, s15 8003daa: ed97 6a02 vldr s12, [r7, #8] 8003dae: eddf 5a2e vldr s11, [pc, #184] ; 8003e68 8003db2: eec6 7a25 vdiv.f32 s15, s12, s11 8003db6: ee76 7aa7 vadd.f32 s15, s13, s15 8003dba: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003dbe: ee77 7aa6 vadd.f32 s15, s15, s13 8003dc2: ee67 7a27 vmul.f32 s15, s14, s15 8003dc6: edc7 7a07 vstr s15, [r7, #28] break; 8003dca: e021 b.n 8003e10 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8003dcc: 693b ldr r3, [r7, #16] 8003dce: ee07 3a90 vmov s15, r3 8003dd2: eef8 7a67 vcvt.f32.u32 s15, s15 8003dd6: eddf 6a26 vldr s13, [pc, #152] ; 8003e70 8003dda: ee86 7aa7 vdiv.f32 s14, s13, s15 8003dde: 4b1e ldr r3, [pc, #120] ; (8003e58 ) 8003de0: 6b1b ldr r3, [r3, #48] ; 0x30 8003de2: f3c3 0308 ubfx r3, r3, #0, #9 8003de6: ee07 3a90 vmov s15, r3 8003dea: eef8 6a67 vcvt.f32.u32 s13, s15 8003dee: ed97 6a02 vldr s12, [r7, #8] 8003df2: eddf 5a1d vldr s11, [pc, #116] ; 8003e68 8003df6: eec6 7a25 vdiv.f32 s15, s12, s11 8003dfa: ee76 7aa7 vadd.f32 s15, s13, s15 8003dfe: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003e02: ee77 7aa6 vadd.f32 s15, s15, s13 8003e06: ee67 7a27 vmul.f32 s15, s14, s15 8003e0a: edc7 7a07 vstr s15, [r7, #28] break; 8003e0e: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; 8003e10: 4b11 ldr r3, [pc, #68] ; (8003e58 ) 8003e12: 6b1b ldr r3, [r3, #48] ; 0x30 8003e14: 0a5b lsrs r3, r3, #9 8003e16: f003 037f and.w r3, r3, #127 ; 0x7f 8003e1a: 3301 adds r3, #1 8003e1c: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco/(float_t)pllp); 8003e1e: 683b ldr r3, [r7, #0] 8003e20: ee07 3a90 vmov s15, r3 8003e24: eeb8 7a67 vcvt.f32.u32 s14, s15 8003e28: edd7 6a07 vldr s13, [r7, #28] 8003e2c: eec6 7a87 vdiv.f32 s15, s13, s14 8003e30: eefc 7ae7 vcvt.u32.f32 s15, s15 8003e34: ee17 3a90 vmov r3, s15 8003e38: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 8003e3a: e005 b.n 8003e48 sysclockfreq = 0U; 8003e3c: 2300 movs r3, #0 8003e3e: 61bb str r3, [r7, #24] break; 8003e40: e002 b.n 8003e48 default: sysclockfreq = CSI_VALUE; 8003e42: 4b07 ldr r3, [pc, #28] ; (8003e60 ) 8003e44: 61bb str r3, [r7, #24] break; 8003e46: bf00 nop } return sysclockfreq; 8003e48: 69bb ldr r3, [r7, #24] } 8003e4a: 4618 mov r0, r3 8003e4c: 3724 adds r7, #36 ; 0x24 8003e4e: 46bd mov sp, r7 8003e50: f85d 7b04 ldr.w r7, [sp], #4 8003e54: 4770 bx lr 8003e56: bf00 nop 8003e58: 58024400 .word 0x58024400 8003e5c: 03d09000 .word 0x03d09000 8003e60: 003d0900 .word 0x003d0900 8003e64: 007a1200 .word 0x007a1200 8003e68: 46000000 .word 0x46000000 8003e6c: 4c742400 .word 0x4c742400 8003e70: 4a742400 .word 0x4a742400 8003e74: 4af42400 .word 0x4af42400 08003e78 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8003e78: b580 push {r7, lr} 8003e7a: b082 sub sp, #8 8003e7c: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8003e7e: f7ff fe81 bl 8003b84 8003e82: 4602 mov r2, r0 8003e84: 4b10 ldr r3, [pc, #64] ; (8003ec8 ) 8003e86: 699b ldr r3, [r3, #24] 8003e88: 0a1b lsrs r3, r3, #8 8003e8a: f003 030f and.w r3, r3, #15 8003e8e: 490f ldr r1, [pc, #60] ; (8003ecc ) 8003e90: 5ccb ldrb r3, [r1, r3] 8003e92: f003 031f and.w r3, r3, #31 8003e96: fa22 f303 lsr.w r3, r2, r3 8003e9a: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8003e9c: 4b0a ldr r3, [pc, #40] ; (8003ec8 ) 8003e9e: 699b ldr r3, [r3, #24] 8003ea0: f003 030f and.w r3, r3, #15 8003ea4: 4a09 ldr r2, [pc, #36] ; (8003ecc ) 8003ea6: 5cd3 ldrb r3, [r2, r3] 8003ea8: f003 031f and.w r3, r3, #31 8003eac: 687a ldr r2, [r7, #4] 8003eae: fa22 f303 lsr.w r3, r2, r3 8003eb2: 4a07 ldr r2, [pc, #28] ; (8003ed0 ) 8003eb4: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8003eb6: 4a07 ldr r2, [pc, #28] ; (8003ed4 ) 8003eb8: 687b ldr r3, [r7, #4] 8003eba: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 8003ebc: 4b04 ldr r3, [pc, #16] ; (8003ed0 ) 8003ebe: 681b ldr r3, [r3, #0] } 8003ec0: 4618 mov r0, r3 8003ec2: 3708 adds r7, #8 8003ec4: 46bd mov sp, r7 8003ec6: bd80 pop {r7, pc} 8003ec8: 58024400 .word 0x58024400 8003ecc: 0800aa10 .word 0x0800aa10 8003ed0: 24000004 .word 0x24000004 8003ed4: 24000000 .word 0x24000000 08003ed8 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8003ed8: b580 push {r7, lr} 8003eda: b086 sub sp, #24 8003edc: af00 add r7, sp, #0 8003ede: 6078 str r0, [r7, #4] uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8003ee0: 2300 movs r3, #0 8003ee2: 75fb strb r3, [r7, #23] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8003ee4: 2300 movs r3, #0 8003ee6: 75bb strb r3, [r7, #22] /*---------------------------- SPDIFRX configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8003ee8: 687b ldr r3, [r7, #4] 8003eea: 681b ldr r3, [r3, #0] 8003eec: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8003ef0: 2b00 cmp r3, #0 8003ef2: d03f beq.n 8003f74 { switch(PeriphClkInit->SpdifrxClockSelection) 8003ef4: 687b ldr r3, [r7, #4] 8003ef6: 6e1b ldr r3, [r3, #96] ; 0x60 8003ef8: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8003efc: d02a beq.n 8003f54 8003efe: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8003f02: d824 bhi.n 8003f4e 8003f04: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8003f08: d018 beq.n 8003f3c 8003f0a: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8003f0e: d81e bhi.n 8003f4e 8003f10: 2b00 cmp r3, #0 8003f12: d003 beq.n 8003f1c 8003f14: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8003f18: d007 beq.n 8003f2a 8003f1a: e018 b.n 8003f4e { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003f1c: 4bab ldr r3, [pc, #684] ; (80041cc ) 8003f1e: 6adb ldr r3, [r3, #44] ; 0x2c 8003f20: 4aaa ldr r2, [pc, #680] ; (80041cc ) 8003f22: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003f26: 62d3 str r3, [r2, #44] ; 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 8003f28: e015 b.n 8003f56 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8003f2a: 687b ldr r3, [r7, #4] 8003f2c: 3304 adds r3, #4 8003f2e: 2102 movs r1, #2 8003f30: 4618 mov r0, r3 8003f32: f000 fecb bl 8004ccc 8003f36: 4603 mov r3, r0 8003f38: 75fb strb r3, [r7, #23] /* SPDIFRX clock source configuration done later after clock selection check */ break; 8003f3a: e00c b.n 8003f56 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8003f3c: 687b ldr r3, [r7, #4] 8003f3e: 3324 adds r3, #36 ; 0x24 8003f40: 2102 movs r1, #2 8003f42: 4618 mov r0, r3 8003f44: f000 ff74 bl 8004e30 8003f48: 4603 mov r3, r0 8003f4a: 75fb strb r3, [r7, #23] /* SPDIFRX clock source configuration done later after clock selection check */ break; 8003f4c: e003 b.n 8003f56 /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003f4e: 2301 movs r3, #1 8003f50: 75fb strb r3, [r7, #23] break; 8003f52: e000 b.n 8003f56 break; 8003f54: bf00 nop } if(ret == HAL_OK) 8003f56: 7dfb ldrb r3, [r7, #23] 8003f58: 2b00 cmp r3, #0 8003f5a: d109 bne.n 8003f70 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 8003f5c: 4b9b ldr r3, [pc, #620] ; (80041cc ) 8003f5e: 6d1b ldr r3, [r3, #80] ; 0x50 8003f60: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8003f64: 687b ldr r3, [r7, #4] 8003f66: 6e1b ldr r3, [r3, #96] ; 0x60 8003f68: 4998 ldr r1, [pc, #608] ; (80041cc ) 8003f6a: 4313 orrs r3, r2 8003f6c: 650b str r3, [r1, #80] ; 0x50 8003f6e: e001 b.n 8003f74 } else { /* set overall return value */ status = ret; 8003f70: 7dfb ldrb r3, [r7, #23] 8003f72: 75bb strb r3, [r7, #22] } } /*---------------------------- SAI1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8003f74: 687b ldr r3, [r7, #4] 8003f76: 681b ldr r3, [r3, #0] 8003f78: f403 7380 and.w r3, r3, #256 ; 0x100 8003f7c: 2b00 cmp r3, #0 8003f7e: d03d beq.n 8003ffc { switch(PeriphClkInit->Sai1ClockSelection) 8003f80: 687b ldr r3, [r7, #4] 8003f82: 6d5b ldr r3, [r3, #84] ; 0x54 8003f84: 2b04 cmp r3, #4 8003f86: d826 bhi.n 8003fd6 8003f88: a201 add r2, pc, #4 ; (adr r2, 8003f90 ) 8003f8a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003f8e: bf00 nop 8003f90: 08003fa5 .word 0x08003fa5 8003f94: 08003fb3 .word 0x08003fb3 8003f98: 08003fc5 .word 0x08003fc5 8003f9c: 08003fdd .word 0x08003fdd 8003fa0: 08003fdd .word 0x08003fdd { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003fa4: 4b89 ldr r3, [pc, #548] ; (80041cc ) 8003fa6: 6adb ldr r3, [r3, #44] ; 0x2c 8003fa8: 4a88 ldr r2, [pc, #544] ; (80041cc ) 8003faa: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003fae: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8003fb0: e015 b.n 8003fde case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8003fb2: 687b ldr r3, [r7, #4] 8003fb4: 3304 adds r3, #4 8003fb6: 2100 movs r1, #0 8003fb8: 4618 mov r0, r3 8003fba: f000 fe87 bl 8004ccc 8003fbe: 4603 mov r3, r0 8003fc0: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 8003fc2: e00c b.n 8003fde case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 8003fc4: 687b ldr r3, [r7, #4] 8003fc6: 3324 adds r3, #36 ; 0x24 8003fc8: 2100 movs r1, #0 8003fca: 4618 mov r0, r3 8003fcc: f000 ff30 bl 8004e30 8003fd0: 4603 mov r3, r0 8003fd2: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 8003fd4: e003 b.n 8003fde /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003fd6: 2301 movs r3, #1 8003fd8: 75fb strb r3, [r7, #23] break; 8003fda: e000 b.n 8003fde break; 8003fdc: bf00 nop } if(ret == HAL_OK) 8003fde: 7dfb ldrb r3, [r7, #23] 8003fe0: 2b00 cmp r3, #0 8003fe2: d109 bne.n 8003ff8 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8003fe4: 4b79 ldr r3, [pc, #484] ; (80041cc ) 8003fe6: 6d1b ldr r3, [r3, #80] ; 0x50 8003fe8: f023 0207 bic.w r2, r3, #7 8003fec: 687b ldr r3, [r7, #4] 8003fee: 6d5b ldr r3, [r3, #84] ; 0x54 8003ff0: 4976 ldr r1, [pc, #472] ; (80041cc ) 8003ff2: 4313 orrs r3, r2 8003ff4: 650b str r3, [r1, #80] ; 0x50 8003ff6: e001 b.n 8003ffc } else { /* set overall return value */ status = ret; 8003ff8: 7dfb ldrb r3, [r7, #23] 8003ffa: 75bb strb r3, [r7, #22] } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 8003ffc: 687b ldr r3, [r7, #4] 8003ffe: 681b ldr r3, [r3, #0] 8004000: f403 6380 and.w r3, r3, #1024 ; 0x400 8004004: 2b00 cmp r3, #0 8004006: d051 beq.n 80040ac { switch(PeriphClkInit->Sai4AClockSelection) 8004008: 687b ldr r3, [r7, #4] 800400a: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 800400e: f5b3 0f20 cmp.w r3, #10485760 ; 0xa00000 8004012: d036 beq.n 8004082 8004014: f5b3 0f20 cmp.w r3, #10485760 ; 0xa00000 8004018: d830 bhi.n 800407c 800401a: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 800401e: d032 beq.n 8004086 8004020: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 8004024: d82a bhi.n 800407c 8004026: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000 800402a: d02e beq.n 800408a 800402c: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000 8004030: d824 bhi.n 800407c 8004032: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8004036: d018 beq.n 800406a 8004038: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 800403c: d81e bhi.n 800407c 800403e: 2b00 cmp r3, #0 8004040: d003 beq.n 800404a 8004042: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8004046: d007 beq.n 8004058 8004048: e018 b.n 800407c { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800404a: 4b60 ldr r3, [pc, #384] ; (80041cc ) 800404c: 6adb ldr r3, [r3, #44] ; 0x2c 800404e: 4a5f ldr r2, [pc, #380] ; (80041cc ) 8004050: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004054: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8004056: e019 b.n 800408c case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8004058: 687b ldr r3, [r7, #4] 800405a: 3304 adds r3, #4 800405c: 2100 movs r1, #0 800405e: 4618 mov r0, r3 8004060: f000 fe34 bl 8004ccc 8004064: 4603 mov r3, r0 8004066: 75fb strb r3, [r7, #23] /* SAI2 clock source configuration done later after clock selection check */ break; 8004068: e010 b.n 800408c case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 800406a: 687b ldr r3, [r7, #4] 800406c: 3324 adds r3, #36 ; 0x24 800406e: 2100 movs r1, #0 8004070: 4618 mov r0, r3 8004072: f000 fedd bl 8004e30 8004076: 4603 mov r3, r0 8004078: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 800407a: e007 b.n 800408c /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800407c: 2301 movs r3, #1 800407e: 75fb strb r3, [r7, #23] break; 8004080: e004 b.n 800408c break; 8004082: bf00 nop 8004084: e002 b.n 800408c break; 8004086: bf00 nop 8004088: e000 b.n 800408c break; 800408a: bf00 nop } if(ret == HAL_OK) 800408c: 7dfb ldrb r3, [r7, #23] 800408e: 2b00 cmp r3, #0 8004090: d10a bne.n 80040a8 { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 8004092: 4b4e ldr r3, [pc, #312] ; (80041cc ) 8004094: 6d9b ldr r3, [r3, #88] ; 0x58 8004096: f423 0260 bic.w r2, r3, #14680064 ; 0xe00000 800409a: 687b ldr r3, [r7, #4] 800409c: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 80040a0: 494a ldr r1, [pc, #296] ; (80041cc ) 80040a2: 4313 orrs r3, r2 80040a4: 658b str r3, [r1, #88] ; 0x58 80040a6: e001 b.n 80040ac } else { /* set overall return value */ status = ret; 80040a8: 7dfb ldrb r3, [r7, #23] 80040aa: 75bb strb r3, [r7, #22] } } /*---------------------------- SAI4B configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 80040ac: 687b ldr r3, [r7, #4] 80040ae: 681b ldr r3, [r3, #0] 80040b0: f403 6300 and.w r3, r3, #2048 ; 0x800 80040b4: 2b00 cmp r3, #0 80040b6: d051 beq.n 800415c { switch(PeriphClkInit->Sai4BClockSelection) 80040b8: 687b ldr r3, [r7, #4] 80040ba: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 80040be: f1b3 6fa0 cmp.w r3, #83886080 ; 0x5000000 80040c2: d036 beq.n 8004132 80040c4: f1b3 6fa0 cmp.w r3, #83886080 ; 0x5000000 80040c8: d830 bhi.n 800412c 80040ca: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 80040ce: d032 beq.n 8004136 80040d0: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 80040d4: d82a bhi.n 800412c 80040d6: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000 80040da: d02e beq.n 800413a 80040dc: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000 80040e0: d824 bhi.n 800412c 80040e2: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 80040e6: d018 beq.n 800411a 80040e8: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 80040ec: d81e bhi.n 800412c 80040ee: 2b00 cmp r3, #0 80040f0: d003 beq.n 80040fa 80040f2: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 80040f6: d007 beq.n 8004108 80040f8: e018 b.n 800412c { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80040fa: 4b34 ldr r3, [pc, #208] ; (80041cc ) 80040fc: 6adb ldr r3, [r3, #44] ; 0x2c 80040fe: 4a33 ldr r2, [pc, #204] ; (80041cc ) 8004100: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004104: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8004106: e019 b.n 800413c case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8004108: 687b ldr r3, [r7, #4] 800410a: 3304 adds r3, #4 800410c: 2100 movs r1, #0 800410e: 4618 mov r0, r3 8004110: f000 fddc bl 8004ccc 8004114: 4603 mov r3, r0 8004116: 75fb strb r3, [r7, #23] /* SAI2 clock source configuration done later after clock selection check */ break; 8004118: e010 b.n 800413c case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800411a: 687b ldr r3, [r7, #4] 800411c: 3324 adds r3, #36 ; 0x24 800411e: 2100 movs r1, #0 8004120: 4618 mov r0, r3 8004122: f000 fe85 bl 8004e30 8004126: 4603 mov r3, r0 8004128: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 800412a: e007 b.n 800413c /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800412c: 2301 movs r3, #1 800412e: 75fb strb r3, [r7, #23] break; 8004130: e004 b.n 800413c break; 8004132: bf00 nop 8004134: e002 b.n 800413c break; 8004136: bf00 nop 8004138: e000 b.n 800413c break; 800413a: bf00 nop } if(ret == HAL_OK) 800413c: 7dfb ldrb r3, [r7, #23] 800413e: 2b00 cmp r3, #0 8004140: d10a bne.n 8004158 { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 8004142: 4b22 ldr r3, [pc, #136] ; (80041cc ) 8004144: 6d9b ldr r3, [r3, #88] ; 0x58 8004146: f023 62e0 bic.w r2, r3, #117440512 ; 0x7000000 800414a: 687b ldr r3, [r7, #4] 800414c: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 8004150: 491e ldr r1, [pc, #120] ; (80041cc ) 8004152: 4313 orrs r3, r2 8004154: 658b str r3, [r1, #88] ; 0x58 8004156: e001 b.n 800415c } else { /* set overall return value */ status = ret; 8004158: 7dfb ldrb r3, [r7, #23] 800415a: 75bb strb r3, [r7, #22] } #endif /*QUADSPI*/ #if defined(OCTOSPI1) || defined(OCTOSPI2) /*---------------------------- OCTOSPI configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) 800415c: 687b ldr r3, [r7, #4] 800415e: 681b ldr r3, [r3, #0] 8004160: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8004164: 2b00 cmp r3, #0 8004166: d035 beq.n 80041d4 { switch(PeriphClkInit->OspiClockSelection) 8004168: 687b ldr r3, [r7, #4] 800416a: 6c9b ldr r3, [r3, #72] ; 0x48 800416c: 2b30 cmp r3, #48 ; 0x30 800416e: d01c beq.n 80041aa 8004170: 2b30 cmp r3, #48 ; 0x30 8004172: d817 bhi.n 80041a4 8004174: 2b20 cmp r3, #32 8004176: d00c beq.n 8004192 8004178: 2b20 cmp r3, #32 800417a: d813 bhi.n 80041a4 800417c: 2b00 cmp r3, #0 800417e: d016 beq.n 80041ae 8004180: 2b10 cmp r3, #16 8004182: d10f bne.n 80041a4 { case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ /* Enable OSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004184: 4b11 ldr r3, [pc, #68] ; (80041cc ) 8004186: 6adb ldr r3, [r3, #44] ; 0x2c 8004188: 4a10 ldr r2, [pc, #64] ; (80041cc ) 800418a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800418e: 62d3 str r3, [r2, #44] ; 0x2c /* OSPI clock source configuration done later after clock selection check */ break; 8004190: e00e b.n 80041b0 case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8004192: 687b ldr r3, [r7, #4] 8004194: 3304 adds r3, #4 8004196: 2102 movs r1, #2 8004198: 4618 mov r0, r3 800419a: f000 fd97 bl 8004ccc 800419e: 4603 mov r3, r0 80041a0: 75fb strb r3, [r7, #23] /* OSPI clock source configuration done later after clock selection check */ break; 80041a2: e005 b.n 80041b0 case RCC_OSPICLKSOURCE_HCLK: /* HCLK clock selected as OSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 80041a4: 2301 movs r3, #1 80041a6: 75fb strb r3, [r7, #23] break; 80041a8: e002 b.n 80041b0 break; 80041aa: bf00 nop 80041ac: e000 b.n 80041b0 break; 80041ae: bf00 nop } if(ret == HAL_OK) 80041b0: 7dfb ldrb r3, [r7, #23] 80041b2: 2b00 cmp r3, #0 80041b4: d10c bne.n 80041d0 { /* Set the source of OSPI clock*/ __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); 80041b6: 4b05 ldr r3, [pc, #20] ; (80041cc ) 80041b8: 6cdb ldr r3, [r3, #76] ; 0x4c 80041ba: f023 0230 bic.w r2, r3, #48 ; 0x30 80041be: 687b ldr r3, [r7, #4] 80041c0: 6c9b ldr r3, [r3, #72] ; 0x48 80041c2: 4902 ldr r1, [pc, #8] ; (80041cc ) 80041c4: 4313 orrs r3, r2 80041c6: 64cb str r3, [r1, #76] ; 0x4c 80041c8: e004 b.n 80041d4 80041ca: bf00 nop 80041cc: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 80041d0: 7dfb ldrb r3, [r7, #23] 80041d2: 75bb strb r3, [r7, #22] } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 80041d4: 687b ldr r3, [r7, #4] 80041d6: 681b ldr r3, [r3, #0] 80041d8: f403 5380 and.w r3, r3, #4096 ; 0x1000 80041dc: 2b00 cmp r3, #0 80041de: d047 beq.n 8004270 { switch(PeriphClkInit->Spi123ClockSelection) 80041e0: 687b ldr r3, [r7, #4] 80041e2: 6d9b ldr r3, [r3, #88] ; 0x58 80041e4: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 80041e8: d030 beq.n 800424c 80041ea: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 80041ee: d82a bhi.n 8004246 80041f0: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 80041f4: d02c beq.n 8004250 80041f6: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 80041fa: d824 bhi.n 8004246 80041fc: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8004200: d018 beq.n 8004234 8004202: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8004206: d81e bhi.n 8004246 8004208: 2b00 cmp r3, #0 800420a: d003 beq.n 8004214 800420c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004210: d007 beq.n 8004222 8004212: e018 b.n 8004246 { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004214: 4bac ldr r3, [pc, #688] ; (80044c8 ) 8004216: 6adb ldr r3, [r3, #44] ; 0x2c 8004218: 4aab ldr r2, [pc, #684] ; (80044c8 ) 800421a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800421e: 62d3 str r3, [r2, #44] ; 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8004220: e017 b.n 8004252 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8004222: 687b ldr r3, [r7, #4] 8004224: 3304 adds r3, #4 8004226: 2100 movs r1, #0 8004228: 4618 mov r0, r3 800422a: f000 fd4f bl 8004ccc 800422e: 4603 mov r3, r0 8004230: 75fb strb r3, [r7, #23] /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8004232: e00e b.n 8004252 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 8004234: 687b ldr r3, [r7, #4] 8004236: 3324 adds r3, #36 ; 0x24 8004238: 2100 movs r1, #0 800423a: 4618 mov r0, r3 800423c: f000 fdf8 bl 8004e30 8004240: 4603 mov r3, r0 8004242: 75fb strb r3, [r7, #23] /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8004244: e005 b.n 8004252 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004246: 2301 movs r3, #1 8004248: 75fb strb r3, [r7, #23] break; 800424a: e002 b.n 8004252 break; 800424c: bf00 nop 800424e: e000 b.n 8004252 break; 8004250: bf00 nop } if(ret == HAL_OK) 8004252: 7dfb ldrb r3, [r7, #23] 8004254: 2b00 cmp r3, #0 8004256: d109 bne.n 800426c { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 8004258: 4b9b ldr r3, [pc, #620] ; (80044c8 ) 800425a: 6d1b ldr r3, [r3, #80] ; 0x50 800425c: f423 42e0 bic.w r2, r3, #28672 ; 0x7000 8004260: 687b ldr r3, [r7, #4] 8004262: 6d9b ldr r3, [r3, #88] ; 0x58 8004264: 4998 ldr r1, [pc, #608] ; (80044c8 ) 8004266: 4313 orrs r3, r2 8004268: 650b str r3, [r1, #80] ; 0x50 800426a: e001 b.n 8004270 } else { /* set overall return value */ status = ret; 800426c: 7dfb ldrb r3, [r7, #23] 800426e: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 8004270: 687b ldr r3, [r7, #4] 8004272: 681b ldr r3, [r3, #0] 8004274: f403 5300 and.w r3, r3, #8192 ; 0x2000 8004278: 2b00 cmp r3, #0 800427a: d049 beq.n 8004310 { switch(PeriphClkInit->Spi45ClockSelection) 800427c: 687b ldr r3, [r7, #4] 800427e: 6ddb ldr r3, [r3, #92] ; 0x5c 8004280: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8004284: d02e beq.n 80042e4 8004286: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 800428a: d828 bhi.n 80042de 800428c: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 8004290: d02a beq.n 80042e8 8004292: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 8004296: d822 bhi.n 80042de 8004298: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 800429c: d026 beq.n 80042ec 800429e: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 80042a2: d81c bhi.n 80042de 80042a4: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80042a8: d010 beq.n 80042cc 80042aa: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80042ae: d816 bhi.n 80042de 80042b0: 2b00 cmp r3, #0 80042b2: d01d beq.n 80042f0 80042b4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80042b8: d111 bne.n 80042de /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 80042ba: 687b ldr r3, [r7, #4] 80042bc: 3304 adds r3, #4 80042be: 2101 movs r1, #1 80042c0: 4618 mov r0, r3 80042c2: f000 fd03 bl 8004ccc 80042c6: 4603 mov r3, r0 80042c8: 75fb strb r3, [r7, #23] /* SPI4/5 clock source configuration done later after clock selection check */ break; 80042ca: e012 b.n 80042f2 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 80042cc: 687b ldr r3, [r7, #4] 80042ce: 3324 adds r3, #36 ; 0x24 80042d0: 2101 movs r1, #1 80042d2: 4618 mov r0, r3 80042d4: f000 fdac bl 8004e30 80042d8: 4603 mov r3, r0 80042da: 75fb strb r3, [r7, #23] /* SPI4/5 clock source configuration done later after clock selection check */ break; 80042dc: e009 b.n 80042f2 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80042de: 2301 movs r3, #1 80042e0: 75fb strb r3, [r7, #23] break; 80042e2: e006 b.n 80042f2 break; 80042e4: bf00 nop 80042e6: e004 b.n 80042f2 break; 80042e8: bf00 nop 80042ea: e002 b.n 80042f2 break; 80042ec: bf00 nop 80042ee: e000 b.n 80042f2 break; 80042f0: bf00 nop } if(ret == HAL_OK) 80042f2: 7dfb ldrb r3, [r7, #23] 80042f4: 2b00 cmp r3, #0 80042f6: d109 bne.n 800430c { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 80042f8: 4b73 ldr r3, [pc, #460] ; (80044c8 ) 80042fa: 6d1b ldr r3, [r3, #80] ; 0x50 80042fc: f423 22e0 bic.w r2, r3, #458752 ; 0x70000 8004300: 687b ldr r3, [r7, #4] 8004302: 6ddb ldr r3, [r3, #92] ; 0x5c 8004304: 4970 ldr r1, [pc, #448] ; (80044c8 ) 8004306: 4313 orrs r3, r2 8004308: 650b str r3, [r1, #80] ; 0x50 800430a: e001 b.n 8004310 } else { /* set overall return value */ status = ret; 800430c: 7dfb ldrb r3, [r7, #23] 800430e: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI6 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 8004310: 687b ldr r3, [r7, #4] 8004312: 681b ldr r3, [r3, #0] 8004314: f403 4380 and.w r3, r3, #16384 ; 0x4000 8004318: 2b00 cmp r3, #0 800431a: d04b beq.n 80043b4 { switch(PeriphClkInit->Spi6ClockSelection) 800431c: 687b ldr r3, [r7, #4] 800431e: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 8004322: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8004326: d02e beq.n 8004386 8004328: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 800432c: d828 bhi.n 8004380 800432e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004332: d02a beq.n 800438a 8004334: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004338: d822 bhi.n 8004380 800433a: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 800433e: d026 beq.n 800438e 8004340: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8004344: d81c bhi.n 8004380 8004346: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800434a: d010 beq.n 800436e 800434c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004350: d816 bhi.n 8004380 8004352: 2b00 cmp r3, #0 8004354: d01d beq.n 8004392 8004356: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 800435a: d111 bne.n 8004380 /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 800435c: 687b ldr r3, [r7, #4] 800435e: 3304 adds r3, #4 8004360: 2101 movs r1, #1 8004362: 4618 mov r0, r3 8004364: f000 fcb2 bl 8004ccc 8004368: 4603 mov r3, r0 800436a: 75fb strb r3, [r7, #23] /* SPI6 clock source configuration done later after clock selection check */ break; 800436c: e012 b.n 8004394 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 800436e: 687b ldr r3, [r7, #4] 8004370: 3324 adds r3, #36 ; 0x24 8004372: 2101 movs r1, #1 8004374: 4618 mov r0, r3 8004376: f000 fd5b bl 8004e30 800437a: 4603 mov r3, r0 800437c: 75fb strb r3, [r7, #23] /* SPI6 clock source configuration done later after clock selection check */ break; 800437e: e009 b.n 8004394 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 8004380: 2301 movs r3, #1 8004382: 75fb strb r3, [r7, #23] break; 8004384: e006 b.n 8004394 break; 8004386: bf00 nop 8004388: e004 b.n 8004394 break; 800438a: bf00 nop 800438c: e002 b.n 8004394 break; 800438e: bf00 nop 8004390: e000 b.n 8004394 break; 8004392: bf00 nop } if(ret == HAL_OK) 8004394: 7dfb ldrb r3, [r7, #23] 8004396: 2b00 cmp r3, #0 8004398: d10a bne.n 80043b0 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800439a: 4b4b ldr r3, [pc, #300] ; (80044c8 ) 800439c: 6d9b ldr r3, [r3, #88] ; 0x58 800439e: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000 80043a2: 687b ldr r3, [r7, #4] 80043a4: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 80043a8: 4947 ldr r1, [pc, #284] ; (80044c8 ) 80043aa: 4313 orrs r3, r2 80043ac: 658b str r3, [r1, #88] ; 0x58 80043ae: e001 b.n 80043b4 } else { /* set overall return value */ status = ret; 80043b0: 7dfb ldrb r3, [r7, #23] 80043b2: 75bb strb r3, [r7, #22] } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 80043b4: 687b ldr r3, [r7, #4] 80043b6: 681b ldr r3, [r3, #0] 80043b8: f403 4300 and.w r3, r3, #32768 ; 0x8000 80043bc: 2b00 cmp r3, #0 80043be: d02f beq.n 8004420 { switch(PeriphClkInit->FdcanClockSelection) 80043c0: 687b ldr r3, [r7, #4] 80043c2: 6e9b ldr r3, [r3, #104] ; 0x68 80043c4: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80043c8: d00e beq.n 80043e8 80043ca: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80043ce: d814 bhi.n 80043fa 80043d0: 2b00 cmp r3, #0 80043d2: d015 beq.n 8004400 80043d4: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 80043d8: d10f bne.n 80043fa { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80043da: 4b3b ldr r3, [pc, #236] ; (80044c8 ) 80043dc: 6adb ldr r3, [r3, #44] ; 0x2c 80043de: 4a3a ldr r2, [pc, #232] ; (80044c8 ) 80043e0: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80043e4: 62d3 str r3, [r2, #44] ; 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 80043e6: e00c b.n 8004402 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 80043e8: 687b ldr r3, [r7, #4] 80043ea: 3304 adds r3, #4 80043ec: 2101 movs r1, #1 80043ee: 4618 mov r0, r3 80043f0: f000 fc6c bl 8004ccc 80043f4: 4603 mov r3, r0 80043f6: 75fb strb r3, [r7, #23] /* FDCAN clock source configuration done later after clock selection check */ break; 80043f8: e003 b.n 8004402 /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80043fa: 2301 movs r3, #1 80043fc: 75fb strb r3, [r7, #23] break; 80043fe: e000 b.n 8004402 break; 8004400: bf00 nop } if(ret == HAL_OK) 8004402: 7dfb ldrb r3, [r7, #23] 8004404: 2b00 cmp r3, #0 8004406: d109 bne.n 800441c { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 8004408: 4b2f ldr r3, [pc, #188] ; (80044c8 ) 800440a: 6d1b ldr r3, [r3, #80] ; 0x50 800440c: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 8004410: 687b ldr r3, [r7, #4] 8004412: 6e9b ldr r3, [r3, #104] ; 0x68 8004414: 492c ldr r1, [pc, #176] ; (80044c8 ) 8004416: 4313 orrs r3, r2 8004418: 650b str r3, [r1, #80] ; 0x50 800441a: e001 b.n 8004420 } else { /* set overall return value */ status = ret; 800441c: 7dfb ldrb r3, [r7, #23] 800441e: 75bb strb r3, [r7, #22] } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 8004420: 687b ldr r3, [r7, #4] 8004422: 681b ldr r3, [r3, #0] 8004424: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8004428: 2b00 cmp r3, #0 800442a: d032 beq.n 8004492 { switch(PeriphClkInit->FmcClockSelection) 800442c: 687b ldr r3, [r7, #4] 800442e: 6c5b ldr r3, [r3, #68] ; 0x44 8004430: 2b03 cmp r3, #3 8004432: d81b bhi.n 800446c 8004434: a201 add r2, pc, #4 ; (adr r2, 800443c ) 8004436: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800443a: bf00 nop 800443c: 08004473 .word 0x08004473 8004440: 0800444d .word 0x0800444d 8004444: 0800445b .word 0x0800445b 8004448: 08004473 .word 0x08004473 { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800444c: 4b1e ldr r3, [pc, #120] ; (80044c8 ) 800444e: 6adb ldr r3, [r3, #44] ; 0x2c 8004450: 4a1d ldr r2, [pc, #116] ; (80044c8 ) 8004452: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004456: 62d3 str r3, [r2, #44] ; 0x2c /* FMC clock source configuration done later after clock selection check */ break; 8004458: e00c b.n 8004474 case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 800445a: 687b ldr r3, [r7, #4] 800445c: 3304 adds r3, #4 800445e: 2102 movs r1, #2 8004460: 4618 mov r0, r3 8004462: f000 fc33 bl 8004ccc 8004466: 4603 mov r3, r0 8004468: 75fb strb r3, [r7, #23] /* FMC clock source configuration done later after clock selection check */ break; 800446a: e003 b.n 8004474 case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 800446c: 2301 movs r3, #1 800446e: 75fb strb r3, [r7, #23] break; 8004470: e000 b.n 8004474 break; 8004472: bf00 nop } if(ret == HAL_OK) 8004474: 7dfb ldrb r3, [r7, #23] 8004476: 2b00 cmp r3, #0 8004478: d109 bne.n 800448e { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 800447a: 4b13 ldr r3, [pc, #76] ; (80044c8 ) 800447c: 6cdb ldr r3, [r3, #76] ; 0x4c 800447e: f023 0203 bic.w r2, r3, #3 8004482: 687b ldr r3, [r7, #4] 8004484: 6c5b ldr r3, [r3, #68] ; 0x44 8004486: 4910 ldr r1, [pc, #64] ; (80044c8 ) 8004488: 4313 orrs r3, r2 800448a: 64cb str r3, [r1, #76] ; 0x4c 800448c: e001 b.n 8004492 } else { /* set overall return value */ status = ret; 800448e: 7dfb ldrb r3, [r7, #23] 8004490: 75bb strb r3, [r7, #22] } } /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8004492: 687b ldr r3, [r7, #4] 8004494: 681b ldr r3, [r3, #0] 8004496: f403 0380 and.w r3, r3, #4194304 ; 0x400000 800449a: 2b00 cmp r3, #0 800449c: f000 808a beq.w 80045b4 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 80044a0: 4b0a ldr r3, [pc, #40] ; (80044cc ) 80044a2: 681b ldr r3, [r3, #0] 80044a4: 4a09 ldr r2, [pc, #36] ; (80044cc ) 80044a6: f443 7380 orr.w r3, r3, #256 ; 0x100 80044aa: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80044ac: f7fd f8d4 bl 8001658 80044b0: 6138 str r0, [r7, #16] while((PWR->CR1 & PWR_CR1_DBP) == 0U) 80044b2: e00d b.n 80044d0 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80044b4: f7fd f8d0 bl 8001658 80044b8: 4602 mov r2, r0 80044ba: 693b ldr r3, [r7, #16] 80044bc: 1ad3 subs r3, r2, r3 80044be: 2b64 cmp r3, #100 ; 0x64 80044c0: d906 bls.n 80044d0 { ret = HAL_TIMEOUT; 80044c2: 2303 movs r3, #3 80044c4: 75fb strb r3, [r7, #23] break; 80044c6: e009 b.n 80044dc 80044c8: 58024400 .word 0x58024400 80044cc: 58024800 .word 0x58024800 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 80044d0: 4bb9 ldr r3, [pc, #740] ; (80047b8 ) 80044d2: 681b ldr r3, [r3, #0] 80044d4: f403 7380 and.w r3, r3, #256 ; 0x100 80044d8: 2b00 cmp r3, #0 80044da: d0eb beq.n 80044b4 } } if(ret == HAL_OK) 80044dc: 7dfb ldrb r3, [r7, #23] 80044de: 2b00 cmp r3, #0 80044e0: d166 bne.n 80045b0 { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 80044e2: 4bb6 ldr r3, [pc, #728] ; (80047bc ) 80044e4: 6f1a ldr r2, [r3, #112] ; 0x70 80044e6: 687b ldr r3, [r7, #4] 80044e8: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 80044ec: 4053 eors r3, r2 80044ee: f403 7340 and.w r3, r3, #768 ; 0x300 80044f2: 2b00 cmp r3, #0 80044f4: d013 beq.n 800451e { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80044f6: 4bb1 ldr r3, [pc, #708] ; (80047bc ) 80044f8: 6f1b ldr r3, [r3, #112] ; 0x70 80044fa: f423 7340 bic.w r3, r3, #768 ; 0x300 80044fe: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8004500: 4bae ldr r3, [pc, #696] ; (80047bc ) 8004502: 6f1b ldr r3, [r3, #112] ; 0x70 8004504: 4aad ldr r2, [pc, #692] ; (80047bc ) 8004506: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800450a: 6713 str r3, [r2, #112] ; 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 800450c: 4bab ldr r3, [pc, #684] ; (80047bc ) 800450e: 6f1b ldr r3, [r3, #112] ; 0x70 8004510: 4aaa ldr r2, [pc, #680] ; (80047bc ) 8004512: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8004516: 6713 str r3, [r2, #112] ; 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 8004518: 4aa8 ldr r2, [pc, #672] ; (80047bc ) 800451a: 68fb ldr r3, [r7, #12] 800451c: 6713 str r3, [r2, #112] ; 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 800451e: 687b ldr r3, [r7, #4] 8004520: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 8004524: f5b3 7f80 cmp.w r3, #256 ; 0x100 8004528: d115 bne.n 8004556 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800452a: f7fd f895 bl 8001658 800452e: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8004530: e00b b.n 800454a { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004532: f7fd f891 bl 8001658 8004536: 4602 mov r2, r0 8004538: 693b ldr r3, [r7, #16] 800453a: 1ad3 subs r3, r2, r3 800453c: f241 3288 movw r2, #5000 ; 0x1388 8004540: 4293 cmp r3, r2 8004542: d902 bls.n 800454a { ret = HAL_TIMEOUT; 8004544: 2303 movs r3, #3 8004546: 75fb strb r3, [r7, #23] break; 8004548: e005 b.n 8004556 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800454a: 4b9c ldr r3, [pc, #624] ; (80047bc ) 800454c: 6f1b ldr r3, [r3, #112] ; 0x70 800454e: f003 0302 and.w r3, r3, #2 8004552: 2b00 cmp r3, #0 8004554: d0ed beq.n 8004532 } } } if(ret == HAL_OK) 8004556: 7dfb ldrb r3, [r7, #23] 8004558: 2b00 cmp r3, #0 800455a: d126 bne.n 80045aa { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800455c: 687b ldr r3, [r7, #4] 800455e: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 8004562: f403 7340 and.w r3, r3, #768 ; 0x300 8004566: f5b3 7f40 cmp.w r3, #768 ; 0x300 800456a: d10d bne.n 8004588 800456c: 4b93 ldr r3, [pc, #588] ; (80047bc ) 800456e: 691b ldr r3, [r3, #16] 8004570: f423 527c bic.w r2, r3, #16128 ; 0x3f00 8004574: 687b ldr r3, [r7, #4] 8004576: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 800457a: 0919 lsrs r1, r3, #4 800457c: 4b90 ldr r3, [pc, #576] ; (80047c0 ) 800457e: 400b ands r3, r1 8004580: 498e ldr r1, [pc, #568] ; (80047bc ) 8004582: 4313 orrs r3, r2 8004584: 610b str r3, [r1, #16] 8004586: e005 b.n 8004594 8004588: 4b8c ldr r3, [pc, #560] ; (80047bc ) 800458a: 691b ldr r3, [r3, #16] 800458c: 4a8b ldr r2, [pc, #556] ; (80047bc ) 800458e: f423 537c bic.w r3, r3, #16128 ; 0x3f00 8004592: 6113 str r3, [r2, #16] 8004594: 4b89 ldr r3, [pc, #548] ; (80047bc ) 8004596: 6f1a ldr r2, [r3, #112] ; 0x70 8004598: 687b ldr r3, [r7, #4] 800459a: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 800459e: f3c3 030b ubfx r3, r3, #0, #12 80045a2: 4986 ldr r1, [pc, #536] ; (80047bc ) 80045a4: 4313 orrs r3, r2 80045a6: 670b str r3, [r1, #112] ; 0x70 80045a8: e004 b.n 80045b4 } else { /* set overall return value */ status = ret; 80045aa: 7dfb ldrb r3, [r7, #23] 80045ac: 75bb strb r3, [r7, #22] 80045ae: e001 b.n 80045b4 } } else { /* set overall return value */ status = ret; 80045b0: 7dfb ldrb r3, [r7, #23] 80045b2: 75bb strb r3, [r7, #22] } } /*-------------------------- USART1/6 configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 80045b4: 687b ldr r3, [r7, #4] 80045b6: 681b ldr r3, [r3, #0] 80045b8: f003 0301 and.w r3, r3, #1 80045bc: 2b00 cmp r3, #0 80045be: d07e beq.n 80046be { switch(PeriphClkInit->Usart16ClockSelection) 80045c0: 687b ldr r3, [r7, #4] 80045c2: 6f5b ldr r3, [r3, #116] ; 0x74 80045c4: 2b28 cmp r3, #40 ; 0x28 80045c6: d867 bhi.n 8004698 80045c8: a201 add r2, pc, #4 ; (adr r2, 80045d0 ) 80045ca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80045ce: bf00 nop 80045d0: 0800469f .word 0x0800469f 80045d4: 08004699 .word 0x08004699 80045d8: 08004699 .word 0x08004699 80045dc: 08004699 .word 0x08004699 80045e0: 08004699 .word 0x08004699 80045e4: 08004699 .word 0x08004699 80045e8: 08004699 .word 0x08004699 80045ec: 08004699 .word 0x08004699 80045f0: 08004675 .word 0x08004675 80045f4: 08004699 .word 0x08004699 80045f8: 08004699 .word 0x08004699 80045fc: 08004699 .word 0x08004699 8004600: 08004699 .word 0x08004699 8004604: 08004699 .word 0x08004699 8004608: 08004699 .word 0x08004699 800460c: 08004699 .word 0x08004699 8004610: 08004687 .word 0x08004687 8004614: 08004699 .word 0x08004699 8004618: 08004699 .word 0x08004699 800461c: 08004699 .word 0x08004699 8004620: 08004699 .word 0x08004699 8004624: 08004699 .word 0x08004699 8004628: 08004699 .word 0x08004699 800462c: 08004699 .word 0x08004699 8004630: 0800469f .word 0x0800469f 8004634: 08004699 .word 0x08004699 8004638: 08004699 .word 0x08004699 800463c: 08004699 .word 0x08004699 8004640: 08004699 .word 0x08004699 8004644: 08004699 .word 0x08004699 8004648: 08004699 .word 0x08004699 800464c: 08004699 .word 0x08004699 8004650: 0800469f .word 0x0800469f 8004654: 08004699 .word 0x08004699 8004658: 08004699 .word 0x08004699 800465c: 08004699 .word 0x08004699 8004660: 08004699 .word 0x08004699 8004664: 08004699 .word 0x08004699 8004668: 08004699 .word 0x08004699 800466c: 08004699 .word 0x08004699 8004670: 0800469f .word 0x0800469f case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8004674: 687b ldr r3, [r7, #4] 8004676: 3304 adds r3, #4 8004678: 2101 movs r1, #1 800467a: 4618 mov r0, r3 800467c: f000 fb26 bl 8004ccc 8004680: 4603 mov r3, r0 8004682: 75fb strb r3, [r7, #23] /* USART1/6 clock source configuration done later after clock selection check */ break; 8004684: e00c b.n 80046a0 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8004686: 687b ldr r3, [r7, #4] 8004688: 3324 adds r3, #36 ; 0x24 800468a: 2101 movs r1, #1 800468c: 4618 mov r0, r3 800468e: f000 fbcf bl 8004e30 8004692: 4603 mov r3, r0 8004694: 75fb strb r3, [r7, #23] /* USART1/6 clock source configuration done later after clock selection check */ break; 8004696: e003 b.n 80046a0 /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004698: 2301 movs r3, #1 800469a: 75fb strb r3, [r7, #23] break; 800469c: e000 b.n 80046a0 break; 800469e: bf00 nop } if(ret == HAL_OK) 80046a0: 7dfb ldrb r3, [r7, #23] 80046a2: 2b00 cmp r3, #0 80046a4: d109 bne.n 80046ba { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 80046a6: 4b45 ldr r3, [pc, #276] ; (80047bc ) 80046a8: 6d5b ldr r3, [r3, #84] ; 0x54 80046aa: f023 0238 bic.w r2, r3, #56 ; 0x38 80046ae: 687b ldr r3, [r7, #4] 80046b0: 6f5b ldr r3, [r3, #116] ; 0x74 80046b2: 4942 ldr r1, [pc, #264] ; (80047bc ) 80046b4: 4313 orrs r3, r2 80046b6: 654b str r3, [r1, #84] ; 0x54 80046b8: e001 b.n 80046be } else { /* set overall return value */ status = ret; 80046ba: 7dfb ldrb r3, [r7, #23] 80046bc: 75bb strb r3, [r7, #22] } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 80046be: 687b ldr r3, [r7, #4] 80046c0: 681b ldr r3, [r3, #0] 80046c2: f003 0302 and.w r3, r3, #2 80046c6: 2b00 cmp r3, #0 80046c8: d037 beq.n 800473a { switch(PeriphClkInit->Usart234578ClockSelection) 80046ca: 687b ldr r3, [r7, #4] 80046cc: 6f1b ldr r3, [r3, #112] ; 0x70 80046ce: 2b05 cmp r3, #5 80046d0: d820 bhi.n 8004714 80046d2: a201 add r2, pc, #4 ; (adr r2, 80046d8 ) 80046d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80046d8: 0800471b .word 0x0800471b 80046dc: 080046f1 .word 0x080046f1 80046e0: 08004703 .word 0x08004703 80046e4: 0800471b .word 0x0800471b 80046e8: 0800471b .word 0x0800471b 80046ec: 0800471b .word 0x0800471b case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 80046f0: 687b ldr r3, [r7, #4] 80046f2: 3304 adds r3, #4 80046f4: 2101 movs r1, #1 80046f6: 4618 mov r0, r3 80046f8: f000 fae8 bl 8004ccc 80046fc: 4603 mov r3, r0 80046fe: 75fb strb r3, [r7, #23] /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8004700: e00c b.n 800471c case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8004702: 687b ldr r3, [r7, #4] 8004704: 3324 adds r3, #36 ; 0x24 8004706: 2101 movs r1, #1 8004708: 4618 mov r0, r3 800470a: f000 fb91 bl 8004e30 800470e: 4603 mov r3, r0 8004710: 75fb strb r3, [r7, #23] /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8004712: e003 b.n 800471c /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004714: 2301 movs r3, #1 8004716: 75fb strb r3, [r7, #23] break; 8004718: e000 b.n 800471c break; 800471a: bf00 nop } if(ret == HAL_OK) 800471c: 7dfb ldrb r3, [r7, #23] 800471e: 2b00 cmp r3, #0 8004720: d109 bne.n 8004736 { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 8004722: 4b26 ldr r3, [pc, #152] ; (80047bc ) 8004724: 6d5b ldr r3, [r3, #84] ; 0x54 8004726: f023 0207 bic.w r2, r3, #7 800472a: 687b ldr r3, [r7, #4] 800472c: 6f1b ldr r3, [r3, #112] ; 0x70 800472e: 4923 ldr r1, [pc, #140] ; (80047bc ) 8004730: 4313 orrs r3, r2 8004732: 654b str r3, [r1, #84] ; 0x54 8004734: e001 b.n 800473a } else { /* set overall return value */ status = ret; 8004736: 7dfb ldrb r3, [r7, #23] 8004738: 75bb strb r3, [r7, #22] } } /*-------------------------- LPUART1 Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800473a: 687b ldr r3, [r7, #4] 800473c: 681b ldr r3, [r3, #0] 800473e: f003 0304 and.w r3, r3, #4 8004742: 2b00 cmp r3, #0 8004744: d040 beq.n 80047c8 { switch(PeriphClkInit->Lpuart1ClockSelection) 8004746: 687b ldr r3, [r7, #4] 8004748: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 800474c: 2b05 cmp r3, #5 800474e: d821 bhi.n 8004794 8004750: a201 add r2, pc, #4 ; (adr r2, 8004758 ) 8004752: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004756: bf00 nop 8004758: 0800479b .word 0x0800479b 800475c: 08004771 .word 0x08004771 8004760: 08004783 .word 0x08004783 8004764: 0800479b .word 0x0800479b 8004768: 0800479b .word 0x0800479b 800476c: 0800479b .word 0x0800479b case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8004770: 687b ldr r3, [r7, #4] 8004772: 3304 adds r3, #4 8004774: 2101 movs r1, #1 8004776: 4618 mov r0, r3 8004778: f000 faa8 bl 8004ccc 800477c: 4603 mov r3, r0 800477e: 75fb strb r3, [r7, #23] /* LPUART1 clock source configuration done later after clock selection check */ break; 8004780: e00c b.n 800479c case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8004782: 687b ldr r3, [r7, #4] 8004784: 3324 adds r3, #36 ; 0x24 8004786: 2101 movs r1, #1 8004788: 4618 mov r0, r3 800478a: f000 fb51 bl 8004e30 800478e: 4603 mov r3, r0 8004790: 75fb strb r3, [r7, #23] /* LPUART1 clock source configuration done later after clock selection check */ break; 8004792: e003 b.n 800479c /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004794: 2301 movs r3, #1 8004796: 75fb strb r3, [r7, #23] break; 8004798: e000 b.n 800479c break; 800479a: bf00 nop } if(ret == HAL_OK) 800479c: 7dfb ldrb r3, [r7, #23] 800479e: 2b00 cmp r3, #0 80047a0: d110 bne.n 80047c4 { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 80047a2: 4b06 ldr r3, [pc, #24] ; (80047bc ) 80047a4: 6d9b ldr r3, [r3, #88] ; 0x58 80047a6: f023 0207 bic.w r2, r3, #7 80047aa: 687b ldr r3, [r7, #4] 80047ac: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 80047b0: 4902 ldr r1, [pc, #8] ; (80047bc ) 80047b2: 4313 orrs r3, r2 80047b4: 658b str r3, [r1, #88] ; 0x58 80047b6: e007 b.n 80047c8 80047b8: 58024800 .word 0x58024800 80047bc: 58024400 .word 0x58024400 80047c0: 00ffffcf .word 0x00ffffcf } else { /* set overall return value */ status = ret; 80047c4: 7dfb ldrb r3, [r7, #23] 80047c6: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 80047c8: 687b ldr r3, [r7, #4] 80047ca: 681b ldr r3, [r3, #0] 80047cc: f003 0320 and.w r3, r3, #32 80047d0: 2b00 cmp r3, #0 80047d2: d04b beq.n 800486c { switch(PeriphClkInit->Lptim1ClockSelection) 80047d4: 687b ldr r3, [r7, #4] 80047d6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80047da: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 80047de: d02e beq.n 800483e 80047e0: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 80047e4: d828 bhi.n 8004838 80047e6: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80047ea: d02a beq.n 8004842 80047ec: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80047f0: d822 bhi.n 8004838 80047f2: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 80047f6: d026 beq.n 8004846 80047f8: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 80047fc: d81c bhi.n 8004838 80047fe: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004802: d010 beq.n 8004826 8004804: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004808: d816 bhi.n 8004838 800480a: 2b00 cmp r3, #0 800480c: d01d beq.n 800484a 800480e: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8004812: d111 bne.n 8004838 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8004814: 687b ldr r3, [r7, #4] 8004816: 3304 adds r3, #4 8004818: 2100 movs r1, #0 800481a: 4618 mov r0, r3 800481c: f000 fa56 bl 8004ccc 8004820: 4603 mov r3, r0 8004822: 75fb strb r3, [r7, #23] /* LPTIM1 clock source configuration done later after clock selection check */ break; 8004824: e012 b.n 800484c case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8004826: 687b ldr r3, [r7, #4] 8004828: 3324 adds r3, #36 ; 0x24 800482a: 2102 movs r1, #2 800482c: 4618 mov r0, r3 800482e: f000 faff bl 8004e30 8004832: 4603 mov r3, r0 8004834: 75fb strb r3, [r7, #23] /* LPTIM1 clock source configuration done later after clock selection check */ break; 8004836: e009 b.n 800484c /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004838: 2301 movs r3, #1 800483a: 75fb strb r3, [r7, #23] break; 800483c: e006 b.n 800484c break; 800483e: bf00 nop 8004840: e004 b.n 800484c break; 8004842: bf00 nop 8004844: e002 b.n 800484c break; 8004846: bf00 nop 8004848: e000 b.n 800484c break; 800484a: bf00 nop } if(ret == HAL_OK) 800484c: 7dfb ldrb r3, [r7, #23] 800484e: 2b00 cmp r3, #0 8004850: d10a bne.n 8004868 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8004852: 4bb2 ldr r3, [pc, #712] ; (8004b1c ) 8004854: 6d5b ldr r3, [r3, #84] ; 0x54 8004856: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000 800485a: 687b ldr r3, [r7, #4] 800485c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8004860: 49ae ldr r1, [pc, #696] ; (8004b1c ) 8004862: 4313 orrs r3, r2 8004864: 654b str r3, [r1, #84] ; 0x54 8004866: e001 b.n 800486c } else { /* set overall return value */ status = ret; 8004868: 7dfb ldrb r3, [r7, #23] 800486a: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800486c: 687b ldr r3, [r7, #4] 800486e: 681b ldr r3, [r3, #0] 8004870: f003 0340 and.w r3, r3, #64 ; 0x40 8004874: 2b00 cmp r3, #0 8004876: d04b beq.n 8004910 { switch(PeriphClkInit->Lptim2ClockSelection) 8004878: 687b ldr r3, [r7, #4] 800487a: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 800487e: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 8004882: d02e beq.n 80048e2 8004884: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 8004888: d828 bhi.n 80048dc 800488a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 800488e: d02a beq.n 80048e6 8004890: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004894: d822 bhi.n 80048dc 8004896: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 800489a: d026 beq.n 80048ea 800489c: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 80048a0: d81c bhi.n 80048dc 80048a2: f5b3 6f00 cmp.w r3, #2048 ; 0x800 80048a6: d010 beq.n 80048ca 80048a8: f5b3 6f00 cmp.w r3, #2048 ; 0x800 80048ac: d816 bhi.n 80048dc 80048ae: 2b00 cmp r3, #0 80048b0: d01d beq.n 80048ee 80048b2: f5b3 6f80 cmp.w r3, #1024 ; 0x400 80048b6: d111 bne.n 80048dc /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 80048b8: 687b ldr r3, [r7, #4] 80048ba: 3304 adds r3, #4 80048bc: 2100 movs r1, #0 80048be: 4618 mov r0, r3 80048c0: f000 fa04 bl 8004ccc 80048c4: 4603 mov r3, r0 80048c6: 75fb strb r3, [r7, #23] /* LPTIM2 clock source configuration done later after clock selection check */ break; 80048c8: e012 b.n 80048f0 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 80048ca: 687b ldr r3, [r7, #4] 80048cc: 3324 adds r3, #36 ; 0x24 80048ce: 2102 movs r1, #2 80048d0: 4618 mov r0, r3 80048d2: f000 faad bl 8004e30 80048d6: 4603 mov r3, r0 80048d8: 75fb strb r3, [r7, #23] /* LPTIM2 clock source configuration done later after clock selection check */ break; 80048da: e009 b.n 80048f0 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80048dc: 2301 movs r3, #1 80048de: 75fb strb r3, [r7, #23] break; 80048e0: e006 b.n 80048f0 break; 80048e2: bf00 nop 80048e4: e004 b.n 80048f0 break; 80048e6: bf00 nop 80048e8: e002 b.n 80048f0 break; 80048ea: bf00 nop 80048ec: e000 b.n 80048f0 break; 80048ee: bf00 nop } if(ret == HAL_OK) 80048f0: 7dfb ldrb r3, [r7, #23] 80048f2: 2b00 cmp r3, #0 80048f4: d10a bne.n 800490c { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 80048f6: 4b89 ldr r3, [pc, #548] ; (8004b1c ) 80048f8: 6d9b ldr r3, [r3, #88] ; 0x58 80048fa: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 80048fe: 687b ldr r3, [r7, #4] 8004900: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8004904: 4985 ldr r1, [pc, #532] ; (8004b1c ) 8004906: 4313 orrs r3, r2 8004908: 658b str r3, [r1, #88] ; 0x58 800490a: e001 b.n 8004910 } else { /* set overall return value */ status = ret; 800490c: 7dfb ldrb r3, [r7, #23] 800490e: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 8004910: 687b ldr r3, [r7, #4] 8004912: 681b ldr r3, [r3, #0] 8004914: f003 0380 and.w r3, r3, #128 ; 0x80 8004918: 2b00 cmp r3, #0 800491a: d04b beq.n 80049b4 { switch(PeriphClkInit->Lptim345ClockSelection) 800491c: 687b ldr r3, [r7, #4] 800491e: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8004922: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 8004926: d02e beq.n 8004986 8004928: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 800492c: d828 bhi.n 8004980 800492e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8004932: d02a beq.n 800498a 8004934: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8004938: d822 bhi.n 8004980 800493a: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 800493e: d026 beq.n 800498e 8004940: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 8004944: d81c bhi.n 8004980 8004946: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 800494a: d010 beq.n 800496e 800494c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8004950: d816 bhi.n 8004980 8004952: 2b00 cmp r3, #0 8004954: d01d beq.n 8004992 8004956: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800495a: d111 bne.n 8004980 case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 800495c: 687b ldr r3, [r7, #4] 800495e: 3304 adds r3, #4 8004960: 2100 movs r1, #0 8004962: 4618 mov r0, r3 8004964: f000 f9b2 bl 8004ccc 8004968: 4603 mov r3, r0 800496a: 75fb strb r3, [r7, #23] /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800496c: e012 b.n 8004994 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 800496e: 687b ldr r3, [r7, #4] 8004970: 3324 adds r3, #36 ; 0x24 8004972: 2102 movs r1, #2 8004974: 4618 mov r0, r3 8004976: f000 fa5b bl 8004e30 800497a: 4603 mov r3, r0 800497c: 75fb strb r3, [r7, #23] /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800497e: e009 b.n 8004994 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004980: 2301 movs r3, #1 8004982: 75fb strb r3, [r7, #23] break; 8004984: e006 b.n 8004994 break; 8004986: bf00 nop 8004988: e004 b.n 8004994 break; 800498a: bf00 nop 800498c: e002 b.n 8004994 break; 800498e: bf00 nop 8004990: e000 b.n 8004994 break; 8004992: bf00 nop } if(ret == HAL_OK) 8004994: 7dfb ldrb r3, [r7, #23] 8004996: 2b00 cmp r3, #0 8004998: d10a bne.n 80049b0 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 800499a: 4b60 ldr r3, [pc, #384] ; (8004b1c ) 800499c: 6d9b ldr r3, [r3, #88] ; 0x58 800499e: f423 4260 bic.w r2, r3, #57344 ; 0xe000 80049a2: 687b ldr r3, [r7, #4] 80049a4: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 80049a8: 495c ldr r1, [pc, #368] ; (8004b1c ) 80049aa: 4313 orrs r3, r2 80049ac: 658b str r3, [r1, #88] ; 0x58 80049ae: e001 b.n 80049b4 } else { /* set overall return value */ status = ret; 80049b0: 7dfb ldrb r3, [r7, #23] 80049b2: 75bb strb r3, [r7, #22] } } /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ #if defined(I2C5) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) 80049b4: 687b ldr r3, [r7, #4] 80049b6: 681b ldr r3, [r3, #0] 80049b8: f003 0308 and.w r3, r3, #8 80049bc: 2b00 cmp r3, #0 80049be: d018 beq.n 80049f2 { /* Check the parameters */ assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection)); if ((PeriphClkInit->I2c1235ClockSelection )== RCC_I2C1235CLKSOURCE_PLL3 ) 80049c0: 687b ldr r3, [r7, #4] 80049c2: 6fdb ldr r3, [r3, #124] ; 0x7c 80049c4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80049c8: d10a bne.n 80049e0 { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 80049ca: 687b ldr r3, [r7, #4] 80049cc: 3324 adds r3, #36 ; 0x24 80049ce: 2102 movs r1, #2 80049d0: 4618 mov r0, r3 80049d2: f000 fa2d bl 8004e30 80049d6: 4603 mov r3, r0 80049d8: 2b00 cmp r3, #0 80049da: d001 beq.n 80049e0 { status = HAL_ERROR; 80049dc: 2301 movs r3, #1 80049de: 75bb strb r3, [r7, #22] } } __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); 80049e0: 4b4e ldr r3, [pc, #312] ; (8004b1c ) 80049e2: 6d5b ldr r3, [r3, #84] ; 0x54 80049e4: f423 5240 bic.w r2, r3, #12288 ; 0x3000 80049e8: 687b ldr r3, [r7, #4] 80049ea: 6fdb ldr r3, [r3, #124] ; 0x7c 80049ec: 494b ldr r1, [pc, #300] ; (8004b1c ) 80049ee: 4313 orrs r3, r2 80049f0: 654b str r3, [r1, #84] ; 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 80049f2: 687b ldr r3, [r7, #4] 80049f4: 681b ldr r3, [r3, #0] 80049f6: f003 0310 and.w r3, r3, #16 80049fa: 2b00 cmp r3, #0 80049fc: d01a beq.n 8004a34 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 ) 80049fe: 687b ldr r3, [r7, #4] 8004a00: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8004a04: f5b3 7f80 cmp.w r3, #256 ; 0x100 8004a08: d10a bne.n 8004a20 { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 8004a0a: 687b ldr r3, [r7, #4] 8004a0c: 3324 adds r3, #36 ; 0x24 8004a0e: 2102 movs r1, #2 8004a10: 4618 mov r0, r3 8004a12: f000 fa0d bl 8004e30 8004a16: 4603 mov r3, r0 8004a18: 2b00 cmp r3, #0 8004a1a: d001 beq.n 8004a20 { status = HAL_ERROR; 8004a1c: 2301 movs r3, #1 8004a1e: 75bb strb r3, [r7, #22] } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 8004a20: 4b3e ldr r3, [pc, #248] ; (8004b1c ) 8004a22: 6d9b ldr r3, [r3, #88] ; 0x58 8004a24: f423 7240 bic.w r2, r3, #768 ; 0x300 8004a28: 687b ldr r3, [r7, #4] 8004a2a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8004a2e: 493b ldr r1, [pc, #236] ; (8004b1c ) 8004a30: 4313 orrs r3, r2 8004a32: 658b str r3, [r1, #88] ; 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8004a34: 687b ldr r3, [r7, #4] 8004a36: 681b ldr r3, [r3, #0] 8004a38: f403 2300 and.w r3, r3, #524288 ; 0x80000 8004a3c: 2b00 cmp r3, #0 8004a3e: d034 beq.n 8004aaa { switch(PeriphClkInit->AdcClockSelection) 8004a40: 687b ldr r3, [r7, #4] 8004a42: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8004a46: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8004a4a: d01d beq.n 8004a88 8004a4c: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8004a50: d817 bhi.n 8004a82 8004a52: 2b00 cmp r3, #0 8004a54: d003 beq.n 8004a5e 8004a56: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8004a5a: d009 beq.n 8004a70 8004a5c: e011 b.n 8004a82 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8004a5e: 687b ldr r3, [r7, #4] 8004a60: 3304 adds r3, #4 8004a62: 2100 movs r1, #0 8004a64: 4618 mov r0, r3 8004a66: f000 f931 bl 8004ccc 8004a6a: 4603 mov r3, r0 8004a6c: 75fb strb r3, [r7, #23] /* ADC clock source configuration done later after clock selection check */ break; 8004a6e: e00c b.n 8004a8a case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8004a70: 687b ldr r3, [r7, #4] 8004a72: 3324 adds r3, #36 ; 0x24 8004a74: 2102 movs r1, #2 8004a76: 4618 mov r0, r3 8004a78: f000 f9da bl 8004e30 8004a7c: 4603 mov r3, r0 8004a7e: 75fb strb r3, [r7, #23] /* ADC clock source configuration done later after clock selection check */ break; 8004a80: e003 b.n 8004a8a /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004a82: 2301 movs r3, #1 8004a84: 75fb strb r3, [r7, #23] break; 8004a86: e000 b.n 8004a8a break; 8004a88: bf00 nop } if(ret == HAL_OK) 8004a8a: 7dfb ldrb r3, [r7, #23] 8004a8c: 2b00 cmp r3, #0 8004a8e: d10a bne.n 8004aa6 { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8004a90: 4b22 ldr r3, [pc, #136] ; (8004b1c ) 8004a92: 6d9b ldr r3, [r3, #88] ; 0x58 8004a94: f423 3240 bic.w r2, r3, #196608 ; 0x30000 8004a98: 687b ldr r3, [r7, #4] 8004a9a: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8004a9e: 491f ldr r1, [pc, #124] ; (8004b1c ) 8004aa0: 4313 orrs r3, r2 8004aa2: 658b str r3, [r1, #88] ; 0x58 8004aa4: e001 b.n 8004aaa } else { /* set overall return value */ status = ret; 8004aa6: 7dfb ldrb r3, [r7, #23] 8004aa8: 75bb strb r3, [r7, #22] } } /*------------------------------ USB Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8004aaa: 687b ldr r3, [r7, #4] 8004aac: 681b ldr r3, [r3, #0] 8004aae: f403 2380 and.w r3, r3, #262144 ; 0x40000 8004ab2: 2b00 cmp r3, #0 8004ab4: d036 beq.n 8004b24 { switch(PeriphClkInit->UsbClockSelection) 8004ab6: 687b ldr r3, [r7, #4] 8004ab8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8004abc: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8004ac0: d01c beq.n 8004afc 8004ac2: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8004ac6: d816 bhi.n 8004af6 8004ac8: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8004acc: d003 beq.n 8004ad6 8004ace: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8004ad2: d007 beq.n 8004ae4 8004ad4: e00f b.n 8004af6 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004ad6: 4b11 ldr r3, [pc, #68] ; (8004b1c ) 8004ad8: 6adb ldr r3, [r3, #44] ; 0x2c 8004ada: 4a10 ldr r2, [pc, #64] ; (8004b1c ) 8004adc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004ae0: 62d3 str r3, [r2, #44] ; 0x2c /* USB clock source configuration done later after clock selection check */ break; 8004ae2: e00c b.n 8004afe case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8004ae4: 687b ldr r3, [r7, #4] 8004ae6: 3324 adds r3, #36 ; 0x24 8004ae8: 2101 movs r1, #1 8004aea: 4618 mov r0, r3 8004aec: f000 f9a0 bl 8004e30 8004af0: 4603 mov r3, r0 8004af2: 75fb strb r3, [r7, #23] /* USB clock source configuration done later after clock selection check */ break; 8004af4: e003 b.n 8004afe /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004af6: 2301 movs r3, #1 8004af8: 75fb strb r3, [r7, #23] break; 8004afa: e000 b.n 8004afe break; 8004afc: bf00 nop } if(ret == HAL_OK) 8004afe: 7dfb ldrb r3, [r7, #23] 8004b00: 2b00 cmp r3, #0 8004b02: d10d bne.n 8004b20 { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8004b04: 4b05 ldr r3, [pc, #20] ; (8004b1c ) 8004b06: 6d5b ldr r3, [r3, #84] ; 0x54 8004b08: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8004b0c: 687b ldr r3, [r7, #4] 8004b0e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8004b12: 4902 ldr r1, [pc, #8] ; (8004b1c ) 8004b14: 4313 orrs r3, r2 8004b16: 654b str r3, [r1, #84] ; 0x54 8004b18: e004 b.n 8004b24 8004b1a: bf00 nop 8004b1c: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8004b20: 7dfb ldrb r3, [r7, #23] 8004b22: 75bb strb r3, [r7, #22] } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 8004b24: 687b ldr r3, [r7, #4] 8004b26: 681b ldr r3, [r3, #0] 8004b28: f403 3380 and.w r3, r3, #65536 ; 0x10000 8004b2c: 2b00 cmp r3, #0 8004b2e: d029 beq.n 8004b84 { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch(PeriphClkInit->SdmmcClockSelection) 8004b30: 687b ldr r3, [r7, #4] 8004b32: 6cdb ldr r3, [r3, #76] ; 0x4c 8004b34: 2b00 cmp r3, #0 8004b36: d003 beq.n 8004b40 8004b38: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8004b3c: d007 beq.n 8004b4e 8004b3e: e00f b.n 8004b60 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004b40: 4b61 ldr r3, [pc, #388] ; (8004cc8 ) 8004b42: 6adb ldr r3, [r3, #44] ; 0x2c 8004b44: 4a60 ldr r2, [pc, #384] ; (8004cc8 ) 8004b46: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004b4a: 62d3 str r3, [r2, #44] ; 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 8004b4c: e00b b.n 8004b66 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8004b4e: 687b ldr r3, [r7, #4] 8004b50: 3304 adds r3, #4 8004b52: 2102 movs r1, #2 8004b54: 4618 mov r0, r3 8004b56: f000 f8b9 bl 8004ccc 8004b5a: 4603 mov r3, r0 8004b5c: 75fb strb r3, [r7, #23] /* SDMMC clock source configuration done later after clock selection check */ break; 8004b5e: e002 b.n 8004b66 default: ret = HAL_ERROR; 8004b60: 2301 movs r3, #1 8004b62: 75fb strb r3, [r7, #23] break; 8004b64: bf00 nop } if(ret == HAL_OK) 8004b66: 7dfb ldrb r3, [r7, #23] 8004b68: 2b00 cmp r3, #0 8004b6a: d109 bne.n 8004b80 { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 8004b6c: 4b56 ldr r3, [pc, #344] ; (8004cc8 ) 8004b6e: 6cdb ldr r3, [r3, #76] ; 0x4c 8004b70: f423 3280 bic.w r2, r3, #65536 ; 0x10000 8004b74: 687b ldr r3, [r7, #4] 8004b76: 6cdb ldr r3, [r3, #76] ; 0x4c 8004b78: 4953 ldr r1, [pc, #332] ; (8004cc8 ) 8004b7a: 4313 orrs r3, r2 8004b7c: 64cb str r3, [r1, #76] ; 0x4c 8004b7e: e001 b.n 8004b84 } else { /* set overall return value */ status = ret; 8004b80: 7dfb ldrb r3, [r7, #23] 8004b82: 75bb strb r3, [r7, #22] } } #if defined(LTDC) /*-------------------------------------- LTDC Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 8004b84: 687b ldr r3, [r7, #4] 8004b86: 681b ldr r3, [r3, #0] 8004b88: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8004b8c: 2b00 cmp r3, #0 8004b8e: d00a beq.n 8004ba6 { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK) 8004b90: 687b ldr r3, [r7, #4] 8004b92: 3324 adds r3, #36 ; 0x24 8004b94: 2102 movs r1, #2 8004b96: 4618 mov r0, r3 8004b98: f000 f94a bl 8004e30 8004b9c: 4603 mov r3, r0 8004b9e: 2b00 cmp r3, #0 8004ba0: d001 beq.n 8004ba6 { status=HAL_ERROR; 8004ba2: 2301 movs r3, #1 8004ba4: 75bb strb r3, [r7, #22] } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 8004ba6: 687b ldr r3, [r7, #4] 8004ba8: 681b ldr r3, [r3, #0] 8004baa: f403 3300 and.w r3, r3, #131072 ; 0x20000 8004bae: 2b00 cmp r3, #0 8004bb0: d030 beq.n 8004c14 { switch(PeriphClkInit->RngClockSelection) 8004bb2: 687b ldr r3, [r7, #4] 8004bb4: 6f9b ldr r3, [r3, #120] ; 0x78 8004bb6: f5b3 7f40 cmp.w r3, #768 ; 0x300 8004bba: d017 beq.n 8004bec 8004bbc: f5b3 7f40 cmp.w r3, #768 ; 0x300 8004bc0: d811 bhi.n 8004be6 8004bc2: f5b3 7f00 cmp.w r3, #512 ; 0x200 8004bc6: d013 beq.n 8004bf0 8004bc8: f5b3 7f00 cmp.w r3, #512 ; 0x200 8004bcc: d80b bhi.n 8004be6 8004bce: 2b00 cmp r3, #0 8004bd0: d010 beq.n 8004bf4 8004bd2: f5b3 7f80 cmp.w r3, #256 ; 0x100 8004bd6: d106 bne.n 8004be6 { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004bd8: 4b3b ldr r3, [pc, #236] ; (8004cc8 ) 8004bda: 6adb ldr r3, [r3, #44] ; 0x2c 8004bdc: 4a3a ldr r2, [pc, #232] ; (8004cc8 ) 8004bde: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004be2: 62d3 str r3, [r2, #44] ; 0x2c /* RNG clock source configuration done later after clock selection check */ break; 8004be4: e007 b.n 8004bf6 /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004be6: 2301 movs r3, #1 8004be8: 75fb strb r3, [r7, #23] break; 8004bea: e004 b.n 8004bf6 break; 8004bec: bf00 nop 8004bee: e002 b.n 8004bf6 break; 8004bf0: bf00 nop 8004bf2: e000 b.n 8004bf6 break; 8004bf4: bf00 nop } if(ret == HAL_OK) 8004bf6: 7dfb ldrb r3, [r7, #23] 8004bf8: 2b00 cmp r3, #0 8004bfa: d109 bne.n 8004c10 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 8004bfc: 4b32 ldr r3, [pc, #200] ; (8004cc8 ) 8004bfe: 6d5b ldr r3, [r3, #84] ; 0x54 8004c00: f423 7240 bic.w r2, r3, #768 ; 0x300 8004c04: 687b ldr r3, [r7, #4] 8004c06: 6f9b ldr r3, [r3, #120] ; 0x78 8004c08: 492f ldr r1, [pc, #188] ; (8004cc8 ) 8004c0a: 4313 orrs r3, r2 8004c0c: 654b str r3, [r1, #84] ; 0x54 8004c0e: e001 b.n 8004c14 } else { /* set overall return value */ status = ret; 8004c10: 7dfb ldrb r3, [r7, #23] 8004c12: 75bb strb r3, [r7, #22] } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 8004c14: 687b ldr r3, [r7, #4] 8004c16: 681b ldr r3, [r3, #0] 8004c18: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8004c1c: 2b00 cmp r3, #0 8004c1e: d008 beq.n 8004c32 { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 8004c20: 4b29 ldr r3, [pc, #164] ; (8004cc8 ) 8004c22: 6d1b ldr r3, [r3, #80] ; 0x50 8004c24: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 8004c28: 687b ldr r3, [r7, #4] 8004c2a: 6edb ldr r3, [r3, #108] ; 0x6c 8004c2c: 4926 ldr r1, [pc, #152] ; (8004cc8 ) 8004c2e: 4313 orrs r3, r2 8004c30: 650b str r3, [r1, #80] ; 0x50 /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 8004c32: 687b ldr r3, [r7, #4] 8004c34: 681b ldr r3, [r3, #0] 8004c36: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8004c3a: 2b00 cmp r3, #0 8004c3c: d008 beq.n 8004c50 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 8004c3e: 4b22 ldr r3, [pc, #136] ; (8004cc8 ) 8004c40: 6d1b ldr r3, [r3, #80] ; 0x50 8004c42: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000 8004c46: 687b ldr r3, [r7, #4] 8004c48: 6e5b ldr r3, [r3, #100] ; 0x64 8004c4a: 491f ldr r1, [pc, #124] ; (8004cc8 ) 8004c4c: 4313 orrs r3, r2 8004c4e: 650b str r3, [r1, #80] ; 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 8004c50: 687b ldr r3, [r7, #4] 8004c52: 681b ldr r3, [r3, #0] 8004c54: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 8004c58: 2b00 cmp r3, #0 8004c5a: d00d beq.n 8004c78 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8004c5c: 4b1a ldr r3, [pc, #104] ; (8004cc8 ) 8004c5e: 691b ldr r3, [r3, #16] 8004c60: 4a19 ldr r2, [pc, #100] ; (8004cc8 ) 8004c62: f423 4300 bic.w r3, r3, #32768 ; 0x8000 8004c66: 6113 str r3, [r2, #16] 8004c68: 4b17 ldr r3, [pc, #92] ; (8004cc8 ) 8004c6a: 691a ldr r2, [r3, #16] 8004c6c: 687b ldr r3, [r7, #4] 8004c6e: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8004c72: 4915 ldr r1, [pc, #84] ; (8004cc8 ) 8004c74: 4313 orrs r3, r2 8004c76: 610b str r3, [r1, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 8004c78: 687b ldr r3, [r7, #4] 8004c7a: 681b ldr r3, [r3, #0] 8004c7c: 2b00 cmp r3, #0 8004c7e: da08 bge.n 8004c92 { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 8004c80: 4b11 ldr r3, [pc, #68] ; (8004cc8 ) 8004c82: 6cdb ldr r3, [r3, #76] ; 0x4c 8004c84: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 8004c88: 687b ldr r3, [r7, #4] 8004c8a: 6d1b ldr r3, [r3, #80] ; 0x50 8004c8c: 490e ldr r1, [pc, #56] ; (8004cc8 ) 8004c8e: 4313 orrs r3, r2 8004c90: 64cb str r3, [r1, #76] ; 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 8004c92: 687b ldr r3, [r7, #4] 8004c94: 681b ldr r3, [r3, #0] 8004c96: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8004c9a: 2b00 cmp r3, #0 8004c9c: d009 beq.n 8004cb2 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 8004c9e: 4b0a ldr r3, [pc, #40] ; (8004cc8 ) 8004ca0: 6d5b ldr r3, [r3, #84] ; 0x54 8004ca2: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 8004ca6: 687b ldr r3, [r7, #4] 8004ca8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8004cac: 4906 ldr r1, [pc, #24] ; (8004cc8 ) 8004cae: 4313 orrs r3, r2 8004cb0: 654b str r3, [r1, #84] ; 0x54 } if (status == HAL_OK) 8004cb2: 7dbb ldrb r3, [r7, #22] 8004cb4: 2b00 cmp r3, #0 8004cb6: d101 bne.n 8004cbc { return HAL_OK; 8004cb8: 2300 movs r3, #0 8004cba: e000 b.n 8004cbe } return HAL_ERROR; 8004cbc: 2301 movs r3, #1 } 8004cbe: 4618 mov r0, r3 8004cc0: 3718 adds r7, #24 8004cc2: 46bd mov sp, r7 8004cc4: bd80 pop {r7, pc} 8004cc6: bf00 nop 8004cc8: 58024400 .word 0x58024400 08004ccc : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 8004ccc: b580 push {r7, lr} 8004cce: b084 sub sp, #16 8004cd0: af00 add r7, sp, #0 8004cd2: 6078 str r0, [r7, #4] 8004cd4: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 8004cd6: 2300 movs r3, #0 8004cd8: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8004cda: 4b53 ldr r3, [pc, #332] ; (8004e28 ) 8004cdc: 6a9b ldr r3, [r3, #40] ; 0x28 8004cde: f003 0303 and.w r3, r3, #3 8004ce2: 2b03 cmp r3, #3 8004ce4: d101 bne.n 8004cea { return HAL_ERROR; 8004ce6: 2301 movs r3, #1 8004ce8: e099 b.n 8004e1e else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8004cea: 4b4f ldr r3, [pc, #316] ; (8004e28 ) 8004cec: 681b ldr r3, [r3, #0] 8004cee: 4a4e ldr r2, [pc, #312] ; (8004e28 ) 8004cf0: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 8004cf4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004cf6: f7fc fcaf bl 8001658 8004cfa: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 8004cfc: e008 b.n 8004d10 { if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 8004cfe: f7fc fcab bl 8001658 8004d02: 4602 mov r2, r0 8004d04: 68bb ldr r3, [r7, #8] 8004d06: 1ad3 subs r3, r2, r3 8004d08: 2b02 cmp r3, #2 8004d0a: d901 bls.n 8004d10 { return HAL_TIMEOUT; 8004d0c: 2303 movs r3, #3 8004d0e: e086 b.n 8004e1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 8004d10: 4b45 ldr r3, [pc, #276] ; (8004e28 ) 8004d12: 681b ldr r3, [r3, #0] 8004d14: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8004d18: 2b00 cmp r3, #0 8004d1a: d1f0 bne.n 8004cfe } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 8004d1c: 4b42 ldr r3, [pc, #264] ; (8004e28 ) 8004d1e: 6a9b ldr r3, [r3, #40] ; 0x28 8004d20: f423 327c bic.w r2, r3, #258048 ; 0x3f000 8004d24: 687b ldr r3, [r7, #4] 8004d26: 681b ldr r3, [r3, #0] 8004d28: 031b lsls r3, r3, #12 8004d2a: 493f ldr r1, [pc, #252] ; (8004e28 ) 8004d2c: 4313 orrs r3, r2 8004d2e: 628b str r3, [r1, #40] ; 0x28 8004d30: 687b ldr r3, [r7, #4] 8004d32: 685b ldr r3, [r3, #4] 8004d34: 3b01 subs r3, #1 8004d36: f3c3 0208 ubfx r2, r3, #0, #9 8004d3a: 687b ldr r3, [r7, #4] 8004d3c: 689b ldr r3, [r3, #8] 8004d3e: 3b01 subs r3, #1 8004d40: 025b lsls r3, r3, #9 8004d42: b29b uxth r3, r3 8004d44: 431a orrs r2, r3 8004d46: 687b ldr r3, [r7, #4] 8004d48: 68db ldr r3, [r3, #12] 8004d4a: 3b01 subs r3, #1 8004d4c: 041b lsls r3, r3, #16 8004d4e: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8004d52: 431a orrs r2, r3 8004d54: 687b ldr r3, [r7, #4] 8004d56: 691b ldr r3, [r3, #16] 8004d58: 3b01 subs r3, #1 8004d5a: 061b lsls r3, r3, #24 8004d5c: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 8004d60: 4931 ldr r1, [pc, #196] ; (8004e28 ) 8004d62: 4313 orrs r3, r2 8004d64: 638b str r3, [r1, #56] ; 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 8004d66: 4b30 ldr r3, [pc, #192] ; (8004e28 ) 8004d68: 6adb ldr r3, [r3, #44] ; 0x2c 8004d6a: f023 02c0 bic.w r2, r3, #192 ; 0xc0 8004d6e: 687b ldr r3, [r7, #4] 8004d70: 695b ldr r3, [r3, #20] 8004d72: 492d ldr r1, [pc, #180] ; (8004e28 ) 8004d74: 4313 orrs r3, r2 8004d76: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 8004d78: 4b2b ldr r3, [pc, #172] ; (8004e28 ) 8004d7a: 6adb ldr r3, [r3, #44] ; 0x2c 8004d7c: f023 0220 bic.w r2, r3, #32 8004d80: 687b ldr r3, [r7, #4] 8004d82: 699b ldr r3, [r3, #24] 8004d84: 4928 ldr r1, [pc, #160] ; (8004e28 ) 8004d86: 4313 orrs r3, r2 8004d88: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 8004d8a: 4b27 ldr r3, [pc, #156] ; (8004e28 ) 8004d8c: 6adb ldr r3, [r3, #44] ; 0x2c 8004d8e: 4a26 ldr r2, [pc, #152] ; (8004e28 ) 8004d90: f023 0310 bic.w r3, r3, #16 8004d94: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 8004d96: 4b24 ldr r3, [pc, #144] ; (8004e28 ) 8004d98: 6bda ldr r2, [r3, #60] ; 0x3c 8004d9a: 4b24 ldr r3, [pc, #144] ; (8004e2c ) 8004d9c: 4013 ands r3, r2 8004d9e: 687a ldr r2, [r7, #4] 8004da0: 69d2 ldr r2, [r2, #28] 8004da2: 00d2 lsls r2, r2, #3 8004da4: 4920 ldr r1, [pc, #128] ; (8004e28 ) 8004da6: 4313 orrs r3, r2 8004da8: 63cb str r3, [r1, #60] ; 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 8004daa: 4b1f ldr r3, [pc, #124] ; (8004e28 ) 8004dac: 6adb ldr r3, [r3, #44] ; 0x2c 8004dae: 4a1e ldr r2, [pc, #120] ; (8004e28 ) 8004db0: f043 0310 orr.w r3, r3, #16 8004db4: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL2 clock output */ if(Divider == DIVIDER_P_UPDATE) 8004db6: 683b ldr r3, [r7, #0] 8004db8: 2b00 cmp r3, #0 8004dba: d106 bne.n 8004dca { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 8004dbc: 4b1a ldr r3, [pc, #104] ; (8004e28 ) 8004dbe: 6adb ldr r3, [r3, #44] ; 0x2c 8004dc0: 4a19 ldr r2, [pc, #100] ; (8004e28 ) 8004dc2: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8004dc6: 62d3 str r3, [r2, #44] ; 0x2c 8004dc8: e00f b.n 8004dea } else if(Divider == DIVIDER_Q_UPDATE) 8004dca: 683b ldr r3, [r7, #0] 8004dcc: 2b01 cmp r3, #1 8004dce: d106 bne.n 8004dde { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 8004dd0: 4b15 ldr r3, [pc, #84] ; (8004e28 ) 8004dd2: 6adb ldr r3, [r3, #44] ; 0x2c 8004dd4: 4a14 ldr r2, [pc, #80] ; (8004e28 ) 8004dd6: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8004dda: 62d3 str r3, [r2, #44] ; 0x2c 8004ddc: e005 b.n 8004dea } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 8004dde: 4b12 ldr r3, [pc, #72] ; (8004e28 ) 8004de0: 6adb ldr r3, [r3, #44] ; 0x2c 8004de2: 4a11 ldr r2, [pc, #68] ; (8004e28 ) 8004de4: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8004de8: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 8004dea: 4b0f ldr r3, [pc, #60] ; (8004e28 ) 8004dec: 681b ldr r3, [r3, #0] 8004dee: 4a0e ldr r2, [pc, #56] ; (8004e28 ) 8004df0: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8004df4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004df6: f7fc fc2f bl 8001658 8004dfa: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 8004dfc: e008 b.n 8004e10 { if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 8004dfe: f7fc fc2b bl 8001658 8004e02: 4602 mov r2, r0 8004e04: 68bb ldr r3, [r7, #8] 8004e06: 1ad3 subs r3, r2, r3 8004e08: 2b02 cmp r3, #2 8004e0a: d901 bls.n 8004e10 { return HAL_TIMEOUT; 8004e0c: 2303 movs r3, #3 8004e0e: e006 b.n 8004e1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 8004e10: 4b05 ldr r3, [pc, #20] ; (8004e28 ) 8004e12: 681b ldr r3, [r3, #0] 8004e14: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8004e18: 2b00 cmp r3, #0 8004e1a: d0f0 beq.n 8004dfe } } return status; 8004e1c: 7bfb ldrb r3, [r7, #15] } 8004e1e: 4618 mov r0, r3 8004e20: 3710 adds r7, #16 8004e22: 46bd mov sp, r7 8004e24: bd80 pop {r7, pc} 8004e26: bf00 nop 8004e28: 58024400 .word 0x58024400 8004e2c: ffff0007 .word 0xffff0007 08004e30 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 8004e30: b580 push {r7, lr} 8004e32: b084 sub sp, #16 8004e34: af00 add r7, sp, #0 8004e36: 6078 str r0, [r7, #4] 8004e38: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 8004e3a: 2300 movs r3, #0 8004e3c: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8004e3e: 4b53 ldr r3, [pc, #332] ; (8004f8c ) 8004e40: 6a9b ldr r3, [r3, #40] ; 0x28 8004e42: f003 0303 and.w r3, r3, #3 8004e46: 2b03 cmp r3, #3 8004e48: d101 bne.n 8004e4e { return HAL_ERROR; 8004e4a: 2301 movs r3, #1 8004e4c: e099 b.n 8004f82 else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 8004e4e: 4b4f ldr r3, [pc, #316] ; (8004f8c ) 8004e50: 681b ldr r3, [r3, #0] 8004e52: 4a4e ldr r2, [pc, #312] ; (8004f8c ) 8004e54: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8004e58: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004e5a: f7fc fbfd bl 8001658 8004e5e: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 8004e60: e008 b.n 8004e74 { if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 8004e62: f7fc fbf9 bl 8001658 8004e66: 4602 mov r2, r0 8004e68: 68bb ldr r3, [r7, #8] 8004e6a: 1ad3 subs r3, r2, r3 8004e6c: 2b02 cmp r3, #2 8004e6e: d901 bls.n 8004e74 { return HAL_TIMEOUT; 8004e70: 2303 movs r3, #3 8004e72: e086 b.n 8004f82 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 8004e74: 4b45 ldr r3, [pc, #276] ; (8004f8c ) 8004e76: 681b ldr r3, [r3, #0] 8004e78: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8004e7c: 2b00 cmp r3, #0 8004e7e: d1f0 bne.n 8004e62 } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 8004e80: 4b42 ldr r3, [pc, #264] ; (8004f8c ) 8004e82: 6a9b ldr r3, [r3, #40] ; 0x28 8004e84: f023 727c bic.w r2, r3, #66060288 ; 0x3f00000 8004e88: 687b ldr r3, [r7, #4] 8004e8a: 681b ldr r3, [r3, #0] 8004e8c: 051b lsls r3, r3, #20 8004e8e: 493f ldr r1, [pc, #252] ; (8004f8c ) 8004e90: 4313 orrs r3, r2 8004e92: 628b str r3, [r1, #40] ; 0x28 8004e94: 687b ldr r3, [r7, #4] 8004e96: 685b ldr r3, [r3, #4] 8004e98: 3b01 subs r3, #1 8004e9a: f3c3 0208 ubfx r2, r3, #0, #9 8004e9e: 687b ldr r3, [r7, #4] 8004ea0: 689b ldr r3, [r3, #8] 8004ea2: 3b01 subs r3, #1 8004ea4: 025b lsls r3, r3, #9 8004ea6: b29b uxth r3, r3 8004ea8: 431a orrs r2, r3 8004eaa: 687b ldr r3, [r7, #4] 8004eac: 68db ldr r3, [r3, #12] 8004eae: 3b01 subs r3, #1 8004eb0: 041b lsls r3, r3, #16 8004eb2: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8004eb6: 431a orrs r2, r3 8004eb8: 687b ldr r3, [r7, #4] 8004eba: 691b ldr r3, [r3, #16] 8004ebc: 3b01 subs r3, #1 8004ebe: 061b lsls r3, r3, #24 8004ec0: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 8004ec4: 4931 ldr r1, [pc, #196] ; (8004f8c ) 8004ec6: 4313 orrs r3, r2 8004ec8: 640b str r3, [r1, #64] ; 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 8004eca: 4b30 ldr r3, [pc, #192] ; (8004f8c ) 8004ecc: 6adb ldr r3, [r3, #44] ; 0x2c 8004ece: f423 6240 bic.w r2, r3, #3072 ; 0xc00 8004ed2: 687b ldr r3, [r7, #4] 8004ed4: 695b ldr r3, [r3, #20] 8004ed6: 492d ldr r1, [pc, #180] ; (8004f8c ) 8004ed8: 4313 orrs r3, r2 8004eda: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 8004edc: 4b2b ldr r3, [pc, #172] ; (8004f8c ) 8004ede: 6adb ldr r3, [r3, #44] ; 0x2c 8004ee0: f423 7200 bic.w r2, r3, #512 ; 0x200 8004ee4: 687b ldr r3, [r7, #4] 8004ee6: 699b ldr r3, [r3, #24] 8004ee8: 4928 ldr r1, [pc, #160] ; (8004f8c ) 8004eea: 4313 orrs r3, r2 8004eec: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 8004eee: 4b27 ldr r3, [pc, #156] ; (8004f8c ) 8004ef0: 6adb ldr r3, [r3, #44] ; 0x2c 8004ef2: 4a26 ldr r2, [pc, #152] ; (8004f8c ) 8004ef4: f423 7380 bic.w r3, r3, #256 ; 0x100 8004ef8: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 8004efa: 4b24 ldr r3, [pc, #144] ; (8004f8c ) 8004efc: 6c5a ldr r2, [r3, #68] ; 0x44 8004efe: 4b24 ldr r3, [pc, #144] ; (8004f90 ) 8004f00: 4013 ands r3, r2 8004f02: 687a ldr r2, [r7, #4] 8004f04: 69d2 ldr r2, [r2, #28] 8004f06: 00d2 lsls r2, r2, #3 8004f08: 4920 ldr r1, [pc, #128] ; (8004f8c ) 8004f0a: 4313 orrs r3, r2 8004f0c: 644b str r3, [r1, #68] ; 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 8004f0e: 4b1f ldr r3, [pc, #124] ; (8004f8c ) 8004f10: 6adb ldr r3, [r3, #44] ; 0x2c 8004f12: 4a1e ldr r2, [pc, #120] ; (8004f8c ) 8004f14: f443 7380 orr.w r3, r3, #256 ; 0x100 8004f18: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL3 clock output */ if(Divider == DIVIDER_P_UPDATE) 8004f1a: 683b ldr r3, [r7, #0] 8004f1c: 2b00 cmp r3, #0 8004f1e: d106 bne.n 8004f2e { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 8004f20: 4b1a ldr r3, [pc, #104] ; (8004f8c ) 8004f22: 6adb ldr r3, [r3, #44] ; 0x2c 8004f24: 4a19 ldr r2, [pc, #100] ; (8004f8c ) 8004f26: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 8004f2a: 62d3 str r3, [r2, #44] ; 0x2c 8004f2c: e00f b.n 8004f4e } else if(Divider == DIVIDER_Q_UPDATE) 8004f2e: 683b ldr r3, [r7, #0] 8004f30: 2b01 cmp r3, #1 8004f32: d106 bne.n 8004f42 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 8004f34: 4b15 ldr r3, [pc, #84] ; (8004f8c ) 8004f36: 6adb ldr r3, [r3, #44] ; 0x2c 8004f38: 4a14 ldr r2, [pc, #80] ; (8004f8c ) 8004f3a: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 8004f3e: 62d3 str r3, [r2, #44] ; 0x2c 8004f40: e005 b.n 8004f4e } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 8004f42: 4b12 ldr r3, [pc, #72] ; (8004f8c ) 8004f44: 6adb ldr r3, [r3, #44] ; 0x2c 8004f46: 4a11 ldr r2, [pc, #68] ; (8004f8c ) 8004f48: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8004f4c: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 8004f4e: 4b0f ldr r3, [pc, #60] ; (8004f8c ) 8004f50: 681b ldr r3, [r3, #0] 8004f52: 4a0e ldr r2, [pc, #56] ; (8004f8c ) 8004f54: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8004f58: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004f5a: f7fc fb7d bl 8001658 8004f5e: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 8004f60: e008 b.n 8004f74 { if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 8004f62: f7fc fb79 bl 8001658 8004f66: 4602 mov r2, r0 8004f68: 68bb ldr r3, [r7, #8] 8004f6a: 1ad3 subs r3, r2, r3 8004f6c: 2b02 cmp r3, #2 8004f6e: d901 bls.n 8004f74 { return HAL_TIMEOUT; 8004f70: 2303 movs r3, #3 8004f72: e006 b.n 8004f82 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 8004f74: 4b05 ldr r3, [pc, #20] ; (8004f8c ) 8004f76: 681b ldr r3, [r3, #0] 8004f78: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8004f7c: 2b00 cmp r3, #0 8004f7e: d0f0 beq.n 8004f62 } } return status; 8004f80: 7bfb ldrb r3, [r7, #15] } 8004f82: 4618 mov r0, r3 8004f84: 3710 adds r7, #16 8004f86: 46bd mov sp, r7 8004f88: bd80 pop {r7, pc} 8004f8a: bf00 nop 8004f8c: 58024400 .word 0x58024400 8004f90: ffff0007 .word 0xffff0007 08004f94 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8004f94: b580 push {r7, lr} 8004f96: b082 sub sp, #8 8004f98: af00 add r7, sp, #0 8004f9a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8004f9c: 687b ldr r3, [r7, #4] 8004f9e: 2b00 cmp r3, #0 8004fa0: d101 bne.n 8004fa6 { return HAL_ERROR; 8004fa2: 2301 movs r3, #1 8004fa4: e049 b.n 800503a assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8004fa6: 687b ldr r3, [r7, #4] 8004fa8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8004fac: b2db uxtb r3, r3 8004fae: 2b00 cmp r3, #0 8004fb0: d106 bne.n 8004fc0 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8004fb2: 687b ldr r3, [r7, #4] 8004fb4: 2200 movs r2, #0 8004fb6: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8004fba: 6878 ldr r0, [r7, #4] 8004fbc: f7fc f8f8 bl 80011b0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8004fc0: 687b ldr r3, [r7, #4] 8004fc2: 2202 movs r2, #2 8004fc4: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8004fc8: 687b ldr r3, [r7, #4] 8004fca: 681a ldr r2, [r3, #0] 8004fcc: 687b ldr r3, [r7, #4] 8004fce: 3304 adds r3, #4 8004fd0: 4619 mov r1, r3 8004fd2: 4610 mov r0, r2 8004fd4: f000 fafc bl 80055d0 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8004fd8: 687b ldr r3, [r7, #4] 8004fda: 2201 movs r2, #1 8004fdc: f883 2048 strb.w r2, [r3, #72] ; 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004fe0: 687b ldr r3, [r7, #4] 8004fe2: 2201 movs r2, #1 8004fe4: f883 203e strb.w r2, [r3, #62] ; 0x3e 8004fe8: 687b ldr r3, [r7, #4] 8004fea: 2201 movs r2, #1 8004fec: f883 203f strb.w r2, [r3, #63] ; 0x3f 8004ff0: 687b ldr r3, [r7, #4] 8004ff2: 2201 movs r2, #1 8004ff4: f883 2040 strb.w r2, [r3, #64] ; 0x40 8004ff8: 687b ldr r3, [r7, #4] 8004ffa: 2201 movs r2, #1 8004ffc: f883 2041 strb.w r2, [r3, #65] ; 0x41 8005000: 687b ldr r3, [r7, #4] 8005002: 2201 movs r2, #1 8005004: f883 2042 strb.w r2, [r3, #66] ; 0x42 8005008: 687b ldr r3, [r7, #4] 800500a: 2201 movs r2, #1 800500c: f883 2043 strb.w r2, [r3, #67] ; 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005010: 687b ldr r3, [r7, #4] 8005012: 2201 movs r2, #1 8005014: f883 2044 strb.w r2, [r3, #68] ; 0x44 8005018: 687b ldr r3, [r7, #4] 800501a: 2201 movs r2, #1 800501c: f883 2045 strb.w r2, [r3, #69] ; 0x45 8005020: 687b ldr r3, [r7, #4] 8005022: 2201 movs r2, #1 8005024: f883 2046 strb.w r2, [r3, #70] ; 0x46 8005028: 687b ldr r3, [r7, #4] 800502a: 2201 movs r2, #1 800502c: f883 2047 strb.w r2, [r3, #71] ; 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005030: 687b ldr r3, [r7, #4] 8005032: 2201 movs r2, #1 8005034: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8005038: 2300 movs r3, #0 } 800503a: 4618 mov r0, r3 800503c: 3708 adds r7, #8 800503e: 46bd mov sp, r7 8005040: bd80 pop {r7, pc} ... 08005044 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8005044: b480 push {r7} 8005046: b085 sub sp, #20 8005048: af00 add r7, sp, #0 800504a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800504c: 687b ldr r3, [r7, #4] 800504e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8005052: b2db uxtb r3, r3 8005054: 2b01 cmp r3, #1 8005056: d001 beq.n 800505c { return HAL_ERROR; 8005058: 2301 movs r3, #1 800505a: e05e b.n 800511a } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800505c: 687b ldr r3, [r7, #4] 800505e: 2202 movs r2, #2 8005060: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8005064: 687b ldr r3, [r7, #4] 8005066: 681b ldr r3, [r3, #0] 8005068: 68da ldr r2, [r3, #12] 800506a: 687b ldr r3, [r7, #4] 800506c: 681b ldr r3, [r3, #0] 800506e: f042 0201 orr.w r2, r2, #1 8005072: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005074: 687b ldr r3, [r7, #4] 8005076: 681b ldr r3, [r3, #0] 8005078: 4a2b ldr r2, [pc, #172] ; (8005128 ) 800507a: 4293 cmp r3, r2 800507c: d02c beq.n 80050d8 800507e: 687b ldr r3, [r7, #4] 8005080: 681b ldr r3, [r3, #0] 8005082: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8005086: d027 beq.n 80050d8 8005088: 687b ldr r3, [r7, #4] 800508a: 681b ldr r3, [r3, #0] 800508c: 4a27 ldr r2, [pc, #156] ; (800512c ) 800508e: 4293 cmp r3, r2 8005090: d022 beq.n 80050d8 8005092: 687b ldr r3, [r7, #4] 8005094: 681b ldr r3, [r3, #0] 8005096: 4a26 ldr r2, [pc, #152] ; (8005130 ) 8005098: 4293 cmp r3, r2 800509a: d01d beq.n 80050d8 800509c: 687b ldr r3, [r7, #4] 800509e: 681b ldr r3, [r3, #0] 80050a0: 4a24 ldr r2, [pc, #144] ; (8005134 ) 80050a2: 4293 cmp r3, r2 80050a4: d018 beq.n 80050d8 80050a6: 687b ldr r3, [r7, #4] 80050a8: 681b ldr r3, [r3, #0] 80050aa: 4a23 ldr r2, [pc, #140] ; (8005138 ) 80050ac: 4293 cmp r3, r2 80050ae: d013 beq.n 80050d8 80050b0: 687b ldr r3, [r7, #4] 80050b2: 681b ldr r3, [r3, #0] 80050b4: 4a21 ldr r2, [pc, #132] ; (800513c ) 80050b6: 4293 cmp r3, r2 80050b8: d00e beq.n 80050d8 80050ba: 687b ldr r3, [r7, #4] 80050bc: 681b ldr r3, [r3, #0] 80050be: 4a20 ldr r2, [pc, #128] ; (8005140 ) 80050c0: 4293 cmp r3, r2 80050c2: d009 beq.n 80050d8 80050c4: 687b ldr r3, [r7, #4] 80050c6: 681b ldr r3, [r3, #0] 80050c8: 4a1e ldr r2, [pc, #120] ; (8005144 ) 80050ca: 4293 cmp r3, r2 80050cc: d004 beq.n 80050d8 80050ce: 687b ldr r3, [r7, #4] 80050d0: 681b ldr r3, [r3, #0] 80050d2: 4a1d ldr r2, [pc, #116] ; (8005148 ) 80050d4: 4293 cmp r3, r2 80050d6: d115 bne.n 8005104 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80050d8: 687b ldr r3, [r7, #4] 80050da: 681b ldr r3, [r3, #0] 80050dc: 689a ldr r2, [r3, #8] 80050de: 4b1b ldr r3, [pc, #108] ; (800514c ) 80050e0: 4013 ands r3, r2 80050e2: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80050e4: 68fb ldr r3, [r7, #12] 80050e6: 2b06 cmp r3, #6 80050e8: d015 beq.n 8005116 80050ea: 68fb ldr r3, [r7, #12] 80050ec: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80050f0: d011 beq.n 8005116 { __HAL_TIM_ENABLE(htim); 80050f2: 687b ldr r3, [r7, #4] 80050f4: 681b ldr r3, [r3, #0] 80050f6: 681a ldr r2, [r3, #0] 80050f8: 687b ldr r3, [r7, #4] 80050fa: 681b ldr r3, [r3, #0] 80050fc: f042 0201 orr.w r2, r2, #1 8005100: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005102: e008 b.n 8005116 } } else { __HAL_TIM_ENABLE(htim); 8005104: 687b ldr r3, [r7, #4] 8005106: 681b ldr r3, [r3, #0] 8005108: 681a ldr r2, [r3, #0] 800510a: 687b ldr r3, [r7, #4] 800510c: 681b ldr r3, [r3, #0] 800510e: f042 0201 orr.w r2, r2, #1 8005112: 601a str r2, [r3, #0] 8005114: e000 b.n 8005118 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005116: bf00 nop } /* Return function status */ return HAL_OK; 8005118: 2300 movs r3, #0 } 800511a: 4618 mov r0, r3 800511c: 3714 adds r7, #20 800511e: 46bd mov sp, r7 8005120: f85d 7b04 ldr.w r7, [sp], #4 8005124: 4770 bx lr 8005126: bf00 nop 8005128: 40010000 .word 0x40010000 800512c: 40000400 .word 0x40000400 8005130: 40000800 .word 0x40000800 8005134: 40000c00 .word 0x40000c00 8005138: 40010400 .word 0x40010400 800513c: 40001800 .word 0x40001800 8005140: 40014000 .word 0x40014000 8005144: 4000e000 .word 0x4000e000 8005148: 4000e400 .word 0x4000e400 800514c: 00010007 .word 0x00010007 08005150 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8005150: b580 push {r7, lr} 8005152: b082 sub sp, #8 8005154: af00 add r7, sp, #0 8005156: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 8005158: 687b ldr r3, [r7, #4] 800515a: 681b ldr r3, [r3, #0] 800515c: 691b ldr r3, [r3, #16] 800515e: f003 0302 and.w r3, r3, #2 8005162: 2b02 cmp r3, #2 8005164: d122 bne.n 80051ac { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 8005166: 687b ldr r3, [r7, #4] 8005168: 681b ldr r3, [r3, #0] 800516a: 68db ldr r3, [r3, #12] 800516c: f003 0302 and.w r3, r3, #2 8005170: 2b02 cmp r3, #2 8005172: d11b bne.n 80051ac { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 8005174: 687b ldr r3, [r7, #4] 8005176: 681b ldr r3, [r3, #0] 8005178: f06f 0202 mvn.w r2, #2 800517c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800517e: 687b ldr r3, [r7, #4] 8005180: 2201 movs r2, #1 8005182: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8005184: 687b ldr r3, [r7, #4] 8005186: 681b ldr r3, [r3, #0] 8005188: 699b ldr r3, [r3, #24] 800518a: f003 0303 and.w r3, r3, #3 800518e: 2b00 cmp r3, #0 8005190: d003 beq.n 800519a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8005192: 6878 ldr r0, [r7, #4] 8005194: f000 f9fe bl 8005594 8005198: e005 b.n 80051a6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800519a: 6878 ldr r0, [r7, #4] 800519c: f000 f9f0 bl 8005580 HAL_TIM_PWM_PulseFinishedCallback(htim); 80051a0: 6878 ldr r0, [r7, #4] 80051a2: f000 fa01 bl 80055a8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80051a6: 687b ldr r3, [r7, #4] 80051a8: 2200 movs r2, #0 80051aa: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 80051ac: 687b ldr r3, [r7, #4] 80051ae: 681b ldr r3, [r3, #0] 80051b0: 691b ldr r3, [r3, #16] 80051b2: f003 0304 and.w r3, r3, #4 80051b6: 2b04 cmp r3, #4 80051b8: d122 bne.n 8005200 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 80051ba: 687b ldr r3, [r7, #4] 80051bc: 681b ldr r3, [r3, #0] 80051be: 68db ldr r3, [r3, #12] 80051c0: f003 0304 and.w r3, r3, #4 80051c4: 2b04 cmp r3, #4 80051c6: d11b bne.n 8005200 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 80051c8: 687b ldr r3, [r7, #4] 80051ca: 681b ldr r3, [r3, #0] 80051cc: f06f 0204 mvn.w r2, #4 80051d0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80051d2: 687b ldr r3, [r7, #4] 80051d4: 2202 movs r2, #2 80051d6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80051d8: 687b ldr r3, [r7, #4] 80051da: 681b ldr r3, [r3, #0] 80051dc: 699b ldr r3, [r3, #24] 80051de: f403 7340 and.w r3, r3, #768 ; 0x300 80051e2: 2b00 cmp r3, #0 80051e4: d003 beq.n 80051ee { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80051e6: 6878 ldr r0, [r7, #4] 80051e8: f000 f9d4 bl 8005594 80051ec: e005 b.n 80051fa { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80051ee: 6878 ldr r0, [r7, #4] 80051f0: f000 f9c6 bl 8005580 HAL_TIM_PWM_PulseFinishedCallback(htim); 80051f4: 6878 ldr r0, [r7, #4] 80051f6: f000 f9d7 bl 80055a8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80051fa: 687b ldr r3, [r7, #4] 80051fc: 2200 movs r2, #0 80051fe: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 8005200: 687b ldr r3, [r7, #4] 8005202: 681b ldr r3, [r3, #0] 8005204: 691b ldr r3, [r3, #16] 8005206: f003 0308 and.w r3, r3, #8 800520a: 2b08 cmp r3, #8 800520c: d122 bne.n 8005254 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 800520e: 687b ldr r3, [r7, #4] 8005210: 681b ldr r3, [r3, #0] 8005212: 68db ldr r3, [r3, #12] 8005214: f003 0308 and.w r3, r3, #8 8005218: 2b08 cmp r3, #8 800521a: d11b bne.n 8005254 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 800521c: 687b ldr r3, [r7, #4] 800521e: 681b ldr r3, [r3, #0] 8005220: f06f 0208 mvn.w r2, #8 8005224: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8005226: 687b ldr r3, [r7, #4] 8005228: 2204 movs r2, #4 800522a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800522c: 687b ldr r3, [r7, #4] 800522e: 681b ldr r3, [r3, #0] 8005230: 69db ldr r3, [r3, #28] 8005232: f003 0303 and.w r3, r3, #3 8005236: 2b00 cmp r3, #0 8005238: d003 beq.n 8005242 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800523a: 6878 ldr r0, [r7, #4] 800523c: f000 f9aa bl 8005594 8005240: e005 b.n 800524e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005242: 6878 ldr r0, [r7, #4] 8005244: f000 f99c bl 8005580 HAL_TIM_PWM_PulseFinishedCallback(htim); 8005248: 6878 ldr r0, [r7, #4] 800524a: f000 f9ad bl 80055a8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800524e: 687b ldr r3, [r7, #4] 8005250: 2200 movs r2, #0 8005252: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 8005254: 687b ldr r3, [r7, #4] 8005256: 681b ldr r3, [r3, #0] 8005258: 691b ldr r3, [r3, #16] 800525a: f003 0310 and.w r3, r3, #16 800525e: 2b10 cmp r3, #16 8005260: d122 bne.n 80052a8 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 8005262: 687b ldr r3, [r7, #4] 8005264: 681b ldr r3, [r3, #0] 8005266: 68db ldr r3, [r3, #12] 8005268: f003 0310 and.w r3, r3, #16 800526c: 2b10 cmp r3, #16 800526e: d11b bne.n 80052a8 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 8005270: 687b ldr r3, [r7, #4] 8005272: 681b ldr r3, [r3, #0] 8005274: f06f 0210 mvn.w r2, #16 8005278: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800527a: 687b ldr r3, [r7, #4] 800527c: 2208 movs r2, #8 800527e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8005280: 687b ldr r3, [r7, #4] 8005282: 681b ldr r3, [r3, #0] 8005284: 69db ldr r3, [r3, #28] 8005286: f403 7340 and.w r3, r3, #768 ; 0x300 800528a: 2b00 cmp r3, #0 800528c: d003 beq.n 8005296 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800528e: 6878 ldr r0, [r7, #4] 8005290: f000 f980 bl 8005594 8005294: e005 b.n 80052a2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005296: 6878 ldr r0, [r7, #4] 8005298: f000 f972 bl 8005580 HAL_TIM_PWM_PulseFinishedCallback(htim); 800529c: 6878 ldr r0, [r7, #4] 800529e: f000 f983 bl 80055a8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80052a2: 687b ldr r3, [r7, #4] 80052a4: 2200 movs r2, #0 80052a6: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 80052a8: 687b ldr r3, [r7, #4] 80052aa: 681b ldr r3, [r3, #0] 80052ac: 691b ldr r3, [r3, #16] 80052ae: f003 0301 and.w r3, r3, #1 80052b2: 2b01 cmp r3, #1 80052b4: d10e bne.n 80052d4 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 80052b6: 687b ldr r3, [r7, #4] 80052b8: 681b ldr r3, [r3, #0] 80052ba: 68db ldr r3, [r3, #12] 80052bc: f003 0301 and.w r3, r3, #1 80052c0: 2b01 cmp r3, #1 80052c2: d107 bne.n 80052d4 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 80052c4: 687b ldr r3, [r7, #4] 80052c6: 681b ldr r3, [r3, #0] 80052c8: f06f 0201 mvn.w r2, #1 80052cc: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 80052ce: 6878 ldr r0, [r7, #4] 80052d0: f7fb fb7c bl 80009cc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 80052d4: 687b ldr r3, [r7, #4] 80052d6: 681b ldr r3, [r3, #0] 80052d8: 691b ldr r3, [r3, #16] 80052da: f003 0380 and.w r3, r3, #128 ; 0x80 80052de: 2b80 cmp r3, #128 ; 0x80 80052e0: d10e bne.n 8005300 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 80052e2: 687b ldr r3, [r7, #4] 80052e4: 681b ldr r3, [r3, #0] 80052e6: 68db ldr r3, [r3, #12] 80052e8: f003 0380 and.w r3, r3, #128 ; 0x80 80052ec: 2b80 cmp r3, #128 ; 0x80 80052ee: d107 bne.n 8005300 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 80052f0: 687b ldr r3, [r7, #4] 80052f2: 681b ldr r3, [r3, #0] 80052f4: f06f 0280 mvn.w r2, #128 ; 0x80 80052f8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 80052fa: 6878 ldr r0, [r7, #4] 80052fc: f000 fb52 bl 80059a4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) 8005300: 687b ldr r3, [r7, #4] 8005302: 681b ldr r3, [r3, #0] 8005304: 691b ldr r3, [r3, #16] 8005306: f403 7380 and.w r3, r3, #256 ; 0x100 800530a: f5b3 7f80 cmp.w r3, #256 ; 0x100 800530e: d10e bne.n 800532e { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 8005310: 687b ldr r3, [r7, #4] 8005312: 681b ldr r3, [r3, #0] 8005314: 68db ldr r3, [r3, #12] 8005316: f003 0380 and.w r3, r3, #128 ; 0x80 800531a: 2b80 cmp r3, #128 ; 0x80 800531c: d107 bne.n 800532e { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800531e: 687b ldr r3, [r7, #4] 8005320: 681b ldr r3, [r3, #0] 8005322: f46f 7280 mvn.w r2, #256 ; 0x100 8005326: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 8005328: 6878 ldr r0, [r7, #4] 800532a: f000 fb45 bl 80059b8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 800532e: 687b ldr r3, [r7, #4] 8005330: 681b ldr r3, [r3, #0] 8005332: 691b ldr r3, [r3, #16] 8005334: f003 0340 and.w r3, r3, #64 ; 0x40 8005338: 2b40 cmp r3, #64 ; 0x40 800533a: d10e bne.n 800535a { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 800533c: 687b ldr r3, [r7, #4] 800533e: 681b ldr r3, [r3, #0] 8005340: 68db ldr r3, [r3, #12] 8005342: f003 0340 and.w r3, r3, #64 ; 0x40 8005346: 2b40 cmp r3, #64 ; 0x40 8005348: d107 bne.n 800535a { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 800534a: 687b ldr r3, [r7, #4] 800534c: 681b ldr r3, [r3, #0] 800534e: f06f 0240 mvn.w r2, #64 ; 0x40 8005352: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8005354: 6878 ldr r0, [r7, #4] 8005356: f000 f931 bl 80055bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 800535a: 687b ldr r3, [r7, #4] 800535c: 681b ldr r3, [r3, #0] 800535e: 691b ldr r3, [r3, #16] 8005360: f003 0320 and.w r3, r3, #32 8005364: 2b20 cmp r3, #32 8005366: d10e bne.n 8005386 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 8005368: 687b ldr r3, [r7, #4] 800536a: 681b ldr r3, [r3, #0] 800536c: 68db ldr r3, [r3, #12] 800536e: f003 0320 and.w r3, r3, #32 8005372: 2b20 cmp r3, #32 8005374: d107 bne.n 8005386 { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 8005376: 687b ldr r3, [r7, #4] 8005378: 681b ldr r3, [r3, #0] 800537a: f06f 0220 mvn.w r2, #32 800537e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8005380: 6878 ldr r0, [r7, #4] 8005382: f000 fb05 bl 8005990 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8005386: bf00 nop 8005388: 3708 adds r7, #8 800538a: 46bd mov sp, r7 800538c: bd80 pop {r7, pc} ... 08005390 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { 8005390: b580 push {r7, lr} 8005392: b084 sub sp, #16 8005394: af00 add r7, sp, #0 8005396: 6078 str r0, [r7, #4] 8005398: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800539a: 2300 movs r3, #0 800539c: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 800539e: 687b ldr r3, [r7, #4] 80053a0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 80053a4: 2b01 cmp r3, #1 80053a6: d101 bne.n 80053ac 80053a8: 2302 movs r3, #2 80053aa: e0dc b.n 8005566 80053ac: 687b ldr r3, [r7, #4] 80053ae: 2201 movs r2, #1 80053b0: f883 203c strb.w r2, [r3, #60] ; 0x3c htim->State = HAL_TIM_STATE_BUSY; 80053b4: 687b ldr r3, [r7, #4] 80053b6: 2202 movs r2, #2 80053b8: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 80053bc: 687b ldr r3, [r7, #4] 80053be: 681b ldr r3, [r3, #0] 80053c0: 689b ldr r3, [r3, #8] 80053c2: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 80053c4: 68ba ldr r2, [r7, #8] 80053c6: 4b6a ldr r3, [pc, #424] ; (8005570 ) 80053c8: 4013 ands r3, r2 80053ca: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80053cc: 68bb ldr r3, [r7, #8] 80053ce: f423 437f bic.w r3, r3, #65280 ; 0xff00 80053d2: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 80053d4: 687b ldr r3, [r7, #4] 80053d6: 681b ldr r3, [r3, #0] 80053d8: 68ba ldr r2, [r7, #8] 80053da: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 80053dc: 683b ldr r3, [r7, #0] 80053de: 681b ldr r3, [r3, #0] 80053e0: 4a64 ldr r2, [pc, #400] ; (8005574 ) 80053e2: 4293 cmp r3, r2 80053e4: f000 80a9 beq.w 800553a 80053e8: 4a62 ldr r2, [pc, #392] ; (8005574 ) 80053ea: 4293 cmp r3, r2 80053ec: f200 80ae bhi.w 800554c 80053f0: 4a61 ldr r2, [pc, #388] ; (8005578 ) 80053f2: 4293 cmp r3, r2 80053f4: f000 80a1 beq.w 800553a 80053f8: 4a5f ldr r2, [pc, #380] ; (8005578 ) 80053fa: 4293 cmp r3, r2 80053fc: f200 80a6 bhi.w 800554c 8005400: 4a5e ldr r2, [pc, #376] ; (800557c ) 8005402: 4293 cmp r3, r2 8005404: f000 8099 beq.w 800553a 8005408: 4a5c ldr r2, [pc, #368] ; (800557c ) 800540a: 4293 cmp r3, r2 800540c: f200 809e bhi.w 800554c 8005410: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010 8005414: f000 8091 beq.w 800553a 8005418: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010 800541c: f200 8096 bhi.w 800554c 8005420: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8005424: f000 8089 beq.w 800553a 8005428: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 800542c: f200 808e bhi.w 800554c 8005430: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8005434: d03e beq.n 80054b4 8005436: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800543a: f200 8087 bhi.w 800554c 800543e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8005442: f000 8086 beq.w 8005552 8005446: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 800544a: d87f bhi.n 800554c 800544c: 2b70 cmp r3, #112 ; 0x70 800544e: d01a beq.n 8005486 8005450: 2b70 cmp r3, #112 ; 0x70 8005452: d87b bhi.n 800554c 8005454: 2b60 cmp r3, #96 ; 0x60 8005456: d050 beq.n 80054fa 8005458: 2b60 cmp r3, #96 ; 0x60 800545a: d877 bhi.n 800554c 800545c: 2b50 cmp r3, #80 ; 0x50 800545e: d03c beq.n 80054da 8005460: 2b50 cmp r3, #80 ; 0x50 8005462: d873 bhi.n 800554c 8005464: 2b40 cmp r3, #64 ; 0x40 8005466: d058 beq.n 800551a 8005468: 2b40 cmp r3, #64 ; 0x40 800546a: d86f bhi.n 800554c 800546c: 2b30 cmp r3, #48 ; 0x30 800546e: d064 beq.n 800553a 8005470: 2b30 cmp r3, #48 ; 0x30 8005472: d86b bhi.n 800554c 8005474: 2b20 cmp r3, #32 8005476: d060 beq.n 800553a 8005478: 2b20 cmp r3, #32 800547a: d867 bhi.n 800554c 800547c: 2b00 cmp r3, #0 800547e: d05c beq.n 800553a 8005480: 2b10 cmp r3, #16 8005482: d05a beq.n 800553a 8005484: e062 b.n 800554c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8005486: 687b ldr r3, [r7, #4] 8005488: 6818 ldr r0, [r3, #0] 800548a: 683b ldr r3, [r7, #0] 800548c: 6899 ldr r1, [r3, #8] 800548e: 683b ldr r3, [r7, #0] 8005490: 685a ldr r2, [r3, #4] 8005492: 683b ldr r3, [r7, #0] 8005494: 68db ldr r3, [r3, #12] 8005496: f000 f9bf bl 8005818 sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 800549a: 687b ldr r3, [r7, #4] 800549c: 681b ldr r3, [r3, #0] 800549e: 689b ldr r3, [r3, #8] 80054a0: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 80054a2: 68bb ldr r3, [r7, #8] 80054a4: f043 0377 orr.w r3, r3, #119 ; 0x77 80054a8: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80054aa: 687b ldr r3, [r7, #4] 80054ac: 681b ldr r3, [r3, #0] 80054ae: 68ba ldr r2, [r7, #8] 80054b0: 609a str r2, [r3, #8] break; 80054b2: e04f b.n 8005554 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80054b4: 687b ldr r3, [r7, #4] 80054b6: 6818 ldr r0, [r3, #0] 80054b8: 683b ldr r3, [r7, #0] 80054ba: 6899 ldr r1, [r3, #8] 80054bc: 683b ldr r3, [r7, #0] 80054be: 685a ldr r2, [r3, #4] 80054c0: 683b ldr r3, [r7, #0] 80054c2: 68db ldr r3, [r3, #12] 80054c4: f000 f9a8 bl 8005818 sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 80054c8: 687b ldr r3, [r7, #4] 80054ca: 681b ldr r3, [r3, #0] 80054cc: 689a ldr r2, [r3, #8] 80054ce: 687b ldr r3, [r7, #4] 80054d0: 681b ldr r3, [r3, #0] 80054d2: f442 4280 orr.w r2, r2, #16384 ; 0x4000 80054d6: 609a str r2, [r3, #8] break; 80054d8: e03c b.n 8005554 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80054da: 687b ldr r3, [r7, #4] 80054dc: 6818 ldr r0, [r3, #0] 80054de: 683b ldr r3, [r7, #0] 80054e0: 6859 ldr r1, [r3, #4] 80054e2: 683b ldr r3, [r7, #0] 80054e4: 68db ldr r3, [r3, #12] 80054e6: 461a mov r2, r3 80054e8: f000 f918 bl 800571c sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80054ec: 687b ldr r3, [r7, #4] 80054ee: 681b ldr r3, [r3, #0] 80054f0: 2150 movs r1, #80 ; 0x50 80054f2: 4618 mov r0, r3 80054f4: f000 f972 bl 80057dc break; 80054f8: e02c b.n 8005554 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 80054fa: 687b ldr r3, [r7, #4] 80054fc: 6818 ldr r0, [r3, #0] 80054fe: 683b ldr r3, [r7, #0] 8005500: 6859 ldr r1, [r3, #4] 8005502: 683b ldr r3, [r7, #0] 8005504: 68db ldr r3, [r3, #12] 8005506: 461a mov r2, r3 8005508: f000 f937 bl 800577a sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 800550c: 687b ldr r3, [r7, #4] 800550e: 681b ldr r3, [r3, #0] 8005510: 2160 movs r1, #96 ; 0x60 8005512: 4618 mov r0, r3 8005514: f000 f962 bl 80057dc break; 8005518: e01c b.n 8005554 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800551a: 687b ldr r3, [r7, #4] 800551c: 6818 ldr r0, [r3, #0] 800551e: 683b ldr r3, [r7, #0] 8005520: 6859 ldr r1, [r3, #4] 8005522: 683b ldr r3, [r7, #0] 8005524: 68db ldr r3, [r3, #12] 8005526: 461a mov r2, r3 8005528: f000 f8f8 bl 800571c sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 800552c: 687b ldr r3, [r7, #4] 800552e: 681b ldr r3, [r3, #0] 8005530: 2140 movs r1, #64 ; 0x40 8005532: 4618 mov r0, r3 8005534: f000 f952 bl 80057dc break; 8005538: e00c b.n 8005554 case TIM_CLOCKSOURCE_ITR8: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 800553a: 687b ldr r3, [r7, #4] 800553c: 681a ldr r2, [r3, #0] 800553e: 683b ldr r3, [r7, #0] 8005540: 681b ldr r3, [r3, #0] 8005542: 4619 mov r1, r3 8005544: 4610 mov r0, r2 8005546: f000 f949 bl 80057dc break; 800554a: e003 b.n 8005554 } default: status = HAL_ERROR; 800554c: 2301 movs r3, #1 800554e: 73fb strb r3, [r7, #15] break; 8005550: e000 b.n 8005554 break; 8005552: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8005554: 687b ldr r3, [r7, #4] 8005556: 2201 movs r2, #1 8005558: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 800555c: 687b ldr r3, [r7, #4] 800555e: 2200 movs r2, #0 8005560: f883 203c strb.w r2, [r3, #60] ; 0x3c return status; 8005564: 7bfb ldrb r3, [r7, #15] } 8005566: 4618 mov r0, r3 8005568: 3710 adds r7, #16 800556a: 46bd mov sp, r7 800556c: bd80 pop {r7, pc} 800556e: bf00 nop 8005570: ffceff88 .word 0xffceff88 8005574: 00100040 .word 0x00100040 8005578: 00100030 .word 0x00100030 800557c: 00100020 .word 0x00100020 08005580 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8005580: b480 push {r7} 8005582: b083 sub sp, #12 8005584: af00 add r7, sp, #0 8005586: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8005588: bf00 nop 800558a: 370c adds r7, #12 800558c: 46bd mov sp, r7 800558e: f85d 7b04 ldr.w r7, [sp], #4 8005592: 4770 bx lr 08005594 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8005594: b480 push {r7} 8005596: b083 sub sp, #12 8005598: af00 add r7, sp, #0 800559a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 800559c: bf00 nop 800559e: 370c adds r7, #12 80055a0: 46bd mov sp, r7 80055a2: f85d 7b04 ldr.w r7, [sp], #4 80055a6: 4770 bx lr 080055a8 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80055a8: b480 push {r7} 80055aa: b083 sub sp, #12 80055ac: af00 add r7, sp, #0 80055ae: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 80055b0: bf00 nop 80055b2: 370c adds r7, #12 80055b4: 46bd mov sp, r7 80055b6: f85d 7b04 ldr.w r7, [sp], #4 80055ba: 4770 bx lr 080055bc : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 80055bc: b480 push {r7} 80055be: b083 sub sp, #12 80055c0: af00 add r7, sp, #0 80055c2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 80055c4: bf00 nop 80055c6: 370c adds r7, #12 80055c8: 46bd mov sp, r7 80055ca: f85d 7b04 ldr.w r7, [sp], #4 80055ce: 4770 bx lr 080055d0 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 80055d0: b480 push {r7} 80055d2: b085 sub sp, #20 80055d4: af00 add r7, sp, #0 80055d6: 6078 str r0, [r7, #4] 80055d8: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80055da: 687b ldr r3, [r7, #4] 80055dc: 681b ldr r3, [r3, #0] 80055de: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80055e0: 687b ldr r3, [r7, #4] 80055e2: 4a44 ldr r2, [pc, #272] ; (80056f4 ) 80055e4: 4293 cmp r3, r2 80055e6: d013 beq.n 8005610 80055e8: 687b ldr r3, [r7, #4] 80055ea: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80055ee: d00f beq.n 8005610 80055f0: 687b ldr r3, [r7, #4] 80055f2: 4a41 ldr r2, [pc, #260] ; (80056f8 ) 80055f4: 4293 cmp r3, r2 80055f6: d00b beq.n 8005610 80055f8: 687b ldr r3, [r7, #4] 80055fa: 4a40 ldr r2, [pc, #256] ; (80056fc ) 80055fc: 4293 cmp r3, r2 80055fe: d007 beq.n 8005610 8005600: 687b ldr r3, [r7, #4] 8005602: 4a3f ldr r2, [pc, #252] ; (8005700 ) 8005604: 4293 cmp r3, r2 8005606: d003 beq.n 8005610 8005608: 687b ldr r3, [r7, #4] 800560a: 4a3e ldr r2, [pc, #248] ; (8005704 ) 800560c: 4293 cmp r3, r2 800560e: d108 bne.n 8005622 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8005610: 68fb ldr r3, [r7, #12] 8005612: f023 0370 bic.w r3, r3, #112 ; 0x70 8005616: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8005618: 683b ldr r3, [r7, #0] 800561a: 685b ldr r3, [r3, #4] 800561c: 68fa ldr r2, [r7, #12] 800561e: 4313 orrs r3, r2 8005620: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8005622: 687b ldr r3, [r7, #4] 8005624: 4a33 ldr r2, [pc, #204] ; (80056f4 ) 8005626: 4293 cmp r3, r2 8005628: d027 beq.n 800567a 800562a: 687b ldr r3, [r7, #4] 800562c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8005630: d023 beq.n 800567a 8005632: 687b ldr r3, [r7, #4] 8005634: 4a30 ldr r2, [pc, #192] ; (80056f8 ) 8005636: 4293 cmp r3, r2 8005638: d01f beq.n 800567a 800563a: 687b ldr r3, [r7, #4] 800563c: 4a2f ldr r2, [pc, #188] ; (80056fc ) 800563e: 4293 cmp r3, r2 8005640: d01b beq.n 800567a 8005642: 687b ldr r3, [r7, #4] 8005644: 4a2e ldr r2, [pc, #184] ; (8005700 ) 8005646: 4293 cmp r3, r2 8005648: d017 beq.n 800567a 800564a: 687b ldr r3, [r7, #4] 800564c: 4a2d ldr r2, [pc, #180] ; (8005704 ) 800564e: 4293 cmp r3, r2 8005650: d013 beq.n 800567a 8005652: 687b ldr r3, [r7, #4] 8005654: 4a2c ldr r2, [pc, #176] ; (8005708 ) 8005656: 4293 cmp r3, r2 8005658: d00f beq.n 800567a 800565a: 687b ldr r3, [r7, #4] 800565c: 4a2b ldr r2, [pc, #172] ; (800570c ) 800565e: 4293 cmp r3, r2 8005660: d00b beq.n 800567a 8005662: 687b ldr r3, [r7, #4] 8005664: 4a2a ldr r2, [pc, #168] ; (8005710 ) 8005666: 4293 cmp r3, r2 8005668: d007 beq.n 800567a 800566a: 687b ldr r3, [r7, #4] 800566c: 4a29 ldr r2, [pc, #164] ; (8005714 ) 800566e: 4293 cmp r3, r2 8005670: d003 beq.n 800567a 8005672: 687b ldr r3, [r7, #4] 8005674: 4a28 ldr r2, [pc, #160] ; (8005718 ) 8005676: 4293 cmp r3, r2 8005678: d108 bne.n 800568c { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800567a: 68fb ldr r3, [r7, #12] 800567c: f423 7340 bic.w r3, r3, #768 ; 0x300 8005680: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8005682: 683b ldr r3, [r7, #0] 8005684: 68db ldr r3, [r3, #12] 8005686: 68fa ldr r2, [r7, #12] 8005688: 4313 orrs r3, r2 800568a: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800568c: 68fb ldr r3, [r7, #12] 800568e: f023 0280 bic.w r2, r3, #128 ; 0x80 8005692: 683b ldr r3, [r7, #0] 8005694: 695b ldr r3, [r3, #20] 8005696: 4313 orrs r3, r2 8005698: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 800569a: 687b ldr r3, [r7, #4] 800569c: 68fa ldr r2, [r7, #12] 800569e: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80056a0: 683b ldr r3, [r7, #0] 80056a2: 689a ldr r2, [r3, #8] 80056a4: 687b ldr r3, [r7, #4] 80056a6: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80056a8: 683b ldr r3, [r7, #0] 80056aa: 681a ldr r2, [r3, #0] 80056ac: 687b ldr r3, [r7, #4] 80056ae: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80056b0: 687b ldr r3, [r7, #4] 80056b2: 4a10 ldr r2, [pc, #64] ; (80056f4 ) 80056b4: 4293 cmp r3, r2 80056b6: d00f beq.n 80056d8 80056b8: 687b ldr r3, [r7, #4] 80056ba: 4a12 ldr r2, [pc, #72] ; (8005704 ) 80056bc: 4293 cmp r3, r2 80056be: d00b beq.n 80056d8 80056c0: 687b ldr r3, [r7, #4] 80056c2: 4a11 ldr r2, [pc, #68] ; (8005708 ) 80056c4: 4293 cmp r3, r2 80056c6: d007 beq.n 80056d8 80056c8: 687b ldr r3, [r7, #4] 80056ca: 4a10 ldr r2, [pc, #64] ; (800570c ) 80056cc: 4293 cmp r3, r2 80056ce: d003 beq.n 80056d8 80056d0: 687b ldr r3, [r7, #4] 80056d2: 4a0f ldr r2, [pc, #60] ; (8005710 ) 80056d4: 4293 cmp r3, r2 80056d6: d103 bne.n 80056e0 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80056d8: 683b ldr r3, [r7, #0] 80056da: 691a ldr r2, [r3, #16] 80056dc: 687b ldr r3, [r7, #4] 80056de: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80056e0: 687b ldr r3, [r7, #4] 80056e2: 2201 movs r2, #1 80056e4: 615a str r2, [r3, #20] } 80056e6: bf00 nop 80056e8: 3714 adds r7, #20 80056ea: 46bd mov sp, r7 80056ec: f85d 7b04 ldr.w r7, [sp], #4 80056f0: 4770 bx lr 80056f2: bf00 nop 80056f4: 40010000 .word 0x40010000 80056f8: 40000400 .word 0x40000400 80056fc: 40000800 .word 0x40000800 8005700: 40000c00 .word 0x40000c00 8005704: 40010400 .word 0x40010400 8005708: 40014000 .word 0x40014000 800570c: 40014400 .word 0x40014400 8005710: 40014800 .word 0x40014800 8005714: 4000e000 .word 0x4000e000 8005718: 4000e400 .word 0x4000e400 0800571c : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 800571c: b480 push {r7} 800571e: b087 sub sp, #28 8005720: af00 add r7, sp, #0 8005722: 60f8 str r0, [r7, #12] 8005724: 60b9 str r1, [r7, #8] 8005726: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8005728: 68fb ldr r3, [r7, #12] 800572a: 6a1b ldr r3, [r3, #32] 800572c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 800572e: 68fb ldr r3, [r7, #12] 8005730: 6a1b ldr r3, [r3, #32] 8005732: f023 0201 bic.w r2, r3, #1 8005736: 68fb ldr r3, [r7, #12] 8005738: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 800573a: 68fb ldr r3, [r7, #12] 800573c: 699b ldr r3, [r3, #24] 800573e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8005740: 693b ldr r3, [r7, #16] 8005742: f023 03f0 bic.w r3, r3, #240 ; 0xf0 8005746: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8005748: 687b ldr r3, [r7, #4] 800574a: 011b lsls r3, r3, #4 800574c: 693a ldr r2, [r7, #16] 800574e: 4313 orrs r3, r2 8005750: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8005752: 697b ldr r3, [r7, #20] 8005754: f023 030a bic.w r3, r3, #10 8005758: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 800575a: 697a ldr r2, [r7, #20] 800575c: 68bb ldr r3, [r7, #8] 800575e: 4313 orrs r3, r2 8005760: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8005762: 68fb ldr r3, [r7, #12] 8005764: 693a ldr r2, [r7, #16] 8005766: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8005768: 68fb ldr r3, [r7, #12] 800576a: 697a ldr r2, [r7, #20] 800576c: 621a str r2, [r3, #32] } 800576e: bf00 nop 8005770: 371c adds r7, #28 8005772: 46bd mov sp, r7 8005774: f85d 7b04 ldr.w r7, [sp], #4 8005778: 4770 bx lr 0800577a : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 800577a: b480 push {r7} 800577c: b087 sub sp, #28 800577e: af00 add r7, sp, #0 8005780: 60f8 str r0, [r7, #12] 8005782: 60b9 str r1, [r7, #8] 8005784: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8005786: 68fb ldr r3, [r7, #12] 8005788: 6a1b ldr r3, [r3, #32] 800578a: f023 0210 bic.w r2, r3, #16 800578e: 68fb ldr r3, [r7, #12] 8005790: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8005792: 68fb ldr r3, [r7, #12] 8005794: 699b ldr r3, [r3, #24] 8005796: 617b str r3, [r7, #20] tmpccer = TIMx->CCER; 8005798: 68fb ldr r3, [r7, #12] 800579a: 6a1b ldr r3, [r3, #32] 800579c: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 800579e: 697b ldr r3, [r7, #20] 80057a0: f423 4370 bic.w r3, r3, #61440 ; 0xf000 80057a4: 617b str r3, [r7, #20] tmpccmr1 |= (TIM_ICFilter << 12U); 80057a6: 687b ldr r3, [r7, #4] 80057a8: 031b lsls r3, r3, #12 80057aa: 697a ldr r2, [r7, #20] 80057ac: 4313 orrs r3, r2 80057ae: 617b str r3, [r7, #20] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 80057b0: 693b ldr r3, [r7, #16] 80057b2: f023 03a0 bic.w r3, r3, #160 ; 0xa0 80057b6: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity << 4U); 80057b8: 68bb ldr r3, [r7, #8] 80057ba: 011b lsls r3, r3, #4 80057bc: 693a ldr r2, [r7, #16] 80057be: 4313 orrs r3, r2 80057c0: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 80057c2: 68fb ldr r3, [r7, #12] 80057c4: 697a ldr r2, [r7, #20] 80057c6: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 80057c8: 68fb ldr r3, [r7, #12] 80057ca: 693a ldr r2, [r7, #16] 80057cc: 621a str r2, [r3, #32] } 80057ce: bf00 nop 80057d0: 371c adds r7, #28 80057d2: 46bd mov sp, r7 80057d4: f85d 7b04 ldr.w r7, [sp], #4 80057d8: 4770 bx lr ... 080057dc : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 80057dc: b480 push {r7} 80057de: b085 sub sp, #20 80057e0: af00 add r7, sp, #0 80057e2: 6078 str r0, [r7, #4] 80057e4: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 80057e6: 687b ldr r3, [r7, #4] 80057e8: 689b ldr r3, [r3, #8] 80057ea: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 80057ec: 68fa ldr r2, [r7, #12] 80057ee: 4b09 ldr r3, [pc, #36] ; (8005814 ) 80057f0: 4013 ands r3, r2 80057f2: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 80057f4: 683a ldr r2, [r7, #0] 80057f6: 68fb ldr r3, [r7, #12] 80057f8: 4313 orrs r3, r2 80057fa: f043 0307 orr.w r3, r3, #7 80057fe: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8005800: 687b ldr r3, [r7, #4] 8005802: 68fa ldr r2, [r7, #12] 8005804: 609a str r2, [r3, #8] } 8005806: bf00 nop 8005808: 3714 adds r7, #20 800580a: 46bd mov sp, r7 800580c: f85d 7b04 ldr.w r7, [sp], #4 8005810: 4770 bx lr 8005812: bf00 nop 8005814: ffcfff8f .word 0xffcfff8f 08005818 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8005818: b480 push {r7} 800581a: b087 sub sp, #28 800581c: af00 add r7, sp, #0 800581e: 60f8 str r0, [r7, #12] 8005820: 60b9 str r1, [r7, #8] 8005822: 607a str r2, [r7, #4] 8005824: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8005826: 68fb ldr r3, [r7, #12] 8005828: 689b ldr r3, [r3, #8] 800582a: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800582c: 697b ldr r3, [r7, #20] 800582e: f423 437f bic.w r3, r3, #65280 ; 0xff00 8005832: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8005834: 683b ldr r3, [r7, #0] 8005836: 021a lsls r2, r3, #8 8005838: 687b ldr r3, [r7, #4] 800583a: 431a orrs r2, r3 800583c: 68bb ldr r3, [r7, #8] 800583e: 4313 orrs r3, r2 8005840: 697a ldr r2, [r7, #20] 8005842: 4313 orrs r3, r2 8005844: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8005846: 68fb ldr r3, [r7, #12] 8005848: 697a ldr r2, [r7, #20] 800584a: 609a str r2, [r3, #8] } 800584c: bf00 nop 800584e: 371c adds r7, #28 8005850: 46bd mov sp, r7 8005852: f85d 7b04 ldr.w r7, [sp], #4 8005856: 4770 bx lr 08005858 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { 8005858: b480 push {r7} 800585a: b085 sub sp, #20 800585c: af00 add r7, sp, #0 800585e: 6078 str r0, [r7, #4] 8005860: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8005862: 687b ldr r3, [r7, #4] 8005864: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8005868: 2b01 cmp r3, #1 800586a: d101 bne.n 8005870 800586c: 2302 movs r3, #2 800586e: e077 b.n 8005960 8005870: 687b ldr r3, [r7, #4] 8005872: 2201 movs r2, #1 8005874: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8005878: 687b ldr r3, [r7, #4] 800587a: 2202 movs r2, #2 800587c: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8005880: 687b ldr r3, [r7, #4] 8005882: 681b ldr r3, [r3, #0] 8005884: 685b ldr r3, [r3, #4] 8005886: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005888: 687b ldr r3, [r7, #4] 800588a: 681b ldr r3, [r3, #0] 800588c: 689b ldr r3, [r3, #8] 800588e: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 8005890: 687b ldr r3, [r7, #4] 8005892: 681b ldr r3, [r3, #0] 8005894: 4a35 ldr r2, [pc, #212] ; (800596c ) 8005896: 4293 cmp r3, r2 8005898: d004 beq.n 80058a4 800589a: 687b ldr r3, [r7, #4] 800589c: 681b ldr r3, [r3, #0] 800589e: 4a34 ldr r2, [pc, #208] ; (8005970 ) 80058a0: 4293 cmp r3, r2 80058a2: d108 bne.n 80058b6 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 80058a4: 68fb ldr r3, [r7, #12] 80058a6: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 80058aa: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 80058ac: 683b ldr r3, [r7, #0] 80058ae: 685b ldr r3, [r3, #4] 80058b0: 68fa ldr r2, [r7, #12] 80058b2: 4313 orrs r3, r2 80058b4: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80058b6: 68fb ldr r3, [r7, #12] 80058b8: f023 0370 bic.w r3, r3, #112 ; 0x70 80058bc: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80058be: 683b ldr r3, [r7, #0] 80058c0: 681b ldr r3, [r3, #0] 80058c2: 68fa ldr r2, [r7, #12] 80058c4: 4313 orrs r3, r2 80058c6: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80058c8: 687b ldr r3, [r7, #4] 80058ca: 681b ldr r3, [r3, #0] 80058cc: 68fa ldr r2, [r7, #12] 80058ce: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80058d0: 687b ldr r3, [r7, #4] 80058d2: 681b ldr r3, [r3, #0] 80058d4: 4a25 ldr r2, [pc, #148] ; (800596c ) 80058d6: 4293 cmp r3, r2 80058d8: d02c beq.n 8005934 80058da: 687b ldr r3, [r7, #4] 80058dc: 681b ldr r3, [r3, #0] 80058de: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80058e2: d027 beq.n 8005934 80058e4: 687b ldr r3, [r7, #4] 80058e6: 681b ldr r3, [r3, #0] 80058e8: 4a22 ldr r2, [pc, #136] ; (8005974 ) 80058ea: 4293 cmp r3, r2 80058ec: d022 beq.n 8005934 80058ee: 687b ldr r3, [r7, #4] 80058f0: 681b ldr r3, [r3, #0] 80058f2: 4a21 ldr r2, [pc, #132] ; (8005978 ) 80058f4: 4293 cmp r3, r2 80058f6: d01d beq.n 8005934 80058f8: 687b ldr r3, [r7, #4] 80058fa: 681b ldr r3, [r3, #0] 80058fc: 4a1f ldr r2, [pc, #124] ; (800597c ) 80058fe: 4293 cmp r3, r2 8005900: d018 beq.n 8005934 8005902: 687b ldr r3, [r7, #4] 8005904: 681b ldr r3, [r3, #0] 8005906: 4a1a ldr r2, [pc, #104] ; (8005970 ) 8005908: 4293 cmp r3, r2 800590a: d013 beq.n 8005934 800590c: 687b ldr r3, [r7, #4] 800590e: 681b ldr r3, [r3, #0] 8005910: 4a1b ldr r2, [pc, #108] ; (8005980 ) 8005912: 4293 cmp r3, r2 8005914: d00e beq.n 8005934 8005916: 687b ldr r3, [r7, #4] 8005918: 681b ldr r3, [r3, #0] 800591a: 4a1a ldr r2, [pc, #104] ; (8005984 ) 800591c: 4293 cmp r3, r2 800591e: d009 beq.n 8005934 8005920: 687b ldr r3, [r7, #4] 8005922: 681b ldr r3, [r3, #0] 8005924: 4a18 ldr r2, [pc, #96] ; (8005988 ) 8005926: 4293 cmp r3, r2 8005928: d004 beq.n 8005934 800592a: 687b ldr r3, [r7, #4] 800592c: 681b ldr r3, [r3, #0] 800592e: 4a17 ldr r2, [pc, #92] ; (800598c ) 8005930: 4293 cmp r3, r2 8005932: d10c bne.n 800594e { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8005934: 68bb ldr r3, [r7, #8] 8005936: f023 0380 bic.w r3, r3, #128 ; 0x80 800593a: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 800593c: 683b ldr r3, [r7, #0] 800593e: 689b ldr r3, [r3, #8] 8005940: 68ba ldr r2, [r7, #8] 8005942: 4313 orrs r3, r2 8005944: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005946: 687b ldr r3, [r7, #4] 8005948: 681b ldr r3, [r3, #0] 800594a: 68ba ldr r2, [r7, #8] 800594c: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 800594e: 687b ldr r3, [r7, #4] 8005950: 2201 movs r2, #1 8005952: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 8005956: 687b ldr r3, [r7, #4] 8005958: 2200 movs r2, #0 800595a: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 800595e: 2300 movs r3, #0 } 8005960: 4618 mov r0, r3 8005962: 3714 adds r7, #20 8005964: 46bd mov sp, r7 8005966: f85d 7b04 ldr.w r7, [sp], #4 800596a: 4770 bx lr 800596c: 40010000 .word 0x40010000 8005970: 40010400 .word 0x40010400 8005974: 40000400 .word 0x40000400 8005978: 40000800 .word 0x40000800 800597c: 40000c00 .word 0x40000c00 8005980: 40001800 .word 0x40001800 8005984: 40014000 .word 0x40014000 8005988: 4000e000 .word 0x4000e000 800598c: 4000e400 .word 0x4000e400 08005990 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8005990: b480 push {r7} 8005992: b083 sub sp, #12 8005994: af00 add r7, sp, #0 8005996: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8005998: bf00 nop 800599a: 370c adds r7, #12 800599c: 46bd mov sp, r7 800599e: f85d 7b04 ldr.w r7, [sp], #4 80059a2: 4770 bx lr 080059a4 : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 80059a4: b480 push {r7} 80059a6: b083 sub sp, #12 80059a8: af00 add r7, sp, #0 80059aa: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 80059ac: bf00 nop 80059ae: 370c adds r7, #12 80059b0: 46bd mov sp, r7 80059b2: f85d 7b04 ldr.w r7, [sp], #4 80059b6: 4770 bx lr 080059b8 : * @brief Hall Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 80059b8: b480 push {r7} 80059ba: b083 sub sp, #12 80059bc: af00 add r7, sp, #0 80059be: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 80059c0: bf00 nop 80059c2: 370c adds r7, #12 80059c4: 46bd mov sp, r7 80059c6: f85d 7b04 ldr.w r7, [sp], #4 80059ca: 4770 bx lr 080059cc : * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { 80059cc: b480 push {r7} 80059ce: b085 sub sp, #20 80059d0: af00 add r7, sp, #0 80059d2: 60f8 str r0, [r7, #12] 80059d4: 60b9 str r1, [r7, #8] 80059d6: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); 80059d8: 68fb ldr r3, [r7, #12] 80059da: 6819 ldr r1, [r3, #0] 80059dc: 68bb ldr r3, [r7, #8] 80059de: fb03 f203 mul.w r2, r3, r3 80059e2: 4613 mov r3, r2 80059e4: 005b lsls r3, r3, #1 80059e6: 4413 add r3, r2 80059e8: 43db mvns r3, r3 80059ea: ea01 0203 and.w r2, r1, r3 80059ee: 68bb ldr r3, [r7, #8] 80059f0: fb03 f303 mul.w r3, r3, r3 80059f4: 6879 ldr r1, [r7, #4] 80059f6: fb01 f303 mul.w r3, r1, r3 80059fa: 431a orrs r2, r3 80059fc: 68fb ldr r3, [r7, #12] 80059fe: 601a str r2, [r3, #0] } 8005a00: bf00 nop 8005a02: 3714 adds r7, #20 8005a04: 46bd mov sp, r7 8005a06: f85d 7b04 ldr.w r7, [sp], #4 8005a0a: 4770 bx lr 08005a0c : * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) { 8005a0c: b480 push {r7} 8005a0e: b085 sub sp, #20 8005a10: af00 add r7, sp, #0 8005a12: 60f8 str r0, [r7, #12] 8005a14: 60b9 str r1, [r7, #8] 8005a16: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); 8005a18: 68fb ldr r3, [r7, #12] 8005a1a: 685a ldr r2, [r3, #4] 8005a1c: 68bb ldr r3, [r7, #8] 8005a1e: 43db mvns r3, r3 8005a20: 401a ands r2, r3 8005a22: 68bb ldr r3, [r7, #8] 8005a24: 6879 ldr r1, [r7, #4] 8005a26: fb01 f303 mul.w r3, r1, r3 8005a2a: 431a orrs r2, r3 8005a2c: 68fb ldr r3, [r7, #12] 8005a2e: 605a str r2, [r3, #4] } 8005a30: bf00 nop 8005a32: 3714 adds r7, #20 8005a34: 46bd mov sp, r7 8005a36: f85d 7b04 ldr.w r7, [sp], #4 8005a3a: 4770 bx lr 08005a3c : * @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) { 8005a3c: b480 push {r7} 8005a3e: b085 sub sp, #20 8005a40: af00 add r7, sp, #0 8005a42: 60f8 str r0, [r7, #12] 8005a44: 60b9 str r1, [r7, #8] 8005a46: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed)); 8005a48: 68fb ldr r3, [r7, #12] 8005a4a: 6899 ldr r1, [r3, #8] 8005a4c: 68bb ldr r3, [r7, #8] 8005a4e: fb03 f203 mul.w r2, r3, r3 8005a52: 4613 mov r3, r2 8005a54: 005b lsls r3, r3, #1 8005a56: 4413 add r3, r2 8005a58: 43db mvns r3, r3 8005a5a: ea01 0203 and.w r2, r1, r3 8005a5e: 68bb ldr r3, [r7, #8] 8005a60: fb03 f303 mul.w r3, r3, r3 8005a64: 6879 ldr r1, [r7, #4] 8005a66: fb01 f303 mul.w r3, r1, r3 8005a6a: 431a orrs r2, r3 8005a6c: 68fb ldr r3, [r7, #12] 8005a6e: 609a str r2, [r3, #8] } 8005a70: bf00 nop 8005a72: 3714 adds r7, #20 8005a74: 46bd mov sp, r7 8005a76: f85d 7b04 ldr.w r7, [sp], #4 8005a7a: 4770 bx lr 08005a7c : * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) { 8005a7c: b480 push {r7} 8005a7e: b085 sub sp, #20 8005a80: af00 add r7, sp, #0 8005a82: 60f8 str r0, [r7, #12] 8005a84: 60b9 str r1, [r7, #8] 8005a86: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); 8005a88: 68fb ldr r3, [r7, #12] 8005a8a: 68d9 ldr r1, [r3, #12] 8005a8c: 68bb ldr r3, [r7, #8] 8005a8e: fb03 f203 mul.w r2, r3, r3 8005a92: 4613 mov r3, r2 8005a94: 005b lsls r3, r3, #1 8005a96: 4413 add r3, r2 8005a98: 43db mvns r3, r3 8005a9a: ea01 0203 and.w r2, r1, r3 8005a9e: 68bb ldr r3, [r7, #8] 8005aa0: fb03 f303 mul.w r3, r3, r3 8005aa4: 6879 ldr r1, [r7, #4] 8005aa6: fb01 f303 mul.w r3, r1, r3 8005aaa: 431a orrs r2, r3 8005aac: 68fb ldr r3, [r7, #12] 8005aae: 60da str r2, [r3, #12] } 8005ab0: bf00 nop 8005ab2: 3714 adds r7, #20 8005ab4: 46bd mov sp, r7 8005ab6: f85d 7b04 ldr.w r7, [sp], #4 8005aba: 4770 bx lr 08005abc : * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 * @retval None */ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { 8005abc: b480 push {r7} 8005abe: b085 sub sp, #20 8005ac0: af00 add r7, sp, #0 8005ac2: 60f8 str r0, [r7, #12] 8005ac4: 60b9 str r1, [r7, #8] 8005ac6: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), 8005ac8: 68fb ldr r3, [r7, #12] 8005aca: 6a19 ldr r1, [r3, #32] 8005acc: 68bb ldr r3, [r7, #8] 8005ace: fb03 f303 mul.w r3, r3, r3 8005ad2: 68ba ldr r2, [r7, #8] 8005ad4: fb02 f303 mul.w r3, r2, r3 8005ad8: 68ba ldr r2, [r7, #8] 8005ada: fb02 f203 mul.w r2, r2, r3 8005ade: 4613 mov r3, r2 8005ae0: 011b lsls r3, r3, #4 8005ae2: 1a9b subs r3, r3, r2 8005ae4: 43db mvns r3, r3 8005ae6: ea01 0203 and.w r2, r1, r3 8005aea: 68bb ldr r3, [r7, #8] 8005aec: fb03 f303 mul.w r3, r3, r3 8005af0: 68b9 ldr r1, [r7, #8] 8005af2: fb01 f303 mul.w r3, r1, r3 8005af6: 68b9 ldr r1, [r7, #8] 8005af8: fb01 f303 mul.w r3, r1, r3 8005afc: 6879 ldr r1, [r7, #4] 8005afe: fb01 f303 mul.w r3, r1, r3 8005b02: 431a orrs r2, r3 8005b04: 68fb ldr r3, [r7, #12] 8005b06: 621a str r2, [r3, #32] ((((Pin * Pin) * Pin) * Pin) * Alternate)); } 8005b08: bf00 nop 8005b0a: 3714 adds r7, #20 8005b0c: 46bd mov sp, r7 8005b0e: f85d 7b04 ldr.w r7, [sp], #4 8005b12: 4770 bx lr 08005b14 : * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 * @retval None */ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { 8005b14: b480 push {r7} 8005b16: b085 sub sp, #20 8005b18: af00 add r7, sp, #0 8005b1a: 60f8 str r0, [r7, #12] 8005b1c: 60b9 str r1, [r7, #8] 8005b1e: 607a str r2, [r7, #4] MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), 8005b20: 68fb ldr r3, [r7, #12] 8005b22: 6a59 ldr r1, [r3, #36] ; 0x24 8005b24: 68bb ldr r3, [r7, #8] 8005b26: 0a1b lsrs r3, r3, #8 8005b28: 68ba ldr r2, [r7, #8] 8005b2a: 0a12 lsrs r2, r2, #8 8005b2c: fb02 f303 mul.w r3, r2, r3 8005b30: 68ba ldr r2, [r7, #8] 8005b32: 0a12 lsrs r2, r2, #8 8005b34: fb02 f303 mul.w r3, r2, r3 8005b38: 68ba ldr r2, [r7, #8] 8005b3a: 0a12 lsrs r2, r2, #8 8005b3c: fb02 f203 mul.w r2, r2, r3 8005b40: 4613 mov r3, r2 8005b42: 011b lsls r3, r3, #4 8005b44: 1a9b subs r3, r3, r2 8005b46: 43db mvns r3, r3 8005b48: ea01 0203 and.w r2, r1, r3 8005b4c: 68bb ldr r3, [r7, #8] 8005b4e: 0a1b lsrs r3, r3, #8 8005b50: 68b9 ldr r1, [r7, #8] 8005b52: 0a09 lsrs r1, r1, #8 8005b54: fb01 f303 mul.w r3, r1, r3 8005b58: 68b9 ldr r1, [r7, #8] 8005b5a: 0a09 lsrs r1, r1, #8 8005b5c: fb01 f303 mul.w r3, r1, r3 8005b60: 68b9 ldr r1, [r7, #8] 8005b62: 0a09 lsrs r1, r1, #8 8005b64: fb01 f303 mul.w r3, r1, r3 8005b68: 6879 ldr r1, [r7, #4] 8005b6a: fb01 f303 mul.w r3, r1, r3 8005b6e: 431a orrs r2, r3 8005b70: 68fb ldr r3, [r7, #12] 8005b72: 625a str r2, [r3, #36] ; 0x24 (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); } 8005b74: bf00 nop 8005b76: 3714 adds r7, #20 8005b78: 46bd mov sp, r7 8005b7a: f85d 7b04 ldr.w r7, [sp], #4 8005b7e: 4770 bx lr 08005b80 : * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content * - ERROR: Not applicable */ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) { 8005b80: b580 push {r7, lr} 8005b82: b088 sub sp, #32 8005b84: af00 add r7, sp, #0 8005b86: 6078 str r0, [r7, #4] 8005b88: 6039 str r1, [r7, #0] assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); /* ------------------------- Configure the port pins ---------------- */ /* Initialize pinpos on first pin set */ pinpos = POSITION_VAL(GPIO_InitStruct->Pin); 8005b8a: 683b ldr r3, [r7, #0] 8005b8c: 681b ldr r3, [r3, #0] 8005b8e: 613b str r3, [r7, #16] uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005b90: 693b ldr r3, [r7, #16] 8005b92: fa93 f3a3 rbit r3, r3 8005b96: 60fb str r3, [r7, #12] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8005b98: 68fb ldr r3, [r7, #12] 8005b9a: 617b str r3, [r7, #20] optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 8005b9c: 697b ldr r3, [r7, #20] 8005b9e: 2b00 cmp r3, #0 8005ba0: d101 bne.n 8005ba6 { return 32U; 8005ba2: 2320 movs r3, #32 8005ba4: e003 b.n 8005bae } return __builtin_clz(value); 8005ba6: 697b ldr r3, [r7, #20] 8005ba8: fab3 f383 clz r3, r3 8005bac: b2db uxtb r3, r3 8005bae: 61fb str r3, [r7, #28] /* Configure the port pins */ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) 8005bb0: e048 b.n 8005c44 { /* Get current io position */ currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos); 8005bb2: 683b ldr r3, [r7, #0] 8005bb4: 681a ldr r2, [r3, #0] 8005bb6: 2101 movs r1, #1 8005bb8: 69fb ldr r3, [r7, #28] 8005bba: fa01 f303 lsl.w r3, r1, r3 8005bbe: 4013 ands r3, r2 8005bc0: 61bb str r3, [r7, #24] if (currentpin != 0x00000000U) 8005bc2: 69bb ldr r3, [r7, #24] 8005bc4: 2b00 cmp r3, #0 8005bc6: d03a beq.n 8005c3e { if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) 8005bc8: 683b ldr r3, [r7, #0] 8005bca: 685b ldr r3, [r3, #4] 8005bcc: 2b01 cmp r3, #1 8005bce: d003 beq.n 8005bd8 8005bd0: 683b ldr r3, [r7, #0] 8005bd2: 685b ldr r3, [r3, #4] 8005bd4: 2b02 cmp r3, #2 8005bd6: d10e bne.n 8005bf6 { /* Check Speed mode parameters */ assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); /* Speed mode configuration */ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); 8005bd8: 683b ldr r3, [r7, #0] 8005bda: 689b ldr r3, [r3, #8] 8005bdc: 461a mov r2, r3 8005bde: 69b9 ldr r1, [r7, #24] 8005be0: 6878 ldr r0, [r7, #4] 8005be2: f7ff ff2b bl 8005a3c /* Check Output mode parameters */ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); /* Output mode configuration*/ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); 8005be6: 683b ldr r3, [r7, #0] 8005be8: 6819 ldr r1, [r3, #0] 8005bea: 683b ldr r3, [r7, #0] 8005bec: 68db ldr r3, [r3, #12] 8005bee: 461a mov r2, r3 8005bf0: 6878 ldr r0, [r7, #4] 8005bf2: f7ff ff0b bl 8005a0c } /* Pull-up Pull down resistor configuration*/ LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); 8005bf6: 683b ldr r3, [r7, #0] 8005bf8: 691b ldr r3, [r3, #16] 8005bfa: 461a mov r2, r3 8005bfc: 69b9 ldr r1, [r7, #24] 8005bfe: 6878 ldr r0, [r7, #4] 8005c00: f7ff ff3c bl 8005a7c if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) 8005c04: 683b ldr r3, [r7, #0] 8005c06: 685b ldr r3, [r3, #4] 8005c08: 2b02 cmp r3, #2 8005c0a: d111 bne.n 8005c30 { /* Check Alternate parameter */ assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); /* Alternate function configuration */ if (currentpin < LL_GPIO_PIN_8) 8005c0c: 69bb ldr r3, [r7, #24] 8005c0e: 2bff cmp r3, #255 ; 0xff 8005c10: d807 bhi.n 8005c22 { LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); 8005c12: 683b ldr r3, [r7, #0] 8005c14: 695b ldr r3, [r3, #20] 8005c16: 461a mov r2, r3 8005c18: 69b9 ldr r1, [r7, #24] 8005c1a: 6878 ldr r0, [r7, #4] 8005c1c: f7ff ff4e bl 8005abc 8005c20: e006 b.n 8005c30 } else { LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); 8005c22: 683b ldr r3, [r7, #0] 8005c24: 695b ldr r3, [r3, #20] 8005c26: 461a mov r2, r3 8005c28: 69b9 ldr r1, [r7, #24] 8005c2a: 6878 ldr r0, [r7, #4] 8005c2c: f7ff ff72 bl 8005b14 } } /* Pin Mode configuration */ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); 8005c30: 683b ldr r3, [r7, #0] 8005c32: 685b ldr r3, [r3, #4] 8005c34: 461a mov r2, r3 8005c36: 69b9 ldr r1, [r7, #24] 8005c38: 6878 ldr r0, [r7, #4] 8005c3a: f7ff fec7 bl 80059cc } pinpos++; 8005c3e: 69fb ldr r3, [r7, #28] 8005c40: 3301 adds r3, #1 8005c42: 61fb str r3, [r7, #28] while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) 8005c44: 683b ldr r3, [r7, #0] 8005c46: 681a ldr r2, [r3, #0] 8005c48: 69fb ldr r3, [r7, #28] 8005c4a: fa22 f303 lsr.w r3, r2, r3 8005c4e: 2b00 cmp r3, #0 8005c50: d1af bne.n 8005bb2 } return (SUCCESS); 8005c52: 2300 movs r3, #0 } 8005c54: 4618 mov r0, r3 8005c56: 3720 adds r7, #32 8005c58: 46bd mov sp, r7 8005c5a: bd80 pop {r7, pc} 08005c5c : { 8005c5c: b480 push {r7} 8005c5e: b083 sub sp, #12 8005c60: af00 add r7, sp, #0 8005c62: 6078 str r0, [r7, #4] return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); 8005c64: 687b ldr r3, [r7, #4] 8005c66: 681b ldr r3, [r3, #0] 8005c68: f003 0301 and.w r3, r3, #1 8005c6c: 2b01 cmp r3, #1 8005c6e: d101 bne.n 8005c74 8005c70: 2301 movs r3, #1 8005c72: e000 b.n 8005c76 8005c74: 2300 movs r3, #0 } 8005c76: 4618 mov r0, r3 8005c78: 370c adds r7, #12 8005c7a: 46bd mov sp, r7 8005c7c: f85d 7b04 ldr.w r7, [sp], #4 8005c80: 4770 bx lr 08005c82 : { 8005c82: b480 push {r7} 8005c84: b083 sub sp, #12 8005c86: af00 add r7, sp, #0 8005c88: 6078 str r0, [r7, #4] 8005c8a: 6039 str r1, [r7, #0] MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel); 8005c8c: 687b ldr r3, [r7, #4] 8005c8e: 681b ldr r3, [r3, #0] 8005c90: f423 5280 bic.w r2, r3, #4096 ; 0x1000 8005c94: 683b ldr r3, [r7, #0] 8005c96: 431a orrs r2, r3 8005c98: 687b ldr r3, [r7, #4] 8005c9a: 601a str r2, [r3, #0] } 8005c9c: bf00 nop 8005c9e: 370c adds r7, #12 8005ca0: 46bd mov sp, r7 8005ca2: f85d 7b04 ldr.w r7, [sp], #4 8005ca6: 4770 bx lr 08005ca8 : { 8005ca8: b480 push {r7} 8005caa: b083 sub sp, #12 8005cac: af00 add r7, sp, #0 8005cae: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP)); 8005cb0: 687b ldr r3, [r7, #4] 8005cb2: 68db ldr r3, [r3, #12] 8005cb4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 } 8005cb8: 4618 mov r0, r3 8005cba: 370c adds r7, #12 8005cbc: 46bd mov sp, r7 8005cbe: f85d 7b04 ldr.w r7, [sp], #4 8005cc2: 4770 bx lr 08005cc4 : * @param SPIx SPI Instance * @param CRCPoly 0..0xFFFFFFFF * @retval None */ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) { 8005cc4: b480 push {r7} 8005cc6: b083 sub sp, #12 8005cc8: af00 add r7, sp, #0 8005cca: 6078 str r0, [r7, #4] 8005ccc: 6039 str r1, [r7, #0] WRITE_REG(SPIx->CRCPOLY, CRCPoly); 8005cce: 687b ldr r3, [r7, #4] 8005cd0: 683a ldr r2, [r7, #0] 8005cd2: 641a str r2, [r3, #64] ; 0x40 } 8005cd4: bf00 nop 8005cd6: 370c adds r7, #12 8005cd8: 46bd mov sp, r7 8005cda: f85d 7b04 ldr.w r7, [sp], #4 8005cde: 4770 bx lr 08005ce0 : * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) */ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) { 8005ce0: b580 push {r7, lr} 8005ce2: b086 sub sp, #24 8005ce4: af00 add r7, sp, #0 8005ce6: 6078 str r0, [r7, #4] 8005ce8: 6039 str r1, [r7, #0] ErrorStatus status = ERROR; 8005cea: 2301 movs r3, #1 8005cec: 75fb strb r3, [r7, #23] assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate)); assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); /* Check the SPI instance is not enabled */ if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL) 8005cee: 6878 ldr r0, [r7, #4] 8005cf0: f7ff ffb4 bl 8005c5c 8005cf4: 4603 mov r3, r0 8005cf6: 2b00 cmp r3, #0 8005cf8: d169 bne.n 8005dce * Configure SPIx CFG1 with parameters: * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits * - CRC Computation Enable : SPI_CFG1_CRCEN bit * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits */ MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE, 8005cfa: 687b ldr r3, [r7, #4] 8005cfc: 689a ldr r2, [r3, #8] 8005cfe: 4b36 ldr r3, [pc, #216] ; (8005dd8 ) 8005d00: 4013 ands r3, r2 8005d02: 683a ldr r2, [r7, #0] 8005d04: 6991 ldr r1, [r2, #24] 8005d06: 683a ldr r2, [r7, #0] 8005d08: 6a12 ldr r2, [r2, #32] 8005d0a: 4311 orrs r1, r2 8005d0c: 683a ldr r2, [r7, #0] 8005d0e: 6892 ldr r2, [r2, #8] 8005d10: 430a orrs r2, r1 8005d12: 431a orrs r2, r3 8005d14: 687b ldr r3, [r7, #4] 8005d16: 609a str r2, [r3, #8] SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth); tmp_nss = SPI_InitStruct->NSS; 8005d18: 683b ldr r3, [r7, #0] 8005d1a: 695b ldr r3, [r3, #20] 8005d1c: 613b str r3, [r7, #16] tmp_mode = SPI_InitStruct->Mode; 8005d1e: 683b ldr r3, [r7, #0] 8005d20: 685b ldr r3, [r3, #4] 8005d22: 60fb str r3, [r7, #12] /* Checks to setup Internal SS signal level and avoid a MODF Error */ if ((tmp_nss == LL_SPI_NSS_SOFT) && (((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && \ 8005d24: 693b ldr r3, [r7, #16] 8005d26: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 8005d2a: d118 bne.n 8005d5e 8005d2c: 6878 ldr r0, [r7, #4] 8005d2e: f7ff ffbb bl 8005ca8 8005d32: 4603 mov r3, r0 8005d34: 2b00 cmp r3, #0 8005d36: d103 bne.n 8005d40 8005d38: 68fb ldr r3, [r7, #12] 8005d3a: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8005d3e: d009 beq.n 8005d54 (tmp_mode == LL_SPI_MODE_MASTER)) || \ ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && \ 8005d40: 6878 ldr r0, [r7, #4] 8005d42: f7ff ffb1 bl 8005ca8 8005d46: 4603 mov r3, r0 (tmp_mode == LL_SPI_MODE_MASTER)) || \ 8005d48: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8005d4c: d107 bne.n 8005d5e ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && \ 8005d4e: 68fb ldr r3, [r7, #12] 8005d50: 2b00 cmp r3, #0 8005d52: d104 bne.n 8005d5e (tmp_mode == LL_SPI_MODE_SLAVE)))) { LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); 8005d54: f44f 5180 mov.w r1, #4096 ; 0x1000 8005d58: 6878 ldr r0, [r7, #4] 8005d5a: f7ff ff92 bl 8005c82 * - ClockPhase : SPI_CFG2_CPHA bit * - BitOrder : SPI_CFG2_LSBFRST bit * - Master/Slave Mode : SPI_CFG2_MASTER bit * - SPI Mode : SPI_CFG2_COMM[1:0] bits */ MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE | 8005d5e: 687b ldr r3, [r7, #4] 8005d60: 68da ldr r2, [r3, #12] 8005d62: 4b1e ldr r3, [pc, #120] ; (8005ddc ) 8005d64: 4013 ands r3, r2 8005d66: 683a ldr r2, [r7, #0] 8005d68: 6951 ldr r1, [r2, #20] 8005d6a: 683a ldr r2, [r7, #0] 8005d6c: 68d2 ldr r2, [r2, #12] 8005d6e: 4311 orrs r1, r2 8005d70: 683a ldr r2, [r7, #0] 8005d72: 6912 ldr r2, [r2, #16] 8005d74: 4311 orrs r1, r2 8005d76: 683a ldr r2, [r7, #0] 8005d78: 69d2 ldr r2, [r2, #28] 8005d7a: 4311 orrs r1, r2 8005d7c: 683a ldr r2, [r7, #0] 8005d7e: 6852 ldr r2, [r2, #4] 8005d80: 4311 orrs r1, r2 8005d82: 683a ldr r2, [r7, #0] 8005d84: 6812 ldr r2, [r2, #0] 8005d86: f402 22c0 and.w r2, r2, #393216 ; 0x60000 8005d8a: 430a orrs r2, r1 8005d8c: 431a orrs r2, r3 8005d8e: 687b ldr r3, [r7, #4] 8005d90: 60da str r2, [r3, #12] /*---------------------------- SPIx CR1 Configuration ------------------------ * Configure SPIx CR1 with parameter: * - Half Duplex Direction : SPI_CR1_HDDIR bit */ MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR); 8005d92: 687b ldr r3, [r7, #4] 8005d94: 681b ldr r3, [r3, #0] 8005d96: f423 6200 bic.w r2, r3, #2048 ; 0x800 8005d9a: 683b ldr r3, [r7, #0] 8005d9c: 681b ldr r3, [r3, #0] 8005d9e: f403 6300 and.w r3, r3, #2048 ; 0x800 8005da2: 431a orrs r2, r3 8005da4: 687b ldr r3, [r7, #4] 8005da6: 601a str r2, [r3, #0] /*---------------------------- SPIx CRCPOLY Configuration ---------------------- * Configure SPIx CRCPOLY with parameter: * - CRCPoly : CRCPOLY[31:0] bits */ if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) 8005da8: 683b ldr r3, [r7, #0] 8005daa: 6a1b ldr r3, [r3, #32] 8005dac: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8005db0: d105 bne.n 8005dbe { assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); 8005db2: 683b ldr r3, [r7, #0] 8005db4: 6a5b ldr r3, [r3, #36] ; 0x24 8005db6: 4619 mov r1, r3 8005db8: 6878 ldr r0, [r7, #4] 8005dba: f7ff ff83 bl 8005cc4 } /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); 8005dbe: 687b ldr r3, [r7, #4] 8005dc0: 6d1b ldr r3, [r3, #80] ; 0x50 8005dc2: f023 0201 bic.w r2, r3, #1 8005dc6: 687b ldr r3, [r7, #4] 8005dc8: 651a str r2, [r3, #80] ; 0x50 status = SUCCESS; 8005dca: 2300 movs r3, #0 8005dcc: 75fb strb r3, [r7, #23] } return status; 8005dce: 7dfb ldrb r3, [r7, #23] } 8005dd0: 4618 mov r0, r3 8005dd2: 3718 adds r7, #24 8005dd4: 46bd mov sp, r7 8005dd6: bd80 pop {r7, pc} 8005dd8: 8fbfffe0 .word 0x8fbfffe0 8005ddc: d839ffff .word 0xd839ffff 08005de0 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8005de0: b084 sub sp, #16 8005de2: b580 push {r7, lr} 8005de4: b084 sub sp, #16 8005de6: af00 add r7, sp, #0 8005de8: 6078 str r0, [r7, #4] 8005dea: f107 001c add.w r0, r7, #28 8005dee: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8005df2: 6b3b ldr r3, [r7, #48] ; 0x30 8005df4: 2b01 cmp r3, #1 8005df6: d120 bne.n 8005e3a { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8005df8: 687b ldr r3, [r7, #4] 8005dfa: 6b9b ldr r3, [r3, #56] ; 0x38 8005dfc: f423 3280 bic.w r2, r3, #65536 ; 0x10000 8005e00: 687b ldr r3, [r7, #4] 8005e02: 639a str r2, [r3, #56] ; 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 8005e04: 687b ldr r3, [r7, #4] 8005e06: 68da ldr r2, [r3, #12] 8005e08: 4b2a ldr r3, [pc, #168] ; (8005eb4 ) 8005e0a: 4013 ands r3, r2 8005e0c: 687a ldr r2, [r7, #4] 8005e0e: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 8005e10: 687b ldr r3, [r7, #4] 8005e12: 68db ldr r3, [r3, #12] 8005e14: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8005e18: 687b ldr r3, [r7, #4] 8005e1a: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 8005e1c: 6cfb ldr r3, [r7, #76] ; 0x4c 8005e1e: 2b01 cmp r3, #1 8005e20: d105 bne.n 8005e2e { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 8005e22: 687b ldr r3, [r7, #4] 8005e24: 68db ldr r3, [r3, #12] 8005e26: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8005e2a: 687b ldr r3, [r7, #4] 8005e2c: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8005e2e: 6878 ldr r0, [r7, #4] 8005e30: f001 fb4e bl 80074d0 8005e34: 4603 mov r3, r0 8005e36: 73fb strb r3, [r7, #15] 8005e38: e01a b.n 8005e70 } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 8005e3a: 687b ldr r3, [r7, #4] 8005e3c: 68db ldr r3, [r3, #12] 8005e3e: f043 0240 orr.w r2, r3, #64 ; 0x40 8005e42: 687b ldr r3, [r7, #4] 8005e44: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8005e46: 6878 ldr r0, [r7, #4] 8005e48: f001 fb42 bl 80074d0 8005e4c: 4603 mov r3, r0 8005e4e: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 8005e50: 6c3b ldr r3, [r7, #64] ; 0x40 8005e52: 2b00 cmp r3, #0 8005e54: d106 bne.n 8005e64 { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8005e56: 687b ldr r3, [r7, #4] 8005e58: 6b9b ldr r3, [r3, #56] ; 0x38 8005e5a: f443 3280 orr.w r2, r3, #65536 ; 0x10000 8005e5e: 687b ldr r3, [r7, #4] 8005e60: 639a str r2, [r3, #56] ; 0x38 8005e62: e005 b.n 8005e70 } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8005e64: 687b ldr r3, [r7, #4] 8005e66: 6b9b ldr r3, [r3, #56] ; 0x38 8005e68: f423 3280 bic.w r2, r3, #65536 ; 0x10000 8005e6c: 687b ldr r3, [r7, #4] 8005e6e: 639a str r2, [r3, #56] ; 0x38 } } if (cfg.dma_enable == 1U) 8005e70: 6abb ldr r3, [r7, #40] ; 0x28 8005e72: 2b01 cmp r3, #1 8005e74: d116 bne.n 8005ea4 { /* make sure to reserve 18 fifo Locations for DMA buffers */ USBx->GDFIFOCFG &= ~(0xFFFFU << 16); 8005e76: 687b ldr r3, [r7, #4] 8005e78: 6ddb ldr r3, [r3, #92] ; 0x5c 8005e7a: b29a uxth r2, r3 8005e7c: 687b ldr r3, [r7, #4] 8005e7e: 65da str r2, [r3, #92] ; 0x5c USBx->GDFIFOCFG |= 0x3EEU << 16; 8005e80: 687b ldr r3, [r7, #4] 8005e82: 6dda ldr r2, [r3, #92] ; 0x5c 8005e84: 4b0c ldr r3, [pc, #48] ; (8005eb8 ) 8005e86: 4313 orrs r3, r2 8005e88: 687a ldr r2, [r7, #4] 8005e8a: 65d3 str r3, [r2, #92] ; 0x5c USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 8005e8c: 687b ldr r3, [r7, #4] 8005e8e: 689b ldr r3, [r3, #8] 8005e90: f043 0206 orr.w r2, r3, #6 8005e94: 687b ldr r3, [r7, #4] 8005e96: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 8005e98: 687b ldr r3, [r7, #4] 8005e9a: 689b ldr r3, [r3, #8] 8005e9c: f043 0220 orr.w r2, r3, #32 8005ea0: 687b ldr r3, [r7, #4] 8005ea2: 609a str r2, [r3, #8] } return ret; 8005ea4: 7bfb ldrb r3, [r7, #15] } 8005ea6: 4618 mov r0, r3 8005ea8: 3710 adds r7, #16 8005eaa: 46bd mov sp, r7 8005eac: e8bd 4080 ldmia.w sp!, {r7, lr} 8005eb0: b004 add sp, #16 8005eb2: 4770 bx lr 8005eb4: ffbdffbf .word 0xffbdffbf 8005eb8: 03ee0000 .word 0x03ee0000 08005ebc : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 8005ebc: b480 push {r7} 8005ebe: b087 sub sp, #28 8005ec0: af00 add r7, sp, #0 8005ec2: 60f8 str r0, [r7, #12] 8005ec4: 60b9 str r1, [r7, #8] 8005ec6: 4613 mov r3, r2 8005ec8: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 8005eca: 79fb ldrb r3, [r7, #7] 8005ecc: 2b02 cmp r3, #2 8005ece: d165 bne.n 8005f9c { if ((hclk >= 14200000U) && (hclk < 15000000U)) 8005ed0: 68bb ldr r3, [r7, #8] 8005ed2: 4a41 ldr r2, [pc, #260] ; (8005fd8 ) 8005ed4: 4293 cmp r3, r2 8005ed6: d906 bls.n 8005ee6 8005ed8: 68bb ldr r3, [r7, #8] 8005eda: 4a40 ldr r2, [pc, #256] ; (8005fdc ) 8005edc: 4293 cmp r3, r2 8005ede: d202 bcs.n 8005ee6 { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 8005ee0: 230f movs r3, #15 8005ee2: 617b str r3, [r7, #20] 8005ee4: e062 b.n 8005fac } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 8005ee6: 68bb ldr r3, [r7, #8] 8005ee8: 4a3c ldr r2, [pc, #240] ; (8005fdc ) 8005eea: 4293 cmp r3, r2 8005eec: d306 bcc.n 8005efc 8005eee: 68bb ldr r3, [r7, #8] 8005ef0: 4a3b ldr r2, [pc, #236] ; (8005fe0 ) 8005ef2: 4293 cmp r3, r2 8005ef4: d202 bcs.n 8005efc { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 8005ef6: 230e movs r3, #14 8005ef8: 617b str r3, [r7, #20] 8005efa: e057 b.n 8005fac } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 8005efc: 68bb ldr r3, [r7, #8] 8005efe: 4a38 ldr r2, [pc, #224] ; (8005fe0 ) 8005f00: 4293 cmp r3, r2 8005f02: d306 bcc.n 8005f12 8005f04: 68bb ldr r3, [r7, #8] 8005f06: 4a37 ldr r2, [pc, #220] ; (8005fe4 ) 8005f08: 4293 cmp r3, r2 8005f0a: d202 bcs.n 8005f12 { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 8005f0c: 230d movs r3, #13 8005f0e: 617b str r3, [r7, #20] 8005f10: e04c b.n 8005fac } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 8005f12: 68bb ldr r3, [r7, #8] 8005f14: 4a33 ldr r2, [pc, #204] ; (8005fe4 ) 8005f16: 4293 cmp r3, r2 8005f18: d306 bcc.n 8005f28 8005f1a: 68bb ldr r3, [r7, #8] 8005f1c: 4a32 ldr r2, [pc, #200] ; (8005fe8 ) 8005f1e: 4293 cmp r3, r2 8005f20: d802 bhi.n 8005f28 { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 8005f22: 230c movs r3, #12 8005f24: 617b str r3, [r7, #20] 8005f26: e041 b.n 8005fac } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 8005f28: 68bb ldr r3, [r7, #8] 8005f2a: 4a2f ldr r2, [pc, #188] ; (8005fe8 ) 8005f2c: 4293 cmp r3, r2 8005f2e: d906 bls.n 8005f3e 8005f30: 68bb ldr r3, [r7, #8] 8005f32: 4a2e ldr r2, [pc, #184] ; (8005fec ) 8005f34: 4293 cmp r3, r2 8005f36: d802 bhi.n 8005f3e { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 8005f38: 230b movs r3, #11 8005f3a: 617b str r3, [r7, #20] 8005f3c: e036 b.n 8005fac } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 8005f3e: 68bb ldr r3, [r7, #8] 8005f40: 4a2a ldr r2, [pc, #168] ; (8005fec ) 8005f42: 4293 cmp r3, r2 8005f44: d906 bls.n 8005f54 8005f46: 68bb ldr r3, [r7, #8] 8005f48: 4a29 ldr r2, [pc, #164] ; (8005ff0 ) 8005f4a: 4293 cmp r3, r2 8005f4c: d802 bhi.n 8005f54 { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 8005f4e: 230a movs r3, #10 8005f50: 617b str r3, [r7, #20] 8005f52: e02b b.n 8005fac } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 8005f54: 68bb ldr r3, [r7, #8] 8005f56: 4a26 ldr r2, [pc, #152] ; (8005ff0 ) 8005f58: 4293 cmp r3, r2 8005f5a: d906 bls.n 8005f6a 8005f5c: 68bb ldr r3, [r7, #8] 8005f5e: 4a25 ldr r2, [pc, #148] ; (8005ff4 ) 8005f60: 4293 cmp r3, r2 8005f62: d202 bcs.n 8005f6a { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 8005f64: 2309 movs r3, #9 8005f66: 617b str r3, [r7, #20] 8005f68: e020 b.n 8005fac } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 8005f6a: 68bb ldr r3, [r7, #8] 8005f6c: 4a21 ldr r2, [pc, #132] ; (8005ff4 ) 8005f6e: 4293 cmp r3, r2 8005f70: d306 bcc.n 8005f80 8005f72: 68bb ldr r3, [r7, #8] 8005f74: 4a20 ldr r2, [pc, #128] ; (8005ff8 ) 8005f76: 4293 cmp r3, r2 8005f78: d802 bhi.n 8005f80 { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 8005f7a: 2308 movs r3, #8 8005f7c: 617b str r3, [r7, #20] 8005f7e: e015 b.n 8005fac } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 8005f80: 68bb ldr r3, [r7, #8] 8005f82: 4a1d ldr r2, [pc, #116] ; (8005ff8 ) 8005f84: 4293 cmp r3, r2 8005f86: d906 bls.n 8005f96 8005f88: 68bb ldr r3, [r7, #8] 8005f8a: 4a1c ldr r2, [pc, #112] ; (8005ffc ) 8005f8c: 4293 cmp r3, r2 8005f8e: d202 bcs.n 8005f96 { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 8005f90: 2307 movs r3, #7 8005f92: 617b str r3, [r7, #20] 8005f94: e00a b.n 8005fac } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 8005f96: 2306 movs r3, #6 8005f98: 617b str r3, [r7, #20] 8005f9a: e007 b.n 8005fac } } else if (speed == USBD_HS_SPEED) 8005f9c: 79fb ldrb r3, [r7, #7] 8005f9e: 2b00 cmp r3, #0 8005fa0: d102 bne.n 8005fa8 { UsbTrd = USBD_HS_TRDT_VALUE; 8005fa2: 2309 movs r3, #9 8005fa4: 617b str r3, [r7, #20] 8005fa6: e001 b.n 8005fac } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 8005fa8: 2309 movs r3, #9 8005faa: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 8005fac: 68fb ldr r3, [r7, #12] 8005fae: 68db ldr r3, [r3, #12] 8005fb0: f423 5270 bic.w r2, r3, #15360 ; 0x3c00 8005fb4: 68fb ldr r3, [r7, #12] 8005fb6: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 8005fb8: 68fb ldr r3, [r7, #12] 8005fba: 68da ldr r2, [r3, #12] 8005fbc: 697b ldr r3, [r7, #20] 8005fbe: 029b lsls r3, r3, #10 8005fc0: f403 5370 and.w r3, r3, #15360 ; 0x3c00 8005fc4: 431a orrs r2, r3 8005fc6: 68fb ldr r3, [r7, #12] 8005fc8: 60da str r2, [r3, #12] return HAL_OK; 8005fca: 2300 movs r3, #0 } 8005fcc: 4618 mov r0, r3 8005fce: 371c adds r7, #28 8005fd0: 46bd mov sp, r7 8005fd2: f85d 7b04 ldr.w r7, [sp], #4 8005fd6: 4770 bx lr 8005fd8: 00d8acbf .word 0x00d8acbf 8005fdc: 00e4e1c0 .word 0x00e4e1c0 8005fe0: 00f42400 .word 0x00f42400 8005fe4: 01067380 .word 0x01067380 8005fe8: 011a499f .word 0x011a499f 8005fec: 01312cff .word 0x01312cff 8005ff0: 014ca43f .word 0x014ca43f 8005ff4: 016e3600 .word 0x016e3600 8005ff8: 01a6ab1f .word 0x01a6ab1f 8005ffc: 01e84800 .word 0x01e84800 08006000 : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8006000: b480 push {r7} 8006002: b083 sub sp, #12 8006004: af00 add r7, sp, #0 8006006: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 8006008: 687b ldr r3, [r7, #4] 800600a: 689b ldr r3, [r3, #8] 800600c: f043 0201 orr.w r2, r3, #1 8006010: 687b ldr r3, [r7, #4] 8006012: 609a str r2, [r3, #8] return HAL_OK; 8006014: 2300 movs r3, #0 } 8006016: 4618 mov r0, r3 8006018: 370c adds r7, #12 800601a: 46bd mov sp, r7 800601c: f85d 7b04 ldr.w r7, [sp], #4 8006020: 4770 bx lr 08006022 : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8006022: b480 push {r7} 8006024: b083 sub sp, #12 8006026: af00 add r7, sp, #0 8006028: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 800602a: 687b ldr r3, [r7, #4] 800602c: 689b ldr r3, [r3, #8] 800602e: f023 0201 bic.w r2, r3, #1 8006032: 687b ldr r3, [r7, #4] 8006034: 609a str r2, [r3, #8] return HAL_OK; 8006036: 2300 movs r3, #0 } 8006038: 4618 mov r0, r3 800603a: 370c adds r7, #12 800603c: 46bd mov sp, r7 800603e: f85d 7b04 ldr.w r7, [sp], #4 8006042: 4770 bx lr 08006044 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 8006044: b580 push {r7, lr} 8006046: b084 sub sp, #16 8006048: af00 add r7, sp, #0 800604a: 6078 str r0, [r7, #4] 800604c: 460b mov r3, r1 800604e: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 8006050: 2300 movs r3, #0 8006052: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 8006054: 687b ldr r3, [r7, #4] 8006056: 68db ldr r3, [r3, #12] 8006058: f023 42c0 bic.w r2, r3, #1610612736 ; 0x60000000 800605c: 687b ldr r3, [r7, #4] 800605e: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 8006060: 78fb ldrb r3, [r7, #3] 8006062: 2b01 cmp r3, #1 8006064: d115 bne.n 8006092 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 8006066: 687b ldr r3, [r7, #4] 8006068: 68db ldr r3, [r3, #12] 800606a: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000 800606e: 687b ldr r3, [r7, #4] 8006070: 60da str r2, [r3, #12] do { HAL_Delay(1U); 8006072: 2001 movs r0, #1 8006074: f7fb fafc bl 8001670 ms++; 8006078: 68fb ldr r3, [r7, #12] 800607a: 3301 adds r3, #1 800607c: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); 800607e: 6878 ldr r0, [r7, #4] 8006080: f001 f995 bl 80073ae 8006084: 4603 mov r3, r0 8006086: 2b01 cmp r3, #1 8006088: d01e beq.n 80060c8 800608a: 68fb ldr r3, [r7, #12] 800608c: 2b31 cmp r3, #49 ; 0x31 800608e: d9f0 bls.n 8006072 8006090: e01a b.n 80060c8 } else if (mode == USB_DEVICE_MODE) 8006092: 78fb ldrb r3, [r7, #3] 8006094: 2b00 cmp r3, #0 8006096: d115 bne.n 80060c4 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 8006098: 687b ldr r3, [r7, #4] 800609a: 68db ldr r3, [r3, #12] 800609c: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000 80060a0: 687b ldr r3, [r7, #4] 80060a2: 60da str r2, [r3, #12] do { HAL_Delay(1U); 80060a4: 2001 movs r0, #1 80060a6: f7fb fae3 bl 8001670 ms++; 80060aa: 68fb ldr r3, [r7, #12] 80060ac: 3301 adds r3, #1 80060ae: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); 80060b0: 6878 ldr r0, [r7, #4] 80060b2: f001 f97c bl 80073ae 80060b6: 4603 mov r3, r0 80060b8: 2b00 cmp r3, #0 80060ba: d005 beq.n 80060c8 80060bc: 68fb ldr r3, [r7, #12] 80060be: 2b31 cmp r3, #49 ; 0x31 80060c0: d9f0 bls.n 80060a4 80060c2: e001 b.n 80060c8 } else { return HAL_ERROR; 80060c4: 2301 movs r3, #1 80060c6: e005 b.n 80060d4 } if (ms == 50U) 80060c8: 68fb ldr r3, [r7, #12] 80060ca: 2b32 cmp r3, #50 ; 0x32 80060cc: d101 bne.n 80060d2 { return HAL_ERROR; 80060ce: 2301 movs r3, #1 80060d0: e000 b.n 80060d4 } return HAL_OK; 80060d2: 2300 movs r3, #0 } 80060d4: 4618 mov r0, r3 80060d6: 3710 adds r7, #16 80060d8: 46bd mov sp, r7 80060da: bd80 pop {r7, pc} 080060dc : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 80060dc: b084 sub sp, #16 80060de: b580 push {r7, lr} 80060e0: b086 sub sp, #24 80060e2: af00 add r7, sp, #0 80060e4: 6078 str r0, [r7, #4] 80060e6: f107 0024 add.w r0, r7, #36 ; 0x24 80060ea: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 80060ee: 2300 movs r3, #0 80060f0: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 80060f2: 687b ldr r3, [r7, #4] 80060f4: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 80060f6: 2300 movs r3, #0 80060f8: 613b str r3, [r7, #16] 80060fa: e009 b.n 8006110 { USBx->DIEPTXF[i] = 0U; 80060fc: 687a ldr r2, [r7, #4] 80060fe: 693b ldr r3, [r7, #16] 8006100: 3340 adds r3, #64 ; 0x40 8006102: 009b lsls r3, r3, #2 8006104: 4413 add r3, r2 8006106: 2200 movs r2, #0 8006108: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 800610a: 693b ldr r3, [r7, #16] 800610c: 3301 adds r3, #1 800610e: 613b str r3, [r7, #16] 8006110: 693b ldr r3, [r7, #16] 8006112: 2b0e cmp r3, #14 8006114: d9f2 bls.n 80060fc } /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 8006116: 6cfb ldr r3, [r7, #76] ; 0x4c 8006118: 2b00 cmp r3, #0 800611a: d11c bne.n 8006156 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 800611c: 68fb ldr r3, [r7, #12] 800611e: f503 6300 add.w r3, r3, #2048 ; 0x800 8006122: 685b ldr r3, [r3, #4] 8006124: 68fa ldr r2, [r7, #12] 8006126: f502 6200 add.w r2, r2, #2048 ; 0x800 800612a: f043 0302 orr.w r3, r3, #2 800612e: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 8006130: 687b ldr r3, [r7, #4] 8006132: 6b9b ldr r3, [r3, #56] ; 0x38 8006134: f423 1200 bic.w r2, r3, #2097152 ; 0x200000 8006138: 687b ldr r3, [r7, #4] 800613a: 639a str r2, [r3, #56] ; 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 800613c: 687b ldr r3, [r7, #4] 800613e: 681b ldr r3, [r3, #0] 8006140: f043 0240 orr.w r2, r3, #64 ; 0x40 8006144: 687b ldr r3, [r7, #4] 8006146: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 8006148: 687b ldr r3, [r7, #4] 800614a: 681b ldr r3, [r3, #0] 800614c: f043 0280 orr.w r2, r3, #128 ; 0x80 8006150: 687b ldr r3, [r7, #4] 8006152: 601a str r2, [r3, #0] 8006154: e005 b.n 8006162 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 8006156: 687b ldr r3, [r7, #4] 8006158: 6b9b ldr r3, [r3, #56] ; 0x38 800615a: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 800615e: 687b ldr r3, [r7, #4] 8006160: 639a str r2, [r3, #56] ; 0x38 } /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 8006162: 68fb ldr r3, [r7, #12] 8006164: f503 6360 add.w r3, r3, #3584 ; 0xe00 8006168: 461a mov r2, r3 800616a: 2300 movs r3, #0 800616c: 6013 str r3, [r2, #0] /* Device mode configuration */ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; 800616e: 68fb ldr r3, [r7, #12] 8006170: f503 6300 add.w r3, r3, #2048 ; 0x800 8006174: 4619 mov r1, r3 8006176: 68fb ldr r3, [r7, #12] 8006178: f503 6300 add.w r3, r3, #2048 ; 0x800 800617c: 461a mov r2, r3 800617e: 680b ldr r3, [r1, #0] 8006180: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8006182: 6bbb ldr r3, [r7, #56] ; 0x38 8006184: 2b01 cmp r3, #1 8006186: d10c bne.n 80061a2 { if (cfg.speed == USBD_HS_SPEED) 8006188: 6afb ldr r3, [r7, #44] ; 0x2c 800618a: 2b00 cmp r3, #0 800618c: d104 bne.n 8006198 { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 800618e: 2100 movs r1, #0 8006190: 6878 ldr r0, [r7, #4] 8006192: f000 f961 bl 8006458 8006196: e008 b.n 80061aa } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 8006198: 2101 movs r1, #1 800619a: 6878 ldr r0, [r7, #4] 800619c: f000 f95c bl 8006458 80061a0: e003 b.n 80061aa } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 80061a2: 2103 movs r1, #3 80061a4: 6878 ldr r0, [r7, #4] 80061a6: f000 f957 bl 8006458 } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 80061aa: 2110 movs r1, #16 80061ac: 6878 ldr r0, [r7, #4] 80061ae: f000 f8f3 bl 8006398 80061b2: 4603 mov r3, r0 80061b4: 2b00 cmp r3, #0 80061b6: d001 beq.n 80061bc { ret = HAL_ERROR; 80061b8: 2301 movs r3, #1 80061ba: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 80061bc: 6878 ldr r0, [r7, #4] 80061be: f000 f91d bl 80063fc 80061c2: 4603 mov r3, r0 80061c4: 2b00 cmp r3, #0 80061c6: d001 beq.n 80061cc { ret = HAL_ERROR; 80061c8: 2301 movs r3, #1 80061ca: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 80061cc: 68fb ldr r3, [r7, #12] 80061ce: f503 6300 add.w r3, r3, #2048 ; 0x800 80061d2: 461a mov r2, r3 80061d4: 2300 movs r3, #0 80061d6: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 80061d8: 68fb ldr r3, [r7, #12] 80061da: f503 6300 add.w r3, r3, #2048 ; 0x800 80061de: 461a mov r2, r3 80061e0: 2300 movs r3, #0 80061e2: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 80061e4: 68fb ldr r3, [r7, #12] 80061e6: f503 6300 add.w r3, r3, #2048 ; 0x800 80061ea: 461a mov r2, r3 80061ec: 2300 movs r3, #0 80061ee: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 80061f0: 2300 movs r3, #0 80061f2: 613b str r3, [r7, #16] 80061f4: e043 b.n 800627e { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 80061f6: 693b ldr r3, [r7, #16] 80061f8: 015a lsls r2, r3, #5 80061fa: 68fb ldr r3, [r7, #12] 80061fc: 4413 add r3, r2 80061fe: f503 6310 add.w r3, r3, #2304 ; 0x900 8006202: 681b ldr r3, [r3, #0] 8006204: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8006208: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 800620c: d118 bne.n 8006240 { if (i == 0U) 800620e: 693b ldr r3, [r7, #16] 8006210: 2b00 cmp r3, #0 8006212: d10a bne.n 800622a { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 8006214: 693b ldr r3, [r7, #16] 8006216: 015a lsls r2, r3, #5 8006218: 68fb ldr r3, [r7, #12] 800621a: 4413 add r3, r2 800621c: f503 6310 add.w r3, r3, #2304 ; 0x900 8006220: 461a mov r2, r3 8006222: f04f 6300 mov.w r3, #134217728 ; 0x8000000 8006226: 6013 str r3, [r2, #0] 8006228: e013 b.n 8006252 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 800622a: 693b ldr r3, [r7, #16] 800622c: 015a lsls r2, r3, #5 800622e: 68fb ldr r3, [r7, #12] 8006230: 4413 add r3, r2 8006232: f503 6310 add.w r3, r3, #2304 ; 0x900 8006236: 461a mov r2, r3 8006238: f04f 4390 mov.w r3, #1207959552 ; 0x48000000 800623c: 6013 str r3, [r2, #0] 800623e: e008 b.n 8006252 } } else { USBx_INEP(i)->DIEPCTL = 0U; 8006240: 693b ldr r3, [r7, #16] 8006242: 015a lsls r2, r3, #5 8006244: 68fb ldr r3, [r7, #12] 8006246: 4413 add r3, r2 8006248: f503 6310 add.w r3, r3, #2304 ; 0x900 800624c: 461a mov r2, r3 800624e: 2300 movs r3, #0 8006250: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 8006252: 693b ldr r3, [r7, #16] 8006254: 015a lsls r2, r3, #5 8006256: 68fb ldr r3, [r7, #12] 8006258: 4413 add r3, r2 800625a: f503 6310 add.w r3, r3, #2304 ; 0x900 800625e: 461a mov r2, r3 8006260: 2300 movs r3, #0 8006262: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 8006264: 693b ldr r3, [r7, #16] 8006266: 015a lsls r2, r3, #5 8006268: 68fb ldr r3, [r7, #12] 800626a: 4413 add r3, r2 800626c: f503 6310 add.w r3, r3, #2304 ; 0x900 8006270: 461a mov r2, r3 8006272: f64f 337f movw r3, #64383 ; 0xfb7f 8006276: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8006278: 693b ldr r3, [r7, #16] 800627a: 3301 adds r3, #1 800627c: 613b str r3, [r7, #16] 800627e: 6a7b ldr r3, [r7, #36] ; 0x24 8006280: 693a ldr r2, [r7, #16] 8006282: 429a cmp r2, r3 8006284: d3b7 bcc.n 80061f6 } for (i = 0U; i < cfg.dev_endpoints; i++) 8006286: 2300 movs r3, #0 8006288: 613b str r3, [r7, #16] 800628a: e043 b.n 8006314 { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 800628c: 693b ldr r3, [r7, #16] 800628e: 015a lsls r2, r3, #5 8006290: 68fb ldr r3, [r7, #12] 8006292: 4413 add r3, r2 8006294: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006298: 681b ldr r3, [r3, #0] 800629a: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 800629e: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 80062a2: d118 bne.n 80062d6 { if (i == 0U) 80062a4: 693b ldr r3, [r7, #16] 80062a6: 2b00 cmp r3, #0 80062a8: d10a bne.n 80062c0 { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 80062aa: 693b ldr r3, [r7, #16] 80062ac: 015a lsls r2, r3, #5 80062ae: 68fb ldr r3, [r7, #12] 80062b0: 4413 add r3, r2 80062b2: f503 6330 add.w r3, r3, #2816 ; 0xb00 80062b6: 461a mov r2, r3 80062b8: f04f 6300 mov.w r3, #134217728 ; 0x8000000 80062bc: 6013 str r3, [r2, #0] 80062be: e013 b.n 80062e8 } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 80062c0: 693b ldr r3, [r7, #16] 80062c2: 015a lsls r2, r3, #5 80062c4: 68fb ldr r3, [r7, #12] 80062c6: 4413 add r3, r2 80062c8: f503 6330 add.w r3, r3, #2816 ; 0xb00 80062cc: 461a mov r2, r3 80062ce: f04f 4390 mov.w r3, #1207959552 ; 0x48000000 80062d2: 6013 str r3, [r2, #0] 80062d4: e008 b.n 80062e8 } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 80062d6: 693b ldr r3, [r7, #16] 80062d8: 015a lsls r2, r3, #5 80062da: 68fb ldr r3, [r7, #12] 80062dc: 4413 add r3, r2 80062de: f503 6330 add.w r3, r3, #2816 ; 0xb00 80062e2: 461a mov r2, r3 80062e4: 2300 movs r3, #0 80062e6: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 80062e8: 693b ldr r3, [r7, #16] 80062ea: 015a lsls r2, r3, #5 80062ec: 68fb ldr r3, [r7, #12] 80062ee: 4413 add r3, r2 80062f0: f503 6330 add.w r3, r3, #2816 ; 0xb00 80062f4: 461a mov r2, r3 80062f6: 2300 movs r3, #0 80062f8: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 80062fa: 693b ldr r3, [r7, #16] 80062fc: 015a lsls r2, r3, #5 80062fe: 68fb ldr r3, [r7, #12] 8006300: 4413 add r3, r2 8006302: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006306: 461a mov r2, r3 8006308: f64f 337f movw r3, #64383 ; 0xfb7f 800630c: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 800630e: 693b ldr r3, [r7, #16] 8006310: 3301 adds r3, #1 8006312: 613b str r3, [r7, #16] 8006314: 6a7b ldr r3, [r7, #36] ; 0x24 8006316: 693a ldr r2, [r7, #16] 8006318: 429a cmp r2, r3 800631a: d3b7 bcc.n 800628c } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 800631c: 68fb ldr r3, [r7, #12] 800631e: f503 6300 add.w r3, r3, #2048 ; 0x800 8006322: 691b ldr r3, [r3, #16] 8006324: 68fa ldr r2, [r7, #12] 8006326: f502 6200 add.w r2, r2, #2048 ; 0x800 800632a: f423 7380 bic.w r3, r3, #256 ; 0x100 800632e: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 8006330: 687b ldr r3, [r7, #4] 8006332: 2200 movs r2, #0 8006334: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 8006336: 687b ldr r3, [r7, #4] 8006338: f06f 4280 mvn.w r2, #1073741824 ; 0x40000000 800633c: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 800633e: 6b3b ldr r3, [r7, #48] ; 0x30 8006340: 2b00 cmp r3, #0 8006342: d105 bne.n 8006350 { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 8006344: 687b ldr r3, [r7, #4] 8006346: 699b ldr r3, [r3, #24] 8006348: f043 0210 orr.w r2, r3, #16 800634c: 687b ldr r3, [r7, #4] 800634e: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 8006350: 687b ldr r3, [r7, #4] 8006352: 699a ldr r2, [r3, #24] 8006354: 4b0e ldr r3, [pc, #56] ; (8006390 ) 8006356: 4313 orrs r3, r2 8006358: 687a ldr r2, [r7, #4] 800635a: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 800635c: 6bfb ldr r3, [r7, #60] ; 0x3c 800635e: 2b00 cmp r3, #0 8006360: d005 beq.n 800636e { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 8006362: 687b ldr r3, [r7, #4] 8006364: 699b ldr r3, [r3, #24] 8006366: f043 0208 orr.w r2, r3, #8 800636a: 687b ldr r3, [r7, #4] 800636c: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 800636e: 6cfb ldr r3, [r7, #76] ; 0x4c 8006370: 2b01 cmp r3, #1 8006372: d105 bne.n 8006380 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 8006374: 687b ldr r3, [r7, #4] 8006376: 699a ldr r2, [r3, #24] 8006378: 4b06 ldr r3, [pc, #24] ; (8006394 ) 800637a: 4313 orrs r3, r2 800637c: 687a ldr r2, [r7, #4] 800637e: 6193 str r3, [r2, #24] } return ret; 8006380: 7dfb ldrb r3, [r7, #23] } 8006382: 4618 mov r0, r3 8006384: 3718 adds r7, #24 8006386: 46bd mov sp, r7 8006388: e8bd 4080 ldmia.w sp!, {r7, lr} 800638c: b004 add sp, #16 800638e: 4770 bx lr 8006390: 803c3800 .word 0x803c3800 8006394: 40000004 .word 0x40000004 08006398 : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 8006398: b480 push {r7} 800639a: b085 sub sp, #20 800639c: af00 add r7, sp, #0 800639e: 6078 str r0, [r7, #4] 80063a0: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 80063a2: 2300 movs r3, #0 80063a4: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { if (++count > 200000U) 80063a6: 68fb ldr r3, [r7, #12] 80063a8: 3301 adds r3, #1 80063aa: 60fb str r3, [r7, #12] 80063ac: 4a12 ldr r2, [pc, #72] ; (80063f8 ) 80063ae: 4293 cmp r3, r2 80063b0: d901 bls.n 80063b6 { return HAL_TIMEOUT; 80063b2: 2303 movs r3, #3 80063b4: e01a b.n 80063ec } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80063b6: 687b ldr r3, [r7, #4] 80063b8: 691b ldr r3, [r3, #16] 80063ba: 2b00 cmp r3, #0 80063bc: daf3 bge.n 80063a6 /* Flush TX Fifo */ count = 0U; 80063be: 2300 movs r3, #0 80063c0: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 80063c2: 683b ldr r3, [r7, #0] 80063c4: 019b lsls r3, r3, #6 80063c6: f043 0220 orr.w r2, r3, #32 80063ca: 687b ldr r3, [r7, #4] 80063cc: 611a str r2, [r3, #16] do { if (++count > 200000U) 80063ce: 68fb ldr r3, [r7, #12] 80063d0: 3301 adds r3, #1 80063d2: 60fb str r3, [r7, #12] 80063d4: 4a08 ldr r2, [pc, #32] ; (80063f8 ) 80063d6: 4293 cmp r3, r2 80063d8: d901 bls.n 80063de { return HAL_TIMEOUT; 80063da: 2303 movs r3, #3 80063dc: e006 b.n 80063ec } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 80063de: 687b ldr r3, [r7, #4] 80063e0: 691b ldr r3, [r3, #16] 80063e2: f003 0320 and.w r3, r3, #32 80063e6: 2b20 cmp r3, #32 80063e8: d0f1 beq.n 80063ce return HAL_OK; 80063ea: 2300 movs r3, #0 } 80063ec: 4618 mov r0, r3 80063ee: 3714 adds r7, #20 80063f0: 46bd mov sp, r7 80063f2: f85d 7b04 ldr.w r7, [sp], #4 80063f6: 4770 bx lr 80063f8: 00030d40 .word 0x00030d40 080063fc : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 80063fc: b480 push {r7} 80063fe: b085 sub sp, #20 8006400: af00 add r7, sp, #0 8006402: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8006404: 2300 movs r3, #0 8006406: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { if (++count > 200000U) 8006408: 68fb ldr r3, [r7, #12] 800640a: 3301 adds r3, #1 800640c: 60fb str r3, [r7, #12] 800640e: 4a11 ldr r2, [pc, #68] ; (8006454 ) 8006410: 4293 cmp r3, r2 8006412: d901 bls.n 8006418 { return HAL_TIMEOUT; 8006414: 2303 movs r3, #3 8006416: e017 b.n 8006448 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8006418: 687b ldr r3, [r7, #4] 800641a: 691b ldr r3, [r3, #16] 800641c: 2b00 cmp r3, #0 800641e: daf3 bge.n 8006408 /* Flush RX Fifo */ count = 0U; 8006420: 2300 movs r3, #0 8006422: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 8006424: 687b ldr r3, [r7, #4] 8006426: 2210 movs r2, #16 8006428: 611a str r2, [r3, #16] do { if (++count > 200000U) 800642a: 68fb ldr r3, [r7, #12] 800642c: 3301 adds r3, #1 800642e: 60fb str r3, [r7, #12] 8006430: 4a08 ldr r2, [pc, #32] ; (8006454 ) 8006432: 4293 cmp r3, r2 8006434: d901 bls.n 800643a { return HAL_TIMEOUT; 8006436: 2303 movs r3, #3 8006438: e006 b.n 8006448 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 800643a: 687b ldr r3, [r7, #4] 800643c: 691b ldr r3, [r3, #16] 800643e: f003 0310 and.w r3, r3, #16 8006442: 2b10 cmp r3, #16 8006444: d0f1 beq.n 800642a return HAL_OK; 8006446: 2300 movs r3, #0 } 8006448: 4618 mov r0, r3 800644a: 3714 adds r7, #20 800644c: 46bd mov sp, r7 800644e: f85d 7b04 ldr.w r7, [sp], #4 8006452: 4770 bx lr 8006454: 00030d40 .word 0x00030d40 08006458 : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 8006458: b480 push {r7} 800645a: b085 sub sp, #20 800645c: af00 add r7, sp, #0 800645e: 6078 str r0, [r7, #4] 8006460: 460b mov r3, r1 8006462: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8006464: 687b ldr r3, [r7, #4] 8006466: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 8006468: 68fb ldr r3, [r7, #12] 800646a: f503 6300 add.w r3, r3, #2048 ; 0x800 800646e: 681a ldr r2, [r3, #0] 8006470: 78fb ldrb r3, [r7, #3] 8006472: 68f9 ldr r1, [r7, #12] 8006474: f501 6100 add.w r1, r1, #2048 ; 0x800 8006478: 4313 orrs r3, r2 800647a: 600b str r3, [r1, #0] return HAL_OK; 800647c: 2300 movs r3, #0 } 800647e: 4618 mov r0, r3 8006480: 3714 adds r7, #20 8006482: 46bd mov sp, r7 8006484: f85d 7b04 ldr.w r7, [sp], #4 8006488: 4770 bx lr 0800648a : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { 800648a: b480 push {r7} 800648c: b087 sub sp, #28 800648e: af00 add r7, sp, #0 8006490: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8006492: 687b ldr r3, [r7, #4] 8006494: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 8006496: 693b ldr r3, [r7, #16] 8006498: f503 6300 add.w r3, r3, #2048 ; 0x800 800649c: 689b ldr r3, [r3, #8] 800649e: f003 0306 and.w r3, r3, #6 80064a2: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 80064a4: 68fb ldr r3, [r7, #12] 80064a6: 2b00 cmp r3, #0 80064a8: d102 bne.n 80064b0 { speed = USBD_HS_SPEED; 80064aa: 2300 movs r3, #0 80064ac: 75fb strb r3, [r7, #23] 80064ae: e00a b.n 80064c6 } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 80064b0: 68fb ldr r3, [r7, #12] 80064b2: 2b02 cmp r3, #2 80064b4: d002 beq.n 80064bc 80064b6: 68fb ldr r3, [r7, #12] 80064b8: 2b06 cmp r3, #6 80064ba: d102 bne.n 80064c2 (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 80064bc: 2302 movs r3, #2 80064be: 75fb strb r3, [r7, #23] 80064c0: e001 b.n 80064c6 } else { speed = 0xFU; 80064c2: 230f movs r3, #15 80064c4: 75fb strb r3, [r7, #23] } return speed; 80064c6: 7dfb ldrb r3, [r7, #23] } 80064c8: 4618 mov r0, r3 80064ca: 371c adds r7, #28 80064cc: 46bd mov sp, r7 80064ce: f85d 7b04 ldr.w r7, [sp], #4 80064d2: 4770 bx lr 080064d4 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 80064d4: b480 push {r7} 80064d6: b085 sub sp, #20 80064d8: af00 add r7, sp, #0 80064da: 6078 str r0, [r7, #4] 80064dc: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80064de: 687b ldr r3, [r7, #4] 80064e0: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80064e2: 683b ldr r3, [r7, #0] 80064e4: 781b ldrb r3, [r3, #0] 80064e6: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 80064e8: 683b ldr r3, [r7, #0] 80064ea: 785b ldrb r3, [r3, #1] 80064ec: 2b01 cmp r3, #1 80064ee: d139 bne.n 8006564 { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 80064f0: 68fb ldr r3, [r7, #12] 80064f2: f503 6300 add.w r3, r3, #2048 ; 0x800 80064f6: 69da ldr r2, [r3, #28] 80064f8: 683b ldr r3, [r7, #0] 80064fa: 781b ldrb r3, [r3, #0] 80064fc: f003 030f and.w r3, r3, #15 8006500: 2101 movs r1, #1 8006502: fa01 f303 lsl.w r3, r1, r3 8006506: b29b uxth r3, r3 8006508: 68f9 ldr r1, [r7, #12] 800650a: f501 6100 add.w r1, r1, #2048 ; 0x800 800650e: 4313 orrs r3, r2 8006510: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 8006512: 68bb ldr r3, [r7, #8] 8006514: 015a lsls r2, r3, #5 8006516: 68fb ldr r3, [r7, #12] 8006518: 4413 add r3, r2 800651a: f503 6310 add.w r3, r3, #2304 ; 0x900 800651e: 681b ldr r3, [r3, #0] 8006520: f403 4300 and.w r3, r3, #32768 ; 0x8000 8006524: 2b00 cmp r3, #0 8006526: d153 bne.n 80065d0 { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8006528: 68bb ldr r3, [r7, #8] 800652a: 015a lsls r2, r3, #5 800652c: 68fb ldr r3, [r7, #12] 800652e: 4413 add r3, r2 8006530: f503 6310 add.w r3, r3, #2304 ; 0x900 8006534: 681a ldr r2, [r3, #0] 8006536: 683b ldr r3, [r7, #0] 8006538: 689b ldr r3, [r3, #8] 800653a: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 800653e: 683b ldr r3, [r7, #0] 8006540: 78db ldrb r3, [r3, #3] 8006542: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8006544: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 8006546: 68bb ldr r3, [r7, #8] 8006548: 059b lsls r3, r3, #22 800654a: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 800654c: 431a orrs r2, r3 800654e: 68bb ldr r3, [r7, #8] 8006550: 0159 lsls r1, r3, #5 8006552: 68fb ldr r3, [r7, #12] 8006554: 440b add r3, r1 8006556: f503 6310 add.w r3, r3, #2304 ; 0x900 800655a: 4619 mov r1, r3 800655c: 4b20 ldr r3, [pc, #128] ; (80065e0 ) 800655e: 4313 orrs r3, r2 8006560: 600b str r3, [r1, #0] 8006562: e035 b.n 80065d0 USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 8006564: 68fb ldr r3, [r7, #12] 8006566: f503 6300 add.w r3, r3, #2048 ; 0x800 800656a: 69da ldr r2, [r3, #28] 800656c: 683b ldr r3, [r7, #0] 800656e: 781b ldrb r3, [r3, #0] 8006570: f003 030f and.w r3, r3, #15 8006574: 2101 movs r1, #1 8006576: fa01 f303 lsl.w r3, r1, r3 800657a: 041b lsls r3, r3, #16 800657c: 68f9 ldr r1, [r7, #12] 800657e: f501 6100 add.w r1, r1, #2048 ; 0x800 8006582: 4313 orrs r3, r2 8006584: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 8006586: 68bb ldr r3, [r7, #8] 8006588: 015a lsls r2, r3, #5 800658a: 68fb ldr r3, [r7, #12] 800658c: 4413 add r3, r2 800658e: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006592: 681b ldr r3, [r3, #0] 8006594: f403 4300 and.w r3, r3, #32768 ; 0x8000 8006598: 2b00 cmp r3, #0 800659a: d119 bne.n 80065d0 { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 800659c: 68bb ldr r3, [r7, #8] 800659e: 015a lsls r2, r3, #5 80065a0: 68fb ldr r3, [r7, #12] 80065a2: 4413 add r3, r2 80065a4: f503 6330 add.w r3, r3, #2816 ; 0xb00 80065a8: 681a ldr r2, [r3, #0] 80065aa: 683b ldr r3, [r7, #0] 80065ac: 689b ldr r3, [r3, #8] 80065ae: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 80065b2: 683b ldr r3, [r7, #0] 80065b4: 78db ldrb r3, [r3, #3] 80065b6: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 80065b8: 430b orrs r3, r1 80065ba: 431a orrs r2, r3 80065bc: 68bb ldr r3, [r7, #8] 80065be: 0159 lsls r1, r3, #5 80065c0: 68fb ldr r3, [r7, #12] 80065c2: 440b add r3, r1 80065c4: f503 6330 add.w r3, r3, #2816 ; 0xb00 80065c8: 4619 mov r1, r3 80065ca: 4b05 ldr r3, [pc, #20] ; (80065e0 ) 80065cc: 4313 orrs r3, r2 80065ce: 600b str r3, [r1, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 80065d0: 2300 movs r3, #0 } 80065d2: 4618 mov r0, r3 80065d4: 3714 adds r7, #20 80065d6: 46bd mov sp, r7 80065d8: f85d 7b04 ldr.w r7, [sp], #4 80065dc: 4770 bx lr 80065de: bf00 nop 80065e0: 10008000 .word 0x10008000 080065e4 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 80065e4: b480 push {r7} 80065e6: b085 sub sp, #20 80065e8: af00 add r7, sp, #0 80065ea: 6078 str r0, [r7, #4] 80065ec: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80065ee: 687b ldr r3, [r7, #4] 80065f0: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80065f2: 683b ldr r3, [r7, #0] 80065f4: 781b ldrb r3, [r3, #0] 80065f6: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 80065f8: 683b ldr r3, [r7, #0] 80065fa: 785b ldrb r3, [r3, #1] 80065fc: 2b01 cmp r3, #1 80065fe: d161 bne.n 80066c4 { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8006600: 68bb ldr r3, [r7, #8] 8006602: 015a lsls r2, r3, #5 8006604: 68fb ldr r3, [r7, #12] 8006606: 4413 add r3, r2 8006608: f503 6310 add.w r3, r3, #2304 ; 0x900 800660c: 681b ldr r3, [r3, #0] 800660e: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8006612: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8006616: d11f bne.n 8006658 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 8006618: 68bb ldr r3, [r7, #8] 800661a: 015a lsls r2, r3, #5 800661c: 68fb ldr r3, [r7, #12] 800661e: 4413 add r3, r2 8006620: f503 6310 add.w r3, r3, #2304 ; 0x900 8006624: 681b ldr r3, [r3, #0] 8006626: 68ba ldr r2, [r7, #8] 8006628: 0151 lsls r1, r2, #5 800662a: 68fa ldr r2, [r7, #12] 800662c: 440a add r2, r1 800662e: f502 6210 add.w r2, r2, #2304 ; 0x900 8006632: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 8006636: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 8006638: 68bb ldr r3, [r7, #8] 800663a: 015a lsls r2, r3, #5 800663c: 68fb ldr r3, [r7, #12] 800663e: 4413 add r3, r2 8006640: f503 6310 add.w r3, r3, #2304 ; 0x900 8006644: 681b ldr r3, [r3, #0] 8006646: 68ba ldr r2, [r7, #8] 8006648: 0151 lsls r1, r2, #5 800664a: 68fa ldr r2, [r7, #12] 800664c: 440a add r2, r1 800664e: f502 6210 add.w r2, r2, #2304 ; 0x900 8006652: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 8006656: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 8006658: 68fb ldr r3, [r7, #12] 800665a: f503 6300 add.w r3, r3, #2048 ; 0x800 800665e: 6bda ldr r2, [r3, #60] ; 0x3c 8006660: 683b ldr r3, [r7, #0] 8006662: 781b ldrb r3, [r3, #0] 8006664: f003 030f and.w r3, r3, #15 8006668: 2101 movs r1, #1 800666a: fa01 f303 lsl.w r3, r1, r3 800666e: b29b uxth r3, r3 8006670: 43db mvns r3, r3 8006672: 68f9 ldr r1, [r7, #12] 8006674: f501 6100 add.w r1, r1, #2048 ; 0x800 8006678: 4013 ands r3, r2 800667a: 63cb str r3, [r1, #60] ; 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 800667c: 68fb ldr r3, [r7, #12] 800667e: f503 6300 add.w r3, r3, #2048 ; 0x800 8006682: 69da ldr r2, [r3, #28] 8006684: 683b ldr r3, [r7, #0] 8006686: 781b ldrb r3, [r3, #0] 8006688: f003 030f and.w r3, r3, #15 800668c: 2101 movs r1, #1 800668e: fa01 f303 lsl.w r3, r1, r3 8006692: b29b uxth r3, r3 8006694: 43db mvns r3, r3 8006696: 68f9 ldr r1, [r7, #12] 8006698: f501 6100 add.w r1, r1, #2048 ; 0x800 800669c: 4013 ands r3, r2 800669e: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 80066a0: 68bb ldr r3, [r7, #8] 80066a2: 015a lsls r2, r3, #5 80066a4: 68fb ldr r3, [r7, #12] 80066a6: 4413 add r3, r2 80066a8: f503 6310 add.w r3, r3, #2304 ; 0x900 80066ac: 681a ldr r2, [r3, #0] 80066ae: 68bb ldr r3, [r7, #8] 80066b0: 0159 lsls r1, r3, #5 80066b2: 68fb ldr r3, [r7, #12] 80066b4: 440b add r3, r1 80066b6: f503 6310 add.w r3, r3, #2304 ; 0x900 80066ba: 4619 mov r1, r3 80066bc: 4b35 ldr r3, [pc, #212] ; (8006794 ) 80066be: 4013 ands r3, r2 80066c0: 600b str r3, [r1, #0] 80066c2: e060 b.n 8006786 USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80066c4: 68bb ldr r3, [r7, #8] 80066c6: 015a lsls r2, r3, #5 80066c8: 68fb ldr r3, [r7, #12] 80066ca: 4413 add r3, r2 80066cc: f503 6330 add.w r3, r3, #2816 ; 0xb00 80066d0: 681b ldr r3, [r3, #0] 80066d2: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 80066d6: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 80066da: d11f bne.n 800671c { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 80066dc: 68bb ldr r3, [r7, #8] 80066de: 015a lsls r2, r3, #5 80066e0: 68fb ldr r3, [r7, #12] 80066e2: 4413 add r3, r2 80066e4: f503 6330 add.w r3, r3, #2816 ; 0xb00 80066e8: 681b ldr r3, [r3, #0] 80066ea: 68ba ldr r2, [r7, #8] 80066ec: 0151 lsls r1, r2, #5 80066ee: 68fa ldr r2, [r7, #12] 80066f0: 440a add r2, r1 80066f2: f502 6230 add.w r2, r2, #2816 ; 0xb00 80066f6: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 80066fa: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 80066fc: 68bb ldr r3, [r7, #8] 80066fe: 015a lsls r2, r3, #5 8006700: 68fb ldr r3, [r7, #12] 8006702: 4413 add r3, r2 8006704: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006708: 681b ldr r3, [r3, #0] 800670a: 68ba ldr r2, [r7, #8] 800670c: 0151 lsls r1, r2, #5 800670e: 68fa ldr r2, [r7, #12] 8006710: 440a add r2, r1 8006712: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006716: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 800671a: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 800671c: 68fb ldr r3, [r7, #12] 800671e: f503 6300 add.w r3, r3, #2048 ; 0x800 8006722: 6bda ldr r2, [r3, #60] ; 0x3c 8006724: 683b ldr r3, [r7, #0] 8006726: 781b ldrb r3, [r3, #0] 8006728: f003 030f and.w r3, r3, #15 800672c: 2101 movs r1, #1 800672e: fa01 f303 lsl.w r3, r1, r3 8006732: 041b lsls r3, r3, #16 8006734: 43db mvns r3, r3 8006736: 68f9 ldr r1, [r7, #12] 8006738: f501 6100 add.w r1, r1, #2048 ; 0x800 800673c: 4013 ands r3, r2 800673e: 63cb str r3, [r1, #60] ; 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 8006740: 68fb ldr r3, [r7, #12] 8006742: f503 6300 add.w r3, r3, #2048 ; 0x800 8006746: 69da ldr r2, [r3, #28] 8006748: 683b ldr r3, [r7, #0] 800674a: 781b ldrb r3, [r3, #0] 800674c: f003 030f and.w r3, r3, #15 8006750: 2101 movs r1, #1 8006752: fa01 f303 lsl.w r3, r1, r3 8006756: 041b lsls r3, r3, #16 8006758: 43db mvns r3, r3 800675a: 68f9 ldr r1, [r7, #12] 800675c: f501 6100 add.w r1, r1, #2048 ; 0x800 8006760: 4013 ands r3, r2 8006762: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 8006764: 68bb ldr r3, [r7, #8] 8006766: 015a lsls r2, r3, #5 8006768: 68fb ldr r3, [r7, #12] 800676a: 4413 add r3, r2 800676c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006770: 681a ldr r2, [r3, #0] 8006772: 68bb ldr r3, [r7, #8] 8006774: 0159 lsls r1, r3, #5 8006776: 68fb ldr r3, [r7, #12] 8006778: 440b add r3, r1 800677a: f503 6330 add.w r3, r3, #2816 ; 0xb00 800677e: 4619 mov r1, r3 8006780: 4b05 ldr r3, [pc, #20] ; (8006798 ) 8006782: 4013 ands r3, r2 8006784: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 8006786: 2300 movs r3, #0 } 8006788: 4618 mov r0, r3 800678a: 3714 adds r7, #20 800678c: 46bd mov sp, r7 800678e: f85d 7b04 ldr.w r7, [sp], #4 8006792: 4770 bx lr 8006794: ec337800 .word 0xec337800 8006798: eff37800 .word 0xeff37800 0800679c : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 800679c: b580 push {r7, lr} 800679e: b08a sub sp, #40 ; 0x28 80067a0: af02 add r7, sp, #8 80067a2: 60f8 str r0, [r7, #12] 80067a4: 60b9 str r1, [r7, #8] 80067a6: 4613 mov r3, r2 80067a8: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 80067aa: 68fb ldr r3, [r7, #12] 80067ac: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 80067ae: 68bb ldr r3, [r7, #8] 80067b0: 781b ldrb r3, [r3, #0] 80067b2: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 80067b4: 68bb ldr r3, [r7, #8] 80067b6: 785b ldrb r3, [r3, #1] 80067b8: 2b01 cmp r3, #1 80067ba: f040 8163 bne.w 8006a84 { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 80067be: 68bb ldr r3, [r7, #8] 80067c0: 695b ldr r3, [r3, #20] 80067c2: 2b00 cmp r3, #0 80067c4: d132 bne.n 800682c { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 80067c6: 69bb ldr r3, [r7, #24] 80067c8: 015a lsls r2, r3, #5 80067ca: 69fb ldr r3, [r7, #28] 80067cc: 4413 add r3, r2 80067ce: f503 6310 add.w r3, r3, #2304 ; 0x900 80067d2: 691a ldr r2, [r3, #16] 80067d4: 69bb ldr r3, [r7, #24] 80067d6: 0159 lsls r1, r3, #5 80067d8: 69fb ldr r3, [r7, #28] 80067da: 440b add r3, r1 80067dc: f503 6310 add.w r3, r3, #2304 ; 0x900 80067e0: 4619 mov r1, r3 80067e2: 4ba5 ldr r3, [pc, #660] ; (8006a78 ) 80067e4: 4013 ands r3, r2 80067e6: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 80067e8: 69bb ldr r3, [r7, #24] 80067ea: 015a lsls r2, r3, #5 80067ec: 69fb ldr r3, [r7, #28] 80067ee: 4413 add r3, r2 80067f0: f503 6310 add.w r3, r3, #2304 ; 0x900 80067f4: 691b ldr r3, [r3, #16] 80067f6: 69ba ldr r2, [r7, #24] 80067f8: 0151 lsls r1, r2, #5 80067fa: 69fa ldr r2, [r7, #28] 80067fc: 440a add r2, r1 80067fe: f502 6210 add.w r2, r2, #2304 ; 0x900 8006802: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006806: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8006808: 69bb ldr r3, [r7, #24] 800680a: 015a lsls r2, r3, #5 800680c: 69fb ldr r3, [r7, #28] 800680e: 4413 add r3, r2 8006810: f503 6310 add.w r3, r3, #2304 ; 0x900 8006814: 691a ldr r2, [r3, #16] 8006816: 69bb ldr r3, [r7, #24] 8006818: 0159 lsls r1, r3, #5 800681a: 69fb ldr r3, [r7, #28] 800681c: 440b add r3, r1 800681e: f503 6310 add.w r3, r3, #2304 ; 0x900 8006822: 4619 mov r1, r3 8006824: 4b95 ldr r3, [pc, #596] ; (8006a7c ) 8006826: 4013 ands r3, r2 8006828: 610b str r3, [r1, #16] 800682a: e074 b.n 8006916 /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 800682c: 69bb ldr r3, [r7, #24] 800682e: 015a lsls r2, r3, #5 8006830: 69fb ldr r3, [r7, #28] 8006832: 4413 add r3, r2 8006834: f503 6310 add.w r3, r3, #2304 ; 0x900 8006838: 691a ldr r2, [r3, #16] 800683a: 69bb ldr r3, [r7, #24] 800683c: 0159 lsls r1, r3, #5 800683e: 69fb ldr r3, [r7, #28] 8006840: 440b add r3, r1 8006842: f503 6310 add.w r3, r3, #2304 ; 0x900 8006846: 4619 mov r1, r3 8006848: 4b8c ldr r3, [pc, #560] ; (8006a7c ) 800684a: 4013 ands r3, r2 800684c: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 800684e: 69bb ldr r3, [r7, #24] 8006850: 015a lsls r2, r3, #5 8006852: 69fb ldr r3, [r7, #28] 8006854: 4413 add r3, r2 8006856: f503 6310 add.w r3, r3, #2304 ; 0x900 800685a: 691a ldr r2, [r3, #16] 800685c: 69bb ldr r3, [r7, #24] 800685e: 0159 lsls r1, r3, #5 8006860: 69fb ldr r3, [r7, #28] 8006862: 440b add r3, r1 8006864: f503 6310 add.w r3, r3, #2304 ; 0x900 8006868: 4619 mov r1, r3 800686a: 4b83 ldr r3, [pc, #524] ; (8006a78 ) 800686c: 4013 ands r3, r2 800686e: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & 8006870: 69bb ldr r3, [r7, #24] 8006872: 015a lsls r2, r3, #5 8006874: 69fb ldr r3, [r7, #28] 8006876: 4413 add r3, r2 8006878: f503 6310 add.w r3, r3, #2304 ; 0x900 800687c: 691a ldr r2, [r3, #16] (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); 800687e: 68bb ldr r3, [r7, #8] 8006880: 6959 ldr r1, [r3, #20] 8006882: 68bb ldr r3, [r7, #8] 8006884: 689b ldr r3, [r3, #8] 8006886: 440b add r3, r1 8006888: 1e59 subs r1, r3, #1 800688a: 68bb ldr r3, [r7, #8] 800688c: 689b ldr r3, [r3, #8] 800688e: fbb1 f3f3 udiv r3, r1, r3 8006892: 04d9 lsls r1, r3, #19 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & 8006894: 4b7a ldr r3, [pc, #488] ; (8006a80 ) 8006896: 400b ands r3, r1 8006898: 69b9 ldr r1, [r7, #24] 800689a: 0148 lsls r0, r1, #5 800689c: 69f9 ldr r1, [r7, #28] 800689e: 4401 add r1, r0 80068a0: f501 6110 add.w r1, r1, #2304 ; 0x900 80068a4: 4313 orrs r3, r2 80068a6: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 80068a8: 69bb ldr r3, [r7, #24] 80068aa: 015a lsls r2, r3, #5 80068ac: 69fb ldr r3, [r7, #28] 80068ae: 4413 add r3, r2 80068b0: f503 6310 add.w r3, r3, #2304 ; 0x900 80068b4: 691a ldr r2, [r3, #16] 80068b6: 68bb ldr r3, [r7, #8] 80068b8: 695b ldr r3, [r3, #20] 80068ba: f3c3 0312 ubfx r3, r3, #0, #19 80068be: 69b9 ldr r1, [r7, #24] 80068c0: 0148 lsls r0, r1, #5 80068c2: 69f9 ldr r1, [r7, #28] 80068c4: 4401 add r1, r0 80068c6: f501 6110 add.w r1, r1, #2304 ; 0x900 80068ca: 4313 orrs r3, r2 80068cc: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 80068ce: 68bb ldr r3, [r7, #8] 80068d0: 78db ldrb r3, [r3, #3] 80068d2: 2b01 cmp r3, #1 80068d4: d11f bne.n 8006916 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 80068d6: 69bb ldr r3, [r7, #24] 80068d8: 015a lsls r2, r3, #5 80068da: 69fb ldr r3, [r7, #28] 80068dc: 4413 add r3, r2 80068de: f503 6310 add.w r3, r3, #2304 ; 0x900 80068e2: 691b ldr r3, [r3, #16] 80068e4: 69ba ldr r2, [r7, #24] 80068e6: 0151 lsls r1, r2, #5 80068e8: 69fa ldr r2, [r7, #28] 80068ea: 440a add r2, r1 80068ec: f502 6210 add.w r2, r2, #2304 ; 0x900 80068f0: f023 43c0 bic.w r3, r3, #1610612736 ; 0x60000000 80068f4: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); 80068f6: 69bb ldr r3, [r7, #24] 80068f8: 015a lsls r2, r3, #5 80068fa: 69fb ldr r3, [r7, #28] 80068fc: 4413 add r3, r2 80068fe: f503 6310 add.w r3, r3, #2304 ; 0x900 8006902: 691b ldr r3, [r3, #16] 8006904: 69ba ldr r2, [r7, #24] 8006906: 0151 lsls r1, r2, #5 8006908: 69fa ldr r2, [r7, #28] 800690a: 440a add r2, r1 800690c: f502 6210 add.w r2, r2, #2304 ; 0x900 8006910: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 8006914: 6113 str r3, [r2, #16] } } if (dma == 1U) 8006916: 79fb ldrb r3, [r7, #7] 8006918: 2b01 cmp r3, #1 800691a: d14b bne.n 80069b4 { if ((uint32_t)ep->dma_addr != 0U) 800691c: 68bb ldr r3, [r7, #8] 800691e: 691b ldr r3, [r3, #16] 8006920: 2b00 cmp r3, #0 8006922: d009 beq.n 8006938 { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 8006924: 69bb ldr r3, [r7, #24] 8006926: 015a lsls r2, r3, #5 8006928: 69fb ldr r3, [r7, #28] 800692a: 4413 add r3, r2 800692c: f503 6310 add.w r3, r3, #2304 ; 0x900 8006930: 461a mov r2, r3 8006932: 68bb ldr r3, [r7, #8] 8006934: 691b ldr r3, [r3, #16] 8006936: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 8006938: 68bb ldr r3, [r7, #8] 800693a: 78db ldrb r3, [r3, #3] 800693c: 2b01 cmp r3, #1 800693e: d128 bne.n 8006992 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8006940: 69fb ldr r3, [r7, #28] 8006942: f503 6300 add.w r3, r3, #2048 ; 0x800 8006946: 689b ldr r3, [r3, #8] 8006948: f403 7380 and.w r3, r3, #256 ; 0x100 800694c: 2b00 cmp r3, #0 800694e: d110 bne.n 8006972 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8006950: 69bb ldr r3, [r7, #24] 8006952: 015a lsls r2, r3, #5 8006954: 69fb ldr r3, [r7, #28] 8006956: 4413 add r3, r2 8006958: f503 6310 add.w r3, r3, #2304 ; 0x900 800695c: 681b ldr r3, [r3, #0] 800695e: 69ba ldr r2, [r7, #24] 8006960: 0151 lsls r1, r2, #5 8006962: 69fa ldr r2, [r7, #28] 8006964: 440a add r2, r1 8006966: f502 6210 add.w r2, r2, #2304 ; 0x900 800696a: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 800696e: 6013 str r3, [r2, #0] 8006970: e00f b.n 8006992 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8006972: 69bb ldr r3, [r7, #24] 8006974: 015a lsls r2, r3, #5 8006976: 69fb ldr r3, [r7, #28] 8006978: 4413 add r3, r2 800697a: f503 6310 add.w r3, r3, #2304 ; 0x900 800697e: 681b ldr r3, [r3, #0] 8006980: 69ba ldr r2, [r7, #24] 8006982: 0151 lsls r1, r2, #5 8006984: 69fa ldr r2, [r7, #28] 8006986: 440a add r2, r1 8006988: f502 6210 add.w r2, r2, #2304 ; 0x900 800698c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8006990: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8006992: 69bb ldr r3, [r7, #24] 8006994: 015a lsls r2, r3, #5 8006996: 69fb ldr r3, [r7, #28] 8006998: 4413 add r3, r2 800699a: f503 6310 add.w r3, r3, #2304 ; 0x900 800699e: 681b ldr r3, [r3, #0] 80069a0: 69ba ldr r2, [r7, #24] 80069a2: 0151 lsls r1, r2, #5 80069a4: 69fa ldr r2, [r7, #28] 80069a6: 440a add r2, r1 80069a8: f502 6210 add.w r2, r2, #2304 ; 0x900 80069ac: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 80069b0: 6013 str r3, [r2, #0] 80069b2: e133 b.n 8006c1c } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 80069b4: 69bb ldr r3, [r7, #24] 80069b6: 015a lsls r2, r3, #5 80069b8: 69fb ldr r3, [r7, #28] 80069ba: 4413 add r3, r2 80069bc: f503 6310 add.w r3, r3, #2304 ; 0x900 80069c0: 681b ldr r3, [r3, #0] 80069c2: 69ba ldr r2, [r7, #24] 80069c4: 0151 lsls r1, r2, #5 80069c6: 69fa ldr r2, [r7, #28] 80069c8: 440a add r2, r1 80069ca: f502 6210 add.w r2, r2, #2304 ; 0x900 80069ce: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 80069d2: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 80069d4: 68bb ldr r3, [r7, #8] 80069d6: 78db ldrb r3, [r3, #3] 80069d8: 2b01 cmp r3, #1 80069da: d015 beq.n 8006a08 { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 80069dc: 68bb ldr r3, [r7, #8] 80069de: 695b ldr r3, [r3, #20] 80069e0: 2b00 cmp r3, #0 80069e2: f000 811b beq.w 8006c1c { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 80069e6: 69fb ldr r3, [r7, #28] 80069e8: f503 6300 add.w r3, r3, #2048 ; 0x800 80069ec: 6b5a ldr r2, [r3, #52] ; 0x34 80069ee: 68bb ldr r3, [r7, #8] 80069f0: 781b ldrb r3, [r3, #0] 80069f2: f003 030f and.w r3, r3, #15 80069f6: 2101 movs r1, #1 80069f8: fa01 f303 lsl.w r3, r1, r3 80069fc: 69f9 ldr r1, [r7, #28] 80069fe: f501 6100 add.w r1, r1, #2048 ; 0x800 8006a02: 4313 orrs r3, r2 8006a04: 634b str r3, [r1, #52] ; 0x34 8006a06: e109 b.n 8006c1c } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8006a08: 69fb ldr r3, [r7, #28] 8006a0a: f503 6300 add.w r3, r3, #2048 ; 0x800 8006a0e: 689b ldr r3, [r3, #8] 8006a10: f403 7380 and.w r3, r3, #256 ; 0x100 8006a14: 2b00 cmp r3, #0 8006a16: d110 bne.n 8006a3a { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8006a18: 69bb ldr r3, [r7, #24] 8006a1a: 015a lsls r2, r3, #5 8006a1c: 69fb ldr r3, [r7, #28] 8006a1e: 4413 add r3, r2 8006a20: f503 6310 add.w r3, r3, #2304 ; 0x900 8006a24: 681b ldr r3, [r3, #0] 8006a26: 69ba ldr r2, [r7, #24] 8006a28: 0151 lsls r1, r2, #5 8006a2a: 69fa ldr r2, [r7, #28] 8006a2c: 440a add r2, r1 8006a2e: f502 6210 add.w r2, r2, #2304 ; 0x900 8006a32: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 8006a36: 6013 str r3, [r2, #0] 8006a38: e00f b.n 8006a5a } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8006a3a: 69bb ldr r3, [r7, #24] 8006a3c: 015a lsls r2, r3, #5 8006a3e: 69fb ldr r3, [r7, #28] 8006a40: 4413 add r3, r2 8006a42: f503 6310 add.w r3, r3, #2304 ; 0x900 8006a46: 681b ldr r3, [r3, #0] 8006a48: 69ba ldr r2, [r7, #24] 8006a4a: 0151 lsls r1, r2, #5 8006a4c: 69fa ldr r2, [r7, #28] 8006a4e: 440a add r2, r1 8006a50: f502 6210 add.w r2, r2, #2304 ; 0x900 8006a54: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8006a58: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 8006a5a: 68bb ldr r3, [r7, #8] 8006a5c: 68d9 ldr r1, [r3, #12] 8006a5e: 68bb ldr r3, [r7, #8] 8006a60: 781a ldrb r2, [r3, #0] 8006a62: 68bb ldr r3, [r7, #8] 8006a64: 695b ldr r3, [r3, #20] 8006a66: b298 uxth r0, r3 8006a68: 79fb ldrb r3, [r7, #7] 8006a6a: 9300 str r3, [sp, #0] 8006a6c: 4603 mov r3, r0 8006a6e: 68f8 ldr r0, [r7, #12] 8006a70: f000 fa38 bl 8006ee4 8006a74: e0d2 b.n 8006c1c 8006a76: bf00 nop 8006a78: e007ffff .word 0xe007ffff 8006a7c: fff80000 .word 0xfff80000 8006a80: 1ff80000 .word 0x1ff80000 { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 8006a84: 69bb ldr r3, [r7, #24] 8006a86: 015a lsls r2, r3, #5 8006a88: 69fb ldr r3, [r7, #28] 8006a8a: 4413 add r3, r2 8006a8c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a90: 691a ldr r2, [r3, #16] 8006a92: 69bb ldr r3, [r7, #24] 8006a94: 0159 lsls r1, r3, #5 8006a96: 69fb ldr r3, [r7, #28] 8006a98: 440b add r3, r1 8006a9a: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a9e: 4619 mov r1, r3 8006aa0: 4b61 ldr r3, [pc, #388] ; (8006c28 ) 8006aa2: 4013 ands r3, r2 8006aa4: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 8006aa6: 69bb ldr r3, [r7, #24] 8006aa8: 015a lsls r2, r3, #5 8006aaa: 69fb ldr r3, [r7, #28] 8006aac: 4413 add r3, r2 8006aae: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006ab2: 691a ldr r2, [r3, #16] 8006ab4: 69bb ldr r3, [r7, #24] 8006ab6: 0159 lsls r1, r3, #5 8006ab8: 69fb ldr r3, [r7, #28] 8006aba: 440b add r3, r1 8006abc: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006ac0: 4619 mov r1, r3 8006ac2: 4b5a ldr r3, [pc, #360] ; (8006c2c ) 8006ac4: 4013 ands r3, r2 8006ac6: 610b str r3, [r1, #16] if (ep->xfer_len == 0U) 8006ac8: 68bb ldr r3, [r7, #8] 8006aca: 695b ldr r3, [r3, #20] 8006acc: 2b00 cmp r3, #0 8006ace: d123 bne.n 8006b18 { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 8006ad0: 69bb ldr r3, [r7, #24] 8006ad2: 015a lsls r2, r3, #5 8006ad4: 69fb ldr r3, [r7, #28] 8006ad6: 4413 add r3, r2 8006ad8: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006adc: 691a ldr r2, [r3, #16] 8006ade: 68bb ldr r3, [r7, #8] 8006ae0: 689b ldr r3, [r3, #8] 8006ae2: f3c3 0312 ubfx r3, r3, #0, #19 8006ae6: 69b9 ldr r1, [r7, #24] 8006ae8: 0148 lsls r0, r1, #5 8006aea: 69f9 ldr r1, [r7, #28] 8006aec: 4401 add r1, r0 8006aee: f501 6130 add.w r1, r1, #2816 ; 0xb00 8006af2: 4313 orrs r3, r2 8006af4: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8006af6: 69bb ldr r3, [r7, #24] 8006af8: 015a lsls r2, r3, #5 8006afa: 69fb ldr r3, [r7, #28] 8006afc: 4413 add r3, r2 8006afe: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006b02: 691b ldr r3, [r3, #16] 8006b04: 69ba ldr r2, [r7, #24] 8006b06: 0151 lsls r1, r2, #5 8006b08: 69fa ldr r2, [r7, #28] 8006b0a: 440a add r2, r1 8006b0c: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006b10: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006b14: 6113 str r3, [r2, #16] 8006b16: e033 b.n 8006b80 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8006b18: 68bb ldr r3, [r7, #8] 8006b1a: 695a ldr r2, [r3, #20] 8006b1c: 68bb ldr r3, [r7, #8] 8006b1e: 689b ldr r3, [r3, #8] 8006b20: 4413 add r3, r2 8006b22: 1e5a subs r2, r3, #1 8006b24: 68bb ldr r3, [r7, #8] 8006b26: 689b ldr r3, [r3, #8] 8006b28: fbb2 f3f3 udiv r3, r2, r3 8006b2c: 82fb strh r3, [r7, #22] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 8006b2e: 69bb ldr r3, [r7, #24] 8006b30: 015a lsls r2, r3, #5 8006b32: 69fb ldr r3, [r7, #28] 8006b34: 4413 add r3, r2 8006b36: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006b3a: 691a ldr r2, [r3, #16] 8006b3c: 8afb ldrh r3, [r7, #22] 8006b3e: 04d9 lsls r1, r3, #19 8006b40: 4b3b ldr r3, [pc, #236] ; (8006c30 ) 8006b42: 400b ands r3, r1 8006b44: 69b9 ldr r1, [r7, #24] 8006b46: 0148 lsls r0, r1, #5 8006b48: 69f9 ldr r1, [r7, #28] 8006b4a: 4401 add r1, r0 8006b4c: f501 6130 add.w r1, r1, #2816 ; 0xb00 8006b50: 4313 orrs r3, r2 8006b52: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); 8006b54: 69bb ldr r3, [r7, #24] 8006b56: 015a lsls r2, r3, #5 8006b58: 69fb ldr r3, [r7, #28] 8006b5a: 4413 add r3, r2 8006b5c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006b60: 691a ldr r2, [r3, #16] 8006b62: 68bb ldr r3, [r7, #8] 8006b64: 689b ldr r3, [r3, #8] 8006b66: 8af9 ldrh r1, [r7, #22] 8006b68: fb01 f303 mul.w r3, r1, r3 8006b6c: f3c3 0312 ubfx r3, r3, #0, #19 8006b70: 69b9 ldr r1, [r7, #24] 8006b72: 0148 lsls r0, r1, #5 8006b74: 69f9 ldr r1, [r7, #28] 8006b76: 4401 add r1, r0 8006b78: f501 6130 add.w r1, r1, #2816 ; 0xb00 8006b7c: 4313 orrs r3, r2 8006b7e: 610b str r3, [r1, #16] } if (dma == 1U) 8006b80: 79fb ldrb r3, [r7, #7] 8006b82: 2b01 cmp r3, #1 8006b84: d10d bne.n 8006ba2 { if ((uint32_t)ep->xfer_buff != 0U) 8006b86: 68bb ldr r3, [r7, #8] 8006b88: 68db ldr r3, [r3, #12] 8006b8a: 2b00 cmp r3, #0 8006b8c: d009 beq.n 8006ba2 { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8006b8e: 68bb ldr r3, [r7, #8] 8006b90: 68d9 ldr r1, [r3, #12] 8006b92: 69bb ldr r3, [r7, #24] 8006b94: 015a lsls r2, r3, #5 8006b96: 69fb ldr r3, [r7, #28] 8006b98: 4413 add r3, r2 8006b9a: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006b9e: 460a mov r2, r1 8006ba0: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 8006ba2: 68bb ldr r3, [r7, #8] 8006ba4: 78db ldrb r3, [r3, #3] 8006ba6: 2b01 cmp r3, #1 8006ba8: d128 bne.n 8006bfc { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8006baa: 69fb ldr r3, [r7, #28] 8006bac: f503 6300 add.w r3, r3, #2048 ; 0x800 8006bb0: 689b ldr r3, [r3, #8] 8006bb2: f403 7380 and.w r3, r3, #256 ; 0x100 8006bb6: 2b00 cmp r3, #0 8006bb8: d110 bne.n 8006bdc { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 8006bba: 69bb ldr r3, [r7, #24] 8006bbc: 015a lsls r2, r3, #5 8006bbe: 69fb ldr r3, [r7, #28] 8006bc0: 4413 add r3, r2 8006bc2: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006bc6: 681b ldr r3, [r3, #0] 8006bc8: 69ba ldr r2, [r7, #24] 8006bca: 0151 lsls r1, r2, #5 8006bcc: 69fa ldr r2, [r7, #28] 8006bce: 440a add r2, r1 8006bd0: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006bd4: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 8006bd8: 6013 str r3, [r2, #0] 8006bda: e00f b.n 8006bfc } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 8006bdc: 69bb ldr r3, [r7, #24] 8006bde: 015a lsls r2, r3, #5 8006be0: 69fb ldr r3, [r7, #28] 8006be2: 4413 add r3, r2 8006be4: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006be8: 681b ldr r3, [r3, #0] 8006bea: 69ba ldr r2, [r7, #24] 8006bec: 0151 lsls r1, r2, #5 8006bee: 69fa ldr r2, [r7, #28] 8006bf0: 440a add r2, r1 8006bf2: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006bf6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8006bfa: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8006bfc: 69bb ldr r3, [r7, #24] 8006bfe: 015a lsls r2, r3, #5 8006c00: 69fb ldr r3, [r7, #28] 8006c02: 4413 add r3, r2 8006c04: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006c08: 681b ldr r3, [r3, #0] 8006c0a: 69ba ldr r2, [r7, #24] 8006c0c: 0151 lsls r1, r2, #5 8006c0e: 69fa ldr r2, [r7, #28] 8006c10: 440a add r2, r1 8006c12: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006c16: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 8006c1a: 6013 str r3, [r2, #0] } return HAL_OK; 8006c1c: 2300 movs r3, #0 } 8006c1e: 4618 mov r0, r3 8006c20: 3720 adds r7, #32 8006c22: 46bd mov sp, r7 8006c24: bd80 pop {r7, pc} 8006c26: bf00 nop 8006c28: fff80000 .word 0xfff80000 8006c2c: e007ffff .word 0xe007ffff 8006c30: 1ff80000 .word 0x1ff80000 08006c34 : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 8006c34: b480 push {r7} 8006c36: b087 sub sp, #28 8006c38: af00 add r7, sp, #0 8006c3a: 60f8 str r0, [r7, #12] 8006c3c: 60b9 str r1, [r7, #8] 8006c3e: 4613 mov r3, r2 8006c40: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 8006c42: 68fb ldr r3, [r7, #12] 8006c44: 617b str r3, [r7, #20] uint32_t epnum = (uint32_t)ep->num; 8006c46: 68bb ldr r3, [r7, #8] 8006c48: 781b ldrb r3, [r3, #0] 8006c4a: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 8006c4c: 68bb ldr r3, [r7, #8] 8006c4e: 785b ldrb r3, [r3, #1] 8006c50: 2b01 cmp r3, #1 8006c52: f040 80cd bne.w 8006df0 { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 8006c56: 68bb ldr r3, [r7, #8] 8006c58: 695b ldr r3, [r3, #20] 8006c5a: 2b00 cmp r3, #0 8006c5c: d132 bne.n 8006cc4 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8006c5e: 693b ldr r3, [r7, #16] 8006c60: 015a lsls r2, r3, #5 8006c62: 697b ldr r3, [r7, #20] 8006c64: 4413 add r3, r2 8006c66: f503 6310 add.w r3, r3, #2304 ; 0x900 8006c6a: 691a ldr r2, [r3, #16] 8006c6c: 693b ldr r3, [r7, #16] 8006c6e: 0159 lsls r1, r3, #5 8006c70: 697b ldr r3, [r7, #20] 8006c72: 440b add r3, r1 8006c74: f503 6310 add.w r3, r3, #2304 ; 0x900 8006c78: 4619 mov r1, r3 8006c7a: 4b98 ldr r3, [pc, #608] ; (8006edc ) 8006c7c: 4013 ands r3, r2 8006c7e: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8006c80: 693b ldr r3, [r7, #16] 8006c82: 015a lsls r2, r3, #5 8006c84: 697b ldr r3, [r7, #20] 8006c86: 4413 add r3, r2 8006c88: f503 6310 add.w r3, r3, #2304 ; 0x900 8006c8c: 691b ldr r3, [r3, #16] 8006c8e: 693a ldr r2, [r7, #16] 8006c90: 0151 lsls r1, r2, #5 8006c92: 697a ldr r2, [r7, #20] 8006c94: 440a add r2, r1 8006c96: f502 6210 add.w r2, r2, #2304 ; 0x900 8006c9a: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006c9e: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8006ca0: 693b ldr r3, [r7, #16] 8006ca2: 015a lsls r2, r3, #5 8006ca4: 697b ldr r3, [r7, #20] 8006ca6: 4413 add r3, r2 8006ca8: f503 6310 add.w r3, r3, #2304 ; 0x900 8006cac: 691a ldr r2, [r3, #16] 8006cae: 693b ldr r3, [r7, #16] 8006cb0: 0159 lsls r1, r3, #5 8006cb2: 697b ldr r3, [r7, #20] 8006cb4: 440b add r3, r1 8006cb6: f503 6310 add.w r3, r3, #2304 ; 0x900 8006cba: 4619 mov r1, r3 8006cbc: 4b88 ldr r3, [pc, #544] ; (8006ee0 ) 8006cbe: 4013 ands r3, r2 8006cc0: 610b str r3, [r1, #16] 8006cc2: e04e b.n 8006d62 /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8006cc4: 693b ldr r3, [r7, #16] 8006cc6: 015a lsls r2, r3, #5 8006cc8: 697b ldr r3, [r7, #20] 8006cca: 4413 add r3, r2 8006ccc: f503 6310 add.w r3, r3, #2304 ; 0x900 8006cd0: 691a ldr r2, [r3, #16] 8006cd2: 693b ldr r3, [r7, #16] 8006cd4: 0159 lsls r1, r3, #5 8006cd6: 697b ldr r3, [r7, #20] 8006cd8: 440b add r3, r1 8006cda: f503 6310 add.w r3, r3, #2304 ; 0x900 8006cde: 4619 mov r1, r3 8006ce0: 4b7f ldr r3, [pc, #508] ; (8006ee0 ) 8006ce2: 4013 ands r3, r2 8006ce4: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8006ce6: 693b ldr r3, [r7, #16] 8006ce8: 015a lsls r2, r3, #5 8006cea: 697b ldr r3, [r7, #20] 8006cec: 4413 add r3, r2 8006cee: f503 6310 add.w r3, r3, #2304 ; 0x900 8006cf2: 691a ldr r2, [r3, #16] 8006cf4: 693b ldr r3, [r7, #16] 8006cf6: 0159 lsls r1, r3, #5 8006cf8: 697b ldr r3, [r7, #20] 8006cfa: 440b add r3, r1 8006cfc: f503 6310 add.w r3, r3, #2304 ; 0x900 8006d00: 4619 mov r1, r3 8006d02: 4b76 ldr r3, [pc, #472] ; (8006edc ) 8006d04: 4013 ands r3, r2 8006d06: 610b str r3, [r1, #16] if (ep->xfer_len > ep->maxpacket) 8006d08: 68bb ldr r3, [r7, #8] 8006d0a: 695a ldr r2, [r3, #20] 8006d0c: 68bb ldr r3, [r7, #8] 8006d0e: 689b ldr r3, [r3, #8] 8006d10: 429a cmp r2, r3 8006d12: d903 bls.n 8006d1c { ep->xfer_len = ep->maxpacket; 8006d14: 68bb ldr r3, [r7, #8] 8006d16: 689a ldr r2, [r3, #8] 8006d18: 68bb ldr r3, [r7, #8] 8006d1a: 615a str r2, [r3, #20] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8006d1c: 693b ldr r3, [r7, #16] 8006d1e: 015a lsls r2, r3, #5 8006d20: 697b ldr r3, [r7, #20] 8006d22: 4413 add r3, r2 8006d24: f503 6310 add.w r3, r3, #2304 ; 0x900 8006d28: 691b ldr r3, [r3, #16] 8006d2a: 693a ldr r2, [r7, #16] 8006d2c: 0151 lsls r1, r2, #5 8006d2e: 697a ldr r2, [r7, #20] 8006d30: 440a add r2, r1 8006d32: f502 6210 add.w r2, r2, #2304 ; 0x900 8006d36: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006d3a: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 8006d3c: 693b ldr r3, [r7, #16] 8006d3e: 015a lsls r2, r3, #5 8006d40: 697b ldr r3, [r7, #20] 8006d42: 4413 add r3, r2 8006d44: f503 6310 add.w r3, r3, #2304 ; 0x900 8006d48: 691a ldr r2, [r3, #16] 8006d4a: 68bb ldr r3, [r7, #8] 8006d4c: 695b ldr r3, [r3, #20] 8006d4e: f3c3 0312 ubfx r3, r3, #0, #19 8006d52: 6939 ldr r1, [r7, #16] 8006d54: 0148 lsls r0, r1, #5 8006d56: 6979 ldr r1, [r7, #20] 8006d58: 4401 add r1, r0 8006d5a: f501 6110 add.w r1, r1, #2304 ; 0x900 8006d5e: 4313 orrs r3, r2 8006d60: 610b str r3, [r1, #16] } if (dma == 1U) 8006d62: 79fb ldrb r3, [r7, #7] 8006d64: 2b01 cmp r3, #1 8006d66: d11e bne.n 8006da6 { if ((uint32_t)ep->dma_addr != 0U) 8006d68: 68bb ldr r3, [r7, #8] 8006d6a: 691b ldr r3, [r3, #16] 8006d6c: 2b00 cmp r3, #0 8006d6e: d009 beq.n 8006d84 { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 8006d70: 693b ldr r3, [r7, #16] 8006d72: 015a lsls r2, r3, #5 8006d74: 697b ldr r3, [r7, #20] 8006d76: 4413 add r3, r2 8006d78: f503 6310 add.w r3, r3, #2304 ; 0x900 8006d7c: 461a mov r2, r3 8006d7e: 68bb ldr r3, [r7, #8] 8006d80: 691b ldr r3, [r3, #16] 8006d82: 6153 str r3, [r2, #20] } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8006d84: 693b ldr r3, [r7, #16] 8006d86: 015a lsls r2, r3, #5 8006d88: 697b ldr r3, [r7, #20] 8006d8a: 4413 add r3, r2 8006d8c: f503 6310 add.w r3, r3, #2304 ; 0x900 8006d90: 681b ldr r3, [r3, #0] 8006d92: 693a ldr r2, [r7, #16] 8006d94: 0151 lsls r1, r2, #5 8006d96: 697a ldr r2, [r7, #20] 8006d98: 440a add r2, r1 8006d9a: f502 6210 add.w r2, r2, #2304 ; 0x900 8006d9e: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 8006da2: 6013 str r3, [r2, #0] 8006da4: e092 b.n 8006ecc } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8006da6: 693b ldr r3, [r7, #16] 8006da8: 015a lsls r2, r3, #5 8006daa: 697b ldr r3, [r7, #20] 8006dac: 4413 add r3, r2 8006dae: f503 6310 add.w r3, r3, #2304 ; 0x900 8006db2: 681b ldr r3, [r3, #0] 8006db4: 693a ldr r2, [r7, #16] 8006db6: 0151 lsls r1, r2, #5 8006db8: 697a ldr r2, [r7, #20] 8006dba: 440a add r2, r1 8006dbc: f502 6210 add.w r2, r2, #2304 ; 0x900 8006dc0: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 8006dc4: 6013 str r3, [r2, #0] /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 8006dc6: 68bb ldr r3, [r7, #8] 8006dc8: 695b ldr r3, [r3, #20] 8006dca: 2b00 cmp r3, #0 8006dcc: d07e beq.n 8006ecc { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 8006dce: 697b ldr r3, [r7, #20] 8006dd0: f503 6300 add.w r3, r3, #2048 ; 0x800 8006dd4: 6b5a ldr r2, [r3, #52] ; 0x34 8006dd6: 68bb ldr r3, [r7, #8] 8006dd8: 781b ldrb r3, [r3, #0] 8006dda: f003 030f and.w r3, r3, #15 8006dde: 2101 movs r1, #1 8006de0: fa01 f303 lsl.w r3, r1, r3 8006de4: 6979 ldr r1, [r7, #20] 8006de6: f501 6100 add.w r1, r1, #2048 ; 0x800 8006dea: 4313 orrs r3, r2 8006dec: 634b str r3, [r1, #52] ; 0x34 8006dee: e06d b.n 8006ecc { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 8006df0: 693b ldr r3, [r7, #16] 8006df2: 015a lsls r2, r3, #5 8006df4: 697b ldr r3, [r7, #20] 8006df6: 4413 add r3, r2 8006df8: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006dfc: 691a ldr r2, [r3, #16] 8006dfe: 693b ldr r3, [r7, #16] 8006e00: 0159 lsls r1, r3, #5 8006e02: 697b ldr r3, [r7, #20] 8006e04: 440b add r3, r1 8006e06: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006e0a: 4619 mov r1, r3 8006e0c: 4b34 ldr r3, [pc, #208] ; (8006ee0 ) 8006e0e: 4013 ands r3, r2 8006e10: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 8006e12: 693b ldr r3, [r7, #16] 8006e14: 015a lsls r2, r3, #5 8006e16: 697b ldr r3, [r7, #20] 8006e18: 4413 add r3, r2 8006e1a: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006e1e: 691a ldr r2, [r3, #16] 8006e20: 693b ldr r3, [r7, #16] 8006e22: 0159 lsls r1, r3, #5 8006e24: 697b ldr r3, [r7, #20] 8006e26: 440b add r3, r1 8006e28: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006e2c: 4619 mov r1, r3 8006e2e: 4b2b ldr r3, [pc, #172] ; (8006edc ) 8006e30: 4013 ands r3, r2 8006e32: 610b str r3, [r1, #16] if (ep->xfer_len > 0U) 8006e34: 68bb ldr r3, [r7, #8] 8006e36: 695b ldr r3, [r3, #20] 8006e38: 2b00 cmp r3, #0 8006e3a: d003 beq.n 8006e44 { ep->xfer_len = ep->maxpacket; 8006e3c: 68bb ldr r3, [r7, #8] 8006e3e: 689a ldr r2, [r3, #8] 8006e40: 68bb ldr r3, [r7, #8] 8006e42: 615a str r2, [r3, #20] } USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8006e44: 693b ldr r3, [r7, #16] 8006e46: 015a lsls r2, r3, #5 8006e48: 697b ldr r3, [r7, #20] 8006e4a: 4413 add r3, r2 8006e4c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006e50: 691b ldr r3, [r3, #16] 8006e52: 693a ldr r2, [r7, #16] 8006e54: 0151 lsls r1, r2, #5 8006e56: 697a ldr r2, [r7, #20] 8006e58: 440a add r2, r1 8006e5a: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006e5e: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006e62: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); 8006e64: 693b ldr r3, [r7, #16] 8006e66: 015a lsls r2, r3, #5 8006e68: 697b ldr r3, [r7, #20] 8006e6a: 4413 add r3, r2 8006e6c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006e70: 691a ldr r2, [r3, #16] 8006e72: 68bb ldr r3, [r7, #8] 8006e74: 689b ldr r3, [r3, #8] 8006e76: f3c3 0312 ubfx r3, r3, #0, #19 8006e7a: 6939 ldr r1, [r7, #16] 8006e7c: 0148 lsls r0, r1, #5 8006e7e: 6979 ldr r1, [r7, #20] 8006e80: 4401 add r1, r0 8006e82: f501 6130 add.w r1, r1, #2816 ; 0xb00 8006e86: 4313 orrs r3, r2 8006e88: 610b str r3, [r1, #16] if (dma == 1U) 8006e8a: 79fb ldrb r3, [r7, #7] 8006e8c: 2b01 cmp r3, #1 8006e8e: d10d bne.n 8006eac { if ((uint32_t)ep->xfer_buff != 0U) 8006e90: 68bb ldr r3, [r7, #8] 8006e92: 68db ldr r3, [r3, #12] 8006e94: 2b00 cmp r3, #0 8006e96: d009 beq.n 8006eac { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8006e98: 68bb ldr r3, [r7, #8] 8006e9a: 68d9 ldr r1, [r3, #12] 8006e9c: 693b ldr r3, [r7, #16] 8006e9e: 015a lsls r2, r3, #5 8006ea0: 697b ldr r3, [r7, #20] 8006ea2: 4413 add r3, r2 8006ea4: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006ea8: 460a mov r2, r1 8006eaa: 615a str r2, [r3, #20] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8006eac: 693b ldr r3, [r7, #16] 8006eae: 015a lsls r2, r3, #5 8006eb0: 697b ldr r3, [r7, #20] 8006eb2: 4413 add r3, r2 8006eb4: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006eb8: 681b ldr r3, [r3, #0] 8006eba: 693a ldr r2, [r7, #16] 8006ebc: 0151 lsls r1, r2, #5 8006ebe: 697a ldr r2, [r7, #20] 8006ec0: 440a add r2, r1 8006ec2: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006ec6: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 8006eca: 6013 str r3, [r2, #0] } return HAL_OK; 8006ecc: 2300 movs r3, #0 } 8006ece: 4618 mov r0, r3 8006ed0: 371c adds r7, #28 8006ed2: 46bd mov sp, r7 8006ed4: f85d 7b04 ldr.w r7, [sp], #4 8006ed8: 4770 bx lr 8006eda: bf00 nop 8006edc: e007ffff .word 0xe007ffff 8006ee0: fff80000 .word 0xfff80000 08006ee4 : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 8006ee4: b480 push {r7} 8006ee6: b089 sub sp, #36 ; 0x24 8006ee8: af00 add r7, sp, #0 8006eea: 60f8 str r0, [r7, #12] 8006eec: 60b9 str r1, [r7, #8] 8006eee: 4611 mov r1, r2 8006ef0: 461a mov r2, r3 8006ef2: 460b mov r3, r1 8006ef4: 71fb strb r3, [r7, #7] 8006ef6: 4613 mov r3, r2 8006ef8: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8006efa: 68fb ldr r3, [r7, #12] 8006efc: 617b str r3, [r7, #20] uint8_t *pSrc = src; 8006efe: 68bb ldr r3, [r7, #8] 8006f00: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 8006f02: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 8006f06: 2b00 cmp r3, #0 8006f08: d123 bne.n 8006f52 { count32b = ((uint32_t)len + 3U) / 4U; 8006f0a: 88bb ldrh r3, [r7, #4] 8006f0c: 3303 adds r3, #3 8006f0e: 089b lsrs r3, r3, #2 8006f10: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 8006f12: 2300 movs r3, #0 8006f14: 61bb str r3, [r7, #24] 8006f16: e018 b.n 8006f4a { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 8006f18: 79fb ldrb r3, [r7, #7] 8006f1a: 031a lsls r2, r3, #12 8006f1c: 697b ldr r3, [r7, #20] 8006f1e: 4413 add r3, r2 8006f20: f503 5380 add.w r3, r3, #4096 ; 0x1000 8006f24: 461a mov r2, r3 8006f26: 69fb ldr r3, [r7, #28] 8006f28: 681b ldr r3, [r3, #0] 8006f2a: 6013 str r3, [r2, #0] pSrc++; 8006f2c: 69fb ldr r3, [r7, #28] 8006f2e: 3301 adds r3, #1 8006f30: 61fb str r3, [r7, #28] pSrc++; 8006f32: 69fb ldr r3, [r7, #28] 8006f34: 3301 adds r3, #1 8006f36: 61fb str r3, [r7, #28] pSrc++; 8006f38: 69fb ldr r3, [r7, #28] 8006f3a: 3301 adds r3, #1 8006f3c: 61fb str r3, [r7, #28] pSrc++; 8006f3e: 69fb ldr r3, [r7, #28] 8006f40: 3301 adds r3, #1 8006f42: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 8006f44: 69bb ldr r3, [r7, #24] 8006f46: 3301 adds r3, #1 8006f48: 61bb str r3, [r7, #24] 8006f4a: 69ba ldr r2, [r7, #24] 8006f4c: 693b ldr r3, [r7, #16] 8006f4e: 429a cmp r2, r3 8006f50: d3e2 bcc.n 8006f18 } } return HAL_OK; 8006f52: 2300 movs r3, #0 } 8006f54: 4618 mov r0, r3 8006f56: 3724 adds r7, #36 ; 0x24 8006f58: 46bd mov sp, r7 8006f5a: f85d 7b04 ldr.w r7, [sp], #4 8006f5e: 4770 bx lr 08006f60 : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 8006f60: b480 push {r7} 8006f62: b08b sub sp, #44 ; 0x2c 8006f64: af00 add r7, sp, #0 8006f66: 60f8 str r0, [r7, #12] 8006f68: 60b9 str r1, [r7, #8] 8006f6a: 4613 mov r3, r2 8006f6c: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 8006f6e: 68fb ldr r3, [r7, #12] 8006f70: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 8006f72: 68bb ldr r3, [r7, #8] 8006f74: 627b str r3, [r7, #36] ; 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 8006f76: 88fb ldrh r3, [r7, #6] 8006f78: 089b lsrs r3, r3, #2 8006f7a: b29b uxth r3, r3 8006f7c: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 8006f7e: 88fb ldrh r3, [r7, #6] 8006f80: f003 0303 and.w r3, r3, #3 8006f84: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 8006f86: 2300 movs r3, #0 8006f88: 623b str r3, [r7, #32] 8006f8a: e014 b.n 8006fb6 { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 8006f8c: 69bb ldr r3, [r7, #24] 8006f8e: f503 5380 add.w r3, r3, #4096 ; 0x1000 8006f92: 681a ldr r2, [r3, #0] 8006f94: 6a7b ldr r3, [r7, #36] ; 0x24 8006f96: 601a str r2, [r3, #0] pDest++; 8006f98: 6a7b ldr r3, [r7, #36] ; 0x24 8006f9a: 3301 adds r3, #1 8006f9c: 627b str r3, [r7, #36] ; 0x24 pDest++; 8006f9e: 6a7b ldr r3, [r7, #36] ; 0x24 8006fa0: 3301 adds r3, #1 8006fa2: 627b str r3, [r7, #36] ; 0x24 pDest++; 8006fa4: 6a7b ldr r3, [r7, #36] ; 0x24 8006fa6: 3301 adds r3, #1 8006fa8: 627b str r3, [r7, #36] ; 0x24 pDest++; 8006faa: 6a7b ldr r3, [r7, #36] ; 0x24 8006fac: 3301 adds r3, #1 8006fae: 627b str r3, [r7, #36] ; 0x24 for (i = 0U; i < count32b; i++) 8006fb0: 6a3b ldr r3, [r7, #32] 8006fb2: 3301 adds r3, #1 8006fb4: 623b str r3, [r7, #32] 8006fb6: 6a3a ldr r2, [r7, #32] 8006fb8: 697b ldr r3, [r7, #20] 8006fba: 429a cmp r2, r3 8006fbc: d3e6 bcc.n 8006f8c } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 8006fbe: 8bfb ldrh r3, [r7, #30] 8006fc0: 2b00 cmp r3, #0 8006fc2: d01e beq.n 8007002 { i = 0U; 8006fc4: 2300 movs r3, #0 8006fc6: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 8006fc8: 69bb ldr r3, [r7, #24] 8006fca: f503 5380 add.w r3, r3, #4096 ; 0x1000 8006fce: 461a mov r2, r3 8006fd0: f107 0310 add.w r3, r7, #16 8006fd4: 6812 ldr r2, [r2, #0] 8006fd6: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 8006fd8: 693a ldr r2, [r7, #16] 8006fda: 6a3b ldr r3, [r7, #32] 8006fdc: b2db uxtb r3, r3 8006fde: 00db lsls r3, r3, #3 8006fe0: fa22 f303 lsr.w r3, r2, r3 8006fe4: b2da uxtb r2, r3 8006fe6: 6a7b ldr r3, [r7, #36] ; 0x24 8006fe8: 701a strb r2, [r3, #0] i++; 8006fea: 6a3b ldr r3, [r7, #32] 8006fec: 3301 adds r3, #1 8006fee: 623b str r3, [r7, #32] pDest++; 8006ff0: 6a7b ldr r3, [r7, #36] ; 0x24 8006ff2: 3301 adds r3, #1 8006ff4: 627b str r3, [r7, #36] ; 0x24 remaining_bytes--; 8006ff6: 8bfb ldrh r3, [r7, #30] 8006ff8: 3b01 subs r3, #1 8006ffa: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 8006ffc: 8bfb ldrh r3, [r7, #30] 8006ffe: 2b00 cmp r3, #0 8007000: d1ea bne.n 8006fd8 } return ((void *)pDest); 8007002: 6a7b ldr r3, [r7, #36] ; 0x24 } 8007004: 4618 mov r0, r3 8007006: 372c adds r7, #44 ; 0x2c 8007008: 46bd mov sp, r7 800700a: f85d 7b04 ldr.w r7, [sp], #4 800700e: 4770 bx lr 08007010 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8007010: b480 push {r7} 8007012: b085 sub sp, #20 8007014: af00 add r7, sp, #0 8007016: 6078 str r0, [r7, #4] 8007018: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800701a: 687b ldr r3, [r7, #4] 800701c: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 800701e: 683b ldr r3, [r7, #0] 8007020: 781b ldrb r3, [r3, #0] 8007022: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8007024: 683b ldr r3, [r7, #0] 8007026: 785b ldrb r3, [r3, #1] 8007028: 2b01 cmp r3, #1 800702a: d12c bne.n 8007086 { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 800702c: 68bb ldr r3, [r7, #8] 800702e: 015a lsls r2, r3, #5 8007030: 68fb ldr r3, [r7, #12] 8007032: 4413 add r3, r2 8007034: f503 6310 add.w r3, r3, #2304 ; 0x900 8007038: 681b ldr r3, [r3, #0] 800703a: 2b00 cmp r3, #0 800703c: db12 blt.n 8007064 800703e: 68bb ldr r3, [r7, #8] 8007040: 2b00 cmp r3, #0 8007042: d00f beq.n 8007064 { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 8007044: 68bb ldr r3, [r7, #8] 8007046: 015a lsls r2, r3, #5 8007048: 68fb ldr r3, [r7, #12] 800704a: 4413 add r3, r2 800704c: f503 6310 add.w r3, r3, #2304 ; 0x900 8007050: 681b ldr r3, [r3, #0] 8007052: 68ba ldr r2, [r7, #8] 8007054: 0151 lsls r1, r2, #5 8007056: 68fa ldr r2, [r7, #12] 8007058: 440a add r2, r1 800705a: f502 6210 add.w r2, r2, #2304 ; 0x900 800705e: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 8007062: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 8007064: 68bb ldr r3, [r7, #8] 8007066: 015a lsls r2, r3, #5 8007068: 68fb ldr r3, [r7, #12] 800706a: 4413 add r3, r2 800706c: f503 6310 add.w r3, r3, #2304 ; 0x900 8007070: 681b ldr r3, [r3, #0] 8007072: 68ba ldr r2, [r7, #8] 8007074: 0151 lsls r1, r2, #5 8007076: 68fa ldr r2, [r7, #12] 8007078: 440a add r2, r1 800707a: f502 6210 add.w r2, r2, #2304 ; 0x900 800707e: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8007082: 6013 str r3, [r2, #0] 8007084: e02b b.n 80070de } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 8007086: 68bb ldr r3, [r7, #8] 8007088: 015a lsls r2, r3, #5 800708a: 68fb ldr r3, [r7, #12] 800708c: 4413 add r3, r2 800708e: f503 6330 add.w r3, r3, #2816 ; 0xb00 8007092: 681b ldr r3, [r3, #0] 8007094: 2b00 cmp r3, #0 8007096: db12 blt.n 80070be 8007098: 68bb ldr r3, [r7, #8] 800709a: 2b00 cmp r3, #0 800709c: d00f beq.n 80070be { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 800709e: 68bb ldr r3, [r7, #8] 80070a0: 015a lsls r2, r3, #5 80070a2: 68fb ldr r3, [r7, #12] 80070a4: 4413 add r3, r2 80070a6: f503 6330 add.w r3, r3, #2816 ; 0xb00 80070aa: 681b ldr r3, [r3, #0] 80070ac: 68ba ldr r2, [r7, #8] 80070ae: 0151 lsls r1, r2, #5 80070b0: 68fa ldr r2, [r7, #12] 80070b2: 440a add r2, r1 80070b4: f502 6230 add.w r2, r2, #2816 ; 0xb00 80070b8: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 80070bc: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 80070be: 68bb ldr r3, [r7, #8] 80070c0: 015a lsls r2, r3, #5 80070c2: 68fb ldr r3, [r7, #12] 80070c4: 4413 add r3, r2 80070c6: f503 6330 add.w r3, r3, #2816 ; 0xb00 80070ca: 681b ldr r3, [r3, #0] 80070cc: 68ba ldr r2, [r7, #8] 80070ce: 0151 lsls r1, r2, #5 80070d0: 68fa ldr r2, [r7, #12] 80070d2: 440a add r2, r1 80070d4: f502 6230 add.w r2, r2, #2816 ; 0xb00 80070d8: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 80070dc: 6013 str r3, [r2, #0] } return HAL_OK; 80070de: 2300 movs r3, #0 } 80070e0: 4618 mov r0, r3 80070e2: 3714 adds r7, #20 80070e4: 46bd mov sp, r7 80070e6: f85d 7b04 ldr.w r7, [sp], #4 80070ea: 4770 bx lr 080070ec : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 80070ec: b480 push {r7} 80070ee: b085 sub sp, #20 80070f0: af00 add r7, sp, #0 80070f2: 6078 str r0, [r7, #4] 80070f4: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80070f6: 687b ldr r3, [r7, #4] 80070f8: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80070fa: 683b ldr r3, [r7, #0] 80070fc: 781b ldrb r3, [r3, #0] 80070fe: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8007100: 683b ldr r3, [r7, #0] 8007102: 785b ldrb r3, [r3, #1] 8007104: 2b01 cmp r3, #1 8007106: d128 bne.n 800715a { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8007108: 68bb ldr r3, [r7, #8] 800710a: 015a lsls r2, r3, #5 800710c: 68fb ldr r3, [r7, #12] 800710e: 4413 add r3, r2 8007110: f503 6310 add.w r3, r3, #2304 ; 0x900 8007114: 681b ldr r3, [r3, #0] 8007116: 68ba ldr r2, [r7, #8] 8007118: 0151 lsls r1, r2, #5 800711a: 68fa ldr r2, [r7, #12] 800711c: 440a add r2, r1 800711e: f502 6210 add.w r2, r2, #2304 ; 0x900 8007122: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 8007126: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8007128: 683b ldr r3, [r7, #0] 800712a: 78db ldrb r3, [r3, #3] 800712c: 2b03 cmp r3, #3 800712e: d003 beq.n 8007138 8007130: 683b ldr r3, [r7, #0] 8007132: 78db ldrb r3, [r3, #3] 8007134: 2b02 cmp r3, #2 8007136: d138 bne.n 80071aa { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8007138: 68bb ldr r3, [r7, #8] 800713a: 015a lsls r2, r3, #5 800713c: 68fb ldr r3, [r7, #12] 800713e: 4413 add r3, r2 8007140: f503 6310 add.w r3, r3, #2304 ; 0x900 8007144: 681b ldr r3, [r3, #0] 8007146: 68ba ldr r2, [r7, #8] 8007148: 0151 lsls r1, r2, #5 800714a: 68fa ldr r2, [r7, #12] 800714c: 440a add r2, r1 800714e: f502 6210 add.w r2, r2, #2304 ; 0x900 8007152: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8007156: 6013 str r3, [r2, #0] 8007158: e027 b.n 80071aa } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 800715a: 68bb ldr r3, [r7, #8] 800715c: 015a lsls r2, r3, #5 800715e: 68fb ldr r3, [r7, #12] 8007160: 4413 add r3, r2 8007162: f503 6330 add.w r3, r3, #2816 ; 0xb00 8007166: 681b ldr r3, [r3, #0] 8007168: 68ba ldr r2, [r7, #8] 800716a: 0151 lsls r1, r2, #5 800716c: 68fa ldr r2, [r7, #12] 800716e: 440a add r2, r1 8007170: f502 6230 add.w r2, r2, #2816 ; 0xb00 8007174: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 8007178: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 800717a: 683b ldr r3, [r7, #0] 800717c: 78db ldrb r3, [r3, #3] 800717e: 2b03 cmp r3, #3 8007180: d003 beq.n 800718a 8007182: 683b ldr r3, [r7, #0] 8007184: 78db ldrb r3, [r3, #3] 8007186: 2b02 cmp r3, #2 8007188: d10f bne.n 80071aa { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 800718a: 68bb ldr r3, [r7, #8] 800718c: 015a lsls r2, r3, #5 800718e: 68fb ldr r3, [r7, #12] 8007190: 4413 add r3, r2 8007192: f503 6330 add.w r3, r3, #2816 ; 0xb00 8007196: 681b ldr r3, [r3, #0] 8007198: 68ba ldr r2, [r7, #8] 800719a: 0151 lsls r1, r2, #5 800719c: 68fa ldr r2, [r7, #12] 800719e: 440a add r2, r1 80071a0: f502 6230 add.w r2, r2, #2816 ; 0xb00 80071a4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80071a8: 6013 str r3, [r2, #0] } } return HAL_OK; 80071aa: 2300 movs r3, #0 } 80071ac: 4618 mov r0, r3 80071ae: 3714 adds r7, #20 80071b0: 46bd mov sp, r7 80071b2: f85d 7b04 ldr.w r7, [sp], #4 80071b6: 4770 bx lr 080071b8 : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 80071b8: b480 push {r7} 80071ba: b085 sub sp, #20 80071bc: af00 add r7, sp, #0 80071be: 6078 str r0, [r7, #4] 80071c0: 460b mov r3, r1 80071c2: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80071c4: 687b ldr r3, [r7, #4] 80071c6: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 80071c8: 68fb ldr r3, [r7, #12] 80071ca: f503 6300 add.w r3, r3, #2048 ; 0x800 80071ce: 681b ldr r3, [r3, #0] 80071d0: 68fa ldr r2, [r7, #12] 80071d2: f502 6200 add.w r2, r2, #2048 ; 0x800 80071d6: f423 63fe bic.w r3, r3, #2032 ; 0x7f0 80071da: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 80071dc: 68fb ldr r3, [r7, #12] 80071de: f503 6300 add.w r3, r3, #2048 ; 0x800 80071e2: 681a ldr r2, [r3, #0] 80071e4: 78fb ldrb r3, [r7, #3] 80071e6: 011b lsls r3, r3, #4 80071e8: f403 63fe and.w r3, r3, #2032 ; 0x7f0 80071ec: 68f9 ldr r1, [r7, #12] 80071ee: f501 6100 add.w r1, r1, #2048 ; 0x800 80071f2: 4313 orrs r3, r2 80071f4: 600b str r3, [r1, #0] return HAL_OK; 80071f6: 2300 movs r3, #0 } 80071f8: 4618 mov r0, r3 80071fa: 3714 adds r7, #20 80071fc: 46bd mov sp, r7 80071fe: f85d 7b04 ldr.w r7, [sp], #4 8007202: 4770 bx lr 08007204 : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) { 8007204: b480 push {r7} 8007206: b085 sub sp, #20 8007208: af00 add r7, sp, #0 800720a: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800720c: 687b ldr r3, [r7, #4] 800720e: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8007210: 68fb ldr r3, [r7, #12] 8007212: f503 6360 add.w r3, r3, #3584 ; 0xe00 8007216: 681b ldr r3, [r3, #0] 8007218: 68fa ldr r2, [r7, #12] 800721a: f502 6260 add.w r2, r2, #3584 ; 0xe00 800721e: f023 0303 bic.w r3, r3, #3 8007222: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 8007224: 68fb ldr r3, [r7, #12] 8007226: f503 6300 add.w r3, r3, #2048 ; 0x800 800722a: 685b ldr r3, [r3, #4] 800722c: 68fa ldr r2, [r7, #12] 800722e: f502 6200 add.w r2, r2, #2048 ; 0x800 8007232: f023 0302 bic.w r3, r3, #2 8007236: 6053 str r3, [r2, #4] return HAL_OK; 8007238: 2300 movs r3, #0 } 800723a: 4618 mov r0, r3 800723c: 3714 adds r7, #20 800723e: 46bd mov sp, r7 8007240: f85d 7b04 ldr.w r7, [sp], #4 8007244: 4770 bx lr 08007246 : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) { 8007246: b480 push {r7} 8007248: b085 sub sp, #20 800724a: af00 add r7, sp, #0 800724c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800724e: 687b ldr r3, [r7, #4] 8007250: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8007252: 68fb ldr r3, [r7, #12] 8007254: f503 6360 add.w r3, r3, #3584 ; 0xe00 8007258: 681b ldr r3, [r3, #0] 800725a: 68fa ldr r2, [r7, #12] 800725c: f502 6260 add.w r2, r2, #3584 ; 0xe00 8007260: f023 0303 bic.w r3, r3, #3 8007264: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8007266: 68fb ldr r3, [r7, #12] 8007268: f503 6300 add.w r3, r3, #2048 ; 0x800 800726c: 685b ldr r3, [r3, #4] 800726e: 68fa ldr r2, [r7, #12] 8007270: f502 6200 add.w r2, r2, #2048 ; 0x800 8007274: f043 0302 orr.w r3, r3, #2 8007278: 6053 str r3, [r2, #4] return HAL_OK; 800727a: 2300 movs r3, #0 } 800727c: 4618 mov r0, r3 800727e: 3714 adds r7, #20 8007280: 46bd mov sp, r7 8007282: f85d 7b04 ldr.w r7, [sp], #4 8007286: 4770 bx lr 08007288 : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) { 8007288: b480 push {r7} 800728a: b085 sub sp, #20 800728c: af00 add r7, sp, #0 800728e: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 8007290: 687b ldr r3, [r7, #4] 8007292: 695b ldr r3, [r3, #20] 8007294: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 8007296: 687b ldr r3, [r7, #4] 8007298: 699b ldr r3, [r3, #24] 800729a: 68fa ldr r2, [r7, #12] 800729c: 4013 ands r3, r2 800729e: 60fb str r3, [r7, #12] return tmpreg; 80072a0: 68fb ldr r3, [r7, #12] } 80072a2: 4618 mov r0, r3 80072a4: 3714 adds r7, #20 80072a6: 46bd mov sp, r7 80072a8: f85d 7b04 ldr.w r7, [sp], #4 80072ac: 4770 bx lr 080072ae : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { 80072ae: b480 push {r7} 80072b0: b085 sub sp, #20 80072b2: af00 add r7, sp, #0 80072b4: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80072b6: 687b ldr r3, [r7, #4] 80072b8: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 80072ba: 68fb ldr r3, [r7, #12] 80072bc: f503 6300 add.w r3, r3, #2048 ; 0x800 80072c0: 699b ldr r3, [r3, #24] 80072c2: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 80072c4: 68fb ldr r3, [r7, #12] 80072c6: f503 6300 add.w r3, r3, #2048 ; 0x800 80072ca: 69db ldr r3, [r3, #28] 80072cc: 68ba ldr r2, [r7, #8] 80072ce: 4013 ands r3, r2 80072d0: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 80072d2: 68bb ldr r3, [r7, #8] 80072d4: 0c1b lsrs r3, r3, #16 } 80072d6: 4618 mov r0, r3 80072d8: 3714 adds r7, #20 80072da: 46bd mov sp, r7 80072dc: f85d 7b04 ldr.w r7, [sp], #4 80072e0: 4770 bx lr 080072e2 : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { 80072e2: b480 push {r7} 80072e4: b085 sub sp, #20 80072e6: af00 add r7, sp, #0 80072e8: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80072ea: 687b ldr r3, [r7, #4] 80072ec: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 80072ee: 68fb ldr r3, [r7, #12] 80072f0: f503 6300 add.w r3, r3, #2048 ; 0x800 80072f4: 699b ldr r3, [r3, #24] 80072f6: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 80072f8: 68fb ldr r3, [r7, #12] 80072fa: f503 6300 add.w r3, r3, #2048 ; 0x800 80072fe: 69db ldr r3, [r3, #28] 8007300: 68ba ldr r2, [r7, #8] 8007302: 4013 ands r3, r2 8007304: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 8007306: 68bb ldr r3, [r7, #8] 8007308: b29b uxth r3, r3 } 800730a: 4618 mov r0, r3 800730c: 3714 adds r7, #20 800730e: 46bd mov sp, r7 8007310: f85d 7b04 ldr.w r7, [sp], #4 8007314: 4770 bx lr 08007316 : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 8007316: b480 push {r7} 8007318: b085 sub sp, #20 800731a: af00 add r7, sp, #0 800731c: 6078 str r0, [r7, #4] 800731e: 460b mov r3, r1 8007320: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8007322: 687b ldr r3, [r7, #4] 8007324: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 8007326: 78fb ldrb r3, [r7, #3] 8007328: 015a lsls r2, r3, #5 800732a: 68fb ldr r3, [r7, #12] 800732c: 4413 add r3, r2 800732e: f503 6330 add.w r3, r3, #2816 ; 0xb00 8007332: 689b ldr r3, [r3, #8] 8007334: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 8007336: 68fb ldr r3, [r7, #12] 8007338: f503 6300 add.w r3, r3, #2048 ; 0x800 800733c: 695b ldr r3, [r3, #20] 800733e: 68ba ldr r2, [r7, #8] 8007340: 4013 ands r3, r2 8007342: 60bb str r3, [r7, #8] return tmpreg; 8007344: 68bb ldr r3, [r7, #8] } 8007346: 4618 mov r0, r3 8007348: 3714 adds r7, #20 800734a: 46bd mov sp, r7 800734c: f85d 7b04 ldr.w r7, [sp], #4 8007350: 4770 bx lr 08007352 : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 8007352: b480 push {r7} 8007354: b087 sub sp, #28 8007356: af00 add r7, sp, #0 8007358: 6078 str r0, [r7, #4] 800735a: 460b mov r3, r1 800735c: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 800735e: 687b ldr r3, [r7, #4] 8007360: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 8007362: 697b ldr r3, [r7, #20] 8007364: f503 6300 add.w r3, r3, #2048 ; 0x800 8007368: 691b ldr r3, [r3, #16] 800736a: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 800736c: 697b ldr r3, [r7, #20] 800736e: f503 6300 add.w r3, r3, #2048 ; 0x800 8007372: 6b5b ldr r3, [r3, #52] ; 0x34 8007374: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 8007376: 78fb ldrb r3, [r7, #3] 8007378: f003 030f and.w r3, r3, #15 800737c: 68fa ldr r2, [r7, #12] 800737e: fa22 f303 lsr.w r3, r2, r3 8007382: 01db lsls r3, r3, #7 8007384: b2db uxtb r3, r3 8007386: 693a ldr r2, [r7, #16] 8007388: 4313 orrs r3, r2 800738a: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 800738c: 78fb ldrb r3, [r7, #3] 800738e: 015a lsls r2, r3, #5 8007390: 697b ldr r3, [r7, #20] 8007392: 4413 add r3, r2 8007394: f503 6310 add.w r3, r3, #2304 ; 0x900 8007398: 689b ldr r3, [r3, #8] 800739a: 693a ldr r2, [r7, #16] 800739c: 4013 ands r3, r2 800739e: 60bb str r3, [r7, #8] return tmpreg; 80073a0: 68bb ldr r3, [r7, #8] } 80073a2: 4618 mov r0, r3 80073a4: 371c adds r7, #28 80073a6: 46bd mov sp, r7 80073a8: f85d 7b04 ldr.w r7, [sp], #4 80073ac: 4770 bx lr 080073ae : * This parameter can be one of these values: * 0 : Host * 1 : Device */ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) { 80073ae: b480 push {r7} 80073b0: b083 sub sp, #12 80073b2: af00 add r7, sp, #0 80073b4: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 80073b6: 687b ldr r3, [r7, #4] 80073b8: 695b ldr r3, [r3, #20] 80073ba: f003 0301 and.w r3, r3, #1 } 80073be: 4618 mov r0, r3 80073c0: 370c adds r7, #12 80073c2: 46bd mov sp, r7 80073c4: f85d 7b04 ldr.w r7, [sp], #4 80073c8: 4770 bx lr ... 080073cc : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) { 80073cc: b480 push {r7} 80073ce: b085 sub sp, #20 80073d0: af00 add r7, sp, #0 80073d2: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80073d4: 687b ldr r3, [r7, #4] 80073d6: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 80073d8: 68fb ldr r3, [r7, #12] 80073da: f503 6310 add.w r3, r3, #2304 ; 0x900 80073de: 681a ldr r2, [r3, #0] 80073e0: 68fb ldr r3, [r7, #12] 80073e2: f503 6310 add.w r3, r3, #2304 ; 0x900 80073e6: 4619 mov r1, r3 80073e8: 4b09 ldr r3, [pc, #36] ; (8007410 ) 80073ea: 4013 ands r3, r2 80073ec: 600b str r3, [r1, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 80073ee: 68fb ldr r3, [r7, #12] 80073f0: f503 6300 add.w r3, r3, #2048 ; 0x800 80073f4: 685b ldr r3, [r3, #4] 80073f6: 68fa ldr r2, [r7, #12] 80073f8: f502 6200 add.w r2, r2, #2048 ; 0x800 80073fc: f443 7380 orr.w r3, r3, #256 ; 0x100 8007400: 6053 str r3, [r2, #4] return HAL_OK; 8007402: 2300 movs r3, #0 } 8007404: 4618 mov r0, r3 8007406: 3714 adds r7, #20 8007408: 46bd mov sp, r7 800740a: f85d 7b04 ldr.w r7, [sp], #4 800740e: 4770 bx lr 8007410: fffff800 .word 0xfffff800 08007414 : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) { 8007414: b480 push {r7} 8007416: b087 sub sp, #28 8007418: af00 add r7, sp, #0 800741a: 60f8 str r0, [r7, #12] 800741c: 460b mov r3, r1 800741e: 607a str r2, [r7, #4] 8007420: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 8007422: 68fb ldr r3, [r7, #12] 8007424: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); 8007426: 68fb ldr r3, [r7, #12] 8007428: 333c adds r3, #60 ; 0x3c 800742a: 3304 adds r3, #4 800742c: 681b ldr r3, [r3, #0] 800742e: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 8007430: 693b ldr r3, [r7, #16] 8007432: 4a26 ldr r2, [pc, #152] ; (80074cc ) 8007434: 4293 cmp r3, r2 8007436: d90a bls.n 800744e { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007438: 697b ldr r3, [r7, #20] 800743a: f503 6330 add.w r3, r3, #2816 ; 0xb00 800743e: 681b ldr r3, [r3, #0] 8007440: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8007444: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8007448: d101 bne.n 800744e { return HAL_OK; 800744a: 2300 movs r3, #0 800744c: e037 b.n 80074be } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 800744e: 697b ldr r3, [r7, #20] 8007450: f503 6330 add.w r3, r3, #2816 ; 0xb00 8007454: 461a mov r2, r3 8007456: 2300 movs r3, #0 8007458: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 800745a: 697b ldr r3, [r7, #20] 800745c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8007460: 691b ldr r3, [r3, #16] 8007462: 697a ldr r2, [r7, #20] 8007464: f502 6230 add.w r2, r2, #2816 ; 0xb00 8007468: f443 2300 orr.w r3, r3, #524288 ; 0x80000 800746c: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 800746e: 697b ldr r3, [r7, #20] 8007470: f503 6330 add.w r3, r3, #2816 ; 0xb00 8007474: 691b ldr r3, [r3, #16] 8007476: 697a ldr r2, [r7, #20] 8007478: f502 6230 add.w r2, r2, #2816 ; 0xb00 800747c: f043 0318 orr.w r3, r3, #24 8007480: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 8007482: 697b ldr r3, [r7, #20] 8007484: f503 6330 add.w r3, r3, #2816 ; 0xb00 8007488: 691b ldr r3, [r3, #16] 800748a: 697a ldr r2, [r7, #20] 800748c: f502 6230 add.w r2, r2, #2816 ; 0xb00 8007490: f043 43c0 orr.w r3, r3, #1610612736 ; 0x60000000 8007494: 6113 str r3, [r2, #16] if (dma == 1U) 8007496: 7afb ldrb r3, [r7, #11] 8007498: 2b01 cmp r3, #1 800749a: d10f bne.n 80074bc { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 800749c: 697b ldr r3, [r7, #20] 800749e: f503 6330 add.w r3, r3, #2816 ; 0xb00 80074a2: 461a mov r2, r3 80074a4: 687b ldr r3, [r7, #4] 80074a6: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 80074a8: 697b ldr r3, [r7, #20] 80074aa: f503 6330 add.w r3, r3, #2816 ; 0xb00 80074ae: 681b ldr r3, [r3, #0] 80074b0: 697a ldr r2, [r7, #20] 80074b2: f502 6230 add.w r2, r2, #2816 ; 0xb00 80074b6: f043 2380 orr.w r3, r3, #2147516416 ; 0x80008000 80074ba: 6013 str r3, [r2, #0] } return HAL_OK; 80074bc: 2300 movs r3, #0 } 80074be: 4618 mov r0, r3 80074c0: 371c adds r7, #28 80074c2: 46bd mov sp, r7 80074c4: f85d 7b04 ldr.w r7, [sp], #4 80074c8: 4770 bx lr 80074ca: bf00 nop 80074cc: 4f54300a .word 0x4f54300a 080074d0 : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 80074d0: b480 push {r7} 80074d2: b085 sub sp, #20 80074d4: af00 add r7, sp, #0 80074d6: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 80074d8: 2300 movs r3, #0 80074da: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { if (++count > 200000U) 80074dc: 68fb ldr r3, [r7, #12] 80074de: 3301 adds r3, #1 80074e0: 60fb str r3, [r7, #12] 80074e2: 4a13 ldr r2, [pc, #76] ; (8007530 ) 80074e4: 4293 cmp r3, r2 80074e6: d901 bls.n 80074ec { return HAL_TIMEOUT; 80074e8: 2303 movs r3, #3 80074ea: e01a b.n 8007522 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80074ec: 687b ldr r3, [r7, #4] 80074ee: 691b ldr r3, [r3, #16] 80074f0: 2b00 cmp r3, #0 80074f2: daf3 bge.n 80074dc /* Core Soft Reset */ count = 0U; 80074f4: 2300 movs r3, #0 80074f6: 60fb str r3, [r7, #12] USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 80074f8: 687b ldr r3, [r7, #4] 80074fa: 691b ldr r3, [r3, #16] 80074fc: f043 0201 orr.w r2, r3, #1 8007500: 687b ldr r3, [r7, #4] 8007502: 611a str r2, [r3, #16] do { if (++count > 200000U) 8007504: 68fb ldr r3, [r7, #12] 8007506: 3301 adds r3, #1 8007508: 60fb str r3, [r7, #12] 800750a: 4a09 ldr r2, [pc, #36] ; (8007530 ) 800750c: 4293 cmp r3, r2 800750e: d901 bls.n 8007514 { return HAL_TIMEOUT; 8007510: 2303 movs r3, #3 8007512: e006 b.n 8007522 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 8007514: 687b ldr r3, [r7, #4] 8007516: 691b ldr r3, [r3, #16] 8007518: f003 0301 and.w r3, r3, #1 800751c: 2b01 cmp r3, #1 800751e: d0f1 beq.n 8007504 return HAL_OK; 8007520: 2300 movs r3, #0 } 8007522: 4618 mov r0, r3 8007524: 3714 adds r7, #20 8007526: 46bd mov sp, r7 8007528: f85d 7b04 ldr.w r7, [sp], #4 800752c: 4770 bx lr 800752e: bf00 nop 8007530: 00030d40 .word 0x00030d40 08007534 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8007534: b580 push {r7, lr} 8007536: b084 sub sp, #16 8007538: af00 add r7, sp, #0 800753a: 6078 str r0, [r7, #4] 800753c: 460b mov r3, r1 800753e: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_CDC_HandleTypeDef *hcdc; hcdc = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); 8007540: f44f 7007 mov.w r0, #540 ; 0x21c 8007544: f002 f986 bl 8009854 8007548: 60f8 str r0, [r7, #12] if (hcdc == NULL) 800754a: 68fb ldr r3, [r7, #12] 800754c: 2b00 cmp r3, #0 800754e: d105 bne.n 800755c { pdev->pClassData = NULL; 8007550: 687b ldr r3, [r7, #4] 8007552: 2200 movs r2, #0 8007554: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc return (uint8_t)USBD_EMEM; 8007558: 2302 movs r3, #2 800755a: e066 b.n 800762a } pdev->pClassData = (void *)hcdc; 800755c: 687b ldr r3, [r7, #4] 800755e: 68fa ldr r2, [r7, #12] 8007560: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc if (pdev->dev_speed == USBD_SPEED_HIGH) 8007564: 687b ldr r3, [r7, #4] 8007566: 7c1b ldrb r3, [r3, #16] 8007568: 2b00 cmp r3, #0 800756a: d119 bne.n 80075a0 { /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, 800756c: f44f 7300 mov.w r3, #512 ; 0x200 8007570: 2202 movs r2, #2 8007572: 2181 movs r1, #129 ; 0x81 8007574: 6878 ldr r0, [r7, #4] 8007576: f002 f84a bl 800960e CDC_DATA_HS_IN_PACKET_SIZE); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; 800757a: 687b ldr r3, [r7, #4] 800757c: 2201 movs r2, #1 800757e: 871a strh r2, [r3, #56] ; 0x38 /* Open EP OUT */ (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, 8007580: f44f 7300 mov.w r3, #512 ; 0x200 8007584: 2202 movs r2, #2 8007586: 2101 movs r1, #1 8007588: 6878 ldr r0, [r7, #4] 800758a: f002 f840 bl 800960e CDC_DATA_HS_OUT_PACKET_SIZE); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; 800758e: 687b ldr r3, [r7, #4] 8007590: 2201 movs r2, #1 8007592: f8a3 2178 strh.w r2, [r3, #376] ; 0x178 /* Set bInterval for CDC CMD Endpoint */ pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_HS_BINTERVAL; 8007596: 687b ldr r3, [r7, #4] 8007598: 2210 movs r2, #16 800759a: f8a3 204e strh.w r2, [r3, #78] ; 0x4e 800759e: e016 b.n 80075ce } else { /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, 80075a0: 2340 movs r3, #64 ; 0x40 80075a2: 2202 movs r2, #2 80075a4: 2181 movs r1, #129 ; 0x81 80075a6: 6878 ldr r0, [r7, #4] 80075a8: f002 f831 bl 800960e CDC_DATA_FS_IN_PACKET_SIZE); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; 80075ac: 687b ldr r3, [r7, #4] 80075ae: 2201 movs r2, #1 80075b0: 871a strh r2, [r3, #56] ; 0x38 /* Open EP OUT */ (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, 80075b2: 2340 movs r3, #64 ; 0x40 80075b4: 2202 movs r2, #2 80075b6: 2101 movs r1, #1 80075b8: 6878 ldr r0, [r7, #4] 80075ba: f002 f828 bl 800960e CDC_DATA_FS_OUT_PACKET_SIZE); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; 80075be: 687b ldr r3, [r7, #4] 80075c0: 2201 movs r2, #1 80075c2: f8a3 2178 strh.w r2, [r3, #376] ; 0x178 /* Set bInterval for CMD Endpoint */ pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_FS_BINTERVAL; 80075c6: 687b ldr r3, [r7, #4] 80075c8: 2210 movs r2, #16 80075ca: f8a3 204e strh.w r2, [r3, #78] ; 0x4e } /* Open Command IN EP */ (void)USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); 80075ce: 2308 movs r3, #8 80075d0: 2203 movs r2, #3 80075d2: 2182 movs r1, #130 ; 0x82 80075d4: 6878 ldr r0, [r7, #4] 80075d6: f002 f81a bl 800960e pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U; 80075da: 687b ldr r3, [r7, #4] 80075dc: 2201 movs r2, #1 80075de: f8a3 204c strh.w r2, [r3, #76] ; 0x4c /* Init physical Interface components */ ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); 80075e2: 687b ldr r3, [r7, #4] 80075e4: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 80075e8: 681b ldr r3, [r3, #0] 80075ea: 4798 blx r3 /* Init Xfer states */ hcdc->TxState = 0U; 80075ec: 68fb ldr r3, [r7, #12] 80075ee: 2200 movs r2, #0 80075f0: f8c3 2214 str.w r2, [r3, #532] ; 0x214 hcdc->RxState = 0U; 80075f4: 68fb ldr r3, [r7, #12] 80075f6: 2200 movs r2, #0 80075f8: f8c3 2218 str.w r2, [r3, #536] ; 0x218 if (pdev->dev_speed == USBD_SPEED_HIGH) 80075fc: 687b ldr r3, [r7, #4] 80075fe: 7c1b ldrb r3, [r3, #16] 8007600: 2b00 cmp r3, #0 8007602: d109 bne.n 8007618 { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 8007604: 68fb ldr r3, [r7, #12] 8007606: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 800760a: f44f 7300 mov.w r3, #512 ; 0x200 800760e: 2101 movs r1, #1 8007610: 6878 ldr r0, [r7, #4] 8007612: f002 f8eb bl 80097ec 8007616: e007 b.n 8007628 CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 8007618: 68fb ldr r3, [r7, #12] 800761a: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 800761e: 2340 movs r3, #64 ; 0x40 8007620: 2101 movs r1, #1 8007622: 6878 ldr r0, [r7, #4] 8007624: f002 f8e2 bl 80097ec CDC_DATA_FS_OUT_PACKET_SIZE); } return (uint8_t)USBD_OK; 8007628: 2300 movs r3, #0 } 800762a: 4618 mov r0, r3 800762c: 3710 adds r7, #16 800762e: 46bd mov sp, r7 8007630: bd80 pop {r7, pc} 08007632 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8007632: b580 push {r7, lr} 8007634: b082 sub sp, #8 8007636: af00 add r7, sp, #0 8007638: 6078 str r0, [r7, #4] 800763a: 460b mov r3, r1 800763c: 70fb strb r3, [r7, #3] UNUSED(cfgidx); /* Close EP IN */ (void)USBD_LL_CloseEP(pdev, CDC_IN_EP); 800763e: 2181 movs r1, #129 ; 0x81 8007640: 6878 ldr r0, [r7, #4] 8007642: f002 f80a bl 800965a pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U; 8007646: 687b ldr r3, [r7, #4] 8007648: 2200 movs r2, #0 800764a: 871a strh r2, [r3, #56] ; 0x38 /* Close EP OUT */ (void)USBD_LL_CloseEP(pdev, CDC_OUT_EP); 800764c: 2101 movs r1, #1 800764e: 6878 ldr r0, [r7, #4] 8007650: f002 f803 bl 800965a pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U; 8007654: 687b ldr r3, [r7, #4] 8007656: 2200 movs r2, #0 8007658: f8a3 2178 strh.w r2, [r3, #376] ; 0x178 /* Close Command IN EP */ (void)USBD_LL_CloseEP(pdev, CDC_CMD_EP); 800765c: 2182 movs r1, #130 ; 0x82 800765e: 6878 ldr r0, [r7, #4] 8007660: f001 fffb bl 800965a pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U; 8007664: 687b ldr r3, [r7, #4] 8007666: 2200 movs r2, #0 8007668: f8a3 204c strh.w r2, [r3, #76] ; 0x4c pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = 0U; 800766c: 687b ldr r3, [r7, #4] 800766e: 2200 movs r2, #0 8007670: f8a3 204e strh.w r2, [r3, #78] ; 0x4e /* DeInit physical Interface components */ if (pdev->pClassData != NULL) 8007674: 687b ldr r3, [r7, #4] 8007676: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 800767a: 2b00 cmp r3, #0 800767c: d00e beq.n 800769c { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); 800767e: 687b ldr r3, [r7, #4] 8007680: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8007684: 685b ldr r3, [r3, #4] 8007686: 4798 blx r3 (void)USBD_free(pdev->pClassData); 8007688: 687b ldr r3, [r7, #4] 800768a: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 800768e: 4618 mov r0, r3 8007690: f002 f8ee bl 8009870 pdev->pClassData = NULL; 8007694: 687b ldr r3, [r7, #4] 8007696: 2200 movs r2, #0 8007698: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc } return (uint8_t)USBD_OK; 800769c: 2300 movs r3, #0 } 800769e: 4618 mov r0, r3 80076a0: 3708 adds r7, #8 80076a2: 46bd mov sp, r7 80076a4: bd80 pop {r7, pc} ... 080076a8 : * @param req: usb requests * @retval status */ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80076a8: b580 push {r7, lr} 80076aa: b086 sub sp, #24 80076ac: af00 add r7, sp, #0 80076ae: 6078 str r0, [r7, #4] 80076b0: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 80076b2: 687b ldr r3, [r7, #4] 80076b4: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 80076b8: 613b str r3, [r7, #16] uint16_t len; uint8_t ifalt = 0U; 80076ba: 2300 movs r3, #0 80076bc: 737b strb r3, [r7, #13] uint16_t status_info = 0U; 80076be: 2300 movs r3, #0 80076c0: 817b strh r3, [r7, #10] USBD_StatusTypeDef ret = USBD_OK; 80076c2: 2300 movs r3, #0 80076c4: 75fb strb r3, [r7, #23] if (hcdc == NULL) 80076c6: 693b ldr r3, [r7, #16] 80076c8: 2b00 cmp r3, #0 80076ca: d101 bne.n 80076d0 { return (uint8_t)USBD_FAIL; 80076cc: 2303 movs r3, #3 80076ce: e0af b.n 8007830 } switch (req->bmRequest & USB_REQ_TYPE_MASK) 80076d0: 683b ldr r3, [r7, #0] 80076d2: 781b ldrb r3, [r3, #0] 80076d4: f003 0360 and.w r3, r3, #96 ; 0x60 80076d8: 2b00 cmp r3, #0 80076da: d03f beq.n 800775c 80076dc: 2b20 cmp r3, #32 80076de: f040 809f bne.w 8007820 { case USB_REQ_TYPE_CLASS: if (req->wLength != 0U) 80076e2: 683b ldr r3, [r7, #0] 80076e4: 88db ldrh r3, [r3, #6] 80076e6: 2b00 cmp r3, #0 80076e8: d02e beq.n 8007748 { if ((req->bmRequest & 0x80U) != 0U) 80076ea: 683b ldr r3, [r7, #0] 80076ec: 781b ldrb r3, [r3, #0] 80076ee: b25b sxtb r3, r3 80076f0: 2b00 cmp r3, #0 80076f2: da16 bge.n 8007722 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 80076f4: 687b ldr r3, [r7, #4] 80076f6: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 80076fa: 689b ldr r3, [r3, #8] 80076fc: 683a ldr r2, [r7, #0] 80076fe: 7850 ldrb r0, [r2, #1] (uint8_t *)hcdc->data, 8007700: 6939 ldr r1, [r7, #16] ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 8007702: 683a ldr r2, [r7, #0] 8007704: 88d2 ldrh r2, [r2, #6] 8007706: 4798 blx r3 req->wLength); len = MIN(CDC_REQ_MAX_DATA_SIZE, req->wLength); 8007708: 683b ldr r3, [r7, #0] 800770a: 88db ldrh r3, [r3, #6] 800770c: 2b07 cmp r3, #7 800770e: bf28 it cs 8007710: 2307 movcs r3, #7 8007712: 81fb strh r3, [r7, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, len); 8007714: 693b ldr r3, [r7, #16] 8007716: 89fa ldrh r2, [r7, #14] 8007718: 4619 mov r1, r3 800771a: 6878 ldr r0, [r7, #4] 800771c: f001 fb19 bl 8008d52 else { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, (uint8_t *)req, 0U); } break; 8007720: e085 b.n 800782e hcdc->CmdOpCode = req->bRequest; 8007722: 683b ldr r3, [r7, #0] 8007724: 785a ldrb r2, [r3, #1] 8007726: 693b ldr r3, [r7, #16] 8007728: f883 2200 strb.w r2, [r3, #512] ; 0x200 hcdc->CmdLength = (uint8_t)req->wLength; 800772c: 683b ldr r3, [r7, #0] 800772e: 88db ldrh r3, [r3, #6] 8007730: b2da uxtb r2, r3 8007732: 693b ldr r3, [r7, #16] 8007734: f883 2201 strb.w r2, [r3, #513] ; 0x201 (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, req->wLength); 8007738: 6939 ldr r1, [r7, #16] 800773a: 683b ldr r3, [r7, #0] 800773c: 88db ldrh r3, [r3, #6] 800773e: 461a mov r2, r3 8007740: 6878 ldr r0, [r7, #4] 8007742: f001 fb32 bl 8008daa break; 8007746: e072 b.n 800782e ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 8007748: 687b ldr r3, [r7, #4] 800774a: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 800774e: 689b ldr r3, [r3, #8] 8007750: 683a ldr r2, [r7, #0] 8007752: 7850 ldrb r0, [r2, #1] 8007754: 2200 movs r2, #0 8007756: 6839 ldr r1, [r7, #0] 8007758: 4798 blx r3 break; 800775a: e068 b.n 800782e case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 800775c: 683b ldr r3, [r7, #0] 800775e: 785b ldrb r3, [r3, #1] 8007760: 2b0b cmp r3, #11 8007762: d852 bhi.n 800780a 8007764: a201 add r2, pc, #4 ; (adr r2, 800776c ) 8007766: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800776a: bf00 nop 800776c: 0800779d .word 0x0800779d 8007770: 08007819 .word 0x08007819 8007774: 0800780b .word 0x0800780b 8007778: 0800780b .word 0x0800780b 800777c: 0800780b .word 0x0800780b 8007780: 0800780b .word 0x0800780b 8007784: 0800780b .word 0x0800780b 8007788: 0800780b .word 0x0800780b 800778c: 0800780b .word 0x0800780b 8007790: 0800780b .word 0x0800780b 8007794: 080077c7 .word 0x080077c7 8007798: 080077f1 .word 0x080077f1 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 800779c: 687b ldr r3, [r7, #4] 800779e: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80077a2: b2db uxtb r3, r3 80077a4: 2b03 cmp r3, #3 80077a6: d107 bne.n 80077b8 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 80077a8: f107 030a add.w r3, r7, #10 80077ac: 2202 movs r2, #2 80077ae: 4619 mov r1, r3 80077b0: 6878 ldr r0, [r7, #4] 80077b2: f001 face bl 8008d52 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80077b6: e032 b.n 800781e USBD_CtlError(pdev, req); 80077b8: 6839 ldr r1, [r7, #0] 80077ba: 6878 ldr r0, [r7, #4] 80077bc: f001 fa58 bl 8008c70 ret = USBD_FAIL; 80077c0: 2303 movs r3, #3 80077c2: 75fb strb r3, [r7, #23] break; 80077c4: e02b b.n 800781e case USB_REQ_GET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 80077c6: 687b ldr r3, [r7, #4] 80077c8: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80077cc: b2db uxtb r3, r3 80077ce: 2b03 cmp r3, #3 80077d0: d107 bne.n 80077e2 { (void)USBD_CtlSendData(pdev, &ifalt, 1U); 80077d2: f107 030d add.w r3, r7, #13 80077d6: 2201 movs r2, #1 80077d8: 4619 mov r1, r3 80077da: 6878 ldr r0, [r7, #4] 80077dc: f001 fab9 bl 8008d52 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80077e0: e01d b.n 800781e USBD_CtlError(pdev, req); 80077e2: 6839 ldr r1, [r7, #0] 80077e4: 6878 ldr r0, [r7, #4] 80077e6: f001 fa43 bl 8008c70 ret = USBD_FAIL; 80077ea: 2303 movs r3, #3 80077ec: 75fb strb r3, [r7, #23] break; 80077ee: e016 b.n 800781e case USB_REQ_SET_INTERFACE: if (pdev->dev_state != USBD_STATE_CONFIGURED) 80077f0: 687b ldr r3, [r7, #4] 80077f2: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80077f6: b2db uxtb r3, r3 80077f8: 2b03 cmp r3, #3 80077fa: d00f beq.n 800781c { USBD_CtlError(pdev, req); 80077fc: 6839 ldr r1, [r7, #0] 80077fe: 6878 ldr r0, [r7, #4] 8007800: f001 fa36 bl 8008c70 ret = USBD_FAIL; 8007804: 2303 movs r3, #3 8007806: 75fb strb r3, [r7, #23] } break; 8007808: e008 b.n 800781c case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 800780a: 6839 ldr r1, [r7, #0] 800780c: 6878 ldr r0, [r7, #4] 800780e: f001 fa2f bl 8008c70 ret = USBD_FAIL; 8007812: 2303 movs r3, #3 8007814: 75fb strb r3, [r7, #23] break; 8007816: e002 b.n 800781e break; 8007818: bf00 nop 800781a: e008 b.n 800782e break; 800781c: bf00 nop } break; 800781e: e006 b.n 800782e default: USBD_CtlError(pdev, req); 8007820: 6839 ldr r1, [r7, #0] 8007822: 6878 ldr r0, [r7, #4] 8007824: f001 fa24 bl 8008c70 ret = USBD_FAIL; 8007828: 2303 movs r3, #3 800782a: 75fb strb r3, [r7, #23] break; 800782c: bf00 nop } return (uint8_t)ret; 800782e: 7dfb ldrb r3, [r7, #23] } 8007830: 4618 mov r0, r3 8007832: 3718 adds r7, #24 8007834: 46bd mov sp, r7 8007836: bd80 pop {r7, pc} 08007838 : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8007838: b580 push {r7, lr} 800783a: b084 sub sp, #16 800783c: af00 add r7, sp, #0 800783e: 6078 str r0, [r7, #4] 8007840: 460b mov r3, r1 8007842: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc; PCD_HandleTypeDef *hpcd = pdev->pData; 8007844: 687b ldr r3, [r7, #4] 8007846: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 800784a: 60fb str r3, [r7, #12] if (pdev->pClassData == NULL) 800784c: 687b ldr r3, [r7, #4] 800784e: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007852: 2b00 cmp r3, #0 8007854: d101 bne.n 800785a { return (uint8_t)USBD_FAIL; 8007856: 2303 movs r3, #3 8007858: e04f b.n 80078fa } hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 800785a: 687b ldr r3, [r7, #4] 800785c: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007860: 60bb str r3, [r7, #8] if ((pdev->ep_in[epnum].total_length > 0U) && 8007862: 78fa ldrb r2, [r7, #3] 8007864: 6879 ldr r1, [r7, #4] 8007866: 4613 mov r3, r2 8007868: 009b lsls r3, r3, #2 800786a: 4413 add r3, r2 800786c: 009b lsls r3, r3, #2 800786e: 440b add r3, r1 8007870: 3318 adds r3, #24 8007872: 681b ldr r3, [r3, #0] 8007874: 2b00 cmp r3, #0 8007876: d029 beq.n 80078cc ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U)) 8007878: 78fa ldrb r2, [r7, #3] 800787a: 6879 ldr r1, [r7, #4] 800787c: 4613 mov r3, r2 800787e: 009b lsls r3, r3, #2 8007880: 4413 add r3, r2 8007882: 009b lsls r3, r3, #2 8007884: 440b add r3, r1 8007886: 3318 adds r3, #24 8007888: 681a ldr r2, [r3, #0] 800788a: 78f9 ldrb r1, [r7, #3] 800788c: 68f8 ldr r0, [r7, #12] 800788e: 460b mov r3, r1 8007890: 00db lsls r3, r3, #3 8007892: 1a5b subs r3, r3, r1 8007894: 009b lsls r3, r3, #2 8007896: 4403 add r3, r0 8007898: 3344 adds r3, #68 ; 0x44 800789a: 681b ldr r3, [r3, #0] 800789c: fbb2 f1f3 udiv r1, r2, r3 80078a0: fb03 f301 mul.w r3, r3, r1 80078a4: 1ad3 subs r3, r2, r3 if ((pdev->ep_in[epnum].total_length > 0U) && 80078a6: 2b00 cmp r3, #0 80078a8: d110 bne.n 80078cc { /* Update the packet total length */ pdev->ep_in[epnum].total_length = 0U; 80078aa: 78fa ldrb r2, [r7, #3] 80078ac: 6879 ldr r1, [r7, #4] 80078ae: 4613 mov r3, r2 80078b0: 009b lsls r3, r3, #2 80078b2: 4413 add r3, r2 80078b4: 009b lsls r3, r3, #2 80078b6: 440b add r3, r1 80078b8: 3318 adds r3, #24 80078ba: 2200 movs r2, #0 80078bc: 601a str r2, [r3, #0] /* Send ZLP */ (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U); 80078be: 78f9 ldrb r1, [r7, #3] 80078c0: 2300 movs r3, #0 80078c2: 2200 movs r2, #0 80078c4: 6878 ldr r0, [r7, #4] 80078c6: f001 ff70 bl 80097aa 80078ca: e015 b.n 80078f8 } else { hcdc->TxState = 0U; 80078cc: 68bb ldr r3, [r7, #8] 80078ce: 2200 movs r2, #0 80078d0: f8c3 2214 str.w r2, [r3, #532] ; 0x214 if (((USBD_CDC_ItfTypeDef *)pdev->pUserData)->TransmitCplt != NULL) 80078d4: 687b ldr r3, [r7, #4] 80078d6: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 80078da: 691b ldr r3, [r3, #16] 80078dc: 2b00 cmp r3, #0 80078de: d00b beq.n 80078f8 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum); 80078e0: 687b ldr r3, [r7, #4] 80078e2: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 80078e6: 691b ldr r3, [r3, #16] 80078e8: 68ba ldr r2, [r7, #8] 80078ea: f8d2 0208 ldr.w r0, [r2, #520] ; 0x208 80078ee: 68ba ldr r2, [r7, #8] 80078f0: f502 7104 add.w r1, r2, #528 ; 0x210 80078f4: 78fa ldrb r2, [r7, #3] 80078f6: 4798 blx r3 } } return (uint8_t)USBD_OK; 80078f8: 2300 movs r3, #0 } 80078fa: 4618 mov r0, r3 80078fc: 3710 adds r7, #16 80078fe: 46bd mov sp, r7 8007900: bd80 pop {r7, pc} 08007902 : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8007902: b580 push {r7, lr} 8007904: b084 sub sp, #16 8007906: af00 add r7, sp, #0 8007908: 6078 str r0, [r7, #4] 800790a: 460b mov r3, r1 800790c: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 800790e: 687b ldr r3, [r7, #4] 8007910: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007914: 60fb str r3, [r7, #12] if (pdev->pClassData == NULL) 8007916: 687b ldr r3, [r7, #4] 8007918: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 800791c: 2b00 cmp r3, #0 800791e: d101 bne.n 8007924 { return (uint8_t)USBD_FAIL; 8007920: 2303 movs r3, #3 8007922: e015 b.n 8007950 } /* Get the received data length */ hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); 8007924: 78fb ldrb r3, [r7, #3] 8007926: 4619 mov r1, r3 8007928: 6878 ldr r0, [r7, #4] 800792a: f001 ff80 bl 800982e 800792e: 4602 mov r2, r0 8007930: 68fb ldr r3, [r7, #12] 8007932: f8c3 220c str.w r2, [r3, #524] ; 0x20c /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); 8007936: 687b ldr r3, [r7, #4] 8007938: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 800793c: 68db ldr r3, [r3, #12] 800793e: 68fa ldr r2, [r7, #12] 8007940: f8d2 0204 ldr.w r0, [r2, #516] ; 0x204 8007944: 68fa ldr r2, [r7, #12] 8007946: f502 7203 add.w r2, r2, #524 ; 0x20c 800794a: 4611 mov r1, r2 800794c: 4798 blx r3 return (uint8_t)USBD_OK; 800794e: 2300 movs r3, #0 } 8007950: 4618 mov r0, r3 8007952: 3710 adds r7, #16 8007954: 46bd mov sp, r7 8007956: bd80 pop {r7, pc} 08007958 : * Handle EP0 Rx Ready event * @param pdev: device instance * @retval status */ static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) { 8007958: b580 push {r7, lr} 800795a: b084 sub sp, #16 800795c: af00 add r7, sp, #0 800795e: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8007960: 687b ldr r3, [r7, #4] 8007962: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007966: 60fb str r3, [r7, #12] if (hcdc == NULL) 8007968: 68fb ldr r3, [r7, #12] 800796a: 2b00 cmp r3, #0 800796c: d101 bne.n 8007972 { return (uint8_t)USBD_FAIL; 800796e: 2303 movs r3, #3 8007970: e01b b.n 80079aa } if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU)) 8007972: 687b ldr r3, [r7, #4] 8007974: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8007978: 2b00 cmp r3, #0 800797a: d015 beq.n 80079a8 800797c: 68fb ldr r3, [r7, #12] 800797e: f893 3200 ldrb.w r3, [r3, #512] ; 0x200 8007982: 2bff cmp r3, #255 ; 0xff 8007984: d010 beq.n 80079a8 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, 8007986: 687b ldr r3, [r7, #4] 8007988: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 800798c: 689b ldr r3, [r3, #8] 800798e: 68fa ldr r2, [r7, #12] 8007990: f892 0200 ldrb.w r0, [r2, #512] ; 0x200 (uint8_t *)hcdc->data, 8007994: 68f9 ldr r1, [r7, #12] (uint16_t)hcdc->CmdLength); 8007996: 68fa ldr r2, [r7, #12] 8007998: f892 2201 ldrb.w r2, [r2, #513] ; 0x201 ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, 800799c: b292 uxth r2, r2 800799e: 4798 blx r3 hcdc->CmdOpCode = 0xFFU; 80079a0: 68fb ldr r3, [r7, #12] 80079a2: 22ff movs r2, #255 ; 0xff 80079a4: f883 2200 strb.w r2, [r3, #512] ; 0x200 } return (uint8_t)USBD_OK; 80079a8: 2300 movs r3, #0 } 80079aa: 4618 mov r0, r3 80079ac: 3710 adds r7, #16 80079ae: 46bd mov sp, r7 80079b0: bd80 pop {r7, pc} ... 080079b4 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) { 80079b4: b480 push {r7} 80079b6: b083 sub sp, #12 80079b8: af00 add r7, sp, #0 80079ba: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_CfgFSDesc); 80079bc: 687b ldr r3, [r7, #4] 80079be: 2243 movs r2, #67 ; 0x43 80079c0: 801a strh r2, [r3, #0] return USBD_CDC_CfgFSDesc; 80079c2: 4b03 ldr r3, [pc, #12] ; (80079d0 ) } 80079c4: 4618 mov r0, r3 80079c6: 370c adds r7, #12 80079c8: 46bd mov sp, r7 80079ca: f85d 7b04 ldr.w r7, [sp], #4 80079ce: 4770 bx lr 80079d0: 24000098 .word 0x24000098 080079d4 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) { 80079d4: b480 push {r7} 80079d6: b083 sub sp, #12 80079d8: af00 add r7, sp, #0 80079da: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_CfgHSDesc); 80079dc: 687b ldr r3, [r7, #4] 80079de: 2243 movs r2, #67 ; 0x43 80079e0: 801a strh r2, [r3, #0] return USBD_CDC_CfgHSDesc; 80079e2: 4b03 ldr r3, [pc, #12] ; (80079f0 ) } 80079e4: 4618 mov r0, r3 80079e6: 370c adds r7, #12 80079e8: 46bd mov sp, r7 80079ea: f85d 7b04 ldr.w r7, [sp], #4 80079ee: 4770 bx lr 80079f0: 24000054 .word 0x24000054 080079f4 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) { 80079f4: b480 push {r7} 80079f6: b083 sub sp, #12 80079f8: af00 add r7, sp, #0 80079fa: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_OtherSpeedCfgDesc); 80079fc: 687b ldr r3, [r7, #4] 80079fe: 2243 movs r2, #67 ; 0x43 8007a00: 801a strh r2, [r3, #0] return USBD_CDC_OtherSpeedCfgDesc; 8007a02: 4b03 ldr r3, [pc, #12] ; (8007a10 ) } 8007a04: 4618 mov r0, r3 8007a06: 370c adds r7, #12 8007a08: 46bd mov sp, r7 8007a0a: f85d 7b04 ldr.w r7, [sp], #4 8007a0e: 4770 bx lr 8007a10: 240000dc .word 0x240000dc 08007a14 : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) { 8007a14: b480 push {r7} 8007a16: b083 sub sp, #12 8007a18: af00 add r7, sp, #0 8007a1a: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc); 8007a1c: 687b ldr r3, [r7, #4] 8007a1e: 220a movs r2, #10 8007a20: 801a strh r2, [r3, #0] return USBD_CDC_DeviceQualifierDesc; 8007a22: 4b03 ldr r3, [pc, #12] ; (8007a30 ) } 8007a24: 4618 mov r0, r3 8007a26: 370c adds r7, #12 8007a28: 46bd mov sp, r7 8007a2a: f85d 7b04 ldr.w r7, [sp], #4 8007a2e: 4770 bx lr 8007a30: 24000010 .word 0x24000010 08007a34 : * @param fops: CD Interface callback * @retval status */ uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, USBD_CDC_ItfTypeDef *fops) { 8007a34: b480 push {r7} 8007a36: b083 sub sp, #12 8007a38: af00 add r7, sp, #0 8007a3a: 6078 str r0, [r7, #4] 8007a3c: 6039 str r1, [r7, #0] if (fops == NULL) 8007a3e: 683b ldr r3, [r7, #0] 8007a40: 2b00 cmp r3, #0 8007a42: d101 bne.n 8007a48 { return (uint8_t)USBD_FAIL; 8007a44: 2303 movs r3, #3 8007a46: e004 b.n 8007a52 } pdev->pUserData = fops; 8007a48: 687b ldr r3, [r7, #4] 8007a4a: 683a ldr r2, [r7, #0] 8007a4c: f8c3 22c0 str.w r2, [r3, #704] ; 0x2c0 return (uint8_t)USBD_OK; 8007a50: 2300 movs r3, #0 } 8007a52: 4618 mov r0, r3 8007a54: 370c adds r7, #12 8007a56: 46bd mov sp, r7 8007a58: f85d 7b04 ldr.w r7, [sp], #4 8007a5c: 4770 bx lr 08007a5e : * @param pbuff: Tx Buffer * @retval status */ uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, uint32_t length) { 8007a5e: b480 push {r7} 8007a60: b087 sub sp, #28 8007a62: af00 add r7, sp, #0 8007a64: 60f8 str r0, [r7, #12] 8007a66: 60b9 str r1, [r7, #8] 8007a68: 607a str r2, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8007a6a: 68fb ldr r3, [r7, #12] 8007a6c: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007a70: 617b str r3, [r7, #20] if (hcdc == NULL) 8007a72: 697b ldr r3, [r7, #20] 8007a74: 2b00 cmp r3, #0 8007a76: d101 bne.n 8007a7c { return (uint8_t)USBD_FAIL; 8007a78: 2303 movs r3, #3 8007a7a: e008 b.n 8007a8e } hcdc->TxBuffer = pbuff; 8007a7c: 697b ldr r3, [r7, #20] 8007a7e: 68ba ldr r2, [r7, #8] 8007a80: f8c3 2208 str.w r2, [r3, #520] ; 0x208 hcdc->TxLength = length; 8007a84: 697b ldr r3, [r7, #20] 8007a86: 687a ldr r2, [r7, #4] 8007a88: f8c3 2210 str.w r2, [r3, #528] ; 0x210 return (uint8_t)USBD_OK; 8007a8c: 2300 movs r3, #0 } 8007a8e: 4618 mov r0, r3 8007a90: 371c adds r7, #28 8007a92: 46bd mov sp, r7 8007a94: f85d 7b04 ldr.w r7, [sp], #4 8007a98: 4770 bx lr 08007a9a : * @param pdev: device instance * @param pbuff: Rx Buffer * @retval status */ uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) { 8007a9a: b480 push {r7} 8007a9c: b085 sub sp, #20 8007a9e: af00 add r7, sp, #0 8007aa0: 6078 str r0, [r7, #4] 8007aa2: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8007aa4: 687b ldr r3, [r7, #4] 8007aa6: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007aaa: 60fb str r3, [r7, #12] if (hcdc == NULL) 8007aac: 68fb ldr r3, [r7, #12] 8007aae: 2b00 cmp r3, #0 8007ab0: d101 bne.n 8007ab6 { return (uint8_t)USBD_FAIL; 8007ab2: 2303 movs r3, #3 8007ab4: e004 b.n 8007ac0 } hcdc->RxBuffer = pbuff; 8007ab6: 68fb ldr r3, [r7, #12] 8007ab8: 683a ldr r2, [r7, #0] 8007aba: f8c3 2204 str.w r2, [r3, #516] ; 0x204 return (uint8_t)USBD_OK; 8007abe: 2300 movs r3, #0 } 8007ac0: 4618 mov r0, r3 8007ac2: 3714 adds r7, #20 8007ac4: 46bd mov sp, r7 8007ac6: f85d 7b04 ldr.w r7, [sp], #4 8007aca: 4770 bx lr 08007acc : * Transmit packet on IN endpoint * @param pdev: device instance * @retval status */ uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) { 8007acc: b580 push {r7, lr} 8007ace: b084 sub sp, #16 8007ad0: af00 add r7, sp, #0 8007ad2: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8007ad4: 687b ldr r3, [r7, #4] 8007ad6: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007ada: 60bb str r3, [r7, #8] USBD_StatusTypeDef ret = USBD_BUSY; 8007adc: 2301 movs r3, #1 8007ade: 73fb strb r3, [r7, #15] if (pdev->pClassData == NULL) 8007ae0: 687b ldr r3, [r7, #4] 8007ae2: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007ae6: 2b00 cmp r3, #0 8007ae8: d101 bne.n 8007aee { return (uint8_t)USBD_FAIL; 8007aea: 2303 movs r3, #3 8007aec: e01a b.n 8007b24 } if (hcdc->TxState == 0U) 8007aee: 68bb ldr r3, [r7, #8] 8007af0: f8d3 3214 ldr.w r3, [r3, #532] ; 0x214 8007af4: 2b00 cmp r3, #0 8007af6: d114 bne.n 8007b22 { /* Tx Transfer in progress */ hcdc->TxState = 1U; 8007af8: 68bb ldr r3, [r7, #8] 8007afa: 2201 movs r2, #1 8007afc: f8c3 2214 str.w r2, [r3, #532] ; 0x214 /* Update the packet total length */ pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength; 8007b00: 68bb ldr r3, [r7, #8] 8007b02: f8d3 2210 ldr.w r2, [r3, #528] ; 0x210 8007b06: 687b ldr r3, [r7, #4] 8007b08: 62da str r2, [r3, #44] ; 0x2c /* Transmit next packet */ (void)USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer, hcdc->TxLength); 8007b0a: 68bb ldr r3, [r7, #8] 8007b0c: f8d3 2208 ldr.w r2, [r3, #520] ; 0x208 8007b10: 68bb ldr r3, [r7, #8] 8007b12: f8d3 3210 ldr.w r3, [r3, #528] ; 0x210 8007b16: 2181 movs r1, #129 ; 0x81 8007b18: 6878 ldr r0, [r7, #4] 8007b1a: f001 fe46 bl 80097aa ret = USBD_OK; 8007b1e: 2300 movs r3, #0 8007b20: 73fb strb r3, [r7, #15] } return (uint8_t)ret; 8007b22: 7bfb ldrb r3, [r7, #15] } 8007b24: 4618 mov r0, r3 8007b26: 3710 adds r7, #16 8007b28: 46bd mov sp, r7 8007b2a: bd80 pop {r7, pc} 08007b2c : * prepare OUT Endpoint for reception * @param pdev: device instance * @retval status */ uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) { 8007b2c: b580 push {r7, lr} 8007b2e: b084 sub sp, #16 8007b30: af00 add r7, sp, #0 8007b32: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8007b34: 687b ldr r3, [r7, #4] 8007b36: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007b3a: 60fb str r3, [r7, #12] if (pdev->pClassData == NULL) 8007b3c: 687b ldr r3, [r7, #4] 8007b3e: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007b42: 2b00 cmp r3, #0 8007b44: d101 bne.n 8007b4a { return (uint8_t)USBD_FAIL; 8007b46: 2303 movs r3, #3 8007b48: e016 b.n 8007b78 } if (pdev->dev_speed == USBD_SPEED_HIGH) 8007b4a: 687b ldr r3, [r7, #4] 8007b4c: 7c1b ldrb r3, [r3, #16] 8007b4e: 2b00 cmp r3, #0 8007b50: d109 bne.n 8007b66 { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 8007b52: 68fb ldr r3, [r7, #12] 8007b54: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 8007b58: f44f 7300 mov.w r3, #512 ; 0x200 8007b5c: 2101 movs r1, #1 8007b5e: 6878 ldr r0, [r7, #4] 8007b60: f001 fe44 bl 80097ec 8007b64: e007 b.n 8007b76 CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 8007b66: 68fb ldr r3, [r7, #12] 8007b68: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 8007b6c: 2340 movs r3, #64 ; 0x40 8007b6e: 2101 movs r1, #1 8007b70: 6878 ldr r0, [r7, #4] 8007b72: f001 fe3b bl 80097ec CDC_DATA_FS_OUT_PACKET_SIZE); } return (uint8_t)USBD_OK; 8007b76: 2300 movs r3, #0 } 8007b78: 4618 mov r0, r3 8007b7a: 3710 adds r7, #16 8007b7c: 46bd mov sp, r7 8007b7e: bd80 pop {r7, pc} 08007b80 : * @param id: Low level core index * @retval None */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 8007b80: b580 push {r7, lr} 8007b82: b086 sub sp, #24 8007b84: af00 add r7, sp, #0 8007b86: 60f8 str r0, [r7, #12] 8007b88: 60b9 str r1, [r7, #8] 8007b8a: 4613 mov r3, r2 8007b8c: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 8007b8e: 68fb ldr r3, [r7, #12] 8007b90: 2b00 cmp r3, #0 8007b92: d101 bne.n 8007b98 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif return USBD_FAIL; 8007b94: 2303 movs r3, #3 8007b96: e01f b.n 8007bd8 } /* Unlink previous class resources */ pdev->pClass = NULL; 8007b98: 68fb ldr r3, [r7, #12] 8007b9a: 2200 movs r2, #0 8007b9c: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 pdev->pUserData = NULL; 8007ba0: 68fb ldr r3, [r7, #12] 8007ba2: 2200 movs r2, #0 8007ba4: f8c3 22c0 str.w r2, [r3, #704] ; 0x2c0 pdev->pConfDesc = NULL; 8007ba8: 68fb ldr r3, [r7, #12] 8007baa: 2200 movs r2, #0 8007bac: f8c3 22cc str.w r2, [r3, #716] ; 0x2cc /* Assign USBD Descriptors */ if (pdesc != NULL) 8007bb0: 68bb ldr r3, [r7, #8] 8007bb2: 2b00 cmp r3, #0 8007bb4: d003 beq.n 8007bbe { pdev->pDesc = pdesc; 8007bb6: 68fb ldr r3, [r7, #12] 8007bb8: 68ba ldr r2, [r7, #8] 8007bba: f8c3 22b4 str.w r2, [r3, #692] ; 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 8007bbe: 68fb ldr r3, [r7, #12] 8007bc0: 2201 movs r2, #1 8007bc2: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->id = id; 8007bc6: 68fb ldr r3, [r7, #12] 8007bc8: 79fa ldrb r2, [r7, #7] 8007bca: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 8007bcc: 68f8 ldr r0, [r7, #12] 8007bce: f001 fcad bl 800952c 8007bd2: 4603 mov r3, r0 8007bd4: 75fb strb r3, [r7, #23] return ret; 8007bd6: 7dfb ldrb r3, [r7, #23] } 8007bd8: 4618 mov r0, r3 8007bda: 3718 adds r7, #24 8007bdc: 46bd mov sp, r7 8007bde: bd80 pop {r7, pc} 08007be0 : * @param pDevice : Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 8007be0: b580 push {r7, lr} 8007be2: b084 sub sp, #16 8007be4: af00 add r7, sp, #0 8007be6: 6078 str r0, [r7, #4] 8007be8: 6039 str r1, [r7, #0] uint16_t len = 0U; 8007bea: 2300 movs r3, #0 8007bec: 81fb strh r3, [r7, #14] if (pclass == NULL) 8007bee: 683b ldr r3, [r7, #0] 8007bf0: 2b00 cmp r3, #0 8007bf2: d101 bne.n 8007bf8 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif return USBD_FAIL; 8007bf4: 2303 movs r3, #3 8007bf6: e016 b.n 8007c26 } /* link the class to the USB Device handle */ pdev->pClass = pclass; 8007bf8: 687b ldr r3, [r7, #4] 8007bfa: 683a ldr r2, [r7, #0] 8007bfc: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 if (pdev->pClass->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass->GetFSConfigDescriptor != NULL) 8007c00: 687b ldr r3, [r7, #4] 8007c02: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007c06: 6adb ldr r3, [r3, #44] ; 0x2c 8007c08: 2b00 cmp r3, #0 8007c0a: d00b beq.n 8007c24 { pdev->pConfDesc = (void *)pdev->pClass->GetFSConfigDescriptor(&len); 8007c0c: 687b ldr r3, [r7, #4] 8007c0e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007c12: 6adb ldr r3, [r3, #44] ; 0x2c 8007c14: f107 020e add.w r2, r7, #14 8007c18: 4610 mov r0, r2 8007c1a: 4798 blx r3 8007c1c: 4602 mov r2, r0 8007c1e: 687b ldr r3, [r7, #4] 8007c20: f8c3 22cc str.w r2, [r3, #716] ; 0x2cc } #endif /* USE_USB_FS */ return USBD_OK; 8007c24: 2300 movs r3, #0 } 8007c26: 4618 mov r0, r3 8007c28: 3710 adds r7, #16 8007c2a: 46bd mov sp, r7 8007c2c: bd80 pop {r7, pc} 08007c2e : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8007c2e: b580 push {r7, lr} 8007c30: b082 sub sp, #8 8007c32: af00 add r7, sp, #0 8007c34: 6078 str r0, [r7, #4] /* Start the low level driver */ return USBD_LL_Start(pdev); 8007c36: 6878 ldr r0, [r7, #4] 8007c38: f001 fcce bl 80095d8 8007c3c: 4603 mov r3, r0 } 8007c3e: 4618 mov r0, r3 8007c40: 3708 adds r7, #8 8007c42: 46bd mov sp, r7 8007c44: bd80 pop {r7, pc} 08007c46 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 8007c46: b480 push {r7} 8007c48: b083 sub sp, #12 8007c4a: af00 add r7, sp, #0 8007c4c: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8007c4e: 2300 movs r3, #0 } 8007c50: 4618 mov r0, r3 8007c52: 370c adds r7, #12 8007c54: 46bd mov sp, r7 8007c56: f85d 7b04 ldr.w r7, [sp], #4 8007c5a: 4770 bx lr 08007c5c : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8007c5c: b580 push {r7, lr} 8007c5e: b084 sub sp, #16 8007c60: af00 add r7, sp, #0 8007c62: 6078 str r0, [r7, #4] 8007c64: 460b mov r3, r1 8007c66: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_FAIL; 8007c68: 2303 movs r3, #3 8007c6a: 73fb strb r3, [r7, #15] if (pdev->pClass != NULL) 8007c6c: 687b ldr r3, [r7, #4] 8007c6e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007c72: 2b00 cmp r3, #0 8007c74: d009 beq.n 8007c8a { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass->Init(pdev, cfgidx); 8007c76: 687b ldr r3, [r7, #4] 8007c78: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007c7c: 681b ldr r3, [r3, #0] 8007c7e: 78fa ldrb r2, [r7, #3] 8007c80: 4611 mov r1, r2 8007c82: 6878 ldr r0, [r7, #4] 8007c84: 4798 blx r3 8007c86: 4603 mov r3, r0 8007c88: 73fb strb r3, [r7, #15] } return ret; 8007c8a: 7bfb ldrb r3, [r7, #15] } 8007c8c: 4618 mov r0, r3 8007c8e: 3710 adds r7, #16 8007c90: 46bd mov sp, r7 8007c92: bd80 pop {r7, pc} 08007c94 : * @param pdev: device instance * @param cfgidx: configuration index * @retval status: USBD_StatusTypeDef */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8007c94: b580 push {r7, lr} 8007c96: b082 sub sp, #8 8007c98: af00 add r7, sp, #0 8007c9a: 6078 str r0, [r7, #4] 8007c9c: 460b mov r3, r1 8007c9e: 70fb strb r3, [r7, #3] /* Clear configuration and De-initialize the Class process */ if (pdev->pClass != NULL) 8007ca0: 687b ldr r3, [r7, #4] 8007ca2: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007ca6: 2b00 cmp r3, #0 8007ca8: d007 beq.n 8007cba { pdev->pClass->DeInit(pdev, cfgidx); 8007caa: 687b ldr r3, [r7, #4] 8007cac: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007cb0: 685b ldr r3, [r3, #4] 8007cb2: 78fa ldrb r2, [r7, #3] 8007cb4: 4611 mov r1, r2 8007cb6: 6878 ldr r0, [r7, #4] 8007cb8: 4798 blx r3 } return USBD_OK; 8007cba: 2300 movs r3, #0 } 8007cbc: 4618 mov r0, r3 8007cbe: 3708 adds r7, #8 8007cc0: 46bd mov sp, r7 8007cc2: bd80 pop {r7, pc} 08007cc4 : * Handle the setup stage * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 8007cc4: b580 push {r7, lr} 8007cc6: b084 sub sp, #16 8007cc8: af00 add r7, sp, #0 8007cca: 6078 str r0, [r7, #4] 8007ccc: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 8007cce: 687b ldr r3, [r7, #4] 8007cd0: f203 23aa addw r3, r3, #682 ; 0x2aa 8007cd4: 6839 ldr r1, [r7, #0] 8007cd6: 4618 mov r0, r3 8007cd8: f000 ff90 bl 8008bfc pdev->ep0_state = USBD_EP0_SETUP; 8007cdc: 687b ldr r3, [r7, #4] 8007cde: 2201 movs r2, #1 8007ce0: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->ep0_data_len = pdev->request.wLength; 8007ce4: 687b ldr r3, [r7, #4] 8007ce6: f8b3 32b0 ldrh.w r3, [r3, #688] ; 0x2b0 8007cea: 461a mov r2, r3 8007cec: 687b ldr r3, [r7, #4] 8007cee: f8c3 2298 str.w r2, [r3, #664] ; 0x298 switch (pdev->request.bmRequest & 0x1FU) 8007cf2: 687b ldr r3, [r7, #4] 8007cf4: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa 8007cf8: f003 031f and.w r3, r3, #31 8007cfc: 2b02 cmp r3, #2 8007cfe: d01a beq.n 8007d36 8007d00: 2b02 cmp r3, #2 8007d02: d822 bhi.n 8007d4a 8007d04: 2b00 cmp r3, #0 8007d06: d002 beq.n 8007d0e 8007d08: 2b01 cmp r3, #1 8007d0a: d00a beq.n 8007d22 8007d0c: e01d b.n 8007d4a { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 8007d0e: 687b ldr r3, [r7, #4] 8007d10: f203 23aa addw r3, r3, #682 ; 0x2aa 8007d14: 4619 mov r1, r3 8007d16: 6878 ldr r0, [r7, #4] 8007d18: f000 fa62 bl 80081e0 8007d1c: 4603 mov r3, r0 8007d1e: 73fb strb r3, [r7, #15] break; 8007d20: e020 b.n 8007d64 case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 8007d22: 687b ldr r3, [r7, #4] 8007d24: f203 23aa addw r3, r3, #682 ; 0x2aa 8007d28: 4619 mov r1, r3 8007d2a: 6878 ldr r0, [r7, #4] 8007d2c: f000 fac6 bl 80082bc 8007d30: 4603 mov r3, r0 8007d32: 73fb strb r3, [r7, #15] break; 8007d34: e016 b.n 8007d64 case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8007d36: 687b ldr r3, [r7, #4] 8007d38: f203 23aa addw r3, r3, #682 ; 0x2aa 8007d3c: 4619 mov r1, r3 8007d3e: 6878 ldr r0, [r7, #4] 8007d40: f000 fb05 bl 800834e 8007d44: 4603 mov r3, r0 8007d46: 73fb strb r3, [r7, #15] break; 8007d48: e00c b.n 8007d64 default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8007d4a: 687b ldr r3, [r7, #4] 8007d4c: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa 8007d50: f023 037f bic.w r3, r3, #127 ; 0x7f 8007d54: b2db uxtb r3, r3 8007d56: 4619 mov r1, r3 8007d58: 6878 ldr r0, [r7, #4] 8007d5a: f001 fc9d bl 8009698 8007d5e: 4603 mov r3, r0 8007d60: 73fb strb r3, [r7, #15] break; 8007d62: bf00 nop } return ret; 8007d64: 7bfb ldrb r3, [r7, #15] } 8007d66: 4618 mov r0, r3 8007d68: 3710 adds r7, #16 8007d6a: 46bd mov sp, r7 8007d6c: bd80 pop {r7, pc} 08007d6e : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8007d6e: b580 push {r7, lr} 8007d70: b086 sub sp, #24 8007d72: af00 add r7, sp, #0 8007d74: 60f8 str r0, [r7, #12] 8007d76: 460b mov r3, r1 8007d78: 607a str r2, [r7, #4] 8007d7a: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret; if (epnum == 0U) 8007d7c: 7afb ldrb r3, [r7, #11] 8007d7e: 2b00 cmp r3, #0 8007d80: d138 bne.n 8007df4 { pep = &pdev->ep_out[0]; 8007d82: 68fb ldr r3, [r7, #12] 8007d84: f503 73aa add.w r3, r3, #340 ; 0x154 8007d88: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 8007d8a: 68fb ldr r3, [r7, #12] 8007d8c: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 8007d90: 2b03 cmp r3, #3 8007d92: d14a bne.n 8007e2a { if (pep->rem_length > pep->maxpacket) 8007d94: 693b ldr r3, [r7, #16] 8007d96: 689a ldr r2, [r3, #8] 8007d98: 693b ldr r3, [r7, #16] 8007d9a: 68db ldr r3, [r3, #12] 8007d9c: 429a cmp r2, r3 8007d9e: d913 bls.n 8007dc8 { pep->rem_length -= pep->maxpacket; 8007da0: 693b ldr r3, [r7, #16] 8007da2: 689a ldr r2, [r3, #8] 8007da4: 693b ldr r3, [r7, #16] 8007da6: 68db ldr r3, [r3, #12] 8007da8: 1ad2 subs r2, r2, r3 8007daa: 693b ldr r3, [r7, #16] 8007dac: 609a str r2, [r3, #8] (void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket)); 8007dae: 693b ldr r3, [r7, #16] 8007db0: 68da ldr r2, [r3, #12] 8007db2: 693b ldr r3, [r7, #16] 8007db4: 689b ldr r3, [r3, #8] 8007db6: 4293 cmp r3, r2 8007db8: bf28 it cs 8007dba: 4613 movcs r3, r2 8007dbc: 461a mov r2, r3 8007dbe: 6879 ldr r1, [r7, #4] 8007dc0: 68f8 ldr r0, [r7, #12] 8007dc2: f001 f80f bl 8008de4 8007dc6: e030 b.n 8007e2a } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007dc8: 68fb ldr r3, [r7, #12] 8007dca: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007dce: b2db uxtb r3, r3 8007dd0: 2b03 cmp r3, #3 8007dd2: d10b bne.n 8007dec { if (pdev->pClass->EP0_RxReady != NULL) 8007dd4: 68fb ldr r3, [r7, #12] 8007dd6: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007dda: 691b ldr r3, [r3, #16] 8007ddc: 2b00 cmp r3, #0 8007dde: d005 beq.n 8007dec { pdev->pClass->EP0_RxReady(pdev); 8007de0: 68fb ldr r3, [r7, #12] 8007de2: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007de6: 691b ldr r3, [r3, #16] 8007de8: 68f8 ldr r0, [r7, #12] 8007dea: 4798 blx r3 } } (void)USBD_CtlSendStatus(pdev); 8007dec: 68f8 ldr r0, [r7, #12] 8007dee: f001 f80a bl 8008e06 8007df2: e01a b.n 8007e2a #endif } } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007df4: 68fb ldr r3, [r7, #12] 8007df6: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007dfa: b2db uxtb r3, r3 8007dfc: 2b03 cmp r3, #3 8007dfe: d114 bne.n 8007e2a { if (pdev->pClass->DataOut != NULL) 8007e00: 68fb ldr r3, [r7, #12] 8007e02: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007e06: 699b ldr r3, [r3, #24] 8007e08: 2b00 cmp r3, #0 8007e0a: d00e beq.n 8007e2a { ret = (USBD_StatusTypeDef)pdev->pClass->DataOut(pdev, epnum); 8007e0c: 68fb ldr r3, [r7, #12] 8007e0e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007e12: 699b ldr r3, [r3, #24] 8007e14: 7afa ldrb r2, [r7, #11] 8007e16: 4611 mov r1, r2 8007e18: 68f8 ldr r0, [r7, #12] 8007e1a: 4798 blx r3 8007e1c: 4603 mov r3, r0 8007e1e: 75fb strb r3, [r7, #23] if (ret != USBD_OK) 8007e20: 7dfb ldrb r3, [r7, #23] 8007e22: 2b00 cmp r3, #0 8007e24: d001 beq.n 8007e2a { return ret; 8007e26: 7dfb ldrb r3, [r7, #23] 8007e28: e000 b.n 8007e2c } } } } return USBD_OK; 8007e2a: 2300 movs r3, #0 } 8007e2c: 4618 mov r0, r3 8007e2e: 3718 adds r7, #24 8007e30: 46bd mov sp, r7 8007e32: bd80 pop {r7, pc} 08007e34 : * @param epnum: endpoint index * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8007e34: b580 push {r7, lr} 8007e36: b086 sub sp, #24 8007e38: af00 add r7, sp, #0 8007e3a: 60f8 str r0, [r7, #12] 8007e3c: 460b mov r3, r1 8007e3e: 607a str r2, [r7, #4] 8007e40: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret; if (epnum == 0U) 8007e42: 7afb ldrb r3, [r7, #11] 8007e44: 2b00 cmp r3, #0 8007e46: d16b bne.n 8007f20 { pep = &pdev->ep_in[0]; 8007e48: 68fb ldr r3, [r7, #12] 8007e4a: 3314 adds r3, #20 8007e4c: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 8007e4e: 68fb ldr r3, [r7, #12] 8007e50: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 8007e54: 2b02 cmp r3, #2 8007e56: d156 bne.n 8007f06 { if (pep->rem_length > pep->maxpacket) 8007e58: 693b ldr r3, [r7, #16] 8007e5a: 689a ldr r2, [r3, #8] 8007e5c: 693b ldr r3, [r7, #16] 8007e5e: 68db ldr r3, [r3, #12] 8007e60: 429a cmp r2, r3 8007e62: d914 bls.n 8007e8e { pep->rem_length -= pep->maxpacket; 8007e64: 693b ldr r3, [r7, #16] 8007e66: 689a ldr r2, [r3, #8] 8007e68: 693b ldr r3, [r7, #16] 8007e6a: 68db ldr r3, [r3, #12] 8007e6c: 1ad2 subs r2, r2, r3 8007e6e: 693b ldr r3, [r7, #16] 8007e70: 609a str r2, [r3, #8] (void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length); 8007e72: 693b ldr r3, [r7, #16] 8007e74: 689b ldr r3, [r3, #8] 8007e76: 461a mov r2, r3 8007e78: 6879 ldr r1, [r7, #4] 8007e7a: 68f8 ldr r0, [r7, #12] 8007e7c: f000 ff84 bl 8008d88 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8007e80: 2300 movs r3, #0 8007e82: 2200 movs r2, #0 8007e84: 2100 movs r1, #0 8007e86: 68f8 ldr r0, [r7, #12] 8007e88: f001 fcb0 bl 80097ec 8007e8c: e03b b.n 8007f06 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 8007e8e: 693b ldr r3, [r7, #16] 8007e90: 68da ldr r2, [r3, #12] 8007e92: 693b ldr r3, [r7, #16] 8007e94: 689b ldr r3, [r3, #8] 8007e96: 429a cmp r2, r3 8007e98: d11c bne.n 8007ed4 (pep->total_length >= pep->maxpacket) && 8007e9a: 693b ldr r3, [r7, #16] 8007e9c: 685a ldr r2, [r3, #4] 8007e9e: 693b ldr r3, [r7, #16] 8007ea0: 68db ldr r3, [r3, #12] if ((pep->maxpacket == pep->rem_length) && 8007ea2: 429a cmp r2, r3 8007ea4: d316 bcc.n 8007ed4 (pep->total_length < pdev->ep0_data_len)) 8007ea6: 693b ldr r3, [r7, #16] 8007ea8: 685a ldr r2, [r3, #4] 8007eaa: 68fb ldr r3, [r7, #12] 8007eac: f8d3 3298 ldr.w r3, [r3, #664] ; 0x298 (pep->total_length >= pep->maxpacket) && 8007eb0: 429a cmp r2, r3 8007eb2: d20f bcs.n 8007ed4 { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 8007eb4: 2200 movs r2, #0 8007eb6: 2100 movs r1, #0 8007eb8: 68f8 ldr r0, [r7, #12] 8007eba: f000 ff65 bl 8008d88 pdev->ep0_data_len = 0U; 8007ebe: 68fb ldr r3, [r7, #12] 8007ec0: 2200 movs r2, #0 8007ec2: f8c3 2298 str.w r2, [r3, #664] ; 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8007ec6: 2300 movs r3, #0 8007ec8: 2200 movs r2, #0 8007eca: 2100 movs r1, #0 8007ecc: 68f8 ldr r0, [r7, #12] 8007ece: f001 fc8d bl 80097ec 8007ed2: e018 b.n 8007f06 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007ed4: 68fb ldr r3, [r7, #12] 8007ed6: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007eda: b2db uxtb r3, r3 8007edc: 2b03 cmp r3, #3 8007ede: d10b bne.n 8007ef8 { if (pdev->pClass->EP0_TxSent != NULL) 8007ee0: 68fb ldr r3, [r7, #12] 8007ee2: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007ee6: 68db ldr r3, [r3, #12] 8007ee8: 2b00 cmp r3, #0 8007eea: d005 beq.n 8007ef8 { pdev->pClass->EP0_TxSent(pdev); 8007eec: 68fb ldr r3, [r7, #12] 8007eee: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007ef2: 68db ldr r3, [r3, #12] 8007ef4: 68f8 ldr r0, [r7, #12] 8007ef6: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 8007ef8: 2180 movs r1, #128 ; 0x80 8007efa: 68f8 ldr r0, [r7, #12] 8007efc: f001 fbcc bl 8009698 (void)USBD_CtlReceiveStatus(pdev); 8007f00: 68f8 ldr r0, [r7, #12] 8007f02: f000 ff93 bl 8008e2c (void)USBD_LL_StallEP(pdev, 0x80U); } #endif } if (pdev->dev_test_mode == 1U) 8007f06: 68fb ldr r3, [r7, #12] 8007f08: f893 32a0 ldrb.w r3, [r3, #672] ; 0x2a0 8007f0c: 2b01 cmp r3, #1 8007f0e: d122 bne.n 8007f56 { (void)USBD_RunTestMode(pdev); 8007f10: 68f8 ldr r0, [r7, #12] 8007f12: f7ff fe98 bl 8007c46 pdev->dev_test_mode = 0U; 8007f16: 68fb ldr r3, [r7, #12] 8007f18: 2200 movs r2, #0 8007f1a: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0 8007f1e: e01a b.n 8007f56 } } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007f20: 68fb ldr r3, [r7, #12] 8007f22: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007f26: b2db uxtb r3, r3 8007f28: 2b03 cmp r3, #3 8007f2a: d114 bne.n 8007f56 { if (pdev->pClass->DataIn != NULL) 8007f2c: 68fb ldr r3, [r7, #12] 8007f2e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007f32: 695b ldr r3, [r3, #20] 8007f34: 2b00 cmp r3, #0 8007f36: d00e beq.n 8007f56 { ret = (USBD_StatusTypeDef)pdev->pClass->DataIn(pdev, epnum); 8007f38: 68fb ldr r3, [r7, #12] 8007f3a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007f3e: 695b ldr r3, [r3, #20] 8007f40: 7afa ldrb r2, [r7, #11] 8007f42: 4611 mov r1, r2 8007f44: 68f8 ldr r0, [r7, #12] 8007f46: 4798 blx r3 8007f48: 4603 mov r3, r0 8007f4a: 75fb strb r3, [r7, #23] if (ret != USBD_OK) 8007f4c: 7dfb ldrb r3, [r7, #23] 8007f4e: 2b00 cmp r3, #0 8007f50: d001 beq.n 8007f56 { return ret; 8007f52: 7dfb ldrb r3, [r7, #23] 8007f54: e000 b.n 8007f58 } } } } return USBD_OK; 8007f56: 2300 movs r3, #0 } 8007f58: 4618 mov r0, r3 8007f5a: 3718 adds r7, #24 8007f5c: 46bd mov sp, r7 8007f5e: bd80 pop {r7, pc} 08007f60 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 8007f60: b580 push {r7, lr} 8007f62: b082 sub sp, #8 8007f64: af00 add r7, sp, #0 8007f66: 6078 str r0, [r7, #4] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 8007f68: 687b ldr r3, [r7, #4] 8007f6a: 2201 movs r2, #1 8007f6c: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->ep0_state = USBD_EP0_IDLE; 8007f70: 687b ldr r3, [r7, #4] 8007f72: 2200 movs r2, #0 8007f74: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->dev_config = 0U; 8007f78: 687b ldr r3, [r7, #4] 8007f7a: 2200 movs r2, #0 8007f7c: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 8007f7e: 687b ldr r3, [r7, #4] 8007f80: 2200 movs r2, #0 8007f82: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 if (pdev->pClass == NULL) 8007f86: 687b ldr r3, [r7, #4] 8007f88: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007f8c: 2b00 cmp r3, #0 8007f8e: d101 bne.n 8007f94 { return USBD_FAIL; 8007f90: 2303 movs r3, #3 8007f92: e02f b.n 8007ff4 } if (pdev->pClassData != NULL) 8007f94: 687b ldr r3, [r7, #4] 8007f96: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007f9a: 2b00 cmp r3, #0 8007f9c: d00f beq.n 8007fbe { if (pdev->pClass->DeInit != NULL) 8007f9e: 687b ldr r3, [r7, #4] 8007fa0: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007fa4: 685b ldr r3, [r3, #4] 8007fa6: 2b00 cmp r3, #0 8007fa8: d009 beq.n 8007fbe { (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); 8007faa: 687b ldr r3, [r7, #4] 8007fac: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007fb0: 685b ldr r3, [r3, #4] 8007fb2: 687a ldr r2, [r7, #4] 8007fb4: 6852 ldr r2, [r2, #4] 8007fb6: b2d2 uxtb r2, r2 8007fb8: 4611 mov r1, r2 8007fba: 6878 ldr r0, [r7, #4] 8007fbc: 4798 blx r3 } } /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8007fbe: 2340 movs r3, #64 ; 0x40 8007fc0: 2200 movs r2, #0 8007fc2: 2100 movs r1, #0 8007fc4: 6878 ldr r0, [r7, #4] 8007fc6: f001 fb22 bl 800960e pdev->ep_out[0x00U & 0xFU].is_used = 1U; 8007fca: 687b ldr r3, [r7, #4] 8007fcc: 2201 movs r2, #1 8007fce: f8a3 2164 strh.w r2, [r3, #356] ; 0x164 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 8007fd2: 687b ldr r3, [r7, #4] 8007fd4: 2240 movs r2, #64 ; 0x40 8007fd6: f8c3 2160 str.w r2, [r3, #352] ; 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8007fda: 2340 movs r3, #64 ; 0x40 8007fdc: 2200 movs r2, #0 8007fde: 2180 movs r1, #128 ; 0x80 8007fe0: 6878 ldr r0, [r7, #4] 8007fe2: f001 fb14 bl 800960e pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8007fe6: 687b ldr r3, [r7, #4] 8007fe8: 2201 movs r2, #1 8007fea: 849a strh r2, [r3, #36] ; 0x24 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8007fec: 687b ldr r3, [r7, #4] 8007fee: 2240 movs r2, #64 ; 0x40 8007ff0: 621a str r2, [r3, #32] return USBD_OK; 8007ff2: 2300 movs r3, #0 } 8007ff4: 4618 mov r0, r3 8007ff6: 3708 adds r7, #8 8007ff8: 46bd mov sp, r7 8007ffa: bd80 pop {r7, pc} 08007ffc : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8007ffc: b480 push {r7} 8007ffe: b083 sub sp, #12 8008000: af00 add r7, sp, #0 8008002: 6078 str r0, [r7, #4] 8008004: 460b mov r3, r1 8008006: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 8008008: 687b ldr r3, [r7, #4] 800800a: 78fa ldrb r2, [r7, #3] 800800c: 741a strb r2, [r3, #16] return USBD_OK; 800800e: 2300 movs r3, #0 } 8008010: 4618 mov r0, r3 8008012: 370c adds r7, #12 8008014: 46bd mov sp, r7 8008016: f85d 7b04 ldr.w r7, [sp], #4 800801a: 4770 bx lr 0800801c : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 800801c: b480 push {r7} 800801e: b083 sub sp, #12 8008020: af00 add r7, sp, #0 8008022: 6078 str r0, [r7, #4] pdev->dev_old_state = pdev->dev_state; 8008024: 687b ldr r3, [r7, #4] 8008026: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 800802a: b2da uxtb r2, r3 800802c: 687b ldr r3, [r7, #4] 800802e: f883 229d strb.w r2, [r3, #669] ; 0x29d pdev->dev_state = USBD_STATE_SUSPENDED; 8008032: 687b ldr r3, [r7, #4] 8008034: 2204 movs r2, #4 8008036: f883 229c strb.w r2, [r3, #668] ; 0x29c return USBD_OK; 800803a: 2300 movs r3, #0 } 800803c: 4618 mov r0, r3 800803e: 370c adds r7, #12 8008040: 46bd mov sp, r7 8008042: f85d 7b04 ldr.w r7, [sp], #4 8008046: 4770 bx lr 08008048 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 8008048: b480 push {r7} 800804a: b083 sub sp, #12 800804c: af00 add r7, sp, #0 800804e: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 8008050: 687b ldr r3, [r7, #4] 8008052: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008056: b2db uxtb r3, r3 8008058: 2b04 cmp r3, #4 800805a: d106 bne.n 800806a { pdev->dev_state = pdev->dev_old_state; 800805c: 687b ldr r3, [r7, #4] 800805e: f893 329d ldrb.w r3, [r3, #669] ; 0x29d 8008062: b2da uxtb r2, r3 8008064: 687b ldr r3, [r7, #4] 8008066: f883 229c strb.w r2, [r3, #668] ; 0x29c } return USBD_OK; 800806a: 2300 movs r3, #0 } 800806c: 4618 mov r0, r3 800806e: 370c adds r7, #12 8008070: 46bd mov sp, r7 8008072: f85d 7b04 ldr.w r7, [sp], #4 8008076: 4770 bx lr 08008078 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 8008078: b580 push {r7, lr} 800807a: b082 sub sp, #8 800807c: af00 add r7, sp, #0 800807e: 6078 str r0, [r7, #4] if (pdev->pClass == NULL) 8008080: 687b ldr r3, [r7, #4] 8008082: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008086: 2b00 cmp r3, #0 8008088: d101 bne.n 800808e { return USBD_FAIL; 800808a: 2303 movs r3, #3 800808c: e012 b.n 80080b4 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 800808e: 687b ldr r3, [r7, #4] 8008090: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008094: b2db uxtb r3, r3 8008096: 2b03 cmp r3, #3 8008098: d10b bne.n 80080b2 { if (pdev->pClass->SOF != NULL) 800809a: 687b ldr r3, [r7, #4] 800809c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80080a0: 69db ldr r3, [r3, #28] 80080a2: 2b00 cmp r3, #0 80080a4: d005 beq.n 80080b2 { (void)pdev->pClass->SOF(pdev); 80080a6: 687b ldr r3, [r7, #4] 80080a8: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80080ac: 69db ldr r3, [r3, #28] 80080ae: 6878 ldr r0, [r7, #4] 80080b0: 4798 blx r3 } } return USBD_OK; 80080b2: 2300 movs r3, #0 } 80080b4: 4618 mov r0, r3 80080b6: 3708 adds r7, #8 80080b8: 46bd mov sp, r7 80080ba: bd80 pop {r7, pc} 080080bc : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 80080bc: b580 push {r7, lr} 80080be: b082 sub sp, #8 80080c0: af00 add r7, sp, #0 80080c2: 6078 str r0, [r7, #4] 80080c4: 460b mov r3, r1 80080c6: 70fb strb r3, [r7, #3] if (pdev->pClass == NULL) 80080c8: 687b ldr r3, [r7, #4] 80080ca: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80080ce: 2b00 cmp r3, #0 80080d0: d101 bne.n 80080d6 { return USBD_FAIL; 80080d2: 2303 movs r3, #3 80080d4: e014 b.n 8008100 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 80080d6: 687b ldr r3, [r7, #4] 80080d8: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80080dc: b2db uxtb r3, r3 80080de: 2b03 cmp r3, #3 80080e0: d10d bne.n 80080fe { if (pdev->pClass->IsoINIncomplete != NULL) 80080e2: 687b ldr r3, [r7, #4] 80080e4: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80080e8: 6a1b ldr r3, [r3, #32] 80080ea: 2b00 cmp r3, #0 80080ec: d007 beq.n 80080fe { (void)pdev->pClass->IsoINIncomplete(pdev, epnum); 80080ee: 687b ldr r3, [r7, #4] 80080f0: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80080f4: 6a1b ldr r3, [r3, #32] 80080f6: 78fa ldrb r2, [r7, #3] 80080f8: 4611 mov r1, r2 80080fa: 6878 ldr r0, [r7, #4] 80080fc: 4798 blx r3 } } return USBD_OK; 80080fe: 2300 movs r3, #0 } 8008100: 4618 mov r0, r3 8008102: 3708 adds r7, #8 8008104: 46bd mov sp, r7 8008106: bd80 pop {r7, pc} 08008108 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8008108: b580 push {r7, lr} 800810a: b082 sub sp, #8 800810c: af00 add r7, sp, #0 800810e: 6078 str r0, [r7, #4] 8008110: 460b mov r3, r1 8008112: 70fb strb r3, [r7, #3] if (pdev->pClass == NULL) 8008114: 687b ldr r3, [r7, #4] 8008116: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800811a: 2b00 cmp r3, #0 800811c: d101 bne.n 8008122 { return USBD_FAIL; 800811e: 2303 movs r3, #3 8008120: e014 b.n 800814c } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008122: 687b ldr r3, [r7, #4] 8008124: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008128: b2db uxtb r3, r3 800812a: 2b03 cmp r3, #3 800812c: d10d bne.n 800814a { if (pdev->pClass->IsoOUTIncomplete != NULL) 800812e: 687b ldr r3, [r7, #4] 8008130: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008134: 6a5b ldr r3, [r3, #36] ; 0x24 8008136: 2b00 cmp r3, #0 8008138: d007 beq.n 800814a { (void)pdev->pClass->IsoOUTIncomplete(pdev, epnum); 800813a: 687b ldr r3, [r7, #4] 800813c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008140: 6a5b ldr r3, [r3, #36] ; 0x24 8008142: 78fa ldrb r2, [r7, #3] 8008144: 4611 mov r1, r2 8008146: 6878 ldr r0, [r7, #4] 8008148: 4798 blx r3 } } return USBD_OK; 800814a: 2300 movs r3, #0 } 800814c: 4618 mov r0, r3 800814e: 3708 adds r7, #8 8008150: 46bd mov sp, r7 8008152: bd80 pop {r7, pc} 08008154 : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 8008154: b480 push {r7} 8008156: b083 sub sp, #12 8008158: af00 add r7, sp, #0 800815a: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 800815c: 2300 movs r3, #0 } 800815e: 4618 mov r0, r3 8008160: 370c adds r7, #12 8008162: 46bd mov sp, r7 8008164: f85d 7b04 ldr.w r7, [sp], #4 8008168: 4770 bx lr 0800816a : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 800816a: b580 push {r7, lr} 800816c: b082 sub sp, #8 800816e: af00 add r7, sp, #0 8008170: 6078 str r0, [r7, #4] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 8008172: 687b ldr r3, [r7, #4] 8008174: 2201 movs r2, #1 8008176: f883 229c strb.w r2, [r3, #668] ; 0x29c if (pdev->pClass != NULL) 800817a: 687b ldr r3, [r7, #4] 800817c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008180: 2b00 cmp r3, #0 8008182: d009 beq.n 8008198 { (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); 8008184: 687b ldr r3, [r7, #4] 8008186: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800818a: 685b ldr r3, [r3, #4] 800818c: 687a ldr r2, [r7, #4] 800818e: 6852 ldr r2, [r2, #4] 8008190: b2d2 uxtb r2, r2 8008192: 4611 mov r1, r2 8008194: 6878 ldr r0, [r7, #4] 8008196: 4798 blx r3 } return USBD_OK; 8008198: 2300 movs r3, #0 } 800819a: 4618 mov r0, r3 800819c: 3708 adds r7, #8 800819e: 46bd mov sp, r7 80081a0: bd80 pop {r7, pc} 080081a2 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 80081a2: b480 push {r7} 80081a4: b087 sub sp, #28 80081a6: af00 add r7, sp, #0 80081a8: 6078 str r0, [r7, #4] uint16_t _SwapVal, _Byte1, _Byte2; uint8_t *_pbuff = addr; 80081aa: 687b ldr r3, [r7, #4] 80081ac: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 80081ae: 697b ldr r3, [r7, #20] 80081b0: 781b ldrb r3, [r3, #0] 80081b2: 827b strh r3, [r7, #18] _pbuff++; 80081b4: 697b ldr r3, [r7, #20] 80081b6: 3301 adds r3, #1 80081b8: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 80081ba: 697b ldr r3, [r7, #20] 80081bc: 781b ldrb r3, [r3, #0] 80081be: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 80081c0: 8a3b ldrh r3, [r7, #16] 80081c2: 021b lsls r3, r3, #8 80081c4: b21a sxth r2, r3 80081c6: f9b7 3012 ldrsh.w r3, [r7, #18] 80081ca: 4313 orrs r3, r2 80081cc: b21b sxth r3, r3 80081ce: 81fb strh r3, [r7, #14] return _SwapVal; 80081d0: 89fb ldrh r3, [r7, #14] } 80081d2: 4618 mov r0, r3 80081d4: 371c adds r7, #28 80081d6: 46bd mov sp, r7 80081d8: f85d 7b04 ldr.w r7, [sp], #4 80081dc: 4770 bx lr ... 080081e0 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80081e0: b580 push {r7, lr} 80081e2: b084 sub sp, #16 80081e4: af00 add r7, sp, #0 80081e6: 6078 str r0, [r7, #4] 80081e8: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 80081ea: 2300 movs r3, #0 80081ec: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 80081ee: 683b ldr r3, [r7, #0] 80081f0: 781b ldrb r3, [r3, #0] 80081f2: f003 0360 and.w r3, r3, #96 ; 0x60 80081f6: 2b40 cmp r3, #64 ; 0x40 80081f8: d005 beq.n 8008206 80081fa: 2b40 cmp r3, #64 ; 0x40 80081fc: d853 bhi.n 80082a6 80081fe: 2b00 cmp r3, #0 8008200: d00b beq.n 800821a 8008202: 2b20 cmp r3, #32 8008204: d14f bne.n 80082a6 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 8008206: 687b ldr r3, [r7, #4] 8008208: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800820c: 689b ldr r3, [r3, #8] 800820e: 6839 ldr r1, [r7, #0] 8008210: 6878 ldr r0, [r7, #4] 8008212: 4798 blx r3 8008214: 4603 mov r3, r0 8008216: 73fb strb r3, [r7, #15] break; 8008218: e04a b.n 80082b0 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 800821a: 683b ldr r3, [r7, #0] 800821c: 785b ldrb r3, [r3, #1] 800821e: 2b09 cmp r3, #9 8008220: d83b bhi.n 800829a 8008222: a201 add r2, pc, #4 ; (adr r2, 8008228 ) 8008224: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008228: 0800827d .word 0x0800827d 800822c: 08008291 .word 0x08008291 8008230: 0800829b .word 0x0800829b 8008234: 08008287 .word 0x08008287 8008238: 0800829b .word 0x0800829b 800823c: 0800825b .word 0x0800825b 8008240: 08008251 .word 0x08008251 8008244: 0800829b .word 0x0800829b 8008248: 08008273 .word 0x08008273 800824c: 08008265 .word 0x08008265 { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 8008250: 6839 ldr r1, [r7, #0] 8008252: 6878 ldr r0, [r7, #4] 8008254: f000 f9de bl 8008614 break; 8008258: e024 b.n 80082a4 case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 800825a: 6839 ldr r1, [r7, #0] 800825c: 6878 ldr r0, [r7, #4] 800825e: f000 fb43 bl 80088e8 break; 8008262: e01f b.n 80082a4 case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 8008264: 6839 ldr r1, [r7, #0] 8008266: 6878 ldr r0, [r7, #4] 8008268: f000 fb82 bl 8008970 800826c: 4603 mov r3, r0 800826e: 73fb strb r3, [r7, #15] break; 8008270: e018 b.n 80082a4 case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 8008272: 6839 ldr r1, [r7, #0] 8008274: 6878 ldr r0, [r7, #4] 8008276: f000 fc21 bl 8008abc break; 800827a: e013 b.n 80082a4 case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 800827c: 6839 ldr r1, [r7, #0] 800827e: 6878 ldr r0, [r7, #4] 8008280: f000 fc52 bl 8008b28 break; 8008284: e00e b.n 80082a4 case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 8008286: 6839 ldr r1, [r7, #0] 8008288: 6878 ldr r0, [r7, #4] 800828a: f000 fc81 bl 8008b90 break; 800828e: e009 b.n 80082a4 case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 8008290: 6839 ldr r1, [r7, #0] 8008292: 6878 ldr r0, [r7, #4] 8008294: f000 fc90 bl 8008bb8 break; 8008298: e004 b.n 80082a4 default: USBD_CtlError(pdev, req); 800829a: 6839 ldr r1, [r7, #0] 800829c: 6878 ldr r0, [r7, #4] 800829e: f000 fce7 bl 8008c70 break; 80082a2: bf00 nop } break; 80082a4: e004 b.n 80082b0 default: USBD_CtlError(pdev, req); 80082a6: 6839 ldr r1, [r7, #0] 80082a8: 6878 ldr r0, [r7, #4] 80082aa: f000 fce1 bl 8008c70 break; 80082ae: bf00 nop } return ret; 80082b0: 7bfb ldrb r3, [r7, #15] } 80082b2: 4618 mov r0, r3 80082b4: 3710 adds r7, #16 80082b6: 46bd mov sp, r7 80082b8: bd80 pop {r7, pc} 80082ba: bf00 nop 080082bc : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80082bc: b580 push {r7, lr} 80082be: b084 sub sp, #16 80082c0: af00 add r7, sp, #0 80082c2: 6078 str r0, [r7, #4] 80082c4: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 80082c6: 2300 movs r3, #0 80082c8: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 80082ca: 683b ldr r3, [r7, #0] 80082cc: 781b ldrb r3, [r3, #0] 80082ce: f003 0360 and.w r3, r3, #96 ; 0x60 80082d2: 2b40 cmp r3, #64 ; 0x40 80082d4: d005 beq.n 80082e2 80082d6: 2b40 cmp r3, #64 ; 0x40 80082d8: d82f bhi.n 800833a 80082da: 2b00 cmp r3, #0 80082dc: d001 beq.n 80082e2 80082de: 2b20 cmp r3, #32 80082e0: d12b bne.n 800833a { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 80082e2: 687b ldr r3, [r7, #4] 80082e4: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80082e8: b2db uxtb r3, r3 80082ea: 3b01 subs r3, #1 80082ec: 2b02 cmp r3, #2 80082ee: d81d bhi.n 800832c { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 80082f0: 683b ldr r3, [r7, #0] 80082f2: 889b ldrh r3, [r3, #4] 80082f4: b2db uxtb r3, r3 80082f6: 2b01 cmp r3, #1 80082f8: d813 bhi.n 8008322 { ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 80082fa: 687b ldr r3, [r7, #4] 80082fc: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008300: 689b ldr r3, [r3, #8] 8008302: 6839 ldr r1, [r7, #0] 8008304: 6878 ldr r0, [r7, #4] 8008306: 4798 blx r3 8008308: 4603 mov r3, r0 800830a: 73fb strb r3, [r7, #15] if ((req->wLength == 0U) && (ret == USBD_OK)) 800830c: 683b ldr r3, [r7, #0] 800830e: 88db ldrh r3, [r3, #6] 8008310: 2b00 cmp r3, #0 8008312: d110 bne.n 8008336 8008314: 7bfb ldrb r3, [r7, #15] 8008316: 2b00 cmp r3, #0 8008318: d10d bne.n 8008336 { (void)USBD_CtlSendStatus(pdev); 800831a: 6878 ldr r0, [r7, #4] 800831c: f000 fd73 bl 8008e06 } else { USBD_CtlError(pdev, req); } break; 8008320: e009 b.n 8008336 USBD_CtlError(pdev, req); 8008322: 6839 ldr r1, [r7, #0] 8008324: 6878 ldr r0, [r7, #4] 8008326: f000 fca3 bl 8008c70 break; 800832a: e004 b.n 8008336 default: USBD_CtlError(pdev, req); 800832c: 6839 ldr r1, [r7, #0] 800832e: 6878 ldr r0, [r7, #4] 8008330: f000 fc9e bl 8008c70 break; 8008334: e000 b.n 8008338 break; 8008336: bf00 nop } break; 8008338: e004 b.n 8008344 default: USBD_CtlError(pdev, req); 800833a: 6839 ldr r1, [r7, #0] 800833c: 6878 ldr r0, [r7, #4] 800833e: f000 fc97 bl 8008c70 break; 8008342: bf00 nop } return ret; 8008344: 7bfb ldrb r3, [r7, #15] } 8008346: 4618 mov r0, r3 8008348: 3710 adds r7, #16 800834a: 46bd mov sp, r7 800834c: bd80 pop {r7, pc} 0800834e : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800834e: b580 push {r7, lr} 8008350: b084 sub sp, #16 8008352: af00 add r7, sp, #0 8008354: 6078 str r0, [r7, #4] 8008356: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; USBD_StatusTypeDef ret = USBD_OK; 8008358: 2300 movs r3, #0 800835a: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 800835c: 683b ldr r3, [r7, #0] 800835e: 889b ldrh r3, [r3, #4] 8008360: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8008362: 683b ldr r3, [r7, #0] 8008364: 781b ldrb r3, [r3, #0] 8008366: f003 0360 and.w r3, r3, #96 ; 0x60 800836a: 2b40 cmp r3, #64 ; 0x40 800836c: d007 beq.n 800837e 800836e: 2b40 cmp r3, #64 ; 0x40 8008370: f200 8145 bhi.w 80085fe 8008374: 2b00 cmp r3, #0 8008376: d00c beq.n 8008392 8008378: 2b20 cmp r3, #32 800837a: f040 8140 bne.w 80085fe { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 800837e: 687b ldr r3, [r7, #4] 8008380: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008384: 689b ldr r3, [r3, #8] 8008386: 6839 ldr r1, [r7, #0] 8008388: 6878 ldr r0, [r7, #4] 800838a: 4798 blx r3 800838c: 4603 mov r3, r0 800838e: 73fb strb r3, [r7, #15] break; 8008390: e13a b.n 8008608 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8008392: 683b ldr r3, [r7, #0] 8008394: 785b ldrb r3, [r3, #1] 8008396: 2b03 cmp r3, #3 8008398: d007 beq.n 80083aa 800839a: 2b03 cmp r3, #3 800839c: f300 8129 bgt.w 80085f2 80083a0: 2b00 cmp r3, #0 80083a2: d07f beq.n 80084a4 80083a4: 2b01 cmp r3, #1 80083a6: d03c beq.n 8008422 80083a8: e123 b.n 80085f2 { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 80083aa: 687b ldr r3, [r7, #4] 80083ac: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80083b0: b2db uxtb r3, r3 80083b2: 2b02 cmp r3, #2 80083b4: d002 beq.n 80083bc 80083b6: 2b03 cmp r3, #3 80083b8: d016 beq.n 80083e8 80083ba: e02c b.n 8008416 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80083bc: 7bbb ldrb r3, [r7, #14] 80083be: 2b00 cmp r3, #0 80083c0: d00d beq.n 80083de 80083c2: 7bbb ldrb r3, [r7, #14] 80083c4: 2b80 cmp r3, #128 ; 0x80 80083c6: d00a beq.n 80083de { (void)USBD_LL_StallEP(pdev, ep_addr); 80083c8: 7bbb ldrb r3, [r7, #14] 80083ca: 4619 mov r1, r3 80083cc: 6878 ldr r0, [r7, #4] 80083ce: f001 f963 bl 8009698 (void)USBD_LL_StallEP(pdev, 0x80U); 80083d2: 2180 movs r1, #128 ; 0x80 80083d4: 6878 ldr r0, [r7, #4] 80083d6: f001 f95f bl 8009698 80083da: bf00 nop } else { USBD_CtlError(pdev, req); } break; 80083dc: e020 b.n 8008420 USBD_CtlError(pdev, req); 80083de: 6839 ldr r1, [r7, #0] 80083e0: 6878 ldr r0, [r7, #4] 80083e2: f000 fc45 bl 8008c70 break; 80083e6: e01b b.n 8008420 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 80083e8: 683b ldr r3, [r7, #0] 80083ea: 885b ldrh r3, [r3, #2] 80083ec: 2b00 cmp r3, #0 80083ee: d10e bne.n 800840e { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 80083f0: 7bbb ldrb r3, [r7, #14] 80083f2: 2b00 cmp r3, #0 80083f4: d00b beq.n 800840e 80083f6: 7bbb ldrb r3, [r7, #14] 80083f8: 2b80 cmp r3, #128 ; 0x80 80083fa: d008 beq.n 800840e 80083fc: 683b ldr r3, [r7, #0] 80083fe: 88db ldrh r3, [r3, #6] 8008400: 2b00 cmp r3, #0 8008402: d104 bne.n 800840e { (void)USBD_LL_StallEP(pdev, ep_addr); 8008404: 7bbb ldrb r3, [r7, #14] 8008406: 4619 mov r1, r3 8008408: 6878 ldr r0, [r7, #4] 800840a: f001 f945 bl 8009698 } } (void)USBD_CtlSendStatus(pdev); 800840e: 6878 ldr r0, [r7, #4] 8008410: f000 fcf9 bl 8008e06 break; 8008414: e004 b.n 8008420 default: USBD_CtlError(pdev, req); 8008416: 6839 ldr r1, [r7, #0] 8008418: 6878 ldr r0, [r7, #4] 800841a: f000 fc29 bl 8008c70 break; 800841e: bf00 nop } break; 8008420: e0ec b.n 80085fc case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 8008422: 687b ldr r3, [r7, #4] 8008424: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008428: b2db uxtb r3, r3 800842a: 2b02 cmp r3, #2 800842c: d002 beq.n 8008434 800842e: 2b03 cmp r3, #3 8008430: d016 beq.n 8008460 8008432: e030 b.n 8008496 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8008434: 7bbb ldrb r3, [r7, #14] 8008436: 2b00 cmp r3, #0 8008438: d00d beq.n 8008456 800843a: 7bbb ldrb r3, [r7, #14] 800843c: 2b80 cmp r3, #128 ; 0x80 800843e: d00a beq.n 8008456 { (void)USBD_LL_StallEP(pdev, ep_addr); 8008440: 7bbb ldrb r3, [r7, #14] 8008442: 4619 mov r1, r3 8008444: 6878 ldr r0, [r7, #4] 8008446: f001 f927 bl 8009698 (void)USBD_LL_StallEP(pdev, 0x80U); 800844a: 2180 movs r1, #128 ; 0x80 800844c: 6878 ldr r0, [r7, #4] 800844e: f001 f923 bl 8009698 8008452: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8008454: e025 b.n 80084a2 USBD_CtlError(pdev, req); 8008456: 6839 ldr r1, [r7, #0] 8008458: 6878 ldr r0, [r7, #4] 800845a: f000 fc09 bl 8008c70 break; 800845e: e020 b.n 80084a2 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8008460: 683b ldr r3, [r7, #0] 8008462: 885b ldrh r3, [r3, #2] 8008464: 2b00 cmp r3, #0 8008466: d11b bne.n 80084a0 { if ((ep_addr & 0x7FU) != 0x00U) 8008468: 7bbb ldrb r3, [r7, #14] 800846a: f003 037f and.w r3, r3, #127 ; 0x7f 800846e: 2b00 cmp r3, #0 8008470: d004 beq.n 800847c { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 8008472: 7bbb ldrb r3, [r7, #14] 8008474: 4619 mov r1, r3 8008476: 6878 ldr r0, [r7, #4] 8008478: f001 f92d bl 80096d6 } (void)USBD_CtlSendStatus(pdev); 800847c: 6878 ldr r0, [r7, #4] 800847e: f000 fcc2 bl 8008e06 ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 8008482: 687b ldr r3, [r7, #4] 8008484: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008488: 689b ldr r3, [r3, #8] 800848a: 6839 ldr r1, [r7, #0] 800848c: 6878 ldr r0, [r7, #4] 800848e: 4798 blx r3 8008490: 4603 mov r3, r0 8008492: 73fb strb r3, [r7, #15] } break; 8008494: e004 b.n 80084a0 default: USBD_CtlError(pdev, req); 8008496: 6839 ldr r1, [r7, #0] 8008498: 6878 ldr r0, [r7, #4] 800849a: f000 fbe9 bl 8008c70 break; 800849e: e000 b.n 80084a2 break; 80084a0: bf00 nop } break; 80084a2: e0ab b.n 80085fc case USB_REQ_GET_STATUS: switch (pdev->dev_state) 80084a4: 687b ldr r3, [r7, #4] 80084a6: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80084aa: b2db uxtb r3, r3 80084ac: 2b02 cmp r3, #2 80084ae: d002 beq.n 80084b6 80084b0: 2b03 cmp r3, #3 80084b2: d032 beq.n 800851a 80084b4: e097 b.n 80085e6 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80084b6: 7bbb ldrb r3, [r7, #14] 80084b8: 2b00 cmp r3, #0 80084ba: d007 beq.n 80084cc 80084bc: 7bbb ldrb r3, [r7, #14] 80084be: 2b80 cmp r3, #128 ; 0x80 80084c0: d004 beq.n 80084cc { USBD_CtlError(pdev, req); 80084c2: 6839 ldr r1, [r7, #0] 80084c4: 6878 ldr r0, [r7, #4] 80084c6: f000 fbd3 bl 8008c70 break; 80084ca: e091 b.n 80085f0 } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80084cc: f997 300e ldrsb.w r3, [r7, #14] 80084d0: 2b00 cmp r3, #0 80084d2: da0b bge.n 80084ec 80084d4: 7bbb ldrb r3, [r7, #14] 80084d6: f003 027f and.w r2, r3, #127 ; 0x7f 80084da: 4613 mov r3, r2 80084dc: 009b lsls r3, r3, #2 80084de: 4413 add r3, r2 80084e0: 009b lsls r3, r3, #2 80084e2: 3310 adds r3, #16 80084e4: 687a ldr r2, [r7, #4] 80084e6: 4413 add r3, r2 80084e8: 3304 adds r3, #4 80084ea: e00b b.n 8008504 &pdev->ep_out[ep_addr & 0x7FU]; 80084ec: 7bbb ldrb r3, [r7, #14] 80084ee: f003 027f and.w r2, r3, #127 ; 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80084f2: 4613 mov r3, r2 80084f4: 009b lsls r3, r3, #2 80084f6: 4413 add r3, r2 80084f8: 009b lsls r3, r3, #2 80084fa: f503 73a8 add.w r3, r3, #336 ; 0x150 80084fe: 687a ldr r2, [r7, #4] 8008500: 4413 add r3, r2 8008502: 3304 adds r3, #4 8008504: 60bb str r3, [r7, #8] pep->status = 0x0000U; 8008506: 68bb ldr r3, [r7, #8] 8008508: 2200 movs r2, #0 800850a: 601a str r2, [r3, #0] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 800850c: 68bb ldr r3, [r7, #8] 800850e: 2202 movs r2, #2 8008510: 4619 mov r1, r3 8008512: 6878 ldr r0, [r7, #4] 8008514: f000 fc1d bl 8008d52 break; 8008518: e06a b.n 80085f0 case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 800851a: f997 300e ldrsb.w r3, [r7, #14] 800851e: 2b00 cmp r3, #0 8008520: da11 bge.n 8008546 { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 8008522: 7bbb ldrb r3, [r7, #14] 8008524: f003 020f and.w r2, r3, #15 8008528: 6879 ldr r1, [r7, #4] 800852a: 4613 mov r3, r2 800852c: 009b lsls r3, r3, #2 800852e: 4413 add r3, r2 8008530: 009b lsls r3, r3, #2 8008532: 440b add r3, r1 8008534: 3324 adds r3, #36 ; 0x24 8008536: 881b ldrh r3, [r3, #0] 8008538: 2b00 cmp r3, #0 800853a: d117 bne.n 800856c { USBD_CtlError(pdev, req); 800853c: 6839 ldr r1, [r7, #0] 800853e: 6878 ldr r0, [r7, #4] 8008540: f000 fb96 bl 8008c70 break; 8008544: e054 b.n 80085f0 } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 8008546: 7bbb ldrb r3, [r7, #14] 8008548: f003 020f and.w r2, r3, #15 800854c: 6879 ldr r1, [r7, #4] 800854e: 4613 mov r3, r2 8008550: 009b lsls r3, r3, #2 8008552: 4413 add r3, r2 8008554: 009b lsls r3, r3, #2 8008556: 440b add r3, r1 8008558: f503 73b2 add.w r3, r3, #356 ; 0x164 800855c: 881b ldrh r3, [r3, #0] 800855e: 2b00 cmp r3, #0 8008560: d104 bne.n 800856c { USBD_CtlError(pdev, req); 8008562: 6839 ldr r1, [r7, #0] 8008564: 6878 ldr r0, [r7, #4] 8008566: f000 fb83 bl 8008c70 break; 800856a: e041 b.n 80085f0 } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800856c: f997 300e ldrsb.w r3, [r7, #14] 8008570: 2b00 cmp r3, #0 8008572: da0b bge.n 800858c 8008574: 7bbb ldrb r3, [r7, #14] 8008576: f003 027f and.w r2, r3, #127 ; 0x7f 800857a: 4613 mov r3, r2 800857c: 009b lsls r3, r3, #2 800857e: 4413 add r3, r2 8008580: 009b lsls r3, r3, #2 8008582: 3310 adds r3, #16 8008584: 687a ldr r2, [r7, #4] 8008586: 4413 add r3, r2 8008588: 3304 adds r3, #4 800858a: e00b b.n 80085a4 &pdev->ep_out[ep_addr & 0x7FU]; 800858c: 7bbb ldrb r3, [r7, #14] 800858e: f003 027f and.w r2, r3, #127 ; 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8008592: 4613 mov r3, r2 8008594: 009b lsls r3, r3, #2 8008596: 4413 add r3, r2 8008598: 009b lsls r3, r3, #2 800859a: f503 73a8 add.w r3, r3, #336 ; 0x150 800859e: 687a ldr r2, [r7, #4] 80085a0: 4413 add r3, r2 80085a2: 3304 adds r3, #4 80085a4: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 80085a6: 7bbb ldrb r3, [r7, #14] 80085a8: 2b00 cmp r3, #0 80085aa: d002 beq.n 80085b2 80085ac: 7bbb ldrb r3, [r7, #14] 80085ae: 2b80 cmp r3, #128 ; 0x80 80085b0: d103 bne.n 80085ba { pep->status = 0x0000U; 80085b2: 68bb ldr r3, [r7, #8] 80085b4: 2200 movs r2, #0 80085b6: 601a str r2, [r3, #0] 80085b8: e00e b.n 80085d8 } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 80085ba: 7bbb ldrb r3, [r7, #14] 80085bc: 4619 mov r1, r3 80085be: 6878 ldr r0, [r7, #4] 80085c0: f001 f8a8 bl 8009714 80085c4: 4603 mov r3, r0 80085c6: 2b00 cmp r3, #0 80085c8: d003 beq.n 80085d2 { pep->status = 0x0001U; 80085ca: 68bb ldr r3, [r7, #8] 80085cc: 2201 movs r2, #1 80085ce: 601a str r2, [r3, #0] 80085d0: e002 b.n 80085d8 } else { pep->status = 0x0000U; 80085d2: 68bb ldr r3, [r7, #8] 80085d4: 2200 movs r2, #0 80085d6: 601a str r2, [r3, #0] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 80085d8: 68bb ldr r3, [r7, #8] 80085da: 2202 movs r2, #2 80085dc: 4619 mov r1, r3 80085de: 6878 ldr r0, [r7, #4] 80085e0: f000 fbb7 bl 8008d52 break; 80085e4: e004 b.n 80085f0 default: USBD_CtlError(pdev, req); 80085e6: 6839 ldr r1, [r7, #0] 80085e8: 6878 ldr r0, [r7, #4] 80085ea: f000 fb41 bl 8008c70 break; 80085ee: bf00 nop } break; 80085f0: e004 b.n 80085fc default: USBD_CtlError(pdev, req); 80085f2: 6839 ldr r1, [r7, #0] 80085f4: 6878 ldr r0, [r7, #4] 80085f6: f000 fb3b bl 8008c70 break; 80085fa: bf00 nop } break; 80085fc: e004 b.n 8008608 default: USBD_CtlError(pdev, req); 80085fe: 6839 ldr r1, [r7, #0] 8008600: 6878 ldr r0, [r7, #4] 8008602: f000 fb35 bl 8008c70 break; 8008606: bf00 nop } return ret; 8008608: 7bfb ldrb r3, [r7, #15] } 800860a: 4618 mov r0, r3 800860c: 3710 adds r7, #16 800860e: 46bd mov sp, r7 8008610: bd80 pop {r7, pc} ... 08008614 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008614: b580 push {r7, lr} 8008616: b084 sub sp, #16 8008618: af00 add r7, sp, #0 800861a: 6078 str r0, [r7, #4] 800861c: 6039 str r1, [r7, #0] uint16_t len = 0U; 800861e: 2300 movs r3, #0 8008620: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 8008622: 2300 movs r3, #0 8008624: 60fb str r3, [r7, #12] uint8_t err = 0U; 8008626: 2300 movs r3, #0 8008628: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 800862a: 683b ldr r3, [r7, #0] 800862c: 885b ldrh r3, [r3, #2] 800862e: 0a1b lsrs r3, r3, #8 8008630: b29b uxth r3, r3 8008632: 3b01 subs r3, #1 8008634: 2b06 cmp r3, #6 8008636: f200 8128 bhi.w 800888a 800863a: a201 add r2, pc, #4 ; (adr r2, 8008640 ) 800863c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008640: 0800865d .word 0x0800865d 8008644: 08008675 .word 0x08008675 8008648: 080086b5 .word 0x080086b5 800864c: 0800888b .word 0x0800888b 8008650: 0800888b .word 0x0800888b 8008654: 0800882b .word 0x0800882b 8008658: 08008857 .word 0x08008857 err++; } break; #endif case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 800865c: 687b ldr r3, [r7, #4] 800865e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8008662: 681b ldr r3, [r3, #0] 8008664: 687a ldr r2, [r7, #4] 8008666: 7c12 ldrb r2, [r2, #16] 8008668: f107 0108 add.w r1, r7, #8 800866c: 4610 mov r0, r2 800866e: 4798 blx r3 8008670: 60f8 str r0, [r7, #12] break; 8008672: e112 b.n 800889a case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8008674: 687b ldr r3, [r7, #4] 8008676: 7c1b ldrb r3, [r3, #16] 8008678: 2b00 cmp r3, #0 800867a: d10d bne.n 8008698 { pbuf = pdev->pClass->GetHSConfigDescriptor(&len); 800867c: 687b ldr r3, [r7, #4] 800867e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008682: 6a9b ldr r3, [r3, #40] ; 0x28 8008684: f107 0208 add.w r2, r7, #8 8008688: 4610 mov r0, r2 800868a: 4798 blx r3 800868c: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800868e: 68fb ldr r3, [r7, #12] 8008690: 3301 adds r3, #1 8008692: 2202 movs r2, #2 8008694: 701a strb r2, [r3, #0] else { pbuf = pdev->pClass->GetFSConfigDescriptor(&len); pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 8008696: e100 b.n 800889a pbuf = pdev->pClass->GetFSConfigDescriptor(&len); 8008698: 687b ldr r3, [r7, #4] 800869a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800869e: 6adb ldr r3, [r3, #44] ; 0x2c 80086a0: f107 0208 add.w r2, r7, #8 80086a4: 4610 mov r0, r2 80086a6: 4798 blx r3 80086a8: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 80086aa: 68fb ldr r3, [r7, #12] 80086ac: 3301 adds r3, #1 80086ae: 2202 movs r2, #2 80086b0: 701a strb r2, [r3, #0] break; 80086b2: e0f2 b.n 800889a case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 80086b4: 683b ldr r3, [r7, #0] 80086b6: 885b ldrh r3, [r3, #2] 80086b8: b2db uxtb r3, r3 80086ba: 2b05 cmp r3, #5 80086bc: f200 80ac bhi.w 8008818 80086c0: a201 add r2, pc, #4 ; (adr r2, 80086c8 ) 80086c2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80086c6: bf00 nop 80086c8: 080086e1 .word 0x080086e1 80086cc: 08008715 .word 0x08008715 80086d0: 08008749 .word 0x08008749 80086d4: 0800877d .word 0x0800877d 80086d8: 080087b1 .word 0x080087b1 80086dc: 080087e5 .word 0x080087e5 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 80086e0: 687b ldr r3, [r7, #4] 80086e2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 80086e6: 685b ldr r3, [r3, #4] 80086e8: 2b00 cmp r3, #0 80086ea: d00b beq.n 8008704 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 80086ec: 687b ldr r3, [r7, #4] 80086ee: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 80086f2: 685b ldr r3, [r3, #4] 80086f4: 687a ldr r2, [r7, #4] 80086f6: 7c12 ldrb r2, [r2, #16] 80086f8: f107 0108 add.w r1, r7, #8 80086fc: 4610 mov r0, r2 80086fe: 4798 blx r3 8008700: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8008702: e091 b.n 8008828 USBD_CtlError(pdev, req); 8008704: 6839 ldr r1, [r7, #0] 8008706: 6878 ldr r0, [r7, #4] 8008708: f000 fab2 bl 8008c70 err++; 800870c: 7afb ldrb r3, [r7, #11] 800870e: 3301 adds r3, #1 8008710: 72fb strb r3, [r7, #11] break; 8008712: e089 b.n 8008828 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 8008714: 687b ldr r3, [r7, #4] 8008716: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 800871a: 689b ldr r3, [r3, #8] 800871c: 2b00 cmp r3, #0 800871e: d00b beq.n 8008738 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 8008720: 687b ldr r3, [r7, #4] 8008722: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8008726: 689b ldr r3, [r3, #8] 8008728: 687a ldr r2, [r7, #4] 800872a: 7c12 ldrb r2, [r2, #16] 800872c: f107 0108 add.w r1, r7, #8 8008730: 4610 mov r0, r2 8008732: 4798 blx r3 8008734: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8008736: e077 b.n 8008828 USBD_CtlError(pdev, req); 8008738: 6839 ldr r1, [r7, #0] 800873a: 6878 ldr r0, [r7, #4] 800873c: f000 fa98 bl 8008c70 err++; 8008740: 7afb ldrb r3, [r7, #11] 8008742: 3301 adds r3, #1 8008744: 72fb strb r3, [r7, #11] break; 8008746: e06f b.n 8008828 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 8008748: 687b ldr r3, [r7, #4] 800874a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 800874e: 68db ldr r3, [r3, #12] 8008750: 2b00 cmp r3, #0 8008752: d00b beq.n 800876c { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 8008754: 687b ldr r3, [r7, #4] 8008756: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 800875a: 68db ldr r3, [r3, #12] 800875c: 687a ldr r2, [r7, #4] 800875e: 7c12 ldrb r2, [r2, #16] 8008760: f107 0108 add.w r1, r7, #8 8008764: 4610 mov r0, r2 8008766: 4798 blx r3 8008768: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800876a: e05d b.n 8008828 USBD_CtlError(pdev, req); 800876c: 6839 ldr r1, [r7, #0] 800876e: 6878 ldr r0, [r7, #4] 8008770: f000 fa7e bl 8008c70 err++; 8008774: 7afb ldrb r3, [r7, #11] 8008776: 3301 adds r3, #1 8008778: 72fb strb r3, [r7, #11] break; 800877a: e055 b.n 8008828 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 800877c: 687b ldr r3, [r7, #4] 800877e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8008782: 691b ldr r3, [r3, #16] 8008784: 2b00 cmp r3, #0 8008786: d00b beq.n 80087a0 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 8008788: 687b ldr r3, [r7, #4] 800878a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 800878e: 691b ldr r3, [r3, #16] 8008790: 687a ldr r2, [r7, #4] 8008792: 7c12 ldrb r2, [r2, #16] 8008794: f107 0108 add.w r1, r7, #8 8008798: 4610 mov r0, r2 800879a: 4798 blx r3 800879c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800879e: e043 b.n 8008828 USBD_CtlError(pdev, req); 80087a0: 6839 ldr r1, [r7, #0] 80087a2: 6878 ldr r0, [r7, #4] 80087a4: f000 fa64 bl 8008c70 err++; 80087a8: 7afb ldrb r3, [r7, #11] 80087aa: 3301 adds r3, #1 80087ac: 72fb strb r3, [r7, #11] break; 80087ae: e03b b.n 8008828 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 80087b0: 687b ldr r3, [r7, #4] 80087b2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 80087b6: 695b ldr r3, [r3, #20] 80087b8: 2b00 cmp r3, #0 80087ba: d00b beq.n 80087d4 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 80087bc: 687b ldr r3, [r7, #4] 80087be: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 80087c2: 695b ldr r3, [r3, #20] 80087c4: 687a ldr r2, [r7, #4] 80087c6: 7c12 ldrb r2, [r2, #16] 80087c8: f107 0108 add.w r1, r7, #8 80087cc: 4610 mov r0, r2 80087ce: 4798 blx r3 80087d0: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80087d2: e029 b.n 8008828 USBD_CtlError(pdev, req); 80087d4: 6839 ldr r1, [r7, #0] 80087d6: 6878 ldr r0, [r7, #4] 80087d8: f000 fa4a bl 8008c70 err++; 80087dc: 7afb ldrb r3, [r7, #11] 80087de: 3301 adds r3, #1 80087e0: 72fb strb r3, [r7, #11] break; 80087e2: e021 b.n 8008828 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 80087e4: 687b ldr r3, [r7, #4] 80087e6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 80087ea: 699b ldr r3, [r3, #24] 80087ec: 2b00 cmp r3, #0 80087ee: d00b beq.n 8008808 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 80087f0: 687b ldr r3, [r7, #4] 80087f2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 80087f6: 699b ldr r3, [r3, #24] 80087f8: 687a ldr r2, [r7, #4] 80087fa: 7c12 ldrb r2, [r2, #16] 80087fc: f107 0108 add.w r1, r7, #8 8008800: 4610 mov r0, r2 8008802: 4798 blx r3 8008804: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8008806: e00f b.n 8008828 USBD_CtlError(pdev, req); 8008808: 6839 ldr r1, [r7, #0] 800880a: 6878 ldr r0, [r7, #4] 800880c: f000 fa30 bl 8008c70 err++; 8008810: 7afb ldrb r3, [r7, #11] 8008812: 3301 adds r3, #1 8008814: 72fb strb r3, [r7, #11] break; 8008816: e007 b.n 8008828 err++; } #endif #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 8008818: 6839 ldr r1, [r7, #0] 800881a: 6878 ldr r0, [r7, #4] 800881c: f000 fa28 bl 8008c70 err++; 8008820: 7afb ldrb r3, [r7, #11] 8008822: 3301 adds r3, #1 8008824: 72fb strb r3, [r7, #11] #endif break; 8008826: bf00 nop } break; 8008828: e037 b.n 800889a case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 800882a: 687b ldr r3, [r7, #4] 800882c: 7c1b ldrb r3, [r3, #16] 800882e: 2b00 cmp r3, #0 8008830: d109 bne.n 8008846 { pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len); 8008832: 687b ldr r3, [r7, #4] 8008834: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008838: 6b5b ldr r3, [r3, #52] ; 0x34 800883a: f107 0208 add.w r2, r7, #8 800883e: 4610 mov r0, r2 8008840: 4798 blx r3 8008842: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8008844: e029 b.n 800889a USBD_CtlError(pdev, req); 8008846: 6839 ldr r1, [r7, #0] 8008848: 6878 ldr r0, [r7, #4] 800884a: f000 fa11 bl 8008c70 err++; 800884e: 7afb ldrb r3, [r7, #11] 8008850: 3301 adds r3, #1 8008852: 72fb strb r3, [r7, #11] break; 8008854: e021 b.n 800889a case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8008856: 687b ldr r3, [r7, #4] 8008858: 7c1b ldrb r3, [r3, #16] 800885a: 2b00 cmp r3, #0 800885c: d10d bne.n 800887a { pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len); 800885e: 687b ldr r3, [r7, #4] 8008860: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8008864: 6b1b ldr r3, [r3, #48] ; 0x30 8008866: f107 0208 add.w r2, r7, #8 800886a: 4610 mov r0, r2 800886c: 4798 blx r3 800886e: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 8008870: 68fb ldr r3, [r7, #12] 8008872: 3301 adds r3, #1 8008874: 2207 movs r2, #7 8008876: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 8008878: e00f b.n 800889a USBD_CtlError(pdev, req); 800887a: 6839 ldr r1, [r7, #0] 800887c: 6878 ldr r0, [r7, #4] 800887e: f000 f9f7 bl 8008c70 err++; 8008882: 7afb ldrb r3, [r7, #11] 8008884: 3301 adds r3, #1 8008886: 72fb strb r3, [r7, #11] break; 8008888: e007 b.n 800889a default: USBD_CtlError(pdev, req); 800888a: 6839 ldr r1, [r7, #0] 800888c: 6878 ldr r0, [r7, #4] 800888e: f000 f9ef bl 8008c70 err++; 8008892: 7afb ldrb r3, [r7, #11] 8008894: 3301 adds r3, #1 8008896: 72fb strb r3, [r7, #11] break; 8008898: bf00 nop } if (err != 0U) 800889a: 7afb ldrb r3, [r7, #11] 800889c: 2b00 cmp r3, #0 800889e: d11e bne.n 80088de { return; } if (req->wLength != 0U) 80088a0: 683b ldr r3, [r7, #0] 80088a2: 88db ldrh r3, [r3, #6] 80088a4: 2b00 cmp r3, #0 80088a6: d016 beq.n 80088d6 { if (len != 0U) 80088a8: 893b ldrh r3, [r7, #8] 80088aa: 2b00 cmp r3, #0 80088ac: d00e beq.n 80088cc { len = MIN(len, req->wLength); 80088ae: 683b ldr r3, [r7, #0] 80088b0: 88da ldrh r2, [r3, #6] 80088b2: 893b ldrh r3, [r7, #8] 80088b4: 4293 cmp r3, r2 80088b6: bf28 it cs 80088b8: 4613 movcs r3, r2 80088ba: b29b uxth r3, r3 80088bc: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 80088be: 893b ldrh r3, [r7, #8] 80088c0: 461a mov r2, r3 80088c2: 68f9 ldr r1, [r7, #12] 80088c4: 6878 ldr r0, [r7, #4] 80088c6: f000 fa44 bl 8008d52 80088ca: e009 b.n 80088e0 } else { USBD_CtlError(pdev, req); 80088cc: 6839 ldr r1, [r7, #0] 80088ce: 6878 ldr r0, [r7, #4] 80088d0: f000 f9ce bl 8008c70 80088d4: e004 b.n 80088e0 } } else { (void)USBD_CtlSendStatus(pdev); 80088d6: 6878 ldr r0, [r7, #4] 80088d8: f000 fa95 bl 8008e06 80088dc: e000 b.n 80088e0 return; 80088de: bf00 nop } } 80088e0: 3710 adds r7, #16 80088e2: 46bd mov sp, r7 80088e4: bd80 pop {r7, pc} 80088e6: bf00 nop 080088e8 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80088e8: b580 push {r7, lr} 80088ea: b084 sub sp, #16 80088ec: af00 add r7, sp, #0 80088ee: 6078 str r0, [r7, #4] 80088f0: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 80088f2: 683b ldr r3, [r7, #0] 80088f4: 889b ldrh r3, [r3, #4] 80088f6: 2b00 cmp r3, #0 80088f8: d131 bne.n 800895e 80088fa: 683b ldr r3, [r7, #0] 80088fc: 88db ldrh r3, [r3, #6] 80088fe: 2b00 cmp r3, #0 8008900: d12d bne.n 800895e 8008902: 683b ldr r3, [r7, #0] 8008904: 885b ldrh r3, [r3, #2] 8008906: 2b7f cmp r3, #127 ; 0x7f 8008908: d829 bhi.n 800895e { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 800890a: 683b ldr r3, [r7, #0] 800890c: 885b ldrh r3, [r3, #2] 800890e: b2db uxtb r3, r3 8008910: f003 037f and.w r3, r3, #127 ; 0x7f 8008914: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008916: 687b ldr r3, [r7, #4] 8008918: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 800891c: b2db uxtb r3, r3 800891e: 2b03 cmp r3, #3 8008920: d104 bne.n 800892c { USBD_CtlError(pdev, req); 8008922: 6839 ldr r1, [r7, #0] 8008924: 6878 ldr r0, [r7, #4] 8008926: f000 f9a3 bl 8008c70 if (pdev->dev_state == USBD_STATE_CONFIGURED) 800892a: e01d b.n 8008968 } else { pdev->dev_address = dev_addr; 800892c: 687b ldr r3, [r7, #4] 800892e: 7bfa ldrb r2, [r7, #15] 8008930: f883 229e strb.w r2, [r3, #670] ; 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 8008934: 7bfb ldrb r3, [r7, #15] 8008936: 4619 mov r1, r3 8008938: 6878 ldr r0, [r7, #4] 800893a: f000 ff17 bl 800976c (void)USBD_CtlSendStatus(pdev); 800893e: 6878 ldr r0, [r7, #4] 8008940: f000 fa61 bl 8008e06 if (dev_addr != 0U) 8008944: 7bfb ldrb r3, [r7, #15] 8008946: 2b00 cmp r3, #0 8008948: d004 beq.n 8008954 { pdev->dev_state = USBD_STATE_ADDRESSED; 800894a: 687b ldr r3, [r7, #4] 800894c: 2202 movs r2, #2 800894e: f883 229c strb.w r2, [r3, #668] ; 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008952: e009 b.n 8008968 } else { pdev->dev_state = USBD_STATE_DEFAULT; 8008954: 687b ldr r3, [r7, #4] 8008956: 2201 movs r2, #1 8008958: f883 229c strb.w r2, [r3, #668] ; 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 800895c: e004 b.n 8008968 } } } else { USBD_CtlError(pdev, req); 800895e: 6839 ldr r1, [r7, #0] 8008960: 6878 ldr r0, [r7, #4] 8008962: f000 f985 bl 8008c70 } } 8008966: bf00 nop 8008968: bf00 nop 800896a: 3710 adds r7, #16 800896c: 46bd mov sp, r7 800896e: bd80 pop {r7, pc} 08008970 : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008970: b580 push {r7, lr} 8008972: b084 sub sp, #16 8008974: af00 add r7, sp, #0 8008976: 6078 str r0, [r7, #4] 8008978: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800897a: 2300 movs r3, #0 800897c: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 800897e: 683b ldr r3, [r7, #0] 8008980: 885b ldrh r3, [r3, #2] 8008982: b2da uxtb r2, r3 8008984: 4b4c ldr r3, [pc, #304] ; (8008ab8 ) 8008986: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 8008988: 4b4b ldr r3, [pc, #300] ; (8008ab8 ) 800898a: 781b ldrb r3, [r3, #0] 800898c: 2b01 cmp r3, #1 800898e: d905 bls.n 800899c { USBD_CtlError(pdev, req); 8008990: 6839 ldr r1, [r7, #0] 8008992: 6878 ldr r0, [r7, #4] 8008994: f000 f96c bl 8008c70 return USBD_FAIL; 8008998: 2303 movs r3, #3 800899a: e088 b.n 8008aae } switch (pdev->dev_state) 800899c: 687b ldr r3, [r7, #4] 800899e: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80089a2: b2db uxtb r3, r3 80089a4: 2b02 cmp r3, #2 80089a6: d002 beq.n 80089ae 80089a8: 2b03 cmp r3, #3 80089aa: d025 beq.n 80089f8 80089ac: e071 b.n 8008a92 { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 80089ae: 4b42 ldr r3, [pc, #264] ; (8008ab8 ) 80089b0: 781b ldrb r3, [r3, #0] 80089b2: 2b00 cmp r3, #0 80089b4: d01c beq.n 80089f0 { pdev->dev_config = cfgidx; 80089b6: 4b40 ldr r3, [pc, #256] ; (8008ab8 ) 80089b8: 781b ldrb r3, [r3, #0] 80089ba: 461a mov r2, r3 80089bc: 687b ldr r3, [r7, #4] 80089be: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 80089c0: 4b3d ldr r3, [pc, #244] ; (8008ab8 ) 80089c2: 781b ldrb r3, [r3, #0] 80089c4: 4619 mov r1, r3 80089c6: 6878 ldr r0, [r7, #4] 80089c8: f7ff f948 bl 8007c5c 80089cc: 4603 mov r3, r0 80089ce: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 80089d0: 7bfb ldrb r3, [r7, #15] 80089d2: 2b00 cmp r3, #0 80089d4: d004 beq.n 80089e0 { USBD_CtlError(pdev, req); 80089d6: 6839 ldr r1, [r7, #0] 80089d8: 6878 ldr r0, [r7, #4] 80089da: f000 f949 bl 8008c70 } else { (void)USBD_CtlSendStatus(pdev); } break; 80089de: e065 b.n 8008aac (void)USBD_CtlSendStatus(pdev); 80089e0: 6878 ldr r0, [r7, #4] 80089e2: f000 fa10 bl 8008e06 pdev->dev_state = USBD_STATE_CONFIGURED; 80089e6: 687b ldr r3, [r7, #4] 80089e8: 2203 movs r2, #3 80089ea: f883 229c strb.w r2, [r3, #668] ; 0x29c break; 80089ee: e05d b.n 8008aac (void)USBD_CtlSendStatus(pdev); 80089f0: 6878 ldr r0, [r7, #4] 80089f2: f000 fa08 bl 8008e06 break; 80089f6: e059 b.n 8008aac case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 80089f8: 4b2f ldr r3, [pc, #188] ; (8008ab8 ) 80089fa: 781b ldrb r3, [r3, #0] 80089fc: 2b00 cmp r3, #0 80089fe: d112 bne.n 8008a26 { pdev->dev_state = USBD_STATE_ADDRESSED; 8008a00: 687b ldr r3, [r7, #4] 8008a02: 2202 movs r2, #2 8008a04: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->dev_config = cfgidx; 8008a08: 4b2b ldr r3, [pc, #172] ; (8008ab8 ) 8008a0a: 781b ldrb r3, [r3, #0] 8008a0c: 461a mov r2, r3 8008a0e: 687b ldr r3, [r7, #4] 8008a10: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 8008a12: 4b29 ldr r3, [pc, #164] ; (8008ab8 ) 8008a14: 781b ldrb r3, [r3, #0] 8008a16: 4619 mov r1, r3 8008a18: 6878 ldr r0, [r7, #4] 8008a1a: f7ff f93b bl 8007c94 (void)USBD_CtlSendStatus(pdev); 8008a1e: 6878 ldr r0, [r7, #4] 8008a20: f000 f9f1 bl 8008e06 } else { (void)USBD_CtlSendStatus(pdev); } break; 8008a24: e042 b.n 8008aac else if (cfgidx != pdev->dev_config) 8008a26: 4b24 ldr r3, [pc, #144] ; (8008ab8 ) 8008a28: 781b ldrb r3, [r3, #0] 8008a2a: 461a mov r2, r3 8008a2c: 687b ldr r3, [r7, #4] 8008a2e: 685b ldr r3, [r3, #4] 8008a30: 429a cmp r2, r3 8008a32: d02a beq.n 8008a8a (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8008a34: 687b ldr r3, [r7, #4] 8008a36: 685b ldr r3, [r3, #4] 8008a38: b2db uxtb r3, r3 8008a3a: 4619 mov r1, r3 8008a3c: 6878 ldr r0, [r7, #4] 8008a3e: f7ff f929 bl 8007c94 pdev->dev_config = cfgidx; 8008a42: 4b1d ldr r3, [pc, #116] ; (8008ab8 ) 8008a44: 781b ldrb r3, [r3, #0] 8008a46: 461a mov r2, r3 8008a48: 687b ldr r3, [r7, #4] 8008a4a: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8008a4c: 4b1a ldr r3, [pc, #104] ; (8008ab8 ) 8008a4e: 781b ldrb r3, [r3, #0] 8008a50: 4619 mov r1, r3 8008a52: 6878 ldr r0, [r7, #4] 8008a54: f7ff f902 bl 8007c5c 8008a58: 4603 mov r3, r0 8008a5a: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8008a5c: 7bfb ldrb r3, [r7, #15] 8008a5e: 2b00 cmp r3, #0 8008a60: d00f beq.n 8008a82 USBD_CtlError(pdev, req); 8008a62: 6839 ldr r1, [r7, #0] 8008a64: 6878 ldr r0, [r7, #4] 8008a66: f000 f903 bl 8008c70 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8008a6a: 687b ldr r3, [r7, #4] 8008a6c: 685b ldr r3, [r3, #4] 8008a6e: b2db uxtb r3, r3 8008a70: 4619 mov r1, r3 8008a72: 6878 ldr r0, [r7, #4] 8008a74: f7ff f90e bl 8007c94 pdev->dev_state = USBD_STATE_ADDRESSED; 8008a78: 687b ldr r3, [r7, #4] 8008a7a: 2202 movs r2, #2 8008a7c: f883 229c strb.w r2, [r3, #668] ; 0x29c break; 8008a80: e014 b.n 8008aac (void)USBD_CtlSendStatus(pdev); 8008a82: 6878 ldr r0, [r7, #4] 8008a84: f000 f9bf bl 8008e06 break; 8008a88: e010 b.n 8008aac (void)USBD_CtlSendStatus(pdev); 8008a8a: 6878 ldr r0, [r7, #4] 8008a8c: f000 f9bb bl 8008e06 break; 8008a90: e00c b.n 8008aac default: USBD_CtlError(pdev, req); 8008a92: 6839 ldr r1, [r7, #0] 8008a94: 6878 ldr r0, [r7, #4] 8008a96: f000 f8eb bl 8008c70 (void)USBD_ClrClassConfig(pdev, cfgidx); 8008a9a: 4b07 ldr r3, [pc, #28] ; (8008ab8 ) 8008a9c: 781b ldrb r3, [r3, #0] 8008a9e: 4619 mov r1, r3 8008aa0: 6878 ldr r0, [r7, #4] 8008aa2: f7ff f8f7 bl 8007c94 ret = USBD_FAIL; 8008aa6: 2303 movs r3, #3 8008aa8: 73fb strb r3, [r7, #15] break; 8008aaa: bf00 nop } return ret; 8008aac: 7bfb ldrb r3, [r7, #15] } 8008aae: 4618 mov r0, r3 8008ab0: 3710 adds r7, #16 8008ab2: 46bd mov sp, r7 8008ab4: bd80 pop {r7, pc} 8008ab6: bf00 nop 8008ab8: 240011b4 .word 0x240011b4 08008abc : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008abc: b580 push {r7, lr} 8008abe: b082 sub sp, #8 8008ac0: af00 add r7, sp, #0 8008ac2: 6078 str r0, [r7, #4] 8008ac4: 6039 str r1, [r7, #0] if (req->wLength != 1U) 8008ac6: 683b ldr r3, [r7, #0] 8008ac8: 88db ldrh r3, [r3, #6] 8008aca: 2b01 cmp r3, #1 8008acc: d004 beq.n 8008ad8 { USBD_CtlError(pdev, req); 8008ace: 6839 ldr r1, [r7, #0] 8008ad0: 6878 ldr r0, [r7, #4] 8008ad2: f000 f8cd bl 8008c70 default: USBD_CtlError(pdev, req); break; } } } 8008ad6: e023 b.n 8008b20 switch (pdev->dev_state) 8008ad8: 687b ldr r3, [r7, #4] 8008ada: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008ade: b2db uxtb r3, r3 8008ae0: 2b02 cmp r3, #2 8008ae2: dc02 bgt.n 8008aea 8008ae4: 2b00 cmp r3, #0 8008ae6: dc03 bgt.n 8008af0 8008ae8: e015 b.n 8008b16 8008aea: 2b03 cmp r3, #3 8008aec: d00b beq.n 8008b06 8008aee: e012 b.n 8008b16 pdev->dev_default_config = 0U; 8008af0: 687b ldr r3, [r7, #4] 8008af2: 2200 movs r2, #0 8008af4: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 8008af6: 687b ldr r3, [r7, #4] 8008af8: 3308 adds r3, #8 8008afa: 2201 movs r2, #1 8008afc: 4619 mov r1, r3 8008afe: 6878 ldr r0, [r7, #4] 8008b00: f000 f927 bl 8008d52 break; 8008b04: e00c b.n 8008b20 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 8008b06: 687b ldr r3, [r7, #4] 8008b08: 3304 adds r3, #4 8008b0a: 2201 movs r2, #1 8008b0c: 4619 mov r1, r3 8008b0e: 6878 ldr r0, [r7, #4] 8008b10: f000 f91f bl 8008d52 break; 8008b14: e004 b.n 8008b20 USBD_CtlError(pdev, req); 8008b16: 6839 ldr r1, [r7, #0] 8008b18: 6878 ldr r0, [r7, #4] 8008b1a: f000 f8a9 bl 8008c70 break; 8008b1e: bf00 nop } 8008b20: bf00 nop 8008b22: 3708 adds r7, #8 8008b24: 46bd mov sp, r7 8008b26: bd80 pop {r7, pc} 08008b28 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008b28: b580 push {r7, lr} 8008b2a: b082 sub sp, #8 8008b2c: af00 add r7, sp, #0 8008b2e: 6078 str r0, [r7, #4] 8008b30: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8008b32: 687b ldr r3, [r7, #4] 8008b34: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008b38: b2db uxtb r3, r3 8008b3a: 3b01 subs r3, #1 8008b3c: 2b02 cmp r3, #2 8008b3e: d81e bhi.n 8008b7e { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 8008b40: 683b ldr r3, [r7, #0] 8008b42: 88db ldrh r3, [r3, #6] 8008b44: 2b02 cmp r3, #2 8008b46: d004 beq.n 8008b52 { USBD_CtlError(pdev, req); 8008b48: 6839 ldr r1, [r7, #0] 8008b4a: 6878 ldr r0, [r7, #4] 8008b4c: f000 f890 bl 8008c70 break; 8008b50: e01a b.n 8008b88 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 8008b52: 687b ldr r3, [r7, #4] 8008b54: 2201 movs r2, #1 8008b56: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif if (pdev->dev_remote_wakeup != 0U) 8008b58: 687b ldr r3, [r7, #4] 8008b5a: f8d3 32a4 ldr.w r3, [r3, #676] ; 0x2a4 8008b5e: 2b00 cmp r3, #0 8008b60: d005 beq.n 8008b6e { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 8008b62: 687b ldr r3, [r7, #4] 8008b64: 68db ldr r3, [r3, #12] 8008b66: f043 0202 orr.w r2, r3, #2 8008b6a: 687b ldr r3, [r7, #4] 8008b6c: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 8008b6e: 687b ldr r3, [r7, #4] 8008b70: 330c adds r3, #12 8008b72: 2202 movs r2, #2 8008b74: 4619 mov r1, r3 8008b76: 6878 ldr r0, [r7, #4] 8008b78: f000 f8eb bl 8008d52 break; 8008b7c: e004 b.n 8008b88 default: USBD_CtlError(pdev, req); 8008b7e: 6839 ldr r1, [r7, #0] 8008b80: 6878 ldr r0, [r7, #4] 8008b82: f000 f875 bl 8008c70 break; 8008b86: bf00 nop } } 8008b88: bf00 nop 8008b8a: 3708 adds r7, #8 8008b8c: 46bd mov sp, r7 8008b8e: bd80 pop {r7, pc} 08008b90 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008b90: b580 push {r7, lr} 8008b92: b082 sub sp, #8 8008b94: af00 add r7, sp, #0 8008b96: 6078 str r0, [r7, #4] 8008b98: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8008b9a: 683b ldr r3, [r7, #0] 8008b9c: 885b ldrh r3, [r3, #2] 8008b9e: 2b01 cmp r3, #1 8008ba0: d106 bne.n 8008bb0 { pdev->dev_remote_wakeup = 1U; 8008ba2: 687b ldr r3, [r7, #4] 8008ba4: 2201 movs r2, #1 8008ba6: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 (void)USBD_CtlSendStatus(pdev); 8008baa: 6878 ldr r0, [r7, #4] 8008bac: f000 f92b bl 8008e06 } } 8008bb0: bf00 nop 8008bb2: 3708 adds r7, #8 8008bb4: 46bd mov sp, r7 8008bb6: bd80 pop {r7, pc} 08008bb8 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008bb8: b580 push {r7, lr} 8008bba: b082 sub sp, #8 8008bbc: af00 add r7, sp, #0 8008bbe: 6078 str r0, [r7, #4] 8008bc0: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8008bc2: 687b ldr r3, [r7, #4] 8008bc4: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008bc8: b2db uxtb r3, r3 8008bca: 3b01 subs r3, #1 8008bcc: 2b02 cmp r3, #2 8008bce: d80b bhi.n 8008be8 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8008bd0: 683b ldr r3, [r7, #0] 8008bd2: 885b ldrh r3, [r3, #2] 8008bd4: 2b01 cmp r3, #1 8008bd6: d10c bne.n 8008bf2 { pdev->dev_remote_wakeup = 0U; 8008bd8: 687b ldr r3, [r7, #4] 8008bda: 2200 movs r2, #0 8008bdc: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 (void)USBD_CtlSendStatus(pdev); 8008be0: 6878 ldr r0, [r7, #4] 8008be2: f000 f910 bl 8008e06 } break; 8008be6: e004 b.n 8008bf2 default: USBD_CtlError(pdev, req); 8008be8: 6839 ldr r1, [r7, #0] 8008bea: 6878 ldr r0, [r7, #4] 8008bec: f000 f840 bl 8008c70 break; 8008bf0: e000 b.n 8008bf4 break; 8008bf2: bf00 nop } } 8008bf4: bf00 nop 8008bf6: 3708 adds r7, #8 8008bf8: 46bd mov sp, r7 8008bfa: bd80 pop {r7, pc} 08008bfc : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 8008bfc: b580 push {r7, lr} 8008bfe: b084 sub sp, #16 8008c00: af00 add r7, sp, #0 8008c02: 6078 str r0, [r7, #4] 8008c04: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 8008c06: 683b ldr r3, [r7, #0] 8008c08: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 8008c0a: 68fb ldr r3, [r7, #12] 8008c0c: 781a ldrb r2, [r3, #0] 8008c0e: 687b ldr r3, [r7, #4] 8008c10: 701a strb r2, [r3, #0] pbuff++; 8008c12: 68fb ldr r3, [r7, #12] 8008c14: 3301 adds r3, #1 8008c16: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 8008c18: 68fb ldr r3, [r7, #12] 8008c1a: 781a ldrb r2, [r3, #0] 8008c1c: 687b ldr r3, [r7, #4] 8008c1e: 705a strb r2, [r3, #1] pbuff++; 8008c20: 68fb ldr r3, [r7, #12] 8008c22: 3301 adds r3, #1 8008c24: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 8008c26: 68f8 ldr r0, [r7, #12] 8008c28: f7ff fabb bl 80081a2 8008c2c: 4603 mov r3, r0 8008c2e: 461a mov r2, r3 8008c30: 687b ldr r3, [r7, #4] 8008c32: 805a strh r2, [r3, #2] pbuff++; 8008c34: 68fb ldr r3, [r7, #12] 8008c36: 3301 adds r3, #1 8008c38: 60fb str r3, [r7, #12] pbuff++; 8008c3a: 68fb ldr r3, [r7, #12] 8008c3c: 3301 adds r3, #1 8008c3e: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 8008c40: 68f8 ldr r0, [r7, #12] 8008c42: f7ff faae bl 80081a2 8008c46: 4603 mov r3, r0 8008c48: 461a mov r2, r3 8008c4a: 687b ldr r3, [r7, #4] 8008c4c: 809a strh r2, [r3, #4] pbuff++; 8008c4e: 68fb ldr r3, [r7, #12] 8008c50: 3301 adds r3, #1 8008c52: 60fb str r3, [r7, #12] pbuff++; 8008c54: 68fb ldr r3, [r7, #12] 8008c56: 3301 adds r3, #1 8008c58: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 8008c5a: 68f8 ldr r0, [r7, #12] 8008c5c: f7ff faa1 bl 80081a2 8008c60: 4603 mov r3, r0 8008c62: 461a mov r2, r3 8008c64: 687b ldr r3, [r7, #4] 8008c66: 80da strh r2, [r3, #6] } 8008c68: bf00 nop 8008c6a: 3710 adds r7, #16 8008c6c: 46bd mov sp, r7 8008c6e: bd80 pop {r7, pc} 08008c70 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008c70: b580 push {r7, lr} 8008c72: b082 sub sp, #8 8008c74: af00 add r7, sp, #0 8008c76: 6078 str r0, [r7, #4] 8008c78: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 8008c7a: 2180 movs r1, #128 ; 0x80 8008c7c: 6878 ldr r0, [r7, #4] 8008c7e: f000 fd0b bl 8009698 (void)USBD_LL_StallEP(pdev, 0U); 8008c82: 2100 movs r1, #0 8008c84: 6878 ldr r0, [r7, #4] 8008c86: f000 fd07 bl 8009698 } 8008c8a: bf00 nop 8008c8c: 3708 adds r7, #8 8008c8e: 46bd mov sp, r7 8008c90: bd80 pop {r7, pc} 08008c92 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 8008c92: b580 push {r7, lr} 8008c94: b086 sub sp, #24 8008c96: af00 add r7, sp, #0 8008c98: 60f8 str r0, [r7, #12] 8008c9a: 60b9 str r1, [r7, #8] 8008c9c: 607a str r2, [r7, #4] uint8_t idx = 0U; 8008c9e: 2300 movs r3, #0 8008ca0: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 8008ca2: 68fb ldr r3, [r7, #12] 8008ca4: 2b00 cmp r3, #0 8008ca6: d036 beq.n 8008d16 { return; } pdesc = desc; 8008ca8: 68fb ldr r3, [r7, #12] 8008caa: 613b str r3, [r7, #16] *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U; 8008cac: 6938 ldr r0, [r7, #16] 8008cae: f000 f836 bl 8008d1e 8008cb2: 4603 mov r3, r0 8008cb4: 3301 adds r3, #1 8008cb6: b29b uxth r3, r3 8008cb8: 005b lsls r3, r3, #1 8008cba: b29a uxth r2, r3 8008cbc: 687b ldr r3, [r7, #4] 8008cbe: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 8008cc0: 7dfb ldrb r3, [r7, #23] 8008cc2: 68ba ldr r2, [r7, #8] 8008cc4: 4413 add r3, r2 8008cc6: 687a ldr r2, [r7, #4] 8008cc8: 7812 ldrb r2, [r2, #0] 8008cca: 701a strb r2, [r3, #0] idx++; 8008ccc: 7dfb ldrb r3, [r7, #23] 8008cce: 3301 adds r3, #1 8008cd0: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 8008cd2: 7dfb ldrb r3, [r7, #23] 8008cd4: 68ba ldr r2, [r7, #8] 8008cd6: 4413 add r3, r2 8008cd8: 2203 movs r2, #3 8008cda: 701a strb r2, [r3, #0] idx++; 8008cdc: 7dfb ldrb r3, [r7, #23] 8008cde: 3301 adds r3, #1 8008ce0: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8008ce2: e013 b.n 8008d0c { unicode[idx] = *pdesc; 8008ce4: 7dfb ldrb r3, [r7, #23] 8008ce6: 68ba ldr r2, [r7, #8] 8008ce8: 4413 add r3, r2 8008cea: 693a ldr r2, [r7, #16] 8008cec: 7812 ldrb r2, [r2, #0] 8008cee: 701a strb r2, [r3, #0] pdesc++; 8008cf0: 693b ldr r3, [r7, #16] 8008cf2: 3301 adds r3, #1 8008cf4: 613b str r3, [r7, #16] idx++; 8008cf6: 7dfb ldrb r3, [r7, #23] 8008cf8: 3301 adds r3, #1 8008cfa: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 8008cfc: 7dfb ldrb r3, [r7, #23] 8008cfe: 68ba ldr r2, [r7, #8] 8008d00: 4413 add r3, r2 8008d02: 2200 movs r2, #0 8008d04: 701a strb r2, [r3, #0] idx++; 8008d06: 7dfb ldrb r3, [r7, #23] 8008d08: 3301 adds r3, #1 8008d0a: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8008d0c: 693b ldr r3, [r7, #16] 8008d0e: 781b ldrb r3, [r3, #0] 8008d10: 2b00 cmp r3, #0 8008d12: d1e7 bne.n 8008ce4 8008d14: e000 b.n 8008d18 return; 8008d16: bf00 nop } } 8008d18: 3718 adds r7, #24 8008d1a: 46bd mov sp, r7 8008d1c: bd80 pop {r7, pc} 08008d1e : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 8008d1e: b480 push {r7} 8008d20: b085 sub sp, #20 8008d22: af00 add r7, sp, #0 8008d24: 6078 str r0, [r7, #4] uint8_t len = 0U; 8008d26: 2300 movs r3, #0 8008d28: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 8008d2a: 687b ldr r3, [r7, #4] 8008d2c: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 8008d2e: e005 b.n 8008d3c { len++; 8008d30: 7bfb ldrb r3, [r7, #15] 8008d32: 3301 adds r3, #1 8008d34: 73fb strb r3, [r7, #15] pbuff++; 8008d36: 68bb ldr r3, [r7, #8] 8008d38: 3301 adds r3, #1 8008d3a: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 8008d3c: 68bb ldr r3, [r7, #8] 8008d3e: 781b ldrb r3, [r3, #0] 8008d40: 2b00 cmp r3, #0 8008d42: d1f5 bne.n 8008d30 } return len; 8008d44: 7bfb ldrb r3, [r7, #15] } 8008d46: 4618 mov r0, r3 8008d48: 3714 adds r7, #20 8008d4a: 46bd mov sp, r7 8008d4c: f85d 7b04 ldr.w r7, [sp], #4 8008d50: 4770 bx lr 08008d52 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8008d52: b580 push {r7, lr} 8008d54: b084 sub sp, #16 8008d56: af00 add r7, sp, #0 8008d58: 60f8 str r0, [r7, #12] 8008d5a: 60b9 str r1, [r7, #8] 8008d5c: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 8008d5e: 68fb ldr r3, [r7, #12] 8008d60: 2202 movs r2, #2 8008d62: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->ep_in[0].total_length = len; 8008d66: 68fb ldr r3, [r7, #12] 8008d68: 687a ldr r2, [r7, #4] 8008d6a: 619a str r2, [r3, #24] #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 8008d6c: 68fb ldr r3, [r7, #12] 8008d6e: 687a ldr r2, [r7, #4] 8008d70: 61da str r2, [r3, #28] #endif /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8008d72: 687b ldr r3, [r7, #4] 8008d74: 68ba ldr r2, [r7, #8] 8008d76: 2100 movs r1, #0 8008d78: 68f8 ldr r0, [r7, #12] 8008d7a: f000 fd16 bl 80097aa return USBD_OK; 8008d7e: 2300 movs r3, #0 } 8008d80: 4618 mov r0, r3 8008d82: 3710 adds r7, #16 8008d84: 46bd mov sp, r7 8008d86: bd80 pop {r7, pc} 08008d88 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8008d88: b580 push {r7, lr} 8008d8a: b084 sub sp, #16 8008d8c: af00 add r7, sp, #0 8008d8e: 60f8 str r0, [r7, #12] 8008d90: 60b9 str r1, [r7, #8] 8008d92: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8008d94: 687b ldr r3, [r7, #4] 8008d96: 68ba ldr r2, [r7, #8] 8008d98: 2100 movs r1, #0 8008d9a: 68f8 ldr r0, [r7, #12] 8008d9c: f000 fd05 bl 80097aa return USBD_OK; 8008da0: 2300 movs r3, #0 } 8008da2: 4618 mov r0, r3 8008da4: 3710 adds r7, #16 8008da6: 46bd mov sp, r7 8008da8: bd80 pop {r7, pc} 08008daa : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8008daa: b580 push {r7, lr} 8008dac: b084 sub sp, #16 8008dae: af00 add r7, sp, #0 8008db0: 60f8 str r0, [r7, #12] 8008db2: 60b9 str r1, [r7, #8] 8008db4: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_OUT; 8008db6: 68fb ldr r3, [r7, #12] 8008db8: 2203 movs r2, #3 8008dba: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->ep_out[0].total_length = len; 8008dbe: 68fb ldr r3, [r7, #12] 8008dc0: 687a ldr r2, [r7, #4] 8008dc2: f8c3 2158 str.w r2, [r3, #344] ; 0x158 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_out[0].rem_length = 0U; #else pdev->ep_out[0].rem_length = len; 8008dc6: 68fb ldr r3, [r7, #12] 8008dc8: 687a ldr r2, [r7, #4] 8008dca: f8c3 215c str.w r2, [r3, #348] ; 0x15c #endif /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 8008dce: 687b ldr r3, [r7, #4] 8008dd0: 68ba ldr r2, [r7, #8] 8008dd2: 2100 movs r1, #0 8008dd4: 68f8 ldr r0, [r7, #12] 8008dd6: f000 fd09 bl 80097ec return USBD_OK; 8008dda: 2300 movs r3, #0 } 8008ddc: 4618 mov r0, r3 8008dde: 3710 adds r7, #16 8008de0: 46bd mov sp, r7 8008de2: bd80 pop {r7, pc} 08008de4 : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8008de4: b580 push {r7, lr} 8008de6: b084 sub sp, #16 8008de8: af00 add r7, sp, #0 8008dea: 60f8 str r0, [r7, #12] 8008dec: 60b9 str r1, [r7, #8] 8008dee: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 8008df0: 687b ldr r3, [r7, #4] 8008df2: 68ba ldr r2, [r7, #8] 8008df4: 2100 movs r1, #0 8008df6: 68f8 ldr r0, [r7, #12] 8008df8: f000 fcf8 bl 80097ec return USBD_OK; 8008dfc: 2300 movs r3, #0 } 8008dfe: 4618 mov r0, r3 8008e00: 3710 adds r7, #16 8008e02: 46bd mov sp, r7 8008e04: bd80 pop {r7, pc} 08008e06 : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 8008e06: b580 push {r7, lr} 8008e08: b082 sub sp, #8 8008e0a: af00 add r7, sp, #0 8008e0c: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 8008e0e: 687b ldr r3, [r7, #4] 8008e10: 2204 movs r2, #4 8008e12: f8c3 2294 str.w r2, [r3, #660] ; 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 8008e16: 2300 movs r3, #0 8008e18: 2200 movs r2, #0 8008e1a: 2100 movs r1, #0 8008e1c: 6878 ldr r0, [r7, #4] 8008e1e: f000 fcc4 bl 80097aa return USBD_OK; 8008e22: 2300 movs r3, #0 } 8008e24: 4618 mov r0, r3 8008e26: 3708 adds r7, #8 8008e28: 46bd mov sp, r7 8008e2a: bd80 pop {r7, pc} 08008e2c : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 8008e2c: b580 push {r7, lr} 8008e2e: b082 sub sp, #8 8008e30: af00 add r7, sp, #0 8008e32: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 8008e34: 687b ldr r3, [r7, #4] 8008e36: 2205 movs r2, #5 8008e38: f8c3 2294 str.w r2, [r3, #660] ; 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008e3c: 2300 movs r3, #0 8008e3e: 2200 movs r2, #0 8008e40: 2100 movs r1, #0 8008e42: 6878 ldr r0, [r7, #4] 8008e44: f000 fcd2 bl 80097ec return USBD_OK; 8008e48: 2300 movs r3, #0 } 8008e4a: 4618 mov r0, r3 8008e4c: 3708 adds r7, #8 8008e4e: 46bd mov sp, r7 8008e50: bd80 pop {r7, pc} ... 08008e54 : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 8008e54: b580 push {r7, lr} 8008e56: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceHS, &HS_Desc, DEVICE_HS) != USBD_OK) 8008e58: 2201 movs r2, #1 8008e5a: 4913 ldr r1, [pc, #76] ; (8008ea8 ) 8008e5c: 4813 ldr r0, [pc, #76] ; (8008eac ) 8008e5e: f7fe fe8f bl 8007b80 8008e62: 4603 mov r3, r0 8008e64: 2b00 cmp r3, #0 8008e66: d001 beq.n 8008e6c { Error_Handler(); 8008e68: f7f8 f982 bl 8001170 } if (USBD_RegisterClass(&hUsbDeviceHS, &USBD_CDC) != USBD_OK) 8008e6c: 4910 ldr r1, [pc, #64] ; (8008eb0 ) 8008e6e: 480f ldr r0, [pc, #60] ; (8008eac ) 8008e70: f7fe feb6 bl 8007be0 8008e74: 4603 mov r3, r0 8008e76: 2b00 cmp r3, #0 8008e78: d001 beq.n 8008e7e { Error_Handler(); 8008e7a: f7f8 f979 bl 8001170 } if (USBD_CDC_RegisterInterface(&hUsbDeviceHS, &USBD_Interface_fops_HS) != USBD_OK) 8008e7e: 490d ldr r1, [pc, #52] ; (8008eb4 ) 8008e80: 480a ldr r0, [pc, #40] ; (8008eac ) 8008e82: f7fe fdd7 bl 8007a34 8008e86: 4603 mov r3, r0 8008e88: 2b00 cmp r3, #0 8008e8a: d001 beq.n 8008e90 { Error_Handler(); 8008e8c: f7f8 f970 bl 8001170 } if (USBD_Start(&hUsbDeviceHS) != USBD_OK) 8008e90: 4806 ldr r0, [pc, #24] ; (8008eac ) 8008e92: f7fe fecc bl 8007c2e 8008e96: 4603 mov r3, r0 8008e98: 2b00 cmp r3, #0 8008e9a: d001 beq.n 8008ea0 { Error_Handler(); 8008e9c: f7f8 f968 bl 8001170 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ HAL_PWREx_EnableUSBVoltageDetector(); 8008ea0: f7fa f8fe bl 80030a0 /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 8008ea4: bf00 nop 8008ea6: bd80 pop {r7, pc} 8008ea8: 24000134 .word 0x24000134 8008eac: 24001430 .word 0x24001430 8008eb0: 2400001c .word 0x2400001c 8008eb4: 24000120 .word 0x24000120 08008eb8 : /** * @brief Initializes the CDC media low layer over the USB HS IP * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Init_HS(void) { 8008eb8: b580 push {r7, lr} 8008eba: af00 add r7, sp, #0 /* USER CODE BEGIN 8 */ /* Set Application Buffers */ USBD_CDC_SetTxBuffer(&hUsbDeviceHS, UserTxBufferHS, 0); 8008ebc: 2200 movs r2, #0 8008ebe: 4905 ldr r1, [pc, #20] ; (8008ed4 ) 8008ec0: 4805 ldr r0, [pc, #20] ; (8008ed8 ) 8008ec2: f7fe fdcc bl 8007a5e USBD_CDC_SetRxBuffer(&hUsbDeviceHS, UserRxBufferHS); 8008ec6: 4905 ldr r1, [pc, #20] ; (8008edc ) 8008ec8: 4803 ldr r0, [pc, #12] ; (8008ed8 ) 8008eca: f7fe fde6 bl 8007a9a return (USBD_OK); 8008ece: 2300 movs r3, #0 /* USER CODE END 8 */ } 8008ed0: 4618 mov r0, r3 8008ed2: bd80 pop {r7, pc} 8008ed4: 24001f00 .word 0x24001f00 8008ed8: 24001430 .word 0x24001430 8008edc: 24001700 .word 0x24001700 08008ee0 : * @brief DeInitializes the CDC media low layer * @param None * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_DeInit_HS(void) { 8008ee0: b480 push {r7} 8008ee2: af00 add r7, sp, #0 /* USER CODE BEGIN 9 */ return (USBD_OK); 8008ee4: 2300 movs r3, #0 /* USER CODE END 9 */ } 8008ee6: 4618 mov r0, r3 8008ee8: 46bd mov sp, r7 8008eea: f85d 7b04 ldr.w r7, [sp], #4 8008eee: 4770 bx lr 08008ef0 : * @param pbuf: Buffer containing command data (request parameters) * @param length: Number of data to be sent (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Control_HS(uint8_t cmd, uint8_t* pbuf, uint16_t length) { 8008ef0: b480 push {r7} 8008ef2: b083 sub sp, #12 8008ef4: af00 add r7, sp, #0 8008ef6: 4603 mov r3, r0 8008ef8: 6039 str r1, [r7, #0] 8008efa: 71fb strb r3, [r7, #7] 8008efc: 4613 mov r3, r2 8008efe: 80bb strh r3, [r7, #4] /* USER CODE BEGIN 10 */ switch(cmd) 8008f00: 79fb ldrb r3, [r7, #7] 8008f02: 2b23 cmp r3, #35 ; 0x23 8008f04: d84a bhi.n 8008f9c 8008f06: a201 add r2, pc, #4 ; (adr r2, 8008f0c ) 8008f08: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008f0c: 08008f9d .word 0x08008f9d 8008f10: 08008f9d .word 0x08008f9d 8008f14: 08008f9d .word 0x08008f9d 8008f18: 08008f9d .word 0x08008f9d 8008f1c: 08008f9d .word 0x08008f9d 8008f20: 08008f9d .word 0x08008f9d 8008f24: 08008f9d .word 0x08008f9d 8008f28: 08008f9d .word 0x08008f9d 8008f2c: 08008f9d .word 0x08008f9d 8008f30: 08008f9d .word 0x08008f9d 8008f34: 08008f9d .word 0x08008f9d 8008f38: 08008f9d .word 0x08008f9d 8008f3c: 08008f9d .word 0x08008f9d 8008f40: 08008f9d .word 0x08008f9d 8008f44: 08008f9d .word 0x08008f9d 8008f48: 08008f9d .word 0x08008f9d 8008f4c: 08008f9d .word 0x08008f9d 8008f50: 08008f9d .word 0x08008f9d 8008f54: 08008f9d .word 0x08008f9d 8008f58: 08008f9d .word 0x08008f9d 8008f5c: 08008f9d .word 0x08008f9d 8008f60: 08008f9d .word 0x08008f9d 8008f64: 08008f9d .word 0x08008f9d 8008f68: 08008f9d .word 0x08008f9d 8008f6c: 08008f9d .word 0x08008f9d 8008f70: 08008f9d .word 0x08008f9d 8008f74: 08008f9d .word 0x08008f9d 8008f78: 08008f9d .word 0x08008f9d 8008f7c: 08008f9d .word 0x08008f9d 8008f80: 08008f9d .word 0x08008f9d 8008f84: 08008f9d .word 0x08008f9d 8008f88: 08008f9d .word 0x08008f9d 8008f8c: 08008f9d .word 0x08008f9d 8008f90: 08008f9d .word 0x08008f9d 8008f94: 08008f9d .word 0x08008f9d 8008f98: 08008f9d .word 0x08008f9d case CDC_SEND_BREAK: break; default: break; 8008f9c: bf00 nop } return (USBD_OK); 8008f9e: 2300 movs r3, #0 /* USER CODE END 10 */ } 8008fa0: 4618 mov r0, r3 8008fa2: 370c adds r7, #12 8008fa4: 46bd mov sp, r7 8008fa6: f85d 7b04 ldr.w r7, [sp], #4 8008faa: 4770 bx lr 08008fac : * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAILL */ static int8_t CDC_Receive_HS(uint8_t* Buf, uint32_t *Len) { 8008fac: b580 push {r7, lr} 8008fae: b082 sub sp, #8 8008fb0: af00 add r7, sp, #0 8008fb2: 6078 str r0, [r7, #4] 8008fb4: 6039 str r1, [r7, #0] /* USER CODE BEGIN 11 */ USBD_CDC_SetRxBuffer(&hUsbDeviceHS, &Buf[0]); 8008fb6: 6879 ldr r1, [r7, #4] 8008fb8: 4805 ldr r0, [pc, #20] ; (8008fd0 ) 8008fba: f7fe fd6e bl 8007a9a USBD_CDC_ReceivePacket(&hUsbDeviceHS); 8008fbe: 4804 ldr r0, [pc, #16] ; (8008fd0 ) 8008fc0: f7fe fdb4 bl 8007b2c return (USBD_OK); 8008fc4: 2300 movs r3, #0 /* USER CODE END 11 */ } 8008fc6: 4618 mov r0, r3 8008fc8: 3708 adds r7, #8 8008fca: 46bd mov sp, r7 8008fcc: bd80 pop {r7, pc} 8008fce: bf00 nop 8008fd0: 24001430 .word 0x24001430 08008fd4 : * @param Buf: Buffer of data to be sent * @param Len: Number of data to be sent (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY */ uint8_t CDC_Transmit_HS(uint8_t* Buf, uint16_t Len) { 8008fd4: b580 push {r7, lr} 8008fd6: b084 sub sp, #16 8008fd8: af00 add r7, sp, #0 8008fda: 6078 str r0, [r7, #4] 8008fdc: 460b mov r3, r1 8008fde: 807b strh r3, [r7, #2] uint8_t result = USBD_OK; 8008fe0: 2300 movs r3, #0 8008fe2: 73fb strb r3, [r7, #15] /* USER CODE BEGIN 12 */ USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceHS.pClassData; 8008fe4: 4b0d ldr r3, [pc, #52] ; (800901c ) 8008fe6: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8008fea: 60bb str r3, [r7, #8] if (hcdc->TxState != 0){ 8008fec: 68bb ldr r3, [r7, #8] 8008fee: f8d3 3214 ldr.w r3, [r3, #532] ; 0x214 8008ff2: 2b00 cmp r3, #0 8008ff4: d001 beq.n 8008ffa return USBD_BUSY; 8008ff6: 2301 movs r3, #1 8008ff8: e00b b.n 8009012 } USBD_CDC_SetTxBuffer(&hUsbDeviceHS, Buf, Len); 8008ffa: 887b ldrh r3, [r7, #2] 8008ffc: 461a mov r2, r3 8008ffe: 6879 ldr r1, [r7, #4] 8009000: 4806 ldr r0, [pc, #24] ; (800901c ) 8009002: f7fe fd2c bl 8007a5e result = USBD_CDC_TransmitPacket(&hUsbDeviceHS); 8009006: 4805 ldr r0, [pc, #20] ; (800901c ) 8009008: f7fe fd60 bl 8007acc 800900c: 4603 mov r3, r0 800900e: 73fb strb r3, [r7, #15] /* USER CODE END 12 */ return result; 8009010: 7bfb ldrb r3, [r7, #15] } 8009012: 4618 mov r0, r3 8009014: 3710 adds r7, #16 8009016: 46bd mov sp, r7 8009018: bd80 pop {r7, pc} 800901a: bf00 nop 800901c: 24001430 .word 0x24001430 08009020 : * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_TransmitCplt_HS(uint8_t *Buf, uint32_t *Len, uint8_t epnum) { 8009020: b480 push {r7} 8009022: b087 sub sp, #28 8009024: af00 add r7, sp, #0 8009026: 60f8 str r0, [r7, #12] 8009028: 60b9 str r1, [r7, #8] 800902a: 4613 mov r3, r2 800902c: 71fb strb r3, [r7, #7] uint8_t result = USBD_OK; 800902e: 2300 movs r3, #0 8009030: 75fb strb r3, [r7, #23] /* USER CODE BEGIN 14 */ UNUSED(Buf); UNUSED(Len); UNUSED(epnum); /* USER CODE END 14 */ return result; 8009032: f997 3017 ldrsb.w r3, [r7, #23] } 8009036: 4618 mov r0, r3 8009038: 371c adds r7, #28 800903a: 46bd mov sp, r7 800903c: f85d 7b04 ldr.w r7, [sp], #4 8009040: 4770 bx lr ... 08009044 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009044: b480 push {r7} 8009046: b083 sub sp, #12 8009048: af00 add r7, sp, #0 800904a: 4603 mov r3, r0 800904c: 6039 str r1, [r7, #0] 800904e: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_HS_DeviceDesc); 8009050: 683b ldr r3, [r7, #0] 8009052: 2212 movs r2, #18 8009054: 801a strh r2, [r3, #0] return USBD_HS_DeviceDesc; 8009056: 4b03 ldr r3, [pc, #12] ; (8009064 ) } 8009058: 4618 mov r0, r3 800905a: 370c adds r7, #12 800905c: 46bd mov sp, r7 800905e: f85d 7b04 ldr.w r7, [sp], #4 8009062: 4770 bx lr 8009064: 24000150 .word 0x24000150 08009068 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009068: b480 push {r7} 800906a: b083 sub sp, #12 800906c: af00 add r7, sp, #0 800906e: 4603 mov r3, r0 8009070: 6039 str r1, [r7, #0] 8009072: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 8009074: 683b ldr r3, [r7, #0] 8009076: 2204 movs r2, #4 8009078: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 800907a: 4b03 ldr r3, [pc, #12] ; (8009088 ) } 800907c: 4618 mov r0, r3 800907e: 370c adds r7, #12 8009080: 46bd mov sp, r7 8009082: f85d 7b04 ldr.w r7, [sp], #4 8009086: 4770 bx lr 8009088: 24000164 .word 0x24000164 0800908c : * @param speed : current device speed * @param length : pointer to data length variable * @retval pointer to descriptor buffer */ uint8_t * USBD_HS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800908c: b580 push {r7, lr} 800908e: b082 sub sp, #8 8009090: af00 add r7, sp, #0 8009092: 4603 mov r3, r0 8009094: 6039 str r1, [r7, #0] 8009096: 71fb strb r3, [r7, #7] if(speed == 0) 8009098: 79fb ldrb r3, [r7, #7] 800909a: 2b00 cmp r3, #0 800909c: d105 bne.n 80090aa { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_HS, USBD_StrDesc, length); 800909e: 683a ldr r2, [r7, #0] 80090a0: 4907 ldr r1, [pc, #28] ; (80090c0 ) 80090a2: 4808 ldr r0, [pc, #32] ; (80090c4 ) 80090a4: f7ff fdf5 bl 8008c92 80090a8: e004 b.n 80090b4 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_HS, USBD_StrDesc, length); 80090aa: 683a ldr r2, [r7, #0] 80090ac: 4904 ldr r1, [pc, #16] ; (80090c0 ) 80090ae: 4805 ldr r0, [pc, #20] ; (80090c4 ) 80090b0: f7ff fdef bl 8008c92 } return USBD_StrDesc; 80090b4: 4b02 ldr r3, [pc, #8] ; (80090c0 ) } 80090b6: 4618 mov r0, r3 80090b8: 3708 adds r7, #8 80090ba: 46bd mov sp, r7 80090bc: bd80 pop {r7, pc} 80090be: bf00 nop 80090c0: 24002700 .word 0x24002700 80090c4: 0800a8e8 .word 0x0800a8e8 080090c8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 80090c8: b580 push {r7, lr} 80090ca: b082 sub sp, #8 80090cc: af00 add r7, sp, #0 80090ce: 4603 mov r3, r0 80090d0: 6039 str r1, [r7, #0] 80090d2: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 80090d4: 683a ldr r2, [r7, #0] 80090d6: 4904 ldr r1, [pc, #16] ; (80090e8 ) 80090d8: 4804 ldr r0, [pc, #16] ; (80090ec ) 80090da: f7ff fdda bl 8008c92 return USBD_StrDesc; 80090de: 4b02 ldr r3, [pc, #8] ; (80090e8 ) } 80090e0: 4618 mov r0, r3 80090e2: 3708 adds r7, #8 80090e4: 46bd mov sp, r7 80090e6: bd80 pop {r7, pc} 80090e8: 24002700 .word 0x24002700 80090ec: 0800a900 .word 0x0800a900 080090f0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 80090f0: b580 push {r7, lr} 80090f2: b082 sub sp, #8 80090f4: af00 add r7, sp, #0 80090f6: 4603 mov r3, r0 80090f8: 6039 str r1, [r7, #0] 80090fa: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 80090fc: 683b ldr r3, [r7, #0] 80090fe: 221a movs r2, #26 8009100: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 8009102: f000 f843 bl 800918c /* USER CODE BEGIN USBD_HS_SerialStrDescriptor */ /* USER CODE END USBD_HS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 8009106: 4b02 ldr r3, [pc, #8] ; (8009110 ) } 8009108: 4618 mov r0, r3 800910a: 3708 adds r7, #8 800910c: 46bd mov sp, r7 800910e: bd80 pop {r7, pc} 8009110: 24000168 .word 0x24000168 08009114 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009114: b580 push {r7, lr} 8009116: b082 sub sp, #8 8009118: af00 add r7, sp, #0 800911a: 4603 mov r3, r0 800911c: 6039 str r1, [r7, #0] 800911e: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 8009120: 79fb ldrb r3, [r7, #7] 8009122: 2b00 cmp r3, #0 8009124: d105 bne.n 8009132 { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_HS, USBD_StrDesc, length); 8009126: 683a ldr r2, [r7, #0] 8009128: 4907 ldr r1, [pc, #28] ; (8009148 ) 800912a: 4808 ldr r0, [pc, #32] ; (800914c ) 800912c: f7ff fdb1 bl 8008c92 8009130: e004 b.n 800913c } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_HS, USBD_StrDesc, length); 8009132: 683a ldr r2, [r7, #0] 8009134: 4904 ldr r1, [pc, #16] ; (8009148 ) 8009136: 4805 ldr r0, [pc, #20] ; (800914c ) 8009138: f7ff fdab bl 8008c92 } return USBD_StrDesc; 800913c: 4b02 ldr r3, [pc, #8] ; (8009148 ) } 800913e: 4618 mov r0, r3 8009140: 3708 adds r7, #8 8009142: 46bd mov sp, r7 8009144: bd80 pop {r7, pc} 8009146: bf00 nop 8009148: 24002700 .word 0x24002700 800914c: 0800a914 .word 0x0800a914 08009150 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_HS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009150: b580 push {r7, lr} 8009152: b082 sub sp, #8 8009154: af00 add r7, sp, #0 8009156: 4603 mov r3, r0 8009158: 6039 str r1, [r7, #0] 800915a: 71fb strb r3, [r7, #7] if(speed == 0) 800915c: 79fb ldrb r3, [r7, #7] 800915e: 2b00 cmp r3, #0 8009160: d105 bne.n 800916e { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_HS, USBD_StrDesc, length); 8009162: 683a ldr r2, [r7, #0] 8009164: 4907 ldr r1, [pc, #28] ; (8009184 ) 8009166: 4808 ldr r0, [pc, #32] ; (8009188 ) 8009168: f7ff fd93 bl 8008c92 800916c: e004 b.n 8009178 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_HS, USBD_StrDesc, length); 800916e: 683a ldr r2, [r7, #0] 8009170: 4904 ldr r1, [pc, #16] ; (8009184 ) 8009172: 4805 ldr r0, [pc, #20] ; (8009188 ) 8009174: f7ff fd8d bl 8008c92 } return USBD_StrDesc; 8009178: 4b02 ldr r3, [pc, #8] ; (8009184 ) } 800917a: 4618 mov r0, r3 800917c: 3708 adds r7, #8 800917e: 46bd mov sp, r7 8009180: bd80 pop {r7, pc} 8009182: bf00 nop 8009184: 24002700 .word 0x24002700 8009188: 0800a920 .word 0x0800a920 0800918c : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 800918c: b580 push {r7, lr} 800918e: b084 sub sp, #16 8009190: af00 add r7, sp, #0 uint32_t deviceserial0, deviceserial1, deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 8009192: 4b0f ldr r3, [pc, #60] ; (80091d0 ) 8009194: 681b ldr r3, [r3, #0] 8009196: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 8009198: 4b0e ldr r3, [pc, #56] ; (80091d4 ) 800919a: 681b ldr r3, [r3, #0] 800919c: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 800919e: 4b0e ldr r3, [pc, #56] ; (80091d8 ) 80091a0: 681b ldr r3, [r3, #0] 80091a2: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 80091a4: 68fa ldr r2, [r7, #12] 80091a6: 687b ldr r3, [r7, #4] 80091a8: 4413 add r3, r2 80091aa: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 80091ac: 68fb ldr r3, [r7, #12] 80091ae: 2b00 cmp r3, #0 80091b0: d009 beq.n 80091c6 { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 80091b2: 2208 movs r2, #8 80091b4: 4909 ldr r1, [pc, #36] ; (80091dc ) 80091b6: 68f8 ldr r0, [r7, #12] 80091b8: f000 f814 bl 80091e4 IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 80091bc: 2204 movs r2, #4 80091be: 4908 ldr r1, [pc, #32] ; (80091e0 ) 80091c0: 68b8 ldr r0, [r7, #8] 80091c2: f000 f80f bl 80091e4 } } 80091c6: bf00 nop 80091c8: 3710 adds r7, #16 80091ca: 46bd mov sp, r7 80091cc: bd80 pop {r7, pc} 80091ce: bf00 nop 80091d0: 1ff1e800 .word 0x1ff1e800 80091d4: 1ff1e804 .word 0x1ff1e804 80091d8: 1ff1e808 .word 0x1ff1e808 80091dc: 2400016a .word 0x2400016a 80091e0: 2400017a .word 0x2400017a 080091e4 : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 80091e4: b480 push {r7} 80091e6: b087 sub sp, #28 80091e8: af00 add r7, sp, #0 80091ea: 60f8 str r0, [r7, #12] 80091ec: 60b9 str r1, [r7, #8] 80091ee: 4613 mov r3, r2 80091f0: 71fb strb r3, [r7, #7] uint8_t idx = 0; 80091f2: 2300 movs r3, #0 80091f4: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 80091f6: 2300 movs r3, #0 80091f8: 75fb strb r3, [r7, #23] 80091fa: e027 b.n 800924c { if (((value >> 28)) < 0xA) 80091fc: 68fb ldr r3, [r7, #12] 80091fe: 0f1b lsrs r3, r3, #28 8009200: 2b09 cmp r3, #9 8009202: d80b bhi.n 800921c { pbuf[2 * idx] = (value >> 28) + '0'; 8009204: 68fb ldr r3, [r7, #12] 8009206: 0f1b lsrs r3, r3, #28 8009208: b2da uxtb r2, r3 800920a: 7dfb ldrb r3, [r7, #23] 800920c: 005b lsls r3, r3, #1 800920e: 4619 mov r1, r3 8009210: 68bb ldr r3, [r7, #8] 8009212: 440b add r3, r1 8009214: 3230 adds r2, #48 ; 0x30 8009216: b2d2 uxtb r2, r2 8009218: 701a strb r2, [r3, #0] 800921a: e00a b.n 8009232 } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 800921c: 68fb ldr r3, [r7, #12] 800921e: 0f1b lsrs r3, r3, #28 8009220: b2da uxtb r2, r3 8009222: 7dfb ldrb r3, [r7, #23] 8009224: 005b lsls r3, r3, #1 8009226: 4619 mov r1, r3 8009228: 68bb ldr r3, [r7, #8] 800922a: 440b add r3, r1 800922c: 3237 adds r2, #55 ; 0x37 800922e: b2d2 uxtb r2, r2 8009230: 701a strb r2, [r3, #0] } value = value << 4; 8009232: 68fb ldr r3, [r7, #12] 8009234: 011b lsls r3, r3, #4 8009236: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 8009238: 7dfb ldrb r3, [r7, #23] 800923a: 005b lsls r3, r3, #1 800923c: 3301 adds r3, #1 800923e: 68ba ldr r2, [r7, #8] 8009240: 4413 add r3, r2 8009242: 2200 movs r2, #0 8009244: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 8009246: 7dfb ldrb r3, [r7, #23] 8009248: 3301 adds r3, #1 800924a: 75fb strb r3, [r7, #23] 800924c: 7dfa ldrb r2, [r7, #23] 800924e: 79fb ldrb r3, [r7, #7] 8009250: 429a cmp r2, r3 8009252: d3d3 bcc.n 80091fc } } 8009254: bf00 nop 8009256: bf00 nop 8009258: 371c adds r7, #28 800925a: 46bd mov sp, r7 800925c: f85d 7b04 ldr.w r7, [sp], #4 8009260: 4770 bx lr ... 08009264 : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 8009264: b580 push {r7, lr} 8009266: b0b6 sub sp, #216 ; 0xd8 8009268: af00 add r7, sp, #0 800926a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800926c: f107 03c4 add.w r3, r7, #196 ; 0xc4 8009270: 2200 movs r2, #0 8009272: 601a str r2, [r3, #0] 8009274: 605a str r2, [r3, #4] 8009276: 609a str r2, [r3, #8] 8009278: 60da str r2, [r3, #12] 800927a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 800927c: f107 0310 add.w r3, r7, #16 8009280: 22b4 movs r2, #180 ; 0xb4 8009282: 2100 movs r1, #0 8009284: 4618 mov r0, r3 8009286: f000 fb83 bl 8009990 if(pcdHandle->Instance==USB_OTG_HS) 800928a: 687b ldr r3, [r7, #4] 800928c: 681b ldr r3, [r3, #0] 800928e: 4a2b ldr r2, [pc, #172] ; (800933c ) 8009290: 4293 cmp r3, r2 8009292: d14e bne.n 8009332 /* USER CODE BEGIN USB_OTG_HS_MspInit 0 */ /* USER CODE END USB_OTG_HS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; 8009294: f44f 2380 mov.w r3, #262144 ; 0x40000 8009298: 613b str r3, [r7, #16] PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; 800929a: f44f 1340 mov.w r3, #3145728 ; 0x300000 800929e: f8c7 3090 str.w r3, [r7, #144] ; 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80092a2: f107 0310 add.w r3, r7, #16 80092a6: 4618 mov r0, r3 80092a8: f7fa fe16 bl 8003ed8 80092ac: 4603 mov r3, r0 80092ae: 2b00 cmp r3, #0 80092b0: d001 beq.n 80092b6 { Error_Handler(); 80092b2: f7f7 ff5d bl 8001170 } /** Enable USB Voltage detector */ HAL_PWREx_EnableUSBVoltageDetector(); 80092b6: f7f9 fef3 bl 80030a0 __HAL_RCC_GPIOA_CLK_ENABLE(); 80092ba: 4b21 ldr r3, [pc, #132] ; (8009340 ) 80092bc: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80092c0: 4a1f ldr r2, [pc, #124] ; (8009340 ) 80092c2: f043 0301 orr.w r3, r3, #1 80092c6: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 80092ca: 4b1d ldr r3, [pc, #116] ; (8009340 ) 80092cc: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 80092d0: f003 0301 and.w r3, r3, #1 80092d4: 60fb str r3, [r7, #12] 80092d6: 68fb ldr r3, [r7, #12] /**USB_OTG_HS GPIO Configuration PA10 ------> USB_OTG_HS_ID */ GPIO_InitStruct.Pin = USB_FS_ID_Pin; 80092d8: f44f 6380 mov.w r3, #1024 ; 0x400 80092dc: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80092e0: 2302 movs r3, #2 80092e2: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 GPIO_InitStruct.Pull = GPIO_NOPULL; 80092e6: 2300 movs r3, #0 80092e8: f8c7 30cc str.w r3, [r7, #204] ; 0xcc GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80092ec: 2300 movs r3, #0 80092ee: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_HS; 80092f2: 230a movs r3, #10 80092f4: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 HAL_GPIO_Init(USB_FS_ID_GPIO_Port, &GPIO_InitStruct); 80092f8: f107 03c4 add.w r3, r7, #196 ; 0xc4 80092fc: 4619 mov r1, r3 80092fe: 4811 ldr r0, [pc, #68] ; (8009344 ) 8009300: f7f8 faea bl 80018d8 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); 8009304: 4b0e ldr r3, [pc, #56] ; (8009340 ) 8009306: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 800930a: 4a0d ldr r2, [pc, #52] ; (8009340 ) 800930c: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8009310: f8c2 30d8 str.w r3, [r2, #216] ; 0xd8 8009314: 4b0a ldr r3, [pc, #40] ; (8009340 ) 8009316: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 800931a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800931e: 60bb str r3, [r7, #8] 8009320: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_HS_IRQn, 0, 0); 8009322: 2200 movs r2, #0 8009324: 2100 movs r1, #0 8009326: 204d movs r0, #77 ; 0x4d 8009328: f7f8 faa1 bl 800186e HAL_NVIC_EnableIRQ(OTG_HS_IRQn); 800932c: 204d movs r0, #77 ; 0x4d 800932e: f7f8 fab8 bl 80018a2 /* USER CODE BEGIN USB_OTG_HS_MspInit 1 */ /* USER CODE END USB_OTG_HS_MspInit 1 */ } } 8009332: bf00 nop 8009334: 37d8 adds r7, #216 ; 0xd8 8009336: 46bd mov sp, r7 8009338: bd80 pop {r7, pc} 800933a: bf00 nop 800933c: 40040000 .word 0x40040000 8009340: 58024400 .word 0x58024400 8009344: 58020000 .word 0x58020000 08009348 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009348: b580 push {r7, lr} 800934a: b082 sub sp, #8 800934c: af00 add r7, sp, #0 800934e: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 8009350: 687b ldr r3, [r7, #4] 8009352: f8d3 2404 ldr.w r2, [r3, #1028] ; 0x404 8009356: 687b ldr r3, [r7, #4] 8009358: f503 7371 add.w r3, r3, #964 ; 0x3c4 800935c: 4619 mov r1, r3 800935e: 4610 mov r0, r2 8009360: f7fe fcb0 bl 8007cc4 } 8009364: bf00 nop 8009366: 3708 adds r7, #8 8009368: 46bd mov sp, r7 800936a: bd80 pop {r7, pc} 0800936c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800936c: b580 push {r7, lr} 800936e: b082 sub sp, #8 8009370: af00 add r7, sp, #0 8009372: 6078 str r0, [r7, #4] 8009374: 460b mov r3, r1 8009376: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 8009378: 687b ldr r3, [r7, #4] 800937a: f8d3 0404 ldr.w r0, [r3, #1028] ; 0x404 800937e: 78fa ldrb r2, [r7, #3] 8009380: 6879 ldr r1, [r7, #4] 8009382: 4613 mov r3, r2 8009384: 00db lsls r3, r3, #3 8009386: 1a9b subs r3, r3, r2 8009388: 009b lsls r3, r3, #2 800938a: 440b add r3, r1 800938c: f503 7302 add.w r3, r3, #520 ; 0x208 8009390: 681a ldr r2, [r3, #0] 8009392: 78fb ldrb r3, [r7, #3] 8009394: 4619 mov r1, r3 8009396: f7fe fcea bl 8007d6e } 800939a: bf00 nop 800939c: 3708 adds r7, #8 800939e: 46bd mov sp, r7 80093a0: bd80 pop {r7, pc} 080093a2 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80093a2: b580 push {r7, lr} 80093a4: b082 sub sp, #8 80093a6: af00 add r7, sp, #0 80093a8: 6078 str r0, [r7, #4] 80093aa: 460b mov r3, r1 80093ac: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 80093ae: 687b ldr r3, [r7, #4] 80093b0: f8d3 0404 ldr.w r0, [r3, #1028] ; 0x404 80093b4: 78fa ldrb r2, [r7, #3] 80093b6: 6879 ldr r1, [r7, #4] 80093b8: 4613 mov r3, r2 80093ba: 00db lsls r3, r3, #3 80093bc: 1a9b subs r3, r3, r2 80093be: 009b lsls r3, r3, #2 80093c0: 440b add r3, r1 80093c2: 3348 adds r3, #72 ; 0x48 80093c4: 681a ldr r2, [r3, #0] 80093c6: 78fb ldrb r3, [r7, #3] 80093c8: 4619 mov r1, r3 80093ca: f7fe fd33 bl 8007e34 } 80093ce: bf00 nop 80093d0: 3708 adds r7, #8 80093d2: 46bd mov sp, r7 80093d4: bd80 pop {r7, pc} 080093d6 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80093d6: b580 push {r7, lr} 80093d8: b082 sub sp, #8 80093da: af00 add r7, sp, #0 80093dc: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 80093de: 687b ldr r3, [r7, #4] 80093e0: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 80093e4: 4618 mov r0, r3 80093e6: f7fe fe47 bl 8008078 } 80093ea: bf00 nop 80093ec: 3708 adds r7, #8 80093ee: 46bd mov sp, r7 80093f0: bd80 pop {r7, pc} 080093f2 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80093f2: b580 push {r7, lr} 80093f4: b084 sub sp, #16 80093f6: af00 add r7, sp, #0 80093f8: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 80093fa: 2301 movs r3, #1 80093fc: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 80093fe: 687b ldr r3, [r7, #4] 8009400: 68db ldr r3, [r3, #12] 8009402: 2b00 cmp r3, #0 8009404: d102 bne.n 800940c { speed = USBD_SPEED_HIGH; 8009406: 2300 movs r3, #0 8009408: 73fb strb r3, [r7, #15] 800940a: e008 b.n 800941e } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 800940c: 687b ldr r3, [r7, #4] 800940e: 68db ldr r3, [r3, #12] 8009410: 2b02 cmp r3, #2 8009412: d102 bne.n 800941a { speed = USBD_SPEED_FULL; 8009414: 2301 movs r3, #1 8009416: 73fb strb r3, [r7, #15] 8009418: e001 b.n 800941e } else { Error_Handler(); 800941a: f7f7 fea9 bl 8001170 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 800941e: 687b ldr r3, [r7, #4] 8009420: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8009424: 7bfa ldrb r2, [r7, #15] 8009426: 4611 mov r1, r2 8009428: 4618 mov r0, r3 800942a: f7fe fde7 bl 8007ffc /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 800942e: 687b ldr r3, [r7, #4] 8009430: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8009434: 4618 mov r0, r3 8009436: f7fe fd93 bl 8007f60 } 800943a: bf00 nop 800943c: 3710 adds r7, #16 800943e: 46bd mov sp, r7 8009440: bd80 pop {r7, pc} ... 08009444 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009444: b580 push {r7, lr} 8009446: b082 sub sp, #8 8009448: af00 add r7, sp, #0 800944a: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 800944c: 687b ldr r3, [r7, #4] 800944e: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8009452: 4618 mov r0, r3 8009454: f7fe fde2 bl 800801c __HAL_PCD_GATE_PHYCLOCK(hpcd); 8009458: 687b ldr r3, [r7, #4] 800945a: 681b ldr r3, [r3, #0] 800945c: f503 6360 add.w r3, r3, #3584 ; 0xe00 8009460: 681b ldr r3, [r3, #0] 8009462: 687a ldr r2, [r7, #4] 8009464: 6812 ldr r2, [r2, #0] 8009466: f502 6260 add.w r2, r2, #3584 ; 0xe00 800946a: f043 0301 orr.w r3, r3, #1 800946e: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 8009470: 687b ldr r3, [r7, #4] 8009472: 6a1b ldr r3, [r3, #32] 8009474: 2b00 cmp r3, #0 8009476: d005 beq.n 8009484 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 8009478: 4b04 ldr r3, [pc, #16] ; (800948c ) 800947a: 691b ldr r3, [r3, #16] 800947c: 4a03 ldr r2, [pc, #12] ; (800948c ) 800947e: f043 0306 orr.w r3, r3, #6 8009482: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 8009484: bf00 nop 8009486: 3708 adds r7, #8 8009488: 46bd mov sp, r7 800948a: bd80 pop {r7, pc} 800948c: e000ed00 .word 0xe000ed00 08009490 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009490: b580 push {r7, lr} 8009492: b082 sub sp, #8 8009494: af00 add r7, sp, #0 8009496: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 8009498: 687b ldr r3, [r7, #4] 800949a: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 800949e: 4618 mov r0, r3 80094a0: f7fe fdd2 bl 8008048 } 80094a4: bf00 nop 80094a6: 3708 adds r7, #8 80094a8: 46bd mov sp, r7 80094aa: bd80 pop {r7, pc} 080094ac : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80094ac: b580 push {r7, lr} 80094ae: b082 sub sp, #8 80094b0: af00 add r7, sp, #0 80094b2: 6078 str r0, [r7, #4] 80094b4: 460b mov r3, r1 80094b6: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 80094b8: 687b ldr r3, [r7, #4] 80094ba: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 80094be: 78fa ldrb r2, [r7, #3] 80094c0: 4611 mov r1, r2 80094c2: 4618 mov r0, r3 80094c4: f7fe fe20 bl 8008108 } 80094c8: bf00 nop 80094ca: 3708 adds r7, #8 80094cc: 46bd mov sp, r7 80094ce: bd80 pop {r7, pc} 080094d0 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80094d0: b580 push {r7, lr} 80094d2: b082 sub sp, #8 80094d4: af00 add r7, sp, #0 80094d6: 6078 str r0, [r7, #4] 80094d8: 460b mov r3, r1 80094da: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 80094dc: 687b ldr r3, [r7, #4] 80094de: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 80094e2: 78fa ldrb r2, [r7, #3] 80094e4: 4611 mov r1, r2 80094e6: 4618 mov r0, r3 80094e8: f7fe fde8 bl 80080bc } 80094ec: bf00 nop 80094ee: 3708 adds r7, #8 80094f0: 46bd mov sp, r7 80094f2: bd80 pop {r7, pc} 080094f4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80094f4: b580 push {r7, lr} 80094f6: b082 sub sp, #8 80094f8: af00 add r7, sp, #0 80094fa: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 80094fc: 687b ldr r3, [r7, #4] 80094fe: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8009502: 4618 mov r0, r3 8009504: f7fe fe26 bl 8008154 } 8009508: bf00 nop 800950a: 3708 adds r7, #8 800950c: 46bd mov sp, r7 800950e: bd80 pop {r7, pc} 08009510 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009510: b580 push {r7, lr} 8009512: b082 sub sp, #8 8009514: af00 add r7, sp, #0 8009516: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 8009518: 687b ldr r3, [r7, #4] 800951a: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 800951e: 4618 mov r0, r3 8009520: f7fe fe23 bl 800816a } 8009524: bf00 nop 8009526: 3708 adds r7, #8 8009528: 46bd mov sp, r7 800952a: bd80 pop {r7, pc} 0800952c : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 800952c: b580 push {r7, lr} 800952e: b082 sub sp, #8 8009530: af00 add r7, sp, #0 8009532: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_HS) { 8009534: 687b ldr r3, [r7, #4] 8009536: 781b ldrb r3, [r3, #0] 8009538: 2b01 cmp r3, #1 800953a: d143 bne.n 80095c4 /* Link the driver to the stack. */ hpcd_USB_OTG_HS.pData = pdev; 800953c: 4a24 ldr r2, [pc, #144] ; (80095d0 ) 800953e: 687b ldr r3, [r7, #4] 8009540: f8c2 3404 str.w r3, [r2, #1028] ; 0x404 pdev->pData = &hpcd_USB_OTG_HS; 8009544: 687b ldr r3, [r7, #4] 8009546: 4a22 ldr r2, [pc, #136] ; (80095d0 ) 8009548: f8c3 22c4 str.w r2, [r3, #708] ; 0x2c4 hpcd_USB_OTG_HS.Instance = USB_OTG_HS; 800954c: 4b20 ldr r3, [pc, #128] ; (80095d0 ) 800954e: 4a21 ldr r2, [pc, #132] ; (80095d4 ) 8009550: 601a str r2, [r3, #0] hpcd_USB_OTG_HS.Init.dev_endpoints = 9; 8009552: 4b1f ldr r3, [pc, #124] ; (80095d0 ) 8009554: 2209 movs r2, #9 8009556: 605a str r2, [r3, #4] hpcd_USB_OTG_HS.Init.speed = PCD_SPEED_FULL; 8009558: 4b1d ldr r3, [pc, #116] ; (80095d0 ) 800955a: 2202 movs r2, #2 800955c: 60da str r2, [r3, #12] hpcd_USB_OTG_HS.Init.dma_enable = DISABLE; 800955e: 4b1c ldr r3, [pc, #112] ; (80095d0 ) 8009560: 2200 movs r2, #0 8009562: 611a str r2, [r3, #16] hpcd_USB_OTG_HS.Init.phy_itface = USB_OTG_EMBEDDED_PHY; 8009564: 4b1a ldr r3, [pc, #104] ; (80095d0 ) 8009566: 2202 movs r2, #2 8009568: 619a str r2, [r3, #24] hpcd_USB_OTG_HS.Init.Sof_enable = DISABLE; 800956a: 4b19 ldr r3, [pc, #100] ; (80095d0 ) 800956c: 2200 movs r2, #0 800956e: 61da str r2, [r3, #28] hpcd_USB_OTG_HS.Init.low_power_enable = DISABLE; 8009570: 4b17 ldr r3, [pc, #92] ; (80095d0 ) 8009572: 2200 movs r2, #0 8009574: 621a str r2, [r3, #32] hpcd_USB_OTG_HS.Init.lpm_enable = DISABLE; 8009576: 4b16 ldr r3, [pc, #88] ; (80095d0 ) 8009578: 2200 movs r2, #0 800957a: 625a str r2, [r3, #36] ; 0x24 hpcd_USB_OTG_HS.Init.battery_charging_enable = ENABLE; 800957c: 4b14 ldr r3, [pc, #80] ; (80095d0 ) 800957e: 2201 movs r2, #1 8009580: 629a str r2, [r3, #40] ; 0x28 hpcd_USB_OTG_HS.Init.vbus_sensing_enable = DISABLE; 8009582: 4b13 ldr r3, [pc, #76] ; (80095d0 ) 8009584: 2200 movs r2, #0 8009586: 62da str r2, [r3, #44] ; 0x2c hpcd_USB_OTG_HS.Init.use_dedicated_ep1 = DISABLE; 8009588: 4b11 ldr r3, [pc, #68] ; (80095d0 ) 800958a: 2200 movs r2, #0 800958c: 631a str r2, [r3, #48] ; 0x30 hpcd_USB_OTG_HS.Init.use_external_vbus = DISABLE; 800958e: 4b10 ldr r3, [pc, #64] ; (80095d0 ) 8009590: 2200 movs r2, #0 8009592: 635a str r2, [r3, #52] ; 0x34 if (HAL_PCD_Init(&hpcd_USB_OTG_HS) != HAL_OK) 8009594: 480e ldr r0, [pc, #56] ; (80095d0 ) 8009596: f7f8 fb7a bl 8001c8e 800959a: 4603 mov r3, r0 800959c: 2b00 cmp r3, #0 800959e: d001 beq.n 80095a4 { Error_Handler( ); 80095a0: f7f7 fde6 bl 8001170 HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_HS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /* USER CODE BEGIN TxRx_Configuration */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_HS, 0x200); 80095a4: f44f 7100 mov.w r1, #512 ; 0x200 80095a8: 4809 ldr r0, [pc, #36] ; (80095d0 ) 80095aa: f7f9 fcfe bl 8002faa HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x80); 80095ae: 2280 movs r2, #128 ; 0x80 80095b0: 2100 movs r1, #0 80095b2: 4807 ldr r0, [pc, #28] ; (80095d0 ) 80095b4: f7f9 fcb2 bl 8002f1c HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x174); 80095b8: f44f 72ba mov.w r2, #372 ; 0x174 80095bc: 2101 movs r1, #1 80095be: 4804 ldr r0, [pc, #16] ; (80095d0 ) 80095c0: f7f9 fcac bl 8002f1c /* USER CODE END TxRx_Configuration */ } return USBD_OK; 80095c4: 2300 movs r3, #0 } 80095c6: 4618 mov r0, r3 80095c8: 3708 adds r7, #8 80095ca: 46bd mov sp, r7 80095cc: bd80 pop {r7, pc} 80095ce: bf00 nop 80095d0: 24002900 .word 0x24002900 80095d4: 40040000 .word 0x40040000 080095d8 : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 80095d8: b580 push {r7, lr} 80095da: b084 sub sp, #16 80095dc: af00 add r7, sp, #0 80095de: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 80095e0: 2300 movs r3, #0 80095e2: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 80095e4: 2300 movs r3, #0 80095e6: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 80095e8: 687b ldr r3, [r7, #4] 80095ea: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 80095ee: 4618 mov r0, r3 80095f0: f7f8 fc71 bl 8001ed6 80095f4: 4603 mov r3, r0 80095f6: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 80095f8: 7bfb ldrb r3, [r7, #15] 80095fa: 4618 mov r0, r3 80095fc: f000 f942 bl 8009884 8009600: 4603 mov r3, r0 8009602: 73bb strb r3, [r7, #14] return usb_status; 8009604: 7bbb ldrb r3, [r7, #14] } 8009606: 4618 mov r0, r3 8009608: 3710 adds r7, #16 800960a: 46bd mov sp, r7 800960c: bd80 pop {r7, pc} 0800960e : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 800960e: b580 push {r7, lr} 8009610: b084 sub sp, #16 8009612: af00 add r7, sp, #0 8009614: 6078 str r0, [r7, #4] 8009616: 4608 mov r0, r1 8009618: 4611 mov r1, r2 800961a: 461a mov r2, r3 800961c: 4603 mov r3, r0 800961e: 70fb strb r3, [r7, #3] 8009620: 460b mov r3, r1 8009622: 70bb strb r3, [r7, #2] 8009624: 4613 mov r3, r2 8009626: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 8009628: 2300 movs r3, #0 800962a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800962c: 2300 movs r3, #0 800962e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 8009630: 687b ldr r3, [r7, #4] 8009632: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4 8009636: 78bb ldrb r3, [r7, #2] 8009638: 883a ldrh r2, [r7, #0] 800963a: 78f9 ldrb r1, [r7, #3] 800963c: f7f9 f876 bl 800272c 8009640: 4603 mov r3, r0 8009642: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8009644: 7bfb ldrb r3, [r7, #15] 8009646: 4618 mov r0, r3 8009648: f000 f91c bl 8009884 800964c: 4603 mov r3, r0 800964e: 73bb strb r3, [r7, #14] return usb_status; 8009650: 7bbb ldrb r3, [r7, #14] } 8009652: 4618 mov r0, r3 8009654: 3710 adds r7, #16 8009656: 46bd mov sp, r7 8009658: bd80 pop {r7, pc} 0800965a : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800965a: b580 push {r7, lr} 800965c: b084 sub sp, #16 800965e: af00 add r7, sp, #0 8009660: 6078 str r0, [r7, #4] 8009662: 460b mov r3, r1 8009664: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 8009666: 2300 movs r3, #0 8009668: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800966a: 2300 movs r3, #0 800966c: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 800966e: 687b ldr r3, [r7, #4] 8009670: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8009674: 78fa ldrb r2, [r7, #3] 8009676: 4611 mov r1, r2 8009678: 4618 mov r0, r3 800967a: f7f9 f8bf bl 80027fc 800967e: 4603 mov r3, r0 8009680: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8009682: 7bfb ldrb r3, [r7, #15] 8009684: 4618 mov r0, r3 8009686: f000 f8fd bl 8009884 800968a: 4603 mov r3, r0 800968c: 73bb strb r3, [r7, #14] return usb_status; 800968e: 7bbb ldrb r3, [r7, #14] } 8009690: 4618 mov r0, r3 8009692: 3710 adds r7, #16 8009694: 46bd mov sp, r7 8009696: bd80 pop {r7, pc} 08009698 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 8009698: b580 push {r7, lr} 800969a: b084 sub sp, #16 800969c: af00 add r7, sp, #0 800969e: 6078 str r0, [r7, #4] 80096a0: 460b mov r3, r1 80096a2: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 80096a4: 2300 movs r3, #0 80096a6: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 80096a8: 2300 movs r3, #0 80096aa: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 80096ac: 687b ldr r3, [r7, #4] 80096ae: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 80096b2: 78fa ldrb r2, [r7, #3] 80096b4: 4611 mov r1, r2 80096b6: 4618 mov r0, r3 80096b8: f7f9 f997 bl 80029ea 80096bc: 4603 mov r3, r0 80096be: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 80096c0: 7bfb ldrb r3, [r7, #15] 80096c2: 4618 mov r0, r3 80096c4: f000 f8de bl 8009884 80096c8: 4603 mov r3, r0 80096ca: 73bb strb r3, [r7, #14] return usb_status; 80096cc: 7bbb ldrb r3, [r7, #14] } 80096ce: 4618 mov r0, r3 80096d0: 3710 adds r7, #16 80096d2: 46bd mov sp, r7 80096d4: bd80 pop {r7, pc} 080096d6 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 80096d6: b580 push {r7, lr} 80096d8: b084 sub sp, #16 80096da: af00 add r7, sp, #0 80096dc: 6078 str r0, [r7, #4] 80096de: 460b mov r3, r1 80096e0: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 80096e2: 2300 movs r3, #0 80096e4: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 80096e6: 2300 movs r3, #0 80096e8: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 80096ea: 687b ldr r3, [r7, #4] 80096ec: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 80096f0: 78fa ldrb r2, [r7, #3] 80096f2: 4611 mov r1, r2 80096f4: 4618 mov r0, r3 80096f6: f7f9 f9dc bl 8002ab2 80096fa: 4603 mov r3, r0 80096fc: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 80096fe: 7bfb ldrb r3, [r7, #15] 8009700: 4618 mov r0, r3 8009702: f000 f8bf bl 8009884 8009706: 4603 mov r3, r0 8009708: 73bb strb r3, [r7, #14] return usb_status; 800970a: 7bbb ldrb r3, [r7, #14] } 800970c: 4618 mov r0, r3 800970e: 3710 adds r7, #16 8009710: 46bd mov sp, r7 8009712: bd80 pop {r7, pc} 08009714 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 8009714: b480 push {r7} 8009716: b085 sub sp, #20 8009718: af00 add r7, sp, #0 800971a: 6078 str r0, [r7, #4] 800971c: 460b mov r3, r1 800971e: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 8009720: 687b ldr r3, [r7, #4] 8009722: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8009726: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 8009728: f997 3003 ldrsb.w r3, [r7, #3] 800972c: 2b00 cmp r3, #0 800972e: da0b bge.n 8009748 { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 8009730: 78fb ldrb r3, [r7, #3] 8009732: f003 027f and.w r2, r3, #127 ; 0x7f 8009736: 68f9 ldr r1, [r7, #12] 8009738: 4613 mov r3, r2 800973a: 00db lsls r3, r3, #3 800973c: 1a9b subs r3, r3, r2 800973e: 009b lsls r3, r3, #2 8009740: 440b add r3, r1 8009742: 333e adds r3, #62 ; 0x3e 8009744: 781b ldrb r3, [r3, #0] 8009746: e00b b.n 8009760 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 8009748: 78fb ldrb r3, [r7, #3] 800974a: f003 027f and.w r2, r3, #127 ; 0x7f 800974e: 68f9 ldr r1, [r7, #12] 8009750: 4613 mov r3, r2 8009752: 00db lsls r3, r3, #3 8009754: 1a9b subs r3, r3, r2 8009756: 009b lsls r3, r3, #2 8009758: 440b add r3, r1 800975a: f503 73ff add.w r3, r3, #510 ; 0x1fe 800975e: 781b ldrb r3, [r3, #0] } } 8009760: 4618 mov r0, r3 8009762: 3714 adds r7, #20 8009764: 46bd mov sp, r7 8009766: f85d 7b04 ldr.w r7, [sp], #4 800976a: 4770 bx lr 0800976c : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 800976c: b580 push {r7, lr} 800976e: b084 sub sp, #16 8009770: af00 add r7, sp, #0 8009772: 6078 str r0, [r7, #4] 8009774: 460b mov r3, r1 8009776: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 8009778: 2300 movs r3, #0 800977a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800977c: 2300 movs r3, #0 800977e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 8009780: 687b ldr r3, [r7, #4] 8009782: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8009786: 78fa ldrb r2, [r7, #3] 8009788: 4611 mov r1, r2 800978a: 4618 mov r0, r3 800978c: f7f8 ffa9 bl 80026e2 8009790: 4603 mov r3, r0 8009792: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8009794: 7bfb ldrb r3, [r7, #15] 8009796: 4618 mov r0, r3 8009798: f000 f874 bl 8009884 800979c: 4603 mov r3, r0 800979e: 73bb strb r3, [r7, #14] return usb_status; 80097a0: 7bbb ldrb r3, [r7, #14] } 80097a2: 4618 mov r0, r3 80097a4: 3710 adds r7, #16 80097a6: 46bd mov sp, r7 80097a8: bd80 pop {r7, pc} 080097aa : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 80097aa: b580 push {r7, lr} 80097ac: b086 sub sp, #24 80097ae: af00 add r7, sp, #0 80097b0: 60f8 str r0, [r7, #12] 80097b2: 607a str r2, [r7, #4] 80097b4: 603b str r3, [r7, #0] 80097b6: 460b mov r3, r1 80097b8: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 80097ba: 2300 movs r3, #0 80097bc: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 80097be: 2300 movs r3, #0 80097c0: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 80097c2: 68fb ldr r3, [r7, #12] 80097c4: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4 80097c8: 7af9 ldrb r1, [r7, #11] 80097ca: 683b ldr r3, [r7, #0] 80097cc: 687a ldr r2, [r7, #4] 80097ce: f7f9 f8c2 bl 8002956 80097d2: 4603 mov r3, r0 80097d4: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 80097d6: 7dfb ldrb r3, [r7, #23] 80097d8: 4618 mov r0, r3 80097da: f000 f853 bl 8009884 80097de: 4603 mov r3, r0 80097e0: 75bb strb r3, [r7, #22] return usb_status; 80097e2: 7dbb ldrb r3, [r7, #22] } 80097e4: 4618 mov r0, r3 80097e6: 3718 adds r7, #24 80097e8: 46bd mov sp, r7 80097ea: bd80 pop {r7, pc} 080097ec : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 80097ec: b580 push {r7, lr} 80097ee: b086 sub sp, #24 80097f0: af00 add r7, sp, #0 80097f2: 60f8 str r0, [r7, #12] 80097f4: 607a str r2, [r7, #4] 80097f6: 603b str r3, [r7, #0] 80097f8: 460b mov r3, r1 80097fa: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 80097fc: 2300 movs r3, #0 80097fe: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 8009800: 2300 movs r3, #0 8009802: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 8009804: 68fb ldr r3, [r7, #12] 8009806: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4 800980a: 7af9 ldrb r1, [r7, #11] 800980c: 683b ldr r3, [r7, #0] 800980e: 687a ldr r2, [r7, #4] 8009810: f7f9 f83e bl 8002890 8009814: 4603 mov r3, r0 8009816: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 8009818: 7dfb ldrb r3, [r7, #23] 800981a: 4618 mov r0, r3 800981c: f000 f832 bl 8009884 8009820: 4603 mov r3, r0 8009822: 75bb strb r3, [r7, #22] return usb_status; 8009824: 7dbb ldrb r3, [r7, #22] } 8009826: 4618 mov r0, r3 8009828: 3718 adds r7, #24 800982a: 46bd mov sp, r7 800982c: bd80 pop {r7, pc} 0800982e : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Received Data Size */ uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800982e: b580 push {r7, lr} 8009830: b082 sub sp, #8 8009832: af00 add r7, sp, #0 8009834: 6078 str r0, [r7, #4] 8009836: 460b mov r3, r1 8009838: 70fb strb r3, [r7, #3] return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); 800983a: 687b ldr r3, [r7, #4] 800983c: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8009840: 78fa ldrb r2, [r7, #3] 8009842: 4611 mov r1, r2 8009844: 4618 mov r0, r3 8009846: f7f9 f86e bl 8002926 800984a: 4603 mov r3, r0 } 800984c: 4618 mov r0, r3 800984e: 3708 adds r7, #8 8009850: 46bd mov sp, r7 8009852: bd80 pop {r7, pc} 08009854 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 8009854: b480 push {r7} 8009856: b083 sub sp, #12 8009858: af00 add r7, sp, #0 800985a: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 800985c: 4b03 ldr r3, [pc, #12] ; (800986c ) } 800985e: 4618 mov r0, r3 8009860: 370c adds r7, #12 8009862: 46bd mov sp, r7 8009864: f85d 7b04 ldr.w r7, [sp], #4 8009868: 4770 bx lr 800986a: bf00 nop 800986c: 240011b8 .word 0x240011b8 08009870 : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 8009870: b480 push {r7} 8009872: b083 sub sp, #12 8009874: af00 add r7, sp, #0 8009876: 6078 str r0, [r7, #4] } 8009878: bf00 nop 800987a: 370c adds r7, #12 800987c: 46bd mov sp, r7 800987e: f85d 7b04 ldr.w r7, [sp], #4 8009882: 4770 bx lr 08009884 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 8009884: b480 push {r7} 8009886: b085 sub sp, #20 8009888: af00 add r7, sp, #0 800988a: 4603 mov r3, r0 800988c: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 800988e: 2300 movs r3, #0 8009890: 73fb strb r3, [r7, #15] switch (hal_status) 8009892: 79fb ldrb r3, [r7, #7] 8009894: 2b03 cmp r3, #3 8009896: d817 bhi.n 80098c8 8009898: a201 add r2, pc, #4 ; (adr r2, 80098a0 ) 800989a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800989e: bf00 nop 80098a0: 080098b1 .word 0x080098b1 80098a4: 080098b7 .word 0x080098b7 80098a8: 080098bd .word 0x080098bd 80098ac: 080098c3 .word 0x080098c3 { case HAL_OK : usb_status = USBD_OK; 80098b0: 2300 movs r3, #0 80098b2: 73fb strb r3, [r7, #15] break; 80098b4: e00b b.n 80098ce case HAL_ERROR : usb_status = USBD_FAIL; 80098b6: 2303 movs r3, #3 80098b8: 73fb strb r3, [r7, #15] break; 80098ba: e008 b.n 80098ce case HAL_BUSY : usb_status = USBD_BUSY; 80098bc: 2301 movs r3, #1 80098be: 73fb strb r3, [r7, #15] break; 80098c0: e005 b.n 80098ce case HAL_TIMEOUT : usb_status = USBD_FAIL; 80098c2: 2303 movs r3, #3 80098c4: 73fb strb r3, [r7, #15] break; 80098c6: e002 b.n 80098ce default : usb_status = USBD_FAIL; 80098c8: 2303 movs r3, #3 80098ca: 73fb strb r3, [r7, #15] break; 80098cc: bf00 nop } return usb_status; 80098ce: 7bfb ldrb r3, [r7, #15] } 80098d0: 4618 mov r0, r3 80098d2: 3714 adds r7, #20 80098d4: 46bd mov sp, r7 80098d6: f85d 7b04 ldr.w r7, [sp], #4 80098da: 4770 bx lr 080098dc <__assert_func>: 80098dc: b51f push {r0, r1, r2, r3, r4, lr} 80098de: 4614 mov r4, r2 80098e0: 461a mov r2, r3 80098e2: 4b09 ldr r3, [pc, #36] ; (8009908 <__assert_func+0x2c>) 80098e4: 681b ldr r3, [r3, #0] 80098e6: 4605 mov r5, r0 80098e8: 68d8 ldr r0, [r3, #12] 80098ea: b14c cbz r4, 8009900 <__assert_func+0x24> 80098ec: 4b07 ldr r3, [pc, #28] ; (800990c <__assert_func+0x30>) 80098ee: 9100 str r1, [sp, #0] 80098f0: e9cd 3401 strd r3, r4, [sp, #4] 80098f4: 4906 ldr r1, [pc, #24] ; (8009910 <__assert_func+0x34>) 80098f6: 462b mov r3, r5 80098f8: f000 f814 bl 8009924 80098fc: f000 fbfe bl 800a0fc 8009900: 4b04 ldr r3, [pc, #16] ; (8009914 <__assert_func+0x38>) 8009902: 461c mov r4, r3 8009904: e7f3 b.n 80098ee <__assert_func+0x12> 8009906: bf00 nop 8009908: 24000184 .word 0x24000184 800990c: 0800aa20 .word 0x0800aa20 8009910: 0800aa2d .word 0x0800aa2d 8009914: 0800aa5b .word 0x0800aa5b 08009918 <__errno>: 8009918: 4b01 ldr r3, [pc, #4] ; (8009920 <__errno+0x8>) 800991a: 6818 ldr r0, [r3, #0] 800991c: 4770 bx lr 800991e: bf00 nop 8009920: 24000184 .word 0x24000184 08009924 : 8009924: b40e push {r1, r2, r3} 8009926: b503 push {r0, r1, lr} 8009928: 4601 mov r1, r0 800992a: ab03 add r3, sp, #12 800992c: 4805 ldr r0, [pc, #20] ; (8009944 ) 800992e: f853 2b04 ldr.w r2, [r3], #4 8009932: 6800 ldr r0, [r0, #0] 8009934: 9301 str r3, [sp, #4] 8009936: f000 f85d bl 80099f4 <_vfiprintf_r> 800993a: b002 add sp, #8 800993c: f85d eb04 ldr.w lr, [sp], #4 8009940: b003 add sp, #12 8009942: 4770 bx lr 8009944: 24000184 .word 0x24000184 08009948 <__libc_init_array>: 8009948: b570 push {r4, r5, r6, lr} 800994a: 4d0d ldr r5, [pc, #52] ; (8009980 <__libc_init_array+0x38>) 800994c: 4c0d ldr r4, [pc, #52] ; (8009984 <__libc_init_array+0x3c>) 800994e: 1b64 subs r4, r4, r5 8009950: 10a4 asrs r4, r4, #2 8009952: 2600 movs r6, #0 8009954: 42a6 cmp r6, r4 8009956: d109 bne.n 800996c <__libc_init_array+0x24> 8009958: 4d0b ldr r5, [pc, #44] ; (8009988 <__libc_init_array+0x40>) 800995a: 4c0c ldr r4, [pc, #48] ; (800998c <__libc_init_array+0x44>) 800995c: f000 ffaa bl 800a8b4 <_init> 8009960: 1b64 subs r4, r4, r5 8009962: 10a4 asrs r4, r4, #2 8009964: 2600 movs r6, #0 8009966: 42a6 cmp r6, r4 8009968: d105 bne.n 8009976 <__libc_init_array+0x2e> 800996a: bd70 pop {r4, r5, r6, pc} 800996c: f855 3b04 ldr.w r3, [r5], #4 8009970: 4798 blx r3 8009972: 3601 adds r6, #1 8009974: e7ee b.n 8009954 <__libc_init_array+0xc> 8009976: f855 3b04 ldr.w r3, [r5], #4 800997a: 4798 blx r3 800997c: 3601 adds r6, #1 800997e: e7f2 b.n 8009966 <__libc_init_array+0x1e> 8009980: 0800aaf4 .word 0x0800aaf4 8009984: 0800aaf4 .word 0x0800aaf4 8009988: 0800aaf4 .word 0x0800aaf4 800998c: 0800aaf8 .word 0x0800aaf8 08009990 : 8009990: 4402 add r2, r0 8009992: 4603 mov r3, r0 8009994: 4293 cmp r3, r2 8009996: d100 bne.n 800999a 8009998: 4770 bx lr 800999a: f803 1b01 strb.w r1, [r3], #1 800999e: e7f9 b.n 8009994 080099a0 <__sfputc_r>: 80099a0: 6893 ldr r3, [r2, #8] 80099a2: 3b01 subs r3, #1 80099a4: 2b00 cmp r3, #0 80099a6: b410 push {r4} 80099a8: 6093 str r3, [r2, #8] 80099aa: da08 bge.n 80099be <__sfputc_r+0x1e> 80099ac: 6994 ldr r4, [r2, #24] 80099ae: 42a3 cmp r3, r4 80099b0: db01 blt.n 80099b6 <__sfputc_r+0x16> 80099b2: 290a cmp r1, #10 80099b4: d103 bne.n 80099be <__sfputc_r+0x1e> 80099b6: f85d 4b04 ldr.w r4, [sp], #4 80099ba: f000 badf b.w 8009f7c <__swbuf_r> 80099be: 6813 ldr r3, [r2, #0] 80099c0: 1c58 adds r0, r3, #1 80099c2: 6010 str r0, [r2, #0] 80099c4: 7019 strb r1, [r3, #0] 80099c6: 4608 mov r0, r1 80099c8: f85d 4b04 ldr.w r4, [sp], #4 80099cc: 4770 bx lr 080099ce <__sfputs_r>: 80099ce: b5f8 push {r3, r4, r5, r6, r7, lr} 80099d0: 4606 mov r6, r0 80099d2: 460f mov r7, r1 80099d4: 4614 mov r4, r2 80099d6: 18d5 adds r5, r2, r3 80099d8: 42ac cmp r4, r5 80099da: d101 bne.n 80099e0 <__sfputs_r+0x12> 80099dc: 2000 movs r0, #0 80099de: e007 b.n 80099f0 <__sfputs_r+0x22> 80099e0: f814 1b01 ldrb.w r1, [r4], #1 80099e4: 463a mov r2, r7 80099e6: 4630 mov r0, r6 80099e8: f7ff ffda bl 80099a0 <__sfputc_r> 80099ec: 1c43 adds r3, r0, #1 80099ee: d1f3 bne.n 80099d8 <__sfputs_r+0xa> 80099f0: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 080099f4 <_vfiprintf_r>: 80099f4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80099f8: 460d mov r5, r1 80099fa: b09d sub sp, #116 ; 0x74 80099fc: 4614 mov r4, r2 80099fe: 4698 mov r8, r3 8009a00: 4606 mov r6, r0 8009a02: b118 cbz r0, 8009a0c <_vfiprintf_r+0x18> 8009a04: 6983 ldr r3, [r0, #24] 8009a06: b90b cbnz r3, 8009a0c <_vfiprintf_r+0x18> 8009a08: f000 fc9a bl 800a340 <__sinit> 8009a0c: 4b89 ldr r3, [pc, #548] ; (8009c34 <_vfiprintf_r+0x240>) 8009a0e: 429d cmp r5, r3 8009a10: d11b bne.n 8009a4a <_vfiprintf_r+0x56> 8009a12: 6875 ldr r5, [r6, #4] 8009a14: 6e6b ldr r3, [r5, #100] ; 0x64 8009a16: 07d9 lsls r1, r3, #31 8009a18: d405 bmi.n 8009a26 <_vfiprintf_r+0x32> 8009a1a: 89ab ldrh r3, [r5, #12] 8009a1c: 059a lsls r2, r3, #22 8009a1e: d402 bmi.n 8009a26 <_vfiprintf_r+0x32> 8009a20: 6da8 ldr r0, [r5, #88] ; 0x58 8009a22: f000 fd2b bl 800a47c <__retarget_lock_acquire_recursive> 8009a26: 89ab ldrh r3, [r5, #12] 8009a28: 071b lsls r3, r3, #28 8009a2a: d501 bpl.n 8009a30 <_vfiprintf_r+0x3c> 8009a2c: 692b ldr r3, [r5, #16] 8009a2e: b9eb cbnz r3, 8009a6c <_vfiprintf_r+0x78> 8009a30: 4629 mov r1, r5 8009a32: 4630 mov r0, r6 8009a34: f000 faf4 bl 800a020 <__swsetup_r> 8009a38: b1c0 cbz r0, 8009a6c <_vfiprintf_r+0x78> 8009a3a: 6e6b ldr r3, [r5, #100] ; 0x64 8009a3c: 07dc lsls r4, r3, #31 8009a3e: d50e bpl.n 8009a5e <_vfiprintf_r+0x6a> 8009a40: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8009a44: b01d add sp, #116 ; 0x74 8009a46: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8009a4a: 4b7b ldr r3, [pc, #492] ; (8009c38 <_vfiprintf_r+0x244>) 8009a4c: 429d cmp r5, r3 8009a4e: d101 bne.n 8009a54 <_vfiprintf_r+0x60> 8009a50: 68b5 ldr r5, [r6, #8] 8009a52: e7df b.n 8009a14 <_vfiprintf_r+0x20> 8009a54: 4b79 ldr r3, [pc, #484] ; (8009c3c <_vfiprintf_r+0x248>) 8009a56: 429d cmp r5, r3 8009a58: bf08 it eq 8009a5a: 68f5 ldreq r5, [r6, #12] 8009a5c: e7da b.n 8009a14 <_vfiprintf_r+0x20> 8009a5e: 89ab ldrh r3, [r5, #12] 8009a60: 0598 lsls r0, r3, #22 8009a62: d4ed bmi.n 8009a40 <_vfiprintf_r+0x4c> 8009a64: 6da8 ldr r0, [r5, #88] ; 0x58 8009a66: f000 fd0a bl 800a47e <__retarget_lock_release_recursive> 8009a6a: e7e9 b.n 8009a40 <_vfiprintf_r+0x4c> 8009a6c: 2300 movs r3, #0 8009a6e: 9309 str r3, [sp, #36] ; 0x24 8009a70: 2320 movs r3, #32 8009a72: f88d 3029 strb.w r3, [sp, #41] ; 0x29 8009a76: f8cd 800c str.w r8, [sp, #12] 8009a7a: 2330 movs r3, #48 ; 0x30 8009a7c: f8df 81c0 ldr.w r8, [pc, #448] ; 8009c40 <_vfiprintf_r+0x24c> 8009a80: f88d 302a strb.w r3, [sp, #42] ; 0x2a 8009a84: f04f 0901 mov.w r9, #1 8009a88: 4623 mov r3, r4 8009a8a: 469a mov sl, r3 8009a8c: f813 2b01 ldrb.w r2, [r3], #1 8009a90: b10a cbz r2, 8009a96 <_vfiprintf_r+0xa2> 8009a92: 2a25 cmp r2, #37 ; 0x25 8009a94: d1f9 bne.n 8009a8a <_vfiprintf_r+0x96> 8009a96: ebba 0b04 subs.w fp, sl, r4 8009a9a: d00b beq.n 8009ab4 <_vfiprintf_r+0xc0> 8009a9c: 465b mov r3, fp 8009a9e: 4622 mov r2, r4 8009aa0: 4629 mov r1, r5 8009aa2: 4630 mov r0, r6 8009aa4: f7ff ff93 bl 80099ce <__sfputs_r> 8009aa8: 3001 adds r0, #1 8009aaa: f000 80aa beq.w 8009c02 <_vfiprintf_r+0x20e> 8009aae: 9a09 ldr r2, [sp, #36] ; 0x24 8009ab0: 445a add r2, fp 8009ab2: 9209 str r2, [sp, #36] ; 0x24 8009ab4: f89a 3000 ldrb.w r3, [sl] 8009ab8: 2b00 cmp r3, #0 8009aba: f000 80a2 beq.w 8009c02 <_vfiprintf_r+0x20e> 8009abe: 2300 movs r3, #0 8009ac0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8009ac4: e9cd 2305 strd r2, r3, [sp, #20] 8009ac8: f10a 0a01 add.w sl, sl, #1 8009acc: 9304 str r3, [sp, #16] 8009ace: 9307 str r3, [sp, #28] 8009ad0: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8009ad4: 931a str r3, [sp, #104] ; 0x68 8009ad6: 4654 mov r4, sl 8009ad8: 2205 movs r2, #5 8009ada: f814 1b01 ldrb.w r1, [r4], #1 8009ade: 4858 ldr r0, [pc, #352] ; (8009c40 <_vfiprintf_r+0x24c>) 8009ae0: f7f6 fc16 bl 8000310 8009ae4: 9a04 ldr r2, [sp, #16] 8009ae6: b9d8 cbnz r0, 8009b20 <_vfiprintf_r+0x12c> 8009ae8: 06d1 lsls r1, r2, #27 8009aea: bf44 itt mi 8009aec: 2320 movmi r3, #32 8009aee: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8009af2: 0713 lsls r3, r2, #28 8009af4: bf44 itt mi 8009af6: 232b movmi r3, #43 ; 0x2b 8009af8: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8009afc: f89a 3000 ldrb.w r3, [sl] 8009b00: 2b2a cmp r3, #42 ; 0x2a 8009b02: d015 beq.n 8009b30 <_vfiprintf_r+0x13c> 8009b04: 9a07 ldr r2, [sp, #28] 8009b06: 4654 mov r4, sl 8009b08: 2000 movs r0, #0 8009b0a: f04f 0c0a mov.w ip, #10 8009b0e: 4621 mov r1, r4 8009b10: f811 3b01 ldrb.w r3, [r1], #1 8009b14: 3b30 subs r3, #48 ; 0x30 8009b16: 2b09 cmp r3, #9 8009b18: d94e bls.n 8009bb8 <_vfiprintf_r+0x1c4> 8009b1a: b1b0 cbz r0, 8009b4a <_vfiprintf_r+0x156> 8009b1c: 9207 str r2, [sp, #28] 8009b1e: e014 b.n 8009b4a <_vfiprintf_r+0x156> 8009b20: eba0 0308 sub.w r3, r0, r8 8009b24: fa09 f303 lsl.w r3, r9, r3 8009b28: 4313 orrs r3, r2 8009b2a: 9304 str r3, [sp, #16] 8009b2c: 46a2 mov sl, r4 8009b2e: e7d2 b.n 8009ad6 <_vfiprintf_r+0xe2> 8009b30: 9b03 ldr r3, [sp, #12] 8009b32: 1d19 adds r1, r3, #4 8009b34: 681b ldr r3, [r3, #0] 8009b36: 9103 str r1, [sp, #12] 8009b38: 2b00 cmp r3, #0 8009b3a: bfbb ittet lt 8009b3c: 425b neglt r3, r3 8009b3e: f042 0202 orrlt.w r2, r2, #2 8009b42: 9307 strge r3, [sp, #28] 8009b44: 9307 strlt r3, [sp, #28] 8009b46: bfb8 it lt 8009b48: 9204 strlt r2, [sp, #16] 8009b4a: 7823 ldrb r3, [r4, #0] 8009b4c: 2b2e cmp r3, #46 ; 0x2e 8009b4e: d10c bne.n 8009b6a <_vfiprintf_r+0x176> 8009b50: 7863 ldrb r3, [r4, #1] 8009b52: 2b2a cmp r3, #42 ; 0x2a 8009b54: d135 bne.n 8009bc2 <_vfiprintf_r+0x1ce> 8009b56: 9b03 ldr r3, [sp, #12] 8009b58: 1d1a adds r2, r3, #4 8009b5a: 681b ldr r3, [r3, #0] 8009b5c: 9203 str r2, [sp, #12] 8009b5e: 2b00 cmp r3, #0 8009b60: bfb8 it lt 8009b62: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff 8009b66: 3402 adds r4, #2 8009b68: 9305 str r3, [sp, #20] 8009b6a: f8df a0e4 ldr.w sl, [pc, #228] ; 8009c50 <_vfiprintf_r+0x25c> 8009b6e: 7821 ldrb r1, [r4, #0] 8009b70: 2203 movs r2, #3 8009b72: 4650 mov r0, sl 8009b74: f7f6 fbcc bl 8000310 8009b78: b140 cbz r0, 8009b8c <_vfiprintf_r+0x198> 8009b7a: 2340 movs r3, #64 ; 0x40 8009b7c: eba0 000a sub.w r0, r0, sl 8009b80: fa03 f000 lsl.w r0, r3, r0 8009b84: 9b04 ldr r3, [sp, #16] 8009b86: 4303 orrs r3, r0 8009b88: 3401 adds r4, #1 8009b8a: 9304 str r3, [sp, #16] 8009b8c: f814 1b01 ldrb.w r1, [r4], #1 8009b90: 482c ldr r0, [pc, #176] ; (8009c44 <_vfiprintf_r+0x250>) 8009b92: f88d 1028 strb.w r1, [sp, #40] ; 0x28 8009b96: 2206 movs r2, #6 8009b98: f7f6 fbba bl 8000310 8009b9c: 2800 cmp r0, #0 8009b9e: d03f beq.n 8009c20 <_vfiprintf_r+0x22c> 8009ba0: 4b29 ldr r3, [pc, #164] ; (8009c48 <_vfiprintf_r+0x254>) 8009ba2: bb1b cbnz r3, 8009bec <_vfiprintf_r+0x1f8> 8009ba4: 9b03 ldr r3, [sp, #12] 8009ba6: 3307 adds r3, #7 8009ba8: f023 0307 bic.w r3, r3, #7 8009bac: 3308 adds r3, #8 8009bae: 9303 str r3, [sp, #12] 8009bb0: 9b09 ldr r3, [sp, #36] ; 0x24 8009bb2: 443b add r3, r7 8009bb4: 9309 str r3, [sp, #36] ; 0x24 8009bb6: e767 b.n 8009a88 <_vfiprintf_r+0x94> 8009bb8: fb0c 3202 mla r2, ip, r2, r3 8009bbc: 460c mov r4, r1 8009bbe: 2001 movs r0, #1 8009bc0: e7a5 b.n 8009b0e <_vfiprintf_r+0x11a> 8009bc2: 2300 movs r3, #0 8009bc4: 3401 adds r4, #1 8009bc6: 9305 str r3, [sp, #20] 8009bc8: 4619 mov r1, r3 8009bca: f04f 0c0a mov.w ip, #10 8009bce: 4620 mov r0, r4 8009bd0: f810 2b01 ldrb.w r2, [r0], #1 8009bd4: 3a30 subs r2, #48 ; 0x30 8009bd6: 2a09 cmp r2, #9 8009bd8: d903 bls.n 8009be2 <_vfiprintf_r+0x1ee> 8009bda: 2b00 cmp r3, #0 8009bdc: d0c5 beq.n 8009b6a <_vfiprintf_r+0x176> 8009bde: 9105 str r1, [sp, #20] 8009be0: e7c3 b.n 8009b6a <_vfiprintf_r+0x176> 8009be2: fb0c 2101 mla r1, ip, r1, r2 8009be6: 4604 mov r4, r0 8009be8: 2301 movs r3, #1 8009bea: e7f0 b.n 8009bce <_vfiprintf_r+0x1da> 8009bec: ab03 add r3, sp, #12 8009bee: 9300 str r3, [sp, #0] 8009bf0: 462a mov r2, r5 8009bf2: 4b16 ldr r3, [pc, #88] ; (8009c4c <_vfiprintf_r+0x258>) 8009bf4: a904 add r1, sp, #16 8009bf6: 4630 mov r0, r6 8009bf8: f3af 8000 nop.w 8009bfc: 4607 mov r7, r0 8009bfe: 1c78 adds r0, r7, #1 8009c00: d1d6 bne.n 8009bb0 <_vfiprintf_r+0x1bc> 8009c02: 6e6b ldr r3, [r5, #100] ; 0x64 8009c04: 07d9 lsls r1, r3, #31 8009c06: d405 bmi.n 8009c14 <_vfiprintf_r+0x220> 8009c08: 89ab ldrh r3, [r5, #12] 8009c0a: 059a lsls r2, r3, #22 8009c0c: d402 bmi.n 8009c14 <_vfiprintf_r+0x220> 8009c0e: 6da8 ldr r0, [r5, #88] ; 0x58 8009c10: f000 fc35 bl 800a47e <__retarget_lock_release_recursive> 8009c14: 89ab ldrh r3, [r5, #12] 8009c16: 065b lsls r3, r3, #25 8009c18: f53f af12 bmi.w 8009a40 <_vfiprintf_r+0x4c> 8009c1c: 9809 ldr r0, [sp, #36] ; 0x24 8009c1e: e711 b.n 8009a44 <_vfiprintf_r+0x50> 8009c20: ab03 add r3, sp, #12 8009c22: 9300 str r3, [sp, #0] 8009c24: 462a mov r2, r5 8009c26: 4b09 ldr r3, [pc, #36] ; (8009c4c <_vfiprintf_r+0x258>) 8009c28: a904 add r1, sp, #16 8009c2a: 4630 mov r0, r6 8009c2c: f000 f880 bl 8009d30 <_printf_i> 8009c30: e7e4 b.n 8009bfc <_vfiprintf_r+0x208> 8009c32: bf00 nop 8009c34: 0800aab4 .word 0x0800aab4 8009c38: 0800aad4 .word 0x0800aad4 8009c3c: 0800aa94 .word 0x0800aa94 8009c40: 0800aa60 .word 0x0800aa60 8009c44: 0800aa6a .word 0x0800aa6a 8009c48: 00000000 .word 0x00000000 8009c4c: 080099cf .word 0x080099cf 8009c50: 0800aa66 .word 0x0800aa66 08009c54 <_printf_common>: 8009c54: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009c58: 4616 mov r6, r2 8009c5a: 4699 mov r9, r3 8009c5c: 688a ldr r2, [r1, #8] 8009c5e: 690b ldr r3, [r1, #16] 8009c60: f8dd 8020 ldr.w r8, [sp, #32] 8009c64: 4293 cmp r3, r2 8009c66: bfb8 it lt 8009c68: 4613 movlt r3, r2 8009c6a: 6033 str r3, [r6, #0] 8009c6c: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8009c70: 4607 mov r7, r0 8009c72: 460c mov r4, r1 8009c74: b10a cbz r2, 8009c7a <_printf_common+0x26> 8009c76: 3301 adds r3, #1 8009c78: 6033 str r3, [r6, #0] 8009c7a: 6823 ldr r3, [r4, #0] 8009c7c: 0699 lsls r1, r3, #26 8009c7e: bf42 ittt mi 8009c80: 6833 ldrmi r3, [r6, #0] 8009c82: 3302 addmi r3, #2 8009c84: 6033 strmi r3, [r6, #0] 8009c86: 6825 ldr r5, [r4, #0] 8009c88: f015 0506 ands.w r5, r5, #6 8009c8c: d106 bne.n 8009c9c <_printf_common+0x48> 8009c8e: f104 0a19 add.w sl, r4, #25 8009c92: 68e3 ldr r3, [r4, #12] 8009c94: 6832 ldr r2, [r6, #0] 8009c96: 1a9b subs r3, r3, r2 8009c98: 42ab cmp r3, r5 8009c9a: dc26 bgt.n 8009cea <_printf_common+0x96> 8009c9c: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 8009ca0: 1e13 subs r3, r2, #0 8009ca2: 6822 ldr r2, [r4, #0] 8009ca4: bf18 it ne 8009ca6: 2301 movne r3, #1 8009ca8: 0692 lsls r2, r2, #26 8009caa: d42b bmi.n 8009d04 <_printf_common+0xb0> 8009cac: f104 0243 add.w r2, r4, #67 ; 0x43 8009cb0: 4649 mov r1, r9 8009cb2: 4638 mov r0, r7 8009cb4: 47c0 blx r8 8009cb6: 3001 adds r0, #1 8009cb8: d01e beq.n 8009cf8 <_printf_common+0xa4> 8009cba: 6823 ldr r3, [r4, #0] 8009cbc: 68e5 ldr r5, [r4, #12] 8009cbe: 6832 ldr r2, [r6, #0] 8009cc0: f003 0306 and.w r3, r3, #6 8009cc4: 2b04 cmp r3, #4 8009cc6: bf08 it eq 8009cc8: 1aad subeq r5, r5, r2 8009cca: 68a3 ldr r3, [r4, #8] 8009ccc: 6922 ldr r2, [r4, #16] 8009cce: bf0c ite eq 8009cd0: ea25 75e5 biceq.w r5, r5, r5, asr #31 8009cd4: 2500 movne r5, #0 8009cd6: 4293 cmp r3, r2 8009cd8: bfc4 itt gt 8009cda: 1a9b subgt r3, r3, r2 8009cdc: 18ed addgt r5, r5, r3 8009cde: 2600 movs r6, #0 8009ce0: 341a adds r4, #26 8009ce2: 42b5 cmp r5, r6 8009ce4: d11a bne.n 8009d1c <_printf_common+0xc8> 8009ce6: 2000 movs r0, #0 8009ce8: e008 b.n 8009cfc <_printf_common+0xa8> 8009cea: 2301 movs r3, #1 8009cec: 4652 mov r2, sl 8009cee: 4649 mov r1, r9 8009cf0: 4638 mov r0, r7 8009cf2: 47c0 blx r8 8009cf4: 3001 adds r0, #1 8009cf6: d103 bne.n 8009d00 <_printf_common+0xac> 8009cf8: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8009cfc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8009d00: 3501 adds r5, #1 8009d02: e7c6 b.n 8009c92 <_printf_common+0x3e> 8009d04: 18e1 adds r1, r4, r3 8009d06: 1c5a adds r2, r3, #1 8009d08: 2030 movs r0, #48 ; 0x30 8009d0a: f881 0043 strb.w r0, [r1, #67] ; 0x43 8009d0e: 4422 add r2, r4 8009d10: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 8009d14: f882 1043 strb.w r1, [r2, #67] ; 0x43 8009d18: 3302 adds r3, #2 8009d1a: e7c7 b.n 8009cac <_printf_common+0x58> 8009d1c: 2301 movs r3, #1 8009d1e: 4622 mov r2, r4 8009d20: 4649 mov r1, r9 8009d22: 4638 mov r0, r7 8009d24: 47c0 blx r8 8009d26: 3001 adds r0, #1 8009d28: d0e6 beq.n 8009cf8 <_printf_common+0xa4> 8009d2a: 3601 adds r6, #1 8009d2c: e7d9 b.n 8009ce2 <_printf_common+0x8e> ... 08009d30 <_printf_i>: 8009d30: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8009d34: 460c mov r4, r1 8009d36: 4691 mov r9, r2 8009d38: 7e27 ldrb r7, [r4, #24] 8009d3a: 990c ldr r1, [sp, #48] ; 0x30 8009d3c: 2f78 cmp r7, #120 ; 0x78 8009d3e: 4680 mov r8, r0 8009d40: 469a mov sl, r3 8009d42: f104 0243 add.w r2, r4, #67 ; 0x43 8009d46: d807 bhi.n 8009d58 <_printf_i+0x28> 8009d48: 2f62 cmp r7, #98 ; 0x62 8009d4a: d80a bhi.n 8009d62 <_printf_i+0x32> 8009d4c: 2f00 cmp r7, #0 8009d4e: f000 80d8 beq.w 8009f02 <_printf_i+0x1d2> 8009d52: 2f58 cmp r7, #88 ; 0x58 8009d54: f000 80a3 beq.w 8009e9e <_printf_i+0x16e> 8009d58: f104 0642 add.w r6, r4, #66 ; 0x42 8009d5c: f884 7042 strb.w r7, [r4, #66] ; 0x42 8009d60: e03a b.n 8009dd8 <_printf_i+0xa8> 8009d62: f1a7 0363 sub.w r3, r7, #99 ; 0x63 8009d66: 2b15 cmp r3, #21 8009d68: d8f6 bhi.n 8009d58 <_printf_i+0x28> 8009d6a: a001 add r0, pc, #4 ; (adr r0, 8009d70 <_printf_i+0x40>) 8009d6c: f850 f023 ldr.w pc, [r0, r3, lsl #2] 8009d70: 08009dc9 .word 0x08009dc9 8009d74: 08009ddd .word 0x08009ddd 8009d78: 08009d59 .word 0x08009d59 8009d7c: 08009d59 .word 0x08009d59 8009d80: 08009d59 .word 0x08009d59 8009d84: 08009d59 .word 0x08009d59 8009d88: 08009ddd .word 0x08009ddd 8009d8c: 08009d59 .word 0x08009d59 8009d90: 08009d59 .word 0x08009d59 8009d94: 08009d59 .word 0x08009d59 8009d98: 08009d59 .word 0x08009d59 8009d9c: 08009ee9 .word 0x08009ee9 8009da0: 08009e0d .word 0x08009e0d 8009da4: 08009ecb .word 0x08009ecb 8009da8: 08009d59 .word 0x08009d59 8009dac: 08009d59 .word 0x08009d59 8009db0: 08009f0b .word 0x08009f0b 8009db4: 08009d59 .word 0x08009d59 8009db8: 08009e0d .word 0x08009e0d 8009dbc: 08009d59 .word 0x08009d59 8009dc0: 08009d59 .word 0x08009d59 8009dc4: 08009ed3 .word 0x08009ed3 8009dc8: 680b ldr r3, [r1, #0] 8009dca: 1d1a adds r2, r3, #4 8009dcc: 681b ldr r3, [r3, #0] 8009dce: 600a str r2, [r1, #0] 8009dd0: f104 0642 add.w r6, r4, #66 ; 0x42 8009dd4: f884 3042 strb.w r3, [r4, #66] ; 0x42 8009dd8: 2301 movs r3, #1 8009dda: e0a3 b.n 8009f24 <_printf_i+0x1f4> 8009ddc: 6825 ldr r5, [r4, #0] 8009dde: 6808 ldr r0, [r1, #0] 8009de0: 062e lsls r6, r5, #24 8009de2: f100 0304 add.w r3, r0, #4 8009de6: d50a bpl.n 8009dfe <_printf_i+0xce> 8009de8: 6805 ldr r5, [r0, #0] 8009dea: 600b str r3, [r1, #0] 8009dec: 2d00 cmp r5, #0 8009dee: da03 bge.n 8009df8 <_printf_i+0xc8> 8009df0: 232d movs r3, #45 ; 0x2d 8009df2: 426d negs r5, r5 8009df4: f884 3043 strb.w r3, [r4, #67] ; 0x43 8009df8: 485e ldr r0, [pc, #376] ; (8009f74 <_printf_i+0x244>) 8009dfa: 230a movs r3, #10 8009dfc: e019 b.n 8009e32 <_printf_i+0x102> 8009dfe: f015 0f40 tst.w r5, #64 ; 0x40 8009e02: 6805 ldr r5, [r0, #0] 8009e04: 600b str r3, [r1, #0] 8009e06: bf18 it ne 8009e08: b22d sxthne r5, r5 8009e0a: e7ef b.n 8009dec <_printf_i+0xbc> 8009e0c: 680b ldr r3, [r1, #0] 8009e0e: 6825 ldr r5, [r4, #0] 8009e10: 1d18 adds r0, r3, #4 8009e12: 6008 str r0, [r1, #0] 8009e14: 0628 lsls r0, r5, #24 8009e16: d501 bpl.n 8009e1c <_printf_i+0xec> 8009e18: 681d ldr r5, [r3, #0] 8009e1a: e002 b.n 8009e22 <_printf_i+0xf2> 8009e1c: 0669 lsls r1, r5, #25 8009e1e: d5fb bpl.n 8009e18 <_printf_i+0xe8> 8009e20: 881d ldrh r5, [r3, #0] 8009e22: 4854 ldr r0, [pc, #336] ; (8009f74 <_printf_i+0x244>) 8009e24: 2f6f cmp r7, #111 ; 0x6f 8009e26: bf0c ite eq 8009e28: 2308 moveq r3, #8 8009e2a: 230a movne r3, #10 8009e2c: 2100 movs r1, #0 8009e2e: f884 1043 strb.w r1, [r4, #67] ; 0x43 8009e32: 6866 ldr r6, [r4, #4] 8009e34: 60a6 str r6, [r4, #8] 8009e36: 2e00 cmp r6, #0 8009e38: bfa2 ittt ge 8009e3a: 6821 ldrge r1, [r4, #0] 8009e3c: f021 0104 bicge.w r1, r1, #4 8009e40: 6021 strge r1, [r4, #0] 8009e42: b90d cbnz r5, 8009e48 <_printf_i+0x118> 8009e44: 2e00 cmp r6, #0 8009e46: d04d beq.n 8009ee4 <_printf_i+0x1b4> 8009e48: 4616 mov r6, r2 8009e4a: fbb5 f1f3 udiv r1, r5, r3 8009e4e: fb03 5711 mls r7, r3, r1, r5 8009e52: 5dc7 ldrb r7, [r0, r7] 8009e54: f806 7d01 strb.w r7, [r6, #-1]! 8009e58: 462f mov r7, r5 8009e5a: 42bb cmp r3, r7 8009e5c: 460d mov r5, r1 8009e5e: d9f4 bls.n 8009e4a <_printf_i+0x11a> 8009e60: 2b08 cmp r3, #8 8009e62: d10b bne.n 8009e7c <_printf_i+0x14c> 8009e64: 6823 ldr r3, [r4, #0] 8009e66: 07df lsls r7, r3, #31 8009e68: d508 bpl.n 8009e7c <_printf_i+0x14c> 8009e6a: 6923 ldr r3, [r4, #16] 8009e6c: 6861 ldr r1, [r4, #4] 8009e6e: 4299 cmp r1, r3 8009e70: bfde ittt le 8009e72: 2330 movle r3, #48 ; 0x30 8009e74: f806 3c01 strble.w r3, [r6, #-1] 8009e78: f106 36ff addle.w r6, r6, #4294967295 ; 0xffffffff 8009e7c: 1b92 subs r2, r2, r6 8009e7e: 6122 str r2, [r4, #16] 8009e80: f8cd a000 str.w sl, [sp] 8009e84: 464b mov r3, r9 8009e86: aa03 add r2, sp, #12 8009e88: 4621 mov r1, r4 8009e8a: 4640 mov r0, r8 8009e8c: f7ff fee2 bl 8009c54 <_printf_common> 8009e90: 3001 adds r0, #1 8009e92: d14c bne.n 8009f2e <_printf_i+0x1fe> 8009e94: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8009e98: b004 add sp, #16 8009e9a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8009e9e: 4835 ldr r0, [pc, #212] ; (8009f74 <_printf_i+0x244>) 8009ea0: f884 7045 strb.w r7, [r4, #69] ; 0x45 8009ea4: 6823 ldr r3, [r4, #0] 8009ea6: 680e ldr r6, [r1, #0] 8009ea8: 061f lsls r7, r3, #24 8009eaa: f856 5b04 ldr.w r5, [r6], #4 8009eae: 600e str r6, [r1, #0] 8009eb0: d514 bpl.n 8009edc <_printf_i+0x1ac> 8009eb2: 07d9 lsls r1, r3, #31 8009eb4: bf44 itt mi 8009eb6: f043 0320 orrmi.w r3, r3, #32 8009eba: 6023 strmi r3, [r4, #0] 8009ebc: b91d cbnz r5, 8009ec6 <_printf_i+0x196> 8009ebe: 6823 ldr r3, [r4, #0] 8009ec0: f023 0320 bic.w r3, r3, #32 8009ec4: 6023 str r3, [r4, #0] 8009ec6: 2310 movs r3, #16 8009ec8: e7b0 b.n 8009e2c <_printf_i+0xfc> 8009eca: 6823 ldr r3, [r4, #0] 8009ecc: f043 0320 orr.w r3, r3, #32 8009ed0: 6023 str r3, [r4, #0] 8009ed2: 2378 movs r3, #120 ; 0x78 8009ed4: 4828 ldr r0, [pc, #160] ; (8009f78 <_printf_i+0x248>) 8009ed6: f884 3045 strb.w r3, [r4, #69] ; 0x45 8009eda: e7e3 b.n 8009ea4 <_printf_i+0x174> 8009edc: 065e lsls r6, r3, #25 8009ede: bf48 it mi 8009ee0: b2ad uxthmi r5, r5 8009ee2: e7e6 b.n 8009eb2 <_printf_i+0x182> 8009ee4: 4616 mov r6, r2 8009ee6: e7bb b.n 8009e60 <_printf_i+0x130> 8009ee8: 680b ldr r3, [r1, #0] 8009eea: 6826 ldr r6, [r4, #0] 8009eec: 6960 ldr r0, [r4, #20] 8009eee: 1d1d adds r5, r3, #4 8009ef0: 600d str r5, [r1, #0] 8009ef2: 0635 lsls r5, r6, #24 8009ef4: 681b ldr r3, [r3, #0] 8009ef6: d501 bpl.n 8009efc <_printf_i+0x1cc> 8009ef8: 6018 str r0, [r3, #0] 8009efa: e002 b.n 8009f02 <_printf_i+0x1d2> 8009efc: 0671 lsls r1, r6, #25 8009efe: d5fb bpl.n 8009ef8 <_printf_i+0x1c8> 8009f00: 8018 strh r0, [r3, #0] 8009f02: 2300 movs r3, #0 8009f04: 6123 str r3, [r4, #16] 8009f06: 4616 mov r6, r2 8009f08: e7ba b.n 8009e80 <_printf_i+0x150> 8009f0a: 680b ldr r3, [r1, #0] 8009f0c: 1d1a adds r2, r3, #4 8009f0e: 600a str r2, [r1, #0] 8009f10: 681e ldr r6, [r3, #0] 8009f12: 6862 ldr r2, [r4, #4] 8009f14: 2100 movs r1, #0 8009f16: 4630 mov r0, r6 8009f18: f7f6 f9fa bl 8000310 8009f1c: b108 cbz r0, 8009f22 <_printf_i+0x1f2> 8009f1e: 1b80 subs r0, r0, r6 8009f20: 6060 str r0, [r4, #4] 8009f22: 6863 ldr r3, [r4, #4] 8009f24: 6123 str r3, [r4, #16] 8009f26: 2300 movs r3, #0 8009f28: f884 3043 strb.w r3, [r4, #67] ; 0x43 8009f2c: e7a8 b.n 8009e80 <_printf_i+0x150> 8009f2e: 6923 ldr r3, [r4, #16] 8009f30: 4632 mov r2, r6 8009f32: 4649 mov r1, r9 8009f34: 4640 mov r0, r8 8009f36: 47d0 blx sl 8009f38: 3001 adds r0, #1 8009f3a: d0ab beq.n 8009e94 <_printf_i+0x164> 8009f3c: 6823 ldr r3, [r4, #0] 8009f3e: 079b lsls r3, r3, #30 8009f40: d413 bmi.n 8009f6a <_printf_i+0x23a> 8009f42: 68e0 ldr r0, [r4, #12] 8009f44: 9b03 ldr r3, [sp, #12] 8009f46: 4298 cmp r0, r3 8009f48: bfb8 it lt 8009f4a: 4618 movlt r0, r3 8009f4c: e7a4 b.n 8009e98 <_printf_i+0x168> 8009f4e: 2301 movs r3, #1 8009f50: 4632 mov r2, r6 8009f52: 4649 mov r1, r9 8009f54: 4640 mov r0, r8 8009f56: 47d0 blx sl 8009f58: 3001 adds r0, #1 8009f5a: d09b beq.n 8009e94 <_printf_i+0x164> 8009f5c: 3501 adds r5, #1 8009f5e: 68e3 ldr r3, [r4, #12] 8009f60: 9903 ldr r1, [sp, #12] 8009f62: 1a5b subs r3, r3, r1 8009f64: 42ab cmp r3, r5 8009f66: dcf2 bgt.n 8009f4e <_printf_i+0x21e> 8009f68: e7eb b.n 8009f42 <_printf_i+0x212> 8009f6a: 2500 movs r5, #0 8009f6c: f104 0619 add.w r6, r4, #25 8009f70: e7f5 b.n 8009f5e <_printf_i+0x22e> 8009f72: bf00 nop 8009f74: 0800aa71 .word 0x0800aa71 8009f78: 0800aa82 .word 0x0800aa82 08009f7c <__swbuf_r>: 8009f7c: b5f8 push {r3, r4, r5, r6, r7, lr} 8009f7e: 460e mov r6, r1 8009f80: 4614 mov r4, r2 8009f82: 4605 mov r5, r0 8009f84: b118 cbz r0, 8009f8e <__swbuf_r+0x12> 8009f86: 6983 ldr r3, [r0, #24] 8009f88: b90b cbnz r3, 8009f8e <__swbuf_r+0x12> 8009f8a: f000 f9d9 bl 800a340 <__sinit> 8009f8e: 4b21 ldr r3, [pc, #132] ; (800a014 <__swbuf_r+0x98>) 8009f90: 429c cmp r4, r3 8009f92: d12b bne.n 8009fec <__swbuf_r+0x70> 8009f94: 686c ldr r4, [r5, #4] 8009f96: 69a3 ldr r3, [r4, #24] 8009f98: 60a3 str r3, [r4, #8] 8009f9a: 89a3 ldrh r3, [r4, #12] 8009f9c: 071a lsls r2, r3, #28 8009f9e: d52f bpl.n 800a000 <__swbuf_r+0x84> 8009fa0: 6923 ldr r3, [r4, #16] 8009fa2: b36b cbz r3, 800a000 <__swbuf_r+0x84> 8009fa4: 6923 ldr r3, [r4, #16] 8009fa6: 6820 ldr r0, [r4, #0] 8009fa8: 1ac0 subs r0, r0, r3 8009faa: 6963 ldr r3, [r4, #20] 8009fac: b2f6 uxtb r6, r6 8009fae: 4283 cmp r3, r0 8009fb0: 4637 mov r7, r6 8009fb2: dc04 bgt.n 8009fbe <__swbuf_r+0x42> 8009fb4: 4621 mov r1, r4 8009fb6: 4628 mov r0, r5 8009fb8: f000 f92e bl 800a218 <_fflush_r> 8009fbc: bb30 cbnz r0, 800a00c <__swbuf_r+0x90> 8009fbe: 68a3 ldr r3, [r4, #8] 8009fc0: 3b01 subs r3, #1 8009fc2: 60a3 str r3, [r4, #8] 8009fc4: 6823 ldr r3, [r4, #0] 8009fc6: 1c5a adds r2, r3, #1 8009fc8: 6022 str r2, [r4, #0] 8009fca: 701e strb r6, [r3, #0] 8009fcc: 6963 ldr r3, [r4, #20] 8009fce: 3001 adds r0, #1 8009fd0: 4283 cmp r3, r0 8009fd2: d004 beq.n 8009fde <__swbuf_r+0x62> 8009fd4: 89a3 ldrh r3, [r4, #12] 8009fd6: 07db lsls r3, r3, #31 8009fd8: d506 bpl.n 8009fe8 <__swbuf_r+0x6c> 8009fda: 2e0a cmp r6, #10 8009fdc: d104 bne.n 8009fe8 <__swbuf_r+0x6c> 8009fde: 4621 mov r1, r4 8009fe0: 4628 mov r0, r5 8009fe2: f000 f919 bl 800a218 <_fflush_r> 8009fe6: b988 cbnz r0, 800a00c <__swbuf_r+0x90> 8009fe8: 4638 mov r0, r7 8009fea: bdf8 pop {r3, r4, r5, r6, r7, pc} 8009fec: 4b0a ldr r3, [pc, #40] ; (800a018 <__swbuf_r+0x9c>) 8009fee: 429c cmp r4, r3 8009ff0: d101 bne.n 8009ff6 <__swbuf_r+0x7a> 8009ff2: 68ac ldr r4, [r5, #8] 8009ff4: e7cf b.n 8009f96 <__swbuf_r+0x1a> 8009ff6: 4b09 ldr r3, [pc, #36] ; (800a01c <__swbuf_r+0xa0>) 8009ff8: 429c cmp r4, r3 8009ffa: bf08 it eq 8009ffc: 68ec ldreq r4, [r5, #12] 8009ffe: e7ca b.n 8009f96 <__swbuf_r+0x1a> 800a000: 4621 mov r1, r4 800a002: 4628 mov r0, r5 800a004: f000 f80c bl 800a020 <__swsetup_r> 800a008: 2800 cmp r0, #0 800a00a: d0cb beq.n 8009fa4 <__swbuf_r+0x28> 800a00c: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff 800a010: e7ea b.n 8009fe8 <__swbuf_r+0x6c> 800a012: bf00 nop 800a014: 0800aab4 .word 0x0800aab4 800a018: 0800aad4 .word 0x0800aad4 800a01c: 0800aa94 .word 0x0800aa94 0800a020 <__swsetup_r>: 800a020: 4b32 ldr r3, [pc, #200] ; (800a0ec <__swsetup_r+0xcc>) 800a022: b570 push {r4, r5, r6, lr} 800a024: 681d ldr r5, [r3, #0] 800a026: 4606 mov r6, r0 800a028: 460c mov r4, r1 800a02a: b125 cbz r5, 800a036 <__swsetup_r+0x16> 800a02c: 69ab ldr r3, [r5, #24] 800a02e: b913 cbnz r3, 800a036 <__swsetup_r+0x16> 800a030: 4628 mov r0, r5 800a032: f000 f985 bl 800a340 <__sinit> 800a036: 4b2e ldr r3, [pc, #184] ; (800a0f0 <__swsetup_r+0xd0>) 800a038: 429c cmp r4, r3 800a03a: d10f bne.n 800a05c <__swsetup_r+0x3c> 800a03c: 686c ldr r4, [r5, #4] 800a03e: 89a3 ldrh r3, [r4, #12] 800a040: f9b4 200c ldrsh.w r2, [r4, #12] 800a044: 0719 lsls r1, r3, #28 800a046: d42c bmi.n 800a0a2 <__swsetup_r+0x82> 800a048: 06dd lsls r5, r3, #27 800a04a: d411 bmi.n 800a070 <__swsetup_r+0x50> 800a04c: 2309 movs r3, #9 800a04e: 6033 str r3, [r6, #0] 800a050: f042 0340 orr.w r3, r2, #64 ; 0x40 800a054: 81a3 strh r3, [r4, #12] 800a056: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800a05a: e03e b.n 800a0da <__swsetup_r+0xba> 800a05c: 4b25 ldr r3, [pc, #148] ; (800a0f4 <__swsetup_r+0xd4>) 800a05e: 429c cmp r4, r3 800a060: d101 bne.n 800a066 <__swsetup_r+0x46> 800a062: 68ac ldr r4, [r5, #8] 800a064: e7eb b.n 800a03e <__swsetup_r+0x1e> 800a066: 4b24 ldr r3, [pc, #144] ; (800a0f8 <__swsetup_r+0xd8>) 800a068: 429c cmp r4, r3 800a06a: bf08 it eq 800a06c: 68ec ldreq r4, [r5, #12] 800a06e: e7e6 b.n 800a03e <__swsetup_r+0x1e> 800a070: 0758 lsls r0, r3, #29 800a072: d512 bpl.n 800a09a <__swsetup_r+0x7a> 800a074: 6b61 ldr r1, [r4, #52] ; 0x34 800a076: b141 cbz r1, 800a08a <__swsetup_r+0x6a> 800a078: f104 0344 add.w r3, r4, #68 ; 0x44 800a07c: 4299 cmp r1, r3 800a07e: d002 beq.n 800a086 <__swsetup_r+0x66> 800a080: 4630 mov r0, r6 800a082: f000 fa61 bl 800a548 <_free_r> 800a086: 2300 movs r3, #0 800a088: 6363 str r3, [r4, #52] ; 0x34 800a08a: 89a3 ldrh r3, [r4, #12] 800a08c: f023 0324 bic.w r3, r3, #36 ; 0x24 800a090: 81a3 strh r3, [r4, #12] 800a092: 2300 movs r3, #0 800a094: 6063 str r3, [r4, #4] 800a096: 6923 ldr r3, [r4, #16] 800a098: 6023 str r3, [r4, #0] 800a09a: 89a3 ldrh r3, [r4, #12] 800a09c: f043 0308 orr.w r3, r3, #8 800a0a0: 81a3 strh r3, [r4, #12] 800a0a2: 6923 ldr r3, [r4, #16] 800a0a4: b94b cbnz r3, 800a0ba <__swsetup_r+0x9a> 800a0a6: 89a3 ldrh r3, [r4, #12] 800a0a8: f403 7320 and.w r3, r3, #640 ; 0x280 800a0ac: f5b3 7f00 cmp.w r3, #512 ; 0x200 800a0b0: d003 beq.n 800a0ba <__swsetup_r+0x9a> 800a0b2: 4621 mov r1, r4 800a0b4: 4630 mov r0, r6 800a0b6: f000 fa07 bl 800a4c8 <__smakebuf_r> 800a0ba: 89a0 ldrh r0, [r4, #12] 800a0bc: f9b4 200c ldrsh.w r2, [r4, #12] 800a0c0: f010 0301 ands.w r3, r0, #1 800a0c4: d00a beq.n 800a0dc <__swsetup_r+0xbc> 800a0c6: 2300 movs r3, #0 800a0c8: 60a3 str r3, [r4, #8] 800a0ca: 6963 ldr r3, [r4, #20] 800a0cc: 425b negs r3, r3 800a0ce: 61a3 str r3, [r4, #24] 800a0d0: 6923 ldr r3, [r4, #16] 800a0d2: b943 cbnz r3, 800a0e6 <__swsetup_r+0xc6> 800a0d4: f010 0080 ands.w r0, r0, #128 ; 0x80 800a0d8: d1ba bne.n 800a050 <__swsetup_r+0x30> 800a0da: bd70 pop {r4, r5, r6, pc} 800a0dc: 0781 lsls r1, r0, #30 800a0de: bf58 it pl 800a0e0: 6963 ldrpl r3, [r4, #20] 800a0e2: 60a3 str r3, [r4, #8] 800a0e4: e7f4 b.n 800a0d0 <__swsetup_r+0xb0> 800a0e6: 2000 movs r0, #0 800a0e8: e7f7 b.n 800a0da <__swsetup_r+0xba> 800a0ea: bf00 nop 800a0ec: 24000184 .word 0x24000184 800a0f0: 0800aab4 .word 0x0800aab4 800a0f4: 0800aad4 .word 0x0800aad4 800a0f8: 0800aa94 .word 0x0800aa94 0800a0fc : 800a0fc: b508 push {r3, lr} 800a0fe: 2006 movs r0, #6 800a100: f000 fb04 bl 800a70c 800a104: 2001 movs r0, #1 800a106: f7f7 f8d1 bl 80012ac <_exit> ... 0800a10c <__sflush_r>: 800a10c: 898a ldrh r2, [r1, #12] 800a10e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800a112: 4605 mov r5, r0 800a114: 0710 lsls r0, r2, #28 800a116: 460c mov r4, r1 800a118: d458 bmi.n 800a1cc <__sflush_r+0xc0> 800a11a: 684b ldr r3, [r1, #4] 800a11c: 2b00 cmp r3, #0 800a11e: dc05 bgt.n 800a12c <__sflush_r+0x20> 800a120: 6c0b ldr r3, [r1, #64] ; 0x40 800a122: 2b00 cmp r3, #0 800a124: dc02 bgt.n 800a12c <__sflush_r+0x20> 800a126: 2000 movs r0, #0 800a128: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800a12c: 6ae6 ldr r6, [r4, #44] ; 0x2c 800a12e: 2e00 cmp r6, #0 800a130: d0f9 beq.n 800a126 <__sflush_r+0x1a> 800a132: 2300 movs r3, #0 800a134: f412 5280 ands.w r2, r2, #4096 ; 0x1000 800a138: 682f ldr r7, [r5, #0] 800a13a: 602b str r3, [r5, #0] 800a13c: d032 beq.n 800a1a4 <__sflush_r+0x98> 800a13e: 6d60 ldr r0, [r4, #84] ; 0x54 800a140: 89a3 ldrh r3, [r4, #12] 800a142: 075a lsls r2, r3, #29 800a144: d505 bpl.n 800a152 <__sflush_r+0x46> 800a146: 6863 ldr r3, [r4, #4] 800a148: 1ac0 subs r0, r0, r3 800a14a: 6b63 ldr r3, [r4, #52] ; 0x34 800a14c: b10b cbz r3, 800a152 <__sflush_r+0x46> 800a14e: 6c23 ldr r3, [r4, #64] ; 0x40 800a150: 1ac0 subs r0, r0, r3 800a152: 2300 movs r3, #0 800a154: 4602 mov r2, r0 800a156: 6ae6 ldr r6, [r4, #44] ; 0x2c 800a158: 6a21 ldr r1, [r4, #32] 800a15a: 4628 mov r0, r5 800a15c: 47b0 blx r6 800a15e: 1c43 adds r3, r0, #1 800a160: 89a3 ldrh r3, [r4, #12] 800a162: d106 bne.n 800a172 <__sflush_r+0x66> 800a164: 6829 ldr r1, [r5, #0] 800a166: 291d cmp r1, #29 800a168: d82c bhi.n 800a1c4 <__sflush_r+0xb8> 800a16a: 4a2a ldr r2, [pc, #168] ; (800a214 <__sflush_r+0x108>) 800a16c: 40ca lsrs r2, r1 800a16e: 07d6 lsls r6, r2, #31 800a170: d528 bpl.n 800a1c4 <__sflush_r+0xb8> 800a172: 2200 movs r2, #0 800a174: 6062 str r2, [r4, #4] 800a176: 04d9 lsls r1, r3, #19 800a178: 6922 ldr r2, [r4, #16] 800a17a: 6022 str r2, [r4, #0] 800a17c: d504 bpl.n 800a188 <__sflush_r+0x7c> 800a17e: 1c42 adds r2, r0, #1 800a180: d101 bne.n 800a186 <__sflush_r+0x7a> 800a182: 682b ldr r3, [r5, #0] 800a184: b903 cbnz r3, 800a188 <__sflush_r+0x7c> 800a186: 6560 str r0, [r4, #84] ; 0x54 800a188: 6b61 ldr r1, [r4, #52] ; 0x34 800a18a: 602f str r7, [r5, #0] 800a18c: 2900 cmp r1, #0 800a18e: d0ca beq.n 800a126 <__sflush_r+0x1a> 800a190: f104 0344 add.w r3, r4, #68 ; 0x44 800a194: 4299 cmp r1, r3 800a196: d002 beq.n 800a19e <__sflush_r+0x92> 800a198: 4628 mov r0, r5 800a19a: f000 f9d5 bl 800a548 <_free_r> 800a19e: 2000 movs r0, #0 800a1a0: 6360 str r0, [r4, #52] ; 0x34 800a1a2: e7c1 b.n 800a128 <__sflush_r+0x1c> 800a1a4: 6a21 ldr r1, [r4, #32] 800a1a6: 2301 movs r3, #1 800a1a8: 4628 mov r0, r5 800a1aa: 47b0 blx r6 800a1ac: 1c41 adds r1, r0, #1 800a1ae: d1c7 bne.n 800a140 <__sflush_r+0x34> 800a1b0: 682b ldr r3, [r5, #0] 800a1b2: 2b00 cmp r3, #0 800a1b4: d0c4 beq.n 800a140 <__sflush_r+0x34> 800a1b6: 2b1d cmp r3, #29 800a1b8: d001 beq.n 800a1be <__sflush_r+0xb2> 800a1ba: 2b16 cmp r3, #22 800a1bc: d101 bne.n 800a1c2 <__sflush_r+0xb6> 800a1be: 602f str r7, [r5, #0] 800a1c0: e7b1 b.n 800a126 <__sflush_r+0x1a> 800a1c2: 89a3 ldrh r3, [r4, #12] 800a1c4: f043 0340 orr.w r3, r3, #64 ; 0x40 800a1c8: 81a3 strh r3, [r4, #12] 800a1ca: e7ad b.n 800a128 <__sflush_r+0x1c> 800a1cc: 690f ldr r7, [r1, #16] 800a1ce: 2f00 cmp r7, #0 800a1d0: d0a9 beq.n 800a126 <__sflush_r+0x1a> 800a1d2: 0793 lsls r3, r2, #30 800a1d4: 680e ldr r6, [r1, #0] 800a1d6: bf08 it eq 800a1d8: 694b ldreq r3, [r1, #20] 800a1da: 600f str r7, [r1, #0] 800a1dc: bf18 it ne 800a1de: 2300 movne r3, #0 800a1e0: eba6 0807 sub.w r8, r6, r7 800a1e4: 608b str r3, [r1, #8] 800a1e6: f1b8 0f00 cmp.w r8, #0 800a1ea: dd9c ble.n 800a126 <__sflush_r+0x1a> 800a1ec: 6a21 ldr r1, [r4, #32] 800a1ee: 6aa6 ldr r6, [r4, #40] ; 0x28 800a1f0: 4643 mov r3, r8 800a1f2: 463a mov r2, r7 800a1f4: 4628 mov r0, r5 800a1f6: 47b0 blx r6 800a1f8: 2800 cmp r0, #0 800a1fa: dc06 bgt.n 800a20a <__sflush_r+0xfe> 800a1fc: 89a3 ldrh r3, [r4, #12] 800a1fe: f043 0340 orr.w r3, r3, #64 ; 0x40 800a202: 81a3 strh r3, [r4, #12] 800a204: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800a208: e78e b.n 800a128 <__sflush_r+0x1c> 800a20a: 4407 add r7, r0 800a20c: eba8 0800 sub.w r8, r8, r0 800a210: e7e9 b.n 800a1e6 <__sflush_r+0xda> 800a212: bf00 nop 800a214: 20400001 .word 0x20400001 0800a218 <_fflush_r>: 800a218: b538 push {r3, r4, r5, lr} 800a21a: 690b ldr r3, [r1, #16] 800a21c: 4605 mov r5, r0 800a21e: 460c mov r4, r1 800a220: b913 cbnz r3, 800a228 <_fflush_r+0x10> 800a222: 2500 movs r5, #0 800a224: 4628 mov r0, r5 800a226: bd38 pop {r3, r4, r5, pc} 800a228: b118 cbz r0, 800a232 <_fflush_r+0x1a> 800a22a: 6983 ldr r3, [r0, #24] 800a22c: b90b cbnz r3, 800a232 <_fflush_r+0x1a> 800a22e: f000 f887 bl 800a340 <__sinit> 800a232: 4b14 ldr r3, [pc, #80] ; (800a284 <_fflush_r+0x6c>) 800a234: 429c cmp r4, r3 800a236: d11b bne.n 800a270 <_fflush_r+0x58> 800a238: 686c ldr r4, [r5, #4] 800a23a: f9b4 300c ldrsh.w r3, [r4, #12] 800a23e: 2b00 cmp r3, #0 800a240: d0ef beq.n 800a222 <_fflush_r+0xa> 800a242: 6e62 ldr r2, [r4, #100] ; 0x64 800a244: 07d0 lsls r0, r2, #31 800a246: d404 bmi.n 800a252 <_fflush_r+0x3a> 800a248: 0599 lsls r1, r3, #22 800a24a: d402 bmi.n 800a252 <_fflush_r+0x3a> 800a24c: 6da0 ldr r0, [r4, #88] ; 0x58 800a24e: f000 f915 bl 800a47c <__retarget_lock_acquire_recursive> 800a252: 4628 mov r0, r5 800a254: 4621 mov r1, r4 800a256: f7ff ff59 bl 800a10c <__sflush_r> 800a25a: 6e63 ldr r3, [r4, #100] ; 0x64 800a25c: 07da lsls r2, r3, #31 800a25e: 4605 mov r5, r0 800a260: d4e0 bmi.n 800a224 <_fflush_r+0xc> 800a262: 89a3 ldrh r3, [r4, #12] 800a264: 059b lsls r3, r3, #22 800a266: d4dd bmi.n 800a224 <_fflush_r+0xc> 800a268: 6da0 ldr r0, [r4, #88] ; 0x58 800a26a: f000 f908 bl 800a47e <__retarget_lock_release_recursive> 800a26e: e7d9 b.n 800a224 <_fflush_r+0xc> 800a270: 4b05 ldr r3, [pc, #20] ; (800a288 <_fflush_r+0x70>) 800a272: 429c cmp r4, r3 800a274: d101 bne.n 800a27a <_fflush_r+0x62> 800a276: 68ac ldr r4, [r5, #8] 800a278: e7df b.n 800a23a <_fflush_r+0x22> 800a27a: 4b04 ldr r3, [pc, #16] ; (800a28c <_fflush_r+0x74>) 800a27c: 429c cmp r4, r3 800a27e: bf08 it eq 800a280: 68ec ldreq r4, [r5, #12] 800a282: e7da b.n 800a23a <_fflush_r+0x22> 800a284: 0800aab4 .word 0x0800aab4 800a288: 0800aad4 .word 0x0800aad4 800a28c: 0800aa94 .word 0x0800aa94 0800a290 : 800a290: 2300 movs r3, #0 800a292: b510 push {r4, lr} 800a294: 4604 mov r4, r0 800a296: e9c0 3300 strd r3, r3, [r0] 800a29a: e9c0 3304 strd r3, r3, [r0, #16] 800a29e: 6083 str r3, [r0, #8] 800a2a0: 8181 strh r1, [r0, #12] 800a2a2: 6643 str r3, [r0, #100] ; 0x64 800a2a4: 81c2 strh r2, [r0, #14] 800a2a6: 6183 str r3, [r0, #24] 800a2a8: 4619 mov r1, r3 800a2aa: 2208 movs r2, #8 800a2ac: 305c adds r0, #92 ; 0x5c 800a2ae: f7ff fb6f bl 8009990 800a2b2: 4b05 ldr r3, [pc, #20] ; (800a2c8 ) 800a2b4: 6263 str r3, [r4, #36] ; 0x24 800a2b6: 4b05 ldr r3, [pc, #20] ; (800a2cc ) 800a2b8: 62a3 str r3, [r4, #40] ; 0x28 800a2ba: 4b05 ldr r3, [pc, #20] ; (800a2d0 ) 800a2bc: 62e3 str r3, [r4, #44] ; 0x2c 800a2be: 4b05 ldr r3, [pc, #20] ; (800a2d4 ) 800a2c0: 6224 str r4, [r4, #32] 800a2c2: 6323 str r3, [r4, #48] ; 0x30 800a2c4: bd10 pop {r4, pc} 800a2c6: bf00 nop 800a2c8: 0800a745 .word 0x0800a745 800a2cc: 0800a767 .word 0x0800a767 800a2d0: 0800a79f .word 0x0800a79f 800a2d4: 0800a7c3 .word 0x0800a7c3 0800a2d8 <_cleanup_r>: 800a2d8: 4901 ldr r1, [pc, #4] ; (800a2e0 <_cleanup_r+0x8>) 800a2da: f000 b8af b.w 800a43c <_fwalk_reent> 800a2de: bf00 nop 800a2e0: 0800a219 .word 0x0800a219 0800a2e4 <__sfmoreglue>: 800a2e4: b570 push {r4, r5, r6, lr} 800a2e6: 1e4a subs r2, r1, #1 800a2e8: 2568 movs r5, #104 ; 0x68 800a2ea: 4355 muls r5, r2 800a2ec: 460e mov r6, r1 800a2ee: f105 0174 add.w r1, r5, #116 ; 0x74 800a2f2: f000 f979 bl 800a5e8 <_malloc_r> 800a2f6: 4604 mov r4, r0 800a2f8: b140 cbz r0, 800a30c <__sfmoreglue+0x28> 800a2fa: 2100 movs r1, #0 800a2fc: e9c0 1600 strd r1, r6, [r0] 800a300: 300c adds r0, #12 800a302: 60a0 str r0, [r4, #8] 800a304: f105 0268 add.w r2, r5, #104 ; 0x68 800a308: f7ff fb42 bl 8009990 800a30c: 4620 mov r0, r4 800a30e: bd70 pop {r4, r5, r6, pc} 0800a310 <__sfp_lock_acquire>: 800a310: 4801 ldr r0, [pc, #4] ; (800a318 <__sfp_lock_acquire+0x8>) 800a312: f000 b8b3 b.w 800a47c <__retarget_lock_acquire_recursive> 800a316: bf00 nop 800a318: 24002d10 .word 0x24002d10 0800a31c <__sfp_lock_release>: 800a31c: 4801 ldr r0, [pc, #4] ; (800a324 <__sfp_lock_release+0x8>) 800a31e: f000 b8ae b.w 800a47e <__retarget_lock_release_recursive> 800a322: bf00 nop 800a324: 24002d10 .word 0x24002d10 0800a328 <__sinit_lock_acquire>: 800a328: 4801 ldr r0, [pc, #4] ; (800a330 <__sinit_lock_acquire+0x8>) 800a32a: f000 b8a7 b.w 800a47c <__retarget_lock_acquire_recursive> 800a32e: bf00 nop 800a330: 24002d0b .word 0x24002d0b 0800a334 <__sinit_lock_release>: 800a334: 4801 ldr r0, [pc, #4] ; (800a33c <__sinit_lock_release+0x8>) 800a336: f000 b8a2 b.w 800a47e <__retarget_lock_release_recursive> 800a33a: bf00 nop 800a33c: 24002d0b .word 0x24002d0b 0800a340 <__sinit>: 800a340: b510 push {r4, lr} 800a342: 4604 mov r4, r0 800a344: f7ff fff0 bl 800a328 <__sinit_lock_acquire> 800a348: 69a3 ldr r3, [r4, #24] 800a34a: b11b cbz r3, 800a354 <__sinit+0x14> 800a34c: e8bd 4010 ldmia.w sp!, {r4, lr} 800a350: f7ff bff0 b.w 800a334 <__sinit_lock_release> 800a354: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 800a358: 6523 str r3, [r4, #80] ; 0x50 800a35a: 4b13 ldr r3, [pc, #76] ; (800a3a8 <__sinit+0x68>) 800a35c: 4a13 ldr r2, [pc, #76] ; (800a3ac <__sinit+0x6c>) 800a35e: 681b ldr r3, [r3, #0] 800a360: 62a2 str r2, [r4, #40] ; 0x28 800a362: 42a3 cmp r3, r4 800a364: bf04 itt eq 800a366: 2301 moveq r3, #1 800a368: 61a3 streq r3, [r4, #24] 800a36a: 4620 mov r0, r4 800a36c: f000 f820 bl 800a3b0 <__sfp> 800a370: 6060 str r0, [r4, #4] 800a372: 4620 mov r0, r4 800a374: f000 f81c bl 800a3b0 <__sfp> 800a378: 60a0 str r0, [r4, #8] 800a37a: 4620 mov r0, r4 800a37c: f000 f818 bl 800a3b0 <__sfp> 800a380: 2200 movs r2, #0 800a382: 60e0 str r0, [r4, #12] 800a384: 2104 movs r1, #4 800a386: 6860 ldr r0, [r4, #4] 800a388: f7ff ff82 bl 800a290 800a38c: 68a0 ldr r0, [r4, #8] 800a38e: 2201 movs r2, #1 800a390: 2109 movs r1, #9 800a392: f7ff ff7d bl 800a290 800a396: 68e0 ldr r0, [r4, #12] 800a398: 2202 movs r2, #2 800a39a: 2112 movs r1, #18 800a39c: f7ff ff78 bl 800a290 800a3a0: 2301 movs r3, #1 800a3a2: 61a3 str r3, [r4, #24] 800a3a4: e7d2 b.n 800a34c <__sinit+0xc> 800a3a6: bf00 nop 800a3a8: 0800aa5c .word 0x0800aa5c 800a3ac: 0800a2d9 .word 0x0800a2d9 0800a3b0 <__sfp>: 800a3b0: b5f8 push {r3, r4, r5, r6, r7, lr} 800a3b2: 4607 mov r7, r0 800a3b4: f7ff ffac bl 800a310 <__sfp_lock_acquire> 800a3b8: 4b1e ldr r3, [pc, #120] ; (800a434 <__sfp+0x84>) 800a3ba: 681e ldr r6, [r3, #0] 800a3bc: 69b3 ldr r3, [r6, #24] 800a3be: b913 cbnz r3, 800a3c6 <__sfp+0x16> 800a3c0: 4630 mov r0, r6 800a3c2: f7ff ffbd bl 800a340 <__sinit> 800a3c6: 3648 adds r6, #72 ; 0x48 800a3c8: e9d6 3401 ldrd r3, r4, [r6, #4] 800a3cc: 3b01 subs r3, #1 800a3ce: d503 bpl.n 800a3d8 <__sfp+0x28> 800a3d0: 6833 ldr r3, [r6, #0] 800a3d2: b30b cbz r3, 800a418 <__sfp+0x68> 800a3d4: 6836 ldr r6, [r6, #0] 800a3d6: e7f7 b.n 800a3c8 <__sfp+0x18> 800a3d8: f9b4 500c ldrsh.w r5, [r4, #12] 800a3dc: b9d5 cbnz r5, 800a414 <__sfp+0x64> 800a3de: 4b16 ldr r3, [pc, #88] ; (800a438 <__sfp+0x88>) 800a3e0: 60e3 str r3, [r4, #12] 800a3e2: f104 0058 add.w r0, r4, #88 ; 0x58 800a3e6: 6665 str r5, [r4, #100] ; 0x64 800a3e8: f000 f847 bl 800a47a <__retarget_lock_init_recursive> 800a3ec: f7ff ff96 bl 800a31c <__sfp_lock_release> 800a3f0: e9c4 5501 strd r5, r5, [r4, #4] 800a3f4: e9c4 5504 strd r5, r5, [r4, #16] 800a3f8: 6025 str r5, [r4, #0] 800a3fa: 61a5 str r5, [r4, #24] 800a3fc: 2208 movs r2, #8 800a3fe: 4629 mov r1, r5 800a400: f104 005c add.w r0, r4, #92 ; 0x5c 800a404: f7ff fac4 bl 8009990 800a408: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 800a40c: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 800a410: 4620 mov r0, r4 800a412: bdf8 pop {r3, r4, r5, r6, r7, pc} 800a414: 3468 adds r4, #104 ; 0x68 800a416: e7d9 b.n 800a3cc <__sfp+0x1c> 800a418: 2104 movs r1, #4 800a41a: 4638 mov r0, r7 800a41c: f7ff ff62 bl 800a2e4 <__sfmoreglue> 800a420: 4604 mov r4, r0 800a422: 6030 str r0, [r6, #0] 800a424: 2800 cmp r0, #0 800a426: d1d5 bne.n 800a3d4 <__sfp+0x24> 800a428: f7ff ff78 bl 800a31c <__sfp_lock_release> 800a42c: 230c movs r3, #12 800a42e: 603b str r3, [r7, #0] 800a430: e7ee b.n 800a410 <__sfp+0x60> 800a432: bf00 nop 800a434: 0800aa5c .word 0x0800aa5c 800a438: ffff0001 .word 0xffff0001 0800a43c <_fwalk_reent>: 800a43c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800a440: 4606 mov r6, r0 800a442: 4688 mov r8, r1 800a444: f100 0448 add.w r4, r0, #72 ; 0x48 800a448: 2700 movs r7, #0 800a44a: e9d4 9501 ldrd r9, r5, [r4, #4] 800a44e: f1b9 0901 subs.w r9, r9, #1 800a452: d505 bpl.n 800a460 <_fwalk_reent+0x24> 800a454: 6824 ldr r4, [r4, #0] 800a456: 2c00 cmp r4, #0 800a458: d1f7 bne.n 800a44a <_fwalk_reent+0xe> 800a45a: 4638 mov r0, r7 800a45c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800a460: 89ab ldrh r3, [r5, #12] 800a462: 2b01 cmp r3, #1 800a464: d907 bls.n 800a476 <_fwalk_reent+0x3a> 800a466: f9b5 300e ldrsh.w r3, [r5, #14] 800a46a: 3301 adds r3, #1 800a46c: d003 beq.n 800a476 <_fwalk_reent+0x3a> 800a46e: 4629 mov r1, r5 800a470: 4630 mov r0, r6 800a472: 47c0 blx r8 800a474: 4307 orrs r7, r0 800a476: 3568 adds r5, #104 ; 0x68 800a478: e7e9 b.n 800a44e <_fwalk_reent+0x12> 0800a47a <__retarget_lock_init_recursive>: 800a47a: 4770 bx lr 0800a47c <__retarget_lock_acquire_recursive>: 800a47c: 4770 bx lr 0800a47e <__retarget_lock_release_recursive>: 800a47e: 4770 bx lr 0800a480 <__swhatbuf_r>: 800a480: b570 push {r4, r5, r6, lr} 800a482: 460e mov r6, r1 800a484: f9b1 100e ldrsh.w r1, [r1, #14] 800a488: 2900 cmp r1, #0 800a48a: b096 sub sp, #88 ; 0x58 800a48c: 4614 mov r4, r2 800a48e: 461d mov r5, r3 800a490: da07 bge.n 800a4a2 <__swhatbuf_r+0x22> 800a492: 2300 movs r3, #0 800a494: 602b str r3, [r5, #0] 800a496: 89b3 ldrh r3, [r6, #12] 800a498: 061a lsls r2, r3, #24 800a49a: d410 bmi.n 800a4be <__swhatbuf_r+0x3e> 800a49c: f44f 6380 mov.w r3, #1024 ; 0x400 800a4a0: e00e b.n 800a4c0 <__swhatbuf_r+0x40> 800a4a2: 466a mov r2, sp 800a4a4: f000 f9b4 bl 800a810 <_fstat_r> 800a4a8: 2800 cmp r0, #0 800a4aa: dbf2 blt.n 800a492 <__swhatbuf_r+0x12> 800a4ac: 9a01 ldr r2, [sp, #4] 800a4ae: f402 4270 and.w r2, r2, #61440 ; 0xf000 800a4b2: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 800a4b6: 425a negs r2, r3 800a4b8: 415a adcs r2, r3 800a4ba: 602a str r2, [r5, #0] 800a4bc: e7ee b.n 800a49c <__swhatbuf_r+0x1c> 800a4be: 2340 movs r3, #64 ; 0x40 800a4c0: 2000 movs r0, #0 800a4c2: 6023 str r3, [r4, #0] 800a4c4: b016 add sp, #88 ; 0x58 800a4c6: bd70 pop {r4, r5, r6, pc} 0800a4c8 <__smakebuf_r>: 800a4c8: 898b ldrh r3, [r1, #12] 800a4ca: b573 push {r0, r1, r4, r5, r6, lr} 800a4cc: 079d lsls r5, r3, #30 800a4ce: 4606 mov r6, r0 800a4d0: 460c mov r4, r1 800a4d2: d507 bpl.n 800a4e4 <__smakebuf_r+0x1c> 800a4d4: f104 0347 add.w r3, r4, #71 ; 0x47 800a4d8: 6023 str r3, [r4, #0] 800a4da: 6123 str r3, [r4, #16] 800a4dc: 2301 movs r3, #1 800a4de: 6163 str r3, [r4, #20] 800a4e0: b002 add sp, #8 800a4e2: bd70 pop {r4, r5, r6, pc} 800a4e4: ab01 add r3, sp, #4 800a4e6: 466a mov r2, sp 800a4e8: f7ff ffca bl 800a480 <__swhatbuf_r> 800a4ec: 9900 ldr r1, [sp, #0] 800a4ee: 4605 mov r5, r0 800a4f0: 4630 mov r0, r6 800a4f2: f000 f879 bl 800a5e8 <_malloc_r> 800a4f6: b948 cbnz r0, 800a50c <__smakebuf_r+0x44> 800a4f8: f9b4 300c ldrsh.w r3, [r4, #12] 800a4fc: 059a lsls r2, r3, #22 800a4fe: d4ef bmi.n 800a4e0 <__smakebuf_r+0x18> 800a500: f023 0303 bic.w r3, r3, #3 800a504: f043 0302 orr.w r3, r3, #2 800a508: 81a3 strh r3, [r4, #12] 800a50a: e7e3 b.n 800a4d4 <__smakebuf_r+0xc> 800a50c: 4b0d ldr r3, [pc, #52] ; (800a544 <__smakebuf_r+0x7c>) 800a50e: 62b3 str r3, [r6, #40] ; 0x28 800a510: 89a3 ldrh r3, [r4, #12] 800a512: 6020 str r0, [r4, #0] 800a514: f043 0380 orr.w r3, r3, #128 ; 0x80 800a518: 81a3 strh r3, [r4, #12] 800a51a: 9b00 ldr r3, [sp, #0] 800a51c: 6163 str r3, [r4, #20] 800a51e: 9b01 ldr r3, [sp, #4] 800a520: 6120 str r0, [r4, #16] 800a522: b15b cbz r3, 800a53c <__smakebuf_r+0x74> 800a524: f9b4 100e ldrsh.w r1, [r4, #14] 800a528: 4630 mov r0, r6 800a52a: f000 f983 bl 800a834 <_isatty_r> 800a52e: b128 cbz r0, 800a53c <__smakebuf_r+0x74> 800a530: 89a3 ldrh r3, [r4, #12] 800a532: f023 0303 bic.w r3, r3, #3 800a536: f043 0301 orr.w r3, r3, #1 800a53a: 81a3 strh r3, [r4, #12] 800a53c: 89a0 ldrh r0, [r4, #12] 800a53e: 4305 orrs r5, r0 800a540: 81a5 strh r5, [r4, #12] 800a542: e7cd b.n 800a4e0 <__smakebuf_r+0x18> 800a544: 0800a2d9 .word 0x0800a2d9 0800a548 <_free_r>: 800a548: b537 push {r0, r1, r2, r4, r5, lr} 800a54a: 2900 cmp r1, #0 800a54c: d048 beq.n 800a5e0 <_free_r+0x98> 800a54e: f851 3c04 ldr.w r3, [r1, #-4] 800a552: 9001 str r0, [sp, #4] 800a554: 2b00 cmp r3, #0 800a556: f1a1 0404 sub.w r4, r1, #4 800a55a: bfb8 it lt 800a55c: 18e4 addlt r4, r4, r3 800a55e: f000 f98b bl 800a878 <__malloc_lock> 800a562: 4a20 ldr r2, [pc, #128] ; (800a5e4 <_free_r+0x9c>) 800a564: 9801 ldr r0, [sp, #4] 800a566: 6813 ldr r3, [r2, #0] 800a568: 4615 mov r5, r2 800a56a: b933 cbnz r3, 800a57a <_free_r+0x32> 800a56c: 6063 str r3, [r4, #4] 800a56e: 6014 str r4, [r2, #0] 800a570: b003 add sp, #12 800a572: e8bd 4030 ldmia.w sp!, {r4, r5, lr} 800a576: f000 b985 b.w 800a884 <__malloc_unlock> 800a57a: 42a3 cmp r3, r4 800a57c: d90b bls.n 800a596 <_free_r+0x4e> 800a57e: 6821 ldr r1, [r4, #0] 800a580: 1862 adds r2, r4, r1 800a582: 4293 cmp r3, r2 800a584: bf04 itt eq 800a586: 681a ldreq r2, [r3, #0] 800a588: 685b ldreq r3, [r3, #4] 800a58a: 6063 str r3, [r4, #4] 800a58c: bf04 itt eq 800a58e: 1852 addeq r2, r2, r1 800a590: 6022 streq r2, [r4, #0] 800a592: 602c str r4, [r5, #0] 800a594: e7ec b.n 800a570 <_free_r+0x28> 800a596: 461a mov r2, r3 800a598: 685b ldr r3, [r3, #4] 800a59a: b10b cbz r3, 800a5a0 <_free_r+0x58> 800a59c: 42a3 cmp r3, r4 800a59e: d9fa bls.n 800a596 <_free_r+0x4e> 800a5a0: 6811 ldr r1, [r2, #0] 800a5a2: 1855 adds r5, r2, r1 800a5a4: 42a5 cmp r5, r4 800a5a6: d10b bne.n 800a5c0 <_free_r+0x78> 800a5a8: 6824 ldr r4, [r4, #0] 800a5aa: 4421 add r1, r4 800a5ac: 1854 adds r4, r2, r1 800a5ae: 42a3 cmp r3, r4 800a5b0: 6011 str r1, [r2, #0] 800a5b2: d1dd bne.n 800a570 <_free_r+0x28> 800a5b4: 681c ldr r4, [r3, #0] 800a5b6: 685b ldr r3, [r3, #4] 800a5b8: 6053 str r3, [r2, #4] 800a5ba: 4421 add r1, r4 800a5bc: 6011 str r1, [r2, #0] 800a5be: e7d7 b.n 800a570 <_free_r+0x28> 800a5c0: d902 bls.n 800a5c8 <_free_r+0x80> 800a5c2: 230c movs r3, #12 800a5c4: 6003 str r3, [r0, #0] 800a5c6: e7d3 b.n 800a570 <_free_r+0x28> 800a5c8: 6825 ldr r5, [r4, #0] 800a5ca: 1961 adds r1, r4, r5 800a5cc: 428b cmp r3, r1 800a5ce: bf04 itt eq 800a5d0: 6819 ldreq r1, [r3, #0] 800a5d2: 685b ldreq r3, [r3, #4] 800a5d4: 6063 str r3, [r4, #4] 800a5d6: bf04 itt eq 800a5d8: 1949 addeq r1, r1, r5 800a5da: 6021 streq r1, [r4, #0] 800a5dc: 6054 str r4, [r2, #4] 800a5de: e7c7 b.n 800a570 <_free_r+0x28> 800a5e0: b003 add sp, #12 800a5e2: bd30 pop {r4, r5, pc} 800a5e4: 240013d8 .word 0x240013d8 0800a5e8 <_malloc_r>: 800a5e8: b5f8 push {r3, r4, r5, r6, r7, lr} 800a5ea: 1ccd adds r5, r1, #3 800a5ec: f025 0503 bic.w r5, r5, #3 800a5f0: 3508 adds r5, #8 800a5f2: 2d0c cmp r5, #12 800a5f4: bf38 it cc 800a5f6: 250c movcc r5, #12 800a5f8: 2d00 cmp r5, #0 800a5fa: 4606 mov r6, r0 800a5fc: db01 blt.n 800a602 <_malloc_r+0x1a> 800a5fe: 42a9 cmp r1, r5 800a600: d903 bls.n 800a60a <_malloc_r+0x22> 800a602: 230c movs r3, #12 800a604: 6033 str r3, [r6, #0] 800a606: 2000 movs r0, #0 800a608: bdf8 pop {r3, r4, r5, r6, r7, pc} 800a60a: f000 f935 bl 800a878 <__malloc_lock> 800a60e: 4921 ldr r1, [pc, #132] ; (800a694 <_malloc_r+0xac>) 800a610: 680a ldr r2, [r1, #0] 800a612: 4614 mov r4, r2 800a614: b99c cbnz r4, 800a63e <_malloc_r+0x56> 800a616: 4f20 ldr r7, [pc, #128] ; (800a698 <_malloc_r+0xb0>) 800a618: 683b ldr r3, [r7, #0] 800a61a: b923 cbnz r3, 800a626 <_malloc_r+0x3e> 800a61c: 4621 mov r1, r4 800a61e: 4630 mov r0, r6 800a620: f000 f83c bl 800a69c <_sbrk_r> 800a624: 6038 str r0, [r7, #0] 800a626: 4629 mov r1, r5 800a628: 4630 mov r0, r6 800a62a: f000 f837 bl 800a69c <_sbrk_r> 800a62e: 1c43 adds r3, r0, #1 800a630: d123 bne.n 800a67a <_malloc_r+0x92> 800a632: 230c movs r3, #12 800a634: 6033 str r3, [r6, #0] 800a636: 4630 mov r0, r6 800a638: f000 f924 bl 800a884 <__malloc_unlock> 800a63c: e7e3 b.n 800a606 <_malloc_r+0x1e> 800a63e: 6823 ldr r3, [r4, #0] 800a640: 1b5b subs r3, r3, r5 800a642: d417 bmi.n 800a674 <_malloc_r+0x8c> 800a644: 2b0b cmp r3, #11 800a646: d903 bls.n 800a650 <_malloc_r+0x68> 800a648: 6023 str r3, [r4, #0] 800a64a: 441c add r4, r3 800a64c: 6025 str r5, [r4, #0] 800a64e: e004 b.n 800a65a <_malloc_r+0x72> 800a650: 6863 ldr r3, [r4, #4] 800a652: 42a2 cmp r2, r4 800a654: bf0c ite eq 800a656: 600b streq r3, [r1, #0] 800a658: 6053 strne r3, [r2, #4] 800a65a: 4630 mov r0, r6 800a65c: f000 f912 bl 800a884 <__malloc_unlock> 800a660: f104 000b add.w r0, r4, #11 800a664: 1d23 adds r3, r4, #4 800a666: f020 0007 bic.w r0, r0, #7 800a66a: 1ac2 subs r2, r0, r3 800a66c: d0cc beq.n 800a608 <_malloc_r+0x20> 800a66e: 1a1b subs r3, r3, r0 800a670: 50a3 str r3, [r4, r2] 800a672: e7c9 b.n 800a608 <_malloc_r+0x20> 800a674: 4622 mov r2, r4 800a676: 6864 ldr r4, [r4, #4] 800a678: e7cc b.n 800a614 <_malloc_r+0x2c> 800a67a: 1cc4 adds r4, r0, #3 800a67c: f024 0403 bic.w r4, r4, #3 800a680: 42a0 cmp r0, r4 800a682: d0e3 beq.n 800a64c <_malloc_r+0x64> 800a684: 1a21 subs r1, r4, r0 800a686: 4630 mov r0, r6 800a688: f000 f808 bl 800a69c <_sbrk_r> 800a68c: 3001 adds r0, #1 800a68e: d1dd bne.n 800a64c <_malloc_r+0x64> 800a690: e7cf b.n 800a632 <_malloc_r+0x4a> 800a692: bf00 nop 800a694: 240013d8 .word 0x240013d8 800a698: 240013dc .word 0x240013dc 0800a69c <_sbrk_r>: 800a69c: b538 push {r3, r4, r5, lr} 800a69e: 4d06 ldr r5, [pc, #24] ; (800a6b8 <_sbrk_r+0x1c>) 800a6a0: 2300 movs r3, #0 800a6a2: 4604 mov r4, r0 800a6a4: 4608 mov r0, r1 800a6a6: 602b str r3, [r5, #0] 800a6a8: f7f6 fe78 bl 800139c <_sbrk> 800a6ac: 1c43 adds r3, r0, #1 800a6ae: d102 bne.n 800a6b6 <_sbrk_r+0x1a> 800a6b0: 682b ldr r3, [r5, #0] 800a6b2: b103 cbz r3, 800a6b6 <_sbrk_r+0x1a> 800a6b4: 6023 str r3, [r4, #0] 800a6b6: bd38 pop {r3, r4, r5, pc} 800a6b8: 24002d14 .word 0x24002d14 0800a6bc <_raise_r>: 800a6bc: 291f cmp r1, #31 800a6be: b538 push {r3, r4, r5, lr} 800a6c0: 4604 mov r4, r0 800a6c2: 460d mov r5, r1 800a6c4: d904 bls.n 800a6d0 <_raise_r+0x14> 800a6c6: 2316 movs r3, #22 800a6c8: 6003 str r3, [r0, #0] 800a6ca: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800a6ce: bd38 pop {r3, r4, r5, pc} 800a6d0: 6c42 ldr r2, [r0, #68] ; 0x44 800a6d2: b112 cbz r2, 800a6da <_raise_r+0x1e> 800a6d4: f852 3021 ldr.w r3, [r2, r1, lsl #2] 800a6d8: b94b cbnz r3, 800a6ee <_raise_r+0x32> 800a6da: 4620 mov r0, r4 800a6dc: f000 f830 bl 800a740 <_getpid_r> 800a6e0: 462a mov r2, r5 800a6e2: 4601 mov r1, r0 800a6e4: 4620 mov r0, r4 800a6e6: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800a6ea: f000 b817 b.w 800a71c <_kill_r> 800a6ee: 2b01 cmp r3, #1 800a6f0: d00a beq.n 800a708 <_raise_r+0x4c> 800a6f2: 1c59 adds r1, r3, #1 800a6f4: d103 bne.n 800a6fe <_raise_r+0x42> 800a6f6: 2316 movs r3, #22 800a6f8: 6003 str r3, [r0, #0] 800a6fa: 2001 movs r0, #1 800a6fc: e7e7 b.n 800a6ce <_raise_r+0x12> 800a6fe: 2400 movs r4, #0 800a700: f842 4025 str.w r4, [r2, r5, lsl #2] 800a704: 4628 mov r0, r5 800a706: 4798 blx r3 800a708: 2000 movs r0, #0 800a70a: e7e0 b.n 800a6ce <_raise_r+0x12> 0800a70c : 800a70c: 4b02 ldr r3, [pc, #8] ; (800a718 ) 800a70e: 4601 mov r1, r0 800a710: 6818 ldr r0, [r3, #0] 800a712: f7ff bfd3 b.w 800a6bc <_raise_r> 800a716: bf00 nop 800a718: 24000184 .word 0x24000184 0800a71c <_kill_r>: 800a71c: b538 push {r3, r4, r5, lr} 800a71e: 4d07 ldr r5, [pc, #28] ; (800a73c <_kill_r+0x20>) 800a720: 2300 movs r3, #0 800a722: 4604 mov r4, r0 800a724: 4608 mov r0, r1 800a726: 4611 mov r1, r2 800a728: 602b str r3, [r5, #0] 800a72a: f7f6 fdaf bl 800128c <_kill> 800a72e: 1c43 adds r3, r0, #1 800a730: d102 bne.n 800a738 <_kill_r+0x1c> 800a732: 682b ldr r3, [r5, #0] 800a734: b103 cbz r3, 800a738 <_kill_r+0x1c> 800a736: 6023 str r3, [r4, #0] 800a738: bd38 pop {r3, r4, r5, pc} 800a73a: bf00 nop 800a73c: 24002d14 .word 0x24002d14 0800a740 <_getpid_r>: 800a740: f7f6 bd9c b.w 800127c <_getpid> 0800a744 <__sread>: 800a744: b510 push {r4, lr} 800a746: 460c mov r4, r1 800a748: f9b1 100e ldrsh.w r1, [r1, #14] 800a74c: f000 f8a0 bl 800a890 <_read_r> 800a750: 2800 cmp r0, #0 800a752: bfab itete ge 800a754: 6d63 ldrge r3, [r4, #84] ; 0x54 800a756: 89a3 ldrhlt r3, [r4, #12] 800a758: 181b addge r3, r3, r0 800a75a: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 800a75e: bfac ite ge 800a760: 6563 strge r3, [r4, #84] ; 0x54 800a762: 81a3 strhlt r3, [r4, #12] 800a764: bd10 pop {r4, pc} 0800a766 <__swrite>: 800a766: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800a76a: 461f mov r7, r3 800a76c: 898b ldrh r3, [r1, #12] 800a76e: 05db lsls r3, r3, #23 800a770: 4605 mov r5, r0 800a772: 460c mov r4, r1 800a774: 4616 mov r6, r2 800a776: d505 bpl.n 800a784 <__swrite+0x1e> 800a778: f9b1 100e ldrsh.w r1, [r1, #14] 800a77c: 2302 movs r3, #2 800a77e: 2200 movs r2, #0 800a780: f000 f868 bl 800a854 <_lseek_r> 800a784: 89a3 ldrh r3, [r4, #12] 800a786: f9b4 100e ldrsh.w r1, [r4, #14] 800a78a: f423 5380 bic.w r3, r3, #4096 ; 0x1000 800a78e: 81a3 strh r3, [r4, #12] 800a790: 4632 mov r2, r6 800a792: 463b mov r3, r7 800a794: 4628 mov r0, r5 800a796: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800a79a: f000 b817 b.w 800a7cc <_write_r> 0800a79e <__sseek>: 800a79e: b510 push {r4, lr} 800a7a0: 460c mov r4, r1 800a7a2: f9b1 100e ldrsh.w r1, [r1, #14] 800a7a6: f000 f855 bl 800a854 <_lseek_r> 800a7aa: 1c43 adds r3, r0, #1 800a7ac: 89a3 ldrh r3, [r4, #12] 800a7ae: bf15 itete ne 800a7b0: 6560 strne r0, [r4, #84] ; 0x54 800a7b2: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 800a7b6: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 800a7ba: 81a3 strheq r3, [r4, #12] 800a7bc: bf18 it ne 800a7be: 81a3 strhne r3, [r4, #12] 800a7c0: bd10 pop {r4, pc} 0800a7c2 <__sclose>: 800a7c2: f9b1 100e ldrsh.w r1, [r1, #14] 800a7c6: f000 b813 b.w 800a7f0 <_close_r> ... 0800a7cc <_write_r>: 800a7cc: b538 push {r3, r4, r5, lr} 800a7ce: 4d07 ldr r5, [pc, #28] ; (800a7ec <_write_r+0x20>) 800a7d0: 4604 mov r4, r0 800a7d2: 4608 mov r0, r1 800a7d4: 4611 mov r1, r2 800a7d6: 2200 movs r2, #0 800a7d8: 602a str r2, [r5, #0] 800a7da: 461a mov r2, r3 800a7dc: f7f6 fd8d bl 80012fa <_write> 800a7e0: 1c43 adds r3, r0, #1 800a7e2: d102 bne.n 800a7ea <_write_r+0x1e> 800a7e4: 682b ldr r3, [r5, #0] 800a7e6: b103 cbz r3, 800a7ea <_write_r+0x1e> 800a7e8: 6023 str r3, [r4, #0] 800a7ea: bd38 pop {r3, r4, r5, pc} 800a7ec: 24002d14 .word 0x24002d14 0800a7f0 <_close_r>: 800a7f0: b538 push {r3, r4, r5, lr} 800a7f2: 4d06 ldr r5, [pc, #24] ; (800a80c <_close_r+0x1c>) 800a7f4: 2300 movs r3, #0 800a7f6: 4604 mov r4, r0 800a7f8: 4608 mov r0, r1 800a7fa: 602b str r3, [r5, #0] 800a7fc: f7f6 fd99 bl 8001332 <_close> 800a800: 1c43 adds r3, r0, #1 800a802: d102 bne.n 800a80a <_close_r+0x1a> 800a804: 682b ldr r3, [r5, #0] 800a806: b103 cbz r3, 800a80a <_close_r+0x1a> 800a808: 6023 str r3, [r4, #0] 800a80a: bd38 pop {r3, r4, r5, pc} 800a80c: 24002d14 .word 0x24002d14 0800a810 <_fstat_r>: 800a810: b538 push {r3, r4, r5, lr} 800a812: 4d07 ldr r5, [pc, #28] ; (800a830 <_fstat_r+0x20>) 800a814: 2300 movs r3, #0 800a816: 4604 mov r4, r0 800a818: 4608 mov r0, r1 800a81a: 4611 mov r1, r2 800a81c: 602b str r3, [r5, #0] 800a81e: f7f6 fd94 bl 800134a <_fstat> 800a822: 1c43 adds r3, r0, #1 800a824: d102 bne.n 800a82c <_fstat_r+0x1c> 800a826: 682b ldr r3, [r5, #0] 800a828: b103 cbz r3, 800a82c <_fstat_r+0x1c> 800a82a: 6023 str r3, [r4, #0] 800a82c: bd38 pop {r3, r4, r5, pc} 800a82e: bf00 nop 800a830: 24002d14 .word 0x24002d14 0800a834 <_isatty_r>: 800a834: b538 push {r3, r4, r5, lr} 800a836: 4d06 ldr r5, [pc, #24] ; (800a850 <_isatty_r+0x1c>) 800a838: 2300 movs r3, #0 800a83a: 4604 mov r4, r0 800a83c: 4608 mov r0, r1 800a83e: 602b str r3, [r5, #0] 800a840: f7f6 fd93 bl 800136a <_isatty> 800a844: 1c43 adds r3, r0, #1 800a846: d102 bne.n 800a84e <_isatty_r+0x1a> 800a848: 682b ldr r3, [r5, #0] 800a84a: b103 cbz r3, 800a84e <_isatty_r+0x1a> 800a84c: 6023 str r3, [r4, #0] 800a84e: bd38 pop {r3, r4, r5, pc} 800a850: 24002d14 .word 0x24002d14 0800a854 <_lseek_r>: 800a854: b538 push {r3, r4, r5, lr} 800a856: 4d07 ldr r5, [pc, #28] ; (800a874 <_lseek_r+0x20>) 800a858: 4604 mov r4, r0 800a85a: 4608 mov r0, r1 800a85c: 4611 mov r1, r2 800a85e: 2200 movs r2, #0 800a860: 602a str r2, [r5, #0] 800a862: 461a mov r2, r3 800a864: f7f6 fd8c bl 8001380 <_lseek> 800a868: 1c43 adds r3, r0, #1 800a86a: d102 bne.n 800a872 <_lseek_r+0x1e> 800a86c: 682b ldr r3, [r5, #0] 800a86e: b103 cbz r3, 800a872 <_lseek_r+0x1e> 800a870: 6023 str r3, [r4, #0] 800a872: bd38 pop {r3, r4, r5, pc} 800a874: 24002d14 .word 0x24002d14 0800a878 <__malloc_lock>: 800a878: 4801 ldr r0, [pc, #4] ; (800a880 <__malloc_lock+0x8>) 800a87a: f7ff bdff b.w 800a47c <__retarget_lock_acquire_recursive> 800a87e: bf00 nop 800a880: 24002d0c .word 0x24002d0c 0800a884 <__malloc_unlock>: 800a884: 4801 ldr r0, [pc, #4] ; (800a88c <__malloc_unlock+0x8>) 800a886: f7ff bdfa b.w 800a47e <__retarget_lock_release_recursive> 800a88a: bf00 nop 800a88c: 24002d0c .word 0x24002d0c 0800a890 <_read_r>: 800a890: b538 push {r3, r4, r5, lr} 800a892: 4d07 ldr r5, [pc, #28] ; (800a8b0 <_read_r+0x20>) 800a894: 4604 mov r4, r0 800a896: 4608 mov r0, r1 800a898: 4611 mov r1, r2 800a89a: 2200 movs r2, #0 800a89c: 602a str r2, [r5, #0] 800a89e: 461a mov r2, r3 800a8a0: f7f6 fd0e bl 80012c0 <_read> 800a8a4: 1c43 adds r3, r0, #1 800a8a6: d102 bne.n 800a8ae <_read_r+0x1e> 800a8a8: 682b ldr r3, [r5, #0] 800a8aa: b103 cbz r3, 800a8ae <_read_r+0x1e> 800a8ac: 6023 str r3, [r4, #0] 800a8ae: bd38 pop {r3, r4, r5, pc} 800a8b0: 24002d14 .word 0x24002d14 0800a8b4 <_init>: 800a8b4: b5f8 push {r3, r4, r5, r6, r7, lr} 800a8b6: bf00 nop 800a8b8: bcf8 pop {r3, r4, r5, r6, r7} 800a8ba: bc08 pop {r3} 800a8bc: 469e mov lr, r3 800a8be: 4770 bx lr 0800a8c0 <_fini>: 800a8c0: b5f8 push {r3, r4, r5, r6, r7, lr} 800a8c2: bf00 nop 800a8c4: bcf8 pop {r3, r4, r5, r6, r7} 800a8c6: bc08 pop {r3} 800a8c8: 469e mov lr, r3 800a8ca: 4770 bx lr