cc1200_spi_ripper.list 1006 KB

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  1. cc1200_spi_ripper.elf: file format elf32-littlearm
  2. Sections:
  3. Idx Name Size VMA LMA File off Algn
  4. 0 .isr_vector 000002cc 08000000 08000000 00010000 2**0
  5. CONTENTS, ALLOC, LOAD, READONLY, DATA
  6. 1 .text 0000a5fc 080002d0 080002d0 000102d0 2**4
  7. CONTENTS, ALLOC, LOAD, READONLY, CODE
  8. 2 .rodata 00000228 0800a8cc 0800a8cc 0001a8cc 2**2
  9. CONTENTS, ALLOC, LOAD, READONLY, DATA
  10. 3 .init_array 00000004 0800aaf4 0800aaf4 0001aaf4 2**2
  11. CONTENTS, ALLOC, LOAD, DATA
  12. 4 .fini_array 00000004 0800aaf8 0800aaf8 0001aaf8 2**2
  13. CONTENTS, ALLOC, LOAD, DATA
  14. 5 .data 000001e8 24000000 0800aafc 00020000 2**2
  15. CONTENTS, ALLOC, LOAD, DATA
  16. 6 .bss 00002b30 240001e8 0800ace4 000201e8 2**2
  17. ALLOC
  18. 7 ._user_heap_stack 00000600 24002d18 0800ace4 00022d18 2**0
  19. ALLOC
  20. 8 .ARM.attributes 0000002e 00000000 00000000 000201e8 2**0
  21. CONTENTS, READONLY
  22. 9 .debug_info 0002d6e4 00000000 00000000 00020216 2**0
  23. CONTENTS, READONLY, DEBUGGING, OCTETS
  24. 10 .debug_abbrev 000052e3 00000000 00000000 0004d8fa 2**0
  25. CONTENTS, READONLY, DEBUGGING, OCTETS
  26. 11 .debug_aranges 00001740 00000000 00000000 00052be0 2**3
  27. CONTENTS, READONLY, DEBUGGING, OCTETS
  28. 12 .debug_ranges 00001578 00000000 00000000 00054320 2**3
  29. CONTENTS, READONLY, DEBUGGING, OCTETS
  30. 13 .debug_macro 0003a87c 00000000 00000000 00055898 2**0
  31. CONTENTS, READONLY, DEBUGGING, OCTETS
  32. 14 .debug_line 0001cbe9 00000000 00000000 00090114 2**0
  33. CONTENTS, READONLY, DEBUGGING, OCTETS
  34. 15 .debug_str 001622b1 00000000 00000000 000accfd 2**0
  35. CONTENTS, READONLY, DEBUGGING, OCTETS
  36. 16 .comment 00000053 00000000 00000000 0020efae 2**0
  37. CONTENTS, READONLY
  38. 17 .debug_frame 00006a14 00000000 00000000 0020f004 2**2
  39. CONTENTS, READONLY, DEBUGGING, OCTETS
  40. Disassembly of section .text:
  41. 080002d0 <__do_global_dtors_aux>:
  42. 80002d0: b510 push {r4, lr}
  43. 80002d2: 4c05 ldr r4, [pc, #20] ; (80002e8 <__do_global_dtors_aux+0x18>)
  44. 80002d4: 7823 ldrb r3, [r4, #0]
  45. 80002d6: b933 cbnz r3, 80002e6 <__do_global_dtors_aux+0x16>
  46. 80002d8: 4b04 ldr r3, [pc, #16] ; (80002ec <__do_global_dtors_aux+0x1c>)
  47. 80002da: b113 cbz r3, 80002e2 <__do_global_dtors_aux+0x12>
  48. 80002dc: 4804 ldr r0, [pc, #16] ; (80002f0 <__do_global_dtors_aux+0x20>)
  49. 80002de: f3af 8000 nop.w
  50. 80002e2: 2301 movs r3, #1
  51. 80002e4: 7023 strb r3, [r4, #0]
  52. 80002e6: bd10 pop {r4, pc}
  53. 80002e8: 240001e8 .word 0x240001e8
  54. 80002ec: 00000000 .word 0x00000000
  55. 80002f0: 0800a8b4 .word 0x0800a8b4
  56. 080002f4 <frame_dummy>:
  57. 80002f4: b508 push {r3, lr}
  58. 80002f6: 4b03 ldr r3, [pc, #12] ; (8000304 <frame_dummy+0x10>)
  59. 80002f8: b11b cbz r3, 8000302 <frame_dummy+0xe>
  60. 80002fa: 4903 ldr r1, [pc, #12] ; (8000308 <frame_dummy+0x14>)
  61. 80002fc: 4803 ldr r0, [pc, #12] ; (800030c <frame_dummy+0x18>)
  62. 80002fe: f3af 8000 nop.w
  63. 8000302: bd08 pop {r3, pc}
  64. 8000304: 00000000 .word 0x00000000
  65. 8000308: 240001ec .word 0x240001ec
  66. 800030c: 0800a8b4 .word 0x0800a8b4
  67. 08000310 <memchr>:
  68. 8000310: f001 01ff and.w r1, r1, #255 ; 0xff
  69. 8000314: 2a10 cmp r2, #16
  70. 8000316: db2b blt.n 8000370 <memchr+0x60>
  71. 8000318: f010 0f07 tst.w r0, #7
  72. 800031c: d008 beq.n 8000330 <memchr+0x20>
  73. 800031e: f810 3b01 ldrb.w r3, [r0], #1
  74. 8000322: 3a01 subs r2, #1
  75. 8000324: 428b cmp r3, r1
  76. 8000326: d02d beq.n 8000384 <memchr+0x74>
  77. 8000328: f010 0f07 tst.w r0, #7
  78. 800032c: b342 cbz r2, 8000380 <memchr+0x70>
  79. 800032e: d1f6 bne.n 800031e <memchr+0xe>
  80. 8000330: b4f0 push {r4, r5, r6, r7}
  81. 8000332: ea41 2101 orr.w r1, r1, r1, lsl #8
  82. 8000336: ea41 4101 orr.w r1, r1, r1, lsl #16
  83. 800033a: f022 0407 bic.w r4, r2, #7
  84. 800033e: f07f 0700 mvns.w r7, #0
  85. 8000342: 2300 movs r3, #0
  86. 8000344: e8f0 5602 ldrd r5, r6, [r0], #8
  87. 8000348: 3c08 subs r4, #8
  88. 800034a: ea85 0501 eor.w r5, r5, r1
  89. 800034e: ea86 0601 eor.w r6, r6, r1
  90. 8000352: fa85 f547 uadd8 r5, r5, r7
  91. 8000356: faa3 f587 sel r5, r3, r7
  92. 800035a: fa86 f647 uadd8 r6, r6, r7
  93. 800035e: faa5 f687 sel r6, r5, r7
  94. 8000362: b98e cbnz r6, 8000388 <memchr+0x78>
  95. 8000364: d1ee bne.n 8000344 <memchr+0x34>
  96. 8000366: bcf0 pop {r4, r5, r6, r7}
  97. 8000368: f001 01ff and.w r1, r1, #255 ; 0xff
  98. 800036c: f002 0207 and.w r2, r2, #7
  99. 8000370: b132 cbz r2, 8000380 <memchr+0x70>
  100. 8000372: f810 3b01 ldrb.w r3, [r0], #1
  101. 8000376: 3a01 subs r2, #1
  102. 8000378: ea83 0301 eor.w r3, r3, r1
  103. 800037c: b113 cbz r3, 8000384 <memchr+0x74>
  104. 800037e: d1f8 bne.n 8000372 <memchr+0x62>
  105. 8000380: 2000 movs r0, #0
  106. 8000382: 4770 bx lr
  107. 8000384: 3801 subs r0, #1
  108. 8000386: 4770 bx lr
  109. 8000388: 2d00 cmp r5, #0
  110. 800038a: bf06 itte eq
  111. 800038c: 4635 moveq r5, r6
  112. 800038e: 3803 subeq r0, #3
  113. 8000390: 3807 subne r0, #7
  114. 8000392: f015 0f01 tst.w r5, #1
  115. 8000396: d107 bne.n 80003a8 <memchr+0x98>
  116. 8000398: 3001 adds r0, #1
  117. 800039a: f415 7f80 tst.w r5, #256 ; 0x100
  118. 800039e: bf02 ittt eq
  119. 80003a0: 3001 addeq r0, #1
  120. 80003a2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000
  121. 80003a6: 3001 addeq r0, #1
  122. 80003a8: bcf0 pop {r4, r5, r6, r7}
  123. 80003aa: 3801 subs r0, #1
  124. 80003ac: 4770 bx lr
  125. 80003ae: bf00 nop
  126. 080003b0 <LL_SPI_Enable>:
  127. * @rmtoll CR1 SPE LL_SPI_Enable
  128. * @param SPIx SPI Instance
  129. * @retval None
  130. */
  131. __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
  132. {
  133. 80003b0: b480 push {r7}
  134. 80003b2: b083 sub sp, #12
  135. 80003b4: af00 add r7, sp, #0
  136. 80003b6: 6078 str r0, [r7, #4]
  137. SET_BIT(SPIx->CR1, SPI_CR1_SPE);
  138. 80003b8: 687b ldr r3, [r7, #4]
  139. 80003ba: 681b ldr r3, [r3, #0]
  140. 80003bc: f043 0201 orr.w r2, r3, #1
  141. 80003c0: 687b ldr r3, [r7, #4]
  142. 80003c2: 601a str r2, [r3, #0]
  143. }
  144. 80003c4: bf00 nop
  145. 80003c6: 370c adds r7, #12
  146. 80003c8: 46bd mov sp, r7
  147. 80003ca: f85d 7b04 ldr.w r7, [sp], #4
  148. 80003ce: 4770 bx lr
  149. 080003d0 <LL_SPI_Disable>:
  150. * @rmtoll CR1 SPE LL_SPI_Disable
  151. * @param SPIx SPI Instance
  152. * @retval None
  153. */
  154. __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
  155. {
  156. 80003d0: b480 push {r7}
  157. 80003d2: b083 sub sp, #12
  158. 80003d4: af00 add r7, sp, #0
  159. 80003d6: 6078 str r0, [r7, #4]
  160. CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
  161. 80003d8: 687b ldr r3, [r7, #4]
  162. 80003da: 681b ldr r3, [r3, #0]
  163. 80003dc: f023 0201 bic.w r2, r3, #1
  164. 80003e0: 687b ldr r3, [r7, #4]
  165. 80003e2: 601a str r2, [r3, #0]
  166. }
  167. 80003e4: bf00 nop
  168. 80003e6: 370c adds r7, #12
  169. 80003e8: 46bd mov sp, r7
  170. 80003ea: f85d 7b04 ldr.w r7, [sp], #4
  171. 80003ee: 4770 bx lr
  172. 080003f0 <LL_SPI_SetTransferSize>:
  173. * @param SPIx SPI Instance
  174. * @param Count 0..0xFFFF
  175. * @retval None
  176. */
  177. __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
  178. {
  179. 80003f0: b480 push {r7}
  180. 80003f2: b083 sub sp, #12
  181. 80003f4: af00 add r7, sp, #0
  182. 80003f6: 6078 str r0, [r7, #4]
  183. 80003f8: 6039 str r1, [r7, #0]
  184. MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
  185. 80003fa: 687b ldr r3, [r7, #4]
  186. 80003fc: 685a ldr r2, [r3, #4]
  187. 80003fe: 4b06 ldr r3, [pc, #24] ; (8000418 <LL_SPI_SetTransferSize+0x28>)
  188. 8000400: 4013 ands r3, r2
  189. 8000402: 683a ldr r2, [r7, #0]
  190. 8000404: 431a orrs r2, r3
  191. 8000406: 687b ldr r3, [r7, #4]
  192. 8000408: 605a str r2, [r3, #4]
  193. }
  194. 800040a: bf00 nop
  195. 800040c: 370c adds r7, #12
  196. 800040e: 46bd mov sp, r7
  197. 8000410: f85d 7b04 ldr.w r7, [sp], #4
  198. 8000414: 4770 bx lr
  199. 8000416: bf00 nop
  200. 8000418: ffff0000 .word 0xffff0000
  201. 0800041c <LL_SPI_StartMasterTransfer>:
  202. * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
  203. * @param SPIx SPI Instance
  204. * @retval None
  205. */
  206. __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
  207. {
  208. 800041c: b480 push {r7}
  209. 800041e: b083 sub sp, #12
  210. 8000420: af00 add r7, sp, #0
  211. 8000422: 6078 str r0, [r7, #4]
  212. SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
  213. 8000424: 687b ldr r3, [r7, #4]
  214. 8000426: 681b ldr r3, [r3, #0]
  215. 8000428: f443 7200 orr.w r2, r3, #512 ; 0x200
  216. 800042c: 687b ldr r3, [r7, #4]
  217. 800042e: 601a str r2, [r3, #0]
  218. }
  219. 8000430: bf00 nop
  220. 8000432: 370c adds r7, #12
  221. 8000434: 46bd mov sp, r7
  222. 8000436: f85d 7b04 ldr.w r7, [sp], #4
  223. 800043a: 4770 bx lr
  224. 0800043c <LL_SPI_IsActiveFlag_RXP>:
  225. * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
  226. * @param SPIx SPI Instance
  227. * @retval State of bit (1 or 0)
  228. */
  229. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
  230. {
  231. 800043c: b480 push {r7}
  232. 800043e: b083 sub sp, #12
  233. 8000440: af00 add r7, sp, #0
  234. 8000442: 6078 str r0, [r7, #4]
  235. return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
  236. 8000444: 687b ldr r3, [r7, #4]
  237. 8000446: 695b ldr r3, [r3, #20]
  238. 8000448: f003 0301 and.w r3, r3, #1
  239. 800044c: 2b01 cmp r3, #1
  240. 800044e: d101 bne.n 8000454 <LL_SPI_IsActiveFlag_RXP+0x18>
  241. 8000450: 2301 movs r3, #1
  242. 8000452: e000 b.n 8000456 <LL_SPI_IsActiveFlag_RXP+0x1a>
  243. 8000454: 2300 movs r3, #0
  244. }
  245. 8000456: 4618 mov r0, r3
  246. 8000458: 370c adds r7, #12
  247. 800045a: 46bd mov sp, r7
  248. 800045c: f85d 7b04 ldr.w r7, [sp], #4
  249. 8000460: 4770 bx lr
  250. 08000462 <LL_SPI_IsActiveFlag_EOT>:
  251. * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
  252. * @param SPIx SPI Instance
  253. * @retval State of bit (1 or 0).
  254. */
  255. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
  256. {
  257. 8000462: b480 push {r7}
  258. 8000464: b083 sub sp, #12
  259. 8000466: af00 add r7, sp, #0
  260. 8000468: 6078 str r0, [r7, #4]
  261. return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
  262. 800046a: 687b ldr r3, [r7, #4]
  263. 800046c: 695b ldr r3, [r3, #20]
  264. 800046e: f003 0308 and.w r3, r3, #8
  265. 8000472: 2b08 cmp r3, #8
  266. 8000474: d101 bne.n 800047a <LL_SPI_IsActiveFlag_EOT+0x18>
  267. 8000476: 2301 movs r3, #1
  268. 8000478: e000 b.n 800047c <LL_SPI_IsActiveFlag_EOT+0x1a>
  269. 800047a: 2300 movs r3, #0
  270. }
  271. 800047c: 4618 mov r0, r3
  272. 800047e: 370c adds r7, #12
  273. 8000480: 46bd mov sp, r7
  274. 8000482: f85d 7b04 ldr.w r7, [sp], #4
  275. 8000486: 4770 bx lr
  276. 08000488 <LL_SPI_ReceiveData8>:
  277. * @rmtoll RXDR . LL_SPI_ReceiveData8
  278. * @param SPIx SPI Instance
  279. * @retval 0..0xFF
  280. */
  281. __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
  282. {
  283. 8000488: b480 push {r7}
  284. 800048a: b083 sub sp, #12
  285. 800048c: af00 add r7, sp, #0
  286. 800048e: 6078 str r0, [r7, #4]
  287. return (*((__IO uint8_t *)&SPIx->RXDR));
  288. 8000490: 687b ldr r3, [r7, #4]
  289. 8000492: 3330 adds r3, #48 ; 0x30
  290. 8000494: 781b ldrb r3, [r3, #0]
  291. 8000496: b2db uxtb r3, r3
  292. }
  293. 8000498: 4618 mov r0, r3
  294. 800049a: 370c adds r7, #12
  295. 800049c: 46bd mov sp, r7
  296. 800049e: f85d 7b04 ldr.w r7, [sp], #4
  297. 80004a2: 4770 bx lr
  298. 080004a4 <LL_SPI_TransmitData8>:
  299. * @param SPIx SPI Instance
  300. * @param TxData 0..0xFF
  301. * @retval None
  302. */
  303. __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
  304. {
  305. 80004a4: b480 push {r7}
  306. 80004a6: b083 sub sp, #12
  307. 80004a8: af00 add r7, sp, #0
  308. 80004aa: 6078 str r0, [r7, #4]
  309. 80004ac: 460b mov r3, r1
  310. 80004ae: 70fb strb r3, [r7, #3]
  311. *((__IO uint8_t *)&SPIx->TXDR) = TxData;
  312. 80004b0: 687b ldr r3, [r7, #4]
  313. 80004b2: 3320 adds r3, #32
  314. 80004b4: 78fa ldrb r2, [r7, #3]
  315. 80004b6: 701a strb r2, [r3, #0]
  316. }
  317. 80004b8: bf00 nop
  318. 80004ba: 370c adds r7, #12
  319. 80004bc: 46bd mov sp, r7
  320. 80004be: f85d 7b04 ldr.w r7, [sp], #4
  321. 80004c2: 4770 bx lr
  322. 080004c4 <LL_SPI_TransmitData16>:
  323. * @param SPIx SPI Instance
  324. * @param TxData 0..0xFFFF
  325. * @retval None
  326. */
  327. __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
  328. {
  329. 80004c4: b480 push {r7}
  330. 80004c6: b085 sub sp, #20
  331. 80004c8: af00 add r7, sp, #0
  332. 80004ca: 6078 str r0, [r7, #4]
  333. 80004cc: 460b mov r3, r1
  334. 80004ce: 807b strh r3, [r7, #2]
  335. #if defined (__GNUC__)
  336. __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
  337. 80004d0: 687b ldr r3, [r7, #4]
  338. 80004d2: 3320 adds r3, #32
  339. 80004d4: 60fb str r3, [r7, #12]
  340. *spitxdr = TxData;
  341. 80004d6: 68fb ldr r3, [r7, #12]
  342. 80004d8: 887a ldrh r2, [r7, #2]
  343. 80004da: 801a strh r2, [r3, #0]
  344. #else
  345. SPIx->TXDR = TxData;
  346. #endif /* __GNUC__ */
  347. }
  348. 80004dc: bf00 nop
  349. 80004de: 3714 adds r7, #20
  350. 80004e0: 46bd mov sp, r7
  351. 80004e2: f85d 7b04 ldr.w r7, [sp], #4
  352. 80004e6: 4770 bx lr
  353. 080004e8 <LL_SPI_TransmitData32>:
  354. * @param SPIx SPI Instance
  355. * @param TxData 0..0xFFFFFFFF
  356. * @retval None
  357. */
  358. __STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
  359. {
  360. 80004e8: b480 push {r7}
  361. 80004ea: b083 sub sp, #12
  362. 80004ec: af00 add r7, sp, #0
  363. 80004ee: 6078 str r0, [r7, #4]
  364. 80004f0: 6039 str r1, [r7, #0]
  365. *((__IO uint32_t *)&SPIx->TXDR) = TxData;
  366. 80004f2: 687b ldr r3, [r7, #4]
  367. 80004f4: 683a ldr r2, [r7, #0]
  368. 80004f6: 621a str r2, [r3, #32]
  369. }
  370. 80004f8: bf00 nop
  371. 80004fa: 370c adds r7, #12
  372. 80004fc: 46bd mov sp, r7
  373. 80004fe: f85d 7b04 ldr.w r7, [sp], #4
  374. 8000502: 4770 bx lr
  375. 08000504 <SPI1_TransmitBytes>:
  376. #define CC1200_READ_BIT 0b10000000
  377. #define CC1200_BURST_BIT 0b01000000
  378. void SPI1_TransmitBytes(uint8_t *p_buf, uint8_t len)
  379. {
  380. 8000504: b580 push {r7, lr}
  381. 8000506: b082 sub sp, #8
  382. 8000508: af00 add r7, sp, #0
  383. 800050a: 6078 str r0, [r7, #4]
  384. 800050c: 460b mov r3, r1
  385. 800050e: 70fb strb r3, [r7, #3]
  386. LL_SPI_SetTransferSize(SPI1, len);
  387. 8000510: 78fb ldrb r3, [r7, #3]
  388. 8000512: 4619 mov r1, r3
  389. 8000514: 481f ldr r0, [pc, #124] ; (8000594 <SPI1_TransmitBytes+0x90>)
  390. 8000516: f7ff ff6b bl 80003f0 <LL_SPI_SetTransferSize>
  391. LL_SPI_Enable(SPI1);
  392. 800051a: 481e ldr r0, [pc, #120] ; (8000594 <SPI1_TransmitBytes+0x90>)
  393. 800051c: f7ff ff48 bl 80003b0 <LL_SPI_Enable>
  394. LL_SPI_StartMasterTransfer(SPI1);
  395. 8000520: 481c ldr r0, [pc, #112] ; (8000594 <SPI1_TransmitBytes+0x90>)
  396. 8000522: f7ff ff7b bl 800041c <LL_SPI_StartMasterTransfer>
  397. switch(len)
  398. 8000526: 78fb ldrb r3, [r7, #3]
  399. 8000528: 2b03 cmp r3, #3
  400. 800052a: d014 beq.n 8000556 <SPI1_TransmitBytes+0x52>
  401. 800052c: 2b03 cmp r3, #3
  402. 800052e: dc19 bgt.n 8000564 <SPI1_TransmitBytes+0x60>
  403. 8000530: 2b01 cmp r3, #1
  404. 8000532: d002 beq.n 800053a <SPI1_TransmitBytes+0x36>
  405. 8000534: 2b02 cmp r3, #2
  406. 8000536: d007 beq.n 8000548 <SPI1_TransmitBytes+0x44>
  407. 8000538: e014 b.n 8000564 <SPI1_TransmitBytes+0x60>
  408. {
  409. case 1:
  410. LL_SPI_TransmitData8(SPI1, *p_buf);
  411. 800053a: 687b ldr r3, [r7, #4]
  412. 800053c: 781b ldrb r3, [r3, #0]
  413. 800053e: 4619 mov r1, r3
  414. 8000540: 4814 ldr r0, [pc, #80] ; (8000594 <SPI1_TransmitBytes+0x90>)
  415. 8000542: f7ff ffaf bl 80004a4 <LL_SPI_TransmitData8>
  416. break;
  417. 8000546: e013 b.n 8000570 <SPI1_TransmitBytes+0x6c>
  418. case 2:
  419. LL_SPI_TransmitData16(SPI1, *(uint16_t *)p_buf);
  420. 8000548: 687b ldr r3, [r7, #4]
  421. 800054a: 881b ldrh r3, [r3, #0]
  422. 800054c: 4619 mov r1, r3
  423. 800054e: 4811 ldr r0, [pc, #68] ; (8000594 <SPI1_TransmitBytes+0x90>)
  424. 8000550: f7ff ffb8 bl 80004c4 <LL_SPI_TransmitData16>
  425. break;
  426. 8000554: e00c b.n 8000570 <SPI1_TransmitBytes+0x6c>
  427. case 3:
  428. LL_SPI_TransmitData32(SPI1, *(uint32_t *)p_buf);
  429. 8000556: 687b ldr r3, [r7, #4]
  430. 8000558: 681b ldr r3, [r3, #0]
  431. 800055a: 4619 mov r1, r3
  432. 800055c: 480d ldr r0, [pc, #52] ; (8000594 <SPI1_TransmitBytes+0x90>)
  433. 800055e: f7ff ffc3 bl 80004e8 <LL_SPI_TransmitData32>
  434. break;
  435. 8000562: e005 b.n 8000570 <SPI1_TransmitBytes+0x6c>
  436. default:
  437. assert(0);
  438. 8000564: 4b0c ldr r3, [pc, #48] ; (8000598 <SPI1_TransmitBytes+0x94>)
  439. 8000566: 4a0d ldr r2, [pc, #52] ; (800059c <SPI1_TransmitBytes+0x98>)
  440. 8000568: 212f movs r1, #47 ; 0x2f
  441. 800056a: 480d ldr r0, [pc, #52] ; (80005a0 <SPI1_TransmitBytes+0x9c>)
  442. 800056c: f009 f9b6 bl 80098dc <__assert_func>
  443. }
  444. // Wait until the transmission is complete
  445. while( LL_SPI_IsActiveFlag_EOT(SPI1) == 0);
  446. 8000570: bf00 nop
  447. 8000572: 4808 ldr r0, [pc, #32] ; (8000594 <SPI1_TransmitBytes+0x90>)
  448. 8000574: f7ff ff75 bl 8000462 <LL_SPI_IsActiveFlag_EOT>
  449. 8000578: 4603 mov r3, r0
  450. 800057a: 2b00 cmp r3, #0
  451. 800057c: d0f9 beq.n 8000572 <SPI1_TransmitBytes+0x6e>
  452. SPI1->IFCR = UINT32_MAX;
  453. 800057e: 4b05 ldr r3, [pc, #20] ; (8000594 <SPI1_TransmitBytes+0x90>)
  454. 8000580: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
  455. 8000584: 619a str r2, [r3, #24]
  456. LL_SPI_Disable(SPI1);
  457. 8000586: 4803 ldr r0, [pc, #12] ; (8000594 <SPI1_TransmitBytes+0x90>)
  458. 8000588: f7ff ff22 bl 80003d0 <LL_SPI_Disable>
  459. }
  460. 800058c: bf00 nop
  461. 800058e: 3708 adds r7, #8
  462. 8000590: 46bd mov sp, r7
  463. 8000592: bd80 pop {r7, pc}
  464. 8000594: 40013000 .word 0x40013000
  465. 8000598: 0800a8cc .word 0x0800a8cc
  466. 800059c: 0800a930 .word 0x0800a930
  467. 80005a0: 0800a8d0 .word 0x0800a8d0
  468. 080005a4 <SPI1_ReceiveByte>:
  469. uint8_t SPI1_ReceiveByte(void)
  470. {
  471. 80005a4: b580 push {r7, lr}
  472. 80005a6: b082 sub sp, #8
  473. 80005a8: af00 add r7, sp, #0
  474. uint8_t rxByte;
  475. LL_SPI_SetTransferSize(SPI1, 1);
  476. 80005aa: 2101 movs r1, #1
  477. 80005ac: 4815 ldr r0, [pc, #84] ; (8000604 <SPI1_ReceiveByte+0x60>)
  478. 80005ae: f7ff ff1f bl 80003f0 <LL_SPI_SetTransferSize>
  479. LL_SPI_Enable(SPI1);
  480. 80005b2: 4814 ldr r0, [pc, #80] ; (8000604 <SPI1_ReceiveByte+0x60>)
  481. 80005b4: f7ff fefc bl 80003b0 <LL_SPI_Enable>
  482. LL_SPI_StartMasterTransfer(SPI1);
  483. 80005b8: 4812 ldr r0, [pc, #72] ; (8000604 <SPI1_ReceiveByte+0x60>)
  484. 80005ba: f7ff ff2f bl 800041c <LL_SPI_StartMasterTransfer>
  485. LL_SPI_TransmitData8(SPI1, 0);
  486. 80005be: 2100 movs r1, #0
  487. 80005c0: 4810 ldr r0, [pc, #64] ; (8000604 <SPI1_ReceiveByte+0x60>)
  488. 80005c2: f7ff ff6f bl 80004a4 <LL_SPI_TransmitData8>
  489. while (LL_SPI_IsActiveFlag_RXP(SPI1) == 0);
  490. 80005c6: bf00 nop
  491. 80005c8: 480e ldr r0, [pc, #56] ; (8000604 <SPI1_ReceiveByte+0x60>)
  492. 80005ca: f7ff ff37 bl 800043c <LL_SPI_IsActiveFlag_RXP>
  493. 80005ce: 4603 mov r3, r0
  494. 80005d0: 2b00 cmp r3, #0
  495. 80005d2: d0f9 beq.n 80005c8 <SPI1_ReceiveByte+0x24>
  496. rxByte = LL_SPI_ReceiveData8(SPI1);
  497. 80005d4: 480b ldr r0, [pc, #44] ; (8000604 <SPI1_ReceiveByte+0x60>)
  498. 80005d6: f7ff ff57 bl 8000488 <LL_SPI_ReceiveData8>
  499. 80005da: 4603 mov r3, r0
  500. 80005dc: 71fb strb r3, [r7, #7]
  501. // Wait until the transmission is complete
  502. while( LL_SPI_IsActiveFlag_EOT(SPI1) == 0);
  503. 80005de: bf00 nop
  504. 80005e0: 4808 ldr r0, [pc, #32] ; (8000604 <SPI1_ReceiveByte+0x60>)
  505. 80005e2: f7ff ff3e bl 8000462 <LL_SPI_IsActiveFlag_EOT>
  506. 80005e6: 4603 mov r3, r0
  507. 80005e8: 2b00 cmp r3, #0
  508. 80005ea: d0f9 beq.n 80005e0 <SPI1_ReceiveByte+0x3c>
  509. SPI1->IFCR = UINT32_MAX;
  510. 80005ec: 4b05 ldr r3, [pc, #20] ; (8000604 <SPI1_ReceiveByte+0x60>)
  511. 80005ee: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
  512. 80005f2: 619a str r2, [r3, #24]
  513. LL_SPI_Disable(SPI1);
  514. 80005f4: 4803 ldr r0, [pc, #12] ; (8000604 <SPI1_ReceiveByte+0x60>)
  515. 80005f6: f7ff feeb bl 80003d0 <LL_SPI_Disable>
  516. return rxByte;
  517. 80005fa: 79fb ldrb r3, [r7, #7]
  518. }
  519. 80005fc: 4618 mov r0, r3
  520. 80005fe: 3708 adds r7, #8
  521. 8000600: 46bd mov sp, r7
  522. 8000602: bd80 pop {r7, pc}
  523. 8000604: 40013000 .word 0x40013000
  524. 08000608 <SPI1_TransmitReceive>:
  525. uint8_t SPI1_TransmitReceive(uint8_t *p_buf, uint8_t len)
  526. {
  527. 8000608: b580 push {r7, lr}
  528. 800060a: b082 sub sp, #8
  529. 800060c: af00 add r7, sp, #0
  530. 800060e: 6078 str r0, [r7, #4]
  531. 8000610: 460b mov r3, r1
  532. 8000612: 70fb strb r3, [r7, #3]
  533. SPI1_TransmitBytes(p_buf, len);
  534. 8000614: 78fb ldrb r3, [r7, #3]
  535. 8000616: 4619 mov r1, r3
  536. 8000618: 6878 ldr r0, [r7, #4]
  537. 800061a: f7ff ff73 bl 8000504 <SPI1_TransmitBytes>
  538. return SPI1_ReceiveByte();
  539. 800061e: f7ff ffc1 bl 80005a4 <SPI1_ReceiveByte>
  540. 8000622: 4603 mov r3, r0
  541. }
  542. 8000624: 4618 mov r0, r3
  543. 8000626: 3708 adds r7, #8
  544. 8000628: 46bd mov sp, r7
  545. 800062a: bd80 pop {r7, pc}
  546. 0800062c <cc1200_spi_write_byte>:
  547. // TODO: Fix to use HAL.
  548. static void cc1200_spi_write_byte(uint16_t addr, uint8_t data)
  549. {
  550. 800062c: b580 push {r7, lr}
  551. 800062e: b084 sub sp, #16
  552. 8000630: af00 add r7, sp, #0
  553. 8000632: 4603 mov r3, r0
  554. 8000634: 460a mov r2, r1
  555. 8000636: 80fb strh r3, [r7, #6]
  556. 8000638: 4613 mov r3, r2
  557. 800063a: 717b strb r3, [r7, #5]
  558. // set the data field
  559. HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 0);
  560. 800063c: 2200 movs r2, #0
  561. 800063e: 2140 movs r1, #64 ; 0x40
  562. 8000640: 4815 ldr r0, [pc, #84] ; (8000698 <cc1200_spi_write_byte+0x6c>)
  563. 8000642: f001 faf1 bl 8001c28 <HAL_GPIO_WritePin>
  564. if ((addr & 0xFF00) != 0) // send data with extended address in command field
  565. 8000646: 88fb ldrh r3, [r7, #6]
  566. 8000648: f403 437f and.w r3, r3, #65280 ; 0xff00
  567. 800064c: 2b00 cmp r3, #0
  568. 800064e: d00f beq.n 8000670 <cc1200_spi_write_byte+0x44>
  569. {
  570. txBuf[0] = ((uint8_t *)&addr)[1];
  571. 8000650: 79fb ldrb r3, [r7, #7]
  572. 8000652: 733b strb r3, [r7, #12]
  573. txBuf[1] = ((uint8_t *)&addr)[0];
  574. 8000654: 1dbb adds r3, r7, #6
  575. 8000656: 781b ldrb r3, [r3, #0]
  576. 8000658: 737b strb r3, [r7, #13]
  577. txBuf[0] |= CC1200_WRITE_BIT;
  578. 800065a: 7b3b ldrb r3, [r7, #12]
  579. 800065c: 733b strb r3, [r7, #12]
  580. txBuf[2] = data;
  581. 800065e: 797b ldrb r3, [r7, #5]
  582. 8000660: 73bb strb r3, [r7, #14]
  583. SPI1_TransmitBytes(txBuf, 3);
  584. 8000662: f107 030c add.w r3, r7, #12
  585. 8000666: 2103 movs r1, #3
  586. 8000668: 4618 mov r0, r3
  587. 800066a: f7ff ff4b bl 8000504 <SPI1_TransmitBytes>
  588. 800066e: e00a b.n 8000686 <cc1200_spi_write_byte+0x5a>
  589. }
  590. else
  591. {
  592. // correctly configure the addr field.
  593. txBuf[0] = (uint8_t)addr | CC1200_WRITE_BIT;
  594. 8000670: 88fb ldrh r3, [r7, #6]
  595. 8000672: b2db uxtb r3, r3
  596. 8000674: 733b strb r3, [r7, #12]
  597. txBuf[1] = data;
  598. 8000676: 797b ldrb r3, [r7, #5]
  599. 8000678: 737b strb r3, [r7, #13]
  600. SPI1_TransmitBytes(txBuf, 2);
  601. 800067a: f107 030c add.w r3, r7, #12
  602. 800067e: 2102 movs r1, #2
  603. 8000680: 4618 mov r0, r3
  604. 8000682: f7ff ff3f bl 8000504 <SPI1_TransmitBytes>
  605. }
  606. HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 1);
  607. 8000686: 2201 movs r2, #1
  608. 8000688: 2140 movs r1, #64 ; 0x40
  609. 800068a: 4803 ldr r0, [pc, #12] ; (8000698 <cc1200_spi_write_byte+0x6c>)
  610. 800068c: f001 facc bl 8001c28 <HAL_GPIO_WritePin>
  611. }
  612. 8000690: bf00 nop
  613. 8000692: 3710 adds r7, #16
  614. 8000694: 46bd mov sp, r7
  615. 8000696: bd80 pop {r7, pc}
  616. 8000698: 58020800 .word 0x58020800
  617. 0800069c <cc1200_spi_read_byte>:
  618. // ESP_ERROR_CHECK(ret);
  619. //}
  620. // TODO: Fix to use HAL.
  621. static void cc1200_spi_read_byte(uint16_t addr, uint8_t* data)
  622. {
  623. 800069c: b580 push {r7, lr}
  624. 800069e: b084 sub sp, #16
  625. 80006a0: af00 add r7, sp, #0
  626. 80006a2: 4603 mov r3, r0
  627. 80006a4: 6039 str r1, [r7, #0]
  628. 80006a6: 80fb strh r3, [r7, #6]
  629. uint8_t rxBuf[3];
  630. uint8_t txBuf[3];
  631. // correctly configure the addr field.
  632. txBuf[0] = (uint8_t)addr | CC1200_READ_BIT;
  633. 80006a8: 88fb ldrh r3, [r7, #6]
  634. 80006aa: b2db uxtb r3, r3
  635. 80006ac: f063 037f orn r3, r3, #127 ; 0x7f
  636. 80006b0: b2db uxtb r3, r3
  637. 80006b2: 723b strb r3, [r7, #8]
  638. HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 0);
  639. 80006b4: 2200 movs r2, #0
  640. 80006b6: 2140 movs r1, #64 ; 0x40
  641. 80006b8: 4817 ldr r0, [pc, #92] ; (8000718 <cc1200_spi_read_byte+0x7c>)
  642. 80006ba: f001 fab5 bl 8001c28 <HAL_GPIO_WritePin>
  643. if ((addr & 0xFF00) != 0) // read data with extended address in command field
  644. 80006be: 88fb ldrh r3, [r7, #6]
  645. 80006c0: f403 437f and.w r3, r3, #65280 ; 0xff00
  646. 80006c4: 2b00 cmp r3, #0
  647. 80006c6: d014 beq.n 80006f2 <cc1200_spi_read_byte+0x56>
  648. {
  649. txBuf[0] = ((uint8_t *)&addr)[1];
  650. 80006c8: 79fb ldrb r3, [r7, #7]
  651. 80006ca: 723b strb r3, [r7, #8]
  652. txBuf[1] = ((uint8_t *)&addr)[0];
  653. 80006cc: 1dbb adds r3, r7, #6
  654. 80006ce: 781b ldrb r3, [r3, #0]
  655. 80006d0: 727b strb r3, [r7, #9]
  656. txBuf[0] |= CC1200_READ_BIT;
  657. 80006d2: 7a3b ldrb r3, [r7, #8]
  658. 80006d4: f063 037f orn r3, r3, #127 ; 0x7f
  659. 80006d8: b2db uxtb r3, r3
  660. 80006da: 723b strb r3, [r7, #8]
  661. *data = SPI1_TransmitReceive(txBuf, 2);
  662. 80006dc: f107 0308 add.w r3, r7, #8
  663. 80006e0: 2102 movs r1, #2
  664. 80006e2: 4618 mov r0, r3
  665. 80006e4: f7ff ff90 bl 8000608 <SPI1_TransmitReceive>
  666. 80006e8: 4603 mov r3, r0
  667. 80006ea: 461a mov r2, r3
  668. 80006ec: 683b ldr r3, [r7, #0]
  669. 80006ee: 701a strb r2, [r3, #0]
  670. 80006f0: e009 b.n 8000706 <cc1200_spi_read_byte+0x6a>
  671. }
  672. else
  673. {
  674. *data = SPI1_TransmitReceive(txBuf, 1);
  675. 80006f2: f107 0308 add.w r3, r7, #8
  676. 80006f6: 2101 movs r1, #1
  677. 80006f8: 4618 mov r0, r3
  678. 80006fa: f7ff ff85 bl 8000608 <SPI1_TransmitReceive>
  679. 80006fe: 4603 mov r3, r0
  680. 8000700: 461a mov r2, r3
  681. 8000702: 683b ldr r3, [r7, #0]
  682. 8000704: 701a strb r2, [r3, #0]
  683. }
  684. HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 1);
  685. 8000706: 2201 movs r2, #1
  686. 8000708: 2140 movs r1, #64 ; 0x40
  687. 800070a: 4803 ldr r0, [pc, #12] ; (8000718 <cc1200_spi_read_byte+0x7c>)
  688. 800070c: f001 fa8c bl 8001c28 <HAL_GPIO_WritePin>
  689. }
  690. 8000710: bf00 nop
  691. 8000712: 3710 adds r7, #16
  692. 8000714: 46bd mov sp, r7
  693. 8000716: bd80 pop {r7, pc}
  694. 8000718: 58020800 .word 0x58020800
  695. 0800071c <cc1200_spi_strobe>:
  696. // ESP_ERROR_CHECK(ret);
  697. //}
  698. // TODO: Fix to use HAL.
  699. rf_status_t cc1200_spi_strobe(uint8_t cmd)
  700. {
  701. 800071c: b580 push {r7, lr}
  702. 800071e: b084 sub sp, #16
  703. 8000720: af00 add r7, sp, #0
  704. 8000722: 4603 mov r3, r0
  705. 8000724: 71fb strb r3, [r7, #7]
  706. uint8_t txBuf[2];
  707. txBuf[0] = cmd;
  708. 8000726: 79fb ldrb r3, [r7, #7]
  709. 8000728: 733b strb r3, [r7, #12]
  710. HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 0);
  711. 800072a: 2200 movs r2, #0
  712. 800072c: 2140 movs r1, #64 ; 0x40
  713. 800072e: 481c ldr r0, [pc, #112] ; (80007a0 <cc1200_spi_strobe+0x84>)
  714. 8000730: f001 fa7a bl 8001c28 <HAL_GPIO_WritePin>
  715. uint8_t rxByte;
  716. LL_SPI_SetTransferSize(SPI1, 1);
  717. 8000734: 2101 movs r1, #1
  718. 8000736: 481b ldr r0, [pc, #108] ; (80007a4 <cc1200_spi_strobe+0x88>)
  719. 8000738: f7ff fe5a bl 80003f0 <LL_SPI_SetTransferSize>
  720. LL_SPI_Enable(SPI1);
  721. 800073c: 4819 ldr r0, [pc, #100] ; (80007a4 <cc1200_spi_strobe+0x88>)
  722. 800073e: f7ff fe37 bl 80003b0 <LL_SPI_Enable>
  723. LL_SPI_StartMasterTransfer(SPI1);
  724. 8000742: 4818 ldr r0, [pc, #96] ; (80007a4 <cc1200_spi_strobe+0x88>)
  725. 8000744: f7ff fe6a bl 800041c <LL_SPI_StartMasterTransfer>
  726. LL_SPI_TransmitData8(SPI1, cmd);
  727. 8000748: 79fb ldrb r3, [r7, #7]
  728. 800074a: 4619 mov r1, r3
  729. 800074c: 4815 ldr r0, [pc, #84] ; (80007a4 <cc1200_spi_strobe+0x88>)
  730. 800074e: f7ff fea9 bl 80004a4 <LL_SPI_TransmitData8>
  731. while (LL_SPI_IsActiveFlag_RXP(SPI1) == 0);
  732. 8000752: bf00 nop
  733. 8000754: 4813 ldr r0, [pc, #76] ; (80007a4 <cc1200_spi_strobe+0x88>)
  734. 8000756: f7ff fe71 bl 800043c <LL_SPI_IsActiveFlag_RXP>
  735. 800075a: 4603 mov r3, r0
  736. 800075c: 2b00 cmp r3, #0
  737. 800075e: d0f9 beq.n 8000754 <cc1200_spi_strobe+0x38>
  738. rxByte = LL_SPI_ReceiveData8(SPI1);
  739. 8000760: 4810 ldr r0, [pc, #64] ; (80007a4 <cc1200_spi_strobe+0x88>)
  740. 8000762: f7ff fe91 bl 8000488 <LL_SPI_ReceiveData8>
  741. 8000766: 4603 mov r3, r0
  742. 8000768: 73fb strb r3, [r7, #15]
  743. // Wait until the transmission is complete
  744. while( LL_SPI_IsActiveFlag_EOT(SPI1) == 0);
  745. 800076a: bf00 nop
  746. 800076c: 480d ldr r0, [pc, #52] ; (80007a4 <cc1200_spi_strobe+0x88>)
  747. 800076e: f7ff fe78 bl 8000462 <LL_SPI_IsActiveFlag_EOT>
  748. 8000772: 4603 mov r3, r0
  749. 8000774: 2b00 cmp r3, #0
  750. 8000776: d0f9 beq.n 800076c <cc1200_spi_strobe+0x50>
  751. SPI1->IFCR = UINT32_MAX;
  752. 8000778: 4b0a ldr r3, [pc, #40] ; (80007a4 <cc1200_spi_strobe+0x88>)
  753. 800077a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
  754. 800077e: 619a str r2, [r3, #24]
  755. LL_SPI_Disable(SPI1);
  756. 8000780: 4808 ldr r0, [pc, #32] ; (80007a4 <cc1200_spi_strobe+0x88>)
  757. 8000782: f7ff fe25 bl 80003d0 <LL_SPI_Disable>
  758. HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, 1);
  759. 8000786: 2201 movs r2, #1
  760. 8000788: 2140 movs r1, #64 ; 0x40
  761. 800078a: 4805 ldr r0, [pc, #20] ; (80007a0 <cc1200_spi_strobe+0x84>)
  762. 800078c: f001 fa4c bl 8001c28 <HAL_GPIO_WritePin>
  763. return rxByte & 0xF0;
  764. 8000790: 7bfb ldrb r3, [r7, #15]
  765. 8000792: f023 030f bic.w r3, r3, #15
  766. 8000796: b2db uxtb r3, r3
  767. }
  768. 8000798: 4618 mov r0, r3
  769. 800079a: 3710 adds r7, #16
  770. 800079c: 46bd mov sp, r7
  771. 800079e: bd80 pop {r7, pc}
  772. 80007a0: 58020800 .word 0x58020800
  773. 80007a4: 40013000 .word 0x40013000
  774. 080007a8 <cc1200_radio_read_CFM>:
  775. cc1200_spi_read_byte(CC120X_RSSI1, &data);
  776. return data;
  777. }
  778. uint8_t cc1200_radio_read_CFM(void)
  779. {
  780. 80007a8: b580 push {r7, lr}
  781. 80007aa: b082 sub sp, #8
  782. 80007ac: af00 add r7, sp, #0
  783. uint8_t data = 0;
  784. 80007ae: 2300 movs r3, #0
  785. 80007b0: 71fb strb r3, [r7, #7]
  786. cc1200_spi_read_byte(CC120X_CFM_RX_DATA_OUT, &data);
  787. 80007b2: 1dfb adds r3, r7, #7
  788. 80007b4: 4619 mov r1, r3
  789. 80007b6: f642 707d movw r0, #12157 ; 0x2f7d
  790. 80007ba: f7ff ff6f bl 800069c <cc1200_spi_read_byte>
  791. return data;
  792. 80007be: 79fb ldrb r3, [r7, #7]
  793. }
  794. 80007c0: 4618 mov r0, r3
  795. 80007c2: 3708 adds r7, #8
  796. 80007c4: 46bd mov sp, r7
  797. 80007c6: bd80 pop {r7, pc}
  798. 080007c8 <cc1200_radio_reset>:
  799. {
  800. cc1200_spi_write_byte(CC120X_CFM_TX_DATA_IN, data);
  801. }
  802. rf_status_t cc1200_radio_reset(void)
  803. {
  804. 80007c8: b580 push {r7, lr}
  805. 80007ca: b082 sub sp, #8
  806. 80007cc: af00 add r7, sp, #0
  807. rf_status_t status;
  808. uint8_t retry_count = 0;
  809. 80007ce: 2300 movs r3, #0
  810. 80007d0: 71bb strb r3, [r7, #6]
  811. cc1200_spi_strobe(CC120X_SRES); // soft reset the chip
  812. 80007d2: 2030 movs r0, #48 ; 0x30
  813. 80007d4: f7ff ffa2 bl 800071c <cc1200_spi_strobe>
  814. status = cc1200_spi_strobe(CC120X_SNOP); // get chip status
  815. 80007d8: 203d movs r0, #61 ; 0x3d
  816. 80007da: f7ff ff9f bl 800071c <cc1200_spi_strobe>
  817. 80007de: 4603 mov r3, r0
  818. 80007e0: 71fb strb r3, [r7, #7]
  819. HAL_Delay(20);
  820. 80007e2: 2014 movs r0, #20
  821. 80007e4: f000 ff44 bl 8001670 <HAL_Delay>
  822. while((CC120X_RDYn_BIT & (status & 0x80))) // if chip isn't ready, wait 10ms
  823. 80007e8: e00d b.n 8000806 <cc1200_radio_reset+0x3e>
  824. {
  825. HAL_Delay(10);
  826. 80007ea: 200a movs r0, #10
  827. 80007ec: f000 ff40 bl 8001670 <HAL_Delay>
  828. if (retry_count > 3)
  829. 80007f0: 79bb ldrb r3, [r7, #6]
  830. 80007f2: 2b03 cmp r3, #3
  831. 80007f4: d80c bhi.n 8000810 <cc1200_radio_reset+0x48>
  832. {
  833. break;
  834. }
  835. status = cc1200_spi_strobe(CC120X_SNOP);
  836. 80007f6: 203d movs r0, #61 ; 0x3d
  837. 80007f8: f7ff ff90 bl 800071c <cc1200_spi_strobe>
  838. 80007fc: 4603 mov r3, r0
  839. 80007fe: 71fb strb r3, [r7, #7]
  840. retry_count++;
  841. 8000800: 79bb ldrb r3, [r7, #6]
  842. 8000802: 3301 adds r3, #1
  843. 8000804: 71bb strb r3, [r7, #6]
  844. while((CC120X_RDYn_BIT & (status & 0x80))) // if chip isn't ready, wait 10ms
  845. 8000806: f997 3007 ldrsb.w r3, [r7, #7]
  846. 800080a: 2b00 cmp r3, #0
  847. 800080c: dbed blt.n 80007ea <cc1200_radio_reset+0x22>
  848. 800080e: e000 b.n 8000812 <cc1200_radio_reset+0x4a>
  849. break;
  850. 8000810: bf00 nop
  851. }
  852. return status;
  853. 8000812: 79fb ldrb r3, [r7, #7]
  854. }
  855. 8000814: 4618 mov r0, r3
  856. 8000816: 3708 adds r7, #8
  857. 8000818: 46bd mov sp, r7
  858. 800081a: bd80 pop {r7, pc}
  859. 800081c: 0000 movs r0, r0
  860. ...
  861. 08000820 <cc1200_radio_frequency>:
  862. #define CC1200_LO_DIVIDER 24 // 136.7 - 160 MHz Band
  863. #define CC1200_XOSC 40000000 // 40MHz
  864. void cc1200_radio_frequency(uint32_t freq)
  865. {
  866. 8000820: b580 push {r7, lr}
  867. 8000822: b084 sub sp, #16
  868. 8000824: af00 add r7, sp, #0
  869. 8000826: 6078 str r0, [r7, #4]
  870. // f_VCO = FREQ / 2^16 * f_XOSX + FREQOFF / 2^18 * F_XOSC
  871. double temp_freq;
  872. // calculate FREQ0, FREQ, FREQ2 registers
  873. temp_freq = ((double) freq * 65536 * CC1200_LO_DIVIDER) / CC1200_XOSC;
  874. 8000828: 687b ldr r3, [r7, #4]
  875. 800082a: ee07 3a90 vmov s15, r3
  876. 800082e: eeb8 7b67 vcvt.f64.u32 d7, s15
  877. 8000832: ed9f 6b19 vldr d6, [pc, #100] ; 8000898 <cc1200_radio_frequency+0x78>
  878. 8000836: ee27 7b06 vmul.f64 d7, d7, d6
  879. 800083a: eeb3 6b08 vmov.f64 d6, #56 ; 0x41c00000 24.0
  880. 800083e: ee27 6b06 vmul.f64 d6, d7, d6
  881. 8000842: ed9f 5b17 vldr d5, [pc, #92] ; 80008a0 <cc1200_radio_frequency+0x80>
  882. 8000846: ee86 7b05 vdiv.f64 d7, d6, d5
  883. 800084a: ed87 7b02 vstr d7, [r7, #8]
  884. freq = (uint32_t)temp_freq;
  885. 800084e: ed97 7b02 vldr d7, [r7, #8]
  886. 8000852: eefc 7bc7 vcvt.u32.f64 s15, d7
  887. 8000856: ee17 3a90 vmov r3, s15
  888. 800085a: 607b str r3, [r7, #4]
  889. cc1200_spi_write_byte(CC120X_FREQ0, ((uint8_t *)&freq)[0]);
  890. 800085c: 1d3b adds r3, r7, #4
  891. 800085e: 781b ldrb r3, [r3, #0]
  892. 8000860: 4619 mov r1, r3
  893. 8000862: f642 700e movw r0, #12046 ; 0x2f0e
  894. 8000866: f7ff fee1 bl 800062c <cc1200_spi_write_byte>
  895. cc1200_spi_write_byte(CC120X_FREQ1, ((uint8_t *)&freq)[1]);
  896. 800086a: 1d3b adds r3, r7, #4
  897. 800086c: 3301 adds r3, #1
  898. 800086e: 781b ldrb r3, [r3, #0]
  899. 8000870: 4619 mov r1, r3
  900. 8000872: f642 700d movw r0, #12045 ; 0x2f0d
  901. 8000876: f7ff fed9 bl 800062c <cc1200_spi_write_byte>
  902. cc1200_spi_write_byte(CC120X_FREQ2, ((uint8_t *)&freq)[2]);
  903. 800087a: 1d3b adds r3, r7, #4
  904. 800087c: 3302 adds r3, #2
  905. 800087e: 781b ldrb r3, [r3, #0]
  906. 8000880: 4619 mov r1, r3
  907. 8000882: f642 700c movw r0, #12044 ; 0x2f0c
  908. 8000886: f7ff fed1 bl 800062c <cc1200_spi_write_byte>
  909. return ;
  910. 800088a: bf00 nop
  911. }
  912. 800088c: 3710 adds r7, #16
  913. 800088e: 46bd mov sp, r7
  914. 8000890: bd80 pop {r7, pc}
  915. 8000892: bf00 nop
  916. 8000894: f3af 8000 nop.w
  917. 8000898: 00000000 .word 0x00000000
  918. 800089c: 40f00000 .word 0x40f00000
  919. 80008a0: 00000000 .word 0x00000000
  920. 80008a4: 418312d0 .word 0x418312d0
  921. 080008a8 <cc1200_radio_rx>:
  922. // TODO: Create exception for failure condition
  923. while (cc1200_spi_strobe(CC120X_STX) != CC120X_STATE_TX);
  924. }
  925. void cc1200_radio_rx(void)
  926. {
  927. 80008a8: b580 push {r7, lr}
  928. 80008aa: af00 add r7, sp, #0
  929. // TODO: Create exception for failure condition
  930. while (cc1200_spi_strobe(CC120X_SRX) != CC120X_STATE_RX);
  931. 80008ac: bf00 nop
  932. 80008ae: 2034 movs r0, #52 ; 0x34
  933. 80008b0: f7ff ff34 bl 800071c <cc1200_spi_strobe>
  934. 80008b4: 4603 mov r3, r0
  935. 80008b6: 2b10 cmp r3, #16
  936. 80008b8: d1f9 bne.n 80008ae <cc1200_radio_rx+0x6>
  937. }
  938. 80008ba: bf00 nop
  939. 80008bc: bf00 nop
  940. 80008be: bd80 pop {r7, pc}
  941. 080008c0 <cc1200_radio_init>:
  942. // TODO: Fix to use HAL.
  943. void cc1200_radio_init(const cc1200_reg_settings_t* rf_settings, uint8_t len)
  944. {
  945. 80008c0: b580 push {r7, lr}
  946. 80008c2: b084 sub sp, #16
  947. 80008c4: af00 add r7, sp, #0
  948. 80008c6: 6078 str r0, [r7, #4]
  949. 80008c8: 460b mov r3, r1
  950. 80008ca: 70fb strb r3, [r7, #3]
  951. //cc1200_gpio_init();
  952. //cc1200_spi_init();
  953. cc1200_radio_reset(); //gpio_set_level(CC1200_RESET, 1);
  954. 80008cc: f7ff ff7c bl 80007c8 <cc1200_radio_reset>
  955. uint8_t i;
  956. for (i=0;i<len;i++)
  957. 80008d0: 2300 movs r3, #0
  958. 80008d2: 73fb strb r3, [r7, #15]
  959. 80008d4: e00f b.n 80008f6 <cc1200_radio_init+0x36>
  960. {
  961. cc1200_spi_write_byte(rf_settings[i].addr, rf_settings[i].data);
  962. 80008d6: 7bfb ldrb r3, [r7, #15]
  963. 80008d8: 009b lsls r3, r3, #2
  964. 80008da: 687a ldr r2, [r7, #4]
  965. 80008dc: 4413 add r3, r2
  966. 80008de: 8818 ldrh r0, [r3, #0]
  967. 80008e0: 7bfb ldrb r3, [r7, #15]
  968. 80008e2: 009b lsls r3, r3, #2
  969. 80008e4: 687a ldr r2, [r7, #4]
  970. 80008e6: 4413 add r3, r2
  971. 80008e8: 789b ldrb r3, [r3, #2]
  972. 80008ea: 4619 mov r1, r3
  973. 80008ec: f7ff fe9e bl 800062c <cc1200_spi_write_byte>
  974. for (i=0;i<len;i++)
  975. 80008f0: 7bfb ldrb r3, [r7, #15]
  976. 80008f2: 3301 adds r3, #1
  977. 80008f4: 73fb strb r3, [r7, #15]
  978. 80008f6: 7bfa ldrb r2, [r7, #15]
  979. 80008f8: 78fb ldrb r3, [r7, #3]
  980. 80008fa: 429a cmp r2, r3
  981. 80008fc: d3eb bcc.n 80008d6 <cc1200_radio_init+0x16>
  982. }
  983. while(cc1200_spi_strobe(CC120X_SIDLE) != CC120X_STATE_IDLE);
  984. 80008fe: bf00 nop
  985. 8000900: 2036 movs r0, #54 ; 0x36
  986. 8000902: f7ff ff0b bl 800071c <cc1200_spi_strobe>
  987. 8000906: 4603 mov r3, r0
  988. 8000908: 2b00 cmp r3, #0
  989. 800090a: d1f9 bne.n 8000900 <cc1200_radio_init+0x40>
  990. }
  991. 800090c: bf00 nop
  992. 800090e: bf00 nop
  993. 8000910: 3710 adds r7, #16
  994. 8000912: 46bd mov sp, r7
  995. 8000914: bd80 pop {r7, pc}
  996. 08000916 <LL_SPI_SetStandard>:
  997. {
  998. 8000916: b480 push {r7}
  999. 8000918: b083 sub sp, #12
  1000. 800091a: af00 add r7, sp, #0
  1001. 800091c: 6078 str r0, [r7, #4]
  1002. 800091e: 6039 str r1, [r7, #0]
  1003. MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
  1004. 8000920: 687b ldr r3, [r7, #4]
  1005. 8000922: 68db ldr r3, [r3, #12]
  1006. 8000924: f423 1260 bic.w r2, r3, #3670016 ; 0x380000
  1007. 8000928: 683b ldr r3, [r7, #0]
  1008. 800092a: 431a orrs r2, r3
  1009. 800092c: 687b ldr r3, [r7, #4]
  1010. 800092e: 60da str r2, [r3, #12]
  1011. }
  1012. 8000930: bf00 nop
  1013. 8000932: 370c adds r7, #12
  1014. 8000934: 46bd mov sp, r7
  1015. 8000936: f85d 7b04 ldr.w r7, [sp], #4
  1016. 800093a: 4770 bx lr
  1017. 0800093c <LL_SPI_EnableNSSPulseMgt>:
  1018. {
  1019. 800093c: b480 push {r7}
  1020. 800093e: b083 sub sp, #12
  1021. 8000940: af00 add r7, sp, #0
  1022. 8000942: 6078 str r0, [r7, #4]
  1023. SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
  1024. 8000944: 687b ldr r3, [r7, #4]
  1025. 8000946: 68db ldr r3, [r3, #12]
  1026. 8000948: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000
  1027. 800094c: 687b ldr r3, [r7, #4]
  1028. 800094e: 60da str r2, [r3, #12]
  1029. }
  1030. 8000950: bf00 nop
  1031. 8000952: 370c adds r7, #12
  1032. 8000954: 46bd mov sp, r7
  1033. 8000956: f85d 7b04 ldr.w r7, [sp], #4
  1034. 800095a: 4770 bx lr
  1035. 0800095c <LL_AHB4_GRP1_EnableClock>:
  1036. *
  1037. * (*) value not defined in all devices.
  1038. * @retval None
  1039. */
  1040. __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
  1041. {
  1042. 800095c: b480 push {r7}
  1043. 800095e: b085 sub sp, #20
  1044. 8000960: af00 add r7, sp, #0
  1045. 8000962: 6078 str r0, [r7, #4]
  1046. __IO uint32_t tmpreg;
  1047. SET_BIT(RCC->AHB4ENR, Periphs);
  1048. 8000964: 4b0a ldr r3, [pc, #40] ; (8000990 <LL_AHB4_GRP1_EnableClock+0x34>)
  1049. 8000966: f8d3 20e0 ldr.w r2, [r3, #224] ; 0xe0
  1050. 800096a: 4909 ldr r1, [pc, #36] ; (8000990 <LL_AHB4_GRP1_EnableClock+0x34>)
  1051. 800096c: 687b ldr r3, [r7, #4]
  1052. 800096e: 4313 orrs r3, r2
  1053. 8000970: f8c1 30e0 str.w r3, [r1, #224] ; 0xe0
  1054. /* Delay after an RCC peripheral clock enabling */
  1055. tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
  1056. 8000974: 4b06 ldr r3, [pc, #24] ; (8000990 <LL_AHB4_GRP1_EnableClock+0x34>)
  1057. 8000976: f8d3 20e0 ldr.w r2, [r3, #224] ; 0xe0
  1058. 800097a: 687b ldr r3, [r7, #4]
  1059. 800097c: 4013 ands r3, r2
  1060. 800097e: 60fb str r3, [r7, #12]
  1061. (void)tmpreg;
  1062. 8000980: 68fb ldr r3, [r7, #12]
  1063. }
  1064. 8000982: bf00 nop
  1065. 8000984: 3714 adds r7, #20
  1066. 8000986: 46bd mov sp, r7
  1067. 8000988: f85d 7b04 ldr.w r7, [sp], #4
  1068. 800098c: 4770 bx lr
  1069. 800098e: bf00 nop
  1070. 8000990: 58024400 .word 0x58024400
  1071. 08000994 <LL_APB2_GRP1_EnableClock>:
  1072. *
  1073. * (*) value not defined in all devices.
  1074. * @retval None
  1075. */
  1076. __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
  1077. {
  1078. 8000994: b480 push {r7}
  1079. 8000996: b085 sub sp, #20
  1080. 8000998: af00 add r7, sp, #0
  1081. 800099a: 6078 str r0, [r7, #4]
  1082. __IO uint32_t tmpreg;
  1083. SET_BIT(RCC->APB2ENR, Periphs);
  1084. 800099c: 4b0a ldr r3, [pc, #40] ; (80009c8 <LL_APB2_GRP1_EnableClock+0x34>)
  1085. 800099e: f8d3 20f0 ldr.w r2, [r3, #240] ; 0xf0
  1086. 80009a2: 4909 ldr r1, [pc, #36] ; (80009c8 <LL_APB2_GRP1_EnableClock+0x34>)
  1087. 80009a4: 687b ldr r3, [r7, #4]
  1088. 80009a6: 4313 orrs r3, r2
  1089. 80009a8: f8c1 30f0 str.w r3, [r1, #240] ; 0xf0
  1090. /* Delay after an RCC peripheral clock enabling */
  1091. tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
  1092. 80009ac: 4b06 ldr r3, [pc, #24] ; (80009c8 <LL_APB2_GRP1_EnableClock+0x34>)
  1093. 80009ae: f8d3 20f0 ldr.w r2, [r3, #240] ; 0xf0
  1094. 80009b2: 687b ldr r3, [r7, #4]
  1095. 80009b4: 4013 ands r3, r2
  1096. 80009b6: 60fb str r3, [r7, #12]
  1097. (void)tmpreg;
  1098. 80009b8: 68fb ldr r3, [r7, #12]
  1099. }
  1100. 80009ba: bf00 nop
  1101. 80009bc: 3714 adds r7, #20
  1102. 80009be: 46bd mov sp, r7
  1103. 80009c0: f85d 7b04 ldr.w r7, [sp], #4
  1104. 80009c4: 4770 bx lr
  1105. 80009c6: bf00 nop
  1106. 80009c8: 58024400 .word 0x58024400
  1107. 080009cc <HAL_TIM_PeriodElapsedCallback>:
  1108. static uint8_t txBuffer0[2000];
  1109. static uint8_t txBuffer1[2000];
  1110. static uint32_t i=0, j=0;
  1111. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)
  1112. {
  1113. 80009cc: b590 push {r4, r7, lr}
  1114. 80009ce: b083 sub sp, #12
  1115. 80009d0: af00 add r7, sp, #0
  1116. 80009d2: 6078 str r0, [r7, #4]
  1117. if (i == 2000 && j < 2000)
  1118. 80009d4: 4b1f ldr r3, [pc, #124] ; (8000a54 <HAL_TIM_PeriodElapsedCallback+0x88>)
  1119. 80009d6: 681b ldr r3, [r3, #0]
  1120. 80009d8: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0
  1121. 80009dc: d110 bne.n 8000a00 <HAL_TIM_PeriodElapsedCallback+0x34>
  1122. 80009de: 4b1e ldr r3, [pc, #120] ; (8000a58 <HAL_TIM_PeriodElapsedCallback+0x8c>)
  1123. 80009e0: 681b ldr r3, [r3, #0]
  1124. 80009e2: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0
  1125. 80009e6: d20b bcs.n 8000a00 <HAL_TIM_PeriodElapsedCallback+0x34>
  1126. txBuffer1[j++] = cc1200_radio_read_CFM();
  1127. 80009e8: 4b1b ldr r3, [pc, #108] ; (8000a58 <HAL_TIM_PeriodElapsedCallback+0x8c>)
  1128. 80009ea: 681c ldr r4, [r3, #0]
  1129. 80009ec: 1c63 adds r3, r4, #1
  1130. 80009ee: 4a1a ldr r2, [pc, #104] ; (8000a58 <HAL_TIM_PeriodElapsedCallback+0x8c>)
  1131. 80009f0: 6013 str r3, [r2, #0]
  1132. 80009f2: f7ff fed9 bl 80007a8 <cc1200_radio_read_CFM>
  1133. 80009f6: 4603 mov r3, r0
  1134. 80009f8: 461a mov r2, r3
  1135. 80009fa: 4b18 ldr r3, [pc, #96] ; (8000a5c <HAL_TIM_PeriodElapsedCallback+0x90>)
  1136. 80009fc: 551a strb r2, [r3, r4]
  1137. 80009fe: e014 b.n 8000a2a <HAL_TIM_PeriodElapsedCallback+0x5e>
  1138. else if (i < 2000)
  1139. 8000a00: 4b14 ldr r3, [pc, #80] ; (8000a54 <HAL_TIM_PeriodElapsedCallback+0x88>)
  1140. 8000a02: 681b ldr r3, [r3, #0]
  1141. 8000a04: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0
  1142. 8000a08: d20b bcs.n 8000a22 <HAL_TIM_PeriodElapsedCallback+0x56>
  1143. txBuffer0[i++] = cc1200_radio_read_CFM();
  1144. 8000a0a: 4b12 ldr r3, [pc, #72] ; (8000a54 <HAL_TIM_PeriodElapsedCallback+0x88>)
  1145. 8000a0c: 681c ldr r4, [r3, #0]
  1146. 8000a0e: 1c63 adds r3, r4, #1
  1147. 8000a10: 4a10 ldr r2, [pc, #64] ; (8000a54 <HAL_TIM_PeriodElapsedCallback+0x88>)
  1148. 8000a12: 6013 str r3, [r2, #0]
  1149. 8000a14: f7ff fec8 bl 80007a8 <cc1200_radio_read_CFM>
  1150. 8000a18: 4603 mov r3, r0
  1151. 8000a1a: 461a mov r2, r3
  1152. 8000a1c: 4b10 ldr r3, [pc, #64] ; (8000a60 <HAL_TIM_PeriodElapsedCallback+0x94>)
  1153. 8000a1e: 551a strb r2, [r3, r4]
  1154. 8000a20: e003 b.n 8000a2a <HAL_TIM_PeriodElapsedCallback+0x5e>
  1155. else
  1156. {
  1157. HAL_GPIO_TogglePin(LED_YELLOW_GPIO_Port, LED_YELLOW_Pin);
  1158. 8000a22: 2102 movs r1, #2
  1159. 8000a24: 480f ldr r0, [pc, #60] ; (8000a64 <HAL_TIM_PeriodElapsedCallback+0x98>)
  1160. 8000a26: f001 f918 bl 8001c5a <HAL_GPIO_TogglePin>
  1161. //cc1200_radio_write_CFM(0);
  1162. // Toggle LED as heart beat.
  1163. static uint32_t toggleCount = 0;
  1164. if (toggleCount++ == 40000)
  1165. 8000a2a: 4b0f ldr r3, [pc, #60] ; (8000a68 <HAL_TIM_PeriodElapsedCallback+0x9c>)
  1166. 8000a2c: 681b ldr r3, [r3, #0]
  1167. 8000a2e: 1c5a adds r2, r3, #1
  1168. 8000a30: 490d ldr r1, [pc, #52] ; (8000a68 <HAL_TIM_PeriodElapsedCallback+0x9c>)
  1169. 8000a32: 600a str r2, [r1, #0]
  1170. 8000a34: f649 4240 movw r2, #40000 ; 0x9c40
  1171. 8000a38: 4293 cmp r3, r2
  1172. 8000a3a: d106 bne.n 8000a4a <HAL_TIM_PeriodElapsedCallback+0x7e>
  1173. {
  1174. HAL_GPIO_TogglePin(LED_GREEN_GPIO_Port, LED_GREEN_Pin);
  1175. 8000a3c: 2101 movs r1, #1
  1176. 8000a3e: 480b ldr r0, [pc, #44] ; (8000a6c <HAL_TIM_PeriodElapsedCallback+0xa0>)
  1177. 8000a40: f001 f90b bl 8001c5a <HAL_GPIO_TogglePin>
  1178. toggleCount = 0;
  1179. 8000a44: 4b08 ldr r3, [pc, #32] ; (8000a68 <HAL_TIM_PeriodElapsedCallback+0x9c>)
  1180. 8000a46: 2200 movs r2, #0
  1181. 8000a48: 601a str r2, [r3, #0]
  1182. }
  1183. }
  1184. 8000a4a: bf00 nop
  1185. 8000a4c: 370c adds r7, #12
  1186. 8000a4e: 46bd mov sp, r7
  1187. 8000a50: bd90 pop {r4, r7, pc}
  1188. 8000a52: bf00 nop
  1189. 8000a54: 240011a4 .word 0x240011a4
  1190. 8000a58: 240011a8 .word 0x240011a8
  1191. 8000a5c: 240009d4 .word 0x240009d4
  1192. 8000a60: 24000204 .word 0x24000204
  1193. 8000a64: 58021000 .word 0x58021000
  1194. 8000a68: 240011ac .word 0x240011ac
  1195. 8000a6c: 58020400 .word 0x58020400
  1196. 08000a70 <main>:
  1197. /**
  1198. * @brief The application entry point.
  1199. * @retval int
  1200. */
  1201. int main(void)
  1202. {
  1203. 8000a70: b580 push {r7, lr}
  1204. 8000a72: b084 sub sp, #16
  1205. 8000a74: af00 add r7, sp, #0
  1206. \details Turns on I-Cache
  1207. */
  1208. __STATIC_FORCEINLINE void SCB_EnableICache (void)
  1209. {
  1210. #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
  1211. if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
  1212. 8000a76: 4b5d ldr r3, [pc, #372] ; (8000bec <main+0x17c>)
  1213. 8000a78: 695b ldr r3, [r3, #20]
  1214. 8000a7a: f403 3300 and.w r3, r3, #131072 ; 0x20000
  1215. 8000a7e: 2b00 cmp r3, #0
  1216. 8000a80: d11b bne.n 8000aba <main+0x4a>
  1217. \details Acts as a special kind of Data Memory Barrier.
  1218. It completes when all explicit memory accesses before this instruction complete.
  1219. */
  1220. __STATIC_FORCEINLINE void __DSB(void)
  1221. {
  1222. __ASM volatile ("dsb 0xF":::"memory");
  1223. 8000a82: f3bf 8f4f dsb sy
  1224. }
  1225. 8000a86: bf00 nop
  1226. __ASM volatile ("isb 0xF":::"memory");
  1227. 8000a88: f3bf 8f6f isb sy
  1228. }
  1229. 8000a8c: bf00 nop
  1230. __DSB();
  1231. __ISB();
  1232. SCB->ICIALLU = 0UL; /* invalidate I-Cache */
  1233. 8000a8e: 4b57 ldr r3, [pc, #348] ; (8000bec <main+0x17c>)
  1234. 8000a90: 2200 movs r2, #0
  1235. 8000a92: f8c3 2250 str.w r2, [r3, #592] ; 0x250
  1236. __ASM volatile ("dsb 0xF":::"memory");
  1237. 8000a96: f3bf 8f4f dsb sy
  1238. }
  1239. 8000a9a: bf00 nop
  1240. __ASM volatile ("isb 0xF":::"memory");
  1241. 8000a9c: f3bf 8f6f isb sy
  1242. }
  1243. 8000aa0: bf00 nop
  1244. __DSB();
  1245. __ISB();
  1246. SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
  1247. 8000aa2: 4b52 ldr r3, [pc, #328] ; (8000bec <main+0x17c>)
  1248. 8000aa4: 695b ldr r3, [r3, #20]
  1249. 8000aa6: 4a51 ldr r2, [pc, #324] ; (8000bec <main+0x17c>)
  1250. 8000aa8: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  1251. 8000aac: 6153 str r3, [r2, #20]
  1252. __ASM volatile ("dsb 0xF":::"memory");
  1253. 8000aae: f3bf 8f4f dsb sy
  1254. }
  1255. 8000ab2: bf00 nop
  1256. __ASM volatile ("isb 0xF":::"memory");
  1257. 8000ab4: f3bf 8f6f isb sy
  1258. }
  1259. 8000ab8: e000 b.n 8000abc <main+0x4c>
  1260. if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
  1261. 8000aba: bf00 nop
  1262. #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
  1263. uint32_t ccsidr;
  1264. uint32_t sets;
  1265. uint32_t ways;
  1266. if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
  1267. 8000abc: 4b4b ldr r3, [pc, #300] ; (8000bec <main+0x17c>)
  1268. 8000abe: 695b ldr r3, [r3, #20]
  1269. 8000ac0: f403 3380 and.w r3, r3, #65536 ; 0x10000
  1270. 8000ac4: 2b00 cmp r3, #0
  1271. 8000ac6: d138 bne.n 8000b3a <main+0xca>
  1272. SCB->CSSELR = 0U; /* select Level 1 data cache */
  1273. 8000ac8: 4b48 ldr r3, [pc, #288] ; (8000bec <main+0x17c>)
  1274. 8000aca: 2200 movs r2, #0
  1275. 8000acc: f8c3 2084 str.w r2, [r3, #132] ; 0x84
  1276. __ASM volatile ("dsb 0xF":::"memory");
  1277. 8000ad0: f3bf 8f4f dsb sy
  1278. }
  1279. 8000ad4: bf00 nop
  1280. __DSB();
  1281. ccsidr = SCB->CCSIDR;
  1282. 8000ad6: 4b45 ldr r3, [pc, #276] ; (8000bec <main+0x17c>)
  1283. 8000ad8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
  1284. 8000adc: 60bb str r3, [r7, #8]
  1285. /* invalidate D-Cache */
  1286. sets = (uint32_t)(CCSIDR_SETS(ccsidr));
  1287. 8000ade: 68bb ldr r3, [r7, #8]
  1288. 8000ae0: 0b5b lsrs r3, r3, #13
  1289. 8000ae2: f3c3 030e ubfx r3, r3, #0, #15
  1290. 8000ae6: 607b str r3, [r7, #4]
  1291. do {
  1292. ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
  1293. 8000ae8: 68bb ldr r3, [r7, #8]
  1294. 8000aea: 08db lsrs r3, r3, #3
  1295. 8000aec: f3c3 0309 ubfx r3, r3, #0, #10
  1296. 8000af0: 603b str r3, [r7, #0]
  1297. do {
  1298. SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
  1299. 8000af2: 687b ldr r3, [r7, #4]
  1300. 8000af4: 015a lsls r2, r3, #5
  1301. 8000af6: f643 73e0 movw r3, #16352 ; 0x3fe0
  1302. 8000afa: 4013 ands r3, r2
  1303. ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
  1304. 8000afc: 683a ldr r2, [r7, #0]
  1305. 8000afe: 0792 lsls r2, r2, #30
  1306. SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
  1307. 8000b00: 493a ldr r1, [pc, #232] ; (8000bec <main+0x17c>)
  1308. 8000b02: 4313 orrs r3, r2
  1309. 8000b04: f8c1 3260 str.w r3, [r1, #608] ; 0x260
  1310. #if defined ( __CC_ARM )
  1311. __schedule_barrier();
  1312. #endif
  1313. } while (ways-- != 0U);
  1314. 8000b08: 683b ldr r3, [r7, #0]
  1315. 8000b0a: 1e5a subs r2, r3, #1
  1316. 8000b0c: 603a str r2, [r7, #0]
  1317. 8000b0e: 2b00 cmp r3, #0
  1318. 8000b10: d1ef bne.n 8000af2 <main+0x82>
  1319. } while(sets-- != 0U);
  1320. 8000b12: 687b ldr r3, [r7, #4]
  1321. 8000b14: 1e5a subs r2, r3, #1
  1322. 8000b16: 607a str r2, [r7, #4]
  1323. 8000b18: 2b00 cmp r3, #0
  1324. 8000b1a: d1e5 bne.n 8000ae8 <main+0x78>
  1325. __ASM volatile ("dsb 0xF":::"memory");
  1326. 8000b1c: f3bf 8f4f dsb sy
  1327. }
  1328. 8000b20: bf00 nop
  1329. __DSB();
  1330. SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
  1331. 8000b22: 4b32 ldr r3, [pc, #200] ; (8000bec <main+0x17c>)
  1332. 8000b24: 695b ldr r3, [r3, #20]
  1333. 8000b26: 4a31 ldr r2, [pc, #196] ; (8000bec <main+0x17c>)
  1334. 8000b28: f443 3380 orr.w r3, r3, #65536 ; 0x10000
  1335. 8000b2c: 6153 str r3, [r2, #20]
  1336. __ASM volatile ("dsb 0xF":::"memory");
  1337. 8000b2e: f3bf 8f4f dsb sy
  1338. }
  1339. 8000b32: bf00 nop
  1340. __ASM volatile ("isb 0xF":::"memory");
  1341. 8000b34: f3bf 8f6f isb sy
  1342. }
  1343. 8000b38: e000 b.n 8000b3c <main+0xcc>
  1344. if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
  1345. 8000b3a: bf00 nop
  1346. SCB_EnableDCache();
  1347. /* MCU Configuration--------------------------------------------------------*/
  1348. /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  1349. HAL_Init();
  1350. 8000b3c: f000 fd06 bl 800154c <HAL_Init>
  1351. /* USER CODE BEGIN Init */
  1352. /* USER CODE END Init */
  1353. /* Configure the system clock */
  1354. SystemClock_Config();
  1355. 8000b40: f000 f866 bl 8000c10 <SystemClock_Config>
  1356. /* USER CODE BEGIN SysInit */
  1357. /* USER CODE END SysInit */
  1358. /* Initialize all configured peripherals */
  1359. MX_GPIO_Init();
  1360. 8000b44: f000 f9bc bl 8000ec0 <MX_GPIO_Init>
  1361. MX_SPI1_Init();
  1362. 8000b48: f000 f8d2 bl 8000cf0 <MX_SPI1_Init>
  1363. MX_TIM3_Init();
  1364. 8000b4c: f000 f96a bl 8000e24 <MX_TIM3_Init>
  1365. MX_USB_DEVICE_Init();
  1366. 8000b50: f008 f980 bl 8008e54 <MX_USB_DEVICE_Init>
  1367. /* USER CODE BEGIN 2 */
  1368. HAL_StatusTypeDef errCode;
  1369. // Manually reset the CC1200.
  1370. HAL_GPIO_WritePin(CC1200_RESET_GPIO_Port, CC1200_RESET_Pin, 0);
  1371. 8000b54: 2200 movs r2, #0
  1372. 8000b56: f44f 5180 mov.w r1, #4096 ; 0x1000
  1373. 8000b5a: 4825 ldr r0, [pc, #148] ; (8000bf0 <main+0x180>)
  1374. 8000b5c: f001 f864 bl 8001c28 <HAL_GPIO_WritePin>
  1375. HAL_Delay(50);
  1376. 8000b60: 2032 movs r0, #50 ; 0x32
  1377. 8000b62: f000 fd85 bl 8001670 <HAL_Delay>
  1378. HAL_GPIO_WritePin(CC1200_RESET_GPIO_Port, CC1200_RESET_Pin, 1);
  1379. 8000b66: 2201 movs r2, #1
  1380. 8000b68: f44f 5180 mov.w r1, #4096 ; 0x1000
  1381. 8000b6c: 4820 ldr r0, [pc, #128] ; (8000bf0 <main+0x180>)
  1382. 8000b6e: f001 f85b bl 8001c28 <HAL_GPIO_WritePin>
  1383. HAL_Delay(50);
  1384. 8000b72: 2032 movs r0, #50 ; 0x32
  1385. 8000b74: f000 fd7c bl 8001670 <HAL_Delay>
  1386. // Setup up the 5million registers.
  1387. cc1200_radio_init((cc1200_reg_settings_t *)AX25_SETTINGS, sizeof(AX25_SETTINGS)/sizeof(cc1200_reg_settings_t));
  1388. 8000b78: 2133 movs r1, #51 ; 0x33
  1389. 8000b7a: 481e ldr r0, [pc, #120] ; (8000bf4 <main+0x184>)
  1390. 8000b7c: f7ff fea0 bl 80008c0 <cc1200_radio_init>
  1391. // Set frequency
  1392. cc1200_radio_frequency(144390000);
  1393. 8000b80: 481d ldr r0, [pc, #116] ; (8000bf8 <main+0x188>)
  1394. 8000b82: f7ff fe4d bl 8000820 <cc1200_radio_frequency>
  1395. // Enable TX/RX
  1396. cc1200_radio_rx();
  1397. 8000b86: f7ff fe8f bl 80008a8 <cc1200_radio_rx>
  1398. // Start Timer for SPI
  1399. errCode = HAL_TIM_Base_Start_IT(&htim3);
  1400. 8000b8a: 481c ldr r0, [pc, #112] ; (8000bfc <main+0x18c>)
  1401. 8000b8c: f004 fa5a bl 8005044 <HAL_TIM_Base_Start_IT>
  1402. 8000b90: 4603 mov r3, r0
  1403. 8000b92: 73fb strb r3, [r7, #15]
  1404. /* Infinite loop */
  1405. /* USER CODE BEGIN WHILE */
  1406. while (1)
  1407. {
  1408. if (i >= 2000)
  1409. 8000b94: 4b1a ldr r3, [pc, #104] ; (8000c00 <main+0x190>)
  1410. 8000b96: 681b ldr r3, [r3, #0]
  1411. 8000b98: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0
  1412. 8000b9c: d30f bcc.n 8000bbe <main+0x14e>
  1413. {
  1414. if(CDC_Transmit_HS(txBuffer0, 2000) != USBD_OK)
  1415. 8000b9e: f44f 61fa mov.w r1, #2000 ; 0x7d0
  1416. 8000ba2: 4818 ldr r0, [pc, #96] ; (8000c04 <main+0x194>)
  1417. 8000ba4: f008 fa16 bl 8008fd4 <CDC_Transmit_HS>
  1418. 8000ba8: 4603 mov r3, r0
  1419. 8000baa: 2b00 cmp r3, #0
  1420. 8000bac: d004 beq.n 8000bb8 <main+0x148>
  1421. {
  1422. HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin);
  1423. 8000bae: f44f 4180 mov.w r1, #16384 ; 0x4000
  1424. 8000bb2: 480f ldr r0, [pc, #60] ; (8000bf0 <main+0x180>)
  1425. 8000bb4: f001 f851 bl 8001c5a <HAL_GPIO_TogglePin>
  1426. }
  1427. i = 0;
  1428. 8000bb8: 4b11 ldr r3, [pc, #68] ; (8000c00 <main+0x190>)
  1429. 8000bba: 2200 movs r2, #0
  1430. 8000bbc: 601a str r2, [r3, #0]
  1431. }
  1432. if (j >= 2000)
  1433. 8000bbe: 4b12 ldr r3, [pc, #72] ; (8000c08 <main+0x198>)
  1434. 8000bc0: 681b ldr r3, [r3, #0]
  1435. 8000bc2: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0
  1436. 8000bc6: d3e5 bcc.n 8000b94 <main+0x124>
  1437. {
  1438. if(CDC_Transmit_HS(txBuffer1, 2000) != USBD_OK)
  1439. 8000bc8: f44f 61fa mov.w r1, #2000 ; 0x7d0
  1440. 8000bcc: 480f ldr r0, [pc, #60] ; (8000c0c <main+0x19c>)
  1441. 8000bce: f008 fa01 bl 8008fd4 <CDC_Transmit_HS>
  1442. 8000bd2: 4603 mov r3, r0
  1443. 8000bd4: 2b00 cmp r3, #0
  1444. 8000bd6: d004 beq.n 8000be2 <main+0x172>
  1445. {
  1446. HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin);
  1447. 8000bd8: f44f 4180 mov.w r1, #16384 ; 0x4000
  1448. 8000bdc: 4804 ldr r0, [pc, #16] ; (8000bf0 <main+0x180>)
  1449. 8000bde: f001 f83c bl 8001c5a <HAL_GPIO_TogglePin>
  1450. }
  1451. j = 0;
  1452. 8000be2: 4b09 ldr r3, [pc, #36] ; (8000c08 <main+0x198>)
  1453. 8000be4: 2200 movs r2, #0
  1454. 8000be6: 601a str r2, [r3, #0]
  1455. if (i >= 2000)
  1456. 8000be8: e7d4 b.n 8000b94 <main+0x124>
  1457. 8000bea: bf00 nop
  1458. 8000bec: e000ed00 .word 0xe000ed00
  1459. 8000bf0: 58020400 .word 0x58020400
  1460. 8000bf4: 0800a944 .word 0x0800a944
  1461. 8000bf8: 089b3770 .word 0x089b3770
  1462. 8000bfc: 240013e0 .word 0x240013e0
  1463. 8000c00: 240011a4 .word 0x240011a4
  1464. 8000c04: 24000204 .word 0x24000204
  1465. 8000c08: 240011a8 .word 0x240011a8
  1466. 8000c0c: 240009d4 .word 0x240009d4
  1467. 08000c10 <SystemClock_Config>:
  1468. /**
  1469. * @brief System Clock Configuration
  1470. * @retval None
  1471. */
  1472. void SystemClock_Config(void)
  1473. {
  1474. 8000c10: b580 push {r7, lr}
  1475. 8000c12: b09c sub sp, #112 ; 0x70
  1476. 8000c14: af00 add r7, sp, #0
  1477. RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  1478. 8000c16: f107 0324 add.w r3, r7, #36 ; 0x24
  1479. 8000c1a: 224c movs r2, #76 ; 0x4c
  1480. 8000c1c: 2100 movs r1, #0
  1481. 8000c1e: 4618 mov r0, r3
  1482. 8000c20: f008 feb6 bl 8009990 <memset>
  1483. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  1484. 8000c24: 1d3b adds r3, r7, #4
  1485. 8000c26: 2220 movs r2, #32
  1486. 8000c28: 2100 movs r1, #0
  1487. 8000c2a: 4618 mov r0, r3
  1488. 8000c2c: f008 feb0 bl 8009990 <memset>
  1489. /** Supply configuration update enable
  1490. */
  1491. HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
  1492. 8000c30: 2002 movs r0, #2
  1493. 8000c32: f002 f9fb bl 800302c <HAL_PWREx_ConfigSupply>
  1494. /** Configure the main internal regulator output voltage
  1495. */
  1496. __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
  1497. 8000c36: 2300 movs r3, #0
  1498. 8000c38: 603b str r3, [r7, #0]
  1499. 8000c3a: 4b2c ldr r3, [pc, #176] ; (8000cec <SystemClock_Config+0xdc>)
  1500. 8000c3c: 699b ldr r3, [r3, #24]
  1501. 8000c3e: 4a2b ldr r2, [pc, #172] ; (8000cec <SystemClock_Config+0xdc>)
  1502. 8000c40: f423 4340 bic.w r3, r3, #49152 ; 0xc000
  1503. 8000c44: 6193 str r3, [r2, #24]
  1504. 8000c46: 4b29 ldr r3, [pc, #164] ; (8000cec <SystemClock_Config+0xdc>)
  1505. 8000c48: 699b ldr r3, [r3, #24]
  1506. 8000c4a: f403 4340 and.w r3, r3, #49152 ; 0xc000
  1507. 8000c4e: 603b str r3, [r7, #0]
  1508. 8000c50: 683b ldr r3, [r7, #0]
  1509. while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
  1510. 8000c52: bf00 nop
  1511. 8000c54: 4b25 ldr r3, [pc, #148] ; (8000cec <SystemClock_Config+0xdc>)
  1512. 8000c56: 699b ldr r3, [r3, #24]
  1513. 8000c58: f403 5300 and.w r3, r3, #8192 ; 0x2000
  1514. 8000c5c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
  1515. 8000c60: d1f8 bne.n 8000c54 <SystemClock_Config+0x44>
  1516. /** Initializes the RCC Oscillators according to the specified parameters
  1517. * in the RCC_OscInitTypeDef structure.
  1518. */
  1519. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
  1520. 8000c62: 2321 movs r3, #33 ; 0x21
  1521. 8000c64: 627b str r3, [r7, #36] ; 0x24
  1522. RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
  1523. 8000c66: f44f 23a0 mov.w r3, #327680 ; 0x50000
  1524. 8000c6a: 62bb str r3, [r7, #40] ; 0x28
  1525. RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
  1526. 8000c6c: 2301 movs r3, #1
  1527. 8000c6e: 63fb str r3, [r7, #60] ; 0x3c
  1528. RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  1529. 8000c70: 2302 movs r3, #2
  1530. 8000c72: 64bb str r3, [r7, #72] ; 0x48
  1531. RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  1532. 8000c74: 2302 movs r3, #2
  1533. 8000c76: 64fb str r3, [r7, #76] ; 0x4c
  1534. RCC_OscInitStruct.PLL.PLLM = 4;
  1535. 8000c78: 2304 movs r3, #4
  1536. 8000c7a: 653b str r3, [r7, #80] ; 0x50
  1537. RCC_OscInitStruct.PLL.PLLN = 275;
  1538. 8000c7c: f240 1313 movw r3, #275 ; 0x113
  1539. 8000c80: 657b str r3, [r7, #84] ; 0x54
  1540. RCC_OscInitStruct.PLL.PLLP = 1;
  1541. 8000c82: 2301 movs r3, #1
  1542. 8000c84: 65bb str r3, [r7, #88] ; 0x58
  1543. RCC_OscInitStruct.PLL.PLLQ = 4;
  1544. 8000c86: 2304 movs r3, #4
  1545. 8000c88: 65fb str r3, [r7, #92] ; 0x5c
  1546. RCC_OscInitStruct.PLL.PLLR = 2;
  1547. 8000c8a: 2302 movs r3, #2
  1548. 8000c8c: 663b str r3, [r7, #96] ; 0x60
  1549. RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
  1550. 8000c8e: 2304 movs r3, #4
  1551. 8000c90: 667b str r3, [r7, #100] ; 0x64
  1552. RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
  1553. 8000c92: 2300 movs r3, #0
  1554. 8000c94: 66bb str r3, [r7, #104] ; 0x68
  1555. RCC_OscInitStruct.PLL.PLLFRACN = 0;
  1556. 8000c96: 2300 movs r3, #0
  1557. 8000c98: 66fb str r3, [r7, #108] ; 0x6c
  1558. if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  1559. 8000c9a: f107 0324 add.w r3, r7, #36 ; 0x24
  1560. 8000c9e: 4618 mov r0, r3
  1561. 8000ca0: f002 fa0e bl 80030c0 <HAL_RCC_OscConfig>
  1562. 8000ca4: 4603 mov r3, r0
  1563. 8000ca6: 2b00 cmp r3, #0
  1564. 8000ca8: d001 beq.n 8000cae <SystemClock_Config+0x9e>
  1565. {
  1566. Error_Handler();
  1567. 8000caa: f000 fa61 bl 8001170 <Error_Handler>
  1568. }
  1569. /** Initializes the CPU, AHB and APB buses clocks
  1570. */
  1571. RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
  1572. 8000cae: 233f movs r3, #63 ; 0x3f
  1573. 8000cb0: 607b str r3, [r7, #4]
  1574. |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
  1575. |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
  1576. RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  1577. 8000cb2: 2303 movs r3, #3
  1578. 8000cb4: 60bb str r3, [r7, #8]
  1579. RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
  1580. 8000cb6: 2300 movs r3, #0
  1581. 8000cb8: 60fb str r3, [r7, #12]
  1582. RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
  1583. 8000cba: 2308 movs r3, #8
  1584. 8000cbc: 613b str r3, [r7, #16]
  1585. RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
  1586. 8000cbe: 2340 movs r3, #64 ; 0x40
  1587. 8000cc0: 617b str r3, [r7, #20]
  1588. RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
  1589. 8000cc2: 2340 movs r3, #64 ; 0x40
  1590. 8000cc4: 61bb str r3, [r7, #24]
  1591. RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
  1592. 8000cc6: f44f 6380 mov.w r3, #1024 ; 0x400
  1593. 8000cca: 61fb str r3, [r7, #28]
  1594. RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
  1595. 8000ccc: 2340 movs r3, #64 ; 0x40
  1596. 8000cce: 623b str r3, [r7, #32]
  1597. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
  1598. 8000cd0: 1d3b adds r3, r7, #4
  1599. 8000cd2: 2103 movs r1, #3
  1600. 8000cd4: 4618 mov r0, r3
  1601. 8000cd6: f002 fd9f bl 8003818 <HAL_RCC_ClockConfig>
  1602. 8000cda: 4603 mov r3, r0
  1603. 8000cdc: 2b00 cmp r3, #0
  1604. 8000cde: d001 beq.n 8000ce4 <SystemClock_Config+0xd4>
  1605. {
  1606. Error_Handler();
  1607. 8000ce0: f000 fa46 bl 8001170 <Error_Handler>
  1608. }
  1609. }
  1610. 8000ce4: bf00 nop
  1611. 8000ce6: 3770 adds r7, #112 ; 0x70
  1612. 8000ce8: 46bd mov sp, r7
  1613. 8000cea: bd80 pop {r7, pc}
  1614. 8000cec: 58024800 .word 0x58024800
  1615. 08000cf0 <MX_SPI1_Init>:
  1616. * @brief SPI1 Initialization Function
  1617. * @param None
  1618. * @retval None
  1619. */
  1620. static void MX_SPI1_Init(void)
  1621. {
  1622. 8000cf0: b580 push {r7, lr}
  1623. 8000cf2: b0be sub sp, #248 ; 0xf8
  1624. 8000cf4: af00 add r7, sp, #0
  1625. /* USER CODE BEGIN SPI1_Init 0 */
  1626. /* USER CODE END SPI1_Init 0 */
  1627. LL_SPI_InitTypeDef SPI_InitStruct = {0};
  1628. 8000cf6: f107 03d0 add.w r3, r7, #208 ; 0xd0
  1629. 8000cfa: 2228 movs r2, #40 ; 0x28
  1630. 8000cfc: 2100 movs r1, #0
  1631. 8000cfe: 4618 mov r0, r3
  1632. 8000d00: f008 fe46 bl 8009990 <memset>
  1633. LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
  1634. 8000d04: f107 03b8 add.w r3, r7, #184 ; 0xb8
  1635. 8000d08: 2200 movs r2, #0
  1636. 8000d0a: 601a str r2, [r3, #0]
  1637. 8000d0c: 605a str r2, [r3, #4]
  1638. 8000d0e: 609a str r2, [r3, #8]
  1639. 8000d10: 60da str r2, [r3, #12]
  1640. 8000d12: 611a str r2, [r3, #16]
  1641. 8000d14: 615a str r2, [r3, #20]
  1642. RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
  1643. 8000d16: 1d3b adds r3, r7, #4
  1644. 8000d18: 22b4 movs r2, #180 ; 0xb4
  1645. 8000d1a: 2100 movs r1, #0
  1646. 8000d1c: 4618 mov r0, r3
  1647. 8000d1e: f008 fe37 bl 8009990 <memset>
  1648. /** Initializes the peripherals clock
  1649. */
  1650. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI1;
  1651. 8000d22: f44f 5380 mov.w r3, #4096 ; 0x1000
  1652. 8000d26: 607b str r3, [r7, #4]
  1653. PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;
  1654. 8000d28: 2300 movs r3, #0
  1655. 8000d2a: 65fb str r3, [r7, #92] ; 0x5c
  1656. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  1657. 8000d2c: 1d3b adds r3, r7, #4
  1658. 8000d2e: 4618 mov r0, r3
  1659. 8000d30: f003 f8d2 bl 8003ed8 <HAL_RCCEx_PeriphCLKConfig>
  1660. 8000d34: 4603 mov r3, r0
  1661. 8000d36: 2b00 cmp r3, #0
  1662. 8000d38: d001 beq.n 8000d3e <MX_SPI1_Init+0x4e>
  1663. {
  1664. Error_Handler();
  1665. 8000d3a: f000 fa19 bl 8001170 <Error_Handler>
  1666. }
  1667. /* Peripheral clock enable */
  1668. LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1);
  1669. 8000d3e: f44f 5080 mov.w r0, #4096 ; 0x1000
  1670. 8000d42: f7ff fe27 bl 8000994 <LL_APB2_GRP1_EnableClock>
  1671. LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA);
  1672. 8000d46: 2001 movs r0, #1
  1673. 8000d48: f7ff fe08 bl 800095c <LL_AHB4_GRP1_EnableClock>
  1674. LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD);
  1675. 8000d4c: 2008 movs r0, #8
  1676. 8000d4e: f7ff fe05 bl 800095c <LL_AHB4_GRP1_EnableClock>
  1677. /**SPI1 GPIO Configuration
  1678. PA5 ------> SPI1_SCK
  1679. PA6 ------> SPI1_MISO
  1680. PD7 ------> SPI1_MOSI
  1681. */
  1682. GPIO_InitStruct.Pin = LL_GPIO_PIN_5|LL_GPIO_PIN_6;
  1683. 8000d52: 2360 movs r3, #96 ; 0x60
  1684. 8000d54: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
  1685. GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
  1686. 8000d58: 2302 movs r3, #2
  1687. 8000d5a: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
  1688. GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
  1689. 8000d5e: 2303 movs r3, #3
  1690. 8000d60: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
  1691. GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
  1692. 8000d64: 2300 movs r3, #0
  1693. 8000d66: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
  1694. GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
  1695. 8000d6a: 2300 movs r3, #0
  1696. 8000d6c: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
  1697. GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
  1698. 8000d70: 2305 movs r3, #5
  1699. 8000d72: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
  1700. LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  1701. 8000d76: f107 03b8 add.w r3, r7, #184 ; 0xb8
  1702. 8000d7a: 4619 mov r1, r3
  1703. 8000d7c: 4826 ldr r0, [pc, #152] ; (8000e18 <MX_SPI1_Init+0x128>)
  1704. 8000d7e: f004 feff bl 8005b80 <LL_GPIO_Init>
  1705. GPIO_InitStruct.Pin = LL_GPIO_PIN_7;
  1706. 8000d82: 2380 movs r3, #128 ; 0x80
  1707. 8000d84: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
  1708. GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
  1709. 8000d88: 2302 movs r3, #2
  1710. 8000d8a: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
  1711. GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
  1712. 8000d8e: 2303 movs r3, #3
  1713. 8000d90: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
  1714. GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
  1715. 8000d94: 2300 movs r3, #0
  1716. 8000d96: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
  1717. GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
  1718. 8000d9a: 2300 movs r3, #0
  1719. 8000d9c: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
  1720. GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
  1721. 8000da0: 2305 movs r3, #5
  1722. 8000da2: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
  1723. LL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  1724. 8000da6: f107 03b8 add.w r3, r7, #184 ; 0xb8
  1725. 8000daa: 4619 mov r1, r3
  1726. 8000dac: 481b ldr r0, [pc, #108] ; (8000e1c <MX_SPI1_Init+0x12c>)
  1727. 8000dae: f004 fee7 bl 8005b80 <LL_GPIO_Init>
  1728. /* USER CODE BEGIN SPI1_Init 1 */
  1729. /* USER CODE END SPI1_Init 1 */
  1730. /* SPI1 parameter configuration*/
  1731. SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX;
  1732. 8000db2: 2300 movs r3, #0
  1733. 8000db4: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
  1734. SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
  1735. 8000db8: f44f 0380 mov.w r3, #4194304 ; 0x400000
  1736. 8000dbc: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4
  1737. SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_8BIT;
  1738. 8000dc0: 2307 movs r3, #7
  1739. 8000dc2: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
  1740. SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW;
  1741. 8000dc6: 2300 movs r3, #0
  1742. 8000dc8: f8c7 30dc str.w r3, [r7, #220] ; 0xdc
  1743. SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
  1744. 8000dcc: 2300 movs r3, #0
  1745. 8000dce: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0
  1746. SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
  1747. 8000dd2: f04f 6380 mov.w r3, #67108864 ; 0x4000000
  1748. 8000dd6: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4
  1749. SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV32;
  1750. 8000dda: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
  1751. 8000dde: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8
  1752. SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
  1753. 8000de2: 2300 movs r3, #0
  1754. 8000de4: f8c7 30ec str.w r3, [r7, #236] ; 0xec
  1755. SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
  1756. 8000de8: 2300 movs r3, #0
  1757. 8000dea: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0
  1758. SPI_InitStruct.CRCPoly = 0x0;
  1759. 8000dee: 2300 movs r3, #0
  1760. 8000df0: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4
  1761. LL_SPI_Init(SPI1, &SPI_InitStruct);
  1762. 8000df4: f107 03d0 add.w r3, r7, #208 ; 0xd0
  1763. 8000df8: 4619 mov r1, r3
  1764. 8000dfa: 4809 ldr r0, [pc, #36] ; (8000e20 <MX_SPI1_Init+0x130>)
  1765. 8000dfc: f004 ff70 bl 8005ce0 <LL_SPI_Init>
  1766. LL_SPI_SetStandard(SPI1, LL_SPI_PROTOCOL_MOTOROLA);
  1767. 8000e00: 2100 movs r1, #0
  1768. 8000e02: 4807 ldr r0, [pc, #28] ; (8000e20 <MX_SPI1_Init+0x130>)
  1769. 8000e04: f7ff fd87 bl 8000916 <LL_SPI_SetStandard>
  1770. LL_SPI_EnableNSSPulseMgt(SPI1);
  1771. 8000e08: 4805 ldr r0, [pc, #20] ; (8000e20 <MX_SPI1_Init+0x130>)
  1772. 8000e0a: f7ff fd97 bl 800093c <LL_SPI_EnableNSSPulseMgt>
  1773. /* USER CODE BEGIN SPI1_Init 2 */
  1774. /* USER CODE END SPI1_Init 2 */
  1775. }
  1776. 8000e0e: bf00 nop
  1777. 8000e10: 37f8 adds r7, #248 ; 0xf8
  1778. 8000e12: 46bd mov sp, r7
  1779. 8000e14: bd80 pop {r7, pc}
  1780. 8000e16: bf00 nop
  1781. 8000e18: 58020000 .word 0x58020000
  1782. 8000e1c: 58020c00 .word 0x58020c00
  1783. 8000e20: 40013000 .word 0x40013000
  1784. 08000e24 <MX_TIM3_Init>:
  1785. * @brief TIM3 Initialization Function
  1786. * @param None
  1787. * @retval None
  1788. */
  1789. static void MX_TIM3_Init(void)
  1790. {
  1791. 8000e24: b580 push {r7, lr}
  1792. 8000e26: b088 sub sp, #32
  1793. 8000e28: af00 add r7, sp, #0
  1794. /* USER CODE BEGIN TIM3_Init 0 */
  1795. /* USER CODE END TIM3_Init 0 */
  1796. TIM_ClockConfigTypeDef sClockSourceConfig = {0};
  1797. 8000e2a: f107 0310 add.w r3, r7, #16
  1798. 8000e2e: 2200 movs r2, #0
  1799. 8000e30: 601a str r2, [r3, #0]
  1800. 8000e32: 605a str r2, [r3, #4]
  1801. 8000e34: 609a str r2, [r3, #8]
  1802. 8000e36: 60da str r2, [r3, #12]
  1803. TIM_MasterConfigTypeDef sMasterConfig = {0};
  1804. 8000e38: 1d3b adds r3, r7, #4
  1805. 8000e3a: 2200 movs r2, #0
  1806. 8000e3c: 601a str r2, [r3, #0]
  1807. 8000e3e: 605a str r2, [r3, #4]
  1808. 8000e40: 609a str r2, [r3, #8]
  1809. /* USER CODE BEGIN TIM3_Init 1 */
  1810. /* USER CODE END TIM3_Init 1 */
  1811. htim3.Instance = TIM3;
  1812. 8000e42: 4b1d ldr r3, [pc, #116] ; (8000eb8 <MX_TIM3_Init+0x94>)
  1813. 8000e44: 4a1d ldr r2, [pc, #116] ; (8000ebc <MX_TIM3_Init+0x98>)
  1814. 8000e46: 601a str r2, [r3, #0]
  1815. htim3.Init.Prescaler = 0;
  1816. 8000e48: 4b1b ldr r3, [pc, #108] ; (8000eb8 <MX_TIM3_Init+0x94>)
  1817. 8000e4a: 2200 movs r2, #0
  1818. 8000e4c: 605a str r2, [r3, #4]
  1819. htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
  1820. 8000e4e: 4b1a ldr r3, [pc, #104] ; (8000eb8 <MX_TIM3_Init+0x94>)
  1821. 8000e50: 2200 movs r2, #0
  1822. 8000e52: 609a str r2, [r3, #8]
  1823. htim3.Init.Period = 6875;
  1824. 8000e54: 4b18 ldr r3, [pc, #96] ; (8000eb8 <MX_TIM3_Init+0x94>)
  1825. 8000e56: f641 22db movw r2, #6875 ; 0x1adb
  1826. 8000e5a: 60da str r2, [r3, #12]
  1827. htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  1828. 8000e5c: 4b16 ldr r3, [pc, #88] ; (8000eb8 <MX_TIM3_Init+0x94>)
  1829. 8000e5e: 2200 movs r2, #0
  1830. 8000e60: 611a str r2, [r3, #16]
  1831. htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
  1832. 8000e62: 4b15 ldr r3, [pc, #84] ; (8000eb8 <MX_TIM3_Init+0x94>)
  1833. 8000e64: 2280 movs r2, #128 ; 0x80
  1834. 8000e66: 619a str r2, [r3, #24]
  1835. if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
  1836. 8000e68: 4813 ldr r0, [pc, #76] ; (8000eb8 <MX_TIM3_Init+0x94>)
  1837. 8000e6a: f004 f893 bl 8004f94 <HAL_TIM_Base_Init>
  1838. 8000e6e: 4603 mov r3, r0
  1839. 8000e70: 2b00 cmp r3, #0
  1840. 8000e72: d001 beq.n 8000e78 <MX_TIM3_Init+0x54>
  1841. {
  1842. Error_Handler();
  1843. 8000e74: f000 f97c bl 8001170 <Error_Handler>
  1844. }
  1845. sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  1846. 8000e78: f44f 5380 mov.w r3, #4096 ; 0x1000
  1847. 8000e7c: 613b str r3, [r7, #16]
  1848. if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
  1849. 8000e7e: f107 0310 add.w r3, r7, #16
  1850. 8000e82: 4619 mov r1, r3
  1851. 8000e84: 480c ldr r0, [pc, #48] ; (8000eb8 <MX_TIM3_Init+0x94>)
  1852. 8000e86: f004 fa83 bl 8005390 <HAL_TIM_ConfigClockSource>
  1853. 8000e8a: 4603 mov r3, r0
  1854. 8000e8c: 2b00 cmp r3, #0
  1855. 8000e8e: d001 beq.n 8000e94 <MX_TIM3_Init+0x70>
  1856. {
  1857. Error_Handler();
  1858. 8000e90: f000 f96e bl 8001170 <Error_Handler>
  1859. }
  1860. sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
  1861. 8000e94: 2300 movs r3, #0
  1862. 8000e96: 607b str r3, [r7, #4]
  1863. sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  1864. 8000e98: 2300 movs r3, #0
  1865. 8000e9a: 60fb str r3, [r7, #12]
  1866. if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
  1867. 8000e9c: 1d3b adds r3, r7, #4
  1868. 8000e9e: 4619 mov r1, r3
  1869. 8000ea0: 4805 ldr r0, [pc, #20] ; (8000eb8 <MX_TIM3_Init+0x94>)
  1870. 8000ea2: f004 fcd9 bl 8005858 <HAL_TIMEx_MasterConfigSynchronization>
  1871. 8000ea6: 4603 mov r3, r0
  1872. 8000ea8: 2b00 cmp r3, #0
  1873. 8000eaa: d001 beq.n 8000eb0 <MX_TIM3_Init+0x8c>
  1874. {
  1875. Error_Handler();
  1876. 8000eac: f000 f960 bl 8001170 <Error_Handler>
  1877. }
  1878. /* USER CODE BEGIN TIM3_Init 2 */
  1879. /* USER CODE END TIM3_Init 2 */
  1880. }
  1881. 8000eb0: bf00 nop
  1882. 8000eb2: 3720 adds r7, #32
  1883. 8000eb4: 46bd mov sp, r7
  1884. 8000eb6: bd80 pop {r7, pc}
  1885. 8000eb8: 240013e0 .word 0x240013e0
  1886. 8000ebc: 40000400 .word 0x40000400
  1887. 08000ec0 <MX_GPIO_Init>:
  1888. * @brief GPIO Initialization Function
  1889. * @param None
  1890. * @retval None
  1891. */
  1892. static void MX_GPIO_Init(void)
  1893. {
  1894. 8000ec0: b580 push {r7, lr}
  1895. 8000ec2: b08c sub sp, #48 ; 0x30
  1896. 8000ec4: af00 add r7, sp, #0
  1897. GPIO_InitTypeDef GPIO_InitStruct = {0};
  1898. 8000ec6: f107 031c add.w r3, r7, #28
  1899. 8000eca: 2200 movs r2, #0
  1900. 8000ecc: 601a str r2, [r3, #0]
  1901. 8000ece: 605a str r2, [r3, #4]
  1902. 8000ed0: 609a str r2, [r3, #8]
  1903. 8000ed2: 60da str r2, [r3, #12]
  1904. 8000ed4: 611a str r2, [r3, #16]
  1905. /* GPIO Ports Clock Enable */
  1906. __HAL_RCC_GPIOC_CLK_ENABLE();
  1907. 8000ed6: 4b9f ldr r3, [pc, #636] ; (8001154 <MX_GPIO_Init+0x294>)
  1908. 8000ed8: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1909. 8000edc: 4a9d ldr r2, [pc, #628] ; (8001154 <MX_GPIO_Init+0x294>)
  1910. 8000ede: f043 0304 orr.w r3, r3, #4
  1911. 8000ee2: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0
  1912. 8000ee6: 4b9b ldr r3, [pc, #620] ; (8001154 <MX_GPIO_Init+0x294>)
  1913. 8000ee8: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1914. 8000eec: f003 0304 and.w r3, r3, #4
  1915. 8000ef0: 61bb str r3, [r7, #24]
  1916. 8000ef2: 69bb ldr r3, [r7, #24]
  1917. __HAL_RCC_GPIOH_CLK_ENABLE();
  1918. 8000ef4: 4b97 ldr r3, [pc, #604] ; (8001154 <MX_GPIO_Init+0x294>)
  1919. 8000ef6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1920. 8000efa: 4a96 ldr r2, [pc, #600] ; (8001154 <MX_GPIO_Init+0x294>)
  1921. 8000efc: f043 0380 orr.w r3, r3, #128 ; 0x80
  1922. 8000f00: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0
  1923. 8000f04: 4b93 ldr r3, [pc, #588] ; (8001154 <MX_GPIO_Init+0x294>)
  1924. 8000f06: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1925. 8000f0a: f003 0380 and.w r3, r3, #128 ; 0x80
  1926. 8000f0e: 617b str r3, [r7, #20]
  1927. 8000f10: 697b ldr r3, [r7, #20]
  1928. __HAL_RCC_GPIOA_CLK_ENABLE();
  1929. 8000f12: 4b90 ldr r3, [pc, #576] ; (8001154 <MX_GPIO_Init+0x294>)
  1930. 8000f14: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1931. 8000f18: 4a8e ldr r2, [pc, #568] ; (8001154 <MX_GPIO_Init+0x294>)
  1932. 8000f1a: f043 0301 orr.w r3, r3, #1
  1933. 8000f1e: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0
  1934. 8000f22: 4b8c ldr r3, [pc, #560] ; (8001154 <MX_GPIO_Init+0x294>)
  1935. 8000f24: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1936. 8000f28: f003 0301 and.w r3, r3, #1
  1937. 8000f2c: 613b str r3, [r7, #16]
  1938. 8000f2e: 693b ldr r3, [r7, #16]
  1939. __HAL_RCC_GPIOB_CLK_ENABLE();
  1940. 8000f30: 4b88 ldr r3, [pc, #544] ; (8001154 <MX_GPIO_Init+0x294>)
  1941. 8000f32: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1942. 8000f36: 4a87 ldr r2, [pc, #540] ; (8001154 <MX_GPIO_Init+0x294>)
  1943. 8000f38: f043 0302 orr.w r3, r3, #2
  1944. 8000f3c: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0
  1945. 8000f40: 4b84 ldr r3, [pc, #528] ; (8001154 <MX_GPIO_Init+0x294>)
  1946. 8000f42: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1947. 8000f46: f003 0302 and.w r3, r3, #2
  1948. 8000f4a: 60fb str r3, [r7, #12]
  1949. 8000f4c: 68fb ldr r3, [r7, #12]
  1950. __HAL_RCC_GPIOD_CLK_ENABLE();
  1951. 8000f4e: 4b81 ldr r3, [pc, #516] ; (8001154 <MX_GPIO_Init+0x294>)
  1952. 8000f50: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1953. 8000f54: 4a7f ldr r2, [pc, #508] ; (8001154 <MX_GPIO_Init+0x294>)
  1954. 8000f56: f043 0308 orr.w r3, r3, #8
  1955. 8000f5a: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0
  1956. 8000f5e: 4b7d ldr r3, [pc, #500] ; (8001154 <MX_GPIO_Init+0x294>)
  1957. 8000f60: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1958. 8000f64: f003 0308 and.w r3, r3, #8
  1959. 8000f68: 60bb str r3, [r7, #8]
  1960. 8000f6a: 68bb ldr r3, [r7, #8]
  1961. __HAL_RCC_GPIOG_CLK_ENABLE();
  1962. 8000f6c: 4b79 ldr r3, [pc, #484] ; (8001154 <MX_GPIO_Init+0x294>)
  1963. 8000f6e: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1964. 8000f72: 4a78 ldr r2, [pc, #480] ; (8001154 <MX_GPIO_Init+0x294>)
  1965. 8000f74: f043 0340 orr.w r3, r3, #64 ; 0x40
  1966. 8000f78: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0
  1967. 8000f7c: 4b75 ldr r3, [pc, #468] ; (8001154 <MX_GPIO_Init+0x294>)
  1968. 8000f7e: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1969. 8000f82: f003 0340 and.w r3, r3, #64 ; 0x40
  1970. 8000f86: 607b str r3, [r7, #4]
  1971. 8000f88: 687b ldr r3, [r7, #4]
  1972. __HAL_RCC_GPIOE_CLK_ENABLE();
  1973. 8000f8a: 4b72 ldr r3, [pc, #456] ; (8001154 <MX_GPIO_Init+0x294>)
  1974. 8000f8c: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1975. 8000f90: 4a70 ldr r2, [pc, #448] ; (8001154 <MX_GPIO_Init+0x294>)
  1976. 8000f92: f043 0310 orr.w r3, r3, #16
  1977. 8000f96: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0
  1978. 8000f9a: 4b6e ldr r3, [pc, #440] ; (8001154 <MX_GPIO_Init+0x294>)
  1979. 8000f9c: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  1980. 8000fa0: f003 0310 and.w r3, r3, #16
  1981. 8000fa4: 603b str r3, [r7, #0]
  1982. 8000fa6: 683b ldr r3, [r7, #0]
  1983. /*Configure GPIO pin Output Level */
  1984. HAL_GPIO_WritePin(GPIOB, LED_GREEN_Pin|CC1200_RESET_Pin|LED_RED_Pin, GPIO_PIN_RESET);
  1985. 8000fa8: 2200 movs r2, #0
  1986. 8000faa: f245 0101 movw r1, #20481 ; 0x5001
  1987. 8000fae: 486a ldr r0, [pc, #424] ; (8001158 <MX_GPIO_Init+0x298>)
  1988. 8000fb0: f000 fe3a bl 8001c28 <HAL_GPIO_WritePin>
  1989. /*Configure GPIO pin Output Level */
  1990. HAL_GPIO_WritePin(CC1200_TCXO_ENABLE_GPIO_Port, CC1200_TCXO_ENABLE_Pin, GPIO_PIN_SET);
  1991. 8000fb4: 2201 movs r2, #1
  1992. 8000fb6: f44f 4100 mov.w r1, #32768 ; 0x8000
  1993. 8000fba: 4867 ldr r0, [pc, #412] ; (8001158 <MX_GPIO_Init+0x298>)
  1994. 8000fbc: f000 fe34 bl 8001c28 <HAL_GPIO_WritePin>
  1995. /*Configure GPIO pin Output Level */
  1996. HAL_GPIO_WritePin(USB_FS_PWR_EN_GPIO_Port, USB_FS_PWR_EN_Pin, GPIO_PIN_RESET);
  1997. 8000fc0: 2200 movs r2, #0
  1998. 8000fc2: f44f 6180 mov.w r1, #1024 ; 0x400
  1999. 8000fc6: 4865 ldr r0, [pc, #404] ; (800115c <MX_GPIO_Init+0x29c>)
  2000. 8000fc8: f000 fe2e bl 8001c28 <HAL_GPIO_WritePin>
  2001. /*Configure GPIO pin Output Level */
  2002. HAL_GPIO_WritePin(CC1200_CS_GPIO_Port, CC1200_CS_Pin, GPIO_PIN_SET);
  2003. 8000fcc: 2201 movs r2, #1
  2004. 8000fce: 2140 movs r1, #64 ; 0x40
  2005. 8000fd0: 4863 ldr r0, [pc, #396] ; (8001160 <MX_GPIO_Init+0x2a0>)
  2006. 8000fd2: f000 fe29 bl 8001c28 <HAL_GPIO_WritePin>
  2007. /*Configure GPIO pin Output Level */
  2008. HAL_GPIO_WritePin(LED_YELLOW_GPIO_Port, LED_YELLOW_Pin, GPIO_PIN_RESET);
  2009. 8000fd6: 2200 movs r2, #0
  2010. 8000fd8: 2102 movs r1, #2
  2011. 8000fda: 4862 ldr r0, [pc, #392] ; (8001164 <MX_GPIO_Init+0x2a4>)
  2012. 8000fdc: f000 fe24 bl 8001c28 <HAL_GPIO_WritePin>
  2013. /*Configure GPIO pin : B1_Pin */
  2014. GPIO_InitStruct.Pin = B1_Pin;
  2015. 8000fe0: f44f 5300 mov.w r3, #8192 ; 0x2000
  2016. 8000fe4: 61fb str r3, [r7, #28]
  2017. GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  2018. 8000fe6: 2300 movs r3, #0
  2019. 8000fe8: 623b str r3, [r7, #32]
  2020. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2021. 8000fea: 2300 movs r3, #0
  2022. 8000fec: 627b str r3, [r7, #36] ; 0x24
  2023. HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
  2024. 8000fee: f107 031c add.w r3, r7, #28
  2025. 8000ff2: 4619 mov r1, r3
  2026. 8000ff4: 485a ldr r0, [pc, #360] ; (8001160 <MX_GPIO_Init+0x2a0>)
  2027. 8000ff6: f000 fc6f bl 80018d8 <HAL_GPIO_Init>
  2028. /*Configure GPIO pins : PC1 PC4 PC5 */
  2029. GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
  2030. 8000ffa: 2332 movs r3, #50 ; 0x32
  2031. 8000ffc: 61fb str r3, [r7, #28]
  2032. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  2033. 8000ffe: 2302 movs r3, #2
  2034. 8001000: 623b str r3, [r7, #32]
  2035. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2036. 8001002: 2300 movs r3, #0
  2037. 8001004: 627b str r3, [r7, #36] ; 0x24
  2038. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  2039. 8001006: 2303 movs r3, #3
  2040. 8001008: 62bb str r3, [r7, #40] ; 0x28
  2041. GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
  2042. 800100a: 230b movs r3, #11
  2043. 800100c: 62fb str r3, [r7, #44] ; 0x2c
  2044. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  2045. 800100e: f107 031c add.w r3, r7, #28
  2046. 8001012: 4619 mov r1, r3
  2047. 8001014: 4852 ldr r0, [pc, #328] ; (8001160 <MX_GPIO_Init+0x2a0>)
  2048. 8001016: f000 fc5f bl 80018d8 <HAL_GPIO_Init>
  2049. /*Configure GPIO pins : PA1 PA2 PA7 */
  2050. GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
  2051. 800101a: 2386 movs r3, #134 ; 0x86
  2052. 800101c: 61fb str r3, [r7, #28]
  2053. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  2054. 800101e: 2302 movs r3, #2
  2055. 8001020: 623b str r3, [r7, #32]
  2056. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2057. 8001022: 2300 movs r3, #0
  2058. 8001024: 627b str r3, [r7, #36] ; 0x24
  2059. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  2060. 8001026: 2303 movs r3, #3
  2061. 8001028: 62bb str r3, [r7, #40] ; 0x28
  2062. GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
  2063. 800102a: 230b movs r3, #11
  2064. 800102c: 62fb str r3, [r7, #44] ; 0x2c
  2065. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  2066. 800102e: f107 031c add.w r3, r7, #28
  2067. 8001032: 4619 mov r1, r3
  2068. 8001034: 484c ldr r0, [pc, #304] ; (8001168 <MX_GPIO_Init+0x2a8>)
  2069. 8001036: f000 fc4f bl 80018d8 <HAL_GPIO_Init>
  2070. /*Configure GPIO pins : LED_GREEN_Pin LED_RED_Pin */
  2071. GPIO_InitStruct.Pin = LED_GREEN_Pin|LED_RED_Pin;
  2072. 800103a: f244 0301 movw r3, #16385 ; 0x4001
  2073. 800103e: 61fb str r3, [r7, #28]
  2074. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  2075. 8001040: 2301 movs r3, #1
  2076. 8001042: 623b str r3, [r7, #32]
  2077. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2078. 8001044: 2300 movs r3, #0
  2079. 8001046: 627b str r3, [r7, #36] ; 0x24
  2080. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  2081. 8001048: 2300 movs r3, #0
  2082. 800104a: 62bb str r3, [r7, #40] ; 0x28
  2083. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  2084. 800104c: f107 031c add.w r3, r7, #28
  2085. 8001050: 4619 mov r1, r3
  2086. 8001052: 4841 ldr r0, [pc, #260] ; (8001158 <MX_GPIO_Init+0x298>)
  2087. 8001054: f000 fc40 bl 80018d8 <HAL_GPIO_Init>
  2088. /*Configure GPIO pins : CC1200_RESET_Pin CC1200_TCXO_ENABLE_Pin */
  2089. GPIO_InitStruct.Pin = CC1200_RESET_Pin|CC1200_TCXO_ENABLE_Pin;
  2090. 8001058: f44f 4310 mov.w r3, #36864 ; 0x9000
  2091. 800105c: 61fb str r3, [r7, #28]
  2092. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  2093. 800105e: 2301 movs r3, #1
  2094. 8001060: 623b str r3, [r7, #32]
  2095. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2096. 8001062: 2300 movs r3, #0
  2097. 8001064: 627b str r3, [r7, #36] ; 0x24
  2098. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  2099. 8001066: 2303 movs r3, #3
  2100. 8001068: 62bb str r3, [r7, #40] ; 0x28
  2101. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  2102. 800106a: f107 031c add.w r3, r7, #28
  2103. 800106e: 4619 mov r1, r3
  2104. 8001070: 4839 ldr r0, [pc, #228] ; (8001158 <MX_GPIO_Init+0x298>)
  2105. 8001072: f000 fc31 bl 80018d8 <HAL_GPIO_Init>
  2106. /*Configure GPIO pin : PB13 */
  2107. GPIO_InitStruct.Pin = GPIO_PIN_13;
  2108. 8001076: f44f 5300 mov.w r3, #8192 ; 0x2000
  2109. 800107a: 61fb str r3, [r7, #28]
  2110. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  2111. 800107c: 2302 movs r3, #2
  2112. 800107e: 623b str r3, [r7, #32]
  2113. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2114. 8001080: 2300 movs r3, #0
  2115. 8001082: 627b str r3, [r7, #36] ; 0x24
  2116. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  2117. 8001084: 2303 movs r3, #3
  2118. 8001086: 62bb str r3, [r7, #40] ; 0x28
  2119. GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
  2120. 8001088: 230b movs r3, #11
  2121. 800108a: 62fb str r3, [r7, #44] ; 0x2c
  2122. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  2123. 800108c: f107 031c add.w r3, r7, #28
  2124. 8001090: 4619 mov r1, r3
  2125. 8001092: 4831 ldr r0, [pc, #196] ; (8001158 <MX_GPIO_Init+0x298>)
  2126. 8001094: f000 fc20 bl 80018d8 <HAL_GPIO_Init>
  2127. /*Configure GPIO pins : STLK_VCP_RX_Pin STLK_VCP_TX_Pin */
  2128. GPIO_InitStruct.Pin = STLK_VCP_RX_Pin|STLK_VCP_TX_Pin;
  2129. 8001098: f44f 7340 mov.w r3, #768 ; 0x300
  2130. 800109c: 61fb str r3, [r7, #28]
  2131. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  2132. 800109e: 2302 movs r3, #2
  2133. 80010a0: 623b str r3, [r7, #32]
  2134. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2135. 80010a2: 2300 movs r3, #0
  2136. 80010a4: 627b str r3, [r7, #36] ; 0x24
  2137. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  2138. 80010a6: 2300 movs r3, #0
  2139. 80010a8: 62bb str r3, [r7, #40] ; 0x28
  2140. GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
  2141. 80010aa: 2307 movs r3, #7
  2142. 80010ac: 62fb str r3, [r7, #44] ; 0x2c
  2143. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  2144. 80010ae: f107 031c add.w r3, r7, #28
  2145. 80010b2: 4619 mov r1, r3
  2146. 80010b4: 4829 ldr r0, [pc, #164] ; (800115c <MX_GPIO_Init+0x29c>)
  2147. 80010b6: f000 fc0f bl 80018d8 <HAL_GPIO_Init>
  2148. /*Configure GPIO pin : USB_FS_PWR_EN_Pin */
  2149. GPIO_InitStruct.Pin = USB_FS_PWR_EN_Pin;
  2150. 80010ba: f44f 6380 mov.w r3, #1024 ; 0x400
  2151. 80010be: 61fb str r3, [r7, #28]
  2152. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  2153. 80010c0: 2301 movs r3, #1
  2154. 80010c2: 623b str r3, [r7, #32]
  2155. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2156. 80010c4: 2300 movs r3, #0
  2157. 80010c6: 627b str r3, [r7, #36] ; 0x24
  2158. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  2159. 80010c8: 2300 movs r3, #0
  2160. 80010ca: 62bb str r3, [r7, #40] ; 0x28
  2161. HAL_GPIO_Init(USB_FS_PWR_EN_GPIO_Port, &GPIO_InitStruct);
  2162. 80010cc: f107 031c add.w r3, r7, #28
  2163. 80010d0: 4619 mov r1, r3
  2164. 80010d2: 4822 ldr r0, [pc, #136] ; (800115c <MX_GPIO_Init+0x29c>)
  2165. 80010d4: f000 fc00 bl 80018d8 <HAL_GPIO_Init>
  2166. /*Configure GPIO pin : USB_FS_OVCR_Pin */
  2167. GPIO_InitStruct.Pin = USB_FS_OVCR_Pin;
  2168. 80010d8: 2380 movs r3, #128 ; 0x80
  2169. 80010da: 61fb str r3, [r7, #28]
  2170. GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
  2171. 80010dc: f44f 1388 mov.w r3, #1114112 ; 0x110000
  2172. 80010e0: 623b str r3, [r7, #32]
  2173. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2174. 80010e2: 2300 movs r3, #0
  2175. 80010e4: 627b str r3, [r7, #36] ; 0x24
  2176. HAL_GPIO_Init(USB_FS_OVCR_GPIO_Port, &GPIO_InitStruct);
  2177. 80010e6: f107 031c add.w r3, r7, #28
  2178. 80010ea: 4619 mov r1, r3
  2179. 80010ec: 481f ldr r0, [pc, #124] ; (800116c <MX_GPIO_Init+0x2ac>)
  2180. 80010ee: f000 fbf3 bl 80018d8 <HAL_GPIO_Init>
  2181. /*Configure GPIO pin : CC1200_CS_Pin */
  2182. GPIO_InitStruct.Pin = CC1200_CS_Pin;
  2183. 80010f2: 2340 movs r3, #64 ; 0x40
  2184. 80010f4: 61fb str r3, [r7, #28]
  2185. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  2186. 80010f6: 2301 movs r3, #1
  2187. 80010f8: 623b str r3, [r7, #32]
  2188. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2189. 80010fa: 2300 movs r3, #0
  2190. 80010fc: 627b str r3, [r7, #36] ; 0x24
  2191. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  2192. 80010fe: 2303 movs r3, #3
  2193. 8001100: 62bb str r3, [r7, #40] ; 0x28
  2194. HAL_GPIO_Init(CC1200_CS_GPIO_Port, &GPIO_InitStruct);
  2195. 8001102: f107 031c add.w r3, r7, #28
  2196. 8001106: 4619 mov r1, r3
  2197. 8001108: 4815 ldr r0, [pc, #84] ; (8001160 <MX_GPIO_Init+0x2a0>)
  2198. 800110a: f000 fbe5 bl 80018d8 <HAL_GPIO_Init>
  2199. /*Configure GPIO pins : PG11 PG13 */
  2200. GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13;
  2201. 800110e: f44f 5320 mov.w r3, #10240 ; 0x2800
  2202. 8001112: 61fb str r3, [r7, #28]
  2203. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  2204. 8001114: 2302 movs r3, #2
  2205. 8001116: 623b str r3, [r7, #32]
  2206. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2207. 8001118: 2300 movs r3, #0
  2208. 800111a: 627b str r3, [r7, #36] ; 0x24
  2209. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  2210. 800111c: 2303 movs r3, #3
  2211. 800111e: 62bb str r3, [r7, #40] ; 0x28
  2212. GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
  2213. 8001120: 230b movs r3, #11
  2214. 8001122: 62fb str r3, [r7, #44] ; 0x2c
  2215. HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
  2216. 8001124: f107 031c add.w r3, r7, #28
  2217. 8001128: 4619 mov r1, r3
  2218. 800112a: 4810 ldr r0, [pc, #64] ; (800116c <MX_GPIO_Init+0x2ac>)
  2219. 800112c: f000 fbd4 bl 80018d8 <HAL_GPIO_Init>
  2220. /*Configure GPIO pin : LED_YELLOW_Pin */
  2221. GPIO_InitStruct.Pin = LED_YELLOW_Pin;
  2222. 8001130: 2302 movs r3, #2
  2223. 8001132: 61fb str r3, [r7, #28]
  2224. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  2225. 8001134: 2301 movs r3, #1
  2226. 8001136: 623b str r3, [r7, #32]
  2227. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2228. 8001138: 2300 movs r3, #0
  2229. 800113a: 627b str r3, [r7, #36] ; 0x24
  2230. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  2231. 800113c: 2300 movs r3, #0
  2232. 800113e: 62bb str r3, [r7, #40] ; 0x28
  2233. HAL_GPIO_Init(LED_YELLOW_GPIO_Port, &GPIO_InitStruct);
  2234. 8001140: f107 031c add.w r3, r7, #28
  2235. 8001144: 4619 mov r1, r3
  2236. 8001146: 4807 ldr r0, [pc, #28] ; (8001164 <MX_GPIO_Init+0x2a4>)
  2237. 8001148: f000 fbc6 bl 80018d8 <HAL_GPIO_Init>
  2238. }
  2239. 800114c: bf00 nop
  2240. 800114e: 3730 adds r7, #48 ; 0x30
  2241. 8001150: 46bd mov sp, r7
  2242. 8001152: bd80 pop {r7, pc}
  2243. 8001154: 58024400 .word 0x58024400
  2244. 8001158: 58020400 .word 0x58020400
  2245. 800115c: 58020c00 .word 0x58020c00
  2246. 8001160: 58020800 .word 0x58020800
  2247. 8001164: 58021000 .word 0x58021000
  2248. 8001168: 58020000 .word 0x58020000
  2249. 800116c: 58021800 .word 0x58021800
  2250. 08001170 <Error_Handler>:
  2251. /**
  2252. * @brief This function is executed in case of error occurrence.
  2253. * @retval None
  2254. */
  2255. void Error_Handler(void)
  2256. {
  2257. 8001170: b480 push {r7}
  2258. 8001172: af00 add r7, sp, #0
  2259. __ASM volatile ("cpsid i" : : : "memory");
  2260. 8001174: b672 cpsid i
  2261. }
  2262. 8001176: bf00 nop
  2263. /* USER CODE BEGIN Error_Handler_Debug */
  2264. /* User can add his own implementation to report the HAL error return state */
  2265. __disable_irq();
  2266. while (1)
  2267. 8001178: e7fe b.n 8001178 <Error_Handler+0x8>
  2268. ...
  2269. 0800117c <HAL_MspInit>:
  2270. /* USER CODE END 0 */
  2271. /**
  2272. * Initializes the Global MSP.
  2273. */
  2274. void HAL_MspInit(void)
  2275. {
  2276. 800117c: b480 push {r7}
  2277. 800117e: b083 sub sp, #12
  2278. 8001180: af00 add r7, sp, #0
  2279. /* USER CODE BEGIN MspInit 0 */
  2280. /* USER CODE END MspInit 0 */
  2281. __HAL_RCC_SYSCFG_CLK_ENABLE();
  2282. 8001182: 4b0a ldr r3, [pc, #40] ; (80011ac <HAL_MspInit+0x30>)
  2283. 8001184: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4
  2284. 8001188: 4a08 ldr r2, [pc, #32] ; (80011ac <HAL_MspInit+0x30>)
  2285. 800118a: f043 0302 orr.w r3, r3, #2
  2286. 800118e: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4
  2287. 8001192: 4b06 ldr r3, [pc, #24] ; (80011ac <HAL_MspInit+0x30>)
  2288. 8001194: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4
  2289. 8001198: f003 0302 and.w r3, r3, #2
  2290. 800119c: 607b str r3, [r7, #4]
  2291. 800119e: 687b ldr r3, [r7, #4]
  2292. /* System interrupt init*/
  2293. /* USER CODE BEGIN MspInit 1 */
  2294. /* USER CODE END MspInit 1 */
  2295. }
  2296. 80011a0: bf00 nop
  2297. 80011a2: 370c adds r7, #12
  2298. 80011a4: 46bd mov sp, r7
  2299. 80011a6: f85d 7b04 ldr.w r7, [sp], #4
  2300. 80011aa: 4770 bx lr
  2301. 80011ac: 58024400 .word 0x58024400
  2302. 080011b0 <HAL_TIM_Base_MspInit>:
  2303. * This function configures the hardware resources used in this example
  2304. * @param htim_base: TIM_Base handle pointer
  2305. * @retval None
  2306. */
  2307. void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
  2308. {
  2309. 80011b0: b580 push {r7, lr}
  2310. 80011b2: b084 sub sp, #16
  2311. 80011b4: af00 add r7, sp, #0
  2312. 80011b6: 6078 str r0, [r7, #4]
  2313. if(htim_base->Instance==TIM3)
  2314. 80011b8: 687b ldr r3, [r7, #4]
  2315. 80011ba: 681b ldr r3, [r3, #0]
  2316. 80011bc: 4a0e ldr r2, [pc, #56] ; (80011f8 <HAL_TIM_Base_MspInit+0x48>)
  2317. 80011be: 4293 cmp r3, r2
  2318. 80011c0: d116 bne.n 80011f0 <HAL_TIM_Base_MspInit+0x40>
  2319. {
  2320. /* USER CODE BEGIN TIM3_MspInit 0 */
  2321. /* USER CODE END TIM3_MspInit 0 */
  2322. /* Peripheral clock enable */
  2323. __HAL_RCC_TIM3_CLK_ENABLE();
  2324. 80011c2: 4b0e ldr r3, [pc, #56] ; (80011fc <HAL_TIM_Base_MspInit+0x4c>)
  2325. 80011c4: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8
  2326. 80011c8: 4a0c ldr r2, [pc, #48] ; (80011fc <HAL_TIM_Base_MspInit+0x4c>)
  2327. 80011ca: f043 0302 orr.w r3, r3, #2
  2328. 80011ce: f8c2 30e8 str.w r3, [r2, #232] ; 0xe8
  2329. 80011d2: 4b0a ldr r3, [pc, #40] ; (80011fc <HAL_TIM_Base_MspInit+0x4c>)
  2330. 80011d4: f8d3 30e8 ldr.w r3, [r3, #232] ; 0xe8
  2331. 80011d8: f003 0302 and.w r3, r3, #2
  2332. 80011dc: 60fb str r3, [r7, #12]
  2333. 80011de: 68fb ldr r3, [r7, #12]
  2334. /* TIM3 interrupt Init */
  2335. HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
  2336. 80011e0: 2200 movs r2, #0
  2337. 80011e2: 2100 movs r1, #0
  2338. 80011e4: 201d movs r0, #29
  2339. 80011e6: f000 fb42 bl 800186e <HAL_NVIC_SetPriority>
  2340. HAL_NVIC_EnableIRQ(TIM3_IRQn);
  2341. 80011ea: 201d movs r0, #29
  2342. 80011ec: f000 fb59 bl 80018a2 <HAL_NVIC_EnableIRQ>
  2343. /* USER CODE BEGIN TIM3_MspInit 1 */
  2344. /* USER CODE END TIM3_MspInit 1 */
  2345. }
  2346. }
  2347. 80011f0: bf00 nop
  2348. 80011f2: 3710 adds r7, #16
  2349. 80011f4: 46bd mov sp, r7
  2350. 80011f6: bd80 pop {r7, pc}
  2351. 80011f8: 40000400 .word 0x40000400
  2352. 80011fc: 58024400 .word 0x58024400
  2353. 08001200 <NMI_Handler>:
  2354. /******************************************************************************/
  2355. /**
  2356. * @brief This function handles Non maskable interrupt.
  2357. */
  2358. void NMI_Handler(void)
  2359. {
  2360. 8001200: b480 push {r7}
  2361. 8001202: af00 add r7, sp, #0
  2362. /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
  2363. /* USER CODE END NonMaskableInt_IRQn 0 */
  2364. /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  2365. while (1)
  2366. 8001204: e7fe b.n 8001204 <NMI_Handler+0x4>
  2367. 08001206 <HardFault_Handler>:
  2368. /**
  2369. * @brief This function handles Hard fault interrupt.
  2370. */
  2371. void HardFault_Handler(void)
  2372. {
  2373. 8001206: b480 push {r7}
  2374. 8001208: af00 add r7, sp, #0
  2375. /* USER CODE BEGIN HardFault_IRQn 0 */
  2376. /* USER CODE END HardFault_IRQn 0 */
  2377. while (1)
  2378. 800120a: e7fe b.n 800120a <HardFault_Handler+0x4>
  2379. 0800120c <MemManage_Handler>:
  2380. /**
  2381. * @brief This function handles Memory management fault.
  2382. */
  2383. void MemManage_Handler(void)
  2384. {
  2385. 800120c: b480 push {r7}
  2386. 800120e: af00 add r7, sp, #0
  2387. /* USER CODE BEGIN MemoryManagement_IRQn 0 */
  2388. /* USER CODE END MemoryManagement_IRQn 0 */
  2389. while (1)
  2390. 8001210: e7fe b.n 8001210 <MemManage_Handler+0x4>
  2391. 08001212 <BusFault_Handler>:
  2392. /**
  2393. * @brief This function handles Pre-fetch fault, memory access fault.
  2394. */
  2395. void BusFault_Handler(void)
  2396. {
  2397. 8001212: b480 push {r7}
  2398. 8001214: af00 add r7, sp, #0
  2399. /* USER CODE BEGIN BusFault_IRQn 0 */
  2400. /* USER CODE END BusFault_IRQn 0 */
  2401. while (1)
  2402. 8001216: e7fe b.n 8001216 <BusFault_Handler+0x4>
  2403. 08001218 <UsageFault_Handler>:
  2404. /**
  2405. * @brief This function handles Undefined instruction or illegal state.
  2406. */
  2407. void UsageFault_Handler(void)
  2408. {
  2409. 8001218: b480 push {r7}
  2410. 800121a: af00 add r7, sp, #0
  2411. /* USER CODE BEGIN UsageFault_IRQn 0 */
  2412. /* USER CODE END UsageFault_IRQn 0 */
  2413. while (1)
  2414. 800121c: e7fe b.n 800121c <UsageFault_Handler+0x4>
  2415. 0800121e <SVC_Handler>:
  2416. /**
  2417. * @brief This function handles System service call via SWI instruction.
  2418. */
  2419. void SVC_Handler(void)
  2420. {
  2421. 800121e: b480 push {r7}
  2422. 8001220: af00 add r7, sp, #0
  2423. /* USER CODE END SVCall_IRQn 0 */
  2424. /* USER CODE BEGIN SVCall_IRQn 1 */
  2425. /* USER CODE END SVCall_IRQn 1 */
  2426. }
  2427. 8001222: bf00 nop
  2428. 8001224: 46bd mov sp, r7
  2429. 8001226: f85d 7b04 ldr.w r7, [sp], #4
  2430. 800122a: 4770 bx lr
  2431. 0800122c <DebugMon_Handler>:
  2432. /**
  2433. * @brief This function handles Debug monitor.
  2434. */
  2435. void DebugMon_Handler(void)
  2436. {
  2437. 800122c: b480 push {r7}
  2438. 800122e: af00 add r7, sp, #0
  2439. /* USER CODE END DebugMonitor_IRQn 0 */
  2440. /* USER CODE BEGIN DebugMonitor_IRQn 1 */
  2441. /* USER CODE END DebugMonitor_IRQn 1 */
  2442. }
  2443. 8001230: bf00 nop
  2444. 8001232: 46bd mov sp, r7
  2445. 8001234: f85d 7b04 ldr.w r7, [sp], #4
  2446. 8001238: 4770 bx lr
  2447. 0800123a <PendSV_Handler>:
  2448. /**
  2449. * @brief This function handles Pendable request for system service.
  2450. */
  2451. void PendSV_Handler(void)
  2452. {
  2453. 800123a: b480 push {r7}
  2454. 800123c: af00 add r7, sp, #0
  2455. /* USER CODE END PendSV_IRQn 0 */
  2456. /* USER CODE BEGIN PendSV_IRQn 1 */
  2457. /* USER CODE END PendSV_IRQn 1 */
  2458. }
  2459. 800123e: bf00 nop
  2460. 8001240: 46bd mov sp, r7
  2461. 8001242: f85d 7b04 ldr.w r7, [sp], #4
  2462. 8001246: 4770 bx lr
  2463. 08001248 <SysTick_Handler>:
  2464. /**
  2465. * @brief This function handles System tick timer.
  2466. */
  2467. void SysTick_Handler(void)
  2468. {
  2469. 8001248: b580 push {r7, lr}
  2470. 800124a: af00 add r7, sp, #0
  2471. /* USER CODE BEGIN SysTick_IRQn 0 */
  2472. /* USER CODE END SysTick_IRQn 0 */
  2473. HAL_IncTick();
  2474. 800124c: f000 f9f0 bl 8001630 <HAL_IncTick>
  2475. /* USER CODE BEGIN SysTick_IRQn 1 */
  2476. /* USER CODE END SysTick_IRQn 1 */
  2477. }
  2478. 8001250: bf00 nop
  2479. 8001252: bd80 pop {r7, pc}
  2480. 08001254 <TIM3_IRQHandler>:
  2481. /**
  2482. * @brief This function handles TIM3 global interrupt.
  2483. */
  2484. void TIM3_IRQHandler(void)
  2485. {
  2486. 8001254: b580 push {r7, lr}
  2487. 8001256: af00 add r7, sp, #0
  2488. /* USER CODE BEGIN TIM3_IRQn 0 */
  2489. /* USER CODE END TIM3_IRQn 0 */
  2490. HAL_TIM_IRQHandler(&htim3);
  2491. 8001258: 4802 ldr r0, [pc, #8] ; (8001264 <TIM3_IRQHandler+0x10>)
  2492. 800125a: f003 ff79 bl 8005150 <HAL_TIM_IRQHandler>
  2493. /* USER CODE BEGIN TIM3_IRQn 1 */
  2494. /* USER CODE END TIM3_IRQn 1 */
  2495. }
  2496. 800125e: bf00 nop
  2497. 8001260: bd80 pop {r7, pc}
  2498. 8001262: bf00 nop
  2499. 8001264: 240013e0 .word 0x240013e0
  2500. 08001268 <OTG_HS_IRQHandler>:
  2501. /**
  2502. * @brief This function handles USB On The Go HS global interrupt.
  2503. */
  2504. void OTG_HS_IRQHandler(void)
  2505. {
  2506. 8001268: b580 push {r7, lr}
  2507. 800126a: af00 add r7, sp, #0
  2508. /* USER CODE BEGIN OTG_HS_IRQn 0 */
  2509. /* USER CODE END OTG_HS_IRQn 0 */
  2510. HAL_PCD_IRQHandler(&hpcd_USB_OTG_HS);
  2511. 800126c: 4802 ldr r0, [pc, #8] ; (8001278 <OTG_HS_IRQHandler+0x10>)
  2512. 800126e: f000 fe65 bl 8001f3c <HAL_PCD_IRQHandler>
  2513. /* USER CODE BEGIN OTG_HS_IRQn 1 */
  2514. /* USER CODE END OTG_HS_IRQn 1 */
  2515. }
  2516. 8001272: bf00 nop
  2517. 8001274: bd80 pop {r7, pc}
  2518. 8001276: bf00 nop
  2519. 8001278: 24002900 .word 0x24002900
  2520. 0800127c <_getpid>:
  2521. void initialise_monitor_handles()
  2522. {
  2523. }
  2524. int _getpid(void)
  2525. {
  2526. 800127c: b480 push {r7}
  2527. 800127e: af00 add r7, sp, #0
  2528. return 1;
  2529. 8001280: 2301 movs r3, #1
  2530. }
  2531. 8001282: 4618 mov r0, r3
  2532. 8001284: 46bd mov sp, r7
  2533. 8001286: f85d 7b04 ldr.w r7, [sp], #4
  2534. 800128a: 4770 bx lr
  2535. 0800128c <_kill>:
  2536. int _kill(int pid, int sig)
  2537. {
  2538. 800128c: b580 push {r7, lr}
  2539. 800128e: b082 sub sp, #8
  2540. 8001290: af00 add r7, sp, #0
  2541. 8001292: 6078 str r0, [r7, #4]
  2542. 8001294: 6039 str r1, [r7, #0]
  2543. errno = EINVAL;
  2544. 8001296: f008 fb3f bl 8009918 <__errno>
  2545. 800129a: 4603 mov r3, r0
  2546. 800129c: 2216 movs r2, #22
  2547. 800129e: 601a str r2, [r3, #0]
  2548. return -1;
  2549. 80012a0: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
  2550. }
  2551. 80012a4: 4618 mov r0, r3
  2552. 80012a6: 3708 adds r7, #8
  2553. 80012a8: 46bd mov sp, r7
  2554. 80012aa: bd80 pop {r7, pc}
  2555. 080012ac <_exit>:
  2556. void _exit (int status)
  2557. {
  2558. 80012ac: b580 push {r7, lr}
  2559. 80012ae: b082 sub sp, #8
  2560. 80012b0: af00 add r7, sp, #0
  2561. 80012b2: 6078 str r0, [r7, #4]
  2562. _kill(status, -1);
  2563. 80012b4: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
  2564. 80012b8: 6878 ldr r0, [r7, #4]
  2565. 80012ba: f7ff ffe7 bl 800128c <_kill>
  2566. while (1) {} /* Make sure we hang here */
  2567. 80012be: e7fe b.n 80012be <_exit+0x12>
  2568. 080012c0 <_read>:
  2569. }
  2570. __attribute__((weak)) int _read(int file, char *ptr, int len)
  2571. {
  2572. 80012c0: b580 push {r7, lr}
  2573. 80012c2: b086 sub sp, #24
  2574. 80012c4: af00 add r7, sp, #0
  2575. 80012c6: 60f8 str r0, [r7, #12]
  2576. 80012c8: 60b9 str r1, [r7, #8]
  2577. 80012ca: 607a str r2, [r7, #4]
  2578. int DataIdx;
  2579. for (DataIdx = 0; DataIdx < len; DataIdx++)
  2580. 80012cc: 2300 movs r3, #0
  2581. 80012ce: 617b str r3, [r7, #20]
  2582. 80012d0: e00a b.n 80012e8 <_read+0x28>
  2583. {
  2584. *ptr++ = __io_getchar();
  2585. 80012d2: f3af 8000 nop.w
  2586. 80012d6: 4601 mov r1, r0
  2587. 80012d8: 68bb ldr r3, [r7, #8]
  2588. 80012da: 1c5a adds r2, r3, #1
  2589. 80012dc: 60ba str r2, [r7, #8]
  2590. 80012de: b2ca uxtb r2, r1
  2591. 80012e0: 701a strb r2, [r3, #0]
  2592. for (DataIdx = 0; DataIdx < len; DataIdx++)
  2593. 80012e2: 697b ldr r3, [r7, #20]
  2594. 80012e4: 3301 adds r3, #1
  2595. 80012e6: 617b str r3, [r7, #20]
  2596. 80012e8: 697a ldr r2, [r7, #20]
  2597. 80012ea: 687b ldr r3, [r7, #4]
  2598. 80012ec: 429a cmp r2, r3
  2599. 80012ee: dbf0 blt.n 80012d2 <_read+0x12>
  2600. }
  2601. return len;
  2602. 80012f0: 687b ldr r3, [r7, #4]
  2603. }
  2604. 80012f2: 4618 mov r0, r3
  2605. 80012f4: 3718 adds r7, #24
  2606. 80012f6: 46bd mov sp, r7
  2607. 80012f8: bd80 pop {r7, pc}
  2608. 080012fa <_write>:
  2609. __attribute__((weak)) int _write(int file, char *ptr, int len)
  2610. {
  2611. 80012fa: b580 push {r7, lr}
  2612. 80012fc: b086 sub sp, #24
  2613. 80012fe: af00 add r7, sp, #0
  2614. 8001300: 60f8 str r0, [r7, #12]
  2615. 8001302: 60b9 str r1, [r7, #8]
  2616. 8001304: 607a str r2, [r7, #4]
  2617. int DataIdx;
  2618. for (DataIdx = 0; DataIdx < len; DataIdx++)
  2619. 8001306: 2300 movs r3, #0
  2620. 8001308: 617b str r3, [r7, #20]
  2621. 800130a: e009 b.n 8001320 <_write+0x26>
  2622. {
  2623. __io_putchar(*ptr++);
  2624. 800130c: 68bb ldr r3, [r7, #8]
  2625. 800130e: 1c5a adds r2, r3, #1
  2626. 8001310: 60ba str r2, [r7, #8]
  2627. 8001312: 781b ldrb r3, [r3, #0]
  2628. 8001314: 4618 mov r0, r3
  2629. 8001316: f3af 8000 nop.w
  2630. for (DataIdx = 0; DataIdx < len; DataIdx++)
  2631. 800131a: 697b ldr r3, [r7, #20]
  2632. 800131c: 3301 adds r3, #1
  2633. 800131e: 617b str r3, [r7, #20]
  2634. 8001320: 697a ldr r2, [r7, #20]
  2635. 8001322: 687b ldr r3, [r7, #4]
  2636. 8001324: 429a cmp r2, r3
  2637. 8001326: dbf1 blt.n 800130c <_write+0x12>
  2638. }
  2639. return len;
  2640. 8001328: 687b ldr r3, [r7, #4]
  2641. }
  2642. 800132a: 4618 mov r0, r3
  2643. 800132c: 3718 adds r7, #24
  2644. 800132e: 46bd mov sp, r7
  2645. 8001330: bd80 pop {r7, pc}
  2646. 08001332 <_close>:
  2647. int _close(int file)
  2648. {
  2649. 8001332: b480 push {r7}
  2650. 8001334: b083 sub sp, #12
  2651. 8001336: af00 add r7, sp, #0
  2652. 8001338: 6078 str r0, [r7, #4]
  2653. return -1;
  2654. 800133a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
  2655. }
  2656. 800133e: 4618 mov r0, r3
  2657. 8001340: 370c adds r7, #12
  2658. 8001342: 46bd mov sp, r7
  2659. 8001344: f85d 7b04 ldr.w r7, [sp], #4
  2660. 8001348: 4770 bx lr
  2661. 0800134a <_fstat>:
  2662. int _fstat(int file, struct stat *st)
  2663. {
  2664. 800134a: b480 push {r7}
  2665. 800134c: b083 sub sp, #12
  2666. 800134e: af00 add r7, sp, #0
  2667. 8001350: 6078 str r0, [r7, #4]
  2668. 8001352: 6039 str r1, [r7, #0]
  2669. st->st_mode = S_IFCHR;
  2670. 8001354: 683b ldr r3, [r7, #0]
  2671. 8001356: f44f 5200 mov.w r2, #8192 ; 0x2000
  2672. 800135a: 605a str r2, [r3, #4]
  2673. return 0;
  2674. 800135c: 2300 movs r3, #0
  2675. }
  2676. 800135e: 4618 mov r0, r3
  2677. 8001360: 370c adds r7, #12
  2678. 8001362: 46bd mov sp, r7
  2679. 8001364: f85d 7b04 ldr.w r7, [sp], #4
  2680. 8001368: 4770 bx lr
  2681. 0800136a <_isatty>:
  2682. int _isatty(int file)
  2683. {
  2684. 800136a: b480 push {r7}
  2685. 800136c: b083 sub sp, #12
  2686. 800136e: af00 add r7, sp, #0
  2687. 8001370: 6078 str r0, [r7, #4]
  2688. return 1;
  2689. 8001372: 2301 movs r3, #1
  2690. }
  2691. 8001374: 4618 mov r0, r3
  2692. 8001376: 370c adds r7, #12
  2693. 8001378: 46bd mov sp, r7
  2694. 800137a: f85d 7b04 ldr.w r7, [sp], #4
  2695. 800137e: 4770 bx lr
  2696. 08001380 <_lseek>:
  2697. int _lseek(int file, int ptr, int dir)
  2698. {
  2699. 8001380: b480 push {r7}
  2700. 8001382: b085 sub sp, #20
  2701. 8001384: af00 add r7, sp, #0
  2702. 8001386: 60f8 str r0, [r7, #12]
  2703. 8001388: 60b9 str r1, [r7, #8]
  2704. 800138a: 607a str r2, [r7, #4]
  2705. return 0;
  2706. 800138c: 2300 movs r3, #0
  2707. }
  2708. 800138e: 4618 mov r0, r3
  2709. 8001390: 3714 adds r7, #20
  2710. 8001392: 46bd mov sp, r7
  2711. 8001394: f85d 7b04 ldr.w r7, [sp], #4
  2712. 8001398: 4770 bx lr
  2713. ...
  2714. 0800139c <_sbrk>:
  2715. *
  2716. * @param incr Memory size
  2717. * @return Pointer to allocated memory
  2718. */
  2719. void *_sbrk(ptrdiff_t incr)
  2720. {
  2721. 800139c: b580 push {r7, lr}
  2722. 800139e: b086 sub sp, #24
  2723. 80013a0: af00 add r7, sp, #0
  2724. 80013a2: 6078 str r0, [r7, #4]
  2725. extern uint8_t _end; /* Symbol defined in the linker script */
  2726. extern uint8_t _estack; /* Symbol defined in the linker script */
  2727. extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
  2728. const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
  2729. 80013a4: 4a14 ldr r2, [pc, #80] ; (80013f8 <_sbrk+0x5c>)
  2730. 80013a6: 4b15 ldr r3, [pc, #84] ; (80013fc <_sbrk+0x60>)
  2731. 80013a8: 1ad3 subs r3, r2, r3
  2732. 80013aa: 617b str r3, [r7, #20]
  2733. const uint8_t *max_heap = (uint8_t *)stack_limit;
  2734. 80013ac: 697b ldr r3, [r7, #20]
  2735. 80013ae: 613b str r3, [r7, #16]
  2736. uint8_t *prev_heap_end;
  2737. /* Initialize heap end at first call */
  2738. if (NULL == __sbrk_heap_end)
  2739. 80013b0: 4b13 ldr r3, [pc, #76] ; (8001400 <_sbrk+0x64>)
  2740. 80013b2: 681b ldr r3, [r3, #0]
  2741. 80013b4: 2b00 cmp r3, #0
  2742. 80013b6: d102 bne.n 80013be <_sbrk+0x22>
  2743. {
  2744. __sbrk_heap_end = &_end;
  2745. 80013b8: 4b11 ldr r3, [pc, #68] ; (8001400 <_sbrk+0x64>)
  2746. 80013ba: 4a12 ldr r2, [pc, #72] ; (8001404 <_sbrk+0x68>)
  2747. 80013bc: 601a str r2, [r3, #0]
  2748. }
  2749. /* Protect heap from growing into the reserved MSP stack */
  2750. if (__sbrk_heap_end + incr > max_heap)
  2751. 80013be: 4b10 ldr r3, [pc, #64] ; (8001400 <_sbrk+0x64>)
  2752. 80013c0: 681a ldr r2, [r3, #0]
  2753. 80013c2: 687b ldr r3, [r7, #4]
  2754. 80013c4: 4413 add r3, r2
  2755. 80013c6: 693a ldr r2, [r7, #16]
  2756. 80013c8: 429a cmp r2, r3
  2757. 80013ca: d207 bcs.n 80013dc <_sbrk+0x40>
  2758. {
  2759. errno = ENOMEM;
  2760. 80013cc: f008 faa4 bl 8009918 <__errno>
  2761. 80013d0: 4603 mov r3, r0
  2762. 80013d2: 220c movs r2, #12
  2763. 80013d4: 601a str r2, [r3, #0]
  2764. return (void *)-1;
  2765. 80013d6: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
  2766. 80013da: e009 b.n 80013f0 <_sbrk+0x54>
  2767. }
  2768. prev_heap_end = __sbrk_heap_end;
  2769. 80013dc: 4b08 ldr r3, [pc, #32] ; (8001400 <_sbrk+0x64>)
  2770. 80013de: 681b ldr r3, [r3, #0]
  2771. 80013e0: 60fb str r3, [r7, #12]
  2772. __sbrk_heap_end += incr;
  2773. 80013e2: 4b07 ldr r3, [pc, #28] ; (8001400 <_sbrk+0x64>)
  2774. 80013e4: 681a ldr r2, [r3, #0]
  2775. 80013e6: 687b ldr r3, [r7, #4]
  2776. 80013e8: 4413 add r3, r2
  2777. 80013ea: 4a05 ldr r2, [pc, #20] ; (8001400 <_sbrk+0x64>)
  2778. 80013ec: 6013 str r3, [r2, #0]
  2779. return (void *)prev_heap_end;
  2780. 80013ee: 68fb ldr r3, [r7, #12]
  2781. }
  2782. 80013f0: 4618 mov r0, r3
  2783. 80013f2: 3718 adds r7, #24
  2784. 80013f4: 46bd mov sp, r7
  2785. 80013f6: bd80 pop {r7, pc}
  2786. 80013f8: 24050000 .word 0x24050000
  2787. 80013fc: 00000400 .word 0x00000400
  2788. 8001400: 240011b0 .word 0x240011b0
  2789. 8001404: 24002d18 .word 0x24002d18
  2790. 08001408 <SystemInit>:
  2791. * configuration.
  2792. * @param None
  2793. * @retval None
  2794. */
  2795. void SystemInit (void)
  2796. {
  2797. 8001408: b480 push {r7}
  2798. 800140a: af00 add r7, sp, #0
  2799. __IO uint32_t tmpreg;
  2800. #endif /* DATA_IN_D2_SRAM */
  2801. /* FPU settings ------------------------------------------------------------*/
  2802. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  2803. SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
  2804. 800140c: 4b32 ldr r3, [pc, #200] ; (80014d8 <SystemInit+0xd0>)
  2805. 800140e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
  2806. 8001412: 4a31 ldr r2, [pc, #196] ; (80014d8 <SystemInit+0xd0>)
  2807. 8001414: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
  2808. 8001418: f8c2 3088 str.w r3, [r2, #136] ; 0x88
  2809. #endif
  2810. /* Reset the RCC clock configuration to the default reset state ------------*/
  2811. /* Increasing the CPU frequency */
  2812. if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
  2813. 800141c: 4b2f ldr r3, [pc, #188] ; (80014dc <SystemInit+0xd4>)
  2814. 800141e: 681b ldr r3, [r3, #0]
  2815. 8001420: f003 030f and.w r3, r3, #15
  2816. 8001424: 2b06 cmp r3, #6
  2817. 8001426: d807 bhi.n 8001438 <SystemInit+0x30>
  2818. {
  2819. /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  2820. MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
  2821. 8001428: 4b2c ldr r3, [pc, #176] ; (80014dc <SystemInit+0xd4>)
  2822. 800142a: 681b ldr r3, [r3, #0]
  2823. 800142c: f023 030f bic.w r3, r3, #15
  2824. 8001430: 4a2a ldr r2, [pc, #168] ; (80014dc <SystemInit+0xd4>)
  2825. 8001432: f043 0307 orr.w r3, r3, #7
  2826. 8001436: 6013 str r3, [r2, #0]
  2827. }
  2828. /* Set HSION bit */
  2829. RCC->CR |= RCC_CR_HSION;
  2830. 8001438: 4b29 ldr r3, [pc, #164] ; (80014e0 <SystemInit+0xd8>)
  2831. 800143a: 681b ldr r3, [r3, #0]
  2832. 800143c: 4a28 ldr r2, [pc, #160] ; (80014e0 <SystemInit+0xd8>)
  2833. 800143e: f043 0301 orr.w r3, r3, #1
  2834. 8001442: 6013 str r3, [r2, #0]
  2835. /* Reset CFGR register */
  2836. RCC->CFGR = 0x00000000;
  2837. 8001444: 4b26 ldr r3, [pc, #152] ; (80014e0 <SystemInit+0xd8>)
  2838. 8001446: 2200 movs r2, #0
  2839. 8001448: 611a str r2, [r3, #16]
  2840. /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
  2841. RCC->CR &= 0xEAF6ED7FU;
  2842. 800144a: 4b25 ldr r3, [pc, #148] ; (80014e0 <SystemInit+0xd8>)
  2843. 800144c: 681a ldr r2, [r3, #0]
  2844. 800144e: 4924 ldr r1, [pc, #144] ; (80014e0 <SystemInit+0xd8>)
  2845. 8001450: 4b24 ldr r3, [pc, #144] ; (80014e4 <SystemInit+0xdc>)
  2846. 8001452: 4013 ands r3, r2
  2847. 8001454: 600b str r3, [r1, #0]
  2848. /* Decreasing the number of wait states because of lower CPU frequency */
  2849. if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
  2850. 8001456: 4b21 ldr r3, [pc, #132] ; (80014dc <SystemInit+0xd4>)
  2851. 8001458: 681b ldr r3, [r3, #0]
  2852. 800145a: f003 0308 and.w r3, r3, #8
  2853. 800145e: 2b00 cmp r3, #0
  2854. 8001460: d007 beq.n 8001472 <SystemInit+0x6a>
  2855. {
  2856. /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  2857. MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
  2858. 8001462: 4b1e ldr r3, [pc, #120] ; (80014dc <SystemInit+0xd4>)
  2859. 8001464: 681b ldr r3, [r3, #0]
  2860. 8001466: f023 030f bic.w r3, r3, #15
  2861. 800146a: 4a1c ldr r2, [pc, #112] ; (80014dc <SystemInit+0xd4>)
  2862. 800146c: f043 0307 orr.w r3, r3, #7
  2863. 8001470: 6013 str r3, [r2, #0]
  2864. }
  2865. #if defined(D3_SRAM_BASE)
  2866. /* Reset D1CFGR register */
  2867. RCC->D1CFGR = 0x00000000;
  2868. 8001472: 4b1b ldr r3, [pc, #108] ; (80014e0 <SystemInit+0xd8>)
  2869. 8001474: 2200 movs r2, #0
  2870. 8001476: 619a str r2, [r3, #24]
  2871. /* Reset D2CFGR register */
  2872. RCC->D2CFGR = 0x00000000;
  2873. 8001478: 4b19 ldr r3, [pc, #100] ; (80014e0 <SystemInit+0xd8>)
  2874. 800147a: 2200 movs r2, #0
  2875. 800147c: 61da str r2, [r3, #28]
  2876. /* Reset D3CFGR register */
  2877. RCC->D3CFGR = 0x00000000;
  2878. 800147e: 4b18 ldr r3, [pc, #96] ; (80014e0 <SystemInit+0xd8>)
  2879. 8001480: 2200 movs r2, #0
  2880. 8001482: 621a str r2, [r3, #32]
  2881. /* Reset SRDCFGR register */
  2882. RCC->SRDCFGR = 0x00000000;
  2883. #endif
  2884. /* Reset PLLCKSELR register */
  2885. RCC->PLLCKSELR = 0x02020200;
  2886. 8001484: 4b16 ldr r3, [pc, #88] ; (80014e0 <SystemInit+0xd8>)
  2887. 8001486: 4a18 ldr r2, [pc, #96] ; (80014e8 <SystemInit+0xe0>)
  2888. 8001488: 629a str r2, [r3, #40] ; 0x28
  2889. /* Reset PLLCFGR register */
  2890. RCC->PLLCFGR = 0x01FF0000;
  2891. 800148a: 4b15 ldr r3, [pc, #84] ; (80014e0 <SystemInit+0xd8>)
  2892. 800148c: 4a17 ldr r2, [pc, #92] ; (80014ec <SystemInit+0xe4>)
  2893. 800148e: 62da str r2, [r3, #44] ; 0x2c
  2894. /* Reset PLL1DIVR register */
  2895. RCC->PLL1DIVR = 0x01010280;
  2896. 8001490: 4b13 ldr r3, [pc, #76] ; (80014e0 <SystemInit+0xd8>)
  2897. 8001492: 4a17 ldr r2, [pc, #92] ; (80014f0 <SystemInit+0xe8>)
  2898. 8001494: 631a str r2, [r3, #48] ; 0x30
  2899. /* Reset PLL1FRACR register */
  2900. RCC->PLL1FRACR = 0x00000000;
  2901. 8001496: 4b12 ldr r3, [pc, #72] ; (80014e0 <SystemInit+0xd8>)
  2902. 8001498: 2200 movs r2, #0
  2903. 800149a: 635a str r2, [r3, #52] ; 0x34
  2904. /* Reset PLL2DIVR register */
  2905. RCC->PLL2DIVR = 0x01010280;
  2906. 800149c: 4b10 ldr r3, [pc, #64] ; (80014e0 <SystemInit+0xd8>)
  2907. 800149e: 4a14 ldr r2, [pc, #80] ; (80014f0 <SystemInit+0xe8>)
  2908. 80014a0: 639a str r2, [r3, #56] ; 0x38
  2909. /* Reset PLL2FRACR register */
  2910. RCC->PLL2FRACR = 0x00000000;
  2911. 80014a2: 4b0f ldr r3, [pc, #60] ; (80014e0 <SystemInit+0xd8>)
  2912. 80014a4: 2200 movs r2, #0
  2913. 80014a6: 63da str r2, [r3, #60] ; 0x3c
  2914. /* Reset PLL3DIVR register */
  2915. RCC->PLL3DIVR = 0x01010280;
  2916. 80014a8: 4b0d ldr r3, [pc, #52] ; (80014e0 <SystemInit+0xd8>)
  2917. 80014aa: 4a11 ldr r2, [pc, #68] ; (80014f0 <SystemInit+0xe8>)
  2918. 80014ac: 641a str r2, [r3, #64] ; 0x40
  2919. /* Reset PLL3FRACR register */
  2920. RCC->PLL3FRACR = 0x00000000;
  2921. 80014ae: 4b0c ldr r3, [pc, #48] ; (80014e0 <SystemInit+0xd8>)
  2922. 80014b0: 2200 movs r2, #0
  2923. 80014b2: 645a str r2, [r3, #68] ; 0x44
  2924. /* Reset HSEBYP bit */
  2925. RCC->CR &= 0xFFFBFFFFU;
  2926. 80014b4: 4b0a ldr r3, [pc, #40] ; (80014e0 <SystemInit+0xd8>)
  2927. 80014b6: 681b ldr r3, [r3, #0]
  2928. 80014b8: 4a09 ldr r2, [pc, #36] ; (80014e0 <SystemInit+0xd8>)
  2929. 80014ba: f423 2380 bic.w r3, r3, #262144 ; 0x40000
  2930. 80014be: 6013 str r3, [r2, #0]
  2931. /* Disable all interrupts */
  2932. RCC->CIER = 0x00000000;
  2933. 80014c0: 4b07 ldr r3, [pc, #28] ; (80014e0 <SystemInit+0xd8>)
  2934. 80014c2: 2200 movs r2, #0
  2935. 80014c4: 661a str r2, [r3, #96] ; 0x60
  2936. /*
  2937. * Disable the FMC bank1 (enabled after reset).
  2938. * This, prevents CPU speculation access on this bank which blocks the use of FMC during
  2939. * 24us. During this time the others FMC master (such as LTDC) cannot use it!
  2940. */
  2941. FMC_Bank1_R->BTCR[0] = 0x000030D2;
  2942. 80014c6: 4b0b ldr r3, [pc, #44] ; (80014f4 <SystemInit+0xec>)
  2943. 80014c8: f243 02d2 movw r2, #12498 ; 0x30d2
  2944. 80014cc: 601a str r2, [r3, #0]
  2945. SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
  2946. #endif /* USER_VECT_TAB_ADDRESS */
  2947. #endif /*DUAL_CORE && CORE_CM4*/
  2948. }
  2949. 80014ce: bf00 nop
  2950. 80014d0: 46bd mov sp, r7
  2951. 80014d2: f85d 7b04 ldr.w r7, [sp], #4
  2952. 80014d6: 4770 bx lr
  2953. 80014d8: e000ed00 .word 0xe000ed00
  2954. 80014dc: 52002000 .word 0x52002000
  2955. 80014e0: 58024400 .word 0x58024400
  2956. 80014e4: eaf6ed7f .word 0xeaf6ed7f
  2957. 80014e8: 02020200 .word 0x02020200
  2958. 80014ec: 01ff0000 .word 0x01ff0000
  2959. 80014f0: 01010280 .word 0x01010280
  2960. 80014f4: 52004000 .word 0x52004000
  2961. 080014f8 <Reset_Handler>:
  2962. .section .text.Reset_Handler
  2963. .weak Reset_Handler
  2964. .type Reset_Handler, %function
  2965. Reset_Handler:
  2966. ldr sp, =_estack /* set stack pointer */
  2967. 80014f8: f8df d034 ldr.w sp, [pc, #52] ; 8001530 <LoopFillZerobss+0xe>
  2968. /* Call the clock system initialization function.*/
  2969. bl SystemInit
  2970. 80014fc: f7ff ff84 bl 8001408 <SystemInit>
  2971. /* Copy the data segment initializers from flash to SRAM */
  2972. ldr r0, =_sdata
  2973. 8001500: 480c ldr r0, [pc, #48] ; (8001534 <LoopFillZerobss+0x12>)
  2974. ldr r1, =_edata
  2975. 8001502: 490d ldr r1, [pc, #52] ; (8001538 <LoopFillZerobss+0x16>)
  2976. ldr r2, =_sidata
  2977. 8001504: 4a0d ldr r2, [pc, #52] ; (800153c <LoopFillZerobss+0x1a>)
  2978. movs r3, #0
  2979. 8001506: 2300 movs r3, #0
  2980. b LoopCopyDataInit
  2981. 8001508: e002 b.n 8001510 <LoopCopyDataInit>
  2982. 0800150a <CopyDataInit>:
  2983. CopyDataInit:
  2984. ldr r4, [r2, r3]
  2985. 800150a: 58d4 ldr r4, [r2, r3]
  2986. str r4, [r0, r3]
  2987. 800150c: 50c4 str r4, [r0, r3]
  2988. adds r3, r3, #4
  2989. 800150e: 3304 adds r3, #4
  2990. 08001510 <LoopCopyDataInit>:
  2991. LoopCopyDataInit:
  2992. adds r4, r0, r3
  2993. 8001510: 18c4 adds r4, r0, r3
  2994. cmp r4, r1
  2995. 8001512: 428c cmp r4, r1
  2996. bcc CopyDataInit
  2997. 8001514: d3f9 bcc.n 800150a <CopyDataInit>
  2998. /* Zero fill the bss segment. */
  2999. ldr r2, =_sbss
  3000. 8001516: 4a0a ldr r2, [pc, #40] ; (8001540 <LoopFillZerobss+0x1e>)
  3001. ldr r4, =_ebss
  3002. 8001518: 4c0a ldr r4, [pc, #40] ; (8001544 <LoopFillZerobss+0x22>)
  3003. movs r3, #0
  3004. 800151a: 2300 movs r3, #0
  3005. b LoopFillZerobss
  3006. 800151c: e001 b.n 8001522 <LoopFillZerobss>
  3007. 0800151e <FillZerobss>:
  3008. FillZerobss:
  3009. str r3, [r2]
  3010. 800151e: 6013 str r3, [r2, #0]
  3011. adds r2, r2, #4
  3012. 8001520: 3204 adds r2, #4
  3013. 08001522 <LoopFillZerobss>:
  3014. LoopFillZerobss:
  3015. cmp r2, r4
  3016. 8001522: 42a2 cmp r2, r4
  3017. bcc FillZerobss
  3018. 8001524: d3fb bcc.n 800151e <FillZerobss>
  3019. /* Call static constructors */
  3020. bl __libc_init_array
  3021. 8001526: f008 fa0f bl 8009948 <__libc_init_array>
  3022. /* Call the application's entry point.*/
  3023. bl main
  3024. 800152a: f7ff faa1 bl 8000a70 <main>
  3025. bx lr
  3026. 800152e: 4770 bx lr
  3027. ldr sp, =_estack /* set stack pointer */
  3028. 8001530: 24050000 .word 0x24050000
  3029. ldr r0, =_sdata
  3030. 8001534: 24000000 .word 0x24000000
  3031. ldr r1, =_edata
  3032. 8001538: 240001e8 .word 0x240001e8
  3033. ldr r2, =_sidata
  3034. 800153c: 0800aafc .word 0x0800aafc
  3035. ldr r2, =_sbss
  3036. 8001540: 240001e8 .word 0x240001e8
  3037. ldr r4, =_ebss
  3038. 8001544: 24002d18 .word 0x24002d18
  3039. 08001548 <ADC3_IRQHandler>:
  3040. * @retval None
  3041. */
  3042. .section .text.Default_Handler,"ax",%progbits
  3043. Default_Handler:
  3044. Infinite_Loop:
  3045. b Infinite_Loop
  3046. 8001548: e7fe b.n 8001548 <ADC3_IRQHandler>
  3047. ...
  3048. 0800154c <HAL_Init>:
  3049. * need to ensure that the SysTick time base is always set to 1 millisecond
  3050. * to have correct HAL operation.
  3051. * @retval HAL status
  3052. */
  3053. HAL_StatusTypeDef HAL_Init(void)
  3054. {
  3055. 800154c: b580 push {r7, lr}
  3056. 800154e: b082 sub sp, #8
  3057. 8001550: af00 add r7, sp, #0
  3058. __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
  3059. __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */
  3060. #endif /* DUAL_CORE && CORE_CM4 */
  3061. /* Set Interrupt Group Priority */
  3062. HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
  3063. 8001552: 2003 movs r0, #3
  3064. 8001554: f000 f980 bl 8001858 <HAL_NVIC_SetPriorityGrouping>
  3065. /* Update the SystemCoreClock global variable */
  3066. #if defined(RCC_D1CFGR_D1CPRE)
  3067. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  3068. 8001558: f002 fb14 bl 8003b84 <HAL_RCC_GetSysClockFreq>
  3069. 800155c: 4602 mov r2, r0
  3070. 800155e: 4b15 ldr r3, [pc, #84] ; (80015b4 <HAL_Init+0x68>)
  3071. 8001560: 699b ldr r3, [r3, #24]
  3072. 8001562: 0a1b lsrs r3, r3, #8
  3073. 8001564: f003 030f and.w r3, r3, #15
  3074. 8001568: 4913 ldr r1, [pc, #76] ; (80015b8 <HAL_Init+0x6c>)
  3075. 800156a: 5ccb ldrb r3, [r1, r3]
  3076. 800156c: f003 031f and.w r3, r3, #31
  3077. 8001570: fa22 f303 lsr.w r3, r2, r3
  3078. 8001574: 607b str r3, [r7, #4]
  3079. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
  3080. #endif
  3081. /* Update the SystemD2Clock global variable */
  3082. #if defined(RCC_D1CFGR_HPRE)
  3083. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  3084. 8001576: 4b0f ldr r3, [pc, #60] ; (80015b4 <HAL_Init+0x68>)
  3085. 8001578: 699b ldr r3, [r3, #24]
  3086. 800157a: f003 030f and.w r3, r3, #15
  3087. 800157e: 4a0e ldr r2, [pc, #56] ; (80015b8 <HAL_Init+0x6c>)
  3088. 8001580: 5cd3 ldrb r3, [r2, r3]
  3089. 8001582: f003 031f and.w r3, r3, #31
  3090. 8001586: 687a ldr r2, [r7, #4]
  3091. 8001588: fa22 f303 lsr.w r3, r2, r3
  3092. 800158c: 4a0b ldr r2, [pc, #44] ; (80015bc <HAL_Init+0x70>)
  3093. 800158e: 6013 str r3, [r2, #0]
  3094. #endif
  3095. #if defined(DUAL_CORE) && defined(CORE_CM4)
  3096. SystemCoreClock = SystemD2Clock;
  3097. #else
  3098. SystemCoreClock = common_system_clock;
  3099. 8001590: 4a0b ldr r2, [pc, #44] ; (80015c0 <HAL_Init+0x74>)
  3100. 8001592: 687b ldr r3, [r7, #4]
  3101. 8001594: 6013 str r3, [r2, #0]
  3102. #endif /* DUAL_CORE && CORE_CM4 */
  3103. /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  3104. if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
  3105. 8001596: 2000 movs r0, #0
  3106. 8001598: f000 f814 bl 80015c4 <HAL_InitTick>
  3107. 800159c: 4603 mov r3, r0
  3108. 800159e: 2b00 cmp r3, #0
  3109. 80015a0: d001 beq.n 80015a6 <HAL_Init+0x5a>
  3110. {
  3111. return HAL_ERROR;
  3112. 80015a2: 2301 movs r3, #1
  3113. 80015a4: e002 b.n 80015ac <HAL_Init+0x60>
  3114. }
  3115. /* Init the low level hardware */
  3116. HAL_MspInit();
  3117. 80015a6: f7ff fde9 bl 800117c <HAL_MspInit>
  3118. /* Return function status */
  3119. return HAL_OK;
  3120. 80015aa: 2300 movs r3, #0
  3121. }
  3122. 80015ac: 4618 mov r0, r3
  3123. 80015ae: 3708 adds r7, #8
  3124. 80015b0: 46bd mov sp, r7
  3125. 80015b2: bd80 pop {r7, pc}
  3126. 80015b4: 58024400 .word 0x58024400
  3127. 80015b8: 0800aa10 .word 0x0800aa10
  3128. 80015bc: 24000004 .word 0x24000004
  3129. 80015c0: 24000000 .word 0x24000000
  3130. 080015c4 <HAL_InitTick>:
  3131. * implementation in user file.
  3132. * @param TickPriority: Tick interrupt priority.
  3133. * @retval HAL status
  3134. */
  3135. __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
  3136. {
  3137. 80015c4: b580 push {r7, lr}
  3138. 80015c6: b082 sub sp, #8
  3139. 80015c8: af00 add r7, sp, #0
  3140. 80015ca: 6078 str r0, [r7, #4]
  3141. /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
  3142. if((uint32_t)uwTickFreq == 0UL)
  3143. 80015cc: 4b15 ldr r3, [pc, #84] ; (8001624 <HAL_InitTick+0x60>)
  3144. 80015ce: 781b ldrb r3, [r3, #0]
  3145. 80015d0: 2b00 cmp r3, #0
  3146. 80015d2: d101 bne.n 80015d8 <HAL_InitTick+0x14>
  3147. {
  3148. return HAL_ERROR;
  3149. 80015d4: 2301 movs r3, #1
  3150. 80015d6: e021 b.n 800161c <HAL_InitTick+0x58>
  3151. }
  3152. /* Configure the SysTick to have interrupt in 1ms time basis*/
  3153. if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
  3154. 80015d8: 4b13 ldr r3, [pc, #76] ; (8001628 <HAL_InitTick+0x64>)
  3155. 80015da: 681a ldr r2, [r3, #0]
  3156. 80015dc: 4b11 ldr r3, [pc, #68] ; (8001624 <HAL_InitTick+0x60>)
  3157. 80015de: 781b ldrb r3, [r3, #0]
  3158. 80015e0: 4619 mov r1, r3
  3159. 80015e2: f44f 737a mov.w r3, #1000 ; 0x3e8
  3160. 80015e6: fbb3 f3f1 udiv r3, r3, r1
  3161. 80015ea: fbb2 f3f3 udiv r3, r2, r3
  3162. 80015ee: 4618 mov r0, r3
  3163. 80015f0: f000 f965 bl 80018be <HAL_SYSTICK_Config>
  3164. 80015f4: 4603 mov r3, r0
  3165. 80015f6: 2b00 cmp r3, #0
  3166. 80015f8: d001 beq.n 80015fe <HAL_InitTick+0x3a>
  3167. {
  3168. return HAL_ERROR;
  3169. 80015fa: 2301 movs r3, #1
  3170. 80015fc: e00e b.n 800161c <HAL_InitTick+0x58>
  3171. }
  3172. /* Configure the SysTick IRQ priority */
  3173. if (TickPriority < (1UL << __NVIC_PRIO_BITS))
  3174. 80015fe: 687b ldr r3, [r7, #4]
  3175. 8001600: 2b0f cmp r3, #15
  3176. 8001602: d80a bhi.n 800161a <HAL_InitTick+0x56>
  3177. {
  3178. HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
  3179. 8001604: 2200 movs r2, #0
  3180. 8001606: 6879 ldr r1, [r7, #4]
  3181. 8001608: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
  3182. 800160c: f000 f92f bl 800186e <HAL_NVIC_SetPriority>
  3183. uwTickPrio = TickPriority;
  3184. 8001610: 4a06 ldr r2, [pc, #24] ; (800162c <HAL_InitTick+0x68>)
  3185. 8001612: 687b ldr r3, [r7, #4]
  3186. 8001614: 6013 str r3, [r2, #0]
  3187. {
  3188. return HAL_ERROR;
  3189. }
  3190. /* Return function status */
  3191. return HAL_OK;
  3192. 8001616: 2300 movs r3, #0
  3193. 8001618: e000 b.n 800161c <HAL_InitTick+0x58>
  3194. return HAL_ERROR;
  3195. 800161a: 2301 movs r3, #1
  3196. }
  3197. 800161c: 4618 mov r0, r3
  3198. 800161e: 3708 adds r7, #8
  3199. 8001620: 46bd mov sp, r7
  3200. 8001622: bd80 pop {r7, pc}
  3201. 8001624: 2400000c .word 0x2400000c
  3202. 8001628: 24000000 .word 0x24000000
  3203. 800162c: 24000008 .word 0x24000008
  3204. 08001630 <HAL_IncTick>:
  3205. * @note This function is declared as __weak to be overwritten in case of other
  3206. * implementations in user file.
  3207. * @retval None
  3208. */
  3209. __weak void HAL_IncTick(void)
  3210. {
  3211. 8001630: b480 push {r7}
  3212. 8001632: af00 add r7, sp, #0
  3213. uwTick += (uint32_t)uwTickFreq;
  3214. 8001634: 4b06 ldr r3, [pc, #24] ; (8001650 <HAL_IncTick+0x20>)
  3215. 8001636: 781b ldrb r3, [r3, #0]
  3216. 8001638: 461a mov r2, r3
  3217. 800163a: 4b06 ldr r3, [pc, #24] ; (8001654 <HAL_IncTick+0x24>)
  3218. 800163c: 681b ldr r3, [r3, #0]
  3219. 800163e: 4413 add r3, r2
  3220. 8001640: 4a04 ldr r2, [pc, #16] ; (8001654 <HAL_IncTick+0x24>)
  3221. 8001642: 6013 str r3, [r2, #0]
  3222. }
  3223. 8001644: bf00 nop
  3224. 8001646: 46bd mov sp, r7
  3225. 8001648: f85d 7b04 ldr.w r7, [sp], #4
  3226. 800164c: 4770 bx lr
  3227. 800164e: bf00 nop
  3228. 8001650: 2400000c .word 0x2400000c
  3229. 8001654: 2400142c .word 0x2400142c
  3230. 08001658 <HAL_GetTick>:
  3231. * @note This function is declared as __weak to be overwritten in case of other
  3232. * implementations in user file.
  3233. * @retval tick value
  3234. */
  3235. __weak uint32_t HAL_GetTick(void)
  3236. {
  3237. 8001658: b480 push {r7}
  3238. 800165a: af00 add r7, sp, #0
  3239. return uwTick;
  3240. 800165c: 4b03 ldr r3, [pc, #12] ; (800166c <HAL_GetTick+0x14>)
  3241. 800165e: 681b ldr r3, [r3, #0]
  3242. }
  3243. 8001660: 4618 mov r0, r3
  3244. 8001662: 46bd mov sp, r7
  3245. 8001664: f85d 7b04 ldr.w r7, [sp], #4
  3246. 8001668: 4770 bx lr
  3247. 800166a: bf00 nop
  3248. 800166c: 2400142c .word 0x2400142c
  3249. 08001670 <HAL_Delay>:
  3250. * implementations in user file.
  3251. * @param Delay specifies the delay time length, in milliseconds.
  3252. * @retval None
  3253. */
  3254. __weak void HAL_Delay(uint32_t Delay)
  3255. {
  3256. 8001670: b580 push {r7, lr}
  3257. 8001672: b084 sub sp, #16
  3258. 8001674: af00 add r7, sp, #0
  3259. 8001676: 6078 str r0, [r7, #4]
  3260. uint32_t tickstart = HAL_GetTick();
  3261. 8001678: f7ff ffee bl 8001658 <HAL_GetTick>
  3262. 800167c: 60b8 str r0, [r7, #8]
  3263. uint32_t wait = Delay;
  3264. 800167e: 687b ldr r3, [r7, #4]
  3265. 8001680: 60fb str r3, [r7, #12]
  3266. /* Add a freq to guarantee minimum wait */
  3267. if (wait < HAL_MAX_DELAY)
  3268. 8001682: 68fb ldr r3, [r7, #12]
  3269. 8001684: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
  3270. 8001688: d005 beq.n 8001696 <HAL_Delay+0x26>
  3271. {
  3272. wait += (uint32_t)(uwTickFreq);
  3273. 800168a: 4b0a ldr r3, [pc, #40] ; (80016b4 <HAL_Delay+0x44>)
  3274. 800168c: 781b ldrb r3, [r3, #0]
  3275. 800168e: 461a mov r2, r3
  3276. 8001690: 68fb ldr r3, [r7, #12]
  3277. 8001692: 4413 add r3, r2
  3278. 8001694: 60fb str r3, [r7, #12]
  3279. }
  3280. while ((HAL_GetTick() - tickstart) < wait)
  3281. 8001696: bf00 nop
  3282. 8001698: f7ff ffde bl 8001658 <HAL_GetTick>
  3283. 800169c: 4602 mov r2, r0
  3284. 800169e: 68bb ldr r3, [r7, #8]
  3285. 80016a0: 1ad3 subs r3, r2, r3
  3286. 80016a2: 68fa ldr r2, [r7, #12]
  3287. 80016a4: 429a cmp r2, r3
  3288. 80016a6: d8f7 bhi.n 8001698 <HAL_Delay+0x28>
  3289. {
  3290. }
  3291. }
  3292. 80016a8: bf00 nop
  3293. 80016aa: bf00 nop
  3294. 80016ac: 3710 adds r7, #16
  3295. 80016ae: 46bd mov sp, r7
  3296. 80016b0: bd80 pop {r7, pc}
  3297. 80016b2: bf00 nop
  3298. 80016b4: 2400000c .word 0x2400000c
  3299. 080016b8 <__NVIC_SetPriorityGrouping>:
  3300. {
  3301. 80016b8: b480 push {r7}
  3302. 80016ba: b085 sub sp, #20
  3303. 80016bc: af00 add r7, sp, #0
  3304. 80016be: 6078 str r0, [r7, #4]
  3305. uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
  3306. 80016c0: 687b ldr r3, [r7, #4]
  3307. 80016c2: f003 0307 and.w r3, r3, #7
  3308. 80016c6: 60fb str r3, [r7, #12]
  3309. reg_value = SCB->AIRCR; /* read old register configuration */
  3310. 80016c8: 4b0b ldr r3, [pc, #44] ; (80016f8 <__NVIC_SetPriorityGrouping+0x40>)
  3311. 80016ca: 68db ldr r3, [r3, #12]
  3312. 80016cc: 60bb str r3, [r7, #8]
  3313. reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
  3314. 80016ce: 68ba ldr r2, [r7, #8]
  3315. 80016d0: f64f 03ff movw r3, #63743 ; 0xf8ff
  3316. 80016d4: 4013 ands r3, r2
  3317. 80016d6: 60bb str r3, [r7, #8]
  3318. (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
  3319. 80016d8: 68fb ldr r3, [r7, #12]
  3320. 80016da: 021a lsls r2, r3, #8
  3321. ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  3322. 80016dc: 68bb ldr r3, [r7, #8]
  3323. 80016de: 431a orrs r2, r3
  3324. reg_value = (reg_value |
  3325. 80016e0: 4b06 ldr r3, [pc, #24] ; (80016fc <__NVIC_SetPriorityGrouping+0x44>)
  3326. 80016e2: 4313 orrs r3, r2
  3327. 80016e4: 60bb str r3, [r7, #8]
  3328. SCB->AIRCR = reg_value;
  3329. 80016e6: 4a04 ldr r2, [pc, #16] ; (80016f8 <__NVIC_SetPriorityGrouping+0x40>)
  3330. 80016e8: 68bb ldr r3, [r7, #8]
  3331. 80016ea: 60d3 str r3, [r2, #12]
  3332. }
  3333. 80016ec: bf00 nop
  3334. 80016ee: 3714 adds r7, #20
  3335. 80016f0: 46bd mov sp, r7
  3336. 80016f2: f85d 7b04 ldr.w r7, [sp], #4
  3337. 80016f6: 4770 bx lr
  3338. 80016f8: e000ed00 .word 0xe000ed00
  3339. 80016fc: 05fa0000 .word 0x05fa0000
  3340. 08001700 <__NVIC_GetPriorityGrouping>:
  3341. {
  3342. 8001700: b480 push {r7}
  3343. 8001702: af00 add r7, sp, #0
  3344. return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
  3345. 8001704: 4b04 ldr r3, [pc, #16] ; (8001718 <__NVIC_GetPriorityGrouping+0x18>)
  3346. 8001706: 68db ldr r3, [r3, #12]
  3347. 8001708: 0a1b lsrs r3, r3, #8
  3348. 800170a: f003 0307 and.w r3, r3, #7
  3349. }
  3350. 800170e: 4618 mov r0, r3
  3351. 8001710: 46bd mov sp, r7
  3352. 8001712: f85d 7b04 ldr.w r7, [sp], #4
  3353. 8001716: 4770 bx lr
  3354. 8001718: e000ed00 .word 0xe000ed00
  3355. 0800171c <__NVIC_EnableIRQ>:
  3356. {
  3357. 800171c: b480 push {r7}
  3358. 800171e: b083 sub sp, #12
  3359. 8001720: af00 add r7, sp, #0
  3360. 8001722: 4603 mov r3, r0
  3361. 8001724: 80fb strh r3, [r7, #6]
  3362. if ((int32_t)(IRQn) >= 0)
  3363. 8001726: f9b7 3006 ldrsh.w r3, [r7, #6]
  3364. 800172a: 2b00 cmp r3, #0
  3365. 800172c: db0b blt.n 8001746 <__NVIC_EnableIRQ+0x2a>
  3366. NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  3367. 800172e: 88fb ldrh r3, [r7, #6]
  3368. 8001730: f003 021f and.w r2, r3, #31
  3369. 8001734: 4907 ldr r1, [pc, #28] ; (8001754 <__NVIC_EnableIRQ+0x38>)
  3370. 8001736: f9b7 3006 ldrsh.w r3, [r7, #6]
  3371. 800173a: 095b lsrs r3, r3, #5
  3372. 800173c: 2001 movs r0, #1
  3373. 800173e: fa00 f202 lsl.w r2, r0, r2
  3374. 8001742: f841 2023 str.w r2, [r1, r3, lsl #2]
  3375. }
  3376. 8001746: bf00 nop
  3377. 8001748: 370c adds r7, #12
  3378. 800174a: 46bd mov sp, r7
  3379. 800174c: f85d 7b04 ldr.w r7, [sp], #4
  3380. 8001750: 4770 bx lr
  3381. 8001752: bf00 nop
  3382. 8001754: e000e100 .word 0xe000e100
  3383. 08001758 <__NVIC_SetPriority>:
  3384. {
  3385. 8001758: b480 push {r7}
  3386. 800175a: b083 sub sp, #12
  3387. 800175c: af00 add r7, sp, #0
  3388. 800175e: 4603 mov r3, r0
  3389. 8001760: 6039 str r1, [r7, #0]
  3390. 8001762: 80fb strh r3, [r7, #6]
  3391. if ((int32_t)(IRQn) >= 0)
  3392. 8001764: f9b7 3006 ldrsh.w r3, [r7, #6]
  3393. 8001768: 2b00 cmp r3, #0
  3394. 800176a: db0a blt.n 8001782 <__NVIC_SetPriority+0x2a>
  3395. NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  3396. 800176c: 683b ldr r3, [r7, #0]
  3397. 800176e: b2da uxtb r2, r3
  3398. 8001770: 490c ldr r1, [pc, #48] ; (80017a4 <__NVIC_SetPriority+0x4c>)
  3399. 8001772: f9b7 3006 ldrsh.w r3, [r7, #6]
  3400. 8001776: 0112 lsls r2, r2, #4
  3401. 8001778: b2d2 uxtb r2, r2
  3402. 800177a: 440b add r3, r1
  3403. 800177c: f883 2300 strb.w r2, [r3, #768] ; 0x300
  3404. }
  3405. 8001780: e00a b.n 8001798 <__NVIC_SetPriority+0x40>
  3406. SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  3407. 8001782: 683b ldr r3, [r7, #0]
  3408. 8001784: b2da uxtb r2, r3
  3409. 8001786: 4908 ldr r1, [pc, #32] ; (80017a8 <__NVIC_SetPriority+0x50>)
  3410. 8001788: 88fb ldrh r3, [r7, #6]
  3411. 800178a: f003 030f and.w r3, r3, #15
  3412. 800178e: 3b04 subs r3, #4
  3413. 8001790: 0112 lsls r2, r2, #4
  3414. 8001792: b2d2 uxtb r2, r2
  3415. 8001794: 440b add r3, r1
  3416. 8001796: 761a strb r2, [r3, #24]
  3417. }
  3418. 8001798: bf00 nop
  3419. 800179a: 370c adds r7, #12
  3420. 800179c: 46bd mov sp, r7
  3421. 800179e: f85d 7b04 ldr.w r7, [sp], #4
  3422. 80017a2: 4770 bx lr
  3423. 80017a4: e000e100 .word 0xe000e100
  3424. 80017a8: e000ed00 .word 0xe000ed00
  3425. 080017ac <NVIC_EncodePriority>:
  3426. {
  3427. 80017ac: b480 push {r7}
  3428. 80017ae: b089 sub sp, #36 ; 0x24
  3429. 80017b0: af00 add r7, sp, #0
  3430. 80017b2: 60f8 str r0, [r7, #12]
  3431. 80017b4: 60b9 str r1, [r7, #8]
  3432. 80017b6: 607a str r2, [r7, #4]
  3433. uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
  3434. 80017b8: 68fb ldr r3, [r7, #12]
  3435. 80017ba: f003 0307 and.w r3, r3, #7
  3436. 80017be: 61fb str r3, [r7, #28]
  3437. PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  3438. 80017c0: 69fb ldr r3, [r7, #28]
  3439. 80017c2: f1c3 0307 rsb r3, r3, #7
  3440. 80017c6: 2b04 cmp r3, #4
  3441. 80017c8: bf28 it cs
  3442. 80017ca: 2304 movcs r3, #4
  3443. 80017cc: 61bb str r3, [r7, #24]
  3444. SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  3445. 80017ce: 69fb ldr r3, [r7, #28]
  3446. 80017d0: 3304 adds r3, #4
  3447. 80017d2: 2b06 cmp r3, #6
  3448. 80017d4: d902 bls.n 80017dc <NVIC_EncodePriority+0x30>
  3449. 80017d6: 69fb ldr r3, [r7, #28]
  3450. 80017d8: 3b03 subs r3, #3
  3451. 80017da: e000 b.n 80017de <NVIC_EncodePriority+0x32>
  3452. 80017dc: 2300 movs r3, #0
  3453. 80017de: 617b str r3, [r7, #20]
  3454. ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
  3455. 80017e0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
  3456. 80017e4: 69bb ldr r3, [r7, #24]
  3457. 80017e6: fa02 f303 lsl.w r3, r2, r3
  3458. 80017ea: 43da mvns r2, r3
  3459. 80017ec: 68bb ldr r3, [r7, #8]
  3460. 80017ee: 401a ands r2, r3
  3461. 80017f0: 697b ldr r3, [r7, #20]
  3462. 80017f2: 409a lsls r2, r3
  3463. ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
  3464. 80017f4: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
  3465. 80017f8: 697b ldr r3, [r7, #20]
  3466. 80017fa: fa01 f303 lsl.w r3, r1, r3
  3467. 80017fe: 43d9 mvns r1, r3
  3468. 8001800: 687b ldr r3, [r7, #4]
  3469. 8001802: 400b ands r3, r1
  3470. ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
  3471. 8001804: 4313 orrs r3, r2
  3472. }
  3473. 8001806: 4618 mov r0, r3
  3474. 8001808: 3724 adds r7, #36 ; 0x24
  3475. 800180a: 46bd mov sp, r7
  3476. 800180c: f85d 7b04 ldr.w r7, [sp], #4
  3477. 8001810: 4770 bx lr
  3478. ...
  3479. 08001814 <SysTick_Config>:
  3480. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
  3481. function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
  3482. must contain a vendor-specific implementation of this function.
  3483. */
  3484. __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
  3485. {
  3486. 8001814: b580 push {r7, lr}
  3487. 8001816: b082 sub sp, #8
  3488. 8001818: af00 add r7, sp, #0
  3489. 800181a: 6078 str r0, [r7, #4]
  3490. if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
  3491. 800181c: 687b ldr r3, [r7, #4]
  3492. 800181e: 3b01 subs r3, #1
  3493. 8001820: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
  3494. 8001824: d301 bcc.n 800182a <SysTick_Config+0x16>
  3495. {
  3496. return (1UL); /* Reload value impossible */
  3497. 8001826: 2301 movs r3, #1
  3498. 8001828: e00f b.n 800184a <SysTick_Config+0x36>
  3499. }
  3500. SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
  3501. 800182a: 4a0a ldr r2, [pc, #40] ; (8001854 <SysTick_Config+0x40>)
  3502. 800182c: 687b ldr r3, [r7, #4]
  3503. 800182e: 3b01 subs r3, #1
  3504. 8001830: 6053 str r3, [r2, #4]
  3505. NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  3506. 8001832: 210f movs r1, #15
  3507. 8001834: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
  3508. 8001838: f7ff ff8e bl 8001758 <__NVIC_SetPriority>
  3509. SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
  3510. 800183c: 4b05 ldr r3, [pc, #20] ; (8001854 <SysTick_Config+0x40>)
  3511. 800183e: 2200 movs r2, #0
  3512. 8001840: 609a str r2, [r3, #8]
  3513. SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
  3514. 8001842: 4b04 ldr r3, [pc, #16] ; (8001854 <SysTick_Config+0x40>)
  3515. 8001844: 2207 movs r2, #7
  3516. 8001846: 601a str r2, [r3, #0]
  3517. SysTick_CTRL_TICKINT_Msk |
  3518. SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
  3519. return (0UL); /* Function successful */
  3520. 8001848: 2300 movs r3, #0
  3521. }
  3522. 800184a: 4618 mov r0, r3
  3523. 800184c: 3708 adds r7, #8
  3524. 800184e: 46bd mov sp, r7
  3525. 8001850: bd80 pop {r7, pc}
  3526. 8001852: bf00 nop
  3527. 8001854: e000e010 .word 0xe000e010
  3528. 08001858 <HAL_NVIC_SetPriorityGrouping>:
  3529. * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
  3530. * The pending IRQ priority will be managed only by the subpriority.
  3531. * @retval None
  3532. */
  3533. void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  3534. {
  3535. 8001858: b580 push {r7, lr}
  3536. 800185a: b082 sub sp, #8
  3537. 800185c: af00 add r7, sp, #0
  3538. 800185e: 6078 str r0, [r7, #4]
  3539. /* Check the parameters */
  3540. assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  3541. /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  3542. NVIC_SetPriorityGrouping(PriorityGroup);
  3543. 8001860: 6878 ldr r0, [r7, #4]
  3544. 8001862: f7ff ff29 bl 80016b8 <__NVIC_SetPriorityGrouping>
  3545. }
  3546. 8001866: bf00 nop
  3547. 8001868: 3708 adds r7, #8
  3548. 800186a: 46bd mov sp, r7
  3549. 800186c: bd80 pop {r7, pc}
  3550. 0800186e <HAL_NVIC_SetPriority>:
  3551. * This parameter can be a value between 0 and 15
  3552. * A lower priority value indicates a higher priority.
  3553. * @retval None
  3554. */
  3555. void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
  3556. {
  3557. 800186e: b580 push {r7, lr}
  3558. 8001870: b086 sub sp, #24
  3559. 8001872: af00 add r7, sp, #0
  3560. 8001874: 4603 mov r3, r0
  3561. 8001876: 60b9 str r1, [r7, #8]
  3562. 8001878: 607a str r2, [r7, #4]
  3563. 800187a: 81fb strh r3, [r7, #14]
  3564. /* Check the parameters */
  3565. assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  3566. assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  3567. prioritygroup = NVIC_GetPriorityGrouping();
  3568. 800187c: f7ff ff40 bl 8001700 <__NVIC_GetPriorityGrouping>
  3569. 8001880: 6178 str r0, [r7, #20]
  3570. NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
  3571. 8001882: 687a ldr r2, [r7, #4]
  3572. 8001884: 68b9 ldr r1, [r7, #8]
  3573. 8001886: 6978 ldr r0, [r7, #20]
  3574. 8001888: f7ff ff90 bl 80017ac <NVIC_EncodePriority>
  3575. 800188c: 4602 mov r2, r0
  3576. 800188e: f9b7 300e ldrsh.w r3, [r7, #14]
  3577. 8001892: 4611 mov r1, r2
  3578. 8001894: 4618 mov r0, r3
  3579. 8001896: f7ff ff5f bl 8001758 <__NVIC_SetPriority>
  3580. }
  3581. 800189a: bf00 nop
  3582. 800189c: 3718 adds r7, #24
  3583. 800189e: 46bd mov sp, r7
  3584. 80018a0: bd80 pop {r7, pc}
  3585. 080018a2 <HAL_NVIC_EnableIRQ>:
  3586. * This parameter can be an enumerator of IRQn_Type enumeration
  3587. * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
  3588. * @retval None
  3589. */
  3590. void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
  3591. {
  3592. 80018a2: b580 push {r7, lr}
  3593. 80018a4: b082 sub sp, #8
  3594. 80018a6: af00 add r7, sp, #0
  3595. 80018a8: 4603 mov r3, r0
  3596. 80018aa: 80fb strh r3, [r7, #6]
  3597. /* Check the parameters */
  3598. assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  3599. /* Enable interrupt */
  3600. NVIC_EnableIRQ(IRQn);
  3601. 80018ac: f9b7 3006 ldrsh.w r3, [r7, #6]
  3602. 80018b0: 4618 mov r0, r3
  3603. 80018b2: f7ff ff33 bl 800171c <__NVIC_EnableIRQ>
  3604. }
  3605. 80018b6: bf00 nop
  3606. 80018b8: 3708 adds r7, #8
  3607. 80018ba: 46bd mov sp, r7
  3608. 80018bc: bd80 pop {r7, pc}
  3609. 080018be <HAL_SYSTICK_Config>:
  3610. * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
  3611. * @retval status - 0 Function succeeded.
  3612. * - 1 Function failed.
  3613. */
  3614. uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
  3615. {
  3616. 80018be: b580 push {r7, lr}
  3617. 80018c0: b082 sub sp, #8
  3618. 80018c2: af00 add r7, sp, #0
  3619. 80018c4: 6078 str r0, [r7, #4]
  3620. return SysTick_Config(TicksNumb);
  3621. 80018c6: 6878 ldr r0, [r7, #4]
  3622. 80018c8: f7ff ffa4 bl 8001814 <SysTick_Config>
  3623. 80018cc: 4603 mov r3, r0
  3624. }
  3625. 80018ce: 4618 mov r0, r3
  3626. 80018d0: 3708 adds r7, #8
  3627. 80018d2: 46bd mov sp, r7
  3628. 80018d4: bd80 pop {r7, pc}
  3629. ...
  3630. 080018d8 <HAL_GPIO_Init>:
  3631. * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  3632. * the configuration information for the specified GPIO peripheral.
  3633. * @retval None
  3634. */
  3635. void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
  3636. {
  3637. 80018d8: b480 push {r7}
  3638. 80018da: b089 sub sp, #36 ; 0x24
  3639. 80018dc: af00 add r7, sp, #0
  3640. 80018de: 6078 str r0, [r7, #4]
  3641. 80018e0: 6039 str r1, [r7, #0]
  3642. uint32_t position = 0x00U;
  3643. 80018e2: 2300 movs r3, #0
  3644. 80018e4: 61fb str r3, [r7, #28]
  3645. EXTI_Core_TypeDef *EXTI_CurrentCPU;
  3646. #if defined(DUAL_CORE) && defined(CORE_CM4)
  3647. EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
  3648. #else
  3649. EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
  3650. 80018e6: 4b86 ldr r3, [pc, #536] ; (8001b00 <HAL_GPIO_Init+0x228>)
  3651. 80018e8: 617b str r3, [r7, #20]
  3652. assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  3653. assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  3654. assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
  3655. /* Configure the port pins */
  3656. while (((GPIO_Init->Pin) >> position) != 0x00U)
  3657. 80018ea: e18c b.n 8001c06 <HAL_GPIO_Init+0x32e>
  3658. {
  3659. /* Get current io position */
  3660. iocurrent = (GPIO_Init->Pin) & (1UL << position);
  3661. 80018ec: 683b ldr r3, [r7, #0]
  3662. 80018ee: 681a ldr r2, [r3, #0]
  3663. 80018f0: 2101 movs r1, #1
  3664. 80018f2: 69fb ldr r3, [r7, #28]
  3665. 80018f4: fa01 f303 lsl.w r3, r1, r3
  3666. 80018f8: 4013 ands r3, r2
  3667. 80018fa: 613b str r3, [r7, #16]
  3668. if (iocurrent != 0x00U)
  3669. 80018fc: 693b ldr r3, [r7, #16]
  3670. 80018fe: 2b00 cmp r3, #0
  3671. 8001900: f000 817e beq.w 8001c00 <HAL_GPIO_Init+0x328>
  3672. {
  3673. /*--------------------- GPIO Mode Configuration ------------------------*/
  3674. /* In case of Output or Alternate function mode selection */
  3675. if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
  3676. 8001904: 683b ldr r3, [r7, #0]
  3677. 8001906: 685b ldr r3, [r3, #4]
  3678. 8001908: f003 0303 and.w r3, r3, #3
  3679. 800190c: 2b01 cmp r3, #1
  3680. 800190e: d005 beq.n 800191c <HAL_GPIO_Init+0x44>
  3681. 8001910: 683b ldr r3, [r7, #0]
  3682. 8001912: 685b ldr r3, [r3, #4]
  3683. 8001914: f003 0303 and.w r3, r3, #3
  3684. 8001918: 2b02 cmp r3, #2
  3685. 800191a: d130 bne.n 800197e <HAL_GPIO_Init+0xa6>
  3686. {
  3687. /* Check the Speed parameter */
  3688. assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
  3689. /* Configure the IO Speed */
  3690. temp = GPIOx->OSPEEDR;
  3691. 800191c: 687b ldr r3, [r7, #4]
  3692. 800191e: 689b ldr r3, [r3, #8]
  3693. 8001920: 61bb str r3, [r7, #24]
  3694. temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
  3695. 8001922: 69fb ldr r3, [r7, #28]
  3696. 8001924: 005b lsls r3, r3, #1
  3697. 8001926: 2203 movs r2, #3
  3698. 8001928: fa02 f303 lsl.w r3, r2, r3
  3699. 800192c: 43db mvns r3, r3
  3700. 800192e: 69ba ldr r2, [r7, #24]
  3701. 8001930: 4013 ands r3, r2
  3702. 8001932: 61bb str r3, [r7, #24]
  3703. temp |= (GPIO_Init->Speed << (position * 2U));
  3704. 8001934: 683b ldr r3, [r7, #0]
  3705. 8001936: 68da ldr r2, [r3, #12]
  3706. 8001938: 69fb ldr r3, [r7, #28]
  3707. 800193a: 005b lsls r3, r3, #1
  3708. 800193c: fa02 f303 lsl.w r3, r2, r3
  3709. 8001940: 69ba ldr r2, [r7, #24]
  3710. 8001942: 4313 orrs r3, r2
  3711. 8001944: 61bb str r3, [r7, #24]
  3712. GPIOx->OSPEEDR = temp;
  3713. 8001946: 687b ldr r3, [r7, #4]
  3714. 8001948: 69ba ldr r2, [r7, #24]
  3715. 800194a: 609a str r2, [r3, #8]
  3716. /* Configure the IO Output Type */
  3717. temp = GPIOx->OTYPER;
  3718. 800194c: 687b ldr r3, [r7, #4]
  3719. 800194e: 685b ldr r3, [r3, #4]
  3720. 8001950: 61bb str r3, [r7, #24]
  3721. temp &= ~(GPIO_OTYPER_OT0 << position) ;
  3722. 8001952: 2201 movs r2, #1
  3723. 8001954: 69fb ldr r3, [r7, #28]
  3724. 8001956: fa02 f303 lsl.w r3, r2, r3
  3725. 800195a: 43db mvns r3, r3
  3726. 800195c: 69ba ldr r2, [r7, #24]
  3727. 800195e: 4013 ands r3, r2
  3728. 8001960: 61bb str r3, [r7, #24]
  3729. temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
  3730. 8001962: 683b ldr r3, [r7, #0]
  3731. 8001964: 685b ldr r3, [r3, #4]
  3732. 8001966: 091b lsrs r3, r3, #4
  3733. 8001968: f003 0201 and.w r2, r3, #1
  3734. 800196c: 69fb ldr r3, [r7, #28]
  3735. 800196e: fa02 f303 lsl.w r3, r2, r3
  3736. 8001972: 69ba ldr r2, [r7, #24]
  3737. 8001974: 4313 orrs r3, r2
  3738. 8001976: 61bb str r3, [r7, #24]
  3739. GPIOx->OTYPER = temp;
  3740. 8001978: 687b ldr r3, [r7, #4]
  3741. 800197a: 69ba ldr r2, [r7, #24]
  3742. 800197c: 605a str r2, [r3, #4]
  3743. }
  3744. if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
  3745. 800197e: 683b ldr r3, [r7, #0]
  3746. 8001980: 685b ldr r3, [r3, #4]
  3747. 8001982: f003 0303 and.w r3, r3, #3
  3748. 8001986: 2b03 cmp r3, #3
  3749. 8001988: d017 beq.n 80019ba <HAL_GPIO_Init+0xe2>
  3750. {
  3751. /* Check the Pull parameter */
  3752. assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
  3753. /* Activate the Pull-up or Pull down resistor for the current IO */
  3754. temp = GPIOx->PUPDR;
  3755. 800198a: 687b ldr r3, [r7, #4]
  3756. 800198c: 68db ldr r3, [r3, #12]
  3757. 800198e: 61bb str r3, [r7, #24]
  3758. temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
  3759. 8001990: 69fb ldr r3, [r7, #28]
  3760. 8001992: 005b lsls r3, r3, #1
  3761. 8001994: 2203 movs r2, #3
  3762. 8001996: fa02 f303 lsl.w r3, r2, r3
  3763. 800199a: 43db mvns r3, r3
  3764. 800199c: 69ba ldr r2, [r7, #24]
  3765. 800199e: 4013 ands r3, r2
  3766. 80019a0: 61bb str r3, [r7, #24]
  3767. temp |= ((GPIO_Init->Pull) << (position * 2U));
  3768. 80019a2: 683b ldr r3, [r7, #0]
  3769. 80019a4: 689a ldr r2, [r3, #8]
  3770. 80019a6: 69fb ldr r3, [r7, #28]
  3771. 80019a8: 005b lsls r3, r3, #1
  3772. 80019aa: fa02 f303 lsl.w r3, r2, r3
  3773. 80019ae: 69ba ldr r2, [r7, #24]
  3774. 80019b0: 4313 orrs r3, r2
  3775. 80019b2: 61bb str r3, [r7, #24]
  3776. GPIOx->PUPDR = temp;
  3777. 80019b4: 687b ldr r3, [r7, #4]
  3778. 80019b6: 69ba ldr r2, [r7, #24]
  3779. 80019b8: 60da str r2, [r3, #12]
  3780. }
  3781. /* In case of Alternate function mode selection */
  3782. if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
  3783. 80019ba: 683b ldr r3, [r7, #0]
  3784. 80019bc: 685b ldr r3, [r3, #4]
  3785. 80019be: f003 0303 and.w r3, r3, #3
  3786. 80019c2: 2b02 cmp r3, #2
  3787. 80019c4: d123 bne.n 8001a0e <HAL_GPIO_Init+0x136>
  3788. /* Check the Alternate function parameters */
  3789. assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
  3790. assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
  3791. /* Configure Alternate function mapped with the current IO */
  3792. temp = GPIOx->AFR[position >> 3U];
  3793. 80019c6: 69fb ldr r3, [r7, #28]
  3794. 80019c8: 08da lsrs r2, r3, #3
  3795. 80019ca: 687b ldr r3, [r7, #4]
  3796. 80019cc: 3208 adds r2, #8
  3797. 80019ce: f853 3022 ldr.w r3, [r3, r2, lsl #2]
  3798. 80019d2: 61bb str r3, [r7, #24]
  3799. temp &= ~(0xFU << ((position & 0x07U) * 4U));
  3800. 80019d4: 69fb ldr r3, [r7, #28]
  3801. 80019d6: f003 0307 and.w r3, r3, #7
  3802. 80019da: 009b lsls r3, r3, #2
  3803. 80019dc: 220f movs r2, #15
  3804. 80019de: fa02 f303 lsl.w r3, r2, r3
  3805. 80019e2: 43db mvns r3, r3
  3806. 80019e4: 69ba ldr r2, [r7, #24]
  3807. 80019e6: 4013 ands r3, r2
  3808. 80019e8: 61bb str r3, [r7, #24]
  3809. temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
  3810. 80019ea: 683b ldr r3, [r7, #0]
  3811. 80019ec: 691a ldr r2, [r3, #16]
  3812. 80019ee: 69fb ldr r3, [r7, #28]
  3813. 80019f0: f003 0307 and.w r3, r3, #7
  3814. 80019f4: 009b lsls r3, r3, #2
  3815. 80019f6: fa02 f303 lsl.w r3, r2, r3
  3816. 80019fa: 69ba ldr r2, [r7, #24]
  3817. 80019fc: 4313 orrs r3, r2
  3818. 80019fe: 61bb str r3, [r7, #24]
  3819. GPIOx->AFR[position >> 3U] = temp;
  3820. 8001a00: 69fb ldr r3, [r7, #28]
  3821. 8001a02: 08da lsrs r2, r3, #3
  3822. 8001a04: 687b ldr r3, [r7, #4]
  3823. 8001a06: 3208 adds r2, #8
  3824. 8001a08: 69b9 ldr r1, [r7, #24]
  3825. 8001a0a: f843 1022 str.w r1, [r3, r2, lsl #2]
  3826. }
  3827. /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
  3828. temp = GPIOx->MODER;
  3829. 8001a0e: 687b ldr r3, [r7, #4]
  3830. 8001a10: 681b ldr r3, [r3, #0]
  3831. 8001a12: 61bb str r3, [r7, #24]
  3832. temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
  3833. 8001a14: 69fb ldr r3, [r7, #28]
  3834. 8001a16: 005b lsls r3, r3, #1
  3835. 8001a18: 2203 movs r2, #3
  3836. 8001a1a: fa02 f303 lsl.w r3, r2, r3
  3837. 8001a1e: 43db mvns r3, r3
  3838. 8001a20: 69ba ldr r2, [r7, #24]
  3839. 8001a22: 4013 ands r3, r2
  3840. 8001a24: 61bb str r3, [r7, #24]
  3841. temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
  3842. 8001a26: 683b ldr r3, [r7, #0]
  3843. 8001a28: 685b ldr r3, [r3, #4]
  3844. 8001a2a: f003 0203 and.w r2, r3, #3
  3845. 8001a2e: 69fb ldr r3, [r7, #28]
  3846. 8001a30: 005b lsls r3, r3, #1
  3847. 8001a32: fa02 f303 lsl.w r3, r2, r3
  3848. 8001a36: 69ba ldr r2, [r7, #24]
  3849. 8001a38: 4313 orrs r3, r2
  3850. 8001a3a: 61bb str r3, [r7, #24]
  3851. GPIOx->MODER = temp;
  3852. 8001a3c: 687b ldr r3, [r7, #4]
  3853. 8001a3e: 69ba ldr r2, [r7, #24]
  3854. 8001a40: 601a str r2, [r3, #0]
  3855. /*--------------------- EXTI Mode Configuration ------------------------*/
  3856. /* Configure the External Interrupt or event for the current IO */
  3857. if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
  3858. 8001a42: 683b ldr r3, [r7, #0]
  3859. 8001a44: 685b ldr r3, [r3, #4]
  3860. 8001a46: f403 3340 and.w r3, r3, #196608 ; 0x30000
  3861. 8001a4a: 2b00 cmp r3, #0
  3862. 8001a4c: f000 80d8 beq.w 8001c00 <HAL_GPIO_Init+0x328>
  3863. {
  3864. /* Enable SYSCFG Clock */
  3865. __HAL_RCC_SYSCFG_CLK_ENABLE();
  3866. 8001a50: 4b2c ldr r3, [pc, #176] ; (8001b04 <HAL_GPIO_Init+0x22c>)
  3867. 8001a52: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4
  3868. 8001a56: 4a2b ldr r2, [pc, #172] ; (8001b04 <HAL_GPIO_Init+0x22c>)
  3869. 8001a58: f043 0302 orr.w r3, r3, #2
  3870. 8001a5c: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4
  3871. 8001a60: 4b28 ldr r3, [pc, #160] ; (8001b04 <HAL_GPIO_Init+0x22c>)
  3872. 8001a62: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4
  3873. 8001a66: f003 0302 and.w r3, r3, #2
  3874. 8001a6a: 60fb str r3, [r7, #12]
  3875. 8001a6c: 68fb ldr r3, [r7, #12]
  3876. temp = SYSCFG->EXTICR[position >> 2U];
  3877. 8001a6e: 4a26 ldr r2, [pc, #152] ; (8001b08 <HAL_GPIO_Init+0x230>)
  3878. 8001a70: 69fb ldr r3, [r7, #28]
  3879. 8001a72: 089b lsrs r3, r3, #2
  3880. 8001a74: 3302 adds r3, #2
  3881. 8001a76: f852 3023 ldr.w r3, [r2, r3, lsl #2]
  3882. 8001a7a: 61bb str r3, [r7, #24]
  3883. temp &= ~(0x0FUL << (4U * (position & 0x03U)));
  3884. 8001a7c: 69fb ldr r3, [r7, #28]
  3885. 8001a7e: f003 0303 and.w r3, r3, #3
  3886. 8001a82: 009b lsls r3, r3, #2
  3887. 8001a84: 220f movs r2, #15
  3888. 8001a86: fa02 f303 lsl.w r3, r2, r3
  3889. 8001a8a: 43db mvns r3, r3
  3890. 8001a8c: 69ba ldr r2, [r7, #24]
  3891. 8001a8e: 4013 ands r3, r2
  3892. 8001a90: 61bb str r3, [r7, #24]
  3893. temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
  3894. 8001a92: 687b ldr r3, [r7, #4]
  3895. 8001a94: 4a1d ldr r2, [pc, #116] ; (8001b0c <HAL_GPIO_Init+0x234>)
  3896. 8001a96: 4293 cmp r3, r2
  3897. 8001a98: d04a beq.n 8001b30 <HAL_GPIO_Init+0x258>
  3898. 8001a9a: 687b ldr r3, [r7, #4]
  3899. 8001a9c: 4a1c ldr r2, [pc, #112] ; (8001b10 <HAL_GPIO_Init+0x238>)
  3900. 8001a9e: 4293 cmp r3, r2
  3901. 8001aa0: d02b beq.n 8001afa <HAL_GPIO_Init+0x222>
  3902. 8001aa2: 687b ldr r3, [r7, #4]
  3903. 8001aa4: 4a1b ldr r2, [pc, #108] ; (8001b14 <HAL_GPIO_Init+0x23c>)
  3904. 8001aa6: 4293 cmp r3, r2
  3905. 8001aa8: d025 beq.n 8001af6 <HAL_GPIO_Init+0x21e>
  3906. 8001aaa: 687b ldr r3, [r7, #4]
  3907. 8001aac: 4a1a ldr r2, [pc, #104] ; (8001b18 <HAL_GPIO_Init+0x240>)
  3908. 8001aae: 4293 cmp r3, r2
  3909. 8001ab0: d01f beq.n 8001af2 <HAL_GPIO_Init+0x21a>
  3910. 8001ab2: 687b ldr r3, [r7, #4]
  3911. 8001ab4: 4a19 ldr r2, [pc, #100] ; (8001b1c <HAL_GPIO_Init+0x244>)
  3912. 8001ab6: 4293 cmp r3, r2
  3913. 8001ab8: d019 beq.n 8001aee <HAL_GPIO_Init+0x216>
  3914. 8001aba: 687b ldr r3, [r7, #4]
  3915. 8001abc: 4a18 ldr r2, [pc, #96] ; (8001b20 <HAL_GPIO_Init+0x248>)
  3916. 8001abe: 4293 cmp r3, r2
  3917. 8001ac0: d013 beq.n 8001aea <HAL_GPIO_Init+0x212>
  3918. 8001ac2: 687b ldr r3, [r7, #4]
  3919. 8001ac4: 4a17 ldr r2, [pc, #92] ; (8001b24 <HAL_GPIO_Init+0x24c>)
  3920. 8001ac6: 4293 cmp r3, r2
  3921. 8001ac8: d00d beq.n 8001ae6 <HAL_GPIO_Init+0x20e>
  3922. 8001aca: 687b ldr r3, [r7, #4]
  3923. 8001acc: 4a16 ldr r2, [pc, #88] ; (8001b28 <HAL_GPIO_Init+0x250>)
  3924. 8001ace: 4293 cmp r3, r2
  3925. 8001ad0: d007 beq.n 8001ae2 <HAL_GPIO_Init+0x20a>
  3926. 8001ad2: 687b ldr r3, [r7, #4]
  3927. 8001ad4: 4a15 ldr r2, [pc, #84] ; (8001b2c <HAL_GPIO_Init+0x254>)
  3928. 8001ad6: 4293 cmp r3, r2
  3929. 8001ad8: d101 bne.n 8001ade <HAL_GPIO_Init+0x206>
  3930. 8001ada: 2309 movs r3, #9
  3931. 8001adc: e029 b.n 8001b32 <HAL_GPIO_Init+0x25a>
  3932. 8001ade: 230a movs r3, #10
  3933. 8001ae0: e027 b.n 8001b32 <HAL_GPIO_Init+0x25a>
  3934. 8001ae2: 2307 movs r3, #7
  3935. 8001ae4: e025 b.n 8001b32 <HAL_GPIO_Init+0x25a>
  3936. 8001ae6: 2306 movs r3, #6
  3937. 8001ae8: e023 b.n 8001b32 <HAL_GPIO_Init+0x25a>
  3938. 8001aea: 2305 movs r3, #5
  3939. 8001aec: e021 b.n 8001b32 <HAL_GPIO_Init+0x25a>
  3940. 8001aee: 2304 movs r3, #4
  3941. 8001af0: e01f b.n 8001b32 <HAL_GPIO_Init+0x25a>
  3942. 8001af2: 2303 movs r3, #3
  3943. 8001af4: e01d b.n 8001b32 <HAL_GPIO_Init+0x25a>
  3944. 8001af6: 2302 movs r3, #2
  3945. 8001af8: e01b b.n 8001b32 <HAL_GPIO_Init+0x25a>
  3946. 8001afa: 2301 movs r3, #1
  3947. 8001afc: e019 b.n 8001b32 <HAL_GPIO_Init+0x25a>
  3948. 8001afe: bf00 nop
  3949. 8001b00: 58000080 .word 0x58000080
  3950. 8001b04: 58024400 .word 0x58024400
  3951. 8001b08: 58000400 .word 0x58000400
  3952. 8001b0c: 58020000 .word 0x58020000
  3953. 8001b10: 58020400 .word 0x58020400
  3954. 8001b14: 58020800 .word 0x58020800
  3955. 8001b18: 58020c00 .word 0x58020c00
  3956. 8001b1c: 58021000 .word 0x58021000
  3957. 8001b20: 58021400 .word 0x58021400
  3958. 8001b24: 58021800 .word 0x58021800
  3959. 8001b28: 58021c00 .word 0x58021c00
  3960. 8001b2c: 58022400 .word 0x58022400
  3961. 8001b30: 2300 movs r3, #0
  3962. 8001b32: 69fa ldr r2, [r7, #28]
  3963. 8001b34: f002 0203 and.w r2, r2, #3
  3964. 8001b38: 0092 lsls r2, r2, #2
  3965. 8001b3a: 4093 lsls r3, r2
  3966. 8001b3c: 69ba ldr r2, [r7, #24]
  3967. 8001b3e: 4313 orrs r3, r2
  3968. 8001b40: 61bb str r3, [r7, #24]
  3969. SYSCFG->EXTICR[position >> 2U] = temp;
  3970. 8001b42: 4938 ldr r1, [pc, #224] ; (8001c24 <HAL_GPIO_Init+0x34c>)
  3971. 8001b44: 69fb ldr r3, [r7, #28]
  3972. 8001b46: 089b lsrs r3, r3, #2
  3973. 8001b48: 3302 adds r3, #2
  3974. 8001b4a: 69ba ldr r2, [r7, #24]
  3975. 8001b4c: f841 2023 str.w r2, [r1, r3, lsl #2]
  3976. /* Clear Rising Falling edge configuration */
  3977. temp = EXTI->RTSR1;
  3978. 8001b50: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000
  3979. 8001b54: 681b ldr r3, [r3, #0]
  3980. 8001b56: 61bb str r3, [r7, #24]
  3981. temp &= ~(iocurrent);
  3982. 8001b58: 693b ldr r3, [r7, #16]
  3983. 8001b5a: 43db mvns r3, r3
  3984. 8001b5c: 69ba ldr r2, [r7, #24]
  3985. 8001b5e: 4013 ands r3, r2
  3986. 8001b60: 61bb str r3, [r7, #24]
  3987. if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
  3988. 8001b62: 683b ldr r3, [r7, #0]
  3989. 8001b64: 685b ldr r3, [r3, #4]
  3990. 8001b66: f403 1380 and.w r3, r3, #1048576 ; 0x100000
  3991. 8001b6a: 2b00 cmp r3, #0
  3992. 8001b6c: d003 beq.n 8001b76 <HAL_GPIO_Init+0x29e>
  3993. {
  3994. temp |= iocurrent;
  3995. 8001b6e: 69ba ldr r2, [r7, #24]
  3996. 8001b70: 693b ldr r3, [r7, #16]
  3997. 8001b72: 4313 orrs r3, r2
  3998. 8001b74: 61bb str r3, [r7, #24]
  3999. }
  4000. EXTI->RTSR1 = temp;
  4001. 8001b76: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000
  4002. 8001b7a: 69bb ldr r3, [r7, #24]
  4003. 8001b7c: 6013 str r3, [r2, #0]
  4004. temp = EXTI->FTSR1;
  4005. 8001b7e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000
  4006. 8001b82: 685b ldr r3, [r3, #4]
  4007. 8001b84: 61bb str r3, [r7, #24]
  4008. temp &= ~(iocurrent);
  4009. 8001b86: 693b ldr r3, [r7, #16]
  4010. 8001b88: 43db mvns r3, r3
  4011. 8001b8a: 69ba ldr r2, [r7, #24]
  4012. 8001b8c: 4013 ands r3, r2
  4013. 8001b8e: 61bb str r3, [r7, #24]
  4014. if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
  4015. 8001b90: 683b ldr r3, [r7, #0]
  4016. 8001b92: 685b ldr r3, [r3, #4]
  4017. 8001b94: f403 1300 and.w r3, r3, #2097152 ; 0x200000
  4018. 8001b98: 2b00 cmp r3, #0
  4019. 8001b9a: d003 beq.n 8001ba4 <HAL_GPIO_Init+0x2cc>
  4020. {
  4021. temp |= iocurrent;
  4022. 8001b9c: 69ba ldr r2, [r7, #24]
  4023. 8001b9e: 693b ldr r3, [r7, #16]
  4024. 8001ba0: 4313 orrs r3, r2
  4025. 8001ba2: 61bb str r3, [r7, #24]
  4026. }
  4027. EXTI->FTSR1 = temp;
  4028. 8001ba4: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000
  4029. 8001ba8: 69bb ldr r3, [r7, #24]
  4030. 8001baa: 6053 str r3, [r2, #4]
  4031. temp = EXTI_CurrentCPU->EMR1;
  4032. 8001bac: 697b ldr r3, [r7, #20]
  4033. 8001bae: 685b ldr r3, [r3, #4]
  4034. 8001bb0: 61bb str r3, [r7, #24]
  4035. temp &= ~(iocurrent);
  4036. 8001bb2: 693b ldr r3, [r7, #16]
  4037. 8001bb4: 43db mvns r3, r3
  4038. 8001bb6: 69ba ldr r2, [r7, #24]
  4039. 8001bb8: 4013 ands r3, r2
  4040. 8001bba: 61bb str r3, [r7, #24]
  4041. if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
  4042. 8001bbc: 683b ldr r3, [r7, #0]
  4043. 8001bbe: 685b ldr r3, [r3, #4]
  4044. 8001bc0: f403 3300 and.w r3, r3, #131072 ; 0x20000
  4045. 8001bc4: 2b00 cmp r3, #0
  4046. 8001bc6: d003 beq.n 8001bd0 <HAL_GPIO_Init+0x2f8>
  4047. {
  4048. temp |= iocurrent;
  4049. 8001bc8: 69ba ldr r2, [r7, #24]
  4050. 8001bca: 693b ldr r3, [r7, #16]
  4051. 8001bcc: 4313 orrs r3, r2
  4052. 8001bce: 61bb str r3, [r7, #24]
  4053. }
  4054. EXTI_CurrentCPU->EMR1 = temp;
  4055. 8001bd0: 697b ldr r3, [r7, #20]
  4056. 8001bd2: 69ba ldr r2, [r7, #24]
  4057. 8001bd4: 605a str r2, [r3, #4]
  4058. /* Clear EXTI line configuration */
  4059. temp = EXTI_CurrentCPU->IMR1;
  4060. 8001bd6: 697b ldr r3, [r7, #20]
  4061. 8001bd8: 681b ldr r3, [r3, #0]
  4062. 8001bda: 61bb str r3, [r7, #24]
  4063. temp &= ~(iocurrent);
  4064. 8001bdc: 693b ldr r3, [r7, #16]
  4065. 8001bde: 43db mvns r3, r3
  4066. 8001be0: 69ba ldr r2, [r7, #24]
  4067. 8001be2: 4013 ands r3, r2
  4068. 8001be4: 61bb str r3, [r7, #24]
  4069. if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
  4070. 8001be6: 683b ldr r3, [r7, #0]
  4071. 8001be8: 685b ldr r3, [r3, #4]
  4072. 8001bea: f403 3380 and.w r3, r3, #65536 ; 0x10000
  4073. 8001bee: 2b00 cmp r3, #0
  4074. 8001bf0: d003 beq.n 8001bfa <HAL_GPIO_Init+0x322>
  4075. {
  4076. temp |= iocurrent;
  4077. 8001bf2: 69ba ldr r2, [r7, #24]
  4078. 8001bf4: 693b ldr r3, [r7, #16]
  4079. 8001bf6: 4313 orrs r3, r2
  4080. 8001bf8: 61bb str r3, [r7, #24]
  4081. }
  4082. EXTI_CurrentCPU->IMR1 = temp;
  4083. 8001bfa: 697b ldr r3, [r7, #20]
  4084. 8001bfc: 69ba ldr r2, [r7, #24]
  4085. 8001bfe: 601a str r2, [r3, #0]
  4086. }
  4087. }
  4088. position++;
  4089. 8001c00: 69fb ldr r3, [r7, #28]
  4090. 8001c02: 3301 adds r3, #1
  4091. 8001c04: 61fb str r3, [r7, #28]
  4092. while (((GPIO_Init->Pin) >> position) != 0x00U)
  4093. 8001c06: 683b ldr r3, [r7, #0]
  4094. 8001c08: 681a ldr r2, [r3, #0]
  4095. 8001c0a: 69fb ldr r3, [r7, #28]
  4096. 8001c0c: fa22 f303 lsr.w r3, r2, r3
  4097. 8001c10: 2b00 cmp r3, #0
  4098. 8001c12: f47f ae6b bne.w 80018ec <HAL_GPIO_Init+0x14>
  4099. }
  4100. }
  4101. 8001c16: bf00 nop
  4102. 8001c18: bf00 nop
  4103. 8001c1a: 3724 adds r7, #36 ; 0x24
  4104. 8001c1c: 46bd mov sp, r7
  4105. 8001c1e: f85d 7b04 ldr.w r7, [sp], #4
  4106. 8001c22: 4770 bx lr
  4107. 8001c24: 58000400 .word 0x58000400
  4108. 08001c28 <HAL_GPIO_WritePin>:
  4109. * @arg GPIO_PIN_RESET: to clear the port pin
  4110. * @arg GPIO_PIN_SET: to set the port pin
  4111. * @retval None
  4112. */
  4113. void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
  4114. {
  4115. 8001c28: b480 push {r7}
  4116. 8001c2a: b083 sub sp, #12
  4117. 8001c2c: af00 add r7, sp, #0
  4118. 8001c2e: 6078 str r0, [r7, #4]
  4119. 8001c30: 460b mov r3, r1
  4120. 8001c32: 807b strh r3, [r7, #2]
  4121. 8001c34: 4613 mov r3, r2
  4122. 8001c36: 707b strb r3, [r7, #1]
  4123. /* Check the parameters */
  4124. assert_param(IS_GPIO_PIN(GPIO_Pin));
  4125. assert_param(IS_GPIO_PIN_ACTION(PinState));
  4126. if (PinState != GPIO_PIN_RESET)
  4127. 8001c38: 787b ldrb r3, [r7, #1]
  4128. 8001c3a: 2b00 cmp r3, #0
  4129. 8001c3c: d003 beq.n 8001c46 <HAL_GPIO_WritePin+0x1e>
  4130. {
  4131. GPIOx->BSRR = GPIO_Pin;
  4132. 8001c3e: 887a ldrh r2, [r7, #2]
  4133. 8001c40: 687b ldr r3, [r7, #4]
  4134. 8001c42: 619a str r2, [r3, #24]
  4135. }
  4136. else
  4137. {
  4138. GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
  4139. }
  4140. }
  4141. 8001c44: e003 b.n 8001c4e <HAL_GPIO_WritePin+0x26>
  4142. GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
  4143. 8001c46: 887b ldrh r3, [r7, #2]
  4144. 8001c48: 041a lsls r2, r3, #16
  4145. 8001c4a: 687b ldr r3, [r7, #4]
  4146. 8001c4c: 619a str r2, [r3, #24]
  4147. }
  4148. 8001c4e: bf00 nop
  4149. 8001c50: 370c adds r7, #12
  4150. 8001c52: 46bd mov sp, r7
  4151. 8001c54: f85d 7b04 ldr.w r7, [sp], #4
  4152. 8001c58: 4770 bx lr
  4153. 08001c5a <HAL_GPIO_TogglePin>:
  4154. * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral.
  4155. * @param GPIO_Pin: Specifies the pins to be toggled.
  4156. * @retval None
  4157. */
  4158. void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
  4159. {
  4160. 8001c5a: b480 push {r7}
  4161. 8001c5c: b085 sub sp, #20
  4162. 8001c5e: af00 add r7, sp, #0
  4163. 8001c60: 6078 str r0, [r7, #4]
  4164. 8001c62: 460b mov r3, r1
  4165. 8001c64: 807b strh r3, [r7, #2]
  4166. /* Check the parameters */
  4167. assert_param(IS_GPIO_PIN(GPIO_Pin));
  4168. /* get current Output Data Register value */
  4169. odr = GPIOx->ODR;
  4170. 8001c66: 687b ldr r3, [r7, #4]
  4171. 8001c68: 695b ldr r3, [r3, #20]
  4172. 8001c6a: 60fb str r3, [r7, #12]
  4173. /* Set selected pins that were at low level, and reset ones that were high */
  4174. GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
  4175. 8001c6c: 887a ldrh r2, [r7, #2]
  4176. 8001c6e: 68fb ldr r3, [r7, #12]
  4177. 8001c70: 4013 ands r3, r2
  4178. 8001c72: 041a lsls r2, r3, #16
  4179. 8001c74: 68fb ldr r3, [r7, #12]
  4180. 8001c76: 43d9 mvns r1, r3
  4181. 8001c78: 887b ldrh r3, [r7, #2]
  4182. 8001c7a: 400b ands r3, r1
  4183. 8001c7c: 431a orrs r2, r3
  4184. 8001c7e: 687b ldr r3, [r7, #4]
  4185. 8001c80: 619a str r2, [r3, #24]
  4186. }
  4187. 8001c82: bf00 nop
  4188. 8001c84: 3714 adds r7, #20
  4189. 8001c86: 46bd mov sp, r7
  4190. 8001c88: f85d 7b04 ldr.w r7, [sp], #4
  4191. 8001c8c: 4770 bx lr
  4192. 08001c8e <HAL_PCD_Init>:
  4193. * parameters in the PCD_InitTypeDef and initialize the associated handle.
  4194. * @param hpcd PCD handle
  4195. * @retval HAL status
  4196. */
  4197. HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
  4198. {
  4199. 8001c8e: b5f0 push {r4, r5, r6, r7, lr}
  4200. 8001c90: b08f sub sp, #60 ; 0x3c
  4201. 8001c92: af0a add r7, sp, #40 ; 0x28
  4202. 8001c94: 6078 str r0, [r7, #4]
  4203. USB_OTG_GlobalTypeDef *USBx;
  4204. uint8_t i;
  4205. /* Check the PCD handle allocation */
  4206. if (hpcd == NULL)
  4207. 8001c96: 687b ldr r3, [r7, #4]
  4208. 8001c98: 2b00 cmp r3, #0
  4209. 8001c9a: d101 bne.n 8001ca0 <HAL_PCD_Init+0x12>
  4210. {
  4211. return HAL_ERROR;
  4212. 8001c9c: 2301 movs r3, #1
  4213. 8001c9e: e116 b.n 8001ece <HAL_PCD_Init+0x240>
  4214. }
  4215. /* Check the parameters */
  4216. assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
  4217. USBx = hpcd->Instance;
  4218. 8001ca0: 687b ldr r3, [r7, #4]
  4219. 8001ca2: 681b ldr r3, [r3, #0]
  4220. 8001ca4: 60bb str r3, [r7, #8]
  4221. if (hpcd->State == HAL_PCD_STATE_RESET)
  4222. 8001ca6: 687b ldr r3, [r7, #4]
  4223. 8001ca8: f893 33bd ldrb.w r3, [r3, #957] ; 0x3bd
  4224. 8001cac: b2db uxtb r3, r3
  4225. 8001cae: 2b00 cmp r3, #0
  4226. 8001cb0: d106 bne.n 8001cc0 <HAL_PCD_Init+0x32>
  4227. {
  4228. /* Allocate lock resource and initialize it */
  4229. hpcd->Lock = HAL_UNLOCKED;
  4230. 8001cb2: 687b ldr r3, [r7, #4]
  4231. 8001cb4: 2200 movs r2, #0
  4232. 8001cb6: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  4233. /* Init the low level hardware */
  4234. hpcd->MspInitCallback(hpcd);
  4235. #else
  4236. /* Init the low level hardware : GPIO, CLOCK, NVIC... */
  4237. HAL_PCD_MspInit(hpcd);
  4238. 8001cba: 6878 ldr r0, [r7, #4]
  4239. 8001cbc: f007 fad2 bl 8009264 <HAL_PCD_MspInit>
  4240. #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
  4241. }
  4242. hpcd->State = HAL_PCD_STATE_BUSY;
  4243. 8001cc0: 687b ldr r3, [r7, #4]
  4244. 8001cc2: 2203 movs r2, #3
  4245. 8001cc4: f883 23bd strb.w r2, [r3, #957] ; 0x3bd
  4246. /* Disable DMA mode for FS instance */
  4247. if ((USBx->CID & (0x1U << 8)) == 0U)
  4248. 8001cc8: 68bb ldr r3, [r7, #8]
  4249. 8001cca: 6bdb ldr r3, [r3, #60] ; 0x3c
  4250. 8001ccc: f403 7380 and.w r3, r3, #256 ; 0x100
  4251. 8001cd0: 2b00 cmp r3, #0
  4252. 8001cd2: d102 bne.n 8001cda <HAL_PCD_Init+0x4c>
  4253. {
  4254. hpcd->Init.dma_enable = 0U;
  4255. 8001cd4: 687b ldr r3, [r7, #4]
  4256. 8001cd6: 2200 movs r2, #0
  4257. 8001cd8: 611a str r2, [r3, #16]
  4258. }
  4259. /* Disable the Interrupts */
  4260. __HAL_PCD_DISABLE(hpcd);
  4261. 8001cda: 687b ldr r3, [r7, #4]
  4262. 8001cdc: 681b ldr r3, [r3, #0]
  4263. 8001cde: 4618 mov r0, r3
  4264. 8001ce0: f004 f99f bl 8006022 <USB_DisableGlobalInt>
  4265. /*Init the Core (common init.) */
  4266. if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
  4267. 8001ce4: 687b ldr r3, [r7, #4]
  4268. 8001ce6: 681b ldr r3, [r3, #0]
  4269. 8001ce8: 603b str r3, [r7, #0]
  4270. 8001cea: 687e ldr r6, [r7, #4]
  4271. 8001cec: 466d mov r5, sp
  4272. 8001cee: f106 0410 add.w r4, r6, #16
  4273. 8001cf2: cc0f ldmia r4!, {r0, r1, r2, r3}
  4274. 8001cf4: c50f stmia r5!, {r0, r1, r2, r3}
  4275. 8001cf6: cc0f ldmia r4!, {r0, r1, r2, r3}
  4276. 8001cf8: c50f stmia r5!, {r0, r1, r2, r3}
  4277. 8001cfa: e894 0003 ldmia.w r4, {r0, r1}
  4278. 8001cfe: e885 0003 stmia.w r5, {r0, r1}
  4279. 8001d02: 1d33 adds r3, r6, #4
  4280. 8001d04: cb0e ldmia r3, {r1, r2, r3}
  4281. 8001d06: 6838 ldr r0, [r7, #0]
  4282. 8001d08: f004 f86a bl 8005de0 <USB_CoreInit>
  4283. 8001d0c: 4603 mov r3, r0
  4284. 8001d0e: 2b00 cmp r3, #0
  4285. 8001d10: d005 beq.n 8001d1e <HAL_PCD_Init+0x90>
  4286. {
  4287. hpcd->State = HAL_PCD_STATE_ERROR;
  4288. 8001d12: 687b ldr r3, [r7, #4]
  4289. 8001d14: 2202 movs r2, #2
  4290. 8001d16: f883 23bd strb.w r2, [r3, #957] ; 0x3bd
  4291. return HAL_ERROR;
  4292. 8001d1a: 2301 movs r3, #1
  4293. 8001d1c: e0d7 b.n 8001ece <HAL_PCD_Init+0x240>
  4294. }
  4295. /* Force Device Mode*/
  4296. (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
  4297. 8001d1e: 687b ldr r3, [r7, #4]
  4298. 8001d20: 681b ldr r3, [r3, #0]
  4299. 8001d22: 2100 movs r1, #0
  4300. 8001d24: 4618 mov r0, r3
  4301. 8001d26: f004 f98d bl 8006044 <USB_SetCurrentMode>
  4302. /* Init endpoints structures */
  4303. for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
  4304. 8001d2a: 2300 movs r3, #0
  4305. 8001d2c: 73fb strb r3, [r7, #15]
  4306. 8001d2e: e04a b.n 8001dc6 <HAL_PCD_Init+0x138>
  4307. {
  4308. /* Init ep structure */
  4309. hpcd->IN_ep[i].is_in = 1U;
  4310. 8001d30: 7bfa ldrb r2, [r7, #15]
  4311. 8001d32: 6879 ldr r1, [r7, #4]
  4312. 8001d34: 4613 mov r3, r2
  4313. 8001d36: 00db lsls r3, r3, #3
  4314. 8001d38: 1a9b subs r3, r3, r2
  4315. 8001d3a: 009b lsls r3, r3, #2
  4316. 8001d3c: 440b add r3, r1
  4317. 8001d3e: 333d adds r3, #61 ; 0x3d
  4318. 8001d40: 2201 movs r2, #1
  4319. 8001d42: 701a strb r2, [r3, #0]
  4320. hpcd->IN_ep[i].num = i;
  4321. 8001d44: 7bfa ldrb r2, [r7, #15]
  4322. 8001d46: 6879 ldr r1, [r7, #4]
  4323. 8001d48: 4613 mov r3, r2
  4324. 8001d4a: 00db lsls r3, r3, #3
  4325. 8001d4c: 1a9b subs r3, r3, r2
  4326. 8001d4e: 009b lsls r3, r3, #2
  4327. 8001d50: 440b add r3, r1
  4328. 8001d52: 333c adds r3, #60 ; 0x3c
  4329. 8001d54: 7bfa ldrb r2, [r7, #15]
  4330. 8001d56: 701a strb r2, [r3, #0]
  4331. hpcd->IN_ep[i].tx_fifo_num = i;
  4332. 8001d58: 7bfa ldrb r2, [r7, #15]
  4333. 8001d5a: 7bfb ldrb r3, [r7, #15]
  4334. 8001d5c: b298 uxth r0, r3
  4335. 8001d5e: 6879 ldr r1, [r7, #4]
  4336. 8001d60: 4613 mov r3, r2
  4337. 8001d62: 00db lsls r3, r3, #3
  4338. 8001d64: 1a9b subs r3, r3, r2
  4339. 8001d66: 009b lsls r3, r3, #2
  4340. 8001d68: 440b add r3, r1
  4341. 8001d6a: 3342 adds r3, #66 ; 0x42
  4342. 8001d6c: 4602 mov r2, r0
  4343. 8001d6e: 801a strh r2, [r3, #0]
  4344. /* Control until ep is activated */
  4345. hpcd->IN_ep[i].type = EP_TYPE_CTRL;
  4346. 8001d70: 7bfa ldrb r2, [r7, #15]
  4347. 8001d72: 6879 ldr r1, [r7, #4]
  4348. 8001d74: 4613 mov r3, r2
  4349. 8001d76: 00db lsls r3, r3, #3
  4350. 8001d78: 1a9b subs r3, r3, r2
  4351. 8001d7a: 009b lsls r3, r3, #2
  4352. 8001d7c: 440b add r3, r1
  4353. 8001d7e: 333f adds r3, #63 ; 0x3f
  4354. 8001d80: 2200 movs r2, #0
  4355. 8001d82: 701a strb r2, [r3, #0]
  4356. hpcd->IN_ep[i].maxpacket = 0U;
  4357. 8001d84: 7bfa ldrb r2, [r7, #15]
  4358. 8001d86: 6879 ldr r1, [r7, #4]
  4359. 8001d88: 4613 mov r3, r2
  4360. 8001d8a: 00db lsls r3, r3, #3
  4361. 8001d8c: 1a9b subs r3, r3, r2
  4362. 8001d8e: 009b lsls r3, r3, #2
  4363. 8001d90: 440b add r3, r1
  4364. 8001d92: 3344 adds r3, #68 ; 0x44
  4365. 8001d94: 2200 movs r2, #0
  4366. 8001d96: 601a str r2, [r3, #0]
  4367. hpcd->IN_ep[i].xfer_buff = 0U;
  4368. 8001d98: 7bfa ldrb r2, [r7, #15]
  4369. 8001d9a: 6879 ldr r1, [r7, #4]
  4370. 8001d9c: 4613 mov r3, r2
  4371. 8001d9e: 00db lsls r3, r3, #3
  4372. 8001da0: 1a9b subs r3, r3, r2
  4373. 8001da2: 009b lsls r3, r3, #2
  4374. 8001da4: 440b add r3, r1
  4375. 8001da6: 3348 adds r3, #72 ; 0x48
  4376. 8001da8: 2200 movs r2, #0
  4377. 8001daa: 601a str r2, [r3, #0]
  4378. hpcd->IN_ep[i].xfer_len = 0U;
  4379. 8001dac: 7bfa ldrb r2, [r7, #15]
  4380. 8001dae: 6879 ldr r1, [r7, #4]
  4381. 8001db0: 4613 mov r3, r2
  4382. 8001db2: 00db lsls r3, r3, #3
  4383. 8001db4: 1a9b subs r3, r3, r2
  4384. 8001db6: 009b lsls r3, r3, #2
  4385. 8001db8: 440b add r3, r1
  4386. 8001dba: 3350 adds r3, #80 ; 0x50
  4387. 8001dbc: 2200 movs r2, #0
  4388. 8001dbe: 601a str r2, [r3, #0]
  4389. for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
  4390. 8001dc0: 7bfb ldrb r3, [r7, #15]
  4391. 8001dc2: 3301 adds r3, #1
  4392. 8001dc4: 73fb strb r3, [r7, #15]
  4393. 8001dc6: 7bfa ldrb r2, [r7, #15]
  4394. 8001dc8: 687b ldr r3, [r7, #4]
  4395. 8001dca: 685b ldr r3, [r3, #4]
  4396. 8001dcc: 429a cmp r2, r3
  4397. 8001dce: d3af bcc.n 8001d30 <HAL_PCD_Init+0xa2>
  4398. }
  4399. for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
  4400. 8001dd0: 2300 movs r3, #0
  4401. 8001dd2: 73fb strb r3, [r7, #15]
  4402. 8001dd4: e044 b.n 8001e60 <HAL_PCD_Init+0x1d2>
  4403. {
  4404. hpcd->OUT_ep[i].is_in = 0U;
  4405. 8001dd6: 7bfa ldrb r2, [r7, #15]
  4406. 8001dd8: 6879 ldr r1, [r7, #4]
  4407. 8001dda: 4613 mov r3, r2
  4408. 8001ddc: 00db lsls r3, r3, #3
  4409. 8001dde: 1a9b subs r3, r3, r2
  4410. 8001de0: 009b lsls r3, r3, #2
  4411. 8001de2: 440b add r3, r1
  4412. 8001de4: f203 13fd addw r3, r3, #509 ; 0x1fd
  4413. 8001de8: 2200 movs r2, #0
  4414. 8001dea: 701a strb r2, [r3, #0]
  4415. hpcd->OUT_ep[i].num = i;
  4416. 8001dec: 7bfa ldrb r2, [r7, #15]
  4417. 8001dee: 6879 ldr r1, [r7, #4]
  4418. 8001df0: 4613 mov r3, r2
  4419. 8001df2: 00db lsls r3, r3, #3
  4420. 8001df4: 1a9b subs r3, r3, r2
  4421. 8001df6: 009b lsls r3, r3, #2
  4422. 8001df8: 440b add r3, r1
  4423. 8001dfa: f503 73fe add.w r3, r3, #508 ; 0x1fc
  4424. 8001dfe: 7bfa ldrb r2, [r7, #15]
  4425. 8001e00: 701a strb r2, [r3, #0]
  4426. /* Control until ep is activated */
  4427. hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
  4428. 8001e02: 7bfa ldrb r2, [r7, #15]
  4429. 8001e04: 6879 ldr r1, [r7, #4]
  4430. 8001e06: 4613 mov r3, r2
  4431. 8001e08: 00db lsls r3, r3, #3
  4432. 8001e0a: 1a9b subs r3, r3, r2
  4433. 8001e0c: 009b lsls r3, r3, #2
  4434. 8001e0e: 440b add r3, r1
  4435. 8001e10: f203 13ff addw r3, r3, #511 ; 0x1ff
  4436. 8001e14: 2200 movs r2, #0
  4437. 8001e16: 701a strb r2, [r3, #0]
  4438. hpcd->OUT_ep[i].maxpacket = 0U;
  4439. 8001e18: 7bfa ldrb r2, [r7, #15]
  4440. 8001e1a: 6879 ldr r1, [r7, #4]
  4441. 8001e1c: 4613 mov r3, r2
  4442. 8001e1e: 00db lsls r3, r3, #3
  4443. 8001e20: 1a9b subs r3, r3, r2
  4444. 8001e22: 009b lsls r3, r3, #2
  4445. 8001e24: 440b add r3, r1
  4446. 8001e26: f503 7301 add.w r3, r3, #516 ; 0x204
  4447. 8001e2a: 2200 movs r2, #0
  4448. 8001e2c: 601a str r2, [r3, #0]
  4449. hpcd->OUT_ep[i].xfer_buff = 0U;
  4450. 8001e2e: 7bfa ldrb r2, [r7, #15]
  4451. 8001e30: 6879 ldr r1, [r7, #4]
  4452. 8001e32: 4613 mov r3, r2
  4453. 8001e34: 00db lsls r3, r3, #3
  4454. 8001e36: 1a9b subs r3, r3, r2
  4455. 8001e38: 009b lsls r3, r3, #2
  4456. 8001e3a: 440b add r3, r1
  4457. 8001e3c: f503 7302 add.w r3, r3, #520 ; 0x208
  4458. 8001e40: 2200 movs r2, #0
  4459. 8001e42: 601a str r2, [r3, #0]
  4460. hpcd->OUT_ep[i].xfer_len = 0U;
  4461. 8001e44: 7bfa ldrb r2, [r7, #15]
  4462. 8001e46: 6879 ldr r1, [r7, #4]
  4463. 8001e48: 4613 mov r3, r2
  4464. 8001e4a: 00db lsls r3, r3, #3
  4465. 8001e4c: 1a9b subs r3, r3, r2
  4466. 8001e4e: 009b lsls r3, r3, #2
  4467. 8001e50: 440b add r3, r1
  4468. 8001e52: f503 7304 add.w r3, r3, #528 ; 0x210
  4469. 8001e56: 2200 movs r2, #0
  4470. 8001e58: 601a str r2, [r3, #0]
  4471. for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
  4472. 8001e5a: 7bfb ldrb r3, [r7, #15]
  4473. 8001e5c: 3301 adds r3, #1
  4474. 8001e5e: 73fb strb r3, [r7, #15]
  4475. 8001e60: 7bfa ldrb r2, [r7, #15]
  4476. 8001e62: 687b ldr r3, [r7, #4]
  4477. 8001e64: 685b ldr r3, [r3, #4]
  4478. 8001e66: 429a cmp r2, r3
  4479. 8001e68: d3b5 bcc.n 8001dd6 <HAL_PCD_Init+0x148>
  4480. }
  4481. /* Init Device */
  4482. if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
  4483. 8001e6a: 687b ldr r3, [r7, #4]
  4484. 8001e6c: 681b ldr r3, [r3, #0]
  4485. 8001e6e: 603b str r3, [r7, #0]
  4486. 8001e70: 687e ldr r6, [r7, #4]
  4487. 8001e72: 466d mov r5, sp
  4488. 8001e74: f106 0410 add.w r4, r6, #16
  4489. 8001e78: cc0f ldmia r4!, {r0, r1, r2, r3}
  4490. 8001e7a: c50f stmia r5!, {r0, r1, r2, r3}
  4491. 8001e7c: cc0f ldmia r4!, {r0, r1, r2, r3}
  4492. 8001e7e: c50f stmia r5!, {r0, r1, r2, r3}
  4493. 8001e80: e894 0003 ldmia.w r4, {r0, r1}
  4494. 8001e84: e885 0003 stmia.w r5, {r0, r1}
  4495. 8001e88: 1d33 adds r3, r6, #4
  4496. 8001e8a: cb0e ldmia r3, {r1, r2, r3}
  4497. 8001e8c: 6838 ldr r0, [r7, #0]
  4498. 8001e8e: f004 f925 bl 80060dc <USB_DevInit>
  4499. 8001e92: 4603 mov r3, r0
  4500. 8001e94: 2b00 cmp r3, #0
  4501. 8001e96: d005 beq.n 8001ea4 <HAL_PCD_Init+0x216>
  4502. {
  4503. hpcd->State = HAL_PCD_STATE_ERROR;
  4504. 8001e98: 687b ldr r3, [r7, #4]
  4505. 8001e9a: 2202 movs r2, #2
  4506. 8001e9c: f883 23bd strb.w r2, [r3, #957] ; 0x3bd
  4507. return HAL_ERROR;
  4508. 8001ea0: 2301 movs r3, #1
  4509. 8001ea2: e014 b.n 8001ece <HAL_PCD_Init+0x240>
  4510. }
  4511. hpcd->USB_Address = 0U;
  4512. 8001ea4: 687b ldr r3, [r7, #4]
  4513. 8001ea6: 2200 movs r2, #0
  4514. 8001ea8: f883 2038 strb.w r2, [r3, #56] ; 0x38
  4515. hpcd->State = HAL_PCD_STATE_READY;
  4516. 8001eac: 687b ldr r3, [r7, #4]
  4517. 8001eae: 2201 movs r2, #1
  4518. 8001eb0: f883 23bd strb.w r2, [r3, #957] ; 0x3bd
  4519. /* Activate LPM */
  4520. if (hpcd->Init.lpm_enable == 1U)
  4521. 8001eb4: 687b ldr r3, [r7, #4]
  4522. 8001eb6: 6a5b ldr r3, [r3, #36] ; 0x24
  4523. 8001eb8: 2b01 cmp r3, #1
  4524. 8001eba: d102 bne.n 8001ec2 <HAL_PCD_Init+0x234>
  4525. {
  4526. (void)HAL_PCDEx_ActivateLPM(hpcd);
  4527. 8001ebc: 6878 ldr r0, [r7, #4]
  4528. 8001ebe: f001 f885 bl 8002fcc <HAL_PCDEx_ActivateLPM>
  4529. }
  4530. (void)USB_DevDisconnect(hpcd->Instance);
  4531. 8001ec2: 687b ldr r3, [r7, #4]
  4532. 8001ec4: 681b ldr r3, [r3, #0]
  4533. 8001ec6: 4618 mov r0, r3
  4534. 8001ec8: f005 f9bd bl 8007246 <USB_DevDisconnect>
  4535. return HAL_OK;
  4536. 8001ecc: 2300 movs r3, #0
  4537. }
  4538. 8001ece: 4618 mov r0, r3
  4539. 8001ed0: 3714 adds r7, #20
  4540. 8001ed2: 46bd mov sp, r7
  4541. 8001ed4: bdf0 pop {r4, r5, r6, r7, pc}
  4542. 08001ed6 <HAL_PCD_Start>:
  4543. * @brief Start the USB device
  4544. * @param hpcd PCD handle
  4545. * @retval HAL status
  4546. */
  4547. HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
  4548. {
  4549. 8001ed6: b580 push {r7, lr}
  4550. 8001ed8: b084 sub sp, #16
  4551. 8001eda: af00 add r7, sp, #0
  4552. 8001edc: 6078 str r0, [r7, #4]
  4553. USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
  4554. 8001ede: 687b ldr r3, [r7, #4]
  4555. 8001ee0: 681b ldr r3, [r3, #0]
  4556. 8001ee2: 60fb str r3, [r7, #12]
  4557. __HAL_LOCK(hpcd);
  4558. 8001ee4: 687b ldr r3, [r7, #4]
  4559. 8001ee6: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc
  4560. 8001eea: 2b01 cmp r3, #1
  4561. 8001eec: d101 bne.n 8001ef2 <HAL_PCD_Start+0x1c>
  4562. 8001eee: 2302 movs r3, #2
  4563. 8001ef0: e020 b.n 8001f34 <HAL_PCD_Start+0x5e>
  4564. 8001ef2: 687b ldr r3, [r7, #4]
  4565. 8001ef4: 2201 movs r2, #1
  4566. 8001ef6: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  4567. if ((hpcd->Init.battery_charging_enable == 1U) &&
  4568. 8001efa: 687b ldr r3, [r7, #4]
  4569. 8001efc: 6a9b ldr r3, [r3, #40] ; 0x28
  4570. 8001efe: 2b01 cmp r3, #1
  4571. 8001f00: d109 bne.n 8001f16 <HAL_PCD_Start+0x40>
  4572. (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
  4573. 8001f02: 687b ldr r3, [r7, #4]
  4574. 8001f04: 699b ldr r3, [r3, #24]
  4575. if ((hpcd->Init.battery_charging_enable == 1U) &&
  4576. 8001f06: 2b01 cmp r3, #1
  4577. 8001f08: d005 beq.n 8001f16 <HAL_PCD_Start+0x40>
  4578. {
  4579. /* Enable USB Transceiver */
  4580. USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
  4581. 8001f0a: 68fb ldr r3, [r7, #12]
  4582. 8001f0c: 6b9b ldr r3, [r3, #56] ; 0x38
  4583. 8001f0e: f443 3280 orr.w r2, r3, #65536 ; 0x10000
  4584. 8001f12: 68fb ldr r3, [r7, #12]
  4585. 8001f14: 639a str r2, [r3, #56] ; 0x38
  4586. }
  4587. __HAL_PCD_ENABLE(hpcd);
  4588. 8001f16: 687b ldr r3, [r7, #4]
  4589. 8001f18: 681b ldr r3, [r3, #0]
  4590. 8001f1a: 4618 mov r0, r3
  4591. 8001f1c: f004 f870 bl 8006000 <USB_EnableGlobalInt>
  4592. (void)USB_DevConnect(hpcd->Instance);
  4593. 8001f20: 687b ldr r3, [r7, #4]
  4594. 8001f22: 681b ldr r3, [r3, #0]
  4595. 8001f24: 4618 mov r0, r3
  4596. 8001f26: f005 f96d bl 8007204 <USB_DevConnect>
  4597. __HAL_UNLOCK(hpcd);
  4598. 8001f2a: 687b ldr r3, [r7, #4]
  4599. 8001f2c: 2200 movs r2, #0
  4600. 8001f2e: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  4601. return HAL_OK;
  4602. 8001f32: 2300 movs r3, #0
  4603. }
  4604. 8001f34: 4618 mov r0, r3
  4605. 8001f36: 3710 adds r7, #16
  4606. 8001f38: 46bd mov sp, r7
  4607. 8001f3a: bd80 pop {r7, pc}
  4608. 08001f3c <HAL_PCD_IRQHandler>:
  4609. * @brief Handles PCD interrupt request.
  4610. * @param hpcd PCD handle
  4611. * @retval HAL status
  4612. */
  4613. void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
  4614. {
  4615. 8001f3c: b590 push {r4, r7, lr}
  4616. 8001f3e: b08d sub sp, #52 ; 0x34
  4617. 8001f40: af00 add r7, sp, #0
  4618. 8001f42: 6078 str r0, [r7, #4]
  4619. USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
  4620. 8001f44: 687b ldr r3, [r7, #4]
  4621. 8001f46: 681b ldr r3, [r3, #0]
  4622. 8001f48: 623b str r3, [r7, #32]
  4623. uint32_t USBx_BASE = (uint32_t)USBx;
  4624. 8001f4a: 6a3b ldr r3, [r7, #32]
  4625. 8001f4c: 61fb str r3, [r7, #28]
  4626. uint32_t epnum;
  4627. uint32_t fifoemptymsk;
  4628. uint32_t temp;
  4629. /* ensure that we are in device mode */
  4630. if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
  4631. 8001f4e: 687b ldr r3, [r7, #4]
  4632. 8001f50: 681b ldr r3, [r3, #0]
  4633. 8001f52: 4618 mov r0, r3
  4634. 8001f54: f005 fa2b bl 80073ae <USB_GetMode>
  4635. 8001f58: 4603 mov r3, r0
  4636. 8001f5a: 2b00 cmp r3, #0
  4637. 8001f5c: f040 83be bne.w 80026dc <HAL_PCD_IRQHandler+0x7a0>
  4638. {
  4639. /* avoid spurious interrupt */
  4640. if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
  4641. 8001f60: 687b ldr r3, [r7, #4]
  4642. 8001f62: 681b ldr r3, [r3, #0]
  4643. 8001f64: 4618 mov r0, r3
  4644. 8001f66: f005 f98f bl 8007288 <USB_ReadInterrupts>
  4645. 8001f6a: 4603 mov r3, r0
  4646. 8001f6c: 2b00 cmp r3, #0
  4647. 8001f6e: f000 83b4 beq.w 80026da <HAL_PCD_IRQHandler+0x79e>
  4648. {
  4649. return;
  4650. }
  4651. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
  4652. 8001f72: 687b ldr r3, [r7, #4]
  4653. 8001f74: 681b ldr r3, [r3, #0]
  4654. 8001f76: 4618 mov r0, r3
  4655. 8001f78: f005 f986 bl 8007288 <USB_ReadInterrupts>
  4656. 8001f7c: 4603 mov r3, r0
  4657. 8001f7e: f003 0302 and.w r3, r3, #2
  4658. 8001f82: 2b02 cmp r3, #2
  4659. 8001f84: d107 bne.n 8001f96 <HAL_PCD_IRQHandler+0x5a>
  4660. {
  4661. /* incorrect mode, acknowledge the interrupt */
  4662. __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
  4663. 8001f86: 687b ldr r3, [r7, #4]
  4664. 8001f88: 681b ldr r3, [r3, #0]
  4665. 8001f8a: 695a ldr r2, [r3, #20]
  4666. 8001f8c: 687b ldr r3, [r7, #4]
  4667. 8001f8e: 681b ldr r3, [r3, #0]
  4668. 8001f90: f002 0202 and.w r2, r2, #2
  4669. 8001f94: 615a str r2, [r3, #20]
  4670. }
  4671. /* Handle RxQLevel Interrupt */
  4672. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
  4673. 8001f96: 687b ldr r3, [r7, #4]
  4674. 8001f98: 681b ldr r3, [r3, #0]
  4675. 8001f9a: 4618 mov r0, r3
  4676. 8001f9c: f005 f974 bl 8007288 <USB_ReadInterrupts>
  4677. 8001fa0: 4603 mov r3, r0
  4678. 8001fa2: f003 0310 and.w r3, r3, #16
  4679. 8001fa6: 2b10 cmp r3, #16
  4680. 8001fa8: d161 bne.n 800206e <HAL_PCD_IRQHandler+0x132>
  4681. {
  4682. USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
  4683. 8001faa: 687b ldr r3, [r7, #4]
  4684. 8001fac: 681b ldr r3, [r3, #0]
  4685. 8001fae: 699a ldr r2, [r3, #24]
  4686. 8001fb0: 687b ldr r3, [r7, #4]
  4687. 8001fb2: 681b ldr r3, [r3, #0]
  4688. 8001fb4: f022 0210 bic.w r2, r2, #16
  4689. 8001fb8: 619a str r2, [r3, #24]
  4690. temp = USBx->GRXSTSP;
  4691. 8001fba: 6a3b ldr r3, [r7, #32]
  4692. 8001fbc: 6a1b ldr r3, [r3, #32]
  4693. 8001fbe: 61bb str r3, [r7, #24]
  4694. ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
  4695. 8001fc0: 69bb ldr r3, [r7, #24]
  4696. 8001fc2: f003 020f and.w r2, r3, #15
  4697. 8001fc6: 4613 mov r3, r2
  4698. 8001fc8: 00db lsls r3, r3, #3
  4699. 8001fca: 1a9b subs r3, r3, r2
  4700. 8001fcc: 009b lsls r3, r3, #2
  4701. 8001fce: f503 73fc add.w r3, r3, #504 ; 0x1f8
  4702. 8001fd2: 687a ldr r2, [r7, #4]
  4703. 8001fd4: 4413 add r3, r2
  4704. 8001fd6: 3304 adds r3, #4
  4705. 8001fd8: 617b str r3, [r7, #20]
  4706. if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
  4707. 8001fda: 69bb ldr r3, [r7, #24]
  4708. 8001fdc: 0c5b lsrs r3, r3, #17
  4709. 8001fde: f003 030f and.w r3, r3, #15
  4710. 8001fe2: 2b02 cmp r3, #2
  4711. 8001fe4: d124 bne.n 8002030 <HAL_PCD_IRQHandler+0xf4>
  4712. {
  4713. if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
  4714. 8001fe6: 69ba ldr r2, [r7, #24]
  4715. 8001fe8: f647 73f0 movw r3, #32752 ; 0x7ff0
  4716. 8001fec: 4013 ands r3, r2
  4717. 8001fee: 2b00 cmp r3, #0
  4718. 8001ff0: d035 beq.n 800205e <HAL_PCD_IRQHandler+0x122>
  4719. {
  4720. (void)USB_ReadPacket(USBx, ep->xfer_buff,
  4721. 8001ff2: 697b ldr r3, [r7, #20]
  4722. 8001ff4: 68d9 ldr r1, [r3, #12]
  4723. (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
  4724. 8001ff6: 69bb ldr r3, [r7, #24]
  4725. 8001ff8: 091b lsrs r3, r3, #4
  4726. 8001ffa: b29b uxth r3, r3
  4727. (void)USB_ReadPacket(USBx, ep->xfer_buff,
  4728. 8001ffc: f3c3 030a ubfx r3, r3, #0, #11
  4729. 8002000: b29b uxth r3, r3
  4730. 8002002: 461a mov r2, r3
  4731. 8002004: 6a38 ldr r0, [r7, #32]
  4732. 8002006: f004 ffab bl 8006f60 <USB_ReadPacket>
  4733. ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
  4734. 800200a: 697b ldr r3, [r7, #20]
  4735. 800200c: 68da ldr r2, [r3, #12]
  4736. 800200e: 69bb ldr r3, [r7, #24]
  4737. 8002010: 091b lsrs r3, r3, #4
  4738. 8002012: f3c3 030a ubfx r3, r3, #0, #11
  4739. 8002016: 441a add r2, r3
  4740. 8002018: 697b ldr r3, [r7, #20]
  4741. 800201a: 60da str r2, [r3, #12]
  4742. ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
  4743. 800201c: 697b ldr r3, [r7, #20]
  4744. 800201e: 699a ldr r2, [r3, #24]
  4745. 8002020: 69bb ldr r3, [r7, #24]
  4746. 8002022: 091b lsrs r3, r3, #4
  4747. 8002024: f3c3 030a ubfx r3, r3, #0, #11
  4748. 8002028: 441a add r2, r3
  4749. 800202a: 697b ldr r3, [r7, #20]
  4750. 800202c: 619a str r2, [r3, #24]
  4751. 800202e: e016 b.n 800205e <HAL_PCD_IRQHandler+0x122>
  4752. }
  4753. }
  4754. else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
  4755. 8002030: 69bb ldr r3, [r7, #24]
  4756. 8002032: 0c5b lsrs r3, r3, #17
  4757. 8002034: f003 030f and.w r3, r3, #15
  4758. 8002038: 2b06 cmp r3, #6
  4759. 800203a: d110 bne.n 800205e <HAL_PCD_IRQHandler+0x122>
  4760. {
  4761. (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
  4762. 800203c: 687b ldr r3, [r7, #4]
  4763. 800203e: f503 7371 add.w r3, r3, #964 ; 0x3c4
  4764. 8002042: 2208 movs r2, #8
  4765. 8002044: 4619 mov r1, r3
  4766. 8002046: 6a38 ldr r0, [r7, #32]
  4767. 8002048: f004 ff8a bl 8006f60 <USB_ReadPacket>
  4768. ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
  4769. 800204c: 697b ldr r3, [r7, #20]
  4770. 800204e: 699a ldr r2, [r3, #24]
  4771. 8002050: 69bb ldr r3, [r7, #24]
  4772. 8002052: 091b lsrs r3, r3, #4
  4773. 8002054: f3c3 030a ubfx r3, r3, #0, #11
  4774. 8002058: 441a add r2, r3
  4775. 800205a: 697b ldr r3, [r7, #20]
  4776. 800205c: 619a str r2, [r3, #24]
  4777. else
  4778. {
  4779. /* ... */
  4780. }
  4781. USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
  4782. 800205e: 687b ldr r3, [r7, #4]
  4783. 8002060: 681b ldr r3, [r3, #0]
  4784. 8002062: 699a ldr r2, [r3, #24]
  4785. 8002064: 687b ldr r3, [r7, #4]
  4786. 8002066: 681b ldr r3, [r3, #0]
  4787. 8002068: f042 0210 orr.w r2, r2, #16
  4788. 800206c: 619a str r2, [r3, #24]
  4789. }
  4790. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
  4791. 800206e: 687b ldr r3, [r7, #4]
  4792. 8002070: 681b ldr r3, [r3, #0]
  4793. 8002072: 4618 mov r0, r3
  4794. 8002074: f005 f908 bl 8007288 <USB_ReadInterrupts>
  4795. 8002078: 4603 mov r3, r0
  4796. 800207a: f403 2300 and.w r3, r3, #524288 ; 0x80000
  4797. 800207e: f5b3 2f00 cmp.w r3, #524288 ; 0x80000
  4798. 8002082: d16e bne.n 8002162 <HAL_PCD_IRQHandler+0x226>
  4799. {
  4800. epnum = 0U;
  4801. 8002084: 2300 movs r3, #0
  4802. 8002086: 627b str r3, [r7, #36] ; 0x24
  4803. /* Read in the device interrupt bits */
  4804. ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
  4805. 8002088: 687b ldr r3, [r7, #4]
  4806. 800208a: 681b ldr r3, [r3, #0]
  4807. 800208c: 4618 mov r0, r3
  4808. 800208e: f005 f90e bl 80072ae <USB_ReadDevAllOutEpInterrupt>
  4809. 8002092: 62b8 str r0, [r7, #40] ; 0x28
  4810. while (ep_intr != 0U)
  4811. 8002094: e062 b.n 800215c <HAL_PCD_IRQHandler+0x220>
  4812. {
  4813. if ((ep_intr & 0x1U) != 0U)
  4814. 8002096: 6abb ldr r3, [r7, #40] ; 0x28
  4815. 8002098: f003 0301 and.w r3, r3, #1
  4816. 800209c: 2b00 cmp r3, #0
  4817. 800209e: d057 beq.n 8002150 <HAL_PCD_IRQHandler+0x214>
  4818. {
  4819. epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
  4820. 80020a0: 687b ldr r3, [r7, #4]
  4821. 80020a2: 681b ldr r3, [r3, #0]
  4822. 80020a4: 6a7a ldr r2, [r7, #36] ; 0x24
  4823. 80020a6: b2d2 uxtb r2, r2
  4824. 80020a8: 4611 mov r1, r2
  4825. 80020aa: 4618 mov r0, r3
  4826. 80020ac: f005 f933 bl 8007316 <USB_ReadDevOutEPInterrupt>
  4827. 80020b0: 6138 str r0, [r7, #16]
  4828. if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
  4829. 80020b2: 693b ldr r3, [r7, #16]
  4830. 80020b4: f003 0301 and.w r3, r3, #1
  4831. 80020b8: 2b00 cmp r3, #0
  4832. 80020ba: d00c beq.n 80020d6 <HAL_PCD_IRQHandler+0x19a>
  4833. {
  4834. CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
  4835. 80020bc: 6a7b ldr r3, [r7, #36] ; 0x24
  4836. 80020be: 015a lsls r2, r3, #5
  4837. 80020c0: 69fb ldr r3, [r7, #28]
  4838. 80020c2: 4413 add r3, r2
  4839. 80020c4: f503 6330 add.w r3, r3, #2816 ; 0xb00
  4840. 80020c8: 461a mov r2, r3
  4841. 80020ca: 2301 movs r3, #1
  4842. 80020cc: 6093 str r3, [r2, #8]
  4843. (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
  4844. 80020ce: 6a79 ldr r1, [r7, #36] ; 0x24
  4845. 80020d0: 6878 ldr r0, [r7, #4]
  4846. 80020d2: f000 fdd1 bl 8002c78 <PCD_EP_OutXfrComplete_int>
  4847. }
  4848. if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
  4849. 80020d6: 693b ldr r3, [r7, #16]
  4850. 80020d8: f003 0308 and.w r3, r3, #8
  4851. 80020dc: 2b00 cmp r3, #0
  4852. 80020de: d00c beq.n 80020fa <HAL_PCD_IRQHandler+0x1be>
  4853. {
  4854. CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
  4855. 80020e0: 6a7b ldr r3, [r7, #36] ; 0x24
  4856. 80020e2: 015a lsls r2, r3, #5
  4857. 80020e4: 69fb ldr r3, [r7, #28]
  4858. 80020e6: 4413 add r3, r2
  4859. 80020e8: f503 6330 add.w r3, r3, #2816 ; 0xb00
  4860. 80020ec: 461a mov r2, r3
  4861. 80020ee: 2308 movs r3, #8
  4862. 80020f0: 6093 str r3, [r2, #8]
  4863. /* Class B setup phase done for previous decoded setup */
  4864. (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
  4865. 80020f2: 6a79 ldr r1, [r7, #36] ; 0x24
  4866. 80020f4: 6878 ldr r0, [r7, #4]
  4867. 80020f6: f000 fecb bl 8002e90 <PCD_EP_OutSetupPacket_int>
  4868. }
  4869. if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
  4870. 80020fa: 693b ldr r3, [r7, #16]
  4871. 80020fc: f003 0310 and.w r3, r3, #16
  4872. 8002100: 2b00 cmp r3, #0
  4873. 8002102: d008 beq.n 8002116 <HAL_PCD_IRQHandler+0x1da>
  4874. {
  4875. CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
  4876. 8002104: 6a7b ldr r3, [r7, #36] ; 0x24
  4877. 8002106: 015a lsls r2, r3, #5
  4878. 8002108: 69fb ldr r3, [r7, #28]
  4879. 800210a: 4413 add r3, r2
  4880. 800210c: f503 6330 add.w r3, r3, #2816 ; 0xb00
  4881. 8002110: 461a mov r2, r3
  4882. 8002112: 2310 movs r3, #16
  4883. 8002114: 6093 str r3, [r2, #8]
  4884. }
  4885. /* Clear Status Phase Received interrupt */
  4886. if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
  4887. 8002116: 693b ldr r3, [r7, #16]
  4888. 8002118: f003 0320 and.w r3, r3, #32
  4889. 800211c: 2b00 cmp r3, #0
  4890. 800211e: d008 beq.n 8002132 <HAL_PCD_IRQHandler+0x1f6>
  4891. {
  4892. CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
  4893. 8002120: 6a7b ldr r3, [r7, #36] ; 0x24
  4894. 8002122: 015a lsls r2, r3, #5
  4895. 8002124: 69fb ldr r3, [r7, #28]
  4896. 8002126: 4413 add r3, r2
  4897. 8002128: f503 6330 add.w r3, r3, #2816 ; 0xb00
  4898. 800212c: 461a mov r2, r3
  4899. 800212e: 2320 movs r3, #32
  4900. 8002130: 6093 str r3, [r2, #8]
  4901. }
  4902. /* Clear OUT NAK interrupt */
  4903. if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
  4904. 8002132: 693b ldr r3, [r7, #16]
  4905. 8002134: f403 5300 and.w r3, r3, #8192 ; 0x2000
  4906. 8002138: 2b00 cmp r3, #0
  4907. 800213a: d009 beq.n 8002150 <HAL_PCD_IRQHandler+0x214>
  4908. {
  4909. CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
  4910. 800213c: 6a7b ldr r3, [r7, #36] ; 0x24
  4911. 800213e: 015a lsls r2, r3, #5
  4912. 8002140: 69fb ldr r3, [r7, #28]
  4913. 8002142: 4413 add r3, r2
  4914. 8002144: f503 6330 add.w r3, r3, #2816 ; 0xb00
  4915. 8002148: 461a mov r2, r3
  4916. 800214a: f44f 5300 mov.w r3, #8192 ; 0x2000
  4917. 800214e: 6093 str r3, [r2, #8]
  4918. }
  4919. }
  4920. epnum++;
  4921. 8002150: 6a7b ldr r3, [r7, #36] ; 0x24
  4922. 8002152: 3301 adds r3, #1
  4923. 8002154: 627b str r3, [r7, #36] ; 0x24
  4924. ep_intr >>= 1U;
  4925. 8002156: 6abb ldr r3, [r7, #40] ; 0x28
  4926. 8002158: 085b lsrs r3, r3, #1
  4927. 800215a: 62bb str r3, [r7, #40] ; 0x28
  4928. while (ep_intr != 0U)
  4929. 800215c: 6abb ldr r3, [r7, #40] ; 0x28
  4930. 800215e: 2b00 cmp r3, #0
  4931. 8002160: d199 bne.n 8002096 <HAL_PCD_IRQHandler+0x15a>
  4932. }
  4933. }
  4934. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
  4935. 8002162: 687b ldr r3, [r7, #4]
  4936. 8002164: 681b ldr r3, [r3, #0]
  4937. 8002166: 4618 mov r0, r3
  4938. 8002168: f005 f88e bl 8007288 <USB_ReadInterrupts>
  4939. 800216c: 4603 mov r3, r0
  4940. 800216e: f403 2380 and.w r3, r3, #262144 ; 0x40000
  4941. 8002172: f5b3 2f80 cmp.w r3, #262144 ; 0x40000
  4942. 8002176: f040 80c4 bne.w 8002302 <HAL_PCD_IRQHandler+0x3c6>
  4943. {
  4944. /* Read in the device interrupt bits */
  4945. ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
  4946. 800217a: 687b ldr r3, [r7, #4]
  4947. 800217c: 681b ldr r3, [r3, #0]
  4948. 800217e: 4618 mov r0, r3
  4949. 8002180: f005 f8af bl 80072e2 <USB_ReadDevAllInEpInterrupt>
  4950. 8002184: 62b8 str r0, [r7, #40] ; 0x28
  4951. epnum = 0U;
  4952. 8002186: 2300 movs r3, #0
  4953. 8002188: 627b str r3, [r7, #36] ; 0x24
  4954. while (ep_intr != 0U)
  4955. 800218a: e0b6 b.n 80022fa <HAL_PCD_IRQHandler+0x3be>
  4956. {
  4957. if ((ep_intr & 0x1U) != 0U) /* In ITR */
  4958. 800218c: 6abb ldr r3, [r7, #40] ; 0x28
  4959. 800218e: f003 0301 and.w r3, r3, #1
  4960. 8002192: 2b00 cmp r3, #0
  4961. 8002194: f000 80ab beq.w 80022ee <HAL_PCD_IRQHandler+0x3b2>
  4962. {
  4963. epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
  4964. 8002198: 687b ldr r3, [r7, #4]
  4965. 800219a: 681b ldr r3, [r3, #0]
  4966. 800219c: 6a7a ldr r2, [r7, #36] ; 0x24
  4967. 800219e: b2d2 uxtb r2, r2
  4968. 80021a0: 4611 mov r1, r2
  4969. 80021a2: 4618 mov r0, r3
  4970. 80021a4: f005 f8d5 bl 8007352 <USB_ReadDevInEPInterrupt>
  4971. 80021a8: 6138 str r0, [r7, #16]
  4972. if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
  4973. 80021aa: 693b ldr r3, [r7, #16]
  4974. 80021ac: f003 0301 and.w r3, r3, #1
  4975. 80021b0: 2b00 cmp r3, #0
  4976. 80021b2: d057 beq.n 8002264 <HAL_PCD_IRQHandler+0x328>
  4977. {
  4978. fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
  4979. 80021b4: 6a7b ldr r3, [r7, #36] ; 0x24
  4980. 80021b6: f003 030f and.w r3, r3, #15
  4981. 80021ba: 2201 movs r2, #1
  4982. 80021bc: fa02 f303 lsl.w r3, r2, r3
  4983. 80021c0: 60fb str r3, [r7, #12]
  4984. USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
  4985. 80021c2: 69fb ldr r3, [r7, #28]
  4986. 80021c4: f503 6300 add.w r3, r3, #2048 ; 0x800
  4987. 80021c8: 6b5a ldr r2, [r3, #52] ; 0x34
  4988. 80021ca: 68fb ldr r3, [r7, #12]
  4989. 80021cc: 43db mvns r3, r3
  4990. 80021ce: 69f9 ldr r1, [r7, #28]
  4991. 80021d0: f501 6100 add.w r1, r1, #2048 ; 0x800
  4992. 80021d4: 4013 ands r3, r2
  4993. 80021d6: 634b str r3, [r1, #52] ; 0x34
  4994. CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
  4995. 80021d8: 6a7b ldr r3, [r7, #36] ; 0x24
  4996. 80021da: 015a lsls r2, r3, #5
  4997. 80021dc: 69fb ldr r3, [r7, #28]
  4998. 80021de: 4413 add r3, r2
  4999. 80021e0: f503 6310 add.w r3, r3, #2304 ; 0x900
  5000. 80021e4: 461a mov r2, r3
  5001. 80021e6: 2301 movs r3, #1
  5002. 80021e8: 6093 str r3, [r2, #8]
  5003. if (hpcd->Init.dma_enable == 1U)
  5004. 80021ea: 687b ldr r3, [r7, #4]
  5005. 80021ec: 691b ldr r3, [r3, #16]
  5006. 80021ee: 2b01 cmp r3, #1
  5007. 80021f0: d132 bne.n 8002258 <HAL_PCD_IRQHandler+0x31c>
  5008. {
  5009. hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
  5010. 80021f2: 6879 ldr r1, [r7, #4]
  5011. 80021f4: 6a7a ldr r2, [r7, #36] ; 0x24
  5012. 80021f6: 4613 mov r3, r2
  5013. 80021f8: 00db lsls r3, r3, #3
  5014. 80021fa: 1a9b subs r3, r3, r2
  5015. 80021fc: 009b lsls r3, r3, #2
  5016. 80021fe: 440b add r3, r1
  5017. 8002200: 3348 adds r3, #72 ; 0x48
  5018. 8002202: 6819 ldr r1, [r3, #0]
  5019. 8002204: 6878 ldr r0, [r7, #4]
  5020. 8002206: 6a7a ldr r2, [r7, #36] ; 0x24
  5021. 8002208: 4613 mov r3, r2
  5022. 800220a: 00db lsls r3, r3, #3
  5023. 800220c: 1a9b subs r3, r3, r2
  5024. 800220e: 009b lsls r3, r3, #2
  5025. 8002210: 4403 add r3, r0
  5026. 8002212: 3344 adds r3, #68 ; 0x44
  5027. 8002214: 681b ldr r3, [r3, #0]
  5028. 8002216: 4419 add r1, r3
  5029. 8002218: 6878 ldr r0, [r7, #4]
  5030. 800221a: 6a7a ldr r2, [r7, #36] ; 0x24
  5031. 800221c: 4613 mov r3, r2
  5032. 800221e: 00db lsls r3, r3, #3
  5033. 8002220: 1a9b subs r3, r3, r2
  5034. 8002222: 009b lsls r3, r3, #2
  5035. 8002224: 4403 add r3, r0
  5036. 8002226: 3348 adds r3, #72 ; 0x48
  5037. 8002228: 6019 str r1, [r3, #0]
  5038. /* this is ZLP, so prepare EP0 for next setup */
  5039. if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
  5040. 800222a: 6a7b ldr r3, [r7, #36] ; 0x24
  5041. 800222c: 2b00 cmp r3, #0
  5042. 800222e: d113 bne.n 8002258 <HAL_PCD_IRQHandler+0x31c>
  5043. 8002230: 6879 ldr r1, [r7, #4]
  5044. 8002232: 6a7a ldr r2, [r7, #36] ; 0x24
  5045. 8002234: 4613 mov r3, r2
  5046. 8002236: 00db lsls r3, r3, #3
  5047. 8002238: 1a9b subs r3, r3, r2
  5048. 800223a: 009b lsls r3, r3, #2
  5049. 800223c: 440b add r3, r1
  5050. 800223e: 3350 adds r3, #80 ; 0x50
  5051. 8002240: 681b ldr r3, [r3, #0]
  5052. 8002242: 2b00 cmp r3, #0
  5053. 8002244: d108 bne.n 8002258 <HAL_PCD_IRQHandler+0x31c>
  5054. {
  5055. /* prepare to rx more setup packets */
  5056. (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
  5057. 8002246: 687b ldr r3, [r7, #4]
  5058. 8002248: 6818 ldr r0, [r3, #0]
  5059. 800224a: 687b ldr r3, [r7, #4]
  5060. 800224c: f503 7371 add.w r3, r3, #964 ; 0x3c4
  5061. 8002250: 461a mov r2, r3
  5062. 8002252: 2101 movs r1, #1
  5063. 8002254: f005 f8de bl 8007414 <USB_EP0_OutStart>
  5064. }
  5065. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5066. hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
  5067. #else
  5068. HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
  5069. 8002258: 6a7b ldr r3, [r7, #36] ; 0x24
  5070. 800225a: b2db uxtb r3, r3
  5071. 800225c: 4619 mov r1, r3
  5072. 800225e: 6878 ldr r0, [r7, #4]
  5073. 8002260: f007 f89f bl 80093a2 <HAL_PCD_DataInStageCallback>
  5074. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  5075. }
  5076. if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
  5077. 8002264: 693b ldr r3, [r7, #16]
  5078. 8002266: f003 0308 and.w r3, r3, #8
  5079. 800226a: 2b00 cmp r3, #0
  5080. 800226c: d008 beq.n 8002280 <HAL_PCD_IRQHandler+0x344>
  5081. {
  5082. CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
  5083. 800226e: 6a7b ldr r3, [r7, #36] ; 0x24
  5084. 8002270: 015a lsls r2, r3, #5
  5085. 8002272: 69fb ldr r3, [r7, #28]
  5086. 8002274: 4413 add r3, r2
  5087. 8002276: f503 6310 add.w r3, r3, #2304 ; 0x900
  5088. 800227a: 461a mov r2, r3
  5089. 800227c: 2308 movs r3, #8
  5090. 800227e: 6093 str r3, [r2, #8]
  5091. }
  5092. if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
  5093. 8002280: 693b ldr r3, [r7, #16]
  5094. 8002282: f003 0310 and.w r3, r3, #16
  5095. 8002286: 2b00 cmp r3, #0
  5096. 8002288: d008 beq.n 800229c <HAL_PCD_IRQHandler+0x360>
  5097. {
  5098. CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
  5099. 800228a: 6a7b ldr r3, [r7, #36] ; 0x24
  5100. 800228c: 015a lsls r2, r3, #5
  5101. 800228e: 69fb ldr r3, [r7, #28]
  5102. 8002290: 4413 add r3, r2
  5103. 8002292: f503 6310 add.w r3, r3, #2304 ; 0x900
  5104. 8002296: 461a mov r2, r3
  5105. 8002298: 2310 movs r3, #16
  5106. 800229a: 6093 str r3, [r2, #8]
  5107. }
  5108. if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
  5109. 800229c: 693b ldr r3, [r7, #16]
  5110. 800229e: f003 0340 and.w r3, r3, #64 ; 0x40
  5111. 80022a2: 2b00 cmp r3, #0
  5112. 80022a4: d008 beq.n 80022b8 <HAL_PCD_IRQHandler+0x37c>
  5113. {
  5114. CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
  5115. 80022a6: 6a7b ldr r3, [r7, #36] ; 0x24
  5116. 80022a8: 015a lsls r2, r3, #5
  5117. 80022aa: 69fb ldr r3, [r7, #28]
  5118. 80022ac: 4413 add r3, r2
  5119. 80022ae: f503 6310 add.w r3, r3, #2304 ; 0x900
  5120. 80022b2: 461a mov r2, r3
  5121. 80022b4: 2340 movs r3, #64 ; 0x40
  5122. 80022b6: 6093 str r3, [r2, #8]
  5123. }
  5124. if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
  5125. 80022b8: 693b ldr r3, [r7, #16]
  5126. 80022ba: f003 0302 and.w r3, r3, #2
  5127. 80022be: 2b00 cmp r3, #0
  5128. 80022c0: d00c beq.n 80022dc <HAL_PCD_IRQHandler+0x3a0>
  5129. {
  5130. (void)USB_FlushTxFifo(USBx, epnum);
  5131. 80022c2: 6a79 ldr r1, [r7, #36] ; 0x24
  5132. 80022c4: 6a38 ldr r0, [r7, #32]
  5133. 80022c6: f004 f867 bl 8006398 <USB_FlushTxFifo>
  5134. CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
  5135. 80022ca: 6a7b ldr r3, [r7, #36] ; 0x24
  5136. 80022cc: 015a lsls r2, r3, #5
  5137. 80022ce: 69fb ldr r3, [r7, #28]
  5138. 80022d0: 4413 add r3, r2
  5139. 80022d2: f503 6310 add.w r3, r3, #2304 ; 0x900
  5140. 80022d6: 461a mov r2, r3
  5141. 80022d8: 2302 movs r3, #2
  5142. 80022da: 6093 str r3, [r2, #8]
  5143. }
  5144. if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
  5145. 80022dc: 693b ldr r3, [r7, #16]
  5146. 80022de: f003 0380 and.w r3, r3, #128 ; 0x80
  5147. 80022e2: 2b00 cmp r3, #0
  5148. 80022e4: d003 beq.n 80022ee <HAL_PCD_IRQHandler+0x3b2>
  5149. {
  5150. (void)PCD_WriteEmptyTxFifo(hpcd, epnum);
  5151. 80022e6: 6a79 ldr r1, [r7, #36] ; 0x24
  5152. 80022e8: 6878 ldr r0, [r7, #4]
  5153. 80022ea: f000 fc38 bl 8002b5e <PCD_WriteEmptyTxFifo>
  5154. }
  5155. }
  5156. epnum++;
  5157. 80022ee: 6a7b ldr r3, [r7, #36] ; 0x24
  5158. 80022f0: 3301 adds r3, #1
  5159. 80022f2: 627b str r3, [r7, #36] ; 0x24
  5160. ep_intr >>= 1U;
  5161. 80022f4: 6abb ldr r3, [r7, #40] ; 0x28
  5162. 80022f6: 085b lsrs r3, r3, #1
  5163. 80022f8: 62bb str r3, [r7, #40] ; 0x28
  5164. while (ep_intr != 0U)
  5165. 80022fa: 6abb ldr r3, [r7, #40] ; 0x28
  5166. 80022fc: 2b00 cmp r3, #0
  5167. 80022fe: f47f af45 bne.w 800218c <HAL_PCD_IRQHandler+0x250>
  5168. }
  5169. }
  5170. /* Handle Resume Interrupt */
  5171. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
  5172. 8002302: 687b ldr r3, [r7, #4]
  5173. 8002304: 681b ldr r3, [r3, #0]
  5174. 8002306: 4618 mov r0, r3
  5175. 8002308: f004 ffbe bl 8007288 <USB_ReadInterrupts>
  5176. 800230c: 4603 mov r3, r0
  5177. 800230e: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000
  5178. 8002312: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
  5179. 8002316: d122 bne.n 800235e <HAL_PCD_IRQHandler+0x422>
  5180. {
  5181. /* Clear the Remote Wake-up Signaling */
  5182. USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
  5183. 8002318: 69fb ldr r3, [r7, #28]
  5184. 800231a: f503 6300 add.w r3, r3, #2048 ; 0x800
  5185. 800231e: 685b ldr r3, [r3, #4]
  5186. 8002320: 69fa ldr r2, [r7, #28]
  5187. 8002322: f502 6200 add.w r2, r2, #2048 ; 0x800
  5188. 8002326: f023 0301 bic.w r3, r3, #1
  5189. 800232a: 6053 str r3, [r2, #4]
  5190. if (hpcd->LPM_State == LPM_L1)
  5191. 800232c: 687b ldr r3, [r7, #4]
  5192. 800232e: f893 33f4 ldrb.w r3, [r3, #1012] ; 0x3f4
  5193. 8002332: 2b01 cmp r3, #1
  5194. 8002334: d108 bne.n 8002348 <HAL_PCD_IRQHandler+0x40c>
  5195. {
  5196. hpcd->LPM_State = LPM_L0;
  5197. 8002336: 687b ldr r3, [r7, #4]
  5198. 8002338: 2200 movs r2, #0
  5199. 800233a: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4
  5200. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5201. hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
  5202. #else
  5203. HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
  5204. 800233e: 2100 movs r1, #0
  5205. 8002340: 6878 ldr r0, [r7, #4]
  5206. 8002342: f000 fe67 bl 8003014 <HAL_PCDEx_LPM_Callback>
  5207. 8002346: e002 b.n 800234e <HAL_PCD_IRQHandler+0x412>
  5208. else
  5209. {
  5210. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5211. hpcd->ResumeCallback(hpcd);
  5212. #else
  5213. HAL_PCD_ResumeCallback(hpcd);
  5214. 8002348: 6878 ldr r0, [r7, #4]
  5215. 800234a: f007 f8a1 bl 8009490 <HAL_PCD_ResumeCallback>
  5216. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  5217. }
  5218. __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
  5219. 800234e: 687b ldr r3, [r7, #4]
  5220. 8002350: 681b ldr r3, [r3, #0]
  5221. 8002352: 695a ldr r2, [r3, #20]
  5222. 8002354: 687b ldr r3, [r7, #4]
  5223. 8002356: 681b ldr r3, [r3, #0]
  5224. 8002358: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
  5225. 800235c: 615a str r2, [r3, #20]
  5226. }
  5227. /* Handle Suspend Interrupt */
  5228. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
  5229. 800235e: 687b ldr r3, [r7, #4]
  5230. 8002360: 681b ldr r3, [r3, #0]
  5231. 8002362: 4618 mov r0, r3
  5232. 8002364: f004 ff90 bl 8007288 <USB_ReadInterrupts>
  5233. 8002368: 4603 mov r3, r0
  5234. 800236a: f403 6300 and.w r3, r3, #2048 ; 0x800
  5235. 800236e: f5b3 6f00 cmp.w r3, #2048 ; 0x800
  5236. 8002372: d112 bne.n 800239a <HAL_PCD_IRQHandler+0x45e>
  5237. {
  5238. if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
  5239. 8002374: 69fb ldr r3, [r7, #28]
  5240. 8002376: f503 6300 add.w r3, r3, #2048 ; 0x800
  5241. 800237a: 689b ldr r3, [r3, #8]
  5242. 800237c: f003 0301 and.w r3, r3, #1
  5243. 8002380: 2b01 cmp r3, #1
  5244. 8002382: d102 bne.n 800238a <HAL_PCD_IRQHandler+0x44e>
  5245. {
  5246. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5247. hpcd->SuspendCallback(hpcd);
  5248. #else
  5249. HAL_PCD_SuspendCallback(hpcd);
  5250. 8002384: 6878 ldr r0, [r7, #4]
  5251. 8002386: f007 f85d bl 8009444 <HAL_PCD_SuspendCallback>
  5252. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  5253. }
  5254. __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
  5255. 800238a: 687b ldr r3, [r7, #4]
  5256. 800238c: 681b ldr r3, [r3, #0]
  5257. 800238e: 695a ldr r2, [r3, #20]
  5258. 8002390: 687b ldr r3, [r7, #4]
  5259. 8002392: 681b ldr r3, [r3, #0]
  5260. 8002394: f402 6200 and.w r2, r2, #2048 ; 0x800
  5261. 8002398: 615a str r2, [r3, #20]
  5262. }
  5263. /* Handle LPM Interrupt */
  5264. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
  5265. 800239a: 687b ldr r3, [r7, #4]
  5266. 800239c: 681b ldr r3, [r3, #0]
  5267. 800239e: 4618 mov r0, r3
  5268. 80023a0: f004 ff72 bl 8007288 <USB_ReadInterrupts>
  5269. 80023a4: 4603 mov r3, r0
  5270. 80023a6: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
  5271. 80023aa: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
  5272. 80023ae: d121 bne.n 80023f4 <HAL_PCD_IRQHandler+0x4b8>
  5273. {
  5274. __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
  5275. 80023b0: 687b ldr r3, [r7, #4]
  5276. 80023b2: 681b ldr r3, [r3, #0]
  5277. 80023b4: 695a ldr r2, [r3, #20]
  5278. 80023b6: 687b ldr r3, [r7, #4]
  5279. 80023b8: 681b ldr r3, [r3, #0]
  5280. 80023ba: f002 6200 and.w r2, r2, #134217728 ; 0x8000000
  5281. 80023be: 615a str r2, [r3, #20]
  5282. if (hpcd->LPM_State == LPM_L0)
  5283. 80023c0: 687b ldr r3, [r7, #4]
  5284. 80023c2: f893 33f4 ldrb.w r3, [r3, #1012] ; 0x3f4
  5285. 80023c6: 2b00 cmp r3, #0
  5286. 80023c8: d111 bne.n 80023ee <HAL_PCD_IRQHandler+0x4b2>
  5287. {
  5288. hpcd->LPM_State = LPM_L1;
  5289. 80023ca: 687b ldr r3, [r7, #4]
  5290. 80023cc: 2201 movs r2, #1
  5291. 80023ce: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4
  5292. hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
  5293. 80023d2: 687b ldr r3, [r7, #4]
  5294. 80023d4: 681b ldr r3, [r3, #0]
  5295. 80023d6: 6d5b ldr r3, [r3, #84] ; 0x54
  5296. 80023d8: 089b lsrs r3, r3, #2
  5297. 80023da: f003 020f and.w r2, r3, #15
  5298. 80023de: 687b ldr r3, [r7, #4]
  5299. 80023e0: f8c3 23f8 str.w r2, [r3, #1016] ; 0x3f8
  5300. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5301. hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
  5302. #else
  5303. HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
  5304. 80023e4: 2101 movs r1, #1
  5305. 80023e6: 6878 ldr r0, [r7, #4]
  5306. 80023e8: f000 fe14 bl 8003014 <HAL_PCDEx_LPM_Callback>
  5307. 80023ec: e002 b.n 80023f4 <HAL_PCD_IRQHandler+0x4b8>
  5308. else
  5309. {
  5310. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5311. hpcd->SuspendCallback(hpcd);
  5312. #else
  5313. HAL_PCD_SuspendCallback(hpcd);
  5314. 80023ee: 6878 ldr r0, [r7, #4]
  5315. 80023f0: f007 f828 bl 8009444 <HAL_PCD_SuspendCallback>
  5316. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  5317. }
  5318. }
  5319. /* Handle Reset Interrupt */
  5320. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
  5321. 80023f4: 687b ldr r3, [r7, #4]
  5322. 80023f6: 681b ldr r3, [r3, #0]
  5323. 80023f8: 4618 mov r0, r3
  5324. 80023fa: f004 ff45 bl 8007288 <USB_ReadInterrupts>
  5325. 80023fe: 4603 mov r3, r0
  5326. 8002400: f403 5380 and.w r3, r3, #4096 ; 0x1000
  5327. 8002404: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  5328. 8002408: f040 80b7 bne.w 800257a <HAL_PCD_IRQHandler+0x63e>
  5329. {
  5330. USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
  5331. 800240c: 69fb ldr r3, [r7, #28]
  5332. 800240e: f503 6300 add.w r3, r3, #2048 ; 0x800
  5333. 8002412: 685b ldr r3, [r3, #4]
  5334. 8002414: 69fa ldr r2, [r7, #28]
  5335. 8002416: f502 6200 add.w r2, r2, #2048 ; 0x800
  5336. 800241a: f023 0301 bic.w r3, r3, #1
  5337. 800241e: 6053 str r3, [r2, #4]
  5338. (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
  5339. 8002420: 687b ldr r3, [r7, #4]
  5340. 8002422: 681b ldr r3, [r3, #0]
  5341. 8002424: 2110 movs r1, #16
  5342. 8002426: 4618 mov r0, r3
  5343. 8002428: f003 ffb6 bl 8006398 <USB_FlushTxFifo>
  5344. for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
  5345. 800242c: 2300 movs r3, #0
  5346. 800242e: 62fb str r3, [r7, #44] ; 0x2c
  5347. 8002430: e046 b.n 80024c0 <HAL_PCD_IRQHandler+0x584>
  5348. {
  5349. USBx_INEP(i)->DIEPINT = 0xFB7FU;
  5350. 8002432: 6afb ldr r3, [r7, #44] ; 0x2c
  5351. 8002434: 015a lsls r2, r3, #5
  5352. 8002436: 69fb ldr r3, [r7, #28]
  5353. 8002438: 4413 add r3, r2
  5354. 800243a: f503 6310 add.w r3, r3, #2304 ; 0x900
  5355. 800243e: 461a mov r2, r3
  5356. 8002440: f64f 337f movw r3, #64383 ; 0xfb7f
  5357. 8002444: 6093 str r3, [r2, #8]
  5358. USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
  5359. 8002446: 6afb ldr r3, [r7, #44] ; 0x2c
  5360. 8002448: 015a lsls r2, r3, #5
  5361. 800244a: 69fb ldr r3, [r7, #28]
  5362. 800244c: 4413 add r3, r2
  5363. 800244e: f503 6310 add.w r3, r3, #2304 ; 0x900
  5364. 8002452: 681b ldr r3, [r3, #0]
  5365. 8002454: 6afa ldr r2, [r7, #44] ; 0x2c
  5366. 8002456: 0151 lsls r1, r2, #5
  5367. 8002458: 69fa ldr r2, [r7, #28]
  5368. 800245a: 440a add r2, r1
  5369. 800245c: f502 6210 add.w r2, r2, #2304 ; 0x900
  5370. 8002460: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
  5371. 8002464: 6013 str r3, [r2, #0]
  5372. USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
  5373. 8002466: 6afb ldr r3, [r7, #44] ; 0x2c
  5374. 8002468: 015a lsls r2, r3, #5
  5375. 800246a: 69fb ldr r3, [r7, #28]
  5376. 800246c: 4413 add r3, r2
  5377. 800246e: f503 6330 add.w r3, r3, #2816 ; 0xb00
  5378. 8002472: 461a mov r2, r3
  5379. 8002474: f64f 337f movw r3, #64383 ; 0xfb7f
  5380. 8002478: 6093 str r3, [r2, #8]
  5381. USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
  5382. 800247a: 6afb ldr r3, [r7, #44] ; 0x2c
  5383. 800247c: 015a lsls r2, r3, #5
  5384. 800247e: 69fb ldr r3, [r7, #28]
  5385. 8002480: 4413 add r3, r2
  5386. 8002482: f503 6330 add.w r3, r3, #2816 ; 0xb00
  5387. 8002486: 681b ldr r3, [r3, #0]
  5388. 8002488: 6afa ldr r2, [r7, #44] ; 0x2c
  5389. 800248a: 0151 lsls r1, r2, #5
  5390. 800248c: 69fa ldr r2, [r7, #28]
  5391. 800248e: 440a add r2, r1
  5392. 8002490: f502 6230 add.w r2, r2, #2816 ; 0xb00
  5393. 8002494: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
  5394. 8002498: 6013 str r3, [r2, #0]
  5395. USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
  5396. 800249a: 6afb ldr r3, [r7, #44] ; 0x2c
  5397. 800249c: 015a lsls r2, r3, #5
  5398. 800249e: 69fb ldr r3, [r7, #28]
  5399. 80024a0: 4413 add r3, r2
  5400. 80024a2: f503 6330 add.w r3, r3, #2816 ; 0xb00
  5401. 80024a6: 681b ldr r3, [r3, #0]
  5402. 80024a8: 6afa ldr r2, [r7, #44] ; 0x2c
  5403. 80024aa: 0151 lsls r1, r2, #5
  5404. 80024ac: 69fa ldr r2, [r7, #28]
  5405. 80024ae: 440a add r2, r1
  5406. 80024b0: f502 6230 add.w r2, r2, #2816 ; 0xb00
  5407. 80024b4: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000
  5408. 80024b8: 6013 str r3, [r2, #0]
  5409. for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
  5410. 80024ba: 6afb ldr r3, [r7, #44] ; 0x2c
  5411. 80024bc: 3301 adds r3, #1
  5412. 80024be: 62fb str r3, [r7, #44] ; 0x2c
  5413. 80024c0: 687b ldr r3, [r7, #4]
  5414. 80024c2: 685b ldr r3, [r3, #4]
  5415. 80024c4: 6afa ldr r2, [r7, #44] ; 0x2c
  5416. 80024c6: 429a cmp r2, r3
  5417. 80024c8: d3b3 bcc.n 8002432 <HAL_PCD_IRQHandler+0x4f6>
  5418. }
  5419. USBx_DEVICE->DAINTMSK |= 0x10001U;
  5420. 80024ca: 69fb ldr r3, [r7, #28]
  5421. 80024cc: f503 6300 add.w r3, r3, #2048 ; 0x800
  5422. 80024d0: 69db ldr r3, [r3, #28]
  5423. 80024d2: 69fa ldr r2, [r7, #28]
  5424. 80024d4: f502 6200 add.w r2, r2, #2048 ; 0x800
  5425. 80024d8: f043 1301 orr.w r3, r3, #65537 ; 0x10001
  5426. 80024dc: 61d3 str r3, [r2, #28]
  5427. if (hpcd->Init.use_dedicated_ep1 != 0U)
  5428. 80024de: 687b ldr r3, [r7, #4]
  5429. 80024e0: 6b1b ldr r3, [r3, #48] ; 0x30
  5430. 80024e2: 2b00 cmp r3, #0
  5431. 80024e4: d016 beq.n 8002514 <HAL_PCD_IRQHandler+0x5d8>
  5432. {
  5433. USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
  5434. 80024e6: 69fb ldr r3, [r7, #28]
  5435. 80024e8: f503 6300 add.w r3, r3, #2048 ; 0x800
  5436. 80024ec: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
  5437. 80024f0: 69fa ldr r2, [r7, #28]
  5438. 80024f2: f502 6200 add.w r2, r2, #2048 ; 0x800
  5439. 80024f6: f043 030b orr.w r3, r3, #11
  5440. 80024fa: f8c2 3084 str.w r3, [r2, #132] ; 0x84
  5441. USB_OTG_DOEPMSK_XFRCM |
  5442. USB_OTG_DOEPMSK_EPDM;
  5443. USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
  5444. 80024fe: 69fb ldr r3, [r7, #28]
  5445. 8002500: f503 6300 add.w r3, r3, #2048 ; 0x800
  5446. 8002504: 6c5b ldr r3, [r3, #68] ; 0x44
  5447. 8002506: 69fa ldr r2, [r7, #28]
  5448. 8002508: f502 6200 add.w r2, r2, #2048 ; 0x800
  5449. 800250c: f043 030b orr.w r3, r3, #11
  5450. 8002510: 6453 str r3, [r2, #68] ; 0x44
  5451. 8002512: e015 b.n 8002540 <HAL_PCD_IRQHandler+0x604>
  5452. USB_OTG_DIEPMSK_XFRCM |
  5453. USB_OTG_DIEPMSK_EPDM;
  5454. }
  5455. else
  5456. {
  5457. USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
  5458. 8002514: 69fb ldr r3, [r7, #28]
  5459. 8002516: f503 6300 add.w r3, r3, #2048 ; 0x800
  5460. 800251a: 695a ldr r2, [r3, #20]
  5461. 800251c: 69fb ldr r3, [r7, #28]
  5462. 800251e: f503 6300 add.w r3, r3, #2048 ; 0x800
  5463. 8002522: 4619 mov r1, r3
  5464. 8002524: f242 032b movw r3, #8235 ; 0x202b
  5465. 8002528: 4313 orrs r3, r2
  5466. 800252a: 614b str r3, [r1, #20]
  5467. USB_OTG_DOEPMSK_XFRCM |
  5468. USB_OTG_DOEPMSK_EPDM |
  5469. USB_OTG_DOEPMSK_OTEPSPRM |
  5470. USB_OTG_DOEPMSK_NAKM;
  5471. USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
  5472. 800252c: 69fb ldr r3, [r7, #28]
  5473. 800252e: f503 6300 add.w r3, r3, #2048 ; 0x800
  5474. 8002532: 691b ldr r3, [r3, #16]
  5475. 8002534: 69fa ldr r2, [r7, #28]
  5476. 8002536: f502 6200 add.w r2, r2, #2048 ; 0x800
  5477. 800253a: f043 030b orr.w r3, r3, #11
  5478. 800253e: 6113 str r3, [r2, #16]
  5479. USB_OTG_DIEPMSK_XFRCM |
  5480. USB_OTG_DIEPMSK_EPDM;
  5481. }
  5482. /* Set Default Address to 0 */
  5483. USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
  5484. 8002540: 69fb ldr r3, [r7, #28]
  5485. 8002542: f503 6300 add.w r3, r3, #2048 ; 0x800
  5486. 8002546: 681b ldr r3, [r3, #0]
  5487. 8002548: 69fa ldr r2, [r7, #28]
  5488. 800254a: f502 6200 add.w r2, r2, #2048 ; 0x800
  5489. 800254e: f423 63fe bic.w r3, r3, #2032 ; 0x7f0
  5490. 8002552: 6013 str r3, [r2, #0]
  5491. /* setup EP0 to receive SETUP packets */
  5492. (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
  5493. 8002554: 687b ldr r3, [r7, #4]
  5494. 8002556: 6818 ldr r0, [r3, #0]
  5495. 8002558: 687b ldr r3, [r7, #4]
  5496. 800255a: 691b ldr r3, [r3, #16]
  5497. 800255c: b2d9 uxtb r1, r3
  5498. (uint8_t *)hpcd->Setup);
  5499. 800255e: 687b ldr r3, [r7, #4]
  5500. 8002560: f503 7371 add.w r3, r3, #964 ; 0x3c4
  5501. (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
  5502. 8002564: 461a mov r2, r3
  5503. 8002566: f004 ff55 bl 8007414 <USB_EP0_OutStart>
  5504. __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
  5505. 800256a: 687b ldr r3, [r7, #4]
  5506. 800256c: 681b ldr r3, [r3, #0]
  5507. 800256e: 695a ldr r2, [r3, #20]
  5508. 8002570: 687b ldr r3, [r7, #4]
  5509. 8002572: 681b ldr r3, [r3, #0]
  5510. 8002574: f402 5280 and.w r2, r2, #4096 ; 0x1000
  5511. 8002578: 615a str r2, [r3, #20]
  5512. }
  5513. /* Handle Enumeration done Interrupt */
  5514. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
  5515. 800257a: 687b ldr r3, [r7, #4]
  5516. 800257c: 681b ldr r3, [r3, #0]
  5517. 800257e: 4618 mov r0, r3
  5518. 8002580: f004 fe82 bl 8007288 <USB_ReadInterrupts>
  5519. 8002584: 4603 mov r3, r0
  5520. 8002586: f403 5300 and.w r3, r3, #8192 ; 0x2000
  5521. 800258a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
  5522. 800258e: d124 bne.n 80025da <HAL_PCD_IRQHandler+0x69e>
  5523. {
  5524. (void)USB_ActivateSetup(hpcd->Instance);
  5525. 8002590: 687b ldr r3, [r7, #4]
  5526. 8002592: 681b ldr r3, [r3, #0]
  5527. 8002594: 4618 mov r0, r3
  5528. 8002596: f004 ff19 bl 80073cc <USB_ActivateSetup>
  5529. hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
  5530. 800259a: 687b ldr r3, [r7, #4]
  5531. 800259c: 681b ldr r3, [r3, #0]
  5532. 800259e: 4618 mov r0, r3
  5533. 80025a0: f003 ff73 bl 800648a <USB_GetDevSpeed>
  5534. 80025a4: 4603 mov r3, r0
  5535. 80025a6: 461a mov r2, r3
  5536. 80025a8: 687b ldr r3, [r7, #4]
  5537. 80025aa: 60da str r2, [r3, #12]
  5538. /* Set USB Turnaround time */
  5539. (void)USB_SetTurnaroundTime(hpcd->Instance,
  5540. 80025ac: 687b ldr r3, [r7, #4]
  5541. 80025ae: 681c ldr r4, [r3, #0]
  5542. 80025b0: f001 fc62 bl 8003e78 <HAL_RCC_GetHCLKFreq>
  5543. 80025b4: 4601 mov r1, r0
  5544. HAL_RCC_GetHCLKFreq(),
  5545. (uint8_t)hpcd->Init.speed);
  5546. 80025b6: 687b ldr r3, [r7, #4]
  5547. 80025b8: 68db ldr r3, [r3, #12]
  5548. (void)USB_SetTurnaroundTime(hpcd->Instance,
  5549. 80025ba: b2db uxtb r3, r3
  5550. 80025bc: 461a mov r2, r3
  5551. 80025be: 4620 mov r0, r4
  5552. 80025c0: f003 fc7c bl 8005ebc <USB_SetTurnaroundTime>
  5553. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5554. hpcd->ResetCallback(hpcd);
  5555. #else
  5556. HAL_PCD_ResetCallback(hpcd);
  5557. 80025c4: 6878 ldr r0, [r7, #4]
  5558. 80025c6: f006 ff14 bl 80093f2 <HAL_PCD_ResetCallback>
  5559. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  5560. __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
  5561. 80025ca: 687b ldr r3, [r7, #4]
  5562. 80025cc: 681b ldr r3, [r3, #0]
  5563. 80025ce: 695a ldr r2, [r3, #20]
  5564. 80025d0: 687b ldr r3, [r7, #4]
  5565. 80025d2: 681b ldr r3, [r3, #0]
  5566. 80025d4: f402 5200 and.w r2, r2, #8192 ; 0x2000
  5567. 80025d8: 615a str r2, [r3, #20]
  5568. }
  5569. /* Handle SOF Interrupt */
  5570. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
  5571. 80025da: 687b ldr r3, [r7, #4]
  5572. 80025dc: 681b ldr r3, [r3, #0]
  5573. 80025de: 4618 mov r0, r3
  5574. 80025e0: f004 fe52 bl 8007288 <USB_ReadInterrupts>
  5575. 80025e4: 4603 mov r3, r0
  5576. 80025e6: f003 0308 and.w r3, r3, #8
  5577. 80025ea: 2b08 cmp r3, #8
  5578. 80025ec: d10a bne.n 8002604 <HAL_PCD_IRQHandler+0x6c8>
  5579. {
  5580. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5581. hpcd->SOFCallback(hpcd);
  5582. #else
  5583. HAL_PCD_SOFCallback(hpcd);
  5584. 80025ee: 6878 ldr r0, [r7, #4]
  5585. 80025f0: f006 fef1 bl 80093d6 <HAL_PCD_SOFCallback>
  5586. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  5587. __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
  5588. 80025f4: 687b ldr r3, [r7, #4]
  5589. 80025f6: 681b ldr r3, [r3, #0]
  5590. 80025f8: 695a ldr r2, [r3, #20]
  5591. 80025fa: 687b ldr r3, [r7, #4]
  5592. 80025fc: 681b ldr r3, [r3, #0]
  5593. 80025fe: f002 0208 and.w r2, r2, #8
  5594. 8002602: 615a str r2, [r3, #20]
  5595. }
  5596. /* Handle Incomplete ISO IN Interrupt */
  5597. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
  5598. 8002604: 687b ldr r3, [r7, #4]
  5599. 8002606: 681b ldr r3, [r3, #0]
  5600. 8002608: 4618 mov r0, r3
  5601. 800260a: f004 fe3d bl 8007288 <USB_ReadInterrupts>
  5602. 800260e: 4603 mov r3, r0
  5603. 8002610: f403 1380 and.w r3, r3, #1048576 ; 0x100000
  5604. 8002614: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
  5605. 8002618: d10f bne.n 800263a <HAL_PCD_IRQHandler+0x6fe>
  5606. {
  5607. /* Keep application checking the corresponding Iso IN endpoint
  5608. causing the incomplete Interrupt */
  5609. epnum = 0U;
  5610. 800261a: 2300 movs r3, #0
  5611. 800261c: 627b str r3, [r7, #36] ; 0x24
  5612. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5613. hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
  5614. #else
  5615. HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
  5616. 800261e: 6a7b ldr r3, [r7, #36] ; 0x24
  5617. 8002620: b2db uxtb r3, r3
  5618. 8002622: 4619 mov r1, r3
  5619. 8002624: 6878 ldr r0, [r7, #4]
  5620. 8002626: f006 ff53 bl 80094d0 <HAL_PCD_ISOINIncompleteCallback>
  5621. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  5622. __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
  5623. 800262a: 687b ldr r3, [r7, #4]
  5624. 800262c: 681b ldr r3, [r3, #0]
  5625. 800262e: 695a ldr r2, [r3, #20]
  5626. 8002630: 687b ldr r3, [r7, #4]
  5627. 8002632: 681b ldr r3, [r3, #0]
  5628. 8002634: f402 1280 and.w r2, r2, #1048576 ; 0x100000
  5629. 8002638: 615a str r2, [r3, #20]
  5630. }
  5631. /* Handle Incomplete ISO OUT Interrupt */
  5632. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
  5633. 800263a: 687b ldr r3, [r7, #4]
  5634. 800263c: 681b ldr r3, [r3, #0]
  5635. 800263e: 4618 mov r0, r3
  5636. 8002640: f004 fe22 bl 8007288 <USB_ReadInterrupts>
  5637. 8002644: 4603 mov r3, r0
  5638. 8002646: f403 1300 and.w r3, r3, #2097152 ; 0x200000
  5639. 800264a: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000
  5640. 800264e: d10f bne.n 8002670 <HAL_PCD_IRQHandler+0x734>
  5641. {
  5642. /* Keep application checking the corresponding Iso OUT endpoint
  5643. causing the incomplete Interrupt */
  5644. epnum = 0U;
  5645. 8002650: 2300 movs r3, #0
  5646. 8002652: 627b str r3, [r7, #36] ; 0x24
  5647. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5648. hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
  5649. #else
  5650. HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
  5651. 8002654: 6a7b ldr r3, [r7, #36] ; 0x24
  5652. 8002656: b2db uxtb r3, r3
  5653. 8002658: 4619 mov r1, r3
  5654. 800265a: 6878 ldr r0, [r7, #4]
  5655. 800265c: f006 ff26 bl 80094ac <HAL_PCD_ISOOUTIncompleteCallback>
  5656. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  5657. __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
  5658. 8002660: 687b ldr r3, [r7, #4]
  5659. 8002662: 681b ldr r3, [r3, #0]
  5660. 8002664: 695a ldr r2, [r3, #20]
  5661. 8002666: 687b ldr r3, [r7, #4]
  5662. 8002668: 681b ldr r3, [r3, #0]
  5663. 800266a: f402 1200 and.w r2, r2, #2097152 ; 0x200000
  5664. 800266e: 615a str r2, [r3, #20]
  5665. }
  5666. /* Handle Connection event Interrupt */
  5667. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
  5668. 8002670: 687b ldr r3, [r7, #4]
  5669. 8002672: 681b ldr r3, [r3, #0]
  5670. 8002674: 4618 mov r0, r3
  5671. 8002676: f004 fe07 bl 8007288 <USB_ReadInterrupts>
  5672. 800267a: 4603 mov r3, r0
  5673. 800267c: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000
  5674. 8002680: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
  5675. 8002684: d10a bne.n 800269c <HAL_PCD_IRQHandler+0x760>
  5676. {
  5677. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5678. hpcd->ConnectCallback(hpcd);
  5679. #else
  5680. HAL_PCD_ConnectCallback(hpcd);
  5681. 8002686: 6878 ldr r0, [r7, #4]
  5682. 8002688: f006 ff34 bl 80094f4 <HAL_PCD_ConnectCallback>
  5683. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  5684. __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
  5685. 800268c: 687b ldr r3, [r7, #4]
  5686. 800268e: 681b ldr r3, [r3, #0]
  5687. 8002690: 695a ldr r2, [r3, #20]
  5688. 8002692: 687b ldr r3, [r7, #4]
  5689. 8002694: 681b ldr r3, [r3, #0]
  5690. 8002696: f002 4280 and.w r2, r2, #1073741824 ; 0x40000000
  5691. 800269a: 615a str r2, [r3, #20]
  5692. }
  5693. /* Handle Disconnection event Interrupt */
  5694. if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
  5695. 800269c: 687b ldr r3, [r7, #4]
  5696. 800269e: 681b ldr r3, [r3, #0]
  5697. 80026a0: 4618 mov r0, r3
  5698. 80026a2: f004 fdf1 bl 8007288 <USB_ReadInterrupts>
  5699. 80026a6: 4603 mov r3, r0
  5700. 80026a8: f003 0304 and.w r3, r3, #4
  5701. 80026ac: 2b04 cmp r3, #4
  5702. 80026ae: d115 bne.n 80026dc <HAL_PCD_IRQHandler+0x7a0>
  5703. {
  5704. temp = hpcd->Instance->GOTGINT;
  5705. 80026b0: 687b ldr r3, [r7, #4]
  5706. 80026b2: 681b ldr r3, [r3, #0]
  5707. 80026b4: 685b ldr r3, [r3, #4]
  5708. 80026b6: 61bb str r3, [r7, #24]
  5709. if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
  5710. 80026b8: 69bb ldr r3, [r7, #24]
  5711. 80026ba: f003 0304 and.w r3, r3, #4
  5712. 80026be: 2b00 cmp r3, #0
  5713. 80026c0: d002 beq.n 80026c8 <HAL_PCD_IRQHandler+0x78c>
  5714. {
  5715. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  5716. hpcd->DisconnectCallback(hpcd);
  5717. #else
  5718. HAL_PCD_DisconnectCallback(hpcd);
  5719. 80026c2: 6878 ldr r0, [r7, #4]
  5720. 80026c4: f006 ff24 bl 8009510 <HAL_PCD_DisconnectCallback>
  5721. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  5722. }
  5723. hpcd->Instance->GOTGINT |= temp;
  5724. 80026c8: 687b ldr r3, [r7, #4]
  5725. 80026ca: 681b ldr r3, [r3, #0]
  5726. 80026cc: 6859 ldr r1, [r3, #4]
  5727. 80026ce: 687b ldr r3, [r7, #4]
  5728. 80026d0: 681b ldr r3, [r3, #0]
  5729. 80026d2: 69ba ldr r2, [r7, #24]
  5730. 80026d4: 430a orrs r2, r1
  5731. 80026d6: 605a str r2, [r3, #4]
  5732. 80026d8: e000 b.n 80026dc <HAL_PCD_IRQHandler+0x7a0>
  5733. return;
  5734. 80026da: bf00 nop
  5735. }
  5736. }
  5737. }
  5738. 80026dc: 3734 adds r7, #52 ; 0x34
  5739. 80026de: 46bd mov sp, r7
  5740. 80026e0: bd90 pop {r4, r7, pc}
  5741. 080026e2 <HAL_PCD_SetAddress>:
  5742. * @param hpcd PCD handle
  5743. * @param address new device address
  5744. * @retval HAL status
  5745. */
  5746. HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
  5747. {
  5748. 80026e2: b580 push {r7, lr}
  5749. 80026e4: b082 sub sp, #8
  5750. 80026e6: af00 add r7, sp, #0
  5751. 80026e8: 6078 str r0, [r7, #4]
  5752. 80026ea: 460b mov r3, r1
  5753. 80026ec: 70fb strb r3, [r7, #3]
  5754. __HAL_LOCK(hpcd);
  5755. 80026ee: 687b ldr r3, [r7, #4]
  5756. 80026f0: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc
  5757. 80026f4: 2b01 cmp r3, #1
  5758. 80026f6: d101 bne.n 80026fc <HAL_PCD_SetAddress+0x1a>
  5759. 80026f8: 2302 movs r3, #2
  5760. 80026fa: e013 b.n 8002724 <HAL_PCD_SetAddress+0x42>
  5761. 80026fc: 687b ldr r3, [r7, #4]
  5762. 80026fe: 2201 movs r2, #1
  5763. 8002700: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  5764. hpcd->USB_Address = address;
  5765. 8002704: 687b ldr r3, [r7, #4]
  5766. 8002706: 78fa ldrb r2, [r7, #3]
  5767. 8002708: f883 2038 strb.w r2, [r3, #56] ; 0x38
  5768. (void)USB_SetDevAddress(hpcd->Instance, address);
  5769. 800270c: 687b ldr r3, [r7, #4]
  5770. 800270e: 681b ldr r3, [r3, #0]
  5771. 8002710: 78fa ldrb r2, [r7, #3]
  5772. 8002712: 4611 mov r1, r2
  5773. 8002714: 4618 mov r0, r3
  5774. 8002716: f004 fd4f bl 80071b8 <USB_SetDevAddress>
  5775. __HAL_UNLOCK(hpcd);
  5776. 800271a: 687b ldr r3, [r7, #4]
  5777. 800271c: 2200 movs r2, #0
  5778. 800271e: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  5779. return HAL_OK;
  5780. 8002722: 2300 movs r3, #0
  5781. }
  5782. 8002724: 4618 mov r0, r3
  5783. 8002726: 3708 adds r7, #8
  5784. 8002728: 46bd mov sp, r7
  5785. 800272a: bd80 pop {r7, pc}
  5786. 0800272c <HAL_PCD_EP_Open>:
  5787. * @param ep_type endpoint type
  5788. * @retval HAL status
  5789. */
  5790. HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
  5791. uint16_t ep_mps, uint8_t ep_type)
  5792. {
  5793. 800272c: b580 push {r7, lr}
  5794. 800272e: b084 sub sp, #16
  5795. 8002730: af00 add r7, sp, #0
  5796. 8002732: 6078 str r0, [r7, #4]
  5797. 8002734: 4608 mov r0, r1
  5798. 8002736: 4611 mov r1, r2
  5799. 8002738: 461a mov r2, r3
  5800. 800273a: 4603 mov r3, r0
  5801. 800273c: 70fb strb r3, [r7, #3]
  5802. 800273e: 460b mov r3, r1
  5803. 8002740: 803b strh r3, [r7, #0]
  5804. 8002742: 4613 mov r3, r2
  5805. 8002744: 70bb strb r3, [r7, #2]
  5806. HAL_StatusTypeDef ret = HAL_OK;
  5807. 8002746: 2300 movs r3, #0
  5808. 8002748: 72fb strb r3, [r7, #11]
  5809. PCD_EPTypeDef *ep;
  5810. if ((ep_addr & 0x80U) == 0x80U)
  5811. 800274a: f997 3003 ldrsb.w r3, [r7, #3]
  5812. 800274e: 2b00 cmp r3, #0
  5813. 8002750: da0f bge.n 8002772 <HAL_PCD_EP_Open+0x46>
  5814. {
  5815. ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
  5816. 8002752: 78fb ldrb r3, [r7, #3]
  5817. 8002754: f003 020f and.w r2, r3, #15
  5818. 8002758: 4613 mov r3, r2
  5819. 800275a: 00db lsls r3, r3, #3
  5820. 800275c: 1a9b subs r3, r3, r2
  5821. 800275e: 009b lsls r3, r3, #2
  5822. 8002760: 3338 adds r3, #56 ; 0x38
  5823. 8002762: 687a ldr r2, [r7, #4]
  5824. 8002764: 4413 add r3, r2
  5825. 8002766: 3304 adds r3, #4
  5826. 8002768: 60fb str r3, [r7, #12]
  5827. ep->is_in = 1U;
  5828. 800276a: 68fb ldr r3, [r7, #12]
  5829. 800276c: 2201 movs r2, #1
  5830. 800276e: 705a strb r2, [r3, #1]
  5831. 8002770: e00f b.n 8002792 <HAL_PCD_EP_Open+0x66>
  5832. }
  5833. else
  5834. {
  5835. ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
  5836. 8002772: 78fb ldrb r3, [r7, #3]
  5837. 8002774: f003 020f and.w r2, r3, #15
  5838. 8002778: 4613 mov r3, r2
  5839. 800277a: 00db lsls r3, r3, #3
  5840. 800277c: 1a9b subs r3, r3, r2
  5841. 800277e: 009b lsls r3, r3, #2
  5842. 8002780: f503 73fc add.w r3, r3, #504 ; 0x1f8
  5843. 8002784: 687a ldr r2, [r7, #4]
  5844. 8002786: 4413 add r3, r2
  5845. 8002788: 3304 adds r3, #4
  5846. 800278a: 60fb str r3, [r7, #12]
  5847. ep->is_in = 0U;
  5848. 800278c: 68fb ldr r3, [r7, #12]
  5849. 800278e: 2200 movs r2, #0
  5850. 8002790: 705a strb r2, [r3, #1]
  5851. }
  5852. ep->num = ep_addr & EP_ADDR_MSK;
  5853. 8002792: 78fb ldrb r3, [r7, #3]
  5854. 8002794: f003 030f and.w r3, r3, #15
  5855. 8002798: b2da uxtb r2, r3
  5856. 800279a: 68fb ldr r3, [r7, #12]
  5857. 800279c: 701a strb r2, [r3, #0]
  5858. ep->maxpacket = ep_mps;
  5859. 800279e: 883a ldrh r2, [r7, #0]
  5860. 80027a0: 68fb ldr r3, [r7, #12]
  5861. 80027a2: 609a str r2, [r3, #8]
  5862. ep->type = ep_type;
  5863. 80027a4: 68fb ldr r3, [r7, #12]
  5864. 80027a6: 78ba ldrb r2, [r7, #2]
  5865. 80027a8: 70da strb r2, [r3, #3]
  5866. if (ep->is_in != 0U)
  5867. 80027aa: 68fb ldr r3, [r7, #12]
  5868. 80027ac: 785b ldrb r3, [r3, #1]
  5869. 80027ae: 2b00 cmp r3, #0
  5870. 80027b0: d004 beq.n 80027bc <HAL_PCD_EP_Open+0x90>
  5871. {
  5872. /* Assign a Tx FIFO */
  5873. ep->tx_fifo_num = ep->num;
  5874. 80027b2: 68fb ldr r3, [r7, #12]
  5875. 80027b4: 781b ldrb r3, [r3, #0]
  5876. 80027b6: b29a uxth r2, r3
  5877. 80027b8: 68fb ldr r3, [r7, #12]
  5878. 80027ba: 80da strh r2, [r3, #6]
  5879. }
  5880. /* Set initial data PID. */
  5881. if (ep_type == EP_TYPE_BULK)
  5882. 80027bc: 78bb ldrb r3, [r7, #2]
  5883. 80027be: 2b02 cmp r3, #2
  5884. 80027c0: d102 bne.n 80027c8 <HAL_PCD_EP_Open+0x9c>
  5885. {
  5886. ep->data_pid_start = 0U;
  5887. 80027c2: 68fb ldr r3, [r7, #12]
  5888. 80027c4: 2200 movs r2, #0
  5889. 80027c6: 711a strb r2, [r3, #4]
  5890. }
  5891. __HAL_LOCK(hpcd);
  5892. 80027c8: 687b ldr r3, [r7, #4]
  5893. 80027ca: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc
  5894. 80027ce: 2b01 cmp r3, #1
  5895. 80027d0: d101 bne.n 80027d6 <HAL_PCD_EP_Open+0xaa>
  5896. 80027d2: 2302 movs r3, #2
  5897. 80027d4: e00e b.n 80027f4 <HAL_PCD_EP_Open+0xc8>
  5898. 80027d6: 687b ldr r3, [r7, #4]
  5899. 80027d8: 2201 movs r2, #1
  5900. 80027da: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  5901. (void)USB_ActivateEndpoint(hpcd->Instance, ep);
  5902. 80027de: 687b ldr r3, [r7, #4]
  5903. 80027e0: 681b ldr r3, [r3, #0]
  5904. 80027e2: 68f9 ldr r1, [r7, #12]
  5905. 80027e4: 4618 mov r0, r3
  5906. 80027e6: f003 fe75 bl 80064d4 <USB_ActivateEndpoint>
  5907. __HAL_UNLOCK(hpcd);
  5908. 80027ea: 687b ldr r3, [r7, #4]
  5909. 80027ec: 2200 movs r2, #0
  5910. 80027ee: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  5911. return ret;
  5912. 80027f2: 7afb ldrb r3, [r7, #11]
  5913. }
  5914. 80027f4: 4618 mov r0, r3
  5915. 80027f6: 3710 adds r7, #16
  5916. 80027f8: 46bd mov sp, r7
  5917. 80027fa: bd80 pop {r7, pc}
  5918. 080027fc <HAL_PCD_EP_Close>:
  5919. * @param hpcd PCD handle
  5920. * @param ep_addr endpoint address
  5921. * @retval HAL status
  5922. */
  5923. HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
  5924. {
  5925. 80027fc: b580 push {r7, lr}
  5926. 80027fe: b084 sub sp, #16
  5927. 8002800: af00 add r7, sp, #0
  5928. 8002802: 6078 str r0, [r7, #4]
  5929. 8002804: 460b mov r3, r1
  5930. 8002806: 70fb strb r3, [r7, #3]
  5931. PCD_EPTypeDef *ep;
  5932. if ((ep_addr & 0x80U) == 0x80U)
  5933. 8002808: f997 3003 ldrsb.w r3, [r7, #3]
  5934. 800280c: 2b00 cmp r3, #0
  5935. 800280e: da0f bge.n 8002830 <HAL_PCD_EP_Close+0x34>
  5936. {
  5937. ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
  5938. 8002810: 78fb ldrb r3, [r7, #3]
  5939. 8002812: f003 020f and.w r2, r3, #15
  5940. 8002816: 4613 mov r3, r2
  5941. 8002818: 00db lsls r3, r3, #3
  5942. 800281a: 1a9b subs r3, r3, r2
  5943. 800281c: 009b lsls r3, r3, #2
  5944. 800281e: 3338 adds r3, #56 ; 0x38
  5945. 8002820: 687a ldr r2, [r7, #4]
  5946. 8002822: 4413 add r3, r2
  5947. 8002824: 3304 adds r3, #4
  5948. 8002826: 60fb str r3, [r7, #12]
  5949. ep->is_in = 1U;
  5950. 8002828: 68fb ldr r3, [r7, #12]
  5951. 800282a: 2201 movs r2, #1
  5952. 800282c: 705a strb r2, [r3, #1]
  5953. 800282e: e00f b.n 8002850 <HAL_PCD_EP_Close+0x54>
  5954. }
  5955. else
  5956. {
  5957. ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
  5958. 8002830: 78fb ldrb r3, [r7, #3]
  5959. 8002832: f003 020f and.w r2, r3, #15
  5960. 8002836: 4613 mov r3, r2
  5961. 8002838: 00db lsls r3, r3, #3
  5962. 800283a: 1a9b subs r3, r3, r2
  5963. 800283c: 009b lsls r3, r3, #2
  5964. 800283e: f503 73fc add.w r3, r3, #504 ; 0x1f8
  5965. 8002842: 687a ldr r2, [r7, #4]
  5966. 8002844: 4413 add r3, r2
  5967. 8002846: 3304 adds r3, #4
  5968. 8002848: 60fb str r3, [r7, #12]
  5969. ep->is_in = 0U;
  5970. 800284a: 68fb ldr r3, [r7, #12]
  5971. 800284c: 2200 movs r2, #0
  5972. 800284e: 705a strb r2, [r3, #1]
  5973. }
  5974. ep->num = ep_addr & EP_ADDR_MSK;
  5975. 8002850: 78fb ldrb r3, [r7, #3]
  5976. 8002852: f003 030f and.w r3, r3, #15
  5977. 8002856: b2da uxtb r2, r3
  5978. 8002858: 68fb ldr r3, [r7, #12]
  5979. 800285a: 701a strb r2, [r3, #0]
  5980. __HAL_LOCK(hpcd);
  5981. 800285c: 687b ldr r3, [r7, #4]
  5982. 800285e: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc
  5983. 8002862: 2b01 cmp r3, #1
  5984. 8002864: d101 bne.n 800286a <HAL_PCD_EP_Close+0x6e>
  5985. 8002866: 2302 movs r3, #2
  5986. 8002868: e00e b.n 8002888 <HAL_PCD_EP_Close+0x8c>
  5987. 800286a: 687b ldr r3, [r7, #4]
  5988. 800286c: 2201 movs r2, #1
  5989. 800286e: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  5990. (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
  5991. 8002872: 687b ldr r3, [r7, #4]
  5992. 8002874: 681b ldr r3, [r3, #0]
  5993. 8002876: 68f9 ldr r1, [r7, #12]
  5994. 8002878: 4618 mov r0, r3
  5995. 800287a: f003 feb3 bl 80065e4 <USB_DeactivateEndpoint>
  5996. __HAL_UNLOCK(hpcd);
  5997. 800287e: 687b ldr r3, [r7, #4]
  5998. 8002880: 2200 movs r2, #0
  5999. 8002882: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  6000. return HAL_OK;
  6001. 8002886: 2300 movs r3, #0
  6002. }
  6003. 8002888: 4618 mov r0, r3
  6004. 800288a: 3710 adds r7, #16
  6005. 800288c: 46bd mov sp, r7
  6006. 800288e: bd80 pop {r7, pc}
  6007. 08002890 <HAL_PCD_EP_Receive>:
  6008. * @param pBuf pointer to the reception buffer
  6009. * @param len amount of data to be received
  6010. * @retval HAL status
  6011. */
  6012. HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
  6013. {
  6014. 8002890: b580 push {r7, lr}
  6015. 8002892: b086 sub sp, #24
  6016. 8002894: af00 add r7, sp, #0
  6017. 8002896: 60f8 str r0, [r7, #12]
  6018. 8002898: 607a str r2, [r7, #4]
  6019. 800289a: 603b str r3, [r7, #0]
  6020. 800289c: 460b mov r3, r1
  6021. 800289e: 72fb strb r3, [r7, #11]
  6022. PCD_EPTypeDef *ep;
  6023. ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
  6024. 80028a0: 7afb ldrb r3, [r7, #11]
  6025. 80028a2: f003 020f and.w r2, r3, #15
  6026. 80028a6: 4613 mov r3, r2
  6027. 80028a8: 00db lsls r3, r3, #3
  6028. 80028aa: 1a9b subs r3, r3, r2
  6029. 80028ac: 009b lsls r3, r3, #2
  6030. 80028ae: f503 73fc add.w r3, r3, #504 ; 0x1f8
  6031. 80028b2: 68fa ldr r2, [r7, #12]
  6032. 80028b4: 4413 add r3, r2
  6033. 80028b6: 3304 adds r3, #4
  6034. 80028b8: 617b str r3, [r7, #20]
  6035. /*setup and start the Xfer */
  6036. ep->xfer_buff = pBuf;
  6037. 80028ba: 697b ldr r3, [r7, #20]
  6038. 80028bc: 687a ldr r2, [r7, #4]
  6039. 80028be: 60da str r2, [r3, #12]
  6040. ep->xfer_len = len;
  6041. 80028c0: 697b ldr r3, [r7, #20]
  6042. 80028c2: 683a ldr r2, [r7, #0]
  6043. 80028c4: 615a str r2, [r3, #20]
  6044. ep->xfer_count = 0U;
  6045. 80028c6: 697b ldr r3, [r7, #20]
  6046. 80028c8: 2200 movs r2, #0
  6047. 80028ca: 619a str r2, [r3, #24]
  6048. ep->is_in = 0U;
  6049. 80028cc: 697b ldr r3, [r7, #20]
  6050. 80028ce: 2200 movs r2, #0
  6051. 80028d0: 705a strb r2, [r3, #1]
  6052. ep->num = ep_addr & EP_ADDR_MSK;
  6053. 80028d2: 7afb ldrb r3, [r7, #11]
  6054. 80028d4: f003 030f and.w r3, r3, #15
  6055. 80028d8: b2da uxtb r2, r3
  6056. 80028da: 697b ldr r3, [r7, #20]
  6057. 80028dc: 701a strb r2, [r3, #0]
  6058. if (hpcd->Init.dma_enable == 1U)
  6059. 80028de: 68fb ldr r3, [r7, #12]
  6060. 80028e0: 691b ldr r3, [r3, #16]
  6061. 80028e2: 2b01 cmp r3, #1
  6062. 80028e4: d102 bne.n 80028ec <HAL_PCD_EP_Receive+0x5c>
  6063. {
  6064. ep->dma_addr = (uint32_t)pBuf;
  6065. 80028e6: 687a ldr r2, [r7, #4]
  6066. 80028e8: 697b ldr r3, [r7, #20]
  6067. 80028ea: 611a str r2, [r3, #16]
  6068. }
  6069. if ((ep_addr & EP_ADDR_MSK) == 0U)
  6070. 80028ec: 7afb ldrb r3, [r7, #11]
  6071. 80028ee: f003 030f and.w r3, r3, #15
  6072. 80028f2: 2b00 cmp r3, #0
  6073. 80028f4: d109 bne.n 800290a <HAL_PCD_EP_Receive+0x7a>
  6074. {
  6075. (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
  6076. 80028f6: 68fb ldr r3, [r7, #12]
  6077. 80028f8: 6818 ldr r0, [r3, #0]
  6078. 80028fa: 68fb ldr r3, [r7, #12]
  6079. 80028fc: 691b ldr r3, [r3, #16]
  6080. 80028fe: b2db uxtb r3, r3
  6081. 8002900: 461a mov r2, r3
  6082. 8002902: 6979 ldr r1, [r7, #20]
  6083. 8002904: f004 f996 bl 8006c34 <USB_EP0StartXfer>
  6084. 8002908: e008 b.n 800291c <HAL_PCD_EP_Receive+0x8c>
  6085. }
  6086. else
  6087. {
  6088. (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
  6089. 800290a: 68fb ldr r3, [r7, #12]
  6090. 800290c: 6818 ldr r0, [r3, #0]
  6091. 800290e: 68fb ldr r3, [r7, #12]
  6092. 8002910: 691b ldr r3, [r3, #16]
  6093. 8002912: b2db uxtb r3, r3
  6094. 8002914: 461a mov r2, r3
  6095. 8002916: 6979 ldr r1, [r7, #20]
  6096. 8002918: f003 ff40 bl 800679c <USB_EPStartXfer>
  6097. }
  6098. return HAL_OK;
  6099. 800291c: 2300 movs r3, #0
  6100. }
  6101. 800291e: 4618 mov r0, r3
  6102. 8002920: 3718 adds r7, #24
  6103. 8002922: 46bd mov sp, r7
  6104. 8002924: bd80 pop {r7, pc}
  6105. 08002926 <HAL_PCD_EP_GetRxCount>:
  6106. * @param hpcd PCD handle
  6107. * @param ep_addr endpoint address
  6108. * @retval Data Size
  6109. */
  6110. uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
  6111. {
  6112. 8002926: b480 push {r7}
  6113. 8002928: b083 sub sp, #12
  6114. 800292a: af00 add r7, sp, #0
  6115. 800292c: 6078 str r0, [r7, #4]
  6116. 800292e: 460b mov r3, r1
  6117. 8002930: 70fb strb r3, [r7, #3]
  6118. return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
  6119. 8002932: 78fb ldrb r3, [r7, #3]
  6120. 8002934: f003 020f and.w r2, r3, #15
  6121. 8002938: 6879 ldr r1, [r7, #4]
  6122. 800293a: 4613 mov r3, r2
  6123. 800293c: 00db lsls r3, r3, #3
  6124. 800293e: 1a9b subs r3, r3, r2
  6125. 8002940: 009b lsls r3, r3, #2
  6126. 8002942: 440b add r3, r1
  6127. 8002944: f503 7305 add.w r3, r3, #532 ; 0x214
  6128. 8002948: 681b ldr r3, [r3, #0]
  6129. }
  6130. 800294a: 4618 mov r0, r3
  6131. 800294c: 370c adds r7, #12
  6132. 800294e: 46bd mov sp, r7
  6133. 8002950: f85d 7b04 ldr.w r7, [sp], #4
  6134. 8002954: 4770 bx lr
  6135. 08002956 <HAL_PCD_EP_Transmit>:
  6136. * @param pBuf pointer to the transmission buffer
  6137. * @param len amount of data to be sent
  6138. * @retval HAL status
  6139. */
  6140. HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
  6141. {
  6142. 8002956: b580 push {r7, lr}
  6143. 8002958: b086 sub sp, #24
  6144. 800295a: af00 add r7, sp, #0
  6145. 800295c: 60f8 str r0, [r7, #12]
  6146. 800295e: 607a str r2, [r7, #4]
  6147. 8002960: 603b str r3, [r7, #0]
  6148. 8002962: 460b mov r3, r1
  6149. 8002964: 72fb strb r3, [r7, #11]
  6150. PCD_EPTypeDef *ep;
  6151. ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
  6152. 8002966: 7afb ldrb r3, [r7, #11]
  6153. 8002968: f003 020f and.w r2, r3, #15
  6154. 800296c: 4613 mov r3, r2
  6155. 800296e: 00db lsls r3, r3, #3
  6156. 8002970: 1a9b subs r3, r3, r2
  6157. 8002972: 009b lsls r3, r3, #2
  6158. 8002974: 3338 adds r3, #56 ; 0x38
  6159. 8002976: 68fa ldr r2, [r7, #12]
  6160. 8002978: 4413 add r3, r2
  6161. 800297a: 3304 adds r3, #4
  6162. 800297c: 617b str r3, [r7, #20]
  6163. /*setup and start the Xfer */
  6164. ep->xfer_buff = pBuf;
  6165. 800297e: 697b ldr r3, [r7, #20]
  6166. 8002980: 687a ldr r2, [r7, #4]
  6167. 8002982: 60da str r2, [r3, #12]
  6168. ep->xfer_len = len;
  6169. 8002984: 697b ldr r3, [r7, #20]
  6170. 8002986: 683a ldr r2, [r7, #0]
  6171. 8002988: 615a str r2, [r3, #20]
  6172. ep->xfer_count = 0U;
  6173. 800298a: 697b ldr r3, [r7, #20]
  6174. 800298c: 2200 movs r2, #0
  6175. 800298e: 619a str r2, [r3, #24]
  6176. ep->is_in = 1U;
  6177. 8002990: 697b ldr r3, [r7, #20]
  6178. 8002992: 2201 movs r2, #1
  6179. 8002994: 705a strb r2, [r3, #1]
  6180. ep->num = ep_addr & EP_ADDR_MSK;
  6181. 8002996: 7afb ldrb r3, [r7, #11]
  6182. 8002998: f003 030f and.w r3, r3, #15
  6183. 800299c: b2da uxtb r2, r3
  6184. 800299e: 697b ldr r3, [r7, #20]
  6185. 80029a0: 701a strb r2, [r3, #0]
  6186. if (hpcd->Init.dma_enable == 1U)
  6187. 80029a2: 68fb ldr r3, [r7, #12]
  6188. 80029a4: 691b ldr r3, [r3, #16]
  6189. 80029a6: 2b01 cmp r3, #1
  6190. 80029a8: d102 bne.n 80029b0 <HAL_PCD_EP_Transmit+0x5a>
  6191. {
  6192. ep->dma_addr = (uint32_t)pBuf;
  6193. 80029aa: 687a ldr r2, [r7, #4]
  6194. 80029ac: 697b ldr r3, [r7, #20]
  6195. 80029ae: 611a str r2, [r3, #16]
  6196. }
  6197. if ((ep_addr & EP_ADDR_MSK) == 0U)
  6198. 80029b0: 7afb ldrb r3, [r7, #11]
  6199. 80029b2: f003 030f and.w r3, r3, #15
  6200. 80029b6: 2b00 cmp r3, #0
  6201. 80029b8: d109 bne.n 80029ce <HAL_PCD_EP_Transmit+0x78>
  6202. {
  6203. (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
  6204. 80029ba: 68fb ldr r3, [r7, #12]
  6205. 80029bc: 6818 ldr r0, [r3, #0]
  6206. 80029be: 68fb ldr r3, [r7, #12]
  6207. 80029c0: 691b ldr r3, [r3, #16]
  6208. 80029c2: b2db uxtb r3, r3
  6209. 80029c4: 461a mov r2, r3
  6210. 80029c6: 6979 ldr r1, [r7, #20]
  6211. 80029c8: f004 f934 bl 8006c34 <USB_EP0StartXfer>
  6212. 80029cc: e008 b.n 80029e0 <HAL_PCD_EP_Transmit+0x8a>
  6213. }
  6214. else
  6215. {
  6216. (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
  6217. 80029ce: 68fb ldr r3, [r7, #12]
  6218. 80029d0: 6818 ldr r0, [r3, #0]
  6219. 80029d2: 68fb ldr r3, [r7, #12]
  6220. 80029d4: 691b ldr r3, [r3, #16]
  6221. 80029d6: b2db uxtb r3, r3
  6222. 80029d8: 461a mov r2, r3
  6223. 80029da: 6979 ldr r1, [r7, #20]
  6224. 80029dc: f003 fede bl 800679c <USB_EPStartXfer>
  6225. }
  6226. return HAL_OK;
  6227. 80029e0: 2300 movs r3, #0
  6228. }
  6229. 80029e2: 4618 mov r0, r3
  6230. 80029e4: 3718 adds r7, #24
  6231. 80029e6: 46bd mov sp, r7
  6232. 80029e8: bd80 pop {r7, pc}
  6233. 080029ea <HAL_PCD_EP_SetStall>:
  6234. * @param hpcd PCD handle
  6235. * @param ep_addr endpoint address
  6236. * @retval HAL status
  6237. */
  6238. HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
  6239. {
  6240. 80029ea: b580 push {r7, lr}
  6241. 80029ec: b084 sub sp, #16
  6242. 80029ee: af00 add r7, sp, #0
  6243. 80029f0: 6078 str r0, [r7, #4]
  6244. 80029f2: 460b mov r3, r1
  6245. 80029f4: 70fb strb r3, [r7, #3]
  6246. PCD_EPTypeDef *ep;
  6247. if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
  6248. 80029f6: 78fb ldrb r3, [r7, #3]
  6249. 80029f8: f003 020f and.w r2, r3, #15
  6250. 80029fc: 687b ldr r3, [r7, #4]
  6251. 80029fe: 685b ldr r3, [r3, #4]
  6252. 8002a00: 429a cmp r2, r3
  6253. 8002a02: d901 bls.n 8002a08 <HAL_PCD_EP_SetStall+0x1e>
  6254. {
  6255. return HAL_ERROR;
  6256. 8002a04: 2301 movs r3, #1
  6257. 8002a06: e050 b.n 8002aaa <HAL_PCD_EP_SetStall+0xc0>
  6258. }
  6259. if ((0x80U & ep_addr) == 0x80U)
  6260. 8002a08: f997 3003 ldrsb.w r3, [r7, #3]
  6261. 8002a0c: 2b00 cmp r3, #0
  6262. 8002a0e: da0f bge.n 8002a30 <HAL_PCD_EP_SetStall+0x46>
  6263. {
  6264. ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
  6265. 8002a10: 78fb ldrb r3, [r7, #3]
  6266. 8002a12: f003 020f and.w r2, r3, #15
  6267. 8002a16: 4613 mov r3, r2
  6268. 8002a18: 00db lsls r3, r3, #3
  6269. 8002a1a: 1a9b subs r3, r3, r2
  6270. 8002a1c: 009b lsls r3, r3, #2
  6271. 8002a1e: 3338 adds r3, #56 ; 0x38
  6272. 8002a20: 687a ldr r2, [r7, #4]
  6273. 8002a22: 4413 add r3, r2
  6274. 8002a24: 3304 adds r3, #4
  6275. 8002a26: 60fb str r3, [r7, #12]
  6276. ep->is_in = 1U;
  6277. 8002a28: 68fb ldr r3, [r7, #12]
  6278. 8002a2a: 2201 movs r2, #1
  6279. 8002a2c: 705a strb r2, [r3, #1]
  6280. 8002a2e: e00d b.n 8002a4c <HAL_PCD_EP_SetStall+0x62>
  6281. }
  6282. else
  6283. {
  6284. ep = &hpcd->OUT_ep[ep_addr];
  6285. 8002a30: 78fa ldrb r2, [r7, #3]
  6286. 8002a32: 4613 mov r3, r2
  6287. 8002a34: 00db lsls r3, r3, #3
  6288. 8002a36: 1a9b subs r3, r3, r2
  6289. 8002a38: 009b lsls r3, r3, #2
  6290. 8002a3a: f503 73fc add.w r3, r3, #504 ; 0x1f8
  6291. 8002a3e: 687a ldr r2, [r7, #4]
  6292. 8002a40: 4413 add r3, r2
  6293. 8002a42: 3304 adds r3, #4
  6294. 8002a44: 60fb str r3, [r7, #12]
  6295. ep->is_in = 0U;
  6296. 8002a46: 68fb ldr r3, [r7, #12]
  6297. 8002a48: 2200 movs r2, #0
  6298. 8002a4a: 705a strb r2, [r3, #1]
  6299. }
  6300. ep->is_stall = 1U;
  6301. 8002a4c: 68fb ldr r3, [r7, #12]
  6302. 8002a4e: 2201 movs r2, #1
  6303. 8002a50: 709a strb r2, [r3, #2]
  6304. ep->num = ep_addr & EP_ADDR_MSK;
  6305. 8002a52: 78fb ldrb r3, [r7, #3]
  6306. 8002a54: f003 030f and.w r3, r3, #15
  6307. 8002a58: b2da uxtb r2, r3
  6308. 8002a5a: 68fb ldr r3, [r7, #12]
  6309. 8002a5c: 701a strb r2, [r3, #0]
  6310. __HAL_LOCK(hpcd);
  6311. 8002a5e: 687b ldr r3, [r7, #4]
  6312. 8002a60: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc
  6313. 8002a64: 2b01 cmp r3, #1
  6314. 8002a66: d101 bne.n 8002a6c <HAL_PCD_EP_SetStall+0x82>
  6315. 8002a68: 2302 movs r3, #2
  6316. 8002a6a: e01e b.n 8002aaa <HAL_PCD_EP_SetStall+0xc0>
  6317. 8002a6c: 687b ldr r3, [r7, #4]
  6318. 8002a6e: 2201 movs r2, #1
  6319. 8002a70: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  6320. (void)USB_EPSetStall(hpcd->Instance, ep);
  6321. 8002a74: 687b ldr r3, [r7, #4]
  6322. 8002a76: 681b ldr r3, [r3, #0]
  6323. 8002a78: 68f9 ldr r1, [r7, #12]
  6324. 8002a7a: 4618 mov r0, r3
  6325. 8002a7c: f004 fac8 bl 8007010 <USB_EPSetStall>
  6326. if ((ep_addr & EP_ADDR_MSK) == 0U)
  6327. 8002a80: 78fb ldrb r3, [r7, #3]
  6328. 8002a82: f003 030f and.w r3, r3, #15
  6329. 8002a86: 2b00 cmp r3, #0
  6330. 8002a88: d10a bne.n 8002aa0 <HAL_PCD_EP_SetStall+0xb6>
  6331. {
  6332. (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
  6333. 8002a8a: 687b ldr r3, [r7, #4]
  6334. 8002a8c: 6818 ldr r0, [r3, #0]
  6335. 8002a8e: 687b ldr r3, [r7, #4]
  6336. 8002a90: 691b ldr r3, [r3, #16]
  6337. 8002a92: b2d9 uxtb r1, r3
  6338. 8002a94: 687b ldr r3, [r7, #4]
  6339. 8002a96: f503 7371 add.w r3, r3, #964 ; 0x3c4
  6340. 8002a9a: 461a mov r2, r3
  6341. 8002a9c: f004 fcba bl 8007414 <USB_EP0_OutStart>
  6342. }
  6343. __HAL_UNLOCK(hpcd);
  6344. 8002aa0: 687b ldr r3, [r7, #4]
  6345. 8002aa2: 2200 movs r2, #0
  6346. 8002aa4: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  6347. return HAL_OK;
  6348. 8002aa8: 2300 movs r3, #0
  6349. }
  6350. 8002aaa: 4618 mov r0, r3
  6351. 8002aac: 3710 adds r7, #16
  6352. 8002aae: 46bd mov sp, r7
  6353. 8002ab0: bd80 pop {r7, pc}
  6354. 08002ab2 <HAL_PCD_EP_ClrStall>:
  6355. * @param hpcd PCD handle
  6356. * @param ep_addr endpoint address
  6357. * @retval HAL status
  6358. */
  6359. HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
  6360. {
  6361. 8002ab2: b580 push {r7, lr}
  6362. 8002ab4: b084 sub sp, #16
  6363. 8002ab6: af00 add r7, sp, #0
  6364. 8002ab8: 6078 str r0, [r7, #4]
  6365. 8002aba: 460b mov r3, r1
  6366. 8002abc: 70fb strb r3, [r7, #3]
  6367. PCD_EPTypeDef *ep;
  6368. if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
  6369. 8002abe: 78fb ldrb r3, [r7, #3]
  6370. 8002ac0: f003 020f and.w r2, r3, #15
  6371. 8002ac4: 687b ldr r3, [r7, #4]
  6372. 8002ac6: 685b ldr r3, [r3, #4]
  6373. 8002ac8: 429a cmp r2, r3
  6374. 8002aca: d901 bls.n 8002ad0 <HAL_PCD_EP_ClrStall+0x1e>
  6375. {
  6376. return HAL_ERROR;
  6377. 8002acc: 2301 movs r3, #1
  6378. 8002ace: e042 b.n 8002b56 <HAL_PCD_EP_ClrStall+0xa4>
  6379. }
  6380. if ((0x80U & ep_addr) == 0x80U)
  6381. 8002ad0: f997 3003 ldrsb.w r3, [r7, #3]
  6382. 8002ad4: 2b00 cmp r3, #0
  6383. 8002ad6: da0f bge.n 8002af8 <HAL_PCD_EP_ClrStall+0x46>
  6384. {
  6385. ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
  6386. 8002ad8: 78fb ldrb r3, [r7, #3]
  6387. 8002ada: f003 020f and.w r2, r3, #15
  6388. 8002ade: 4613 mov r3, r2
  6389. 8002ae0: 00db lsls r3, r3, #3
  6390. 8002ae2: 1a9b subs r3, r3, r2
  6391. 8002ae4: 009b lsls r3, r3, #2
  6392. 8002ae6: 3338 adds r3, #56 ; 0x38
  6393. 8002ae8: 687a ldr r2, [r7, #4]
  6394. 8002aea: 4413 add r3, r2
  6395. 8002aec: 3304 adds r3, #4
  6396. 8002aee: 60fb str r3, [r7, #12]
  6397. ep->is_in = 1U;
  6398. 8002af0: 68fb ldr r3, [r7, #12]
  6399. 8002af2: 2201 movs r2, #1
  6400. 8002af4: 705a strb r2, [r3, #1]
  6401. 8002af6: e00f b.n 8002b18 <HAL_PCD_EP_ClrStall+0x66>
  6402. }
  6403. else
  6404. {
  6405. ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
  6406. 8002af8: 78fb ldrb r3, [r7, #3]
  6407. 8002afa: f003 020f and.w r2, r3, #15
  6408. 8002afe: 4613 mov r3, r2
  6409. 8002b00: 00db lsls r3, r3, #3
  6410. 8002b02: 1a9b subs r3, r3, r2
  6411. 8002b04: 009b lsls r3, r3, #2
  6412. 8002b06: f503 73fc add.w r3, r3, #504 ; 0x1f8
  6413. 8002b0a: 687a ldr r2, [r7, #4]
  6414. 8002b0c: 4413 add r3, r2
  6415. 8002b0e: 3304 adds r3, #4
  6416. 8002b10: 60fb str r3, [r7, #12]
  6417. ep->is_in = 0U;
  6418. 8002b12: 68fb ldr r3, [r7, #12]
  6419. 8002b14: 2200 movs r2, #0
  6420. 8002b16: 705a strb r2, [r3, #1]
  6421. }
  6422. ep->is_stall = 0U;
  6423. 8002b18: 68fb ldr r3, [r7, #12]
  6424. 8002b1a: 2200 movs r2, #0
  6425. 8002b1c: 709a strb r2, [r3, #2]
  6426. ep->num = ep_addr & EP_ADDR_MSK;
  6427. 8002b1e: 78fb ldrb r3, [r7, #3]
  6428. 8002b20: f003 030f and.w r3, r3, #15
  6429. 8002b24: b2da uxtb r2, r3
  6430. 8002b26: 68fb ldr r3, [r7, #12]
  6431. 8002b28: 701a strb r2, [r3, #0]
  6432. __HAL_LOCK(hpcd);
  6433. 8002b2a: 687b ldr r3, [r7, #4]
  6434. 8002b2c: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc
  6435. 8002b30: 2b01 cmp r3, #1
  6436. 8002b32: d101 bne.n 8002b38 <HAL_PCD_EP_ClrStall+0x86>
  6437. 8002b34: 2302 movs r3, #2
  6438. 8002b36: e00e b.n 8002b56 <HAL_PCD_EP_ClrStall+0xa4>
  6439. 8002b38: 687b ldr r3, [r7, #4]
  6440. 8002b3a: 2201 movs r2, #1
  6441. 8002b3c: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  6442. (void)USB_EPClearStall(hpcd->Instance, ep);
  6443. 8002b40: 687b ldr r3, [r7, #4]
  6444. 8002b42: 681b ldr r3, [r3, #0]
  6445. 8002b44: 68f9 ldr r1, [r7, #12]
  6446. 8002b46: 4618 mov r0, r3
  6447. 8002b48: f004 fad0 bl 80070ec <USB_EPClearStall>
  6448. __HAL_UNLOCK(hpcd);
  6449. 8002b4c: 687b ldr r3, [r7, #4]
  6450. 8002b4e: 2200 movs r2, #0
  6451. 8002b50: f883 23bc strb.w r2, [r3, #956] ; 0x3bc
  6452. return HAL_OK;
  6453. 8002b54: 2300 movs r3, #0
  6454. }
  6455. 8002b56: 4618 mov r0, r3
  6456. 8002b58: 3710 adds r7, #16
  6457. 8002b5a: 46bd mov sp, r7
  6458. 8002b5c: bd80 pop {r7, pc}
  6459. 08002b5e <PCD_WriteEmptyTxFifo>:
  6460. * @param hpcd PCD handle
  6461. * @param epnum endpoint number
  6462. * @retval HAL status
  6463. */
  6464. static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
  6465. {
  6466. 8002b5e: b580 push {r7, lr}
  6467. 8002b60: b08a sub sp, #40 ; 0x28
  6468. 8002b62: af02 add r7, sp, #8
  6469. 8002b64: 6078 str r0, [r7, #4]
  6470. 8002b66: 6039 str r1, [r7, #0]
  6471. USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
  6472. 8002b68: 687b ldr r3, [r7, #4]
  6473. 8002b6a: 681b ldr r3, [r3, #0]
  6474. 8002b6c: 617b str r3, [r7, #20]
  6475. uint32_t USBx_BASE = (uint32_t)USBx;
  6476. 8002b6e: 697b ldr r3, [r7, #20]
  6477. 8002b70: 613b str r3, [r7, #16]
  6478. USB_OTG_EPTypeDef *ep;
  6479. uint32_t len;
  6480. uint32_t len32b;
  6481. uint32_t fifoemptymsk;
  6482. ep = &hpcd->IN_ep[epnum];
  6483. 8002b72: 683a ldr r2, [r7, #0]
  6484. 8002b74: 4613 mov r3, r2
  6485. 8002b76: 00db lsls r3, r3, #3
  6486. 8002b78: 1a9b subs r3, r3, r2
  6487. 8002b7a: 009b lsls r3, r3, #2
  6488. 8002b7c: 3338 adds r3, #56 ; 0x38
  6489. 8002b7e: 687a ldr r2, [r7, #4]
  6490. 8002b80: 4413 add r3, r2
  6491. 8002b82: 3304 adds r3, #4
  6492. 8002b84: 60fb str r3, [r7, #12]
  6493. if (ep->xfer_count > ep->xfer_len)
  6494. 8002b86: 68fb ldr r3, [r7, #12]
  6495. 8002b88: 699a ldr r2, [r3, #24]
  6496. 8002b8a: 68fb ldr r3, [r7, #12]
  6497. 8002b8c: 695b ldr r3, [r3, #20]
  6498. 8002b8e: 429a cmp r2, r3
  6499. 8002b90: d901 bls.n 8002b96 <PCD_WriteEmptyTxFifo+0x38>
  6500. {
  6501. return HAL_ERROR;
  6502. 8002b92: 2301 movs r3, #1
  6503. 8002b94: e06c b.n 8002c70 <PCD_WriteEmptyTxFifo+0x112>
  6504. }
  6505. len = ep->xfer_len - ep->xfer_count;
  6506. 8002b96: 68fb ldr r3, [r7, #12]
  6507. 8002b98: 695a ldr r2, [r3, #20]
  6508. 8002b9a: 68fb ldr r3, [r7, #12]
  6509. 8002b9c: 699b ldr r3, [r3, #24]
  6510. 8002b9e: 1ad3 subs r3, r2, r3
  6511. 8002ba0: 61fb str r3, [r7, #28]
  6512. if (len > ep->maxpacket)
  6513. 8002ba2: 68fb ldr r3, [r7, #12]
  6514. 8002ba4: 689b ldr r3, [r3, #8]
  6515. 8002ba6: 69fa ldr r2, [r7, #28]
  6516. 8002ba8: 429a cmp r2, r3
  6517. 8002baa: d902 bls.n 8002bb2 <PCD_WriteEmptyTxFifo+0x54>
  6518. {
  6519. len = ep->maxpacket;
  6520. 8002bac: 68fb ldr r3, [r7, #12]
  6521. 8002bae: 689b ldr r3, [r3, #8]
  6522. 8002bb0: 61fb str r3, [r7, #28]
  6523. }
  6524. len32b = (len + 3U) / 4U;
  6525. 8002bb2: 69fb ldr r3, [r7, #28]
  6526. 8002bb4: 3303 adds r3, #3
  6527. 8002bb6: 089b lsrs r3, r3, #2
  6528. 8002bb8: 61bb str r3, [r7, #24]
  6529. while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
  6530. 8002bba: e02b b.n 8002c14 <PCD_WriteEmptyTxFifo+0xb6>
  6531. (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
  6532. {
  6533. /* Write the FIFO */
  6534. len = ep->xfer_len - ep->xfer_count;
  6535. 8002bbc: 68fb ldr r3, [r7, #12]
  6536. 8002bbe: 695a ldr r2, [r3, #20]
  6537. 8002bc0: 68fb ldr r3, [r7, #12]
  6538. 8002bc2: 699b ldr r3, [r3, #24]
  6539. 8002bc4: 1ad3 subs r3, r2, r3
  6540. 8002bc6: 61fb str r3, [r7, #28]
  6541. if (len > ep->maxpacket)
  6542. 8002bc8: 68fb ldr r3, [r7, #12]
  6543. 8002bca: 689b ldr r3, [r3, #8]
  6544. 8002bcc: 69fa ldr r2, [r7, #28]
  6545. 8002bce: 429a cmp r2, r3
  6546. 8002bd0: d902 bls.n 8002bd8 <PCD_WriteEmptyTxFifo+0x7a>
  6547. {
  6548. len = ep->maxpacket;
  6549. 8002bd2: 68fb ldr r3, [r7, #12]
  6550. 8002bd4: 689b ldr r3, [r3, #8]
  6551. 8002bd6: 61fb str r3, [r7, #28]
  6552. }
  6553. len32b = (len + 3U) / 4U;
  6554. 8002bd8: 69fb ldr r3, [r7, #28]
  6555. 8002bda: 3303 adds r3, #3
  6556. 8002bdc: 089b lsrs r3, r3, #2
  6557. 8002bde: 61bb str r3, [r7, #24]
  6558. (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
  6559. 8002be0: 68fb ldr r3, [r7, #12]
  6560. 8002be2: 68d9 ldr r1, [r3, #12]
  6561. 8002be4: 683b ldr r3, [r7, #0]
  6562. 8002be6: b2da uxtb r2, r3
  6563. 8002be8: 69fb ldr r3, [r7, #28]
  6564. 8002bea: b298 uxth r0, r3
  6565. (uint8_t)hpcd->Init.dma_enable);
  6566. 8002bec: 687b ldr r3, [r7, #4]
  6567. 8002bee: 691b ldr r3, [r3, #16]
  6568. (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
  6569. 8002bf0: b2db uxtb r3, r3
  6570. 8002bf2: 9300 str r3, [sp, #0]
  6571. 8002bf4: 4603 mov r3, r0
  6572. 8002bf6: 6978 ldr r0, [r7, #20]
  6573. 8002bf8: f004 f974 bl 8006ee4 <USB_WritePacket>
  6574. ep->xfer_buff += len;
  6575. 8002bfc: 68fb ldr r3, [r7, #12]
  6576. 8002bfe: 68da ldr r2, [r3, #12]
  6577. 8002c00: 69fb ldr r3, [r7, #28]
  6578. 8002c02: 441a add r2, r3
  6579. 8002c04: 68fb ldr r3, [r7, #12]
  6580. 8002c06: 60da str r2, [r3, #12]
  6581. ep->xfer_count += len;
  6582. 8002c08: 68fb ldr r3, [r7, #12]
  6583. 8002c0a: 699a ldr r2, [r3, #24]
  6584. 8002c0c: 69fb ldr r3, [r7, #28]
  6585. 8002c0e: 441a add r2, r3
  6586. 8002c10: 68fb ldr r3, [r7, #12]
  6587. 8002c12: 619a str r2, [r3, #24]
  6588. while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
  6589. 8002c14: 683b ldr r3, [r7, #0]
  6590. 8002c16: 015a lsls r2, r3, #5
  6591. 8002c18: 693b ldr r3, [r7, #16]
  6592. 8002c1a: 4413 add r3, r2
  6593. 8002c1c: f503 6310 add.w r3, r3, #2304 ; 0x900
  6594. 8002c20: 699b ldr r3, [r3, #24]
  6595. 8002c22: b29b uxth r3, r3
  6596. 8002c24: 69ba ldr r2, [r7, #24]
  6597. 8002c26: 429a cmp r2, r3
  6598. 8002c28: d809 bhi.n 8002c3e <PCD_WriteEmptyTxFifo+0xe0>
  6599. (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
  6600. 8002c2a: 68fb ldr r3, [r7, #12]
  6601. 8002c2c: 699a ldr r2, [r3, #24]
  6602. 8002c2e: 68fb ldr r3, [r7, #12]
  6603. 8002c30: 695b ldr r3, [r3, #20]
  6604. while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
  6605. 8002c32: 429a cmp r2, r3
  6606. 8002c34: d203 bcs.n 8002c3e <PCD_WriteEmptyTxFifo+0xe0>
  6607. (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
  6608. 8002c36: 68fb ldr r3, [r7, #12]
  6609. 8002c38: 695b ldr r3, [r3, #20]
  6610. 8002c3a: 2b00 cmp r3, #0
  6611. 8002c3c: d1be bne.n 8002bbc <PCD_WriteEmptyTxFifo+0x5e>
  6612. }
  6613. if (ep->xfer_len <= ep->xfer_count)
  6614. 8002c3e: 68fb ldr r3, [r7, #12]
  6615. 8002c40: 695a ldr r2, [r3, #20]
  6616. 8002c42: 68fb ldr r3, [r7, #12]
  6617. 8002c44: 699b ldr r3, [r3, #24]
  6618. 8002c46: 429a cmp r2, r3
  6619. 8002c48: d811 bhi.n 8002c6e <PCD_WriteEmptyTxFifo+0x110>
  6620. {
  6621. fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
  6622. 8002c4a: 683b ldr r3, [r7, #0]
  6623. 8002c4c: f003 030f and.w r3, r3, #15
  6624. 8002c50: 2201 movs r2, #1
  6625. 8002c52: fa02 f303 lsl.w r3, r2, r3
  6626. 8002c56: 60bb str r3, [r7, #8]
  6627. USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
  6628. 8002c58: 693b ldr r3, [r7, #16]
  6629. 8002c5a: f503 6300 add.w r3, r3, #2048 ; 0x800
  6630. 8002c5e: 6b5a ldr r2, [r3, #52] ; 0x34
  6631. 8002c60: 68bb ldr r3, [r7, #8]
  6632. 8002c62: 43db mvns r3, r3
  6633. 8002c64: 6939 ldr r1, [r7, #16]
  6634. 8002c66: f501 6100 add.w r1, r1, #2048 ; 0x800
  6635. 8002c6a: 4013 ands r3, r2
  6636. 8002c6c: 634b str r3, [r1, #52] ; 0x34
  6637. }
  6638. return HAL_OK;
  6639. 8002c6e: 2300 movs r3, #0
  6640. }
  6641. 8002c70: 4618 mov r0, r3
  6642. 8002c72: 3720 adds r7, #32
  6643. 8002c74: 46bd mov sp, r7
  6644. 8002c76: bd80 pop {r7, pc}
  6645. 08002c78 <PCD_EP_OutXfrComplete_int>:
  6646. * @param hpcd PCD handle
  6647. * @param epnum endpoint number
  6648. * @retval HAL status
  6649. */
  6650. static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
  6651. {
  6652. 8002c78: b580 push {r7, lr}
  6653. 8002c7a: b086 sub sp, #24
  6654. 8002c7c: af00 add r7, sp, #0
  6655. 8002c7e: 6078 str r0, [r7, #4]
  6656. 8002c80: 6039 str r1, [r7, #0]
  6657. USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
  6658. 8002c82: 687b ldr r3, [r7, #4]
  6659. 8002c84: 681b ldr r3, [r3, #0]
  6660. 8002c86: 617b str r3, [r7, #20]
  6661. uint32_t USBx_BASE = (uint32_t)USBx;
  6662. 8002c88: 697b ldr r3, [r7, #20]
  6663. 8002c8a: 613b str r3, [r7, #16]
  6664. uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
  6665. 8002c8c: 697b ldr r3, [r7, #20]
  6666. 8002c8e: 333c adds r3, #60 ; 0x3c
  6667. 8002c90: 3304 adds r3, #4
  6668. 8002c92: 681b ldr r3, [r3, #0]
  6669. 8002c94: 60fb str r3, [r7, #12]
  6670. uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
  6671. 8002c96: 683b ldr r3, [r7, #0]
  6672. 8002c98: 015a lsls r2, r3, #5
  6673. 8002c9a: 693b ldr r3, [r7, #16]
  6674. 8002c9c: 4413 add r3, r2
  6675. 8002c9e: f503 6330 add.w r3, r3, #2816 ; 0xb00
  6676. 8002ca2: 689b ldr r3, [r3, #8]
  6677. 8002ca4: 60bb str r3, [r7, #8]
  6678. if (hpcd->Init.dma_enable == 1U)
  6679. 8002ca6: 687b ldr r3, [r7, #4]
  6680. 8002ca8: 691b ldr r3, [r3, #16]
  6681. 8002caa: 2b01 cmp r3, #1
  6682. 8002cac: f040 80a0 bne.w 8002df0 <PCD_EP_OutXfrComplete_int+0x178>
  6683. {
  6684. if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
  6685. 8002cb0: 68bb ldr r3, [r7, #8]
  6686. 8002cb2: f003 0308 and.w r3, r3, #8
  6687. 8002cb6: 2b00 cmp r3, #0
  6688. 8002cb8: d015 beq.n 8002ce6 <PCD_EP_OutXfrComplete_int+0x6e>
  6689. {
  6690. /* StupPktRcvd = 1 this is a setup packet */
  6691. if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
  6692. 8002cba: 68fb ldr r3, [r7, #12]
  6693. 8002cbc: 4a72 ldr r2, [pc, #456] ; (8002e88 <PCD_EP_OutXfrComplete_int+0x210>)
  6694. 8002cbe: 4293 cmp r3, r2
  6695. 8002cc0: f240 80dd bls.w 8002e7e <PCD_EP_OutXfrComplete_int+0x206>
  6696. ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
  6697. 8002cc4: 68bb ldr r3, [r7, #8]
  6698. 8002cc6: f403 4300 and.w r3, r3, #32768 ; 0x8000
  6699. if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
  6700. 8002cca: 2b00 cmp r3, #0
  6701. 8002ccc: f000 80d7 beq.w 8002e7e <PCD_EP_OutXfrComplete_int+0x206>
  6702. {
  6703. CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
  6704. 8002cd0: 683b ldr r3, [r7, #0]
  6705. 8002cd2: 015a lsls r2, r3, #5
  6706. 8002cd4: 693b ldr r3, [r7, #16]
  6707. 8002cd6: 4413 add r3, r2
  6708. 8002cd8: f503 6330 add.w r3, r3, #2816 ; 0xb00
  6709. 8002cdc: 461a mov r2, r3
  6710. 8002cde: f44f 4300 mov.w r3, #32768 ; 0x8000
  6711. 8002ce2: 6093 str r3, [r2, #8]
  6712. 8002ce4: e0cb b.n 8002e7e <PCD_EP_OutXfrComplete_int+0x206>
  6713. }
  6714. }
  6715. else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
  6716. 8002ce6: 68bb ldr r3, [r7, #8]
  6717. 8002ce8: f003 0320 and.w r3, r3, #32
  6718. 8002cec: 2b00 cmp r3, #0
  6719. 8002cee: d009 beq.n 8002d04 <PCD_EP_OutXfrComplete_int+0x8c>
  6720. {
  6721. CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
  6722. 8002cf0: 683b ldr r3, [r7, #0]
  6723. 8002cf2: 015a lsls r2, r3, #5
  6724. 8002cf4: 693b ldr r3, [r7, #16]
  6725. 8002cf6: 4413 add r3, r2
  6726. 8002cf8: f503 6330 add.w r3, r3, #2816 ; 0xb00
  6727. 8002cfc: 461a mov r2, r3
  6728. 8002cfe: 2320 movs r3, #32
  6729. 8002d00: 6093 str r3, [r2, #8]
  6730. 8002d02: e0bc b.n 8002e7e <PCD_EP_OutXfrComplete_int+0x206>
  6731. }
  6732. else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
  6733. 8002d04: 68bb ldr r3, [r7, #8]
  6734. 8002d06: f003 0328 and.w r3, r3, #40 ; 0x28
  6735. 8002d0a: 2b00 cmp r3, #0
  6736. 8002d0c: f040 80b7 bne.w 8002e7e <PCD_EP_OutXfrComplete_int+0x206>
  6737. {
  6738. /* StupPktRcvd = 1 this is a setup packet */
  6739. if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
  6740. 8002d10: 68fb ldr r3, [r7, #12]
  6741. 8002d12: 4a5d ldr r2, [pc, #372] ; (8002e88 <PCD_EP_OutXfrComplete_int+0x210>)
  6742. 8002d14: 4293 cmp r3, r2
  6743. 8002d16: d90f bls.n 8002d38 <PCD_EP_OutXfrComplete_int+0xc0>
  6744. ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
  6745. 8002d18: 68bb ldr r3, [r7, #8]
  6746. 8002d1a: f403 4300 and.w r3, r3, #32768 ; 0x8000
  6747. if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
  6748. 8002d1e: 2b00 cmp r3, #0
  6749. 8002d20: d00a beq.n 8002d38 <PCD_EP_OutXfrComplete_int+0xc0>
  6750. {
  6751. CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
  6752. 8002d22: 683b ldr r3, [r7, #0]
  6753. 8002d24: 015a lsls r2, r3, #5
  6754. 8002d26: 693b ldr r3, [r7, #16]
  6755. 8002d28: 4413 add r3, r2
  6756. 8002d2a: f503 6330 add.w r3, r3, #2816 ; 0xb00
  6757. 8002d2e: 461a mov r2, r3
  6758. 8002d30: f44f 4300 mov.w r3, #32768 ; 0x8000
  6759. 8002d34: 6093 str r3, [r2, #8]
  6760. 8002d36: e0a2 b.n 8002e7e <PCD_EP_OutXfrComplete_int+0x206>
  6761. }
  6762. else
  6763. {
  6764. /* out data packet received over EP0 */
  6765. hpcd->OUT_ep[epnum].xfer_count =
  6766. hpcd->OUT_ep[epnum].maxpacket -
  6767. 8002d38: 6879 ldr r1, [r7, #4]
  6768. 8002d3a: 683a ldr r2, [r7, #0]
  6769. 8002d3c: 4613 mov r3, r2
  6770. 8002d3e: 00db lsls r3, r3, #3
  6771. 8002d40: 1a9b subs r3, r3, r2
  6772. 8002d42: 009b lsls r3, r3, #2
  6773. 8002d44: 440b add r3, r1
  6774. 8002d46: f503 7301 add.w r3, r3, #516 ; 0x204
  6775. 8002d4a: 681a ldr r2, [r3, #0]
  6776. (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
  6777. 8002d4c: 683b ldr r3, [r7, #0]
  6778. 8002d4e: 0159 lsls r1, r3, #5
  6779. 8002d50: 693b ldr r3, [r7, #16]
  6780. 8002d52: 440b add r3, r1
  6781. 8002d54: f503 6330 add.w r3, r3, #2816 ; 0xb00
  6782. 8002d58: 691b ldr r3, [r3, #16]
  6783. 8002d5a: f3c3 0312 ubfx r3, r3, #0, #19
  6784. hpcd->OUT_ep[epnum].maxpacket -
  6785. 8002d5e: 1ad1 subs r1, r2, r3
  6786. hpcd->OUT_ep[epnum].xfer_count =
  6787. 8002d60: 6878 ldr r0, [r7, #4]
  6788. 8002d62: 683a ldr r2, [r7, #0]
  6789. 8002d64: 4613 mov r3, r2
  6790. 8002d66: 00db lsls r3, r3, #3
  6791. 8002d68: 1a9b subs r3, r3, r2
  6792. 8002d6a: 009b lsls r3, r3, #2
  6793. 8002d6c: 4403 add r3, r0
  6794. 8002d6e: f503 7305 add.w r3, r3, #532 ; 0x214
  6795. 8002d72: 6019 str r1, [r3, #0]
  6796. hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
  6797. 8002d74: 6879 ldr r1, [r7, #4]
  6798. 8002d76: 683a ldr r2, [r7, #0]
  6799. 8002d78: 4613 mov r3, r2
  6800. 8002d7a: 00db lsls r3, r3, #3
  6801. 8002d7c: 1a9b subs r3, r3, r2
  6802. 8002d7e: 009b lsls r3, r3, #2
  6803. 8002d80: 440b add r3, r1
  6804. 8002d82: f503 7302 add.w r3, r3, #520 ; 0x208
  6805. 8002d86: 6819 ldr r1, [r3, #0]
  6806. 8002d88: 6878 ldr r0, [r7, #4]
  6807. 8002d8a: 683a ldr r2, [r7, #0]
  6808. 8002d8c: 4613 mov r3, r2
  6809. 8002d8e: 00db lsls r3, r3, #3
  6810. 8002d90: 1a9b subs r3, r3, r2
  6811. 8002d92: 009b lsls r3, r3, #2
  6812. 8002d94: 4403 add r3, r0
  6813. 8002d96: f503 7301 add.w r3, r3, #516 ; 0x204
  6814. 8002d9a: 681b ldr r3, [r3, #0]
  6815. 8002d9c: 4419 add r1, r3
  6816. 8002d9e: 6878 ldr r0, [r7, #4]
  6817. 8002da0: 683a ldr r2, [r7, #0]
  6818. 8002da2: 4613 mov r3, r2
  6819. 8002da4: 00db lsls r3, r3, #3
  6820. 8002da6: 1a9b subs r3, r3, r2
  6821. 8002da8: 009b lsls r3, r3, #2
  6822. 8002daa: 4403 add r3, r0
  6823. 8002dac: f503 7302 add.w r3, r3, #520 ; 0x208
  6824. 8002db0: 6019 str r1, [r3, #0]
  6825. if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
  6826. 8002db2: 683b ldr r3, [r7, #0]
  6827. 8002db4: 2b00 cmp r3, #0
  6828. 8002db6: d114 bne.n 8002de2 <PCD_EP_OutXfrComplete_int+0x16a>
  6829. 8002db8: 6879 ldr r1, [r7, #4]
  6830. 8002dba: 683a ldr r2, [r7, #0]
  6831. 8002dbc: 4613 mov r3, r2
  6832. 8002dbe: 00db lsls r3, r3, #3
  6833. 8002dc0: 1a9b subs r3, r3, r2
  6834. 8002dc2: 009b lsls r3, r3, #2
  6835. 8002dc4: 440b add r3, r1
  6836. 8002dc6: f503 7304 add.w r3, r3, #528 ; 0x210
  6837. 8002dca: 681b ldr r3, [r3, #0]
  6838. 8002dcc: 2b00 cmp r3, #0
  6839. 8002dce: d108 bne.n 8002de2 <PCD_EP_OutXfrComplete_int+0x16a>
  6840. {
  6841. /* this is ZLP, so prepare EP0 for next setup */
  6842. (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
  6843. 8002dd0: 687b ldr r3, [r7, #4]
  6844. 8002dd2: 6818 ldr r0, [r3, #0]
  6845. 8002dd4: 687b ldr r3, [r7, #4]
  6846. 8002dd6: f503 7371 add.w r3, r3, #964 ; 0x3c4
  6847. 8002dda: 461a mov r2, r3
  6848. 8002ddc: 2101 movs r1, #1
  6849. 8002dde: f004 fb19 bl 8007414 <USB_EP0_OutStart>
  6850. }
  6851. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  6852. hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
  6853. #else
  6854. HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
  6855. 8002de2: 683b ldr r3, [r7, #0]
  6856. 8002de4: b2db uxtb r3, r3
  6857. 8002de6: 4619 mov r1, r3
  6858. 8002de8: 6878 ldr r0, [r7, #4]
  6859. 8002dea: f006 fabf bl 800936c <HAL_PCD_DataOutStageCallback>
  6860. 8002dee: e046 b.n 8002e7e <PCD_EP_OutXfrComplete_int+0x206>
  6861. /* ... */
  6862. }
  6863. }
  6864. else
  6865. {
  6866. if (gSNPSiD == USB_OTG_CORE_ID_310A)
  6867. 8002df0: 68fb ldr r3, [r7, #12]
  6868. 8002df2: 4a26 ldr r2, [pc, #152] ; (8002e8c <PCD_EP_OutXfrComplete_int+0x214>)
  6869. 8002df4: 4293 cmp r3, r2
  6870. 8002df6: d124 bne.n 8002e42 <PCD_EP_OutXfrComplete_int+0x1ca>
  6871. {
  6872. /* StupPktRcvd = 1 this is a setup packet */
  6873. if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
  6874. 8002df8: 68bb ldr r3, [r7, #8]
  6875. 8002dfa: f403 4300 and.w r3, r3, #32768 ; 0x8000
  6876. 8002dfe: 2b00 cmp r3, #0
  6877. 8002e00: d00a beq.n 8002e18 <PCD_EP_OutXfrComplete_int+0x1a0>
  6878. {
  6879. CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
  6880. 8002e02: 683b ldr r3, [r7, #0]
  6881. 8002e04: 015a lsls r2, r3, #5
  6882. 8002e06: 693b ldr r3, [r7, #16]
  6883. 8002e08: 4413 add r3, r2
  6884. 8002e0a: f503 6330 add.w r3, r3, #2816 ; 0xb00
  6885. 8002e0e: 461a mov r2, r3
  6886. 8002e10: f44f 4300 mov.w r3, #32768 ; 0x8000
  6887. 8002e14: 6093 str r3, [r2, #8]
  6888. 8002e16: e032 b.n 8002e7e <PCD_EP_OutXfrComplete_int+0x206>
  6889. }
  6890. else
  6891. {
  6892. if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
  6893. 8002e18: 68bb ldr r3, [r7, #8]
  6894. 8002e1a: f003 0320 and.w r3, r3, #32
  6895. 8002e1e: 2b00 cmp r3, #0
  6896. 8002e20: d008 beq.n 8002e34 <PCD_EP_OutXfrComplete_int+0x1bc>
  6897. {
  6898. CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
  6899. 8002e22: 683b ldr r3, [r7, #0]
  6900. 8002e24: 015a lsls r2, r3, #5
  6901. 8002e26: 693b ldr r3, [r7, #16]
  6902. 8002e28: 4413 add r3, r2
  6903. 8002e2a: f503 6330 add.w r3, r3, #2816 ; 0xb00
  6904. 8002e2e: 461a mov r2, r3
  6905. 8002e30: 2320 movs r3, #32
  6906. 8002e32: 6093 str r3, [r2, #8]
  6907. }
  6908. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  6909. hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
  6910. #else
  6911. HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
  6912. 8002e34: 683b ldr r3, [r7, #0]
  6913. 8002e36: b2db uxtb r3, r3
  6914. 8002e38: 4619 mov r1, r3
  6915. 8002e3a: 6878 ldr r0, [r7, #4]
  6916. 8002e3c: f006 fa96 bl 800936c <HAL_PCD_DataOutStageCallback>
  6917. 8002e40: e01d b.n 8002e7e <PCD_EP_OutXfrComplete_int+0x206>
  6918. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  6919. }
  6920. }
  6921. else
  6922. {
  6923. if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
  6924. 8002e42: 683b ldr r3, [r7, #0]
  6925. 8002e44: 2b00 cmp r3, #0
  6926. 8002e46: d114 bne.n 8002e72 <PCD_EP_OutXfrComplete_int+0x1fa>
  6927. 8002e48: 6879 ldr r1, [r7, #4]
  6928. 8002e4a: 683a ldr r2, [r7, #0]
  6929. 8002e4c: 4613 mov r3, r2
  6930. 8002e4e: 00db lsls r3, r3, #3
  6931. 8002e50: 1a9b subs r3, r3, r2
  6932. 8002e52: 009b lsls r3, r3, #2
  6933. 8002e54: 440b add r3, r1
  6934. 8002e56: f503 7304 add.w r3, r3, #528 ; 0x210
  6935. 8002e5a: 681b ldr r3, [r3, #0]
  6936. 8002e5c: 2b00 cmp r3, #0
  6937. 8002e5e: d108 bne.n 8002e72 <PCD_EP_OutXfrComplete_int+0x1fa>
  6938. {
  6939. /* this is ZLP, so prepare EP0 for next setup */
  6940. (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
  6941. 8002e60: 687b ldr r3, [r7, #4]
  6942. 8002e62: 6818 ldr r0, [r3, #0]
  6943. 8002e64: 687b ldr r3, [r7, #4]
  6944. 8002e66: f503 7371 add.w r3, r3, #964 ; 0x3c4
  6945. 8002e6a: 461a mov r2, r3
  6946. 8002e6c: 2100 movs r1, #0
  6947. 8002e6e: f004 fad1 bl 8007414 <USB_EP0_OutStart>
  6948. }
  6949. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  6950. hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
  6951. #else
  6952. HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
  6953. 8002e72: 683b ldr r3, [r7, #0]
  6954. 8002e74: b2db uxtb r3, r3
  6955. 8002e76: 4619 mov r1, r3
  6956. 8002e78: 6878 ldr r0, [r7, #4]
  6957. 8002e7a: f006 fa77 bl 800936c <HAL_PCD_DataOutStageCallback>
  6958. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  6959. }
  6960. }
  6961. return HAL_OK;
  6962. 8002e7e: 2300 movs r3, #0
  6963. }
  6964. 8002e80: 4618 mov r0, r3
  6965. 8002e82: 3718 adds r7, #24
  6966. 8002e84: 46bd mov sp, r7
  6967. 8002e86: bd80 pop {r7, pc}
  6968. 8002e88: 4f54300a .word 0x4f54300a
  6969. 8002e8c: 4f54310a .word 0x4f54310a
  6970. 08002e90 <PCD_EP_OutSetupPacket_int>:
  6971. * @param hpcd PCD handle
  6972. * @param epnum endpoint number
  6973. * @retval HAL status
  6974. */
  6975. static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
  6976. {
  6977. 8002e90: b580 push {r7, lr}
  6978. 8002e92: b086 sub sp, #24
  6979. 8002e94: af00 add r7, sp, #0
  6980. 8002e96: 6078 str r0, [r7, #4]
  6981. 8002e98: 6039 str r1, [r7, #0]
  6982. USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
  6983. 8002e9a: 687b ldr r3, [r7, #4]
  6984. 8002e9c: 681b ldr r3, [r3, #0]
  6985. 8002e9e: 617b str r3, [r7, #20]
  6986. uint32_t USBx_BASE = (uint32_t)USBx;
  6987. 8002ea0: 697b ldr r3, [r7, #20]
  6988. 8002ea2: 613b str r3, [r7, #16]
  6989. uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
  6990. 8002ea4: 697b ldr r3, [r7, #20]
  6991. 8002ea6: 333c adds r3, #60 ; 0x3c
  6992. 8002ea8: 3304 adds r3, #4
  6993. 8002eaa: 681b ldr r3, [r3, #0]
  6994. 8002eac: 60fb str r3, [r7, #12]
  6995. uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
  6996. 8002eae: 683b ldr r3, [r7, #0]
  6997. 8002eb0: 015a lsls r2, r3, #5
  6998. 8002eb2: 693b ldr r3, [r7, #16]
  6999. 8002eb4: 4413 add r3, r2
  7000. 8002eb6: f503 6330 add.w r3, r3, #2816 ; 0xb00
  7001. 8002eba: 689b ldr r3, [r3, #8]
  7002. 8002ebc: 60bb str r3, [r7, #8]
  7003. if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
  7004. 8002ebe: 68fb ldr r3, [r7, #12]
  7005. 8002ec0: 4a15 ldr r2, [pc, #84] ; (8002f18 <PCD_EP_OutSetupPacket_int+0x88>)
  7006. 8002ec2: 4293 cmp r3, r2
  7007. 8002ec4: d90e bls.n 8002ee4 <PCD_EP_OutSetupPacket_int+0x54>
  7008. ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
  7009. 8002ec6: 68bb ldr r3, [r7, #8]
  7010. 8002ec8: f403 4300 and.w r3, r3, #32768 ; 0x8000
  7011. if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
  7012. 8002ecc: 2b00 cmp r3, #0
  7013. 8002ece: d009 beq.n 8002ee4 <PCD_EP_OutSetupPacket_int+0x54>
  7014. {
  7015. CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
  7016. 8002ed0: 683b ldr r3, [r7, #0]
  7017. 8002ed2: 015a lsls r2, r3, #5
  7018. 8002ed4: 693b ldr r3, [r7, #16]
  7019. 8002ed6: 4413 add r3, r2
  7020. 8002ed8: f503 6330 add.w r3, r3, #2816 ; 0xb00
  7021. 8002edc: 461a mov r2, r3
  7022. 8002ede: f44f 4300 mov.w r3, #32768 ; 0x8000
  7023. 8002ee2: 6093 str r3, [r2, #8]
  7024. /* Inform the upper layer that a setup packet is available */
  7025. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  7026. hpcd->SetupStageCallback(hpcd);
  7027. #else
  7028. HAL_PCD_SetupStageCallback(hpcd);
  7029. 8002ee4: 6878 ldr r0, [r7, #4]
  7030. 8002ee6: f006 fa2f bl 8009348 <HAL_PCD_SetupStageCallback>
  7031. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  7032. if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
  7033. 8002eea: 68fb ldr r3, [r7, #12]
  7034. 8002eec: 4a0a ldr r2, [pc, #40] ; (8002f18 <PCD_EP_OutSetupPacket_int+0x88>)
  7035. 8002eee: 4293 cmp r3, r2
  7036. 8002ef0: d90c bls.n 8002f0c <PCD_EP_OutSetupPacket_int+0x7c>
  7037. 8002ef2: 687b ldr r3, [r7, #4]
  7038. 8002ef4: 691b ldr r3, [r3, #16]
  7039. 8002ef6: 2b01 cmp r3, #1
  7040. 8002ef8: d108 bne.n 8002f0c <PCD_EP_OutSetupPacket_int+0x7c>
  7041. {
  7042. (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
  7043. 8002efa: 687b ldr r3, [r7, #4]
  7044. 8002efc: 6818 ldr r0, [r3, #0]
  7045. 8002efe: 687b ldr r3, [r7, #4]
  7046. 8002f00: f503 7371 add.w r3, r3, #964 ; 0x3c4
  7047. 8002f04: 461a mov r2, r3
  7048. 8002f06: 2101 movs r1, #1
  7049. 8002f08: f004 fa84 bl 8007414 <USB_EP0_OutStart>
  7050. }
  7051. return HAL_OK;
  7052. 8002f0c: 2300 movs r3, #0
  7053. }
  7054. 8002f0e: 4618 mov r0, r3
  7055. 8002f10: 3718 adds r7, #24
  7056. 8002f12: 46bd mov sp, r7
  7057. 8002f14: bd80 pop {r7, pc}
  7058. 8002f16: bf00 nop
  7059. 8002f18: 4f54300a .word 0x4f54300a
  7060. 08002f1c <HAL_PCDEx_SetTxFiFo>:
  7061. * @param fifo The number of Tx fifo
  7062. * @param size Fifo size
  7063. * @retval HAL status
  7064. */
  7065. HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
  7066. {
  7067. 8002f1c: b480 push {r7}
  7068. 8002f1e: b085 sub sp, #20
  7069. 8002f20: af00 add r7, sp, #0
  7070. 8002f22: 6078 str r0, [r7, #4]
  7071. 8002f24: 460b mov r3, r1
  7072. 8002f26: 70fb strb r3, [r7, #3]
  7073. 8002f28: 4613 mov r3, r2
  7074. 8002f2a: 803b strh r3, [r7, #0]
  7075. --> Txn should be configured with the minimum space of 16 words
  7076. The FIFO is used optimally when used TxFIFOs are allocated in the top
  7077. of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
  7078. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
  7079. Tx_Offset = hpcd->Instance->GRXFSIZ;
  7080. 8002f2c: 687b ldr r3, [r7, #4]
  7081. 8002f2e: 681b ldr r3, [r3, #0]
  7082. 8002f30: 6a5b ldr r3, [r3, #36] ; 0x24
  7083. 8002f32: 60bb str r3, [r7, #8]
  7084. if (fifo == 0U)
  7085. 8002f34: 78fb ldrb r3, [r7, #3]
  7086. 8002f36: 2b00 cmp r3, #0
  7087. 8002f38: d107 bne.n 8002f4a <HAL_PCDEx_SetTxFiFo+0x2e>
  7088. {
  7089. hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
  7090. 8002f3a: 883b ldrh r3, [r7, #0]
  7091. 8002f3c: 0419 lsls r1, r3, #16
  7092. 8002f3e: 687b ldr r3, [r7, #4]
  7093. 8002f40: 681b ldr r3, [r3, #0]
  7094. 8002f42: 68ba ldr r2, [r7, #8]
  7095. 8002f44: 430a orrs r2, r1
  7096. 8002f46: 629a str r2, [r3, #40] ; 0x28
  7097. 8002f48: e028 b.n 8002f9c <HAL_PCDEx_SetTxFiFo+0x80>
  7098. }
  7099. else
  7100. {
  7101. Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
  7102. 8002f4a: 687b ldr r3, [r7, #4]
  7103. 8002f4c: 681b ldr r3, [r3, #0]
  7104. 8002f4e: 6a9b ldr r3, [r3, #40] ; 0x28
  7105. 8002f50: 0c1b lsrs r3, r3, #16
  7106. 8002f52: 68ba ldr r2, [r7, #8]
  7107. 8002f54: 4413 add r3, r2
  7108. 8002f56: 60bb str r3, [r7, #8]
  7109. for (i = 0U; i < (fifo - 1U); i++)
  7110. 8002f58: 2300 movs r3, #0
  7111. 8002f5a: 73fb strb r3, [r7, #15]
  7112. 8002f5c: e00d b.n 8002f7a <HAL_PCDEx_SetTxFiFo+0x5e>
  7113. {
  7114. Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
  7115. 8002f5e: 687b ldr r3, [r7, #4]
  7116. 8002f60: 681a ldr r2, [r3, #0]
  7117. 8002f62: 7bfb ldrb r3, [r7, #15]
  7118. 8002f64: 3340 adds r3, #64 ; 0x40
  7119. 8002f66: 009b lsls r3, r3, #2
  7120. 8002f68: 4413 add r3, r2
  7121. 8002f6a: 685b ldr r3, [r3, #4]
  7122. 8002f6c: 0c1b lsrs r3, r3, #16
  7123. 8002f6e: 68ba ldr r2, [r7, #8]
  7124. 8002f70: 4413 add r3, r2
  7125. 8002f72: 60bb str r3, [r7, #8]
  7126. for (i = 0U; i < (fifo - 1U); i++)
  7127. 8002f74: 7bfb ldrb r3, [r7, #15]
  7128. 8002f76: 3301 adds r3, #1
  7129. 8002f78: 73fb strb r3, [r7, #15]
  7130. 8002f7a: 7bfa ldrb r2, [r7, #15]
  7131. 8002f7c: 78fb ldrb r3, [r7, #3]
  7132. 8002f7e: 3b01 subs r3, #1
  7133. 8002f80: 429a cmp r2, r3
  7134. 8002f82: d3ec bcc.n 8002f5e <HAL_PCDEx_SetTxFiFo+0x42>
  7135. }
  7136. /* Multiply Tx_Size by 2 to get higher performance */
  7137. hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
  7138. 8002f84: 883b ldrh r3, [r7, #0]
  7139. 8002f86: 0418 lsls r0, r3, #16
  7140. 8002f88: 687b ldr r3, [r7, #4]
  7141. 8002f8a: 6819 ldr r1, [r3, #0]
  7142. 8002f8c: 78fb ldrb r3, [r7, #3]
  7143. 8002f8e: 3b01 subs r3, #1
  7144. 8002f90: 68ba ldr r2, [r7, #8]
  7145. 8002f92: 4302 orrs r2, r0
  7146. 8002f94: 3340 adds r3, #64 ; 0x40
  7147. 8002f96: 009b lsls r3, r3, #2
  7148. 8002f98: 440b add r3, r1
  7149. 8002f9a: 605a str r2, [r3, #4]
  7150. }
  7151. return HAL_OK;
  7152. 8002f9c: 2300 movs r3, #0
  7153. }
  7154. 8002f9e: 4618 mov r0, r3
  7155. 8002fa0: 3714 adds r7, #20
  7156. 8002fa2: 46bd mov sp, r7
  7157. 8002fa4: f85d 7b04 ldr.w r7, [sp], #4
  7158. 8002fa8: 4770 bx lr
  7159. 08002faa <HAL_PCDEx_SetRxFiFo>:
  7160. * @param hpcd PCD handle
  7161. * @param size Size of Rx fifo
  7162. * @retval HAL status
  7163. */
  7164. HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
  7165. {
  7166. 8002faa: b480 push {r7}
  7167. 8002fac: b083 sub sp, #12
  7168. 8002fae: af00 add r7, sp, #0
  7169. 8002fb0: 6078 str r0, [r7, #4]
  7170. 8002fb2: 460b mov r3, r1
  7171. 8002fb4: 807b strh r3, [r7, #2]
  7172. hpcd->Instance->GRXFSIZ = size;
  7173. 8002fb6: 687b ldr r3, [r7, #4]
  7174. 8002fb8: 681b ldr r3, [r3, #0]
  7175. 8002fba: 887a ldrh r2, [r7, #2]
  7176. 8002fbc: 625a str r2, [r3, #36] ; 0x24
  7177. return HAL_OK;
  7178. 8002fbe: 2300 movs r3, #0
  7179. }
  7180. 8002fc0: 4618 mov r0, r3
  7181. 8002fc2: 370c adds r7, #12
  7182. 8002fc4: 46bd mov sp, r7
  7183. 8002fc6: f85d 7b04 ldr.w r7, [sp], #4
  7184. 8002fca: 4770 bx lr
  7185. 08002fcc <HAL_PCDEx_ActivateLPM>:
  7186. * @brief Activate LPM feature.
  7187. * @param hpcd PCD handle
  7188. * @retval HAL status
  7189. */
  7190. HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
  7191. {
  7192. 8002fcc: b480 push {r7}
  7193. 8002fce: b085 sub sp, #20
  7194. 8002fd0: af00 add r7, sp, #0
  7195. 8002fd2: 6078 str r0, [r7, #4]
  7196. USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
  7197. 8002fd4: 687b ldr r3, [r7, #4]
  7198. 8002fd6: 681b ldr r3, [r3, #0]
  7199. 8002fd8: 60fb str r3, [r7, #12]
  7200. hpcd->lpm_active = 1U;
  7201. 8002fda: 687b ldr r3, [r7, #4]
  7202. 8002fdc: 2201 movs r2, #1
  7203. 8002fde: f8c3 23fc str.w r2, [r3, #1020] ; 0x3fc
  7204. hpcd->LPM_State = LPM_L0;
  7205. 8002fe2: 687b ldr r3, [r7, #4]
  7206. 8002fe4: 2200 movs r2, #0
  7207. 8002fe6: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4
  7208. USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
  7209. 8002fea: 68fb ldr r3, [r7, #12]
  7210. 8002fec: 699b ldr r3, [r3, #24]
  7211. 8002fee: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000
  7212. 8002ff2: 68fb ldr r3, [r7, #12]
  7213. 8002ff4: 619a str r2, [r3, #24]
  7214. USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
  7215. 8002ff6: 68fb ldr r3, [r7, #12]
  7216. 8002ff8: 6d5a ldr r2, [r3, #84] ; 0x54
  7217. 8002ffa: 4b05 ldr r3, [pc, #20] ; (8003010 <HAL_PCDEx_ActivateLPM+0x44>)
  7218. 8002ffc: 4313 orrs r3, r2
  7219. 8002ffe: 68fa ldr r2, [r7, #12]
  7220. 8003000: 6553 str r3, [r2, #84] ; 0x54
  7221. return HAL_OK;
  7222. 8003002: 2300 movs r3, #0
  7223. }
  7224. 8003004: 4618 mov r0, r3
  7225. 8003006: 3714 adds r7, #20
  7226. 8003008: 46bd mov sp, r7
  7227. 800300a: f85d 7b04 ldr.w r7, [sp], #4
  7228. 800300e: 4770 bx lr
  7229. 8003010: 10000003 .word 0x10000003
  7230. 08003014 <HAL_PCDEx_LPM_Callback>:
  7231. * @param hpcd PCD handle
  7232. * @param msg LPM message
  7233. * @retval HAL status
  7234. */
  7235. __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
  7236. {
  7237. 8003014: b480 push {r7}
  7238. 8003016: b083 sub sp, #12
  7239. 8003018: af00 add r7, sp, #0
  7240. 800301a: 6078 str r0, [r7, #4]
  7241. 800301c: 460b mov r3, r1
  7242. 800301e: 70fb strb r3, [r7, #3]
  7243. UNUSED(msg);
  7244. /* NOTE : This function should not be modified, when the callback is needed,
  7245. the HAL_PCDEx_LPM_Callback could be implemented in the user file
  7246. */
  7247. }
  7248. 8003020: bf00 nop
  7249. 8003022: 370c adds r7, #12
  7250. 8003024: 46bd mov sp, r7
  7251. 8003026: f85d 7b04 ldr.w r7, [sp], #4
  7252. 800302a: 4770 bx lr
  7253. 0800302c <HAL_PWREx_ConfigSupply>:
  7254. * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
  7255. * regulator.
  7256. * @retval HAL status.
  7257. */
  7258. HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
  7259. {
  7260. 800302c: b580 push {r7, lr}
  7261. 800302e: b084 sub sp, #16
  7262. 8003030: af00 add r7, sp, #0
  7263. 8003032: 6078 str r0, [r7, #4]
  7264. /* Check the parameters */
  7265. assert_param (IS_PWR_SUPPLY (SupplySource));
  7266. /* Check if supply source was configured */
  7267. #if defined (PWR_FLAG_SCUEN)
  7268. if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
  7269. 8003034: 4b19 ldr r3, [pc, #100] ; (800309c <HAL_PWREx_ConfigSupply+0x70>)
  7270. 8003036: 68db ldr r3, [r3, #12]
  7271. 8003038: f003 0304 and.w r3, r3, #4
  7272. 800303c: 2b04 cmp r3, #4
  7273. 800303e: d00a beq.n 8003056 <HAL_PWREx_ConfigSupply+0x2a>
  7274. #else
  7275. if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
  7276. #endif /* defined (PWR_FLAG_SCUEN) */
  7277. {
  7278. /* Check supply configuration */
  7279. if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
  7280. 8003040: 4b16 ldr r3, [pc, #88] ; (800309c <HAL_PWREx_ConfigSupply+0x70>)
  7281. 8003042: 68db ldr r3, [r3, #12]
  7282. 8003044: f003 0307 and.w r3, r3, #7
  7283. 8003048: 687a ldr r2, [r7, #4]
  7284. 800304a: 429a cmp r2, r3
  7285. 800304c: d001 beq.n 8003052 <HAL_PWREx_ConfigSupply+0x26>
  7286. {
  7287. /* Supply configuration update locked, can't apply a new supply config */
  7288. return HAL_ERROR;
  7289. 800304e: 2301 movs r3, #1
  7290. 8003050: e01f b.n 8003092 <HAL_PWREx_ConfigSupply+0x66>
  7291. else
  7292. {
  7293. /* Supply configuration update locked, but new supply configuration
  7294. matches with old supply configuration : nothing to do
  7295. */
  7296. return HAL_OK;
  7297. 8003052: 2300 movs r3, #0
  7298. 8003054: e01d b.n 8003092 <HAL_PWREx_ConfigSupply+0x66>
  7299. }
  7300. }
  7301. /* Set the power supply configuration */
  7302. MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
  7303. 8003056: 4b11 ldr r3, [pc, #68] ; (800309c <HAL_PWREx_ConfigSupply+0x70>)
  7304. 8003058: 68db ldr r3, [r3, #12]
  7305. 800305a: f023 0207 bic.w r2, r3, #7
  7306. 800305e: 490f ldr r1, [pc, #60] ; (800309c <HAL_PWREx_ConfigSupply+0x70>)
  7307. 8003060: 687b ldr r3, [r7, #4]
  7308. 8003062: 4313 orrs r3, r2
  7309. 8003064: 60cb str r3, [r1, #12]
  7310. /* Get tick */
  7311. tickstart = HAL_GetTick ();
  7312. 8003066: f7fe faf7 bl 8001658 <HAL_GetTick>
  7313. 800306a: 60f8 str r0, [r7, #12]
  7314. /* Wait till voltage level flag is set */
  7315. while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
  7316. 800306c: e009 b.n 8003082 <HAL_PWREx_ConfigSupply+0x56>
  7317. {
  7318. if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
  7319. 800306e: f7fe faf3 bl 8001658 <HAL_GetTick>
  7320. 8003072: 4602 mov r2, r0
  7321. 8003074: 68fb ldr r3, [r7, #12]
  7322. 8003076: 1ad3 subs r3, r2, r3
  7323. 8003078: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
  7324. 800307c: d901 bls.n 8003082 <HAL_PWREx_ConfigSupply+0x56>
  7325. {
  7326. return HAL_ERROR;
  7327. 800307e: 2301 movs r3, #1
  7328. 8003080: e007 b.n 8003092 <HAL_PWREx_ConfigSupply+0x66>
  7329. while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
  7330. 8003082: 4b06 ldr r3, [pc, #24] ; (800309c <HAL_PWREx_ConfigSupply+0x70>)
  7331. 8003084: 685b ldr r3, [r3, #4]
  7332. 8003086: f403 5300 and.w r3, r3, #8192 ; 0x2000
  7333. 800308a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
  7334. 800308e: d1ee bne.n 800306e <HAL_PWREx_ConfigSupply+0x42>
  7335. }
  7336. }
  7337. }
  7338. #endif /* defined (SMPS) */
  7339. return HAL_OK;
  7340. 8003090: 2300 movs r3, #0
  7341. }
  7342. 8003092: 4618 mov r0, r3
  7343. 8003094: 3710 adds r7, #16
  7344. 8003096: 46bd mov sp, r7
  7345. 8003098: bd80 pop {r7, pc}
  7346. 800309a: bf00 nop
  7347. 800309c: 58024800 .word 0x58024800
  7348. 080030a0 <HAL_PWREx_EnableUSBVoltageDetector>:
  7349. /**
  7350. * @brief Enable the USB voltage level detector.
  7351. * @retval None.
  7352. */
  7353. void HAL_PWREx_EnableUSBVoltageDetector (void)
  7354. {
  7355. 80030a0: b480 push {r7}
  7356. 80030a2: af00 add r7, sp, #0
  7357. /* Enable the USB voltage detector */
  7358. SET_BIT (PWR->CR3, PWR_CR3_USB33DEN);
  7359. 80030a4: 4b05 ldr r3, [pc, #20] ; (80030bc <HAL_PWREx_EnableUSBVoltageDetector+0x1c>)
  7360. 80030a6: 68db ldr r3, [r3, #12]
  7361. 80030a8: 4a04 ldr r2, [pc, #16] ; (80030bc <HAL_PWREx_EnableUSBVoltageDetector+0x1c>)
  7362. 80030aa: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
  7363. 80030ae: 60d3 str r3, [r2, #12]
  7364. }
  7365. 80030b0: bf00 nop
  7366. 80030b2: 46bd mov sp, r7
  7367. 80030b4: f85d 7b04 ldr.w r7, [sp], #4
  7368. 80030b8: 4770 bx lr
  7369. 80030ba: bf00 nop
  7370. 80030bc: 58024800 .word 0x58024800
  7371. 080030c0 <HAL_RCC_OscConfig>:
  7372. * supported by this function. User should request a transition to HSE Off
  7373. * first and then HSE On or HSE Bypass.
  7374. * @retval HAL status
  7375. */
  7376. __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
  7377. {
  7378. 80030c0: b580 push {r7, lr}
  7379. 80030c2: b08c sub sp, #48 ; 0x30
  7380. 80030c4: af00 add r7, sp, #0
  7381. 80030c6: 6078 str r0, [r7, #4]
  7382. uint32_t tickstart;
  7383. uint32_t temp1_pllckcfg, temp2_pllckcfg;
  7384. /* Check Null pointer */
  7385. if(RCC_OscInitStruct == NULL)
  7386. 80030c8: 687b ldr r3, [r7, #4]
  7387. 80030ca: 2b00 cmp r3, #0
  7388. 80030cc: d101 bne.n 80030d2 <HAL_RCC_OscConfig+0x12>
  7389. {
  7390. return HAL_ERROR;
  7391. 80030ce: 2301 movs r3, #1
  7392. 80030d0: e397 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7393. }
  7394. /* Check the parameters */
  7395. assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  7396. /*------------------------------- HSE Configuration ------------------------*/
  7397. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
  7398. 80030d2: 687b ldr r3, [r7, #4]
  7399. 80030d4: 681b ldr r3, [r3, #0]
  7400. 80030d6: f003 0301 and.w r3, r3, #1
  7401. 80030da: 2b00 cmp r3, #0
  7402. 80030dc: f000 8087 beq.w 80031ee <HAL_RCC_OscConfig+0x12e>
  7403. {
  7404. /* Check the parameters */
  7405. assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
  7406. const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
  7407. 80030e0: 4b9e ldr r3, [pc, #632] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7408. 80030e2: 691b ldr r3, [r3, #16]
  7409. 80030e4: f003 0338 and.w r3, r3, #56 ; 0x38
  7410. 80030e8: 62fb str r3, [r7, #44] ; 0x2c
  7411. const uint32_t temp_pllckselr = RCC->PLLCKSELR;
  7412. 80030ea: 4b9c ldr r3, [pc, #624] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7413. 80030ec: 6a9b ldr r3, [r3, #40] ; 0x28
  7414. 80030ee: 62bb str r3, [r7, #40] ; 0x28
  7415. /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
  7416. if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
  7417. 80030f0: 6afb ldr r3, [r7, #44] ; 0x2c
  7418. 80030f2: 2b10 cmp r3, #16
  7419. 80030f4: d007 beq.n 8003106 <HAL_RCC_OscConfig+0x46>
  7420. 80030f6: 6afb ldr r3, [r7, #44] ; 0x2c
  7421. 80030f8: 2b18 cmp r3, #24
  7422. 80030fa: d110 bne.n 800311e <HAL_RCC_OscConfig+0x5e>
  7423. 80030fc: 6abb ldr r3, [r7, #40] ; 0x28
  7424. 80030fe: f003 0303 and.w r3, r3, #3
  7425. 8003102: 2b02 cmp r3, #2
  7426. 8003104: d10b bne.n 800311e <HAL_RCC_OscConfig+0x5e>
  7427. {
  7428. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
  7429. 8003106: 4b95 ldr r3, [pc, #596] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7430. 8003108: 681b ldr r3, [r3, #0]
  7431. 800310a: f403 3300 and.w r3, r3, #131072 ; 0x20000
  7432. 800310e: 2b00 cmp r3, #0
  7433. 8003110: d06c beq.n 80031ec <HAL_RCC_OscConfig+0x12c>
  7434. 8003112: 687b ldr r3, [r7, #4]
  7435. 8003114: 685b ldr r3, [r3, #4]
  7436. 8003116: 2b00 cmp r3, #0
  7437. 8003118: d168 bne.n 80031ec <HAL_RCC_OscConfig+0x12c>
  7438. {
  7439. return HAL_ERROR;
  7440. 800311a: 2301 movs r3, #1
  7441. 800311c: e371 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7442. }
  7443. }
  7444. else
  7445. {
  7446. /* Set the new HSE configuration ---------------------------------------*/
  7447. __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  7448. 800311e: 687b ldr r3, [r7, #4]
  7449. 8003120: 685b ldr r3, [r3, #4]
  7450. 8003122: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
  7451. 8003126: d106 bne.n 8003136 <HAL_RCC_OscConfig+0x76>
  7452. 8003128: 4b8c ldr r3, [pc, #560] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7453. 800312a: 681b ldr r3, [r3, #0]
  7454. 800312c: 4a8b ldr r2, [pc, #556] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7455. 800312e: f443 3380 orr.w r3, r3, #65536 ; 0x10000
  7456. 8003132: 6013 str r3, [r2, #0]
  7457. 8003134: e02e b.n 8003194 <HAL_RCC_OscConfig+0xd4>
  7458. 8003136: 687b ldr r3, [r7, #4]
  7459. 8003138: 685b ldr r3, [r3, #4]
  7460. 800313a: 2b00 cmp r3, #0
  7461. 800313c: d10c bne.n 8003158 <HAL_RCC_OscConfig+0x98>
  7462. 800313e: 4b87 ldr r3, [pc, #540] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7463. 8003140: 681b ldr r3, [r3, #0]
  7464. 8003142: 4a86 ldr r2, [pc, #536] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7465. 8003144: f423 3380 bic.w r3, r3, #65536 ; 0x10000
  7466. 8003148: 6013 str r3, [r2, #0]
  7467. 800314a: 4b84 ldr r3, [pc, #528] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7468. 800314c: 681b ldr r3, [r3, #0]
  7469. 800314e: 4a83 ldr r2, [pc, #524] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7470. 8003150: f423 2380 bic.w r3, r3, #262144 ; 0x40000
  7471. 8003154: 6013 str r3, [r2, #0]
  7472. 8003156: e01d b.n 8003194 <HAL_RCC_OscConfig+0xd4>
  7473. 8003158: 687b ldr r3, [r7, #4]
  7474. 800315a: 685b ldr r3, [r3, #4]
  7475. 800315c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
  7476. 8003160: d10c bne.n 800317c <HAL_RCC_OscConfig+0xbc>
  7477. 8003162: 4b7e ldr r3, [pc, #504] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7478. 8003164: 681b ldr r3, [r3, #0]
  7479. 8003166: 4a7d ldr r2, [pc, #500] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7480. 8003168: f443 2380 orr.w r3, r3, #262144 ; 0x40000
  7481. 800316c: 6013 str r3, [r2, #0]
  7482. 800316e: 4b7b ldr r3, [pc, #492] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7483. 8003170: 681b ldr r3, [r3, #0]
  7484. 8003172: 4a7a ldr r2, [pc, #488] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7485. 8003174: f443 3380 orr.w r3, r3, #65536 ; 0x10000
  7486. 8003178: 6013 str r3, [r2, #0]
  7487. 800317a: e00b b.n 8003194 <HAL_RCC_OscConfig+0xd4>
  7488. 800317c: 4b77 ldr r3, [pc, #476] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7489. 800317e: 681b ldr r3, [r3, #0]
  7490. 8003180: 4a76 ldr r2, [pc, #472] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7491. 8003182: f423 3380 bic.w r3, r3, #65536 ; 0x10000
  7492. 8003186: 6013 str r3, [r2, #0]
  7493. 8003188: 4b74 ldr r3, [pc, #464] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7494. 800318a: 681b ldr r3, [r3, #0]
  7495. 800318c: 4a73 ldr r2, [pc, #460] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7496. 800318e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
  7497. 8003192: 6013 str r3, [r2, #0]
  7498. /* Check the HSE State */
  7499. if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
  7500. 8003194: 687b ldr r3, [r7, #4]
  7501. 8003196: 685b ldr r3, [r3, #4]
  7502. 8003198: 2b00 cmp r3, #0
  7503. 800319a: d013 beq.n 80031c4 <HAL_RCC_OscConfig+0x104>
  7504. {
  7505. /* Get Start Tick*/
  7506. tickstart = HAL_GetTick();
  7507. 800319c: f7fe fa5c bl 8001658 <HAL_GetTick>
  7508. 80031a0: 6278 str r0, [r7, #36] ; 0x24
  7509. /* Wait till HSE is ready */
  7510. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
  7511. 80031a2: e008 b.n 80031b6 <HAL_RCC_OscConfig+0xf6>
  7512. {
  7513. if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  7514. 80031a4: f7fe fa58 bl 8001658 <HAL_GetTick>
  7515. 80031a8: 4602 mov r2, r0
  7516. 80031aa: 6a7b ldr r3, [r7, #36] ; 0x24
  7517. 80031ac: 1ad3 subs r3, r2, r3
  7518. 80031ae: 2b64 cmp r3, #100 ; 0x64
  7519. 80031b0: d901 bls.n 80031b6 <HAL_RCC_OscConfig+0xf6>
  7520. {
  7521. return HAL_TIMEOUT;
  7522. 80031b2: 2303 movs r3, #3
  7523. 80031b4: e325 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7524. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
  7525. 80031b6: 4b69 ldr r3, [pc, #420] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7526. 80031b8: 681b ldr r3, [r3, #0]
  7527. 80031ba: f403 3300 and.w r3, r3, #131072 ; 0x20000
  7528. 80031be: 2b00 cmp r3, #0
  7529. 80031c0: d0f0 beq.n 80031a4 <HAL_RCC_OscConfig+0xe4>
  7530. 80031c2: e014 b.n 80031ee <HAL_RCC_OscConfig+0x12e>
  7531. }
  7532. }
  7533. else
  7534. {
  7535. /* Get Start Tick*/
  7536. tickstart = HAL_GetTick();
  7537. 80031c4: f7fe fa48 bl 8001658 <HAL_GetTick>
  7538. 80031c8: 6278 str r0, [r7, #36] ; 0x24
  7539. /* Wait till HSE is disabled */
  7540. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
  7541. 80031ca: e008 b.n 80031de <HAL_RCC_OscConfig+0x11e>
  7542. {
  7543. if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  7544. 80031cc: f7fe fa44 bl 8001658 <HAL_GetTick>
  7545. 80031d0: 4602 mov r2, r0
  7546. 80031d2: 6a7b ldr r3, [r7, #36] ; 0x24
  7547. 80031d4: 1ad3 subs r3, r2, r3
  7548. 80031d6: 2b64 cmp r3, #100 ; 0x64
  7549. 80031d8: d901 bls.n 80031de <HAL_RCC_OscConfig+0x11e>
  7550. {
  7551. return HAL_TIMEOUT;
  7552. 80031da: 2303 movs r3, #3
  7553. 80031dc: e311 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7554. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
  7555. 80031de: 4b5f ldr r3, [pc, #380] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7556. 80031e0: 681b ldr r3, [r3, #0]
  7557. 80031e2: f403 3300 and.w r3, r3, #131072 ; 0x20000
  7558. 80031e6: 2b00 cmp r3, #0
  7559. 80031e8: d1f0 bne.n 80031cc <HAL_RCC_OscConfig+0x10c>
  7560. 80031ea: e000 b.n 80031ee <HAL_RCC_OscConfig+0x12e>
  7561. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
  7562. 80031ec: bf00 nop
  7563. }
  7564. }
  7565. }
  7566. }
  7567. /*----------------------------- HSI Configuration --------------------------*/
  7568. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
  7569. 80031ee: 687b ldr r3, [r7, #4]
  7570. 80031f0: 681b ldr r3, [r3, #0]
  7571. 80031f2: f003 0302 and.w r3, r3, #2
  7572. 80031f6: 2b00 cmp r3, #0
  7573. 80031f8: f000 808a beq.w 8003310 <HAL_RCC_OscConfig+0x250>
  7574. /* Check the parameters */
  7575. assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
  7576. assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
  7577. /* When the HSI is used as system clock it will not be disabled */
  7578. const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
  7579. 80031fc: 4b57 ldr r3, [pc, #348] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7580. 80031fe: 691b ldr r3, [r3, #16]
  7581. 8003200: f003 0338 and.w r3, r3, #56 ; 0x38
  7582. 8003204: 623b str r3, [r7, #32]
  7583. const uint32_t temp_pllckselr = RCC->PLLCKSELR;
  7584. 8003206: 4b55 ldr r3, [pc, #340] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7585. 8003208: 6a9b ldr r3, [r3, #40] ; 0x28
  7586. 800320a: 61fb str r3, [r7, #28]
  7587. if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
  7588. 800320c: 6a3b ldr r3, [r7, #32]
  7589. 800320e: 2b00 cmp r3, #0
  7590. 8003210: d007 beq.n 8003222 <HAL_RCC_OscConfig+0x162>
  7591. 8003212: 6a3b ldr r3, [r7, #32]
  7592. 8003214: 2b18 cmp r3, #24
  7593. 8003216: d137 bne.n 8003288 <HAL_RCC_OscConfig+0x1c8>
  7594. 8003218: 69fb ldr r3, [r7, #28]
  7595. 800321a: f003 0303 and.w r3, r3, #3
  7596. 800321e: 2b00 cmp r3, #0
  7597. 8003220: d132 bne.n 8003288 <HAL_RCC_OscConfig+0x1c8>
  7598. {
  7599. /* When HSI is used as system clock it will not be disabled */
  7600. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
  7601. 8003222: 4b4e ldr r3, [pc, #312] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7602. 8003224: 681b ldr r3, [r3, #0]
  7603. 8003226: f003 0304 and.w r3, r3, #4
  7604. 800322a: 2b00 cmp r3, #0
  7605. 800322c: d005 beq.n 800323a <HAL_RCC_OscConfig+0x17a>
  7606. 800322e: 687b ldr r3, [r7, #4]
  7607. 8003230: 68db ldr r3, [r3, #12]
  7608. 8003232: 2b00 cmp r3, #0
  7609. 8003234: d101 bne.n 800323a <HAL_RCC_OscConfig+0x17a>
  7610. {
  7611. return HAL_ERROR;
  7612. 8003236: 2301 movs r3, #1
  7613. 8003238: e2e3 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7614. }
  7615. /* Otherwise, only HSI division and calibration are allowed */
  7616. else
  7617. {
  7618. /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */
  7619. __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
  7620. 800323a: 4b48 ldr r3, [pc, #288] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7621. 800323c: 681b ldr r3, [r3, #0]
  7622. 800323e: f023 0219 bic.w r2, r3, #25
  7623. 8003242: 687b ldr r3, [r7, #4]
  7624. 8003244: 68db ldr r3, [r3, #12]
  7625. 8003246: 4945 ldr r1, [pc, #276] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7626. 8003248: 4313 orrs r3, r2
  7627. 800324a: 600b str r3, [r1, #0]
  7628. /* Get Start Tick*/
  7629. tickstart = HAL_GetTick();
  7630. 800324c: f7fe fa04 bl 8001658 <HAL_GetTick>
  7631. 8003250: 6278 str r0, [r7, #36] ; 0x24
  7632. /* Wait till HSI is ready */
  7633. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  7634. 8003252: e008 b.n 8003266 <HAL_RCC_OscConfig+0x1a6>
  7635. {
  7636. if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  7637. 8003254: f7fe fa00 bl 8001658 <HAL_GetTick>
  7638. 8003258: 4602 mov r2, r0
  7639. 800325a: 6a7b ldr r3, [r7, #36] ; 0x24
  7640. 800325c: 1ad3 subs r3, r2, r3
  7641. 800325e: 2b02 cmp r3, #2
  7642. 8003260: d901 bls.n 8003266 <HAL_RCC_OscConfig+0x1a6>
  7643. {
  7644. return HAL_TIMEOUT;
  7645. 8003262: 2303 movs r3, #3
  7646. 8003264: e2cd b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7647. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  7648. 8003266: 4b3d ldr r3, [pc, #244] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7649. 8003268: 681b ldr r3, [r3, #0]
  7650. 800326a: f003 0304 and.w r3, r3, #4
  7651. 800326e: 2b00 cmp r3, #0
  7652. 8003270: d0f0 beq.n 8003254 <HAL_RCC_OscConfig+0x194>
  7653. }
  7654. }
  7655. /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
  7656. __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  7657. 8003272: 4b3a ldr r3, [pc, #232] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7658. 8003274: 685b ldr r3, [r3, #4]
  7659. 8003276: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000
  7660. 800327a: 687b ldr r3, [r7, #4]
  7661. 800327c: 691b ldr r3, [r3, #16]
  7662. 800327e: 061b lsls r3, r3, #24
  7663. 8003280: 4936 ldr r1, [pc, #216] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7664. 8003282: 4313 orrs r3, r2
  7665. 8003284: 604b str r3, [r1, #4]
  7666. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
  7667. 8003286: e043 b.n 8003310 <HAL_RCC_OscConfig+0x250>
  7668. }
  7669. else
  7670. {
  7671. /* Check the HSI State */
  7672. if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
  7673. 8003288: 687b ldr r3, [r7, #4]
  7674. 800328a: 68db ldr r3, [r3, #12]
  7675. 800328c: 2b00 cmp r3, #0
  7676. 800328e: d026 beq.n 80032de <HAL_RCC_OscConfig+0x21e>
  7677. {
  7678. /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
  7679. __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
  7680. 8003290: 4b32 ldr r3, [pc, #200] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7681. 8003292: 681b ldr r3, [r3, #0]
  7682. 8003294: f023 0219 bic.w r2, r3, #25
  7683. 8003298: 687b ldr r3, [r7, #4]
  7684. 800329a: 68db ldr r3, [r3, #12]
  7685. 800329c: 492f ldr r1, [pc, #188] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7686. 800329e: 4313 orrs r3, r2
  7687. 80032a0: 600b str r3, [r1, #0]
  7688. /* Get Start Tick*/
  7689. tickstart = HAL_GetTick();
  7690. 80032a2: f7fe f9d9 bl 8001658 <HAL_GetTick>
  7691. 80032a6: 6278 str r0, [r7, #36] ; 0x24
  7692. /* Wait till HSI is ready */
  7693. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  7694. 80032a8: e008 b.n 80032bc <HAL_RCC_OscConfig+0x1fc>
  7695. {
  7696. if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  7697. 80032aa: f7fe f9d5 bl 8001658 <HAL_GetTick>
  7698. 80032ae: 4602 mov r2, r0
  7699. 80032b0: 6a7b ldr r3, [r7, #36] ; 0x24
  7700. 80032b2: 1ad3 subs r3, r2, r3
  7701. 80032b4: 2b02 cmp r3, #2
  7702. 80032b6: d901 bls.n 80032bc <HAL_RCC_OscConfig+0x1fc>
  7703. {
  7704. return HAL_TIMEOUT;
  7705. 80032b8: 2303 movs r3, #3
  7706. 80032ba: e2a2 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7707. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  7708. 80032bc: 4b27 ldr r3, [pc, #156] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7709. 80032be: 681b ldr r3, [r3, #0]
  7710. 80032c0: f003 0304 and.w r3, r3, #4
  7711. 80032c4: 2b00 cmp r3, #0
  7712. 80032c6: d0f0 beq.n 80032aa <HAL_RCC_OscConfig+0x1ea>
  7713. }
  7714. }
  7715. /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
  7716. __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  7717. 80032c8: 4b24 ldr r3, [pc, #144] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7718. 80032ca: 685b ldr r3, [r3, #4]
  7719. 80032cc: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000
  7720. 80032d0: 687b ldr r3, [r7, #4]
  7721. 80032d2: 691b ldr r3, [r3, #16]
  7722. 80032d4: 061b lsls r3, r3, #24
  7723. 80032d6: 4921 ldr r1, [pc, #132] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7724. 80032d8: 4313 orrs r3, r2
  7725. 80032da: 604b str r3, [r1, #4]
  7726. 80032dc: e018 b.n 8003310 <HAL_RCC_OscConfig+0x250>
  7727. }
  7728. else
  7729. {
  7730. /* Disable the Internal High Speed oscillator (HSI). */
  7731. __HAL_RCC_HSI_DISABLE();
  7732. 80032de: 4b1f ldr r3, [pc, #124] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7733. 80032e0: 681b ldr r3, [r3, #0]
  7734. 80032e2: 4a1e ldr r2, [pc, #120] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7735. 80032e4: f023 0301 bic.w r3, r3, #1
  7736. 80032e8: 6013 str r3, [r2, #0]
  7737. /* Get Start Tick*/
  7738. tickstart = HAL_GetTick();
  7739. 80032ea: f7fe f9b5 bl 8001658 <HAL_GetTick>
  7740. 80032ee: 6278 str r0, [r7, #36] ; 0x24
  7741. /* Wait till HSI is disabled */
  7742. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
  7743. 80032f0: e008 b.n 8003304 <HAL_RCC_OscConfig+0x244>
  7744. {
  7745. if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  7746. 80032f2: f7fe f9b1 bl 8001658 <HAL_GetTick>
  7747. 80032f6: 4602 mov r2, r0
  7748. 80032f8: 6a7b ldr r3, [r7, #36] ; 0x24
  7749. 80032fa: 1ad3 subs r3, r2, r3
  7750. 80032fc: 2b02 cmp r3, #2
  7751. 80032fe: d901 bls.n 8003304 <HAL_RCC_OscConfig+0x244>
  7752. {
  7753. return HAL_TIMEOUT;
  7754. 8003300: 2303 movs r3, #3
  7755. 8003302: e27e b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7756. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
  7757. 8003304: 4b15 ldr r3, [pc, #84] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7758. 8003306: 681b ldr r3, [r3, #0]
  7759. 8003308: f003 0304 and.w r3, r3, #4
  7760. 800330c: 2b00 cmp r3, #0
  7761. 800330e: d1f0 bne.n 80032f2 <HAL_RCC_OscConfig+0x232>
  7762. }
  7763. }
  7764. }
  7765. }
  7766. /*----------------------------- CSI Configuration --------------------------*/
  7767. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
  7768. 8003310: 687b ldr r3, [r7, #4]
  7769. 8003312: 681b ldr r3, [r3, #0]
  7770. 8003314: f003 0310 and.w r3, r3, #16
  7771. 8003318: 2b00 cmp r3, #0
  7772. 800331a: d06d beq.n 80033f8 <HAL_RCC_OscConfig+0x338>
  7773. /* Check the parameters */
  7774. assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
  7775. assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
  7776. /* When the CSI is used as system clock it will not disabled */
  7777. const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
  7778. 800331c: 4b0f ldr r3, [pc, #60] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7779. 800331e: 691b ldr r3, [r3, #16]
  7780. 8003320: f003 0338 and.w r3, r3, #56 ; 0x38
  7781. 8003324: 61bb str r3, [r7, #24]
  7782. const uint32_t temp_pllckselr = RCC->PLLCKSELR;
  7783. 8003326: 4b0d ldr r3, [pc, #52] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7784. 8003328: 6a9b ldr r3, [r3, #40] ; 0x28
  7785. 800332a: 617b str r3, [r7, #20]
  7786. if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
  7787. 800332c: 69bb ldr r3, [r7, #24]
  7788. 800332e: 2b08 cmp r3, #8
  7789. 8003330: d007 beq.n 8003342 <HAL_RCC_OscConfig+0x282>
  7790. 8003332: 69bb ldr r3, [r7, #24]
  7791. 8003334: 2b18 cmp r3, #24
  7792. 8003336: d11e bne.n 8003376 <HAL_RCC_OscConfig+0x2b6>
  7793. 8003338: 697b ldr r3, [r7, #20]
  7794. 800333a: f003 0303 and.w r3, r3, #3
  7795. 800333e: 2b01 cmp r3, #1
  7796. 8003340: d119 bne.n 8003376 <HAL_RCC_OscConfig+0x2b6>
  7797. {
  7798. /* When CSI is used as system clock it will not disabled */
  7799. if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
  7800. 8003342: 4b06 ldr r3, [pc, #24] ; (800335c <HAL_RCC_OscConfig+0x29c>)
  7801. 8003344: 681b ldr r3, [r3, #0]
  7802. 8003346: f403 7380 and.w r3, r3, #256 ; 0x100
  7803. 800334a: 2b00 cmp r3, #0
  7804. 800334c: d008 beq.n 8003360 <HAL_RCC_OscConfig+0x2a0>
  7805. 800334e: 687b ldr r3, [r7, #4]
  7806. 8003350: 69db ldr r3, [r3, #28]
  7807. 8003352: 2b80 cmp r3, #128 ; 0x80
  7808. 8003354: d004 beq.n 8003360 <HAL_RCC_OscConfig+0x2a0>
  7809. {
  7810. return HAL_ERROR;
  7811. 8003356: 2301 movs r3, #1
  7812. 8003358: e253 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7813. 800335a: bf00 nop
  7814. 800335c: 58024400 .word 0x58024400
  7815. }
  7816. /* Otherwise, just the calibration is allowed */
  7817. else
  7818. {
  7819. /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
  7820. __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
  7821. 8003360: 4ba3 ldr r3, [pc, #652] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7822. 8003362: 68db ldr r3, [r3, #12]
  7823. 8003364: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000
  7824. 8003368: 687b ldr r3, [r7, #4]
  7825. 800336a: 6a1b ldr r3, [r3, #32]
  7826. 800336c: 061b lsls r3, r3, #24
  7827. 800336e: 49a0 ldr r1, [pc, #640] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7828. 8003370: 4313 orrs r3, r2
  7829. 8003372: 60cb str r3, [r1, #12]
  7830. if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
  7831. 8003374: e040 b.n 80033f8 <HAL_RCC_OscConfig+0x338>
  7832. }
  7833. }
  7834. else
  7835. {
  7836. /* Check the CSI State */
  7837. if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF)
  7838. 8003376: 687b ldr r3, [r7, #4]
  7839. 8003378: 69db ldr r3, [r3, #28]
  7840. 800337a: 2b00 cmp r3, #0
  7841. 800337c: d023 beq.n 80033c6 <HAL_RCC_OscConfig+0x306>
  7842. {
  7843. /* Enable the Internal High Speed oscillator (CSI). */
  7844. __HAL_RCC_CSI_ENABLE();
  7845. 800337e: 4b9c ldr r3, [pc, #624] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7846. 8003380: 681b ldr r3, [r3, #0]
  7847. 8003382: 4a9b ldr r2, [pc, #620] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7848. 8003384: f043 0380 orr.w r3, r3, #128 ; 0x80
  7849. 8003388: 6013 str r3, [r2, #0]
  7850. /* Get Start Tick*/
  7851. tickstart = HAL_GetTick();
  7852. 800338a: f7fe f965 bl 8001658 <HAL_GetTick>
  7853. 800338e: 6278 str r0, [r7, #36] ; 0x24
  7854. /* Wait till CSI is ready */
  7855. while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
  7856. 8003390: e008 b.n 80033a4 <HAL_RCC_OscConfig+0x2e4>
  7857. {
  7858. if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
  7859. 8003392: f7fe f961 bl 8001658 <HAL_GetTick>
  7860. 8003396: 4602 mov r2, r0
  7861. 8003398: 6a7b ldr r3, [r7, #36] ; 0x24
  7862. 800339a: 1ad3 subs r3, r2, r3
  7863. 800339c: 2b02 cmp r3, #2
  7864. 800339e: d901 bls.n 80033a4 <HAL_RCC_OscConfig+0x2e4>
  7865. {
  7866. return HAL_TIMEOUT;
  7867. 80033a0: 2303 movs r3, #3
  7868. 80033a2: e22e b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7869. while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
  7870. 80033a4: 4b92 ldr r3, [pc, #584] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7871. 80033a6: 681b ldr r3, [r3, #0]
  7872. 80033a8: f403 7380 and.w r3, r3, #256 ; 0x100
  7873. 80033ac: 2b00 cmp r3, #0
  7874. 80033ae: d0f0 beq.n 8003392 <HAL_RCC_OscConfig+0x2d2>
  7875. }
  7876. }
  7877. /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
  7878. __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
  7879. 80033b0: 4b8f ldr r3, [pc, #572] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7880. 80033b2: 68db ldr r3, [r3, #12]
  7881. 80033b4: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000
  7882. 80033b8: 687b ldr r3, [r7, #4]
  7883. 80033ba: 6a1b ldr r3, [r3, #32]
  7884. 80033bc: 061b lsls r3, r3, #24
  7885. 80033be: 498c ldr r1, [pc, #560] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7886. 80033c0: 4313 orrs r3, r2
  7887. 80033c2: 60cb str r3, [r1, #12]
  7888. 80033c4: e018 b.n 80033f8 <HAL_RCC_OscConfig+0x338>
  7889. }
  7890. else
  7891. {
  7892. /* Disable the Internal High Speed oscillator (CSI). */
  7893. __HAL_RCC_CSI_DISABLE();
  7894. 80033c6: 4b8a ldr r3, [pc, #552] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7895. 80033c8: 681b ldr r3, [r3, #0]
  7896. 80033ca: 4a89 ldr r2, [pc, #548] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7897. 80033cc: f023 0380 bic.w r3, r3, #128 ; 0x80
  7898. 80033d0: 6013 str r3, [r2, #0]
  7899. /* Get Start Tick*/
  7900. tickstart = HAL_GetTick();
  7901. 80033d2: f7fe f941 bl 8001658 <HAL_GetTick>
  7902. 80033d6: 6278 str r0, [r7, #36] ; 0x24
  7903. /* Wait till CSI is disabled */
  7904. while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
  7905. 80033d8: e008 b.n 80033ec <HAL_RCC_OscConfig+0x32c>
  7906. {
  7907. if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
  7908. 80033da: f7fe f93d bl 8001658 <HAL_GetTick>
  7909. 80033de: 4602 mov r2, r0
  7910. 80033e0: 6a7b ldr r3, [r7, #36] ; 0x24
  7911. 80033e2: 1ad3 subs r3, r2, r3
  7912. 80033e4: 2b02 cmp r3, #2
  7913. 80033e6: d901 bls.n 80033ec <HAL_RCC_OscConfig+0x32c>
  7914. {
  7915. return HAL_TIMEOUT;
  7916. 80033e8: 2303 movs r3, #3
  7917. 80033ea: e20a b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7918. while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
  7919. 80033ec: 4b80 ldr r3, [pc, #512] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7920. 80033ee: 681b ldr r3, [r3, #0]
  7921. 80033f0: f403 7380 and.w r3, r3, #256 ; 0x100
  7922. 80033f4: 2b00 cmp r3, #0
  7923. 80033f6: d1f0 bne.n 80033da <HAL_RCC_OscConfig+0x31a>
  7924. }
  7925. }
  7926. }
  7927. }
  7928. /*------------------------------ LSI Configuration -------------------------*/
  7929. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  7930. 80033f8: 687b ldr r3, [r7, #4]
  7931. 80033fa: 681b ldr r3, [r3, #0]
  7932. 80033fc: f003 0308 and.w r3, r3, #8
  7933. 8003400: 2b00 cmp r3, #0
  7934. 8003402: d036 beq.n 8003472 <HAL_RCC_OscConfig+0x3b2>
  7935. {
  7936. /* Check the parameters */
  7937. assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
  7938. /* Check the LSI State */
  7939. if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
  7940. 8003404: 687b ldr r3, [r7, #4]
  7941. 8003406: 695b ldr r3, [r3, #20]
  7942. 8003408: 2b00 cmp r3, #0
  7943. 800340a: d019 beq.n 8003440 <HAL_RCC_OscConfig+0x380>
  7944. {
  7945. /* Enable the Internal Low Speed oscillator (LSI). */
  7946. __HAL_RCC_LSI_ENABLE();
  7947. 800340c: 4b78 ldr r3, [pc, #480] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7948. 800340e: 6f5b ldr r3, [r3, #116] ; 0x74
  7949. 8003410: 4a77 ldr r2, [pc, #476] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7950. 8003412: f043 0301 orr.w r3, r3, #1
  7951. 8003416: 6753 str r3, [r2, #116] ; 0x74
  7952. /* Get Start Tick*/
  7953. tickstart = HAL_GetTick();
  7954. 8003418: f7fe f91e bl 8001658 <HAL_GetTick>
  7955. 800341c: 6278 str r0, [r7, #36] ; 0x24
  7956. /* Wait till LSI is ready */
  7957. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
  7958. 800341e: e008 b.n 8003432 <HAL_RCC_OscConfig+0x372>
  7959. {
  7960. if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  7961. 8003420: f7fe f91a bl 8001658 <HAL_GetTick>
  7962. 8003424: 4602 mov r2, r0
  7963. 8003426: 6a7b ldr r3, [r7, #36] ; 0x24
  7964. 8003428: 1ad3 subs r3, r2, r3
  7965. 800342a: 2b02 cmp r3, #2
  7966. 800342c: d901 bls.n 8003432 <HAL_RCC_OscConfig+0x372>
  7967. {
  7968. return HAL_TIMEOUT;
  7969. 800342e: 2303 movs r3, #3
  7970. 8003430: e1e7 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  7971. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
  7972. 8003432: 4b6f ldr r3, [pc, #444] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7973. 8003434: 6f5b ldr r3, [r3, #116] ; 0x74
  7974. 8003436: f003 0302 and.w r3, r3, #2
  7975. 800343a: 2b00 cmp r3, #0
  7976. 800343c: d0f0 beq.n 8003420 <HAL_RCC_OscConfig+0x360>
  7977. 800343e: e018 b.n 8003472 <HAL_RCC_OscConfig+0x3b2>
  7978. }
  7979. }
  7980. else
  7981. {
  7982. /* Disable the Internal Low Speed oscillator (LSI). */
  7983. __HAL_RCC_LSI_DISABLE();
  7984. 8003440: 4b6b ldr r3, [pc, #428] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7985. 8003442: 6f5b ldr r3, [r3, #116] ; 0x74
  7986. 8003444: 4a6a ldr r2, [pc, #424] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  7987. 8003446: f023 0301 bic.w r3, r3, #1
  7988. 800344a: 6753 str r3, [r2, #116] ; 0x74
  7989. /* Get Start Tick*/
  7990. tickstart = HAL_GetTick();
  7991. 800344c: f7fe f904 bl 8001658 <HAL_GetTick>
  7992. 8003450: 6278 str r0, [r7, #36] ; 0x24
  7993. /* Wait till LSI is ready */
  7994. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
  7995. 8003452: e008 b.n 8003466 <HAL_RCC_OscConfig+0x3a6>
  7996. {
  7997. if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  7998. 8003454: f7fe f900 bl 8001658 <HAL_GetTick>
  7999. 8003458: 4602 mov r2, r0
  8000. 800345a: 6a7b ldr r3, [r7, #36] ; 0x24
  8001. 800345c: 1ad3 subs r3, r2, r3
  8002. 800345e: 2b02 cmp r3, #2
  8003. 8003460: d901 bls.n 8003466 <HAL_RCC_OscConfig+0x3a6>
  8004. {
  8005. return HAL_TIMEOUT;
  8006. 8003462: 2303 movs r3, #3
  8007. 8003464: e1cd b.n 8003802 <HAL_RCC_OscConfig+0x742>
  8008. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
  8009. 8003466: 4b62 ldr r3, [pc, #392] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8010. 8003468: 6f5b ldr r3, [r3, #116] ; 0x74
  8011. 800346a: f003 0302 and.w r3, r3, #2
  8012. 800346e: 2b00 cmp r3, #0
  8013. 8003470: d1f0 bne.n 8003454 <HAL_RCC_OscConfig+0x394>
  8014. }
  8015. }
  8016. }
  8017. /*------------------------------ HSI48 Configuration -------------------------*/
  8018. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
  8019. 8003472: 687b ldr r3, [r7, #4]
  8020. 8003474: 681b ldr r3, [r3, #0]
  8021. 8003476: f003 0320 and.w r3, r3, #32
  8022. 800347a: 2b00 cmp r3, #0
  8023. 800347c: d036 beq.n 80034ec <HAL_RCC_OscConfig+0x42c>
  8024. {
  8025. /* Check the parameters */
  8026. assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
  8027. /* Check the HSI48 State */
  8028. if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)
  8029. 800347e: 687b ldr r3, [r7, #4]
  8030. 8003480: 699b ldr r3, [r3, #24]
  8031. 8003482: 2b00 cmp r3, #0
  8032. 8003484: d019 beq.n 80034ba <HAL_RCC_OscConfig+0x3fa>
  8033. {
  8034. /* Enable the Internal Low Speed oscillator (HSI48). */
  8035. __HAL_RCC_HSI48_ENABLE();
  8036. 8003486: 4b5a ldr r3, [pc, #360] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8037. 8003488: 681b ldr r3, [r3, #0]
  8038. 800348a: 4a59 ldr r2, [pc, #356] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8039. 800348c: f443 5380 orr.w r3, r3, #4096 ; 0x1000
  8040. 8003490: 6013 str r3, [r2, #0]
  8041. /* Get time-out */
  8042. tickstart = HAL_GetTick();
  8043. 8003492: f7fe f8e1 bl 8001658 <HAL_GetTick>
  8044. 8003496: 6278 str r0, [r7, #36] ; 0x24
  8045. /* Wait till HSI48 is ready */
  8046. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
  8047. 8003498: e008 b.n 80034ac <HAL_RCC_OscConfig+0x3ec>
  8048. {
  8049. if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
  8050. 800349a: f7fe f8dd bl 8001658 <HAL_GetTick>
  8051. 800349e: 4602 mov r2, r0
  8052. 80034a0: 6a7b ldr r3, [r7, #36] ; 0x24
  8053. 80034a2: 1ad3 subs r3, r2, r3
  8054. 80034a4: 2b02 cmp r3, #2
  8055. 80034a6: d901 bls.n 80034ac <HAL_RCC_OscConfig+0x3ec>
  8056. {
  8057. return HAL_TIMEOUT;
  8058. 80034a8: 2303 movs r3, #3
  8059. 80034aa: e1aa b.n 8003802 <HAL_RCC_OscConfig+0x742>
  8060. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
  8061. 80034ac: 4b50 ldr r3, [pc, #320] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8062. 80034ae: 681b ldr r3, [r3, #0]
  8063. 80034b0: f403 5300 and.w r3, r3, #8192 ; 0x2000
  8064. 80034b4: 2b00 cmp r3, #0
  8065. 80034b6: d0f0 beq.n 800349a <HAL_RCC_OscConfig+0x3da>
  8066. 80034b8: e018 b.n 80034ec <HAL_RCC_OscConfig+0x42c>
  8067. }
  8068. }
  8069. else
  8070. {
  8071. /* Disable the Internal Low Speed oscillator (HSI48). */
  8072. __HAL_RCC_HSI48_DISABLE();
  8073. 80034ba: 4b4d ldr r3, [pc, #308] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8074. 80034bc: 681b ldr r3, [r3, #0]
  8075. 80034be: 4a4c ldr r2, [pc, #304] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8076. 80034c0: f423 5380 bic.w r3, r3, #4096 ; 0x1000
  8077. 80034c4: 6013 str r3, [r2, #0]
  8078. /* Get time-out */
  8079. tickstart = HAL_GetTick();
  8080. 80034c6: f7fe f8c7 bl 8001658 <HAL_GetTick>
  8081. 80034ca: 6278 str r0, [r7, #36] ; 0x24
  8082. /* Wait till HSI48 is ready */
  8083. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
  8084. 80034cc: e008 b.n 80034e0 <HAL_RCC_OscConfig+0x420>
  8085. {
  8086. if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
  8087. 80034ce: f7fe f8c3 bl 8001658 <HAL_GetTick>
  8088. 80034d2: 4602 mov r2, r0
  8089. 80034d4: 6a7b ldr r3, [r7, #36] ; 0x24
  8090. 80034d6: 1ad3 subs r3, r2, r3
  8091. 80034d8: 2b02 cmp r3, #2
  8092. 80034da: d901 bls.n 80034e0 <HAL_RCC_OscConfig+0x420>
  8093. {
  8094. return HAL_TIMEOUT;
  8095. 80034dc: 2303 movs r3, #3
  8096. 80034de: e190 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  8097. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
  8098. 80034e0: 4b43 ldr r3, [pc, #268] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8099. 80034e2: 681b ldr r3, [r3, #0]
  8100. 80034e4: f403 5300 and.w r3, r3, #8192 ; 0x2000
  8101. 80034e8: 2b00 cmp r3, #0
  8102. 80034ea: d1f0 bne.n 80034ce <HAL_RCC_OscConfig+0x40e>
  8103. }
  8104. }
  8105. }
  8106. }
  8107. /*------------------------------ LSE Configuration -------------------------*/
  8108. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
  8109. 80034ec: 687b ldr r3, [r7, #4]
  8110. 80034ee: 681b ldr r3, [r3, #0]
  8111. 80034f0: f003 0304 and.w r3, r3, #4
  8112. 80034f4: 2b00 cmp r3, #0
  8113. 80034f6: f000 8085 beq.w 8003604 <HAL_RCC_OscConfig+0x544>
  8114. {
  8115. /* Check the parameters */
  8116. assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
  8117. /* Enable write access to Backup domain */
  8118. PWR->CR1 |= PWR_CR1_DBP;
  8119. 80034fa: 4b3e ldr r3, [pc, #248] ; (80035f4 <HAL_RCC_OscConfig+0x534>)
  8120. 80034fc: 681b ldr r3, [r3, #0]
  8121. 80034fe: 4a3d ldr r2, [pc, #244] ; (80035f4 <HAL_RCC_OscConfig+0x534>)
  8122. 8003500: f443 7380 orr.w r3, r3, #256 ; 0x100
  8123. 8003504: 6013 str r3, [r2, #0]
  8124. /* Wait for Backup domain Write protection disable */
  8125. tickstart = HAL_GetTick();
  8126. 8003506: f7fe f8a7 bl 8001658 <HAL_GetTick>
  8127. 800350a: 6278 str r0, [r7, #36] ; 0x24
  8128. while((PWR->CR1 & PWR_CR1_DBP) == 0U)
  8129. 800350c: e008 b.n 8003520 <HAL_RCC_OscConfig+0x460>
  8130. {
  8131. if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
  8132. 800350e: f7fe f8a3 bl 8001658 <HAL_GetTick>
  8133. 8003512: 4602 mov r2, r0
  8134. 8003514: 6a7b ldr r3, [r7, #36] ; 0x24
  8135. 8003516: 1ad3 subs r3, r2, r3
  8136. 8003518: 2b64 cmp r3, #100 ; 0x64
  8137. 800351a: d901 bls.n 8003520 <HAL_RCC_OscConfig+0x460>
  8138. {
  8139. return HAL_TIMEOUT;
  8140. 800351c: 2303 movs r3, #3
  8141. 800351e: e170 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  8142. while((PWR->CR1 & PWR_CR1_DBP) == 0U)
  8143. 8003520: 4b34 ldr r3, [pc, #208] ; (80035f4 <HAL_RCC_OscConfig+0x534>)
  8144. 8003522: 681b ldr r3, [r3, #0]
  8145. 8003524: f403 7380 and.w r3, r3, #256 ; 0x100
  8146. 8003528: 2b00 cmp r3, #0
  8147. 800352a: d0f0 beq.n 800350e <HAL_RCC_OscConfig+0x44e>
  8148. }
  8149. }
  8150. /* Set the new LSE configuration -----------------------------------------*/
  8151. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  8152. 800352c: 687b ldr r3, [r7, #4]
  8153. 800352e: 689b ldr r3, [r3, #8]
  8154. 8003530: 2b01 cmp r3, #1
  8155. 8003532: d106 bne.n 8003542 <HAL_RCC_OscConfig+0x482>
  8156. 8003534: 4b2e ldr r3, [pc, #184] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8157. 8003536: 6f1b ldr r3, [r3, #112] ; 0x70
  8158. 8003538: 4a2d ldr r2, [pc, #180] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8159. 800353a: f043 0301 orr.w r3, r3, #1
  8160. 800353e: 6713 str r3, [r2, #112] ; 0x70
  8161. 8003540: e02d b.n 800359e <HAL_RCC_OscConfig+0x4de>
  8162. 8003542: 687b ldr r3, [r7, #4]
  8163. 8003544: 689b ldr r3, [r3, #8]
  8164. 8003546: 2b00 cmp r3, #0
  8165. 8003548: d10c bne.n 8003564 <HAL_RCC_OscConfig+0x4a4>
  8166. 800354a: 4b29 ldr r3, [pc, #164] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8167. 800354c: 6f1b ldr r3, [r3, #112] ; 0x70
  8168. 800354e: 4a28 ldr r2, [pc, #160] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8169. 8003550: f023 0301 bic.w r3, r3, #1
  8170. 8003554: 6713 str r3, [r2, #112] ; 0x70
  8171. 8003556: 4b26 ldr r3, [pc, #152] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8172. 8003558: 6f1b ldr r3, [r3, #112] ; 0x70
  8173. 800355a: 4a25 ldr r2, [pc, #148] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8174. 800355c: f023 0304 bic.w r3, r3, #4
  8175. 8003560: 6713 str r3, [r2, #112] ; 0x70
  8176. 8003562: e01c b.n 800359e <HAL_RCC_OscConfig+0x4de>
  8177. 8003564: 687b ldr r3, [r7, #4]
  8178. 8003566: 689b ldr r3, [r3, #8]
  8179. 8003568: 2b05 cmp r3, #5
  8180. 800356a: d10c bne.n 8003586 <HAL_RCC_OscConfig+0x4c6>
  8181. 800356c: 4b20 ldr r3, [pc, #128] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8182. 800356e: 6f1b ldr r3, [r3, #112] ; 0x70
  8183. 8003570: 4a1f ldr r2, [pc, #124] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8184. 8003572: f043 0304 orr.w r3, r3, #4
  8185. 8003576: 6713 str r3, [r2, #112] ; 0x70
  8186. 8003578: 4b1d ldr r3, [pc, #116] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8187. 800357a: 6f1b ldr r3, [r3, #112] ; 0x70
  8188. 800357c: 4a1c ldr r2, [pc, #112] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8189. 800357e: f043 0301 orr.w r3, r3, #1
  8190. 8003582: 6713 str r3, [r2, #112] ; 0x70
  8191. 8003584: e00b b.n 800359e <HAL_RCC_OscConfig+0x4de>
  8192. 8003586: 4b1a ldr r3, [pc, #104] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8193. 8003588: 6f1b ldr r3, [r3, #112] ; 0x70
  8194. 800358a: 4a19 ldr r2, [pc, #100] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8195. 800358c: f023 0301 bic.w r3, r3, #1
  8196. 8003590: 6713 str r3, [r2, #112] ; 0x70
  8197. 8003592: 4b17 ldr r3, [pc, #92] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8198. 8003594: 6f1b ldr r3, [r3, #112] ; 0x70
  8199. 8003596: 4a16 ldr r2, [pc, #88] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8200. 8003598: f023 0304 bic.w r3, r3, #4
  8201. 800359c: 6713 str r3, [r2, #112] ; 0x70
  8202. /* Check the LSE State */
  8203. if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
  8204. 800359e: 687b ldr r3, [r7, #4]
  8205. 80035a0: 689b ldr r3, [r3, #8]
  8206. 80035a2: 2b00 cmp r3, #0
  8207. 80035a4: d015 beq.n 80035d2 <HAL_RCC_OscConfig+0x512>
  8208. {
  8209. /* Get Start Tick*/
  8210. tickstart = HAL_GetTick();
  8211. 80035a6: f7fe f857 bl 8001658 <HAL_GetTick>
  8212. 80035aa: 6278 str r0, [r7, #36] ; 0x24
  8213. /* Wait till LSE is ready */
  8214. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  8215. 80035ac: e00a b.n 80035c4 <HAL_RCC_OscConfig+0x504>
  8216. {
  8217. if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  8218. 80035ae: f7fe f853 bl 8001658 <HAL_GetTick>
  8219. 80035b2: 4602 mov r2, r0
  8220. 80035b4: 6a7b ldr r3, [r7, #36] ; 0x24
  8221. 80035b6: 1ad3 subs r3, r2, r3
  8222. 80035b8: f241 3288 movw r2, #5000 ; 0x1388
  8223. 80035bc: 4293 cmp r3, r2
  8224. 80035be: d901 bls.n 80035c4 <HAL_RCC_OscConfig+0x504>
  8225. {
  8226. return HAL_TIMEOUT;
  8227. 80035c0: 2303 movs r3, #3
  8228. 80035c2: e11e b.n 8003802 <HAL_RCC_OscConfig+0x742>
  8229. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  8230. 80035c4: 4b0a ldr r3, [pc, #40] ; (80035f0 <HAL_RCC_OscConfig+0x530>)
  8231. 80035c6: 6f1b ldr r3, [r3, #112] ; 0x70
  8232. 80035c8: f003 0302 and.w r3, r3, #2
  8233. 80035cc: 2b00 cmp r3, #0
  8234. 80035ce: d0ee beq.n 80035ae <HAL_RCC_OscConfig+0x4ee>
  8235. 80035d0: e018 b.n 8003604 <HAL_RCC_OscConfig+0x544>
  8236. }
  8237. }
  8238. else
  8239. {
  8240. /* Get Start Tick*/
  8241. tickstart = HAL_GetTick();
  8242. 80035d2: f7fe f841 bl 8001658 <HAL_GetTick>
  8243. 80035d6: 6278 str r0, [r7, #36] ; 0x24
  8244. /* Wait till LSE is disabled */
  8245. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
  8246. 80035d8: e00e b.n 80035f8 <HAL_RCC_OscConfig+0x538>
  8247. {
  8248. if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  8249. 80035da: f7fe f83d bl 8001658 <HAL_GetTick>
  8250. 80035de: 4602 mov r2, r0
  8251. 80035e0: 6a7b ldr r3, [r7, #36] ; 0x24
  8252. 80035e2: 1ad3 subs r3, r2, r3
  8253. 80035e4: f241 3288 movw r2, #5000 ; 0x1388
  8254. 80035e8: 4293 cmp r3, r2
  8255. 80035ea: d905 bls.n 80035f8 <HAL_RCC_OscConfig+0x538>
  8256. {
  8257. return HAL_TIMEOUT;
  8258. 80035ec: 2303 movs r3, #3
  8259. 80035ee: e108 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  8260. 80035f0: 58024400 .word 0x58024400
  8261. 80035f4: 58024800 .word 0x58024800
  8262. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
  8263. 80035f8: 4b84 ldr r3, [pc, #528] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8264. 80035fa: 6f1b ldr r3, [r3, #112] ; 0x70
  8265. 80035fc: f003 0302 and.w r3, r3, #2
  8266. 8003600: 2b00 cmp r3, #0
  8267. 8003602: d1ea bne.n 80035da <HAL_RCC_OscConfig+0x51a>
  8268. }
  8269. }
  8270. /*-------------------------------- PLL Configuration -----------------------*/
  8271. /* Check the parameters */
  8272. assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  8273. if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
  8274. 8003604: 687b ldr r3, [r7, #4]
  8275. 8003606: 6a5b ldr r3, [r3, #36] ; 0x24
  8276. 8003608: 2b00 cmp r3, #0
  8277. 800360a: f000 80f9 beq.w 8003800 <HAL_RCC_OscConfig+0x740>
  8278. {
  8279. /* Check if the PLL is used as system clock or not */
  8280. if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
  8281. 800360e: 4b7f ldr r3, [pc, #508] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8282. 8003610: 691b ldr r3, [r3, #16]
  8283. 8003612: f003 0338 and.w r3, r3, #56 ; 0x38
  8284. 8003616: 2b18 cmp r3, #24
  8285. 8003618: f000 80b4 beq.w 8003784 <HAL_RCC_OscConfig+0x6c4>
  8286. {
  8287. if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
  8288. 800361c: 687b ldr r3, [r7, #4]
  8289. 800361e: 6a5b ldr r3, [r3, #36] ; 0x24
  8290. 8003620: 2b02 cmp r3, #2
  8291. 8003622: f040 8095 bne.w 8003750 <HAL_RCC_OscConfig+0x690>
  8292. assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
  8293. assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
  8294. assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
  8295. /* Disable the main PLL. */
  8296. __HAL_RCC_PLL_DISABLE();
  8297. 8003626: 4b79 ldr r3, [pc, #484] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8298. 8003628: 681b ldr r3, [r3, #0]
  8299. 800362a: 4a78 ldr r2, [pc, #480] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8300. 800362c: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
  8301. 8003630: 6013 str r3, [r2, #0]
  8302. /* Get Start Tick*/
  8303. tickstart = HAL_GetTick();
  8304. 8003632: f7fe f811 bl 8001658 <HAL_GetTick>
  8305. 8003636: 6278 str r0, [r7, #36] ; 0x24
  8306. /* Wait till PLL is disabled */
  8307. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
  8308. 8003638: e008 b.n 800364c <HAL_RCC_OscConfig+0x58c>
  8309. {
  8310. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  8311. 800363a: f7fe f80d bl 8001658 <HAL_GetTick>
  8312. 800363e: 4602 mov r2, r0
  8313. 8003640: 6a7b ldr r3, [r7, #36] ; 0x24
  8314. 8003642: 1ad3 subs r3, r2, r3
  8315. 8003644: 2b02 cmp r3, #2
  8316. 8003646: d901 bls.n 800364c <HAL_RCC_OscConfig+0x58c>
  8317. {
  8318. return HAL_TIMEOUT;
  8319. 8003648: 2303 movs r3, #3
  8320. 800364a: e0da b.n 8003802 <HAL_RCC_OscConfig+0x742>
  8321. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
  8322. 800364c: 4b6f ldr r3, [pc, #444] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8323. 800364e: 681b ldr r3, [r3, #0]
  8324. 8003650: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
  8325. 8003654: 2b00 cmp r3, #0
  8326. 8003656: d1f0 bne.n 800363a <HAL_RCC_OscConfig+0x57a>
  8327. }
  8328. }
  8329. /* Configure the main PLL clock source, multiplication and division factors. */
  8330. __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
  8331. 8003658: 4b6c ldr r3, [pc, #432] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8332. 800365a: 6a9a ldr r2, [r3, #40] ; 0x28
  8333. 800365c: 4b6c ldr r3, [pc, #432] ; (8003810 <HAL_RCC_OscConfig+0x750>)
  8334. 800365e: 4013 ands r3, r2
  8335. 8003660: 687a ldr r2, [r7, #4]
  8336. 8003662: 6a91 ldr r1, [r2, #40] ; 0x28
  8337. 8003664: 687a ldr r2, [r7, #4]
  8338. 8003666: 6ad2 ldr r2, [r2, #44] ; 0x2c
  8339. 8003668: 0112 lsls r2, r2, #4
  8340. 800366a: 430a orrs r2, r1
  8341. 800366c: 4967 ldr r1, [pc, #412] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8342. 800366e: 4313 orrs r3, r2
  8343. 8003670: 628b str r3, [r1, #40] ; 0x28
  8344. 8003672: 687b ldr r3, [r7, #4]
  8345. 8003674: 6b1b ldr r3, [r3, #48] ; 0x30
  8346. 8003676: 3b01 subs r3, #1
  8347. 8003678: f3c3 0208 ubfx r2, r3, #0, #9
  8348. 800367c: 687b ldr r3, [r7, #4]
  8349. 800367e: 6b5b ldr r3, [r3, #52] ; 0x34
  8350. 8003680: 3b01 subs r3, #1
  8351. 8003682: 025b lsls r3, r3, #9
  8352. 8003684: b29b uxth r3, r3
  8353. 8003686: 431a orrs r2, r3
  8354. 8003688: 687b ldr r3, [r7, #4]
  8355. 800368a: 6b9b ldr r3, [r3, #56] ; 0x38
  8356. 800368c: 3b01 subs r3, #1
  8357. 800368e: 041b lsls r3, r3, #16
  8358. 8003690: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000
  8359. 8003694: 431a orrs r2, r3
  8360. 8003696: 687b ldr r3, [r7, #4]
  8361. 8003698: 6bdb ldr r3, [r3, #60] ; 0x3c
  8362. 800369a: 3b01 subs r3, #1
  8363. 800369c: 061b lsls r3, r3, #24
  8364. 800369e: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000
  8365. 80036a2: 495a ldr r1, [pc, #360] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8366. 80036a4: 4313 orrs r3, r2
  8367. 80036a6: 630b str r3, [r1, #48] ; 0x30
  8368. RCC_OscInitStruct->PLL.PLLP,
  8369. RCC_OscInitStruct->PLL.PLLQ,
  8370. RCC_OscInitStruct->PLL.PLLR);
  8371. /* Disable PLLFRACN . */
  8372. __HAL_RCC_PLLFRACN_DISABLE();
  8373. 80036a8: 4b58 ldr r3, [pc, #352] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8374. 80036aa: 6adb ldr r3, [r3, #44] ; 0x2c
  8375. 80036ac: 4a57 ldr r2, [pc, #348] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8376. 80036ae: f023 0301 bic.w r3, r3, #1
  8377. 80036b2: 62d3 str r3, [r2, #44] ; 0x2c
  8378. /* Configure PLL PLL1FRACN */
  8379. __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
  8380. 80036b4: 4b55 ldr r3, [pc, #340] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8381. 80036b6: 6b5a ldr r2, [r3, #52] ; 0x34
  8382. 80036b8: 4b56 ldr r3, [pc, #344] ; (8003814 <HAL_RCC_OscConfig+0x754>)
  8383. 80036ba: 4013 ands r3, r2
  8384. 80036bc: 687a ldr r2, [r7, #4]
  8385. 80036be: 6c92 ldr r2, [r2, #72] ; 0x48
  8386. 80036c0: 00d2 lsls r2, r2, #3
  8387. 80036c2: 4952 ldr r1, [pc, #328] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8388. 80036c4: 4313 orrs r3, r2
  8389. 80036c6: 634b str r3, [r1, #52] ; 0x34
  8390. /* Select PLL1 input reference frequency range: VCI */
  8391. __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
  8392. 80036c8: 4b50 ldr r3, [pc, #320] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8393. 80036ca: 6adb ldr r3, [r3, #44] ; 0x2c
  8394. 80036cc: f023 020c bic.w r2, r3, #12
  8395. 80036d0: 687b ldr r3, [r7, #4]
  8396. 80036d2: 6c1b ldr r3, [r3, #64] ; 0x40
  8397. 80036d4: 494d ldr r1, [pc, #308] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8398. 80036d6: 4313 orrs r3, r2
  8399. 80036d8: 62cb str r3, [r1, #44] ; 0x2c
  8400. /* Select PLL1 output frequency range : VCO */
  8401. __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
  8402. 80036da: 4b4c ldr r3, [pc, #304] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8403. 80036dc: 6adb ldr r3, [r3, #44] ; 0x2c
  8404. 80036de: f023 0202 bic.w r2, r3, #2
  8405. 80036e2: 687b ldr r3, [r7, #4]
  8406. 80036e4: 6c5b ldr r3, [r3, #68] ; 0x44
  8407. 80036e6: 4949 ldr r1, [pc, #292] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8408. 80036e8: 4313 orrs r3, r2
  8409. 80036ea: 62cb str r3, [r1, #44] ; 0x2c
  8410. /* Enable PLL System Clock output. */
  8411. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
  8412. 80036ec: 4b47 ldr r3, [pc, #284] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8413. 80036ee: 6adb ldr r3, [r3, #44] ; 0x2c
  8414. 80036f0: 4a46 ldr r2, [pc, #280] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8415. 80036f2: f443 3380 orr.w r3, r3, #65536 ; 0x10000
  8416. 80036f6: 62d3 str r3, [r2, #44] ; 0x2c
  8417. /* Enable PLL1Q Clock output. */
  8418. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  8419. 80036f8: 4b44 ldr r3, [pc, #272] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8420. 80036fa: 6adb ldr r3, [r3, #44] ; 0x2c
  8421. 80036fc: 4a43 ldr r2, [pc, #268] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8422. 80036fe: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  8423. 8003702: 62d3 str r3, [r2, #44] ; 0x2c
  8424. /* Enable PLL1R Clock output. */
  8425. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
  8426. 8003704: 4b41 ldr r3, [pc, #260] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8427. 8003706: 6adb ldr r3, [r3, #44] ; 0x2c
  8428. 8003708: 4a40 ldr r2, [pc, #256] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8429. 800370a: f443 2380 orr.w r3, r3, #262144 ; 0x40000
  8430. 800370e: 62d3 str r3, [r2, #44] ; 0x2c
  8431. /* Enable PLL1FRACN . */
  8432. __HAL_RCC_PLLFRACN_ENABLE();
  8433. 8003710: 4b3e ldr r3, [pc, #248] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8434. 8003712: 6adb ldr r3, [r3, #44] ; 0x2c
  8435. 8003714: 4a3d ldr r2, [pc, #244] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8436. 8003716: f043 0301 orr.w r3, r3, #1
  8437. 800371a: 62d3 str r3, [r2, #44] ; 0x2c
  8438. /* Enable the main PLL. */
  8439. __HAL_RCC_PLL_ENABLE();
  8440. 800371c: 4b3b ldr r3, [pc, #236] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8441. 800371e: 681b ldr r3, [r3, #0]
  8442. 8003720: 4a3a ldr r2, [pc, #232] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8443. 8003722: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
  8444. 8003726: 6013 str r3, [r2, #0]
  8445. /* Get Start Tick*/
  8446. tickstart = HAL_GetTick();
  8447. 8003728: f7fd ff96 bl 8001658 <HAL_GetTick>
  8448. 800372c: 6278 str r0, [r7, #36] ; 0x24
  8449. /* Wait till PLL is ready */
  8450. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
  8451. 800372e: e008 b.n 8003742 <HAL_RCC_OscConfig+0x682>
  8452. {
  8453. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  8454. 8003730: f7fd ff92 bl 8001658 <HAL_GetTick>
  8455. 8003734: 4602 mov r2, r0
  8456. 8003736: 6a7b ldr r3, [r7, #36] ; 0x24
  8457. 8003738: 1ad3 subs r3, r2, r3
  8458. 800373a: 2b02 cmp r3, #2
  8459. 800373c: d901 bls.n 8003742 <HAL_RCC_OscConfig+0x682>
  8460. {
  8461. return HAL_TIMEOUT;
  8462. 800373e: 2303 movs r3, #3
  8463. 8003740: e05f b.n 8003802 <HAL_RCC_OscConfig+0x742>
  8464. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
  8465. 8003742: 4b32 ldr r3, [pc, #200] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8466. 8003744: 681b ldr r3, [r3, #0]
  8467. 8003746: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
  8468. 800374a: 2b00 cmp r3, #0
  8469. 800374c: d0f0 beq.n 8003730 <HAL_RCC_OscConfig+0x670>
  8470. 800374e: e057 b.n 8003800 <HAL_RCC_OscConfig+0x740>
  8471. }
  8472. }
  8473. else
  8474. {
  8475. /* Disable the main PLL. */
  8476. __HAL_RCC_PLL_DISABLE();
  8477. 8003750: 4b2e ldr r3, [pc, #184] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8478. 8003752: 681b ldr r3, [r3, #0]
  8479. 8003754: 4a2d ldr r2, [pc, #180] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8480. 8003756: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
  8481. 800375a: 6013 str r3, [r2, #0]
  8482. /* Get Start Tick*/
  8483. tickstart = HAL_GetTick();
  8484. 800375c: f7fd ff7c bl 8001658 <HAL_GetTick>
  8485. 8003760: 6278 str r0, [r7, #36] ; 0x24
  8486. /* Wait till PLL is disabled */
  8487. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
  8488. 8003762: e008 b.n 8003776 <HAL_RCC_OscConfig+0x6b6>
  8489. {
  8490. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  8491. 8003764: f7fd ff78 bl 8001658 <HAL_GetTick>
  8492. 8003768: 4602 mov r2, r0
  8493. 800376a: 6a7b ldr r3, [r7, #36] ; 0x24
  8494. 800376c: 1ad3 subs r3, r2, r3
  8495. 800376e: 2b02 cmp r3, #2
  8496. 8003770: d901 bls.n 8003776 <HAL_RCC_OscConfig+0x6b6>
  8497. {
  8498. return HAL_TIMEOUT;
  8499. 8003772: 2303 movs r3, #3
  8500. 8003774: e045 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  8501. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
  8502. 8003776: 4b25 ldr r3, [pc, #148] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8503. 8003778: 681b ldr r3, [r3, #0]
  8504. 800377a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
  8505. 800377e: 2b00 cmp r3, #0
  8506. 8003780: d1f0 bne.n 8003764 <HAL_RCC_OscConfig+0x6a4>
  8507. 8003782: e03d b.n 8003800 <HAL_RCC_OscConfig+0x740>
  8508. }
  8509. }
  8510. else
  8511. {
  8512. /* Do not return HAL_ERROR if request repeats the current configuration */
  8513. temp1_pllckcfg = RCC->PLLCKSELR;
  8514. 8003784: 4b21 ldr r3, [pc, #132] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8515. 8003786: 6a9b ldr r3, [r3, #40] ; 0x28
  8516. 8003788: 613b str r3, [r7, #16]
  8517. temp2_pllckcfg = RCC->PLL1DIVR;
  8518. 800378a: 4b20 ldr r3, [pc, #128] ; (800380c <HAL_RCC_OscConfig+0x74c>)
  8519. 800378c: 6b1b ldr r3, [r3, #48] ; 0x30
  8520. 800378e: 60fb str r3, [r7, #12]
  8521. if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
  8522. 8003790: 687b ldr r3, [r7, #4]
  8523. 8003792: 6a5b ldr r3, [r3, #36] ; 0x24
  8524. 8003794: 2b01 cmp r3, #1
  8525. 8003796: d031 beq.n 80037fc <HAL_RCC_OscConfig+0x73c>
  8526. (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
  8527. 8003798: 693b ldr r3, [r7, #16]
  8528. 800379a: f003 0203 and.w r2, r3, #3
  8529. 800379e: 687b ldr r3, [r7, #4]
  8530. 80037a0: 6a9b ldr r3, [r3, #40] ; 0x28
  8531. if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
  8532. 80037a2: 429a cmp r2, r3
  8533. 80037a4: d12a bne.n 80037fc <HAL_RCC_OscConfig+0x73c>
  8534. ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
  8535. 80037a6: 693b ldr r3, [r7, #16]
  8536. 80037a8: 091b lsrs r3, r3, #4
  8537. 80037aa: f003 023f and.w r2, r3, #63 ; 0x3f
  8538. 80037ae: 687b ldr r3, [r7, #4]
  8539. 80037b0: 6adb ldr r3, [r3, #44] ; 0x2c
  8540. (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
  8541. 80037b2: 429a cmp r2, r3
  8542. 80037b4: d122 bne.n 80037fc <HAL_RCC_OscConfig+0x73c>
  8543. (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
  8544. 80037b6: 68fb ldr r3, [r7, #12]
  8545. 80037b8: f3c3 0208 ubfx r2, r3, #0, #9
  8546. 80037bc: 687b ldr r3, [r7, #4]
  8547. 80037be: 6b1b ldr r3, [r3, #48] ; 0x30
  8548. 80037c0: 3b01 subs r3, #1
  8549. ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
  8550. 80037c2: 429a cmp r2, r3
  8551. 80037c4: d11a bne.n 80037fc <HAL_RCC_OscConfig+0x73c>
  8552. ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
  8553. 80037c6: 68fb ldr r3, [r7, #12]
  8554. 80037c8: 0a5b lsrs r3, r3, #9
  8555. 80037ca: f003 027f and.w r2, r3, #127 ; 0x7f
  8556. 80037ce: 687b ldr r3, [r7, #4]
  8557. 80037d0: 6b5b ldr r3, [r3, #52] ; 0x34
  8558. 80037d2: 3b01 subs r3, #1
  8559. (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
  8560. 80037d4: 429a cmp r2, r3
  8561. 80037d6: d111 bne.n 80037fc <HAL_RCC_OscConfig+0x73c>
  8562. ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
  8563. 80037d8: 68fb ldr r3, [r7, #12]
  8564. 80037da: 0c1b lsrs r3, r3, #16
  8565. 80037dc: f003 027f and.w r2, r3, #127 ; 0x7f
  8566. 80037e0: 687b ldr r3, [r7, #4]
  8567. 80037e2: 6b9b ldr r3, [r3, #56] ; 0x38
  8568. 80037e4: 3b01 subs r3, #1
  8569. ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
  8570. 80037e6: 429a cmp r2, r3
  8571. 80037e8: d108 bne.n 80037fc <HAL_RCC_OscConfig+0x73c>
  8572. ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
  8573. 80037ea: 68fb ldr r3, [r7, #12]
  8574. 80037ec: 0e1b lsrs r3, r3, #24
  8575. 80037ee: f003 027f and.w r2, r3, #127 ; 0x7f
  8576. 80037f2: 687b ldr r3, [r7, #4]
  8577. 80037f4: 6bdb ldr r3, [r3, #60] ; 0x3c
  8578. 80037f6: 3b01 subs r3, #1
  8579. ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
  8580. 80037f8: 429a cmp r2, r3
  8581. 80037fa: d001 beq.n 8003800 <HAL_RCC_OscConfig+0x740>
  8582. {
  8583. return HAL_ERROR;
  8584. 80037fc: 2301 movs r3, #1
  8585. 80037fe: e000 b.n 8003802 <HAL_RCC_OscConfig+0x742>
  8586. }
  8587. }
  8588. }
  8589. return HAL_OK;
  8590. 8003800: 2300 movs r3, #0
  8591. }
  8592. 8003802: 4618 mov r0, r3
  8593. 8003804: 3730 adds r7, #48 ; 0x30
  8594. 8003806: 46bd mov sp, r7
  8595. 8003808: bd80 pop {r7, pc}
  8596. 800380a: bf00 nop
  8597. 800380c: 58024400 .word 0x58024400
  8598. 8003810: fffffc0c .word 0xfffffc0c
  8599. 8003814: ffff0007 .word 0xffff0007
  8600. 08003818 <HAL_RCC_ClockConfig>:
  8601. * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency
  8602. * (for more details refer to section above "Initialization/de-initialization functions")
  8603. * @retval None
  8604. */
  8605. HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
  8606. {
  8607. 8003818: b580 push {r7, lr}
  8608. 800381a: b086 sub sp, #24
  8609. 800381c: af00 add r7, sp, #0
  8610. 800381e: 6078 str r0, [r7, #4]
  8611. 8003820: 6039 str r1, [r7, #0]
  8612. HAL_StatusTypeDef halstatus;
  8613. uint32_t tickstart;
  8614. uint32_t common_system_clock;
  8615. /* Check Null pointer */
  8616. if(RCC_ClkInitStruct == NULL)
  8617. 8003822: 687b ldr r3, [r7, #4]
  8618. 8003824: 2b00 cmp r3, #0
  8619. 8003826: d101 bne.n 800382c <HAL_RCC_ClockConfig+0x14>
  8620. {
  8621. return HAL_ERROR;
  8622. 8003828: 2301 movs r3, #1
  8623. 800382a: e19c b.n 8003b66 <HAL_RCC_ClockConfig+0x34e>
  8624. /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
  8625. must be correctly programmed according to the frequency of the CPU clock
  8626. (HCLK) and the supply voltage of the device. */
  8627. /* Increasing the CPU frequency */
  8628. if(FLatency > __HAL_FLASH_GET_LATENCY())
  8629. 800382c: 4b8a ldr r3, [pc, #552] ; (8003a58 <HAL_RCC_ClockConfig+0x240>)
  8630. 800382e: 681b ldr r3, [r3, #0]
  8631. 8003830: f003 030f and.w r3, r3, #15
  8632. 8003834: 683a ldr r2, [r7, #0]
  8633. 8003836: 429a cmp r2, r3
  8634. 8003838: d910 bls.n 800385c <HAL_RCC_ClockConfig+0x44>
  8635. {
  8636. /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  8637. __HAL_FLASH_SET_LATENCY(FLatency);
  8638. 800383a: 4b87 ldr r3, [pc, #540] ; (8003a58 <HAL_RCC_ClockConfig+0x240>)
  8639. 800383c: 681b ldr r3, [r3, #0]
  8640. 800383e: f023 020f bic.w r2, r3, #15
  8641. 8003842: 4985 ldr r1, [pc, #532] ; (8003a58 <HAL_RCC_ClockConfig+0x240>)
  8642. 8003844: 683b ldr r3, [r7, #0]
  8643. 8003846: 4313 orrs r3, r2
  8644. 8003848: 600b str r3, [r1, #0]
  8645. /* Check that the new number of wait states is taken into account to access the Flash
  8646. memory by reading the FLASH_ACR register */
  8647. if(__HAL_FLASH_GET_LATENCY() != FLatency)
  8648. 800384a: 4b83 ldr r3, [pc, #524] ; (8003a58 <HAL_RCC_ClockConfig+0x240>)
  8649. 800384c: 681b ldr r3, [r3, #0]
  8650. 800384e: f003 030f and.w r3, r3, #15
  8651. 8003852: 683a ldr r2, [r7, #0]
  8652. 8003854: 429a cmp r2, r3
  8653. 8003856: d001 beq.n 800385c <HAL_RCC_ClockConfig+0x44>
  8654. {
  8655. return HAL_ERROR;
  8656. 8003858: 2301 movs r3, #1
  8657. 800385a: e184 b.n 8003b66 <HAL_RCC_ClockConfig+0x34e>
  8658. }
  8659. /* Increasing the BUS frequency divider */
  8660. /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
  8661. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
  8662. 800385c: 687b ldr r3, [r7, #4]
  8663. 800385e: 681b ldr r3, [r3, #0]
  8664. 8003860: f003 0304 and.w r3, r3, #4
  8665. 8003864: 2b00 cmp r3, #0
  8666. 8003866: d010 beq.n 800388a <HAL_RCC_ClockConfig+0x72>
  8667. {
  8668. #if defined (RCC_D1CFGR_D1PPRE)
  8669. if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
  8670. 8003868: 687b ldr r3, [r7, #4]
  8671. 800386a: 691a ldr r2, [r3, #16]
  8672. 800386c: 4b7b ldr r3, [pc, #492] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8673. 800386e: 699b ldr r3, [r3, #24]
  8674. 8003870: f003 0370 and.w r3, r3, #112 ; 0x70
  8675. 8003874: 429a cmp r2, r3
  8676. 8003876: d908 bls.n 800388a <HAL_RCC_ClockConfig+0x72>
  8677. {
  8678. assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
  8679. MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
  8680. 8003878: 4b78 ldr r3, [pc, #480] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8681. 800387a: 699b ldr r3, [r3, #24]
  8682. 800387c: f023 0270 bic.w r2, r3, #112 ; 0x70
  8683. 8003880: 687b ldr r3, [r7, #4]
  8684. 8003882: 691b ldr r3, [r3, #16]
  8685. 8003884: 4975 ldr r1, [pc, #468] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8686. 8003886: 4313 orrs r3, r2
  8687. 8003888: 618b str r3, [r1, #24]
  8688. }
  8689. #endif
  8690. }
  8691. /*-------------------------- PCLK1 Configuration ---------------------------*/
  8692. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  8693. 800388a: 687b ldr r3, [r7, #4]
  8694. 800388c: 681b ldr r3, [r3, #0]
  8695. 800388e: f003 0308 and.w r3, r3, #8
  8696. 8003892: 2b00 cmp r3, #0
  8697. 8003894: d010 beq.n 80038b8 <HAL_RCC_ClockConfig+0xa0>
  8698. {
  8699. #if defined (RCC_D2CFGR_D2PPRE1)
  8700. if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
  8701. 8003896: 687b ldr r3, [r7, #4]
  8702. 8003898: 695a ldr r2, [r3, #20]
  8703. 800389a: 4b70 ldr r3, [pc, #448] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8704. 800389c: 69db ldr r3, [r3, #28]
  8705. 800389e: f003 0370 and.w r3, r3, #112 ; 0x70
  8706. 80038a2: 429a cmp r2, r3
  8707. 80038a4: d908 bls.n 80038b8 <HAL_RCC_ClockConfig+0xa0>
  8708. {
  8709. assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
  8710. MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
  8711. 80038a6: 4b6d ldr r3, [pc, #436] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8712. 80038a8: 69db ldr r3, [r3, #28]
  8713. 80038aa: f023 0270 bic.w r2, r3, #112 ; 0x70
  8714. 80038ae: 687b ldr r3, [r7, #4]
  8715. 80038b0: 695b ldr r3, [r3, #20]
  8716. 80038b2: 496a ldr r1, [pc, #424] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8717. 80038b4: 4313 orrs r3, r2
  8718. 80038b6: 61cb str r3, [r1, #28]
  8719. MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
  8720. }
  8721. #endif
  8722. }
  8723. /*-------------------------- PCLK2 Configuration ---------------------------*/
  8724. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
  8725. 80038b8: 687b ldr r3, [r7, #4]
  8726. 80038ba: 681b ldr r3, [r3, #0]
  8727. 80038bc: f003 0310 and.w r3, r3, #16
  8728. 80038c0: 2b00 cmp r3, #0
  8729. 80038c2: d010 beq.n 80038e6 <HAL_RCC_ClockConfig+0xce>
  8730. {
  8731. #if defined(RCC_D2CFGR_D2PPRE2)
  8732. if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
  8733. 80038c4: 687b ldr r3, [r7, #4]
  8734. 80038c6: 699a ldr r2, [r3, #24]
  8735. 80038c8: 4b64 ldr r3, [pc, #400] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8736. 80038ca: 69db ldr r3, [r3, #28]
  8737. 80038cc: f403 63e0 and.w r3, r3, #1792 ; 0x700
  8738. 80038d0: 429a cmp r2, r3
  8739. 80038d2: d908 bls.n 80038e6 <HAL_RCC_ClockConfig+0xce>
  8740. {
  8741. assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
  8742. MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
  8743. 80038d4: 4b61 ldr r3, [pc, #388] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8744. 80038d6: 69db ldr r3, [r3, #28]
  8745. 80038d8: f423 62e0 bic.w r2, r3, #1792 ; 0x700
  8746. 80038dc: 687b ldr r3, [r7, #4]
  8747. 80038de: 699b ldr r3, [r3, #24]
  8748. 80038e0: 495e ldr r1, [pc, #376] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8749. 80038e2: 4313 orrs r3, r2
  8750. 80038e4: 61cb str r3, [r1, #28]
  8751. }
  8752. #endif
  8753. }
  8754. /*-------------------------- D3PCLK1 Configuration ---------------------------*/
  8755. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
  8756. 80038e6: 687b ldr r3, [r7, #4]
  8757. 80038e8: 681b ldr r3, [r3, #0]
  8758. 80038ea: f003 0320 and.w r3, r3, #32
  8759. 80038ee: 2b00 cmp r3, #0
  8760. 80038f0: d010 beq.n 8003914 <HAL_RCC_ClockConfig+0xfc>
  8761. {
  8762. #if defined(RCC_D3CFGR_D3PPRE)
  8763. if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
  8764. 80038f2: 687b ldr r3, [r7, #4]
  8765. 80038f4: 69da ldr r2, [r3, #28]
  8766. 80038f6: 4b59 ldr r3, [pc, #356] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8767. 80038f8: 6a1b ldr r3, [r3, #32]
  8768. 80038fa: f003 0370 and.w r3, r3, #112 ; 0x70
  8769. 80038fe: 429a cmp r2, r3
  8770. 8003900: d908 bls.n 8003914 <HAL_RCC_ClockConfig+0xfc>
  8771. {
  8772. assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
  8773. MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
  8774. 8003902: 4b56 ldr r3, [pc, #344] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8775. 8003904: 6a1b ldr r3, [r3, #32]
  8776. 8003906: f023 0270 bic.w r2, r3, #112 ; 0x70
  8777. 800390a: 687b ldr r3, [r7, #4]
  8778. 800390c: 69db ldr r3, [r3, #28]
  8779. 800390e: 4953 ldr r1, [pc, #332] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8780. 8003910: 4313 orrs r3, r2
  8781. 8003912: 620b str r3, [r1, #32]
  8782. }
  8783. #endif
  8784. }
  8785. /*-------------------------- HCLK Configuration --------------------------*/
  8786. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
  8787. 8003914: 687b ldr r3, [r7, #4]
  8788. 8003916: 681b ldr r3, [r3, #0]
  8789. 8003918: f003 0302 and.w r3, r3, #2
  8790. 800391c: 2b00 cmp r3, #0
  8791. 800391e: d010 beq.n 8003942 <HAL_RCC_ClockConfig+0x12a>
  8792. {
  8793. #if defined (RCC_D1CFGR_HPRE)
  8794. if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
  8795. 8003920: 687b ldr r3, [r7, #4]
  8796. 8003922: 68da ldr r2, [r3, #12]
  8797. 8003924: 4b4d ldr r3, [pc, #308] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8798. 8003926: 699b ldr r3, [r3, #24]
  8799. 8003928: f003 030f and.w r3, r3, #15
  8800. 800392c: 429a cmp r2, r3
  8801. 800392e: d908 bls.n 8003942 <HAL_RCC_ClockConfig+0x12a>
  8802. {
  8803. /* Set the new HCLK clock divider */
  8804. assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
  8805. MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
  8806. 8003930: 4b4a ldr r3, [pc, #296] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8807. 8003932: 699b ldr r3, [r3, #24]
  8808. 8003934: f023 020f bic.w r2, r3, #15
  8809. 8003938: 687b ldr r3, [r7, #4]
  8810. 800393a: 68db ldr r3, [r3, #12]
  8811. 800393c: 4947 ldr r1, [pc, #284] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8812. 800393e: 4313 orrs r3, r2
  8813. 8003940: 618b str r3, [r1, #24]
  8814. }
  8815. #endif
  8816. }
  8817. /*------------------------- SYSCLK Configuration -------------------------*/
  8818. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
  8819. 8003942: 687b ldr r3, [r7, #4]
  8820. 8003944: 681b ldr r3, [r3, #0]
  8821. 8003946: f003 0301 and.w r3, r3, #1
  8822. 800394a: 2b00 cmp r3, #0
  8823. 800394c: d055 beq.n 80039fa <HAL_RCC_ClockConfig+0x1e2>
  8824. {
  8825. assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
  8826. assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
  8827. #if defined(RCC_D1CFGR_D1CPRE)
  8828. MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
  8829. 800394e: 4b43 ldr r3, [pc, #268] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8830. 8003950: 699b ldr r3, [r3, #24]
  8831. 8003952: f423 6270 bic.w r2, r3, #3840 ; 0xf00
  8832. 8003956: 687b ldr r3, [r7, #4]
  8833. 8003958: 689b ldr r3, [r3, #8]
  8834. 800395a: 4940 ldr r1, [pc, #256] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8835. 800395c: 4313 orrs r3, r2
  8836. 800395e: 618b str r3, [r1, #24]
  8837. #else
  8838. MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
  8839. #endif
  8840. /* HSE is selected as System Clock Source */
  8841. if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  8842. 8003960: 687b ldr r3, [r7, #4]
  8843. 8003962: 685b ldr r3, [r3, #4]
  8844. 8003964: 2b02 cmp r3, #2
  8845. 8003966: d107 bne.n 8003978 <HAL_RCC_ClockConfig+0x160>
  8846. {
  8847. /* Check the HSE ready flag */
  8848. if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
  8849. 8003968: 4b3c ldr r3, [pc, #240] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8850. 800396a: 681b ldr r3, [r3, #0]
  8851. 800396c: f403 3300 and.w r3, r3, #131072 ; 0x20000
  8852. 8003970: 2b00 cmp r3, #0
  8853. 8003972: d121 bne.n 80039b8 <HAL_RCC_ClockConfig+0x1a0>
  8854. {
  8855. return HAL_ERROR;
  8856. 8003974: 2301 movs r3, #1
  8857. 8003976: e0f6 b.n 8003b66 <HAL_RCC_ClockConfig+0x34e>
  8858. }
  8859. }
  8860. /* PLL is selected as System Clock Source */
  8861. else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  8862. 8003978: 687b ldr r3, [r7, #4]
  8863. 800397a: 685b ldr r3, [r3, #4]
  8864. 800397c: 2b03 cmp r3, #3
  8865. 800397e: d107 bne.n 8003990 <HAL_RCC_ClockConfig+0x178>
  8866. {
  8867. /* Check the PLL ready flag */
  8868. if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
  8869. 8003980: 4b36 ldr r3, [pc, #216] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8870. 8003982: 681b ldr r3, [r3, #0]
  8871. 8003984: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
  8872. 8003988: 2b00 cmp r3, #0
  8873. 800398a: d115 bne.n 80039b8 <HAL_RCC_ClockConfig+0x1a0>
  8874. {
  8875. return HAL_ERROR;
  8876. 800398c: 2301 movs r3, #1
  8877. 800398e: e0ea b.n 8003b66 <HAL_RCC_ClockConfig+0x34e>
  8878. }
  8879. }
  8880. /* CSI is selected as System Clock Source */
  8881. else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
  8882. 8003990: 687b ldr r3, [r7, #4]
  8883. 8003992: 685b ldr r3, [r3, #4]
  8884. 8003994: 2b01 cmp r3, #1
  8885. 8003996: d107 bne.n 80039a8 <HAL_RCC_ClockConfig+0x190>
  8886. {
  8887. /* Check the PLL ready flag */
  8888. if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
  8889. 8003998: 4b30 ldr r3, [pc, #192] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8890. 800399a: 681b ldr r3, [r3, #0]
  8891. 800399c: f403 7380 and.w r3, r3, #256 ; 0x100
  8892. 80039a0: 2b00 cmp r3, #0
  8893. 80039a2: d109 bne.n 80039b8 <HAL_RCC_ClockConfig+0x1a0>
  8894. {
  8895. return HAL_ERROR;
  8896. 80039a4: 2301 movs r3, #1
  8897. 80039a6: e0de b.n 8003b66 <HAL_RCC_ClockConfig+0x34e>
  8898. }
  8899. /* HSI is selected as System Clock Source */
  8900. else
  8901. {
  8902. /* Check the HSI ready flag */
  8903. if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  8904. 80039a8: 4b2c ldr r3, [pc, #176] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8905. 80039aa: 681b ldr r3, [r3, #0]
  8906. 80039ac: f003 0304 and.w r3, r3, #4
  8907. 80039b0: 2b00 cmp r3, #0
  8908. 80039b2: d101 bne.n 80039b8 <HAL_RCC_ClockConfig+0x1a0>
  8909. {
  8910. return HAL_ERROR;
  8911. 80039b4: 2301 movs r3, #1
  8912. 80039b6: e0d6 b.n 8003b66 <HAL_RCC_ClockConfig+0x34e>
  8913. }
  8914. }
  8915. MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
  8916. 80039b8: 4b28 ldr r3, [pc, #160] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8917. 80039ba: 691b ldr r3, [r3, #16]
  8918. 80039bc: f023 0207 bic.w r2, r3, #7
  8919. 80039c0: 687b ldr r3, [r7, #4]
  8920. 80039c2: 685b ldr r3, [r3, #4]
  8921. 80039c4: 4925 ldr r1, [pc, #148] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8922. 80039c6: 4313 orrs r3, r2
  8923. 80039c8: 610b str r3, [r1, #16]
  8924. /* Get Start Tick*/
  8925. tickstart = HAL_GetTick();
  8926. 80039ca: f7fd fe45 bl 8001658 <HAL_GetTick>
  8927. 80039ce: 6178 str r0, [r7, #20]
  8928. while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
  8929. 80039d0: e00a b.n 80039e8 <HAL_RCC_ClockConfig+0x1d0>
  8930. {
  8931. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  8932. 80039d2: f7fd fe41 bl 8001658 <HAL_GetTick>
  8933. 80039d6: 4602 mov r2, r0
  8934. 80039d8: 697b ldr r3, [r7, #20]
  8935. 80039da: 1ad3 subs r3, r2, r3
  8936. 80039dc: f241 3288 movw r2, #5000 ; 0x1388
  8937. 80039e0: 4293 cmp r3, r2
  8938. 80039e2: d901 bls.n 80039e8 <HAL_RCC_ClockConfig+0x1d0>
  8939. {
  8940. return HAL_TIMEOUT;
  8941. 80039e4: 2303 movs r3, #3
  8942. 80039e6: e0be b.n 8003b66 <HAL_RCC_ClockConfig+0x34e>
  8943. while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
  8944. 80039e8: 4b1c ldr r3, [pc, #112] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8945. 80039ea: 691b ldr r3, [r3, #16]
  8946. 80039ec: f003 0238 and.w r2, r3, #56 ; 0x38
  8947. 80039f0: 687b ldr r3, [r7, #4]
  8948. 80039f2: 685b ldr r3, [r3, #4]
  8949. 80039f4: 00db lsls r3, r3, #3
  8950. 80039f6: 429a cmp r2, r3
  8951. 80039f8: d1eb bne.n 80039d2 <HAL_RCC_ClockConfig+0x1ba>
  8952. }
  8953. /* Decreasing the BUS frequency divider */
  8954. /*-------------------------- HCLK Configuration --------------------------*/
  8955. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
  8956. 80039fa: 687b ldr r3, [r7, #4]
  8957. 80039fc: 681b ldr r3, [r3, #0]
  8958. 80039fe: f003 0302 and.w r3, r3, #2
  8959. 8003a02: 2b00 cmp r3, #0
  8960. 8003a04: d010 beq.n 8003a28 <HAL_RCC_ClockConfig+0x210>
  8961. {
  8962. #if defined(RCC_D1CFGR_HPRE)
  8963. if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
  8964. 8003a06: 687b ldr r3, [r7, #4]
  8965. 8003a08: 68da ldr r2, [r3, #12]
  8966. 8003a0a: 4b14 ldr r3, [pc, #80] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8967. 8003a0c: 699b ldr r3, [r3, #24]
  8968. 8003a0e: f003 030f and.w r3, r3, #15
  8969. 8003a12: 429a cmp r2, r3
  8970. 8003a14: d208 bcs.n 8003a28 <HAL_RCC_ClockConfig+0x210>
  8971. {
  8972. /* Set the new HCLK clock divider */
  8973. assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
  8974. MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
  8975. 8003a16: 4b11 ldr r3, [pc, #68] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8976. 8003a18: 699b ldr r3, [r3, #24]
  8977. 8003a1a: f023 020f bic.w r2, r3, #15
  8978. 8003a1e: 687b ldr r3, [r7, #4]
  8979. 8003a20: 68db ldr r3, [r3, #12]
  8980. 8003a22: 490e ldr r1, [pc, #56] ; (8003a5c <HAL_RCC_ClockConfig+0x244>)
  8981. 8003a24: 4313 orrs r3, r2
  8982. 8003a26: 618b str r3, [r1, #24]
  8983. }
  8984. #endif
  8985. }
  8986. /* Decreasing the number of wait states because of lower CPU frequency */
  8987. if(FLatency < __HAL_FLASH_GET_LATENCY())
  8988. 8003a28: 4b0b ldr r3, [pc, #44] ; (8003a58 <HAL_RCC_ClockConfig+0x240>)
  8989. 8003a2a: 681b ldr r3, [r3, #0]
  8990. 8003a2c: f003 030f and.w r3, r3, #15
  8991. 8003a30: 683a ldr r2, [r7, #0]
  8992. 8003a32: 429a cmp r2, r3
  8993. 8003a34: d214 bcs.n 8003a60 <HAL_RCC_ClockConfig+0x248>
  8994. {
  8995. /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  8996. __HAL_FLASH_SET_LATENCY(FLatency);
  8997. 8003a36: 4b08 ldr r3, [pc, #32] ; (8003a58 <HAL_RCC_ClockConfig+0x240>)
  8998. 8003a38: 681b ldr r3, [r3, #0]
  8999. 8003a3a: f023 020f bic.w r2, r3, #15
  9000. 8003a3e: 4906 ldr r1, [pc, #24] ; (8003a58 <HAL_RCC_ClockConfig+0x240>)
  9001. 8003a40: 683b ldr r3, [r7, #0]
  9002. 8003a42: 4313 orrs r3, r2
  9003. 8003a44: 600b str r3, [r1, #0]
  9004. /* Check that the new number of wait states is taken into account to access the Flash
  9005. memory by reading the FLASH_ACR register */
  9006. if(__HAL_FLASH_GET_LATENCY() != FLatency)
  9007. 8003a46: 4b04 ldr r3, [pc, #16] ; (8003a58 <HAL_RCC_ClockConfig+0x240>)
  9008. 8003a48: 681b ldr r3, [r3, #0]
  9009. 8003a4a: f003 030f and.w r3, r3, #15
  9010. 8003a4e: 683a ldr r2, [r7, #0]
  9011. 8003a50: 429a cmp r2, r3
  9012. 8003a52: d005 beq.n 8003a60 <HAL_RCC_ClockConfig+0x248>
  9013. {
  9014. return HAL_ERROR;
  9015. 8003a54: 2301 movs r3, #1
  9016. 8003a56: e086 b.n 8003b66 <HAL_RCC_ClockConfig+0x34e>
  9017. 8003a58: 52002000 .word 0x52002000
  9018. 8003a5c: 58024400 .word 0x58024400
  9019. }
  9020. }
  9021. /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
  9022. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
  9023. 8003a60: 687b ldr r3, [r7, #4]
  9024. 8003a62: 681b ldr r3, [r3, #0]
  9025. 8003a64: f003 0304 and.w r3, r3, #4
  9026. 8003a68: 2b00 cmp r3, #0
  9027. 8003a6a: d010 beq.n 8003a8e <HAL_RCC_ClockConfig+0x276>
  9028. {
  9029. #if defined(RCC_D1CFGR_D1PPRE)
  9030. if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
  9031. 8003a6c: 687b ldr r3, [r7, #4]
  9032. 8003a6e: 691a ldr r2, [r3, #16]
  9033. 8003a70: 4b3f ldr r3, [pc, #252] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9034. 8003a72: 699b ldr r3, [r3, #24]
  9035. 8003a74: f003 0370 and.w r3, r3, #112 ; 0x70
  9036. 8003a78: 429a cmp r2, r3
  9037. 8003a7a: d208 bcs.n 8003a8e <HAL_RCC_ClockConfig+0x276>
  9038. {
  9039. assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
  9040. MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
  9041. 8003a7c: 4b3c ldr r3, [pc, #240] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9042. 8003a7e: 699b ldr r3, [r3, #24]
  9043. 8003a80: f023 0270 bic.w r2, r3, #112 ; 0x70
  9044. 8003a84: 687b ldr r3, [r7, #4]
  9045. 8003a86: 691b ldr r3, [r3, #16]
  9046. 8003a88: 4939 ldr r1, [pc, #228] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9047. 8003a8a: 4313 orrs r3, r2
  9048. 8003a8c: 618b str r3, [r1, #24]
  9049. }
  9050. #endif
  9051. }
  9052. /*-------------------------- PCLK1 Configuration ---------------------------*/
  9053. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  9054. 8003a8e: 687b ldr r3, [r7, #4]
  9055. 8003a90: 681b ldr r3, [r3, #0]
  9056. 8003a92: f003 0308 and.w r3, r3, #8
  9057. 8003a96: 2b00 cmp r3, #0
  9058. 8003a98: d010 beq.n 8003abc <HAL_RCC_ClockConfig+0x2a4>
  9059. {
  9060. #if defined(RCC_D2CFGR_D2PPRE1)
  9061. if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
  9062. 8003a9a: 687b ldr r3, [r7, #4]
  9063. 8003a9c: 695a ldr r2, [r3, #20]
  9064. 8003a9e: 4b34 ldr r3, [pc, #208] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9065. 8003aa0: 69db ldr r3, [r3, #28]
  9066. 8003aa2: f003 0370 and.w r3, r3, #112 ; 0x70
  9067. 8003aa6: 429a cmp r2, r3
  9068. 8003aa8: d208 bcs.n 8003abc <HAL_RCC_ClockConfig+0x2a4>
  9069. {
  9070. assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
  9071. MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
  9072. 8003aaa: 4b31 ldr r3, [pc, #196] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9073. 8003aac: 69db ldr r3, [r3, #28]
  9074. 8003aae: f023 0270 bic.w r2, r3, #112 ; 0x70
  9075. 8003ab2: 687b ldr r3, [r7, #4]
  9076. 8003ab4: 695b ldr r3, [r3, #20]
  9077. 8003ab6: 492e ldr r1, [pc, #184] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9078. 8003ab8: 4313 orrs r3, r2
  9079. 8003aba: 61cb str r3, [r1, #28]
  9080. }
  9081. #endif
  9082. }
  9083. /*-------------------------- PCLK2 Configuration ---------------------------*/
  9084. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
  9085. 8003abc: 687b ldr r3, [r7, #4]
  9086. 8003abe: 681b ldr r3, [r3, #0]
  9087. 8003ac0: f003 0310 and.w r3, r3, #16
  9088. 8003ac4: 2b00 cmp r3, #0
  9089. 8003ac6: d010 beq.n 8003aea <HAL_RCC_ClockConfig+0x2d2>
  9090. {
  9091. #if defined (RCC_D2CFGR_D2PPRE2)
  9092. if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
  9093. 8003ac8: 687b ldr r3, [r7, #4]
  9094. 8003aca: 699a ldr r2, [r3, #24]
  9095. 8003acc: 4b28 ldr r3, [pc, #160] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9096. 8003ace: 69db ldr r3, [r3, #28]
  9097. 8003ad0: f403 63e0 and.w r3, r3, #1792 ; 0x700
  9098. 8003ad4: 429a cmp r2, r3
  9099. 8003ad6: d208 bcs.n 8003aea <HAL_RCC_ClockConfig+0x2d2>
  9100. {
  9101. assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
  9102. MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
  9103. 8003ad8: 4b25 ldr r3, [pc, #148] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9104. 8003ada: 69db ldr r3, [r3, #28]
  9105. 8003adc: f423 62e0 bic.w r2, r3, #1792 ; 0x700
  9106. 8003ae0: 687b ldr r3, [r7, #4]
  9107. 8003ae2: 699b ldr r3, [r3, #24]
  9108. 8003ae4: 4922 ldr r1, [pc, #136] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9109. 8003ae6: 4313 orrs r3, r2
  9110. 8003ae8: 61cb str r3, [r1, #28]
  9111. }
  9112. #endif
  9113. }
  9114. /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
  9115. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
  9116. 8003aea: 687b ldr r3, [r7, #4]
  9117. 8003aec: 681b ldr r3, [r3, #0]
  9118. 8003aee: f003 0320 and.w r3, r3, #32
  9119. 8003af2: 2b00 cmp r3, #0
  9120. 8003af4: d010 beq.n 8003b18 <HAL_RCC_ClockConfig+0x300>
  9121. {
  9122. #if defined(RCC_D3CFGR_D3PPRE)
  9123. if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
  9124. 8003af6: 687b ldr r3, [r7, #4]
  9125. 8003af8: 69da ldr r2, [r3, #28]
  9126. 8003afa: 4b1d ldr r3, [pc, #116] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9127. 8003afc: 6a1b ldr r3, [r3, #32]
  9128. 8003afe: f003 0370 and.w r3, r3, #112 ; 0x70
  9129. 8003b02: 429a cmp r2, r3
  9130. 8003b04: d208 bcs.n 8003b18 <HAL_RCC_ClockConfig+0x300>
  9131. {
  9132. assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
  9133. MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
  9134. 8003b06: 4b1a ldr r3, [pc, #104] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9135. 8003b08: 6a1b ldr r3, [r3, #32]
  9136. 8003b0a: f023 0270 bic.w r2, r3, #112 ; 0x70
  9137. 8003b0e: 687b ldr r3, [r7, #4]
  9138. 8003b10: 69db ldr r3, [r3, #28]
  9139. 8003b12: 4917 ldr r1, [pc, #92] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9140. 8003b14: 4313 orrs r3, r2
  9141. 8003b16: 620b str r3, [r1, #32]
  9142. #endif
  9143. }
  9144. /* Update the SystemCoreClock global variable */
  9145. #if defined(RCC_D1CFGR_D1CPRE)
  9146. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  9147. 8003b18: f000 f834 bl 8003b84 <HAL_RCC_GetSysClockFreq>
  9148. 8003b1c: 4602 mov r2, r0
  9149. 8003b1e: 4b14 ldr r3, [pc, #80] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9150. 8003b20: 699b ldr r3, [r3, #24]
  9151. 8003b22: 0a1b lsrs r3, r3, #8
  9152. 8003b24: f003 030f and.w r3, r3, #15
  9153. 8003b28: 4912 ldr r1, [pc, #72] ; (8003b74 <HAL_RCC_ClockConfig+0x35c>)
  9154. 8003b2a: 5ccb ldrb r3, [r1, r3]
  9155. 8003b2c: f003 031f and.w r3, r3, #31
  9156. 8003b30: fa22 f303 lsr.w r3, r2, r3
  9157. 8003b34: 613b str r3, [r7, #16]
  9158. #else
  9159. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
  9160. #endif
  9161. #if defined(RCC_D1CFGR_HPRE)
  9162. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  9163. 8003b36: 4b0e ldr r3, [pc, #56] ; (8003b70 <HAL_RCC_ClockConfig+0x358>)
  9164. 8003b38: 699b ldr r3, [r3, #24]
  9165. 8003b3a: f003 030f and.w r3, r3, #15
  9166. 8003b3e: 4a0d ldr r2, [pc, #52] ; (8003b74 <HAL_RCC_ClockConfig+0x35c>)
  9167. 8003b40: 5cd3 ldrb r3, [r2, r3]
  9168. 8003b42: f003 031f and.w r3, r3, #31
  9169. 8003b46: 693a ldr r2, [r7, #16]
  9170. 8003b48: fa22 f303 lsr.w r3, r2, r3
  9171. 8003b4c: 4a0a ldr r2, [pc, #40] ; (8003b78 <HAL_RCC_ClockConfig+0x360>)
  9172. 8003b4e: 6013 str r3, [r2, #0]
  9173. #endif
  9174. #if defined(DUAL_CORE) && defined(CORE_CM4)
  9175. SystemCoreClock = SystemD2Clock;
  9176. #else
  9177. SystemCoreClock = common_system_clock;
  9178. 8003b50: 4a0a ldr r2, [pc, #40] ; (8003b7c <HAL_RCC_ClockConfig+0x364>)
  9179. 8003b52: 693b ldr r3, [r7, #16]
  9180. 8003b54: 6013 str r3, [r2, #0]
  9181. #endif /* DUAL_CORE && CORE_CM4 */
  9182. /* Configure the source of time base considering new system clocks settings*/
  9183. halstatus = HAL_InitTick (uwTickPrio);
  9184. 8003b56: 4b0a ldr r3, [pc, #40] ; (8003b80 <HAL_RCC_ClockConfig+0x368>)
  9185. 8003b58: 681b ldr r3, [r3, #0]
  9186. 8003b5a: 4618 mov r0, r3
  9187. 8003b5c: f7fd fd32 bl 80015c4 <HAL_InitTick>
  9188. 8003b60: 4603 mov r3, r0
  9189. 8003b62: 73fb strb r3, [r7, #15]
  9190. return halstatus;
  9191. 8003b64: 7bfb ldrb r3, [r7, #15]
  9192. }
  9193. 8003b66: 4618 mov r0, r3
  9194. 8003b68: 3718 adds r7, #24
  9195. 8003b6a: 46bd mov sp, r7
  9196. 8003b6c: bd80 pop {r7, pc}
  9197. 8003b6e: bf00 nop
  9198. 8003b70: 58024400 .word 0x58024400
  9199. 8003b74: 0800aa10 .word 0x0800aa10
  9200. 8003b78: 24000004 .word 0x24000004
  9201. 8003b7c: 24000000 .word 0x24000000
  9202. 8003b80: 24000008 .word 0x24000008
  9203. 08003b84 <HAL_RCC_GetSysClockFreq>:
  9204. *
  9205. *
  9206. * @retval SYSCLK frequency
  9207. */
  9208. uint32_t HAL_RCC_GetSysClockFreq(void)
  9209. {
  9210. 8003b84: b480 push {r7}
  9211. 8003b86: b089 sub sp, #36 ; 0x24
  9212. 8003b88: af00 add r7, sp, #0
  9213. float_t fracn1, pllvco;
  9214. uint32_t sysclockfreq;
  9215. /* Get SYSCLK source -------------------------------------------------------*/
  9216. switch (RCC->CFGR & RCC_CFGR_SWS)
  9217. 8003b8a: 4bb3 ldr r3, [pc, #716] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9218. 8003b8c: 691b ldr r3, [r3, #16]
  9219. 8003b8e: f003 0338 and.w r3, r3, #56 ; 0x38
  9220. 8003b92: 2b18 cmp r3, #24
  9221. 8003b94: f200 8155 bhi.w 8003e42 <HAL_RCC_GetSysClockFreq+0x2be>
  9222. 8003b98: a201 add r2, pc, #4 ; (adr r2, 8003ba0 <HAL_RCC_GetSysClockFreq+0x1c>)
  9223. 8003b9a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  9224. 8003b9e: bf00 nop
  9225. 8003ba0: 08003c05 .word 0x08003c05
  9226. 8003ba4: 08003e43 .word 0x08003e43
  9227. 8003ba8: 08003e43 .word 0x08003e43
  9228. 8003bac: 08003e43 .word 0x08003e43
  9229. 8003bb0: 08003e43 .word 0x08003e43
  9230. 8003bb4: 08003e43 .word 0x08003e43
  9231. 8003bb8: 08003e43 .word 0x08003e43
  9232. 8003bbc: 08003e43 .word 0x08003e43
  9233. 8003bc0: 08003c2b .word 0x08003c2b
  9234. 8003bc4: 08003e43 .word 0x08003e43
  9235. 8003bc8: 08003e43 .word 0x08003e43
  9236. 8003bcc: 08003e43 .word 0x08003e43
  9237. 8003bd0: 08003e43 .word 0x08003e43
  9238. 8003bd4: 08003e43 .word 0x08003e43
  9239. 8003bd8: 08003e43 .word 0x08003e43
  9240. 8003bdc: 08003e43 .word 0x08003e43
  9241. 8003be0: 08003c31 .word 0x08003c31
  9242. 8003be4: 08003e43 .word 0x08003e43
  9243. 8003be8: 08003e43 .word 0x08003e43
  9244. 8003bec: 08003e43 .word 0x08003e43
  9245. 8003bf0: 08003e43 .word 0x08003e43
  9246. 8003bf4: 08003e43 .word 0x08003e43
  9247. 8003bf8: 08003e43 .word 0x08003e43
  9248. 8003bfc: 08003e43 .word 0x08003e43
  9249. 8003c00: 08003c37 .word 0x08003c37
  9250. {
  9251. case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
  9252. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  9253. 8003c04: 4b94 ldr r3, [pc, #592] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9254. 8003c06: 681b ldr r3, [r3, #0]
  9255. 8003c08: f003 0320 and.w r3, r3, #32
  9256. 8003c0c: 2b00 cmp r3, #0
  9257. 8003c0e: d009 beq.n 8003c24 <HAL_RCC_GetSysClockFreq+0xa0>
  9258. {
  9259. sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
  9260. 8003c10: 4b91 ldr r3, [pc, #580] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9261. 8003c12: 681b ldr r3, [r3, #0]
  9262. 8003c14: 08db lsrs r3, r3, #3
  9263. 8003c16: f003 0303 and.w r3, r3, #3
  9264. 8003c1a: 4a90 ldr r2, [pc, #576] ; (8003e5c <HAL_RCC_GetSysClockFreq+0x2d8>)
  9265. 8003c1c: fa22 f303 lsr.w r3, r2, r3
  9266. 8003c20: 61bb str r3, [r7, #24]
  9267. else
  9268. {
  9269. sysclockfreq = (uint32_t) HSI_VALUE;
  9270. }
  9271. break;
  9272. 8003c22: e111 b.n 8003e48 <HAL_RCC_GetSysClockFreq+0x2c4>
  9273. sysclockfreq = (uint32_t) HSI_VALUE;
  9274. 8003c24: 4b8d ldr r3, [pc, #564] ; (8003e5c <HAL_RCC_GetSysClockFreq+0x2d8>)
  9275. 8003c26: 61bb str r3, [r7, #24]
  9276. break;
  9277. 8003c28: e10e b.n 8003e48 <HAL_RCC_GetSysClockFreq+0x2c4>
  9278. case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
  9279. sysclockfreq = CSI_VALUE;
  9280. 8003c2a: 4b8d ldr r3, [pc, #564] ; (8003e60 <HAL_RCC_GetSysClockFreq+0x2dc>)
  9281. 8003c2c: 61bb str r3, [r7, #24]
  9282. break;
  9283. 8003c2e: e10b b.n 8003e48 <HAL_RCC_GetSysClockFreq+0x2c4>
  9284. case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
  9285. sysclockfreq = HSE_VALUE;
  9286. 8003c30: 4b8c ldr r3, [pc, #560] ; (8003e64 <HAL_RCC_GetSysClockFreq+0x2e0>)
  9287. 8003c32: 61bb str r3, [r7, #24]
  9288. break;
  9289. 8003c34: e108 b.n 8003e48 <HAL_RCC_GetSysClockFreq+0x2c4>
  9290. case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
  9291. /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
  9292. SYSCLK = PLL_VCO / PLLR
  9293. */
  9294. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  9295. 8003c36: 4b88 ldr r3, [pc, #544] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9296. 8003c38: 6a9b ldr r3, [r3, #40] ; 0x28
  9297. 8003c3a: f003 0303 and.w r3, r3, #3
  9298. 8003c3e: 617b str r3, [r7, #20]
  9299. pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
  9300. 8003c40: 4b85 ldr r3, [pc, #532] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9301. 8003c42: 6a9b ldr r3, [r3, #40] ; 0x28
  9302. 8003c44: 091b lsrs r3, r3, #4
  9303. 8003c46: f003 033f and.w r3, r3, #63 ; 0x3f
  9304. 8003c4a: 613b str r3, [r7, #16]
  9305. pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
  9306. 8003c4c: 4b82 ldr r3, [pc, #520] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9307. 8003c4e: 6adb ldr r3, [r3, #44] ; 0x2c
  9308. 8003c50: f003 0301 and.w r3, r3, #1
  9309. 8003c54: 60fb str r3, [r7, #12]
  9310. fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
  9311. 8003c56: 4b80 ldr r3, [pc, #512] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9312. 8003c58: 6b5b ldr r3, [r3, #52] ; 0x34
  9313. 8003c5a: 08db lsrs r3, r3, #3
  9314. 8003c5c: f3c3 030c ubfx r3, r3, #0, #13
  9315. 8003c60: 68fa ldr r2, [r7, #12]
  9316. 8003c62: fb02 f303 mul.w r3, r2, r3
  9317. 8003c66: ee07 3a90 vmov s15, r3
  9318. 8003c6a: eef8 7a67 vcvt.f32.u32 s15, s15
  9319. 8003c6e: edc7 7a02 vstr s15, [r7, #8]
  9320. if (pllm != 0U)
  9321. 8003c72: 693b ldr r3, [r7, #16]
  9322. 8003c74: 2b00 cmp r3, #0
  9323. 8003c76: f000 80e1 beq.w 8003e3c <HAL_RCC_GetSysClockFreq+0x2b8>
  9324. 8003c7a: 697b ldr r3, [r7, #20]
  9325. 8003c7c: 2b02 cmp r3, #2
  9326. 8003c7e: f000 8083 beq.w 8003d88 <HAL_RCC_GetSysClockFreq+0x204>
  9327. 8003c82: 697b ldr r3, [r7, #20]
  9328. 8003c84: 2b02 cmp r3, #2
  9329. 8003c86: f200 80a1 bhi.w 8003dcc <HAL_RCC_GetSysClockFreq+0x248>
  9330. 8003c8a: 697b ldr r3, [r7, #20]
  9331. 8003c8c: 2b00 cmp r3, #0
  9332. 8003c8e: d003 beq.n 8003c98 <HAL_RCC_GetSysClockFreq+0x114>
  9333. 8003c90: 697b ldr r3, [r7, #20]
  9334. 8003c92: 2b01 cmp r3, #1
  9335. 8003c94: d056 beq.n 8003d44 <HAL_RCC_GetSysClockFreq+0x1c0>
  9336. 8003c96: e099 b.n 8003dcc <HAL_RCC_GetSysClockFreq+0x248>
  9337. {
  9338. switch (pllsource)
  9339. {
  9340. case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
  9341. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  9342. 8003c98: 4b6f ldr r3, [pc, #444] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9343. 8003c9a: 681b ldr r3, [r3, #0]
  9344. 8003c9c: f003 0320 and.w r3, r3, #32
  9345. 8003ca0: 2b00 cmp r3, #0
  9346. 8003ca2: d02d beq.n 8003d00 <HAL_RCC_GetSysClockFreq+0x17c>
  9347. {
  9348. hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
  9349. 8003ca4: 4b6c ldr r3, [pc, #432] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9350. 8003ca6: 681b ldr r3, [r3, #0]
  9351. 8003ca8: 08db lsrs r3, r3, #3
  9352. 8003caa: f003 0303 and.w r3, r3, #3
  9353. 8003cae: 4a6b ldr r2, [pc, #428] ; (8003e5c <HAL_RCC_GetSysClockFreq+0x2d8>)
  9354. 8003cb0: fa22 f303 lsr.w r3, r2, r3
  9355. 8003cb4: 607b str r3, [r7, #4]
  9356. pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
  9357. 8003cb6: 687b ldr r3, [r7, #4]
  9358. 8003cb8: ee07 3a90 vmov s15, r3
  9359. 8003cbc: eef8 6a67 vcvt.f32.u32 s13, s15
  9360. 8003cc0: 693b ldr r3, [r7, #16]
  9361. 8003cc2: ee07 3a90 vmov s15, r3
  9362. 8003cc6: eef8 7a67 vcvt.f32.u32 s15, s15
  9363. 8003cca: ee86 7aa7 vdiv.f32 s14, s13, s15
  9364. 8003cce: 4b62 ldr r3, [pc, #392] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9365. 8003cd0: 6b1b ldr r3, [r3, #48] ; 0x30
  9366. 8003cd2: f3c3 0308 ubfx r3, r3, #0, #9
  9367. 8003cd6: ee07 3a90 vmov s15, r3
  9368. 8003cda: eef8 6a67 vcvt.f32.u32 s13, s15
  9369. 8003cde: ed97 6a02 vldr s12, [r7, #8]
  9370. 8003ce2: eddf 5a61 vldr s11, [pc, #388] ; 8003e68 <HAL_RCC_GetSysClockFreq+0x2e4>
  9371. 8003ce6: eec6 7a25 vdiv.f32 s15, s12, s11
  9372. 8003cea: ee76 7aa7 vadd.f32 s15, s13, s15
  9373. 8003cee: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0
  9374. 8003cf2: ee77 7aa6 vadd.f32 s15, s15, s13
  9375. 8003cf6: ee67 7a27 vmul.f32 s15, s14, s15
  9376. 8003cfa: edc7 7a07 vstr s15, [r7, #28]
  9377. }
  9378. else
  9379. {
  9380. pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
  9381. }
  9382. break;
  9383. 8003cfe: e087 b.n 8003e10 <HAL_RCC_GetSysClockFreq+0x28c>
  9384. pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
  9385. 8003d00: 693b ldr r3, [r7, #16]
  9386. 8003d02: ee07 3a90 vmov s15, r3
  9387. 8003d06: eef8 7a67 vcvt.f32.u32 s15, s15
  9388. 8003d0a: eddf 6a58 vldr s13, [pc, #352] ; 8003e6c <HAL_RCC_GetSysClockFreq+0x2e8>
  9389. 8003d0e: ee86 7aa7 vdiv.f32 s14, s13, s15
  9390. 8003d12: 4b51 ldr r3, [pc, #324] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9391. 8003d14: 6b1b ldr r3, [r3, #48] ; 0x30
  9392. 8003d16: f3c3 0308 ubfx r3, r3, #0, #9
  9393. 8003d1a: ee07 3a90 vmov s15, r3
  9394. 8003d1e: eef8 6a67 vcvt.f32.u32 s13, s15
  9395. 8003d22: ed97 6a02 vldr s12, [r7, #8]
  9396. 8003d26: eddf 5a50 vldr s11, [pc, #320] ; 8003e68 <HAL_RCC_GetSysClockFreq+0x2e4>
  9397. 8003d2a: eec6 7a25 vdiv.f32 s15, s12, s11
  9398. 8003d2e: ee76 7aa7 vadd.f32 s15, s13, s15
  9399. 8003d32: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0
  9400. 8003d36: ee77 7aa6 vadd.f32 s15, s15, s13
  9401. 8003d3a: ee67 7a27 vmul.f32 s15, s14, s15
  9402. 8003d3e: edc7 7a07 vstr s15, [r7, #28]
  9403. break;
  9404. 8003d42: e065 b.n 8003e10 <HAL_RCC_GetSysClockFreq+0x28c>
  9405. case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
  9406. pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
  9407. 8003d44: 693b ldr r3, [r7, #16]
  9408. 8003d46: ee07 3a90 vmov s15, r3
  9409. 8003d4a: eef8 7a67 vcvt.f32.u32 s15, s15
  9410. 8003d4e: eddf 6a48 vldr s13, [pc, #288] ; 8003e70 <HAL_RCC_GetSysClockFreq+0x2ec>
  9411. 8003d52: ee86 7aa7 vdiv.f32 s14, s13, s15
  9412. 8003d56: 4b40 ldr r3, [pc, #256] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9413. 8003d58: 6b1b ldr r3, [r3, #48] ; 0x30
  9414. 8003d5a: f3c3 0308 ubfx r3, r3, #0, #9
  9415. 8003d5e: ee07 3a90 vmov s15, r3
  9416. 8003d62: eef8 6a67 vcvt.f32.u32 s13, s15
  9417. 8003d66: ed97 6a02 vldr s12, [r7, #8]
  9418. 8003d6a: eddf 5a3f vldr s11, [pc, #252] ; 8003e68 <HAL_RCC_GetSysClockFreq+0x2e4>
  9419. 8003d6e: eec6 7a25 vdiv.f32 s15, s12, s11
  9420. 8003d72: ee76 7aa7 vadd.f32 s15, s13, s15
  9421. 8003d76: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0
  9422. 8003d7a: ee77 7aa6 vadd.f32 s15, s15, s13
  9423. 8003d7e: ee67 7a27 vmul.f32 s15, s14, s15
  9424. 8003d82: edc7 7a07 vstr s15, [r7, #28]
  9425. break;
  9426. 8003d86: e043 b.n 8003e10 <HAL_RCC_GetSysClockFreq+0x28c>
  9427. case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
  9428. pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
  9429. 8003d88: 693b ldr r3, [r7, #16]
  9430. 8003d8a: ee07 3a90 vmov s15, r3
  9431. 8003d8e: eef8 7a67 vcvt.f32.u32 s15, s15
  9432. 8003d92: eddf 6a38 vldr s13, [pc, #224] ; 8003e74 <HAL_RCC_GetSysClockFreq+0x2f0>
  9433. 8003d96: ee86 7aa7 vdiv.f32 s14, s13, s15
  9434. 8003d9a: 4b2f ldr r3, [pc, #188] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9435. 8003d9c: 6b1b ldr r3, [r3, #48] ; 0x30
  9436. 8003d9e: f3c3 0308 ubfx r3, r3, #0, #9
  9437. 8003da2: ee07 3a90 vmov s15, r3
  9438. 8003da6: eef8 6a67 vcvt.f32.u32 s13, s15
  9439. 8003daa: ed97 6a02 vldr s12, [r7, #8]
  9440. 8003dae: eddf 5a2e vldr s11, [pc, #184] ; 8003e68 <HAL_RCC_GetSysClockFreq+0x2e4>
  9441. 8003db2: eec6 7a25 vdiv.f32 s15, s12, s11
  9442. 8003db6: ee76 7aa7 vadd.f32 s15, s13, s15
  9443. 8003dba: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0
  9444. 8003dbe: ee77 7aa6 vadd.f32 s15, s15, s13
  9445. 8003dc2: ee67 7a27 vmul.f32 s15, s14, s15
  9446. 8003dc6: edc7 7a07 vstr s15, [r7, #28]
  9447. break;
  9448. 8003dca: e021 b.n 8003e10 <HAL_RCC_GetSysClockFreq+0x28c>
  9449. default:
  9450. pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
  9451. 8003dcc: 693b ldr r3, [r7, #16]
  9452. 8003dce: ee07 3a90 vmov s15, r3
  9453. 8003dd2: eef8 7a67 vcvt.f32.u32 s15, s15
  9454. 8003dd6: eddf 6a26 vldr s13, [pc, #152] ; 8003e70 <HAL_RCC_GetSysClockFreq+0x2ec>
  9455. 8003dda: ee86 7aa7 vdiv.f32 s14, s13, s15
  9456. 8003dde: 4b1e ldr r3, [pc, #120] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9457. 8003de0: 6b1b ldr r3, [r3, #48] ; 0x30
  9458. 8003de2: f3c3 0308 ubfx r3, r3, #0, #9
  9459. 8003de6: ee07 3a90 vmov s15, r3
  9460. 8003dea: eef8 6a67 vcvt.f32.u32 s13, s15
  9461. 8003dee: ed97 6a02 vldr s12, [r7, #8]
  9462. 8003df2: eddf 5a1d vldr s11, [pc, #116] ; 8003e68 <HAL_RCC_GetSysClockFreq+0x2e4>
  9463. 8003df6: eec6 7a25 vdiv.f32 s15, s12, s11
  9464. 8003dfa: ee76 7aa7 vadd.f32 s15, s13, s15
  9465. 8003dfe: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0
  9466. 8003e02: ee77 7aa6 vadd.f32 s15, s15, s13
  9467. 8003e06: ee67 7a27 vmul.f32 s15, s14, s15
  9468. 8003e0a: edc7 7a07 vstr s15, [r7, #28]
  9469. break;
  9470. 8003e0e: bf00 nop
  9471. }
  9472. pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
  9473. 8003e10: 4b11 ldr r3, [pc, #68] ; (8003e58 <HAL_RCC_GetSysClockFreq+0x2d4>)
  9474. 8003e12: 6b1b ldr r3, [r3, #48] ; 0x30
  9475. 8003e14: 0a5b lsrs r3, r3, #9
  9476. 8003e16: f003 037f and.w r3, r3, #127 ; 0x7f
  9477. 8003e1a: 3301 adds r3, #1
  9478. 8003e1c: 603b str r3, [r7, #0]
  9479. sysclockfreq = (uint32_t)(float_t)(pllvco/(float_t)pllp);
  9480. 8003e1e: 683b ldr r3, [r7, #0]
  9481. 8003e20: ee07 3a90 vmov s15, r3
  9482. 8003e24: eeb8 7a67 vcvt.f32.u32 s14, s15
  9483. 8003e28: edd7 6a07 vldr s13, [r7, #28]
  9484. 8003e2c: eec6 7a87 vdiv.f32 s15, s13, s14
  9485. 8003e30: eefc 7ae7 vcvt.u32.f32 s15, s15
  9486. 8003e34: ee17 3a90 vmov r3, s15
  9487. 8003e38: 61bb str r3, [r7, #24]
  9488. }
  9489. else
  9490. {
  9491. sysclockfreq = 0U;
  9492. }
  9493. break;
  9494. 8003e3a: e005 b.n 8003e48 <HAL_RCC_GetSysClockFreq+0x2c4>
  9495. sysclockfreq = 0U;
  9496. 8003e3c: 2300 movs r3, #0
  9497. 8003e3e: 61bb str r3, [r7, #24]
  9498. break;
  9499. 8003e40: e002 b.n 8003e48 <HAL_RCC_GetSysClockFreq+0x2c4>
  9500. default:
  9501. sysclockfreq = CSI_VALUE;
  9502. 8003e42: 4b07 ldr r3, [pc, #28] ; (8003e60 <HAL_RCC_GetSysClockFreq+0x2dc>)
  9503. 8003e44: 61bb str r3, [r7, #24]
  9504. break;
  9505. 8003e46: bf00 nop
  9506. }
  9507. return sysclockfreq;
  9508. 8003e48: 69bb ldr r3, [r7, #24]
  9509. }
  9510. 8003e4a: 4618 mov r0, r3
  9511. 8003e4c: 3724 adds r7, #36 ; 0x24
  9512. 8003e4e: 46bd mov sp, r7
  9513. 8003e50: f85d 7b04 ldr.w r7, [sp], #4
  9514. 8003e54: 4770 bx lr
  9515. 8003e56: bf00 nop
  9516. 8003e58: 58024400 .word 0x58024400
  9517. 8003e5c: 03d09000 .word 0x03d09000
  9518. 8003e60: 003d0900 .word 0x003d0900
  9519. 8003e64: 007a1200 .word 0x007a1200
  9520. 8003e68: 46000000 .word 0x46000000
  9521. 8003e6c: 4c742400 .word 0x4c742400
  9522. 8003e70: 4a742400 .word 0x4a742400
  9523. 8003e74: 4af42400 .word 0x4af42400
  9524. 08003e78 <HAL_RCC_GetHCLKFreq>:
  9525. * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
  9526. * and updated within this function
  9527. * @retval HCLK frequency
  9528. */
  9529. uint32_t HAL_RCC_GetHCLKFreq(void)
  9530. {
  9531. 8003e78: b580 push {r7, lr}
  9532. 8003e7a: b082 sub sp, #8
  9533. 8003e7c: af00 add r7, sp, #0
  9534. uint32_t common_system_clock;
  9535. #if defined(RCC_D1CFGR_D1CPRE)
  9536. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  9537. 8003e7e: f7ff fe81 bl 8003b84 <HAL_RCC_GetSysClockFreq>
  9538. 8003e82: 4602 mov r2, r0
  9539. 8003e84: 4b10 ldr r3, [pc, #64] ; (8003ec8 <HAL_RCC_GetHCLKFreq+0x50>)
  9540. 8003e86: 699b ldr r3, [r3, #24]
  9541. 8003e88: 0a1b lsrs r3, r3, #8
  9542. 8003e8a: f003 030f and.w r3, r3, #15
  9543. 8003e8e: 490f ldr r1, [pc, #60] ; (8003ecc <HAL_RCC_GetHCLKFreq+0x54>)
  9544. 8003e90: 5ccb ldrb r3, [r1, r3]
  9545. 8003e92: f003 031f and.w r3, r3, #31
  9546. 8003e96: fa22 f303 lsr.w r3, r2, r3
  9547. 8003e9a: 607b str r3, [r7, #4]
  9548. #else
  9549. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
  9550. #endif
  9551. #if defined(RCC_D1CFGR_HPRE)
  9552. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  9553. 8003e9c: 4b0a ldr r3, [pc, #40] ; (8003ec8 <HAL_RCC_GetHCLKFreq+0x50>)
  9554. 8003e9e: 699b ldr r3, [r3, #24]
  9555. 8003ea0: f003 030f and.w r3, r3, #15
  9556. 8003ea4: 4a09 ldr r2, [pc, #36] ; (8003ecc <HAL_RCC_GetHCLKFreq+0x54>)
  9557. 8003ea6: 5cd3 ldrb r3, [r2, r3]
  9558. 8003ea8: f003 031f and.w r3, r3, #31
  9559. 8003eac: 687a ldr r2, [r7, #4]
  9560. 8003eae: fa22 f303 lsr.w r3, r2, r3
  9561. 8003eb2: 4a07 ldr r2, [pc, #28] ; (8003ed0 <HAL_RCC_GetHCLKFreq+0x58>)
  9562. 8003eb4: 6013 str r3, [r2, #0]
  9563. #endif
  9564. #if defined(DUAL_CORE) && defined(CORE_CM4)
  9565. SystemCoreClock = SystemD2Clock;
  9566. #else
  9567. SystemCoreClock = common_system_clock;
  9568. 8003eb6: 4a07 ldr r2, [pc, #28] ; (8003ed4 <HAL_RCC_GetHCLKFreq+0x5c>)
  9569. 8003eb8: 687b ldr r3, [r7, #4]
  9570. 8003eba: 6013 str r3, [r2, #0]
  9571. #endif /* DUAL_CORE && CORE_CM4 */
  9572. return SystemD2Clock;
  9573. 8003ebc: 4b04 ldr r3, [pc, #16] ; (8003ed0 <HAL_RCC_GetHCLKFreq+0x58>)
  9574. 8003ebe: 681b ldr r3, [r3, #0]
  9575. }
  9576. 8003ec0: 4618 mov r0, r3
  9577. 8003ec2: 3708 adds r7, #8
  9578. 8003ec4: 46bd mov sp, r7
  9579. 8003ec6: bd80 pop {r7, pc}
  9580. 8003ec8: 58024400 .word 0x58024400
  9581. 8003ecc: 0800aa10 .word 0x0800aa10
  9582. 8003ed0: 24000004 .word 0x24000004
  9583. 8003ed4: 24000000 .word 0x24000000
  9584. 08003ed8 <HAL_RCCEx_PeriphCLKConfig>:
  9585. * (*) : Available on some STM32H7 lines only.
  9586. *
  9587. * @retval HAL status
  9588. */
  9589. HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
  9590. {
  9591. 8003ed8: b580 push {r7, lr}
  9592. 8003eda: b086 sub sp, #24
  9593. 8003edc: af00 add r7, sp, #0
  9594. 8003ede: 6078 str r0, [r7, #4]
  9595. uint32_t tmpreg;
  9596. uint32_t tickstart;
  9597. HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
  9598. 8003ee0: 2300 movs r3, #0
  9599. 8003ee2: 75fb strb r3, [r7, #23]
  9600. HAL_StatusTypeDef status = HAL_OK; /* Final status */
  9601. 8003ee4: 2300 movs r3, #0
  9602. 8003ee6: 75bb strb r3, [r7, #22]
  9603. /*---------------------------- SPDIFRX configuration -------------------------------*/
  9604. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
  9605. 8003ee8: 687b ldr r3, [r7, #4]
  9606. 8003eea: 681b ldr r3, [r3, #0]
  9607. 8003eec: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
  9608. 8003ef0: 2b00 cmp r3, #0
  9609. 8003ef2: d03f beq.n 8003f74 <HAL_RCCEx_PeriphCLKConfig+0x9c>
  9610. {
  9611. switch(PeriphClkInit->SpdifrxClockSelection)
  9612. 8003ef4: 687b ldr r3, [r7, #4]
  9613. 8003ef6: 6e1b ldr r3, [r3, #96] ; 0x60
  9614. 8003ef8: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000
  9615. 8003efc: d02a beq.n 8003f54 <HAL_RCCEx_PeriphCLKConfig+0x7c>
  9616. 8003efe: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000
  9617. 8003f02: d824 bhi.n 8003f4e <HAL_RCCEx_PeriphCLKConfig+0x76>
  9618. 8003f04: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000
  9619. 8003f08: d018 beq.n 8003f3c <HAL_RCCEx_PeriphCLKConfig+0x64>
  9620. 8003f0a: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000
  9621. 8003f0e: d81e bhi.n 8003f4e <HAL_RCCEx_PeriphCLKConfig+0x76>
  9622. 8003f10: 2b00 cmp r3, #0
  9623. 8003f12: d003 beq.n 8003f1c <HAL_RCCEx_PeriphCLKConfig+0x44>
  9624. 8003f14: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
  9625. 8003f18: d007 beq.n 8003f2a <HAL_RCCEx_PeriphCLKConfig+0x52>
  9626. 8003f1a: e018 b.n 8003f4e <HAL_RCCEx_PeriphCLKConfig+0x76>
  9627. {
  9628. case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/
  9629. /* Enable PLL1Q Clock output generated form System PLL . */
  9630. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  9631. 8003f1c: 4bab ldr r3, [pc, #684] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9632. 8003f1e: 6adb ldr r3, [r3, #44] ; 0x2c
  9633. 8003f20: 4aaa ldr r2, [pc, #680] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9634. 8003f22: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  9635. 8003f26: 62d3 str r3, [r2, #44] ; 0x2c
  9636. /* SPDIFRX clock source configuration done later after clock selection check */
  9637. break;
  9638. 8003f28: e015 b.n 8003f56 <HAL_RCCEx_PeriphCLKConfig+0x7e>
  9639. case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
  9640. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
  9641. 8003f2a: 687b ldr r3, [r7, #4]
  9642. 8003f2c: 3304 adds r3, #4
  9643. 8003f2e: 2102 movs r1, #2
  9644. 8003f30: 4618 mov r0, r3
  9645. 8003f32: f000 fecb bl 8004ccc <RCCEx_PLL2_Config>
  9646. 8003f36: 4603 mov r3, r0
  9647. 8003f38: 75fb strb r3, [r7, #23]
  9648. /* SPDIFRX clock source configuration done later after clock selection check */
  9649. break;
  9650. 8003f3a: e00c b.n 8003f56 <HAL_RCCEx_PeriphCLKConfig+0x7e>
  9651. case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/
  9652. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
  9653. 8003f3c: 687b ldr r3, [r7, #4]
  9654. 8003f3e: 3324 adds r3, #36 ; 0x24
  9655. 8003f40: 2102 movs r1, #2
  9656. 8003f42: 4618 mov r0, r3
  9657. 8003f44: f000 ff74 bl 8004e30 <RCCEx_PLL3_Config>
  9658. 8003f48: 4603 mov r3, r0
  9659. 8003f4a: 75fb strb r3, [r7, #23]
  9660. /* SPDIFRX clock source configuration done later after clock selection check */
  9661. break;
  9662. 8003f4c: e003 b.n 8003f56 <HAL_RCCEx_PeriphCLKConfig+0x7e>
  9663. /* Internal OSC clock is used as source of SPDIFRX clock*/
  9664. /* SPDIFRX clock source configuration done later after clock selection check */
  9665. break;
  9666. default:
  9667. ret = HAL_ERROR;
  9668. 8003f4e: 2301 movs r3, #1
  9669. 8003f50: 75fb strb r3, [r7, #23]
  9670. break;
  9671. 8003f52: e000 b.n 8003f56 <HAL_RCCEx_PeriphCLKConfig+0x7e>
  9672. break;
  9673. 8003f54: bf00 nop
  9674. }
  9675. if(ret == HAL_OK)
  9676. 8003f56: 7dfb ldrb r3, [r7, #23]
  9677. 8003f58: 2b00 cmp r3, #0
  9678. 8003f5a: d109 bne.n 8003f70 <HAL_RCCEx_PeriphCLKConfig+0x98>
  9679. {
  9680. /* Set the source of SPDIFRX clock*/
  9681. __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
  9682. 8003f5c: 4b9b ldr r3, [pc, #620] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9683. 8003f5e: 6d1b ldr r3, [r3, #80] ; 0x50
  9684. 8003f60: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
  9685. 8003f64: 687b ldr r3, [r7, #4]
  9686. 8003f66: 6e1b ldr r3, [r3, #96] ; 0x60
  9687. 8003f68: 4998 ldr r1, [pc, #608] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9688. 8003f6a: 4313 orrs r3, r2
  9689. 8003f6c: 650b str r3, [r1, #80] ; 0x50
  9690. 8003f6e: e001 b.n 8003f74 <HAL_RCCEx_PeriphCLKConfig+0x9c>
  9691. }
  9692. else
  9693. {
  9694. /* set overall return value */
  9695. status = ret;
  9696. 8003f70: 7dfb ldrb r3, [r7, #23]
  9697. 8003f72: 75bb strb r3, [r7, #22]
  9698. }
  9699. }
  9700. /*---------------------------- SAI1 configuration -------------------------------*/
  9701. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
  9702. 8003f74: 687b ldr r3, [r7, #4]
  9703. 8003f76: 681b ldr r3, [r3, #0]
  9704. 8003f78: f403 7380 and.w r3, r3, #256 ; 0x100
  9705. 8003f7c: 2b00 cmp r3, #0
  9706. 8003f7e: d03d beq.n 8003ffc <HAL_RCCEx_PeriphCLKConfig+0x124>
  9707. {
  9708. switch(PeriphClkInit->Sai1ClockSelection)
  9709. 8003f80: 687b ldr r3, [r7, #4]
  9710. 8003f82: 6d5b ldr r3, [r3, #84] ; 0x54
  9711. 8003f84: 2b04 cmp r3, #4
  9712. 8003f86: d826 bhi.n 8003fd6 <HAL_RCCEx_PeriphCLKConfig+0xfe>
  9713. 8003f88: a201 add r2, pc, #4 ; (adr r2, 8003f90 <HAL_RCCEx_PeriphCLKConfig+0xb8>)
  9714. 8003f8a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  9715. 8003f8e: bf00 nop
  9716. 8003f90: 08003fa5 .word 0x08003fa5
  9717. 8003f94: 08003fb3 .word 0x08003fb3
  9718. 8003f98: 08003fc5 .word 0x08003fc5
  9719. 8003f9c: 08003fdd .word 0x08003fdd
  9720. 8003fa0: 08003fdd .word 0x08003fdd
  9721. {
  9722. case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
  9723. /* Enable SAI Clock output generated form System PLL . */
  9724. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  9725. 8003fa4: 4b89 ldr r3, [pc, #548] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9726. 8003fa6: 6adb ldr r3, [r3, #44] ; 0x2c
  9727. 8003fa8: 4a88 ldr r2, [pc, #544] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9728. 8003faa: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  9729. 8003fae: 62d3 str r3, [r2, #44] ; 0x2c
  9730. /* SAI1 clock source configuration done later after clock selection check */
  9731. break;
  9732. 8003fb0: e015 b.n 8003fde <HAL_RCCEx_PeriphCLKConfig+0x106>
  9733. case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
  9734. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
  9735. 8003fb2: 687b ldr r3, [r7, #4]
  9736. 8003fb4: 3304 adds r3, #4
  9737. 8003fb6: 2100 movs r1, #0
  9738. 8003fb8: 4618 mov r0, r3
  9739. 8003fba: f000 fe87 bl 8004ccc <RCCEx_PLL2_Config>
  9740. 8003fbe: 4603 mov r3, r0
  9741. 8003fc0: 75fb strb r3, [r7, #23]
  9742. /* SAI1 clock source configuration done later after clock selection check */
  9743. break;
  9744. 8003fc2: e00c b.n 8003fde <HAL_RCCEx_PeriphCLKConfig+0x106>
  9745. case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/
  9746. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
  9747. 8003fc4: 687b ldr r3, [r7, #4]
  9748. 8003fc6: 3324 adds r3, #36 ; 0x24
  9749. 8003fc8: 2100 movs r1, #0
  9750. 8003fca: 4618 mov r0, r3
  9751. 8003fcc: f000 ff30 bl 8004e30 <RCCEx_PLL3_Config>
  9752. 8003fd0: 4603 mov r3, r0
  9753. 8003fd2: 75fb strb r3, [r7, #23]
  9754. /* SAI1 clock source configuration done later after clock selection check */
  9755. break;
  9756. 8003fd4: e003 b.n 8003fde <HAL_RCCEx_PeriphCLKConfig+0x106>
  9757. /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
  9758. /* SAI1 clock source configuration done later after clock selection check */
  9759. break;
  9760. default:
  9761. ret = HAL_ERROR;
  9762. 8003fd6: 2301 movs r3, #1
  9763. 8003fd8: 75fb strb r3, [r7, #23]
  9764. break;
  9765. 8003fda: e000 b.n 8003fde <HAL_RCCEx_PeriphCLKConfig+0x106>
  9766. break;
  9767. 8003fdc: bf00 nop
  9768. }
  9769. if(ret == HAL_OK)
  9770. 8003fde: 7dfb ldrb r3, [r7, #23]
  9771. 8003fe0: 2b00 cmp r3, #0
  9772. 8003fe2: d109 bne.n 8003ff8 <HAL_RCCEx_PeriphCLKConfig+0x120>
  9773. {
  9774. /* Set the source of SAI1 clock*/
  9775. __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
  9776. 8003fe4: 4b79 ldr r3, [pc, #484] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9777. 8003fe6: 6d1b ldr r3, [r3, #80] ; 0x50
  9778. 8003fe8: f023 0207 bic.w r2, r3, #7
  9779. 8003fec: 687b ldr r3, [r7, #4]
  9780. 8003fee: 6d5b ldr r3, [r3, #84] ; 0x54
  9781. 8003ff0: 4976 ldr r1, [pc, #472] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9782. 8003ff2: 4313 orrs r3, r2
  9783. 8003ff4: 650b str r3, [r1, #80] ; 0x50
  9784. 8003ff6: e001 b.n 8003ffc <HAL_RCCEx_PeriphCLKConfig+0x124>
  9785. }
  9786. else
  9787. {
  9788. /* set overall return value */
  9789. status = ret;
  9790. 8003ff8: 7dfb ldrb r3, [r7, #23]
  9791. 8003ffa: 75bb strb r3, [r7, #22]
  9792. }
  9793. #endif /*SAI2B*/
  9794. #if defined(SAI4)
  9795. /*---------------------------- SAI4A configuration -------------------------------*/
  9796. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
  9797. 8003ffc: 687b ldr r3, [r7, #4]
  9798. 8003ffe: 681b ldr r3, [r3, #0]
  9799. 8004000: f403 6380 and.w r3, r3, #1024 ; 0x400
  9800. 8004004: 2b00 cmp r3, #0
  9801. 8004006: d051 beq.n 80040ac <HAL_RCCEx_PeriphCLKConfig+0x1d4>
  9802. {
  9803. switch(PeriphClkInit->Sai4AClockSelection)
  9804. 8004008: 687b ldr r3, [r7, #4]
  9805. 800400a: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0
  9806. 800400e: f5b3 0f20 cmp.w r3, #10485760 ; 0xa00000
  9807. 8004012: d036 beq.n 8004082 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
  9808. 8004014: f5b3 0f20 cmp.w r3, #10485760 ; 0xa00000
  9809. 8004018: d830 bhi.n 800407c <HAL_RCCEx_PeriphCLKConfig+0x1a4>
  9810. 800401a: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000
  9811. 800401e: d032 beq.n 8004086 <HAL_RCCEx_PeriphCLKConfig+0x1ae>
  9812. 8004020: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000
  9813. 8004024: d82a bhi.n 800407c <HAL_RCCEx_PeriphCLKConfig+0x1a4>
  9814. 8004026: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000
  9815. 800402a: d02e beq.n 800408a <HAL_RCCEx_PeriphCLKConfig+0x1b2>
  9816. 800402c: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000
  9817. 8004030: d824 bhi.n 800407c <HAL_RCCEx_PeriphCLKConfig+0x1a4>
  9818. 8004032: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
  9819. 8004036: d018 beq.n 800406a <HAL_RCCEx_PeriphCLKConfig+0x192>
  9820. 8004038: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
  9821. 800403c: d81e bhi.n 800407c <HAL_RCCEx_PeriphCLKConfig+0x1a4>
  9822. 800403e: 2b00 cmp r3, #0
  9823. 8004040: d003 beq.n 800404a <HAL_RCCEx_PeriphCLKConfig+0x172>
  9824. 8004042: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000
  9825. 8004046: d007 beq.n 8004058 <HAL_RCCEx_PeriphCLKConfig+0x180>
  9826. 8004048: e018 b.n 800407c <HAL_RCCEx_PeriphCLKConfig+0x1a4>
  9827. {
  9828. case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
  9829. /* Enable SAI Clock output generated form System PLL . */
  9830. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  9831. 800404a: 4b60 ldr r3, [pc, #384] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9832. 800404c: 6adb ldr r3, [r3, #44] ; 0x2c
  9833. 800404e: 4a5f ldr r2, [pc, #380] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9834. 8004050: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  9835. 8004054: 62d3 str r3, [r2, #44] ; 0x2c
  9836. /* SAI1 clock source configuration done later after clock selection check */
  9837. break;
  9838. 8004056: e019 b.n 800408c <HAL_RCCEx_PeriphCLKConfig+0x1b4>
  9839. case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
  9840. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
  9841. 8004058: 687b ldr r3, [r7, #4]
  9842. 800405a: 3304 adds r3, #4
  9843. 800405c: 2100 movs r1, #0
  9844. 800405e: 4618 mov r0, r3
  9845. 8004060: f000 fe34 bl 8004ccc <RCCEx_PLL2_Config>
  9846. 8004064: 4603 mov r3, r0
  9847. 8004066: 75fb strb r3, [r7, #23]
  9848. /* SAI2 clock source configuration done later after clock selection check */
  9849. break;
  9850. 8004068: e010 b.n 800408c <HAL_RCCEx_PeriphCLKConfig+0x1b4>
  9851. case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
  9852. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
  9853. 800406a: 687b ldr r3, [r7, #4]
  9854. 800406c: 3324 adds r3, #36 ; 0x24
  9855. 800406e: 2100 movs r1, #0
  9856. 8004070: 4618 mov r0, r3
  9857. 8004072: f000 fedd bl 8004e30 <RCCEx_PLL3_Config>
  9858. 8004076: 4603 mov r3, r0
  9859. 8004078: 75fb strb r3, [r7, #23]
  9860. /* SAI1 clock source configuration done later after clock selection check */
  9861. break;
  9862. 800407a: e007 b.n 800408c <HAL_RCCEx_PeriphCLKConfig+0x1b4>
  9863. /* SAI4A clock source configuration done later after clock selection check */
  9864. break;
  9865. #endif /* RCC_VER_3_0 */
  9866. default:
  9867. ret = HAL_ERROR;
  9868. 800407c: 2301 movs r3, #1
  9869. 800407e: 75fb strb r3, [r7, #23]
  9870. break;
  9871. 8004080: e004 b.n 800408c <HAL_RCCEx_PeriphCLKConfig+0x1b4>
  9872. break;
  9873. 8004082: bf00 nop
  9874. 8004084: e002 b.n 800408c <HAL_RCCEx_PeriphCLKConfig+0x1b4>
  9875. break;
  9876. 8004086: bf00 nop
  9877. 8004088: e000 b.n 800408c <HAL_RCCEx_PeriphCLKConfig+0x1b4>
  9878. break;
  9879. 800408a: bf00 nop
  9880. }
  9881. if(ret == HAL_OK)
  9882. 800408c: 7dfb ldrb r3, [r7, #23]
  9883. 800408e: 2b00 cmp r3, #0
  9884. 8004090: d10a bne.n 80040a8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>
  9885. {
  9886. /* Set the source of SAI4A clock*/
  9887. __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
  9888. 8004092: 4b4e ldr r3, [pc, #312] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9889. 8004094: 6d9b ldr r3, [r3, #88] ; 0x58
  9890. 8004096: f423 0260 bic.w r2, r3, #14680064 ; 0xe00000
  9891. 800409a: 687b ldr r3, [r7, #4]
  9892. 800409c: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0
  9893. 80040a0: 494a ldr r1, [pc, #296] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9894. 80040a2: 4313 orrs r3, r2
  9895. 80040a4: 658b str r3, [r1, #88] ; 0x58
  9896. 80040a6: e001 b.n 80040ac <HAL_RCCEx_PeriphCLKConfig+0x1d4>
  9897. }
  9898. else
  9899. {
  9900. /* set overall return value */
  9901. status = ret;
  9902. 80040a8: 7dfb ldrb r3, [r7, #23]
  9903. 80040aa: 75bb strb r3, [r7, #22]
  9904. }
  9905. }
  9906. /*---------------------------- SAI4B configuration -------------------------------*/
  9907. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
  9908. 80040ac: 687b ldr r3, [r7, #4]
  9909. 80040ae: 681b ldr r3, [r3, #0]
  9910. 80040b0: f403 6300 and.w r3, r3, #2048 ; 0x800
  9911. 80040b4: 2b00 cmp r3, #0
  9912. 80040b6: d051 beq.n 800415c <HAL_RCCEx_PeriphCLKConfig+0x284>
  9913. {
  9914. switch(PeriphClkInit->Sai4BClockSelection)
  9915. 80040b8: 687b ldr r3, [r7, #4]
  9916. 80040ba: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
  9917. 80040be: f1b3 6fa0 cmp.w r3, #83886080 ; 0x5000000
  9918. 80040c2: d036 beq.n 8004132 <HAL_RCCEx_PeriphCLKConfig+0x25a>
  9919. 80040c4: f1b3 6fa0 cmp.w r3, #83886080 ; 0x5000000
  9920. 80040c8: d830 bhi.n 800412c <HAL_RCCEx_PeriphCLKConfig+0x254>
  9921. 80040ca: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
  9922. 80040ce: d032 beq.n 8004136 <HAL_RCCEx_PeriphCLKConfig+0x25e>
  9923. 80040d0: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
  9924. 80040d4: d82a bhi.n 800412c <HAL_RCCEx_PeriphCLKConfig+0x254>
  9925. 80040d6: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000
  9926. 80040da: d02e beq.n 800413a <HAL_RCCEx_PeriphCLKConfig+0x262>
  9927. 80040dc: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000
  9928. 80040e0: d824 bhi.n 800412c <HAL_RCCEx_PeriphCLKConfig+0x254>
  9929. 80040e2: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
  9930. 80040e6: d018 beq.n 800411a <HAL_RCCEx_PeriphCLKConfig+0x242>
  9931. 80040e8: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
  9932. 80040ec: d81e bhi.n 800412c <HAL_RCCEx_PeriphCLKConfig+0x254>
  9933. 80040ee: 2b00 cmp r3, #0
  9934. 80040f0: d003 beq.n 80040fa <HAL_RCCEx_PeriphCLKConfig+0x222>
  9935. 80040f2: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
  9936. 80040f6: d007 beq.n 8004108 <HAL_RCCEx_PeriphCLKConfig+0x230>
  9937. 80040f8: e018 b.n 800412c <HAL_RCCEx_PeriphCLKConfig+0x254>
  9938. {
  9939. case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
  9940. /* Enable SAI Clock output generated form System PLL . */
  9941. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  9942. 80040fa: 4b34 ldr r3, [pc, #208] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9943. 80040fc: 6adb ldr r3, [r3, #44] ; 0x2c
  9944. 80040fe: 4a33 ldr r2, [pc, #204] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  9945. 8004100: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  9946. 8004104: 62d3 str r3, [r2, #44] ; 0x2c
  9947. /* SAI1 clock source configuration done later after clock selection check */
  9948. break;
  9949. 8004106: e019 b.n 800413c <HAL_RCCEx_PeriphCLKConfig+0x264>
  9950. case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
  9951. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
  9952. 8004108: 687b ldr r3, [r7, #4]
  9953. 800410a: 3304 adds r3, #4
  9954. 800410c: 2100 movs r1, #0
  9955. 800410e: 4618 mov r0, r3
  9956. 8004110: f000 fddc bl 8004ccc <RCCEx_PLL2_Config>
  9957. 8004114: 4603 mov r3, r0
  9958. 8004116: 75fb strb r3, [r7, #23]
  9959. /* SAI2 clock source configuration done later after clock selection check */
  9960. break;
  9961. 8004118: e010 b.n 800413c <HAL_RCCEx_PeriphCLKConfig+0x264>
  9962. case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
  9963. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
  9964. 800411a: 687b ldr r3, [r7, #4]
  9965. 800411c: 3324 adds r3, #36 ; 0x24
  9966. 800411e: 2100 movs r1, #0
  9967. 8004120: 4618 mov r0, r3
  9968. 8004122: f000 fe85 bl 8004e30 <RCCEx_PLL3_Config>
  9969. 8004126: 4603 mov r3, r0
  9970. 8004128: 75fb strb r3, [r7, #23]
  9971. /* SAI1 clock source configuration done later after clock selection check */
  9972. break;
  9973. 800412a: e007 b.n 800413c <HAL_RCCEx_PeriphCLKConfig+0x264>
  9974. /* SAI4B clock source configuration done later after clock selection check */
  9975. break;
  9976. #endif /* RCC_VER_3_0 */
  9977. default:
  9978. ret = HAL_ERROR;
  9979. 800412c: 2301 movs r3, #1
  9980. 800412e: 75fb strb r3, [r7, #23]
  9981. break;
  9982. 8004130: e004 b.n 800413c <HAL_RCCEx_PeriphCLKConfig+0x264>
  9983. break;
  9984. 8004132: bf00 nop
  9985. 8004134: e002 b.n 800413c <HAL_RCCEx_PeriphCLKConfig+0x264>
  9986. break;
  9987. 8004136: bf00 nop
  9988. 8004138: e000 b.n 800413c <HAL_RCCEx_PeriphCLKConfig+0x264>
  9989. break;
  9990. 800413a: bf00 nop
  9991. }
  9992. if(ret == HAL_OK)
  9993. 800413c: 7dfb ldrb r3, [r7, #23]
  9994. 800413e: 2b00 cmp r3, #0
  9995. 8004140: d10a bne.n 8004158 <HAL_RCCEx_PeriphCLKConfig+0x280>
  9996. {
  9997. /* Set the source of SAI4B clock*/
  9998. __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
  9999. 8004142: 4b22 ldr r3, [pc, #136] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  10000. 8004144: 6d9b ldr r3, [r3, #88] ; 0x58
  10001. 8004146: f023 62e0 bic.w r2, r3, #117440512 ; 0x7000000
  10002. 800414a: 687b ldr r3, [r7, #4]
  10003. 800414c: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
  10004. 8004150: 491e ldr r1, [pc, #120] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  10005. 8004152: 4313 orrs r3, r2
  10006. 8004154: 658b str r3, [r1, #88] ; 0x58
  10007. 8004156: e001 b.n 800415c <HAL_RCCEx_PeriphCLKConfig+0x284>
  10008. }
  10009. else
  10010. {
  10011. /* set overall return value */
  10012. status = ret;
  10013. 8004158: 7dfb ldrb r3, [r7, #23]
  10014. 800415a: 75bb strb r3, [r7, #22]
  10015. }
  10016. #endif /*QUADSPI*/
  10017. #if defined(OCTOSPI1) || defined(OCTOSPI2)
  10018. /*---------------------------- OCTOSPI configuration -------------------------------*/
  10019. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
  10020. 800415c: 687b ldr r3, [r7, #4]
  10021. 800415e: 681b ldr r3, [r3, #0]
  10022. 8004160: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
  10023. 8004164: 2b00 cmp r3, #0
  10024. 8004166: d035 beq.n 80041d4 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
  10025. {
  10026. switch(PeriphClkInit->OspiClockSelection)
  10027. 8004168: 687b ldr r3, [r7, #4]
  10028. 800416a: 6c9b ldr r3, [r3, #72] ; 0x48
  10029. 800416c: 2b30 cmp r3, #48 ; 0x30
  10030. 800416e: d01c beq.n 80041aa <HAL_RCCEx_PeriphCLKConfig+0x2d2>
  10031. 8004170: 2b30 cmp r3, #48 ; 0x30
  10032. 8004172: d817 bhi.n 80041a4 <HAL_RCCEx_PeriphCLKConfig+0x2cc>
  10033. 8004174: 2b20 cmp r3, #32
  10034. 8004176: d00c beq.n 8004192 <HAL_RCCEx_PeriphCLKConfig+0x2ba>
  10035. 8004178: 2b20 cmp r3, #32
  10036. 800417a: d813 bhi.n 80041a4 <HAL_RCCEx_PeriphCLKConfig+0x2cc>
  10037. 800417c: 2b00 cmp r3, #0
  10038. 800417e: d016 beq.n 80041ae <HAL_RCCEx_PeriphCLKConfig+0x2d6>
  10039. 8004180: 2b10 cmp r3, #16
  10040. 8004182: d10f bne.n 80041a4 <HAL_RCCEx_PeriphCLKConfig+0x2cc>
  10041. {
  10042. case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/
  10043. /* Enable OSPI Clock output generated form System PLL . */
  10044. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  10045. 8004184: 4b11 ldr r3, [pc, #68] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  10046. 8004186: 6adb ldr r3, [r3, #44] ; 0x2c
  10047. 8004188: 4a10 ldr r2, [pc, #64] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  10048. 800418a: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  10049. 800418e: 62d3 str r3, [r2, #44] ; 0x2c
  10050. /* OSPI clock source configuration done later after clock selection check */
  10051. break;
  10052. 8004190: e00e b.n 80041b0 <HAL_RCCEx_PeriphCLKConfig+0x2d8>
  10053. case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
  10054. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
  10055. 8004192: 687b ldr r3, [r7, #4]
  10056. 8004194: 3304 adds r3, #4
  10057. 8004196: 2102 movs r1, #2
  10058. 8004198: 4618 mov r0, r3
  10059. 800419a: f000 fd97 bl 8004ccc <RCCEx_PLL2_Config>
  10060. 800419e: 4603 mov r3, r0
  10061. 80041a0: 75fb strb r3, [r7, #23]
  10062. /* OSPI clock source configuration done later after clock selection check */
  10063. break;
  10064. 80041a2: e005 b.n 80041b0 <HAL_RCCEx_PeriphCLKConfig+0x2d8>
  10065. case RCC_OSPICLKSOURCE_HCLK:
  10066. /* HCLK clock selected as OSPI kernel peripheral clock */
  10067. break;
  10068. default:
  10069. ret = HAL_ERROR;
  10070. 80041a4: 2301 movs r3, #1
  10071. 80041a6: 75fb strb r3, [r7, #23]
  10072. break;
  10073. 80041a8: e002 b.n 80041b0 <HAL_RCCEx_PeriphCLKConfig+0x2d8>
  10074. break;
  10075. 80041aa: bf00 nop
  10076. 80041ac: e000 b.n 80041b0 <HAL_RCCEx_PeriphCLKConfig+0x2d8>
  10077. break;
  10078. 80041ae: bf00 nop
  10079. }
  10080. if(ret == HAL_OK)
  10081. 80041b0: 7dfb ldrb r3, [r7, #23]
  10082. 80041b2: 2b00 cmp r3, #0
  10083. 80041b4: d10c bne.n 80041d0 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
  10084. {
  10085. /* Set the source of OSPI clock*/
  10086. __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
  10087. 80041b6: 4b05 ldr r3, [pc, #20] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  10088. 80041b8: 6cdb ldr r3, [r3, #76] ; 0x4c
  10089. 80041ba: f023 0230 bic.w r2, r3, #48 ; 0x30
  10090. 80041be: 687b ldr r3, [r7, #4]
  10091. 80041c0: 6c9b ldr r3, [r3, #72] ; 0x48
  10092. 80041c2: 4902 ldr r1, [pc, #8] ; (80041cc <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
  10093. 80041c4: 4313 orrs r3, r2
  10094. 80041c6: 64cb str r3, [r1, #76] ; 0x4c
  10095. 80041c8: e004 b.n 80041d4 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
  10096. 80041ca: bf00 nop
  10097. 80041cc: 58024400 .word 0x58024400
  10098. }
  10099. else
  10100. {
  10101. /* set overall return value */
  10102. status = ret;
  10103. 80041d0: 7dfb ldrb r3, [r7, #23]
  10104. 80041d2: 75bb strb r3, [r7, #22]
  10105. }
  10106. }
  10107. #endif /*OCTOSPI*/
  10108. /*---------------------------- SPI1/2/3 configuration -------------------------------*/
  10109. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
  10110. 80041d4: 687b ldr r3, [r7, #4]
  10111. 80041d6: 681b ldr r3, [r3, #0]
  10112. 80041d8: f403 5380 and.w r3, r3, #4096 ; 0x1000
  10113. 80041dc: 2b00 cmp r3, #0
  10114. 80041de: d047 beq.n 8004270 <HAL_RCCEx_PeriphCLKConfig+0x398>
  10115. {
  10116. switch(PeriphClkInit->Spi123ClockSelection)
  10117. 80041e0: 687b ldr r3, [r7, #4]
  10118. 80041e2: 6d9b ldr r3, [r3, #88] ; 0x58
  10119. 80041e4: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
  10120. 80041e8: d030 beq.n 800424c <HAL_RCCEx_PeriphCLKConfig+0x374>
  10121. 80041ea: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
  10122. 80041ee: d82a bhi.n 8004246 <HAL_RCCEx_PeriphCLKConfig+0x36e>
  10123. 80041f0: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
  10124. 80041f4: d02c beq.n 8004250 <HAL_RCCEx_PeriphCLKConfig+0x378>
  10125. 80041f6: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
  10126. 80041fa: d824 bhi.n 8004246 <HAL_RCCEx_PeriphCLKConfig+0x36e>
  10127. 80041fc: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
  10128. 8004200: d018 beq.n 8004234 <HAL_RCCEx_PeriphCLKConfig+0x35c>
  10129. 8004202: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
  10130. 8004206: d81e bhi.n 8004246 <HAL_RCCEx_PeriphCLKConfig+0x36e>
  10131. 8004208: 2b00 cmp r3, #0
  10132. 800420a: d003 beq.n 8004214 <HAL_RCCEx_PeriphCLKConfig+0x33c>
  10133. 800420c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  10134. 8004210: d007 beq.n 8004222 <HAL_RCCEx_PeriphCLKConfig+0x34a>
  10135. 8004212: e018 b.n 8004246 <HAL_RCCEx_PeriphCLKConfig+0x36e>
  10136. {
  10137. case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */
  10138. /* Enable SPI Clock output generated form System PLL . */
  10139. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  10140. 8004214: 4bac ldr r3, [pc, #688] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10141. 8004216: 6adb ldr r3, [r3, #44] ; 0x2c
  10142. 8004218: 4aab ldr r2, [pc, #684] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10143. 800421a: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  10144. 800421e: 62d3 str r3, [r2, #44] ; 0x2c
  10145. /* SPI1/2/3 clock source configuration done later after clock selection check */
  10146. break;
  10147. 8004220: e017 b.n 8004252 <HAL_RCCEx_PeriphCLKConfig+0x37a>
  10148. case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
  10149. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
  10150. 8004222: 687b ldr r3, [r7, #4]
  10151. 8004224: 3304 adds r3, #4
  10152. 8004226: 2100 movs r1, #0
  10153. 8004228: 4618 mov r0, r3
  10154. 800422a: f000 fd4f bl 8004ccc <RCCEx_PLL2_Config>
  10155. 800422e: 4603 mov r3, r0
  10156. 8004230: 75fb strb r3, [r7, #23]
  10157. /* SPI1/2/3 clock source configuration done later after clock selection check */
  10158. break;
  10159. 8004232: e00e b.n 8004252 <HAL_RCCEx_PeriphCLKConfig+0x37a>
  10160. case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */
  10161. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
  10162. 8004234: 687b ldr r3, [r7, #4]
  10163. 8004236: 3324 adds r3, #36 ; 0x24
  10164. 8004238: 2100 movs r1, #0
  10165. 800423a: 4618 mov r0, r3
  10166. 800423c: f000 fdf8 bl 8004e30 <RCCEx_PLL3_Config>
  10167. 8004240: 4603 mov r3, r0
  10168. 8004242: 75fb strb r3, [r7, #23]
  10169. /* SPI1/2/3 clock source configuration done later after clock selection check */
  10170. break;
  10171. 8004244: e005 b.n 8004252 <HAL_RCCEx_PeriphCLKConfig+0x37a>
  10172. /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
  10173. /* SPI1/2/3 clock source configuration done later after clock selection check */
  10174. break;
  10175. default:
  10176. ret = HAL_ERROR;
  10177. 8004246: 2301 movs r3, #1
  10178. 8004248: 75fb strb r3, [r7, #23]
  10179. break;
  10180. 800424a: e002 b.n 8004252 <HAL_RCCEx_PeriphCLKConfig+0x37a>
  10181. break;
  10182. 800424c: bf00 nop
  10183. 800424e: e000 b.n 8004252 <HAL_RCCEx_PeriphCLKConfig+0x37a>
  10184. break;
  10185. 8004250: bf00 nop
  10186. }
  10187. if(ret == HAL_OK)
  10188. 8004252: 7dfb ldrb r3, [r7, #23]
  10189. 8004254: 2b00 cmp r3, #0
  10190. 8004256: d109 bne.n 800426c <HAL_RCCEx_PeriphCLKConfig+0x394>
  10191. {
  10192. /* Set the source of SPI1/2/3 clock*/
  10193. __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
  10194. 8004258: 4b9b ldr r3, [pc, #620] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10195. 800425a: 6d1b ldr r3, [r3, #80] ; 0x50
  10196. 800425c: f423 42e0 bic.w r2, r3, #28672 ; 0x7000
  10197. 8004260: 687b ldr r3, [r7, #4]
  10198. 8004262: 6d9b ldr r3, [r3, #88] ; 0x58
  10199. 8004264: 4998 ldr r1, [pc, #608] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10200. 8004266: 4313 orrs r3, r2
  10201. 8004268: 650b str r3, [r1, #80] ; 0x50
  10202. 800426a: e001 b.n 8004270 <HAL_RCCEx_PeriphCLKConfig+0x398>
  10203. }
  10204. else
  10205. {
  10206. /* set overall return value */
  10207. status = ret;
  10208. 800426c: 7dfb ldrb r3, [r7, #23]
  10209. 800426e: 75bb strb r3, [r7, #22]
  10210. }
  10211. }
  10212. /*---------------------------- SPI4/5 configuration -------------------------------*/
  10213. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
  10214. 8004270: 687b ldr r3, [r7, #4]
  10215. 8004272: 681b ldr r3, [r3, #0]
  10216. 8004274: f403 5300 and.w r3, r3, #8192 ; 0x2000
  10217. 8004278: 2b00 cmp r3, #0
  10218. 800427a: d049 beq.n 8004310 <HAL_RCCEx_PeriphCLKConfig+0x438>
  10219. {
  10220. switch(PeriphClkInit->Spi45ClockSelection)
  10221. 800427c: 687b ldr r3, [r7, #4]
  10222. 800427e: 6ddb ldr r3, [r3, #92] ; 0x5c
  10223. 8004280: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
  10224. 8004284: d02e beq.n 80042e4 <HAL_RCCEx_PeriphCLKConfig+0x40c>
  10225. 8004286: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
  10226. 800428a: d828 bhi.n 80042de <HAL_RCCEx_PeriphCLKConfig+0x406>
  10227. 800428c: f5b3 2f80 cmp.w r3, #262144 ; 0x40000
  10228. 8004290: d02a beq.n 80042e8 <HAL_RCCEx_PeriphCLKConfig+0x410>
  10229. 8004292: f5b3 2f80 cmp.w r3, #262144 ; 0x40000
  10230. 8004296: d822 bhi.n 80042de <HAL_RCCEx_PeriphCLKConfig+0x406>
  10231. 8004298: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
  10232. 800429c: d026 beq.n 80042ec <HAL_RCCEx_PeriphCLKConfig+0x414>
  10233. 800429e: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
  10234. 80042a2: d81c bhi.n 80042de <HAL_RCCEx_PeriphCLKConfig+0x406>
  10235. 80042a4: f5b3 3f00 cmp.w r3, #131072 ; 0x20000
  10236. 80042a8: d010 beq.n 80042cc <HAL_RCCEx_PeriphCLKConfig+0x3f4>
  10237. 80042aa: f5b3 3f00 cmp.w r3, #131072 ; 0x20000
  10238. 80042ae: d816 bhi.n 80042de <HAL_RCCEx_PeriphCLKConfig+0x406>
  10239. 80042b0: 2b00 cmp r3, #0
  10240. 80042b2: d01d beq.n 80042f0 <HAL_RCCEx_PeriphCLKConfig+0x418>
  10241. 80042b4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
  10242. 80042b8: d111 bne.n 80042de <HAL_RCCEx_PeriphCLKConfig+0x406>
  10243. /* SPI4/5 clock source configuration done later after clock selection check */
  10244. break;
  10245. case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
  10246. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
  10247. 80042ba: 687b ldr r3, [r7, #4]
  10248. 80042bc: 3304 adds r3, #4
  10249. 80042be: 2101 movs r1, #1
  10250. 80042c0: 4618 mov r0, r3
  10251. 80042c2: f000 fd03 bl 8004ccc <RCCEx_PLL2_Config>
  10252. 80042c6: 4603 mov r3, r0
  10253. 80042c8: 75fb strb r3, [r7, #23]
  10254. /* SPI4/5 clock source configuration done later after clock selection check */
  10255. break;
  10256. 80042ca: e012 b.n 80042f2 <HAL_RCCEx_PeriphCLKConfig+0x41a>
  10257. case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */
  10258. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
  10259. 80042cc: 687b ldr r3, [r7, #4]
  10260. 80042ce: 3324 adds r3, #36 ; 0x24
  10261. 80042d0: 2101 movs r1, #1
  10262. 80042d2: 4618 mov r0, r3
  10263. 80042d4: f000 fdac bl 8004e30 <RCCEx_PLL3_Config>
  10264. 80042d8: 4603 mov r3, r0
  10265. 80042da: 75fb strb r3, [r7, #23]
  10266. /* SPI4/5 clock source configuration done later after clock selection check */
  10267. break;
  10268. 80042dc: e009 b.n 80042f2 <HAL_RCCEx_PeriphCLKConfig+0x41a>
  10269. /* HSE, oscillator is used as source of SPI4/5 clock */
  10270. /* SPI4/5 clock source configuration done later after clock selection check */
  10271. break;
  10272. default:
  10273. ret = HAL_ERROR;
  10274. 80042de: 2301 movs r3, #1
  10275. 80042e0: 75fb strb r3, [r7, #23]
  10276. break;
  10277. 80042e2: e006 b.n 80042f2 <HAL_RCCEx_PeriphCLKConfig+0x41a>
  10278. break;
  10279. 80042e4: bf00 nop
  10280. 80042e6: e004 b.n 80042f2 <HAL_RCCEx_PeriphCLKConfig+0x41a>
  10281. break;
  10282. 80042e8: bf00 nop
  10283. 80042ea: e002 b.n 80042f2 <HAL_RCCEx_PeriphCLKConfig+0x41a>
  10284. break;
  10285. 80042ec: bf00 nop
  10286. 80042ee: e000 b.n 80042f2 <HAL_RCCEx_PeriphCLKConfig+0x41a>
  10287. break;
  10288. 80042f0: bf00 nop
  10289. }
  10290. if(ret == HAL_OK)
  10291. 80042f2: 7dfb ldrb r3, [r7, #23]
  10292. 80042f4: 2b00 cmp r3, #0
  10293. 80042f6: d109 bne.n 800430c <HAL_RCCEx_PeriphCLKConfig+0x434>
  10294. {
  10295. /* Set the source of SPI4/5 clock*/
  10296. __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
  10297. 80042f8: 4b73 ldr r3, [pc, #460] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10298. 80042fa: 6d1b ldr r3, [r3, #80] ; 0x50
  10299. 80042fc: f423 22e0 bic.w r2, r3, #458752 ; 0x70000
  10300. 8004300: 687b ldr r3, [r7, #4]
  10301. 8004302: 6ddb ldr r3, [r3, #92] ; 0x5c
  10302. 8004304: 4970 ldr r1, [pc, #448] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10303. 8004306: 4313 orrs r3, r2
  10304. 8004308: 650b str r3, [r1, #80] ; 0x50
  10305. 800430a: e001 b.n 8004310 <HAL_RCCEx_PeriphCLKConfig+0x438>
  10306. }
  10307. else
  10308. {
  10309. /* set overall return value */
  10310. status = ret;
  10311. 800430c: 7dfb ldrb r3, [r7, #23]
  10312. 800430e: 75bb strb r3, [r7, #22]
  10313. }
  10314. }
  10315. /*---------------------------- SPI6 configuration -------------------------------*/
  10316. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
  10317. 8004310: 687b ldr r3, [r7, #4]
  10318. 8004312: 681b ldr r3, [r3, #0]
  10319. 8004314: f403 4380 and.w r3, r3, #16384 ; 0x4000
  10320. 8004318: 2b00 cmp r3, #0
  10321. 800431a: d04b beq.n 80043b4 <HAL_RCCEx_PeriphCLKConfig+0x4dc>
  10322. {
  10323. switch(PeriphClkInit->Spi6ClockSelection)
  10324. 800431c: 687b ldr r3, [r7, #4]
  10325. 800431e: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8
  10326. 8004322: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000
  10327. 8004326: d02e beq.n 8004386 <HAL_RCCEx_PeriphCLKConfig+0x4ae>
  10328. 8004328: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000
  10329. 800432c: d828 bhi.n 8004380 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
  10330. 800432e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
  10331. 8004332: d02a beq.n 800438a <HAL_RCCEx_PeriphCLKConfig+0x4b2>
  10332. 8004334: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
  10333. 8004338: d822 bhi.n 8004380 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
  10334. 800433a: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000
  10335. 800433e: d026 beq.n 800438e <HAL_RCCEx_PeriphCLKConfig+0x4b6>
  10336. 8004340: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000
  10337. 8004344: d81c bhi.n 8004380 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
  10338. 8004346: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
  10339. 800434a: d010 beq.n 800436e <HAL_RCCEx_PeriphCLKConfig+0x496>
  10340. 800434c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
  10341. 8004350: d816 bhi.n 8004380 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
  10342. 8004352: 2b00 cmp r3, #0
  10343. 8004354: d01d beq.n 8004392 <HAL_RCCEx_PeriphCLKConfig+0x4ba>
  10344. 8004356: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
  10345. 800435a: d111 bne.n 8004380 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
  10346. /* SPI6 clock source configuration done later after clock selection check */
  10347. break;
  10348. case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
  10349. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
  10350. 800435c: 687b ldr r3, [r7, #4]
  10351. 800435e: 3304 adds r3, #4
  10352. 8004360: 2101 movs r1, #1
  10353. 8004362: 4618 mov r0, r3
  10354. 8004364: f000 fcb2 bl 8004ccc <RCCEx_PLL2_Config>
  10355. 8004368: 4603 mov r3, r0
  10356. 800436a: 75fb strb r3, [r7, #23]
  10357. /* SPI6 clock source configuration done later after clock selection check */
  10358. break;
  10359. 800436c: e012 b.n 8004394 <HAL_RCCEx_PeriphCLKConfig+0x4bc>
  10360. case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/
  10361. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
  10362. 800436e: 687b ldr r3, [r7, #4]
  10363. 8004370: 3324 adds r3, #36 ; 0x24
  10364. 8004372: 2101 movs r1, #1
  10365. 8004374: 4618 mov r0, r3
  10366. 8004376: f000 fd5b bl 8004e30 <RCCEx_PLL3_Config>
  10367. 800437a: 4603 mov r3, r0
  10368. 800437c: 75fb strb r3, [r7, #23]
  10369. /* SPI6 clock source configuration done later after clock selection check */
  10370. break;
  10371. 800437e: e009 b.n 8004394 <HAL_RCCEx_PeriphCLKConfig+0x4bc>
  10372. /* SPI6 clock source configuration done later after clock selection check */
  10373. break;
  10374. #endif
  10375. default:
  10376. ret = HAL_ERROR;
  10377. 8004380: 2301 movs r3, #1
  10378. 8004382: 75fb strb r3, [r7, #23]
  10379. break;
  10380. 8004384: e006 b.n 8004394 <HAL_RCCEx_PeriphCLKConfig+0x4bc>
  10381. break;
  10382. 8004386: bf00 nop
  10383. 8004388: e004 b.n 8004394 <HAL_RCCEx_PeriphCLKConfig+0x4bc>
  10384. break;
  10385. 800438a: bf00 nop
  10386. 800438c: e002 b.n 8004394 <HAL_RCCEx_PeriphCLKConfig+0x4bc>
  10387. break;
  10388. 800438e: bf00 nop
  10389. 8004390: e000 b.n 8004394 <HAL_RCCEx_PeriphCLKConfig+0x4bc>
  10390. break;
  10391. 8004392: bf00 nop
  10392. }
  10393. if(ret == HAL_OK)
  10394. 8004394: 7dfb ldrb r3, [r7, #23]
  10395. 8004396: 2b00 cmp r3, #0
  10396. 8004398: d10a bne.n 80043b0 <HAL_RCCEx_PeriphCLKConfig+0x4d8>
  10397. {
  10398. /* Set the source of SPI6 clock*/
  10399. __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
  10400. 800439a: 4b4b ldr r3, [pc, #300] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10401. 800439c: 6d9b ldr r3, [r3, #88] ; 0x58
  10402. 800439e: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000
  10403. 80043a2: 687b ldr r3, [r7, #4]
  10404. 80043a4: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8
  10405. 80043a8: 4947 ldr r1, [pc, #284] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10406. 80043aa: 4313 orrs r3, r2
  10407. 80043ac: 658b str r3, [r1, #88] ; 0x58
  10408. 80043ae: e001 b.n 80043b4 <HAL_RCCEx_PeriphCLKConfig+0x4dc>
  10409. }
  10410. else
  10411. {
  10412. /* set overall return value */
  10413. status = ret;
  10414. 80043b0: 7dfb ldrb r3, [r7, #23]
  10415. 80043b2: 75bb strb r3, [r7, #22]
  10416. }
  10417. #endif /*DSI*/
  10418. #if defined(FDCAN1) || defined(FDCAN2)
  10419. /*---------------------------- FDCAN configuration -------------------------------*/
  10420. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
  10421. 80043b4: 687b ldr r3, [r7, #4]
  10422. 80043b6: 681b ldr r3, [r3, #0]
  10423. 80043b8: f403 4300 and.w r3, r3, #32768 ; 0x8000
  10424. 80043bc: 2b00 cmp r3, #0
  10425. 80043be: d02f beq.n 8004420 <HAL_RCCEx_PeriphCLKConfig+0x548>
  10426. {
  10427. switch(PeriphClkInit->FdcanClockSelection)
  10428. 80043c0: 687b ldr r3, [r7, #4]
  10429. 80043c2: 6e9b ldr r3, [r3, #104] ; 0x68
  10430. 80043c4: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
  10431. 80043c8: d00e beq.n 80043e8 <HAL_RCCEx_PeriphCLKConfig+0x510>
  10432. 80043ca: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
  10433. 80043ce: d814 bhi.n 80043fa <HAL_RCCEx_PeriphCLKConfig+0x522>
  10434. 80043d0: 2b00 cmp r3, #0
  10435. 80043d2: d015 beq.n 8004400 <HAL_RCCEx_PeriphCLKConfig+0x528>
  10436. 80043d4: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
  10437. 80043d8: d10f bne.n 80043fa <HAL_RCCEx_PeriphCLKConfig+0x522>
  10438. {
  10439. case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/
  10440. /* Enable FDCAN Clock output generated form System PLL . */
  10441. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  10442. 80043da: 4b3b ldr r3, [pc, #236] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10443. 80043dc: 6adb ldr r3, [r3, #44] ; 0x2c
  10444. 80043de: 4a3a ldr r2, [pc, #232] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10445. 80043e0: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  10446. 80043e4: 62d3 str r3, [r2, #44] ; 0x2c
  10447. /* FDCAN clock source configuration done later after clock selection check */
  10448. break;
  10449. 80043e6: e00c b.n 8004402 <HAL_RCCEx_PeriphCLKConfig+0x52a>
  10450. case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
  10451. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
  10452. 80043e8: 687b ldr r3, [r7, #4]
  10453. 80043ea: 3304 adds r3, #4
  10454. 80043ec: 2101 movs r1, #1
  10455. 80043ee: 4618 mov r0, r3
  10456. 80043f0: f000 fc6c bl 8004ccc <RCCEx_PLL2_Config>
  10457. 80043f4: 4603 mov r3, r0
  10458. 80043f6: 75fb strb r3, [r7, #23]
  10459. /* FDCAN clock source configuration done later after clock selection check */
  10460. break;
  10461. 80043f8: e003 b.n 8004402 <HAL_RCCEx_PeriphCLKConfig+0x52a>
  10462. /* HSE is used as clock source for FDCAN*/
  10463. /* FDCAN clock source configuration done later after clock selection check */
  10464. break;
  10465. default:
  10466. ret = HAL_ERROR;
  10467. 80043fa: 2301 movs r3, #1
  10468. 80043fc: 75fb strb r3, [r7, #23]
  10469. break;
  10470. 80043fe: e000 b.n 8004402 <HAL_RCCEx_PeriphCLKConfig+0x52a>
  10471. break;
  10472. 8004400: bf00 nop
  10473. }
  10474. if(ret == HAL_OK)
  10475. 8004402: 7dfb ldrb r3, [r7, #23]
  10476. 8004404: 2b00 cmp r3, #0
  10477. 8004406: d109 bne.n 800441c <HAL_RCCEx_PeriphCLKConfig+0x544>
  10478. {
  10479. /* Set the source of FDCAN clock*/
  10480. __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
  10481. 8004408: 4b2f ldr r3, [pc, #188] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10482. 800440a: 6d1b ldr r3, [r3, #80] ; 0x50
  10483. 800440c: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000
  10484. 8004410: 687b ldr r3, [r7, #4]
  10485. 8004412: 6e9b ldr r3, [r3, #104] ; 0x68
  10486. 8004414: 492c ldr r1, [pc, #176] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10487. 8004416: 4313 orrs r3, r2
  10488. 8004418: 650b str r3, [r1, #80] ; 0x50
  10489. 800441a: e001 b.n 8004420 <HAL_RCCEx_PeriphCLKConfig+0x548>
  10490. }
  10491. else
  10492. {
  10493. /* set overall return value */
  10494. status = ret;
  10495. 800441c: 7dfb ldrb r3, [r7, #23]
  10496. 800441e: 75bb strb r3, [r7, #22]
  10497. }
  10498. }
  10499. #endif /*FDCAN1 || FDCAN2*/
  10500. /*---------------------------- FMC configuration -------------------------------*/
  10501. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
  10502. 8004420: 687b ldr r3, [r7, #4]
  10503. 8004422: 681b ldr r3, [r3, #0]
  10504. 8004424: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
  10505. 8004428: 2b00 cmp r3, #0
  10506. 800442a: d032 beq.n 8004492 <HAL_RCCEx_PeriphCLKConfig+0x5ba>
  10507. {
  10508. switch(PeriphClkInit->FmcClockSelection)
  10509. 800442c: 687b ldr r3, [r7, #4]
  10510. 800442e: 6c5b ldr r3, [r3, #68] ; 0x44
  10511. 8004430: 2b03 cmp r3, #3
  10512. 8004432: d81b bhi.n 800446c <HAL_RCCEx_PeriphCLKConfig+0x594>
  10513. 8004434: a201 add r2, pc, #4 ; (adr r2, 800443c <HAL_RCCEx_PeriphCLKConfig+0x564>)
  10514. 8004436: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  10515. 800443a: bf00 nop
  10516. 800443c: 08004473 .word 0x08004473
  10517. 8004440: 0800444d .word 0x0800444d
  10518. 8004444: 0800445b .word 0x0800445b
  10519. 8004448: 08004473 .word 0x08004473
  10520. {
  10521. case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/
  10522. /* Enable FMC Clock output generated form System PLL . */
  10523. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  10524. 800444c: 4b1e ldr r3, [pc, #120] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10525. 800444e: 6adb ldr r3, [r3, #44] ; 0x2c
  10526. 8004450: 4a1d ldr r2, [pc, #116] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10527. 8004452: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  10528. 8004456: 62d3 str r3, [r2, #44] ; 0x2c
  10529. /* FMC clock source configuration done later after clock selection check */
  10530. break;
  10531. 8004458: e00c b.n 8004474 <HAL_RCCEx_PeriphCLKConfig+0x59c>
  10532. case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
  10533. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
  10534. 800445a: 687b ldr r3, [r7, #4]
  10535. 800445c: 3304 adds r3, #4
  10536. 800445e: 2102 movs r1, #2
  10537. 8004460: 4618 mov r0, r3
  10538. 8004462: f000 fc33 bl 8004ccc <RCCEx_PLL2_Config>
  10539. 8004466: 4603 mov r3, r0
  10540. 8004468: 75fb strb r3, [r7, #23]
  10541. /* FMC clock source configuration done later after clock selection check */
  10542. break;
  10543. 800446a: e003 b.n 8004474 <HAL_RCCEx_PeriphCLKConfig+0x59c>
  10544. case RCC_FMCCLKSOURCE_HCLK:
  10545. /* D1/CD HCLK clock selected as FMC kernel peripheral clock */
  10546. break;
  10547. default:
  10548. ret = HAL_ERROR;
  10549. 800446c: 2301 movs r3, #1
  10550. 800446e: 75fb strb r3, [r7, #23]
  10551. break;
  10552. 8004470: e000 b.n 8004474 <HAL_RCCEx_PeriphCLKConfig+0x59c>
  10553. break;
  10554. 8004472: bf00 nop
  10555. }
  10556. if(ret == HAL_OK)
  10557. 8004474: 7dfb ldrb r3, [r7, #23]
  10558. 8004476: 2b00 cmp r3, #0
  10559. 8004478: d109 bne.n 800448e <HAL_RCCEx_PeriphCLKConfig+0x5b6>
  10560. {
  10561. /* Set the source of FMC clock*/
  10562. __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
  10563. 800447a: 4b13 ldr r3, [pc, #76] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10564. 800447c: 6cdb ldr r3, [r3, #76] ; 0x4c
  10565. 800447e: f023 0203 bic.w r2, r3, #3
  10566. 8004482: 687b ldr r3, [r7, #4]
  10567. 8004484: 6c5b ldr r3, [r3, #68] ; 0x44
  10568. 8004486: 4910 ldr r1, [pc, #64] ; (80044c8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>)
  10569. 8004488: 4313 orrs r3, r2
  10570. 800448a: 64cb str r3, [r1, #76] ; 0x4c
  10571. 800448c: e001 b.n 8004492 <HAL_RCCEx_PeriphCLKConfig+0x5ba>
  10572. }
  10573. else
  10574. {
  10575. /* set overall return value */
  10576. status = ret;
  10577. 800448e: 7dfb ldrb r3, [r7, #23]
  10578. 8004490: 75bb strb r3, [r7, #22]
  10579. }
  10580. }
  10581. /*---------------------------- RTC configuration -------------------------------*/
  10582. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
  10583. 8004492: 687b ldr r3, [r7, #4]
  10584. 8004494: 681b ldr r3, [r3, #0]
  10585. 8004496: f403 0380 and.w r3, r3, #4194304 ; 0x400000
  10586. 800449a: 2b00 cmp r3, #0
  10587. 800449c: f000 808a beq.w 80045b4 <HAL_RCCEx_PeriphCLKConfig+0x6dc>
  10588. {
  10589. /* check for RTC Parameters used to output RTCCLK */
  10590. assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
  10591. /* Enable write access to Backup domain */
  10592. SET_BIT(PWR->CR1, PWR_CR1_DBP);
  10593. 80044a0: 4b0a ldr r3, [pc, #40] ; (80044cc <HAL_RCCEx_PeriphCLKConfig+0x5f4>)
  10594. 80044a2: 681b ldr r3, [r3, #0]
  10595. 80044a4: 4a09 ldr r2, [pc, #36] ; (80044cc <HAL_RCCEx_PeriphCLKConfig+0x5f4>)
  10596. 80044a6: f443 7380 orr.w r3, r3, #256 ; 0x100
  10597. 80044aa: 6013 str r3, [r2, #0]
  10598. /* Wait for Backup domain Write protection disable */
  10599. tickstart = HAL_GetTick();
  10600. 80044ac: f7fd f8d4 bl 8001658 <HAL_GetTick>
  10601. 80044b0: 6138 str r0, [r7, #16]
  10602. while((PWR->CR1 & PWR_CR1_DBP) == 0U)
  10603. 80044b2: e00d b.n 80044d0 <HAL_RCCEx_PeriphCLKConfig+0x5f8>
  10604. {
  10605. if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
  10606. 80044b4: f7fd f8d0 bl 8001658 <HAL_GetTick>
  10607. 80044b8: 4602 mov r2, r0
  10608. 80044ba: 693b ldr r3, [r7, #16]
  10609. 80044bc: 1ad3 subs r3, r2, r3
  10610. 80044be: 2b64 cmp r3, #100 ; 0x64
  10611. 80044c0: d906 bls.n 80044d0 <HAL_RCCEx_PeriphCLKConfig+0x5f8>
  10612. {
  10613. ret = HAL_TIMEOUT;
  10614. 80044c2: 2303 movs r3, #3
  10615. 80044c4: 75fb strb r3, [r7, #23]
  10616. break;
  10617. 80044c6: e009 b.n 80044dc <HAL_RCCEx_PeriphCLKConfig+0x604>
  10618. 80044c8: 58024400 .word 0x58024400
  10619. 80044cc: 58024800 .word 0x58024800
  10620. while((PWR->CR1 & PWR_CR1_DBP) == 0U)
  10621. 80044d0: 4bb9 ldr r3, [pc, #740] ; (80047b8 <HAL_RCCEx_PeriphCLKConfig+0x8e0>)
  10622. 80044d2: 681b ldr r3, [r3, #0]
  10623. 80044d4: f403 7380 and.w r3, r3, #256 ; 0x100
  10624. 80044d8: 2b00 cmp r3, #0
  10625. 80044da: d0eb beq.n 80044b4 <HAL_RCCEx_PeriphCLKConfig+0x5dc>
  10626. }
  10627. }
  10628. if(ret == HAL_OK)
  10629. 80044dc: 7dfb ldrb r3, [r7, #23]
  10630. 80044de: 2b00 cmp r3, #0
  10631. 80044e0: d166 bne.n 80045b0 <HAL_RCCEx_PeriphCLKConfig+0x6d8>
  10632. {
  10633. /* Reset the Backup domain only if the RTC Clock source selection is modified */
  10634. if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
  10635. 80044e2: 4bb6 ldr r3, [pc, #728] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10636. 80044e4: 6f1a ldr r2, [r3, #112] ; 0x70
  10637. 80044e6: 687b ldr r3, [r7, #4]
  10638. 80044e8: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac
  10639. 80044ec: 4053 eors r3, r2
  10640. 80044ee: f403 7340 and.w r3, r3, #768 ; 0x300
  10641. 80044f2: 2b00 cmp r3, #0
  10642. 80044f4: d013 beq.n 800451e <HAL_RCCEx_PeriphCLKConfig+0x646>
  10643. {
  10644. /* Store the content of BDCR register before the reset of Backup Domain */
  10645. tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
  10646. 80044f6: 4bb1 ldr r3, [pc, #708] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10647. 80044f8: 6f1b ldr r3, [r3, #112] ; 0x70
  10648. 80044fa: f423 7340 bic.w r3, r3, #768 ; 0x300
  10649. 80044fe: 60fb str r3, [r7, #12]
  10650. /* RTC Clock selection can be changed only if the Backup Domain is reset */
  10651. __HAL_RCC_BACKUPRESET_FORCE();
  10652. 8004500: 4bae ldr r3, [pc, #696] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10653. 8004502: 6f1b ldr r3, [r3, #112] ; 0x70
  10654. 8004504: 4aad ldr r2, [pc, #692] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10655. 8004506: f443 3380 orr.w r3, r3, #65536 ; 0x10000
  10656. 800450a: 6713 str r3, [r2, #112] ; 0x70
  10657. __HAL_RCC_BACKUPRESET_RELEASE();
  10658. 800450c: 4bab ldr r3, [pc, #684] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10659. 800450e: 6f1b ldr r3, [r3, #112] ; 0x70
  10660. 8004510: 4aaa ldr r2, [pc, #680] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10661. 8004512: f423 3380 bic.w r3, r3, #65536 ; 0x10000
  10662. 8004516: 6713 str r3, [r2, #112] ; 0x70
  10663. /* Restore the Content of BDCR register */
  10664. RCC->BDCR = tmpreg;
  10665. 8004518: 4aa8 ldr r2, [pc, #672] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10666. 800451a: 68fb ldr r3, [r7, #12]
  10667. 800451c: 6713 str r3, [r2, #112] ; 0x70
  10668. }
  10669. /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
  10670. if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
  10671. 800451e: 687b ldr r3, [r7, #4]
  10672. 8004520: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac
  10673. 8004524: f5b3 7f80 cmp.w r3, #256 ; 0x100
  10674. 8004528: d115 bne.n 8004556 <HAL_RCCEx_PeriphCLKConfig+0x67e>
  10675. {
  10676. /* Get Start Tick*/
  10677. tickstart = HAL_GetTick();
  10678. 800452a: f7fd f895 bl 8001658 <HAL_GetTick>
  10679. 800452e: 6138 str r0, [r7, #16]
  10680. /* Wait till LSE is ready */
  10681. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  10682. 8004530: e00b b.n 800454a <HAL_RCCEx_PeriphCLKConfig+0x672>
  10683. {
  10684. if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
  10685. 8004532: f7fd f891 bl 8001658 <HAL_GetTick>
  10686. 8004536: 4602 mov r2, r0
  10687. 8004538: 693b ldr r3, [r7, #16]
  10688. 800453a: 1ad3 subs r3, r2, r3
  10689. 800453c: f241 3288 movw r2, #5000 ; 0x1388
  10690. 8004540: 4293 cmp r3, r2
  10691. 8004542: d902 bls.n 800454a <HAL_RCCEx_PeriphCLKConfig+0x672>
  10692. {
  10693. ret = HAL_TIMEOUT;
  10694. 8004544: 2303 movs r3, #3
  10695. 8004546: 75fb strb r3, [r7, #23]
  10696. break;
  10697. 8004548: e005 b.n 8004556 <HAL_RCCEx_PeriphCLKConfig+0x67e>
  10698. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  10699. 800454a: 4b9c ldr r3, [pc, #624] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10700. 800454c: 6f1b ldr r3, [r3, #112] ; 0x70
  10701. 800454e: f003 0302 and.w r3, r3, #2
  10702. 8004552: 2b00 cmp r3, #0
  10703. 8004554: d0ed beq.n 8004532 <HAL_RCCEx_PeriphCLKConfig+0x65a>
  10704. }
  10705. }
  10706. }
  10707. if(ret == HAL_OK)
  10708. 8004556: 7dfb ldrb r3, [r7, #23]
  10709. 8004558: 2b00 cmp r3, #0
  10710. 800455a: d126 bne.n 80045aa <HAL_RCCEx_PeriphCLKConfig+0x6d2>
  10711. {
  10712. __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
  10713. 800455c: 687b ldr r3, [r7, #4]
  10714. 800455e: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac
  10715. 8004562: f403 7340 and.w r3, r3, #768 ; 0x300
  10716. 8004566: f5b3 7f40 cmp.w r3, #768 ; 0x300
  10717. 800456a: d10d bne.n 8004588 <HAL_RCCEx_PeriphCLKConfig+0x6b0>
  10718. 800456c: 4b93 ldr r3, [pc, #588] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10719. 800456e: 691b ldr r3, [r3, #16]
  10720. 8004570: f423 527c bic.w r2, r3, #16128 ; 0x3f00
  10721. 8004574: 687b ldr r3, [r7, #4]
  10722. 8004576: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac
  10723. 800457a: 0919 lsrs r1, r3, #4
  10724. 800457c: 4b90 ldr r3, [pc, #576] ; (80047c0 <HAL_RCCEx_PeriphCLKConfig+0x8e8>)
  10725. 800457e: 400b ands r3, r1
  10726. 8004580: 498e ldr r1, [pc, #568] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10727. 8004582: 4313 orrs r3, r2
  10728. 8004584: 610b str r3, [r1, #16]
  10729. 8004586: e005 b.n 8004594 <HAL_RCCEx_PeriphCLKConfig+0x6bc>
  10730. 8004588: 4b8c ldr r3, [pc, #560] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10731. 800458a: 691b ldr r3, [r3, #16]
  10732. 800458c: 4a8b ldr r2, [pc, #556] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10733. 800458e: f423 537c bic.w r3, r3, #16128 ; 0x3f00
  10734. 8004592: 6113 str r3, [r2, #16]
  10735. 8004594: 4b89 ldr r3, [pc, #548] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10736. 8004596: 6f1a ldr r2, [r3, #112] ; 0x70
  10737. 8004598: 687b ldr r3, [r7, #4]
  10738. 800459a: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac
  10739. 800459e: f3c3 030b ubfx r3, r3, #0, #12
  10740. 80045a2: 4986 ldr r1, [pc, #536] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10741. 80045a4: 4313 orrs r3, r2
  10742. 80045a6: 670b str r3, [r1, #112] ; 0x70
  10743. 80045a8: e004 b.n 80045b4 <HAL_RCCEx_PeriphCLKConfig+0x6dc>
  10744. }
  10745. else
  10746. {
  10747. /* set overall return value */
  10748. status = ret;
  10749. 80045aa: 7dfb ldrb r3, [r7, #23]
  10750. 80045ac: 75bb strb r3, [r7, #22]
  10751. 80045ae: e001 b.n 80045b4 <HAL_RCCEx_PeriphCLKConfig+0x6dc>
  10752. }
  10753. }
  10754. else
  10755. {
  10756. /* set overall return value */
  10757. status = ret;
  10758. 80045b0: 7dfb ldrb r3, [r7, #23]
  10759. 80045b2: 75bb strb r3, [r7, #22]
  10760. }
  10761. }
  10762. /*-------------------------- USART1/6 configuration --------------------------*/
  10763. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
  10764. 80045b4: 687b ldr r3, [r7, #4]
  10765. 80045b6: 681b ldr r3, [r3, #0]
  10766. 80045b8: f003 0301 and.w r3, r3, #1
  10767. 80045bc: 2b00 cmp r3, #0
  10768. 80045be: d07e beq.n 80046be <HAL_RCCEx_PeriphCLKConfig+0x7e6>
  10769. {
  10770. switch(PeriphClkInit->Usart16ClockSelection)
  10771. 80045c0: 687b ldr r3, [r7, #4]
  10772. 80045c2: 6f5b ldr r3, [r3, #116] ; 0x74
  10773. 80045c4: 2b28 cmp r3, #40 ; 0x28
  10774. 80045c6: d867 bhi.n 8004698 <HAL_RCCEx_PeriphCLKConfig+0x7c0>
  10775. 80045c8: a201 add r2, pc, #4 ; (adr r2, 80045d0 <HAL_RCCEx_PeriphCLKConfig+0x6f8>)
  10776. 80045ca: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  10777. 80045ce: bf00 nop
  10778. 80045d0: 0800469f .word 0x0800469f
  10779. 80045d4: 08004699 .word 0x08004699
  10780. 80045d8: 08004699 .word 0x08004699
  10781. 80045dc: 08004699 .word 0x08004699
  10782. 80045e0: 08004699 .word 0x08004699
  10783. 80045e4: 08004699 .word 0x08004699
  10784. 80045e8: 08004699 .word 0x08004699
  10785. 80045ec: 08004699 .word 0x08004699
  10786. 80045f0: 08004675 .word 0x08004675
  10787. 80045f4: 08004699 .word 0x08004699
  10788. 80045f8: 08004699 .word 0x08004699
  10789. 80045fc: 08004699 .word 0x08004699
  10790. 8004600: 08004699 .word 0x08004699
  10791. 8004604: 08004699 .word 0x08004699
  10792. 8004608: 08004699 .word 0x08004699
  10793. 800460c: 08004699 .word 0x08004699
  10794. 8004610: 08004687 .word 0x08004687
  10795. 8004614: 08004699 .word 0x08004699
  10796. 8004618: 08004699 .word 0x08004699
  10797. 800461c: 08004699 .word 0x08004699
  10798. 8004620: 08004699 .word 0x08004699
  10799. 8004624: 08004699 .word 0x08004699
  10800. 8004628: 08004699 .word 0x08004699
  10801. 800462c: 08004699 .word 0x08004699
  10802. 8004630: 0800469f .word 0x0800469f
  10803. 8004634: 08004699 .word 0x08004699
  10804. 8004638: 08004699 .word 0x08004699
  10805. 800463c: 08004699 .word 0x08004699
  10806. 8004640: 08004699 .word 0x08004699
  10807. 8004644: 08004699 .word 0x08004699
  10808. 8004648: 08004699 .word 0x08004699
  10809. 800464c: 08004699 .word 0x08004699
  10810. 8004650: 0800469f .word 0x0800469f
  10811. 8004654: 08004699 .word 0x08004699
  10812. 8004658: 08004699 .word 0x08004699
  10813. 800465c: 08004699 .word 0x08004699
  10814. 8004660: 08004699 .word 0x08004699
  10815. 8004664: 08004699 .word 0x08004699
  10816. 8004668: 08004699 .word 0x08004699
  10817. 800466c: 08004699 .word 0x08004699
  10818. 8004670: 0800469f .word 0x0800469f
  10819. case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
  10820. /* USART1/6 clock source configuration done later after clock selection check */
  10821. break;
  10822. case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
  10823. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
  10824. 8004674: 687b ldr r3, [r7, #4]
  10825. 8004676: 3304 adds r3, #4
  10826. 8004678: 2101 movs r1, #1
  10827. 800467a: 4618 mov r0, r3
  10828. 800467c: f000 fb26 bl 8004ccc <RCCEx_PLL2_Config>
  10829. 8004680: 4603 mov r3, r0
  10830. 8004682: 75fb strb r3, [r7, #23]
  10831. /* USART1/6 clock source configuration done later after clock selection check */
  10832. break;
  10833. 8004684: e00c b.n 80046a0 <HAL_RCCEx_PeriphCLKConfig+0x7c8>
  10834. case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
  10835. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
  10836. 8004686: 687b ldr r3, [r7, #4]
  10837. 8004688: 3324 adds r3, #36 ; 0x24
  10838. 800468a: 2101 movs r1, #1
  10839. 800468c: 4618 mov r0, r3
  10840. 800468e: f000 fbcf bl 8004e30 <RCCEx_PLL3_Config>
  10841. 8004692: 4603 mov r3, r0
  10842. 8004694: 75fb strb r3, [r7, #23]
  10843. /* USART1/6 clock source configuration done later after clock selection check */
  10844. break;
  10845. 8004696: e003 b.n 80046a0 <HAL_RCCEx_PeriphCLKConfig+0x7c8>
  10846. /* LSE, oscillator is used as source of USART1/6 clock */
  10847. /* USART1/6 clock source configuration done later after clock selection check */
  10848. break;
  10849. default:
  10850. ret = HAL_ERROR;
  10851. 8004698: 2301 movs r3, #1
  10852. 800469a: 75fb strb r3, [r7, #23]
  10853. break;
  10854. 800469c: e000 b.n 80046a0 <HAL_RCCEx_PeriphCLKConfig+0x7c8>
  10855. break;
  10856. 800469e: bf00 nop
  10857. }
  10858. if(ret == HAL_OK)
  10859. 80046a0: 7dfb ldrb r3, [r7, #23]
  10860. 80046a2: 2b00 cmp r3, #0
  10861. 80046a4: d109 bne.n 80046ba <HAL_RCCEx_PeriphCLKConfig+0x7e2>
  10862. {
  10863. /* Set the source of USART1/6 clock */
  10864. __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
  10865. 80046a6: 4b45 ldr r3, [pc, #276] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10866. 80046a8: 6d5b ldr r3, [r3, #84] ; 0x54
  10867. 80046aa: f023 0238 bic.w r2, r3, #56 ; 0x38
  10868. 80046ae: 687b ldr r3, [r7, #4]
  10869. 80046b0: 6f5b ldr r3, [r3, #116] ; 0x74
  10870. 80046b2: 4942 ldr r1, [pc, #264] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10871. 80046b4: 4313 orrs r3, r2
  10872. 80046b6: 654b str r3, [r1, #84] ; 0x54
  10873. 80046b8: e001 b.n 80046be <HAL_RCCEx_PeriphCLKConfig+0x7e6>
  10874. }
  10875. else
  10876. {
  10877. /* set overall return value */
  10878. status = ret;
  10879. 80046ba: 7dfb ldrb r3, [r7, #23]
  10880. 80046bc: 75bb strb r3, [r7, #22]
  10881. }
  10882. }
  10883. /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
  10884. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
  10885. 80046be: 687b ldr r3, [r7, #4]
  10886. 80046c0: 681b ldr r3, [r3, #0]
  10887. 80046c2: f003 0302 and.w r3, r3, #2
  10888. 80046c6: 2b00 cmp r3, #0
  10889. 80046c8: d037 beq.n 800473a <HAL_RCCEx_PeriphCLKConfig+0x862>
  10890. {
  10891. switch(PeriphClkInit->Usart234578ClockSelection)
  10892. 80046ca: 687b ldr r3, [r7, #4]
  10893. 80046cc: 6f1b ldr r3, [r3, #112] ; 0x70
  10894. 80046ce: 2b05 cmp r3, #5
  10895. 80046d0: d820 bhi.n 8004714 <HAL_RCCEx_PeriphCLKConfig+0x83c>
  10896. 80046d2: a201 add r2, pc, #4 ; (adr r2, 80046d8 <HAL_RCCEx_PeriphCLKConfig+0x800>)
  10897. 80046d4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  10898. 80046d8: 0800471b .word 0x0800471b
  10899. 80046dc: 080046f1 .word 0x080046f1
  10900. 80046e0: 08004703 .word 0x08004703
  10901. 80046e4: 0800471b .word 0x0800471b
  10902. 80046e8: 0800471b .word 0x0800471b
  10903. 80046ec: 0800471b .word 0x0800471b
  10904. case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
  10905. /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
  10906. break;
  10907. case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
  10908. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
  10909. 80046f0: 687b ldr r3, [r7, #4]
  10910. 80046f2: 3304 adds r3, #4
  10911. 80046f4: 2101 movs r1, #1
  10912. 80046f6: 4618 mov r0, r3
  10913. 80046f8: f000 fae8 bl 8004ccc <RCCEx_PLL2_Config>
  10914. 80046fc: 4603 mov r3, r0
  10915. 80046fe: 75fb strb r3, [r7, #23]
  10916. /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
  10917. break;
  10918. 8004700: e00c b.n 800471c <HAL_RCCEx_PeriphCLKConfig+0x844>
  10919. case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
  10920. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
  10921. 8004702: 687b ldr r3, [r7, #4]
  10922. 8004704: 3324 adds r3, #36 ; 0x24
  10923. 8004706: 2101 movs r1, #1
  10924. 8004708: 4618 mov r0, r3
  10925. 800470a: f000 fb91 bl 8004e30 <RCCEx_PLL3_Config>
  10926. 800470e: 4603 mov r3, r0
  10927. 8004710: 75fb strb r3, [r7, #23]
  10928. /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
  10929. break;
  10930. 8004712: e003 b.n 800471c <HAL_RCCEx_PeriphCLKConfig+0x844>
  10931. /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */
  10932. /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
  10933. break;
  10934. default:
  10935. ret = HAL_ERROR;
  10936. 8004714: 2301 movs r3, #1
  10937. 8004716: 75fb strb r3, [r7, #23]
  10938. break;
  10939. 8004718: e000 b.n 800471c <HAL_RCCEx_PeriphCLKConfig+0x844>
  10940. break;
  10941. 800471a: bf00 nop
  10942. }
  10943. if(ret == HAL_OK)
  10944. 800471c: 7dfb ldrb r3, [r7, #23]
  10945. 800471e: 2b00 cmp r3, #0
  10946. 8004720: d109 bne.n 8004736 <HAL_RCCEx_PeriphCLKConfig+0x85e>
  10947. {
  10948. /* Set the source of USART2/3/4/5/7/8 clock */
  10949. __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
  10950. 8004722: 4b26 ldr r3, [pc, #152] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10951. 8004724: 6d5b ldr r3, [r3, #84] ; 0x54
  10952. 8004726: f023 0207 bic.w r2, r3, #7
  10953. 800472a: 687b ldr r3, [r7, #4]
  10954. 800472c: 6f1b ldr r3, [r3, #112] ; 0x70
  10955. 800472e: 4923 ldr r1, [pc, #140] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  10956. 8004730: 4313 orrs r3, r2
  10957. 8004732: 654b str r3, [r1, #84] ; 0x54
  10958. 8004734: e001 b.n 800473a <HAL_RCCEx_PeriphCLKConfig+0x862>
  10959. }
  10960. else
  10961. {
  10962. /* set overall return value */
  10963. status = ret;
  10964. 8004736: 7dfb ldrb r3, [r7, #23]
  10965. 8004738: 75bb strb r3, [r7, #22]
  10966. }
  10967. }
  10968. /*-------------------------- LPUART1 Configuration -------------------------*/
  10969. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
  10970. 800473a: 687b ldr r3, [r7, #4]
  10971. 800473c: 681b ldr r3, [r3, #0]
  10972. 800473e: f003 0304 and.w r3, r3, #4
  10973. 8004742: 2b00 cmp r3, #0
  10974. 8004744: d040 beq.n 80047c8 <HAL_RCCEx_PeriphCLKConfig+0x8f0>
  10975. {
  10976. switch(PeriphClkInit->Lpuart1ClockSelection)
  10977. 8004746: 687b ldr r3, [r7, #4]
  10978. 8004748: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
  10979. 800474c: 2b05 cmp r3, #5
  10980. 800474e: d821 bhi.n 8004794 <HAL_RCCEx_PeriphCLKConfig+0x8bc>
  10981. 8004750: a201 add r2, pc, #4 ; (adr r2, 8004758 <HAL_RCCEx_PeriphCLKConfig+0x880>)
  10982. 8004752: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  10983. 8004756: bf00 nop
  10984. 8004758: 0800479b .word 0x0800479b
  10985. 800475c: 08004771 .word 0x08004771
  10986. 8004760: 08004783 .word 0x08004783
  10987. 8004764: 0800479b .word 0x0800479b
  10988. 8004768: 0800479b .word 0x0800479b
  10989. 800476c: 0800479b .word 0x0800479b
  10990. case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
  10991. /* LPUART1 clock source configuration done later after clock selection check */
  10992. break;
  10993. case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
  10994. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
  10995. 8004770: 687b ldr r3, [r7, #4]
  10996. 8004772: 3304 adds r3, #4
  10997. 8004774: 2101 movs r1, #1
  10998. 8004776: 4618 mov r0, r3
  10999. 8004778: f000 faa8 bl 8004ccc <RCCEx_PLL2_Config>
  11000. 800477c: 4603 mov r3, r0
  11001. 800477e: 75fb strb r3, [r7, #23]
  11002. /* LPUART1 clock source configuration done later after clock selection check */
  11003. break;
  11004. 8004780: e00c b.n 800479c <HAL_RCCEx_PeriphCLKConfig+0x8c4>
  11005. case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
  11006. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
  11007. 8004782: 687b ldr r3, [r7, #4]
  11008. 8004784: 3324 adds r3, #36 ; 0x24
  11009. 8004786: 2101 movs r1, #1
  11010. 8004788: 4618 mov r0, r3
  11011. 800478a: f000 fb51 bl 8004e30 <RCCEx_PLL3_Config>
  11012. 800478e: 4603 mov r3, r0
  11013. 8004790: 75fb strb r3, [r7, #23]
  11014. /* LPUART1 clock source configuration done later after clock selection check */
  11015. break;
  11016. 8004792: e003 b.n 800479c <HAL_RCCEx_PeriphCLKConfig+0x8c4>
  11017. /* LSE, oscillator is used as source of LPUART1 clock */
  11018. /* LPUART1 clock source configuration done later after clock selection check */
  11019. break;
  11020. default:
  11021. ret = HAL_ERROR;
  11022. 8004794: 2301 movs r3, #1
  11023. 8004796: 75fb strb r3, [r7, #23]
  11024. break;
  11025. 8004798: e000 b.n 800479c <HAL_RCCEx_PeriphCLKConfig+0x8c4>
  11026. break;
  11027. 800479a: bf00 nop
  11028. }
  11029. if(ret == HAL_OK)
  11030. 800479c: 7dfb ldrb r3, [r7, #23]
  11031. 800479e: 2b00 cmp r3, #0
  11032. 80047a0: d110 bne.n 80047c4 <HAL_RCCEx_PeriphCLKConfig+0x8ec>
  11033. {
  11034. /* Set the source of LPUART1 clock */
  11035. __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
  11036. 80047a2: 4b06 ldr r3, [pc, #24] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  11037. 80047a4: 6d9b ldr r3, [r3, #88] ; 0x58
  11038. 80047a6: f023 0207 bic.w r2, r3, #7
  11039. 80047aa: 687b ldr r3, [r7, #4]
  11040. 80047ac: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
  11041. 80047b0: 4902 ldr r1, [pc, #8] ; (80047bc <HAL_RCCEx_PeriphCLKConfig+0x8e4>)
  11042. 80047b2: 4313 orrs r3, r2
  11043. 80047b4: 658b str r3, [r1, #88] ; 0x58
  11044. 80047b6: e007 b.n 80047c8 <HAL_RCCEx_PeriphCLKConfig+0x8f0>
  11045. 80047b8: 58024800 .word 0x58024800
  11046. 80047bc: 58024400 .word 0x58024400
  11047. 80047c0: 00ffffcf .word 0x00ffffcf
  11048. }
  11049. else
  11050. {
  11051. /* set overall return value */
  11052. status = ret;
  11053. 80047c4: 7dfb ldrb r3, [r7, #23]
  11054. 80047c6: 75bb strb r3, [r7, #22]
  11055. }
  11056. }
  11057. /*---------------------------- LPTIM1 configuration -------------------------------*/
  11058. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
  11059. 80047c8: 687b ldr r3, [r7, #4]
  11060. 80047ca: 681b ldr r3, [r3, #0]
  11061. 80047cc: f003 0320 and.w r3, r3, #32
  11062. 80047d0: 2b00 cmp r3, #0
  11063. 80047d2: d04b beq.n 800486c <HAL_RCCEx_PeriphCLKConfig+0x994>
  11064. {
  11065. switch(PeriphClkInit->Lptim1ClockSelection)
  11066. 80047d4: 687b ldr r3, [r7, #4]
  11067. 80047d6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
  11068. 80047da: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000
  11069. 80047de: d02e beq.n 800483e <HAL_RCCEx_PeriphCLKConfig+0x966>
  11070. 80047e0: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000
  11071. 80047e4: d828 bhi.n 8004838 <HAL_RCCEx_PeriphCLKConfig+0x960>
  11072. 80047e6: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
  11073. 80047ea: d02a beq.n 8004842 <HAL_RCCEx_PeriphCLKConfig+0x96a>
  11074. 80047ec: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
  11075. 80047f0: d822 bhi.n 8004838 <HAL_RCCEx_PeriphCLKConfig+0x960>
  11076. 80047f2: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000
  11077. 80047f6: d026 beq.n 8004846 <HAL_RCCEx_PeriphCLKConfig+0x96e>
  11078. 80047f8: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000
  11079. 80047fc: d81c bhi.n 8004838 <HAL_RCCEx_PeriphCLKConfig+0x960>
  11080. 80047fe: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
  11081. 8004802: d010 beq.n 8004826 <HAL_RCCEx_PeriphCLKConfig+0x94e>
  11082. 8004804: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
  11083. 8004808: d816 bhi.n 8004838 <HAL_RCCEx_PeriphCLKConfig+0x960>
  11084. 800480a: 2b00 cmp r3, #0
  11085. 800480c: d01d beq.n 800484a <HAL_RCCEx_PeriphCLKConfig+0x972>
  11086. 800480e: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
  11087. 8004812: d111 bne.n 8004838 <HAL_RCCEx_PeriphCLKConfig+0x960>
  11088. /* LPTIM1 clock source configuration done later after clock selection check */
  11089. break;
  11090. case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
  11091. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
  11092. 8004814: 687b ldr r3, [r7, #4]
  11093. 8004816: 3304 adds r3, #4
  11094. 8004818: 2100 movs r1, #0
  11095. 800481a: 4618 mov r0, r3
  11096. 800481c: f000 fa56 bl 8004ccc <RCCEx_PLL2_Config>
  11097. 8004820: 4603 mov r3, r0
  11098. 8004822: 75fb strb r3, [r7, #23]
  11099. /* LPTIM1 clock source configuration done later after clock selection check */
  11100. break;
  11101. 8004824: e012 b.n 800484c <HAL_RCCEx_PeriphCLKConfig+0x974>
  11102. case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/
  11103. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
  11104. 8004826: 687b ldr r3, [r7, #4]
  11105. 8004828: 3324 adds r3, #36 ; 0x24
  11106. 800482a: 2102 movs r1, #2
  11107. 800482c: 4618 mov r0, r3
  11108. 800482e: f000 faff bl 8004e30 <RCCEx_PLL3_Config>
  11109. 8004832: 4603 mov r3, r0
  11110. 8004834: 75fb strb r3, [r7, #23]
  11111. /* LPTIM1 clock source configuration done later after clock selection check */
  11112. break;
  11113. 8004836: e009 b.n 800484c <HAL_RCCEx_PeriphCLKConfig+0x974>
  11114. /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
  11115. /* LPTIM1 clock source configuration done later after clock selection check */
  11116. break;
  11117. default:
  11118. ret = HAL_ERROR;
  11119. 8004838: 2301 movs r3, #1
  11120. 800483a: 75fb strb r3, [r7, #23]
  11121. break;
  11122. 800483c: e006 b.n 800484c <HAL_RCCEx_PeriphCLKConfig+0x974>
  11123. break;
  11124. 800483e: bf00 nop
  11125. 8004840: e004 b.n 800484c <HAL_RCCEx_PeriphCLKConfig+0x974>
  11126. break;
  11127. 8004842: bf00 nop
  11128. 8004844: e002 b.n 800484c <HAL_RCCEx_PeriphCLKConfig+0x974>
  11129. break;
  11130. 8004846: bf00 nop
  11131. 8004848: e000 b.n 800484c <HAL_RCCEx_PeriphCLKConfig+0x974>
  11132. break;
  11133. 800484a: bf00 nop
  11134. }
  11135. if(ret == HAL_OK)
  11136. 800484c: 7dfb ldrb r3, [r7, #23]
  11137. 800484e: 2b00 cmp r3, #0
  11138. 8004850: d10a bne.n 8004868 <HAL_RCCEx_PeriphCLKConfig+0x990>
  11139. {
  11140. /* Set the source of LPTIM1 clock*/
  11141. __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
  11142. 8004852: 4bb2 ldr r3, [pc, #712] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11143. 8004854: 6d5b ldr r3, [r3, #84] ; 0x54
  11144. 8004856: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000
  11145. 800485a: 687b ldr r3, [r7, #4]
  11146. 800485c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
  11147. 8004860: 49ae ldr r1, [pc, #696] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11148. 8004862: 4313 orrs r3, r2
  11149. 8004864: 654b str r3, [r1, #84] ; 0x54
  11150. 8004866: e001 b.n 800486c <HAL_RCCEx_PeriphCLKConfig+0x994>
  11151. }
  11152. else
  11153. {
  11154. /* set overall return value */
  11155. status = ret;
  11156. 8004868: 7dfb ldrb r3, [r7, #23]
  11157. 800486a: 75bb strb r3, [r7, #22]
  11158. }
  11159. }
  11160. /*---------------------------- LPTIM2 configuration -------------------------------*/
  11161. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
  11162. 800486c: 687b ldr r3, [r7, #4]
  11163. 800486e: 681b ldr r3, [r3, #0]
  11164. 8004870: f003 0340 and.w r3, r3, #64 ; 0x40
  11165. 8004874: 2b00 cmp r3, #0
  11166. 8004876: d04b beq.n 8004910 <HAL_RCCEx_PeriphCLKConfig+0xa38>
  11167. {
  11168. switch(PeriphClkInit->Lptim2ClockSelection)
  11169. 8004878: 687b ldr r3, [r7, #4]
  11170. 800487a: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
  11171. 800487e: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400
  11172. 8004882: d02e beq.n 80048e2 <HAL_RCCEx_PeriphCLKConfig+0xa0a>
  11173. 8004884: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400
  11174. 8004888: d828 bhi.n 80048dc <HAL_RCCEx_PeriphCLKConfig+0xa04>
  11175. 800488a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  11176. 800488e: d02a beq.n 80048e6 <HAL_RCCEx_PeriphCLKConfig+0xa0e>
  11177. 8004890: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  11178. 8004894: d822 bhi.n 80048dc <HAL_RCCEx_PeriphCLKConfig+0xa04>
  11179. 8004896: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
  11180. 800489a: d026 beq.n 80048ea <HAL_RCCEx_PeriphCLKConfig+0xa12>
  11181. 800489c: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
  11182. 80048a0: d81c bhi.n 80048dc <HAL_RCCEx_PeriphCLKConfig+0xa04>
  11183. 80048a2: f5b3 6f00 cmp.w r3, #2048 ; 0x800
  11184. 80048a6: d010 beq.n 80048ca <HAL_RCCEx_PeriphCLKConfig+0x9f2>
  11185. 80048a8: f5b3 6f00 cmp.w r3, #2048 ; 0x800
  11186. 80048ac: d816 bhi.n 80048dc <HAL_RCCEx_PeriphCLKConfig+0xa04>
  11187. 80048ae: 2b00 cmp r3, #0
  11188. 80048b0: d01d beq.n 80048ee <HAL_RCCEx_PeriphCLKConfig+0xa16>
  11189. 80048b2: f5b3 6f80 cmp.w r3, #1024 ; 0x400
  11190. 80048b6: d111 bne.n 80048dc <HAL_RCCEx_PeriphCLKConfig+0xa04>
  11191. /* LPTIM2 clock source configuration done later after clock selection check */
  11192. break;
  11193. case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
  11194. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
  11195. 80048b8: 687b ldr r3, [r7, #4]
  11196. 80048ba: 3304 adds r3, #4
  11197. 80048bc: 2100 movs r1, #0
  11198. 80048be: 4618 mov r0, r3
  11199. 80048c0: f000 fa04 bl 8004ccc <RCCEx_PLL2_Config>
  11200. 80048c4: 4603 mov r3, r0
  11201. 80048c6: 75fb strb r3, [r7, #23]
  11202. /* LPTIM2 clock source configuration done later after clock selection check */
  11203. break;
  11204. 80048c8: e012 b.n 80048f0 <HAL_RCCEx_PeriphCLKConfig+0xa18>
  11205. case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/
  11206. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
  11207. 80048ca: 687b ldr r3, [r7, #4]
  11208. 80048cc: 3324 adds r3, #36 ; 0x24
  11209. 80048ce: 2102 movs r1, #2
  11210. 80048d0: 4618 mov r0, r3
  11211. 80048d2: f000 faad bl 8004e30 <RCCEx_PLL3_Config>
  11212. 80048d6: 4603 mov r3, r0
  11213. 80048d8: 75fb strb r3, [r7, #23]
  11214. /* LPTIM2 clock source configuration done later after clock selection check */
  11215. break;
  11216. 80048da: e009 b.n 80048f0 <HAL_RCCEx_PeriphCLKConfig+0xa18>
  11217. /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
  11218. /* LPTIM2 clock source configuration done later after clock selection check */
  11219. break;
  11220. default:
  11221. ret = HAL_ERROR;
  11222. 80048dc: 2301 movs r3, #1
  11223. 80048de: 75fb strb r3, [r7, #23]
  11224. break;
  11225. 80048e0: e006 b.n 80048f0 <HAL_RCCEx_PeriphCLKConfig+0xa18>
  11226. break;
  11227. 80048e2: bf00 nop
  11228. 80048e4: e004 b.n 80048f0 <HAL_RCCEx_PeriphCLKConfig+0xa18>
  11229. break;
  11230. 80048e6: bf00 nop
  11231. 80048e8: e002 b.n 80048f0 <HAL_RCCEx_PeriphCLKConfig+0xa18>
  11232. break;
  11233. 80048ea: bf00 nop
  11234. 80048ec: e000 b.n 80048f0 <HAL_RCCEx_PeriphCLKConfig+0xa18>
  11235. break;
  11236. 80048ee: bf00 nop
  11237. }
  11238. if(ret == HAL_OK)
  11239. 80048f0: 7dfb ldrb r3, [r7, #23]
  11240. 80048f2: 2b00 cmp r3, #0
  11241. 80048f4: d10a bne.n 800490c <HAL_RCCEx_PeriphCLKConfig+0xa34>
  11242. {
  11243. /* Set the source of LPTIM2 clock*/
  11244. __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
  11245. 80048f6: 4b89 ldr r3, [pc, #548] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11246. 80048f8: 6d9b ldr r3, [r3, #88] ; 0x58
  11247. 80048fa: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
  11248. 80048fe: 687b ldr r3, [r7, #4]
  11249. 8004900: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
  11250. 8004904: 4985 ldr r1, [pc, #532] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11251. 8004906: 4313 orrs r3, r2
  11252. 8004908: 658b str r3, [r1, #88] ; 0x58
  11253. 800490a: e001 b.n 8004910 <HAL_RCCEx_PeriphCLKConfig+0xa38>
  11254. }
  11255. else
  11256. {
  11257. /* set overall return value */
  11258. status = ret;
  11259. 800490c: 7dfb ldrb r3, [r7, #23]
  11260. 800490e: 75bb strb r3, [r7, #22]
  11261. }
  11262. }
  11263. /*---------------------------- LPTIM345 configuration -------------------------------*/
  11264. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
  11265. 8004910: 687b ldr r3, [r7, #4]
  11266. 8004912: 681b ldr r3, [r3, #0]
  11267. 8004914: f003 0380 and.w r3, r3, #128 ; 0x80
  11268. 8004918: 2b00 cmp r3, #0
  11269. 800491a: d04b beq.n 80049b4 <HAL_RCCEx_PeriphCLKConfig+0xadc>
  11270. {
  11271. switch(PeriphClkInit->Lptim345ClockSelection)
  11272. 800491c: 687b ldr r3, [r7, #4]
  11273. 800491e: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
  11274. 8004922: f5b3 4f20 cmp.w r3, #40960 ; 0xa000
  11275. 8004926: d02e beq.n 8004986 <HAL_RCCEx_PeriphCLKConfig+0xaae>
  11276. 8004928: f5b3 4f20 cmp.w r3, #40960 ; 0xa000
  11277. 800492c: d828 bhi.n 8004980 <HAL_RCCEx_PeriphCLKConfig+0xaa8>
  11278. 800492e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
  11279. 8004932: d02a beq.n 800498a <HAL_RCCEx_PeriphCLKConfig+0xab2>
  11280. 8004934: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
  11281. 8004938: d822 bhi.n 8004980 <HAL_RCCEx_PeriphCLKConfig+0xaa8>
  11282. 800493a: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000
  11283. 800493e: d026 beq.n 800498e <HAL_RCCEx_PeriphCLKConfig+0xab6>
  11284. 8004940: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000
  11285. 8004944: d81c bhi.n 8004980 <HAL_RCCEx_PeriphCLKConfig+0xaa8>
  11286. 8004946: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
  11287. 800494a: d010 beq.n 800496e <HAL_RCCEx_PeriphCLKConfig+0xa96>
  11288. 800494c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
  11289. 8004950: d816 bhi.n 8004980 <HAL_RCCEx_PeriphCLKConfig+0xaa8>
  11290. 8004952: 2b00 cmp r3, #0
  11291. 8004954: d01d beq.n 8004992 <HAL_RCCEx_PeriphCLKConfig+0xaba>
  11292. 8004956: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
  11293. 800495a: d111 bne.n 8004980 <HAL_RCCEx_PeriphCLKConfig+0xaa8>
  11294. case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
  11295. /* LPTIM3/4/5 clock source configuration done later after clock selection check */
  11296. break;
  11297. case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
  11298. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
  11299. 800495c: 687b ldr r3, [r7, #4]
  11300. 800495e: 3304 adds r3, #4
  11301. 8004960: 2100 movs r1, #0
  11302. 8004962: 4618 mov r0, r3
  11303. 8004964: f000 f9b2 bl 8004ccc <RCCEx_PLL2_Config>
  11304. 8004968: 4603 mov r3, r0
  11305. 800496a: 75fb strb r3, [r7, #23]
  11306. /* LPTIM3/4/5 clock source configuration done later after clock selection check */
  11307. break;
  11308. 800496c: e012 b.n 8004994 <HAL_RCCEx_PeriphCLKConfig+0xabc>
  11309. case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */
  11310. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
  11311. 800496e: 687b ldr r3, [r7, #4]
  11312. 8004970: 3324 adds r3, #36 ; 0x24
  11313. 8004972: 2102 movs r1, #2
  11314. 8004974: 4618 mov r0, r3
  11315. 8004976: f000 fa5b bl 8004e30 <RCCEx_PLL3_Config>
  11316. 800497a: 4603 mov r3, r0
  11317. 800497c: 75fb strb r3, [r7, #23]
  11318. /* LPTIM3/4/5 clock source configuration done later after clock selection check */
  11319. break;
  11320. 800497e: e009 b.n 8004994 <HAL_RCCEx_PeriphCLKConfig+0xabc>
  11321. /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
  11322. /* LPTIM3/4/5 clock source configuration done later after clock selection check */
  11323. break;
  11324. default:
  11325. ret = HAL_ERROR;
  11326. 8004980: 2301 movs r3, #1
  11327. 8004982: 75fb strb r3, [r7, #23]
  11328. break;
  11329. 8004984: e006 b.n 8004994 <HAL_RCCEx_PeriphCLKConfig+0xabc>
  11330. break;
  11331. 8004986: bf00 nop
  11332. 8004988: e004 b.n 8004994 <HAL_RCCEx_PeriphCLKConfig+0xabc>
  11333. break;
  11334. 800498a: bf00 nop
  11335. 800498c: e002 b.n 8004994 <HAL_RCCEx_PeriphCLKConfig+0xabc>
  11336. break;
  11337. 800498e: bf00 nop
  11338. 8004990: e000 b.n 8004994 <HAL_RCCEx_PeriphCLKConfig+0xabc>
  11339. break;
  11340. 8004992: bf00 nop
  11341. }
  11342. if(ret == HAL_OK)
  11343. 8004994: 7dfb ldrb r3, [r7, #23]
  11344. 8004996: 2b00 cmp r3, #0
  11345. 8004998: d10a bne.n 80049b0 <HAL_RCCEx_PeriphCLKConfig+0xad8>
  11346. {
  11347. /* Set the source of LPTIM3/4/5 clock */
  11348. __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
  11349. 800499a: 4b60 ldr r3, [pc, #384] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11350. 800499c: 6d9b ldr r3, [r3, #88] ; 0x58
  11351. 800499e: f423 4260 bic.w r2, r3, #57344 ; 0xe000
  11352. 80049a2: 687b ldr r3, [r7, #4]
  11353. 80049a4: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
  11354. 80049a8: 495c ldr r1, [pc, #368] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11355. 80049aa: 4313 orrs r3, r2
  11356. 80049ac: 658b str r3, [r1, #88] ; 0x58
  11357. 80049ae: e001 b.n 80049b4 <HAL_RCCEx_PeriphCLKConfig+0xadc>
  11358. }
  11359. else
  11360. {
  11361. /* set overall return value */
  11362. status = ret;
  11363. 80049b0: 7dfb ldrb r3, [r7, #23]
  11364. 80049b2: 75bb strb r3, [r7, #22]
  11365. }
  11366. }
  11367. /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/
  11368. #if defined(I2C5)
  11369. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235)
  11370. 80049b4: 687b ldr r3, [r7, #4]
  11371. 80049b6: 681b ldr r3, [r3, #0]
  11372. 80049b8: f003 0308 and.w r3, r3, #8
  11373. 80049bc: 2b00 cmp r3, #0
  11374. 80049be: d018 beq.n 80049f2 <HAL_RCCEx_PeriphCLKConfig+0xb1a>
  11375. {
  11376. /* Check the parameters */
  11377. assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection));
  11378. if ((PeriphClkInit->I2c1235ClockSelection )== RCC_I2C1235CLKSOURCE_PLL3 )
  11379. 80049c0: 687b ldr r3, [r7, #4]
  11380. 80049c2: 6fdb ldr r3, [r3, #124] ; 0x7c
  11381. 80049c4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  11382. 80049c8: d10a bne.n 80049e0 <HAL_RCCEx_PeriphCLKConfig+0xb08>
  11383. {
  11384. if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
  11385. 80049ca: 687b ldr r3, [r7, #4]
  11386. 80049cc: 3324 adds r3, #36 ; 0x24
  11387. 80049ce: 2102 movs r1, #2
  11388. 80049d0: 4618 mov r0, r3
  11389. 80049d2: f000 fa2d bl 8004e30 <RCCEx_PLL3_Config>
  11390. 80049d6: 4603 mov r3, r0
  11391. 80049d8: 2b00 cmp r3, #0
  11392. 80049da: d001 beq.n 80049e0 <HAL_RCCEx_PeriphCLKConfig+0xb08>
  11393. {
  11394. status = HAL_ERROR;
  11395. 80049dc: 2301 movs r3, #1
  11396. 80049de: 75bb strb r3, [r7, #22]
  11397. }
  11398. }
  11399. __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection);
  11400. 80049e0: 4b4e ldr r3, [pc, #312] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11401. 80049e2: 6d5b ldr r3, [r3, #84] ; 0x54
  11402. 80049e4: f423 5240 bic.w r2, r3, #12288 ; 0x3000
  11403. 80049e8: 687b ldr r3, [r7, #4]
  11404. 80049ea: 6fdb ldr r3, [r3, #124] ; 0x7c
  11405. 80049ec: 494b ldr r1, [pc, #300] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11406. 80049ee: 4313 orrs r3, r2
  11407. 80049f0: 654b str r3, [r1, #84] ; 0x54
  11408. }
  11409. #endif /* I2C5 */
  11410. /*------------------------------ I2C4 Configuration ------------------------*/
  11411. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
  11412. 80049f2: 687b ldr r3, [r7, #4]
  11413. 80049f4: 681b ldr r3, [r3, #0]
  11414. 80049f6: f003 0310 and.w r3, r3, #16
  11415. 80049fa: 2b00 cmp r3, #0
  11416. 80049fc: d01a beq.n 8004a34 <HAL_RCCEx_PeriphCLKConfig+0xb5c>
  11417. {
  11418. /* Check the parameters */
  11419. assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
  11420. if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 )
  11421. 80049fe: 687b ldr r3, [r7, #4]
  11422. 8004a00: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
  11423. 8004a04: f5b3 7f80 cmp.w r3, #256 ; 0x100
  11424. 8004a08: d10a bne.n 8004a20 <HAL_RCCEx_PeriphCLKConfig+0xb48>
  11425. {
  11426. if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
  11427. 8004a0a: 687b ldr r3, [r7, #4]
  11428. 8004a0c: 3324 adds r3, #36 ; 0x24
  11429. 8004a0e: 2102 movs r1, #2
  11430. 8004a10: 4618 mov r0, r3
  11431. 8004a12: f000 fa0d bl 8004e30 <RCCEx_PLL3_Config>
  11432. 8004a16: 4603 mov r3, r0
  11433. 8004a18: 2b00 cmp r3, #0
  11434. 8004a1a: d001 beq.n 8004a20 <HAL_RCCEx_PeriphCLKConfig+0xb48>
  11435. {
  11436. status = HAL_ERROR;
  11437. 8004a1c: 2301 movs r3, #1
  11438. 8004a1e: 75bb strb r3, [r7, #22]
  11439. }
  11440. }
  11441. __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
  11442. 8004a20: 4b3e ldr r3, [pc, #248] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11443. 8004a22: 6d9b ldr r3, [r3, #88] ; 0x58
  11444. 8004a24: f423 7240 bic.w r2, r3, #768 ; 0x300
  11445. 8004a28: 687b ldr r3, [r7, #4]
  11446. 8004a2a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
  11447. 8004a2e: 493b ldr r1, [pc, #236] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11448. 8004a30: 4313 orrs r3, r2
  11449. 8004a32: 658b str r3, [r1, #88] ; 0x58
  11450. }
  11451. /*---------------------------- ADC configuration -------------------------------*/
  11452. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
  11453. 8004a34: 687b ldr r3, [r7, #4]
  11454. 8004a36: 681b ldr r3, [r3, #0]
  11455. 8004a38: f403 2300 and.w r3, r3, #524288 ; 0x80000
  11456. 8004a3c: 2b00 cmp r3, #0
  11457. 8004a3e: d034 beq.n 8004aaa <HAL_RCCEx_PeriphCLKConfig+0xbd2>
  11458. {
  11459. switch(PeriphClkInit->AdcClockSelection)
  11460. 8004a40: 687b ldr r3, [r7, #4]
  11461. 8004a42: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c
  11462. 8004a46: f5b3 3f00 cmp.w r3, #131072 ; 0x20000
  11463. 8004a4a: d01d beq.n 8004a88 <HAL_RCCEx_PeriphCLKConfig+0xbb0>
  11464. 8004a4c: f5b3 3f00 cmp.w r3, #131072 ; 0x20000
  11465. 8004a50: d817 bhi.n 8004a82 <HAL_RCCEx_PeriphCLKConfig+0xbaa>
  11466. 8004a52: 2b00 cmp r3, #0
  11467. 8004a54: d003 beq.n 8004a5e <HAL_RCCEx_PeriphCLKConfig+0xb86>
  11468. 8004a56: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
  11469. 8004a5a: d009 beq.n 8004a70 <HAL_RCCEx_PeriphCLKConfig+0xb98>
  11470. 8004a5c: e011 b.n 8004a82 <HAL_RCCEx_PeriphCLKConfig+0xbaa>
  11471. {
  11472. case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
  11473. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
  11474. 8004a5e: 687b ldr r3, [r7, #4]
  11475. 8004a60: 3304 adds r3, #4
  11476. 8004a62: 2100 movs r1, #0
  11477. 8004a64: 4618 mov r0, r3
  11478. 8004a66: f000 f931 bl 8004ccc <RCCEx_PLL2_Config>
  11479. 8004a6a: 4603 mov r3, r0
  11480. 8004a6c: 75fb strb r3, [r7, #23]
  11481. /* ADC clock source configuration done later after clock selection check */
  11482. break;
  11483. 8004a6e: e00c b.n 8004a8a <HAL_RCCEx_PeriphCLKConfig+0xbb2>
  11484. case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/
  11485. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
  11486. 8004a70: 687b ldr r3, [r7, #4]
  11487. 8004a72: 3324 adds r3, #36 ; 0x24
  11488. 8004a74: 2102 movs r1, #2
  11489. 8004a76: 4618 mov r0, r3
  11490. 8004a78: f000 f9da bl 8004e30 <RCCEx_PLL3_Config>
  11491. 8004a7c: 4603 mov r3, r0
  11492. 8004a7e: 75fb strb r3, [r7, #23]
  11493. /* ADC clock source configuration done later after clock selection check */
  11494. break;
  11495. 8004a80: e003 b.n 8004a8a <HAL_RCCEx_PeriphCLKConfig+0xbb2>
  11496. /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
  11497. /* ADC clock source configuration done later after clock selection check */
  11498. break;
  11499. default:
  11500. ret = HAL_ERROR;
  11501. 8004a82: 2301 movs r3, #1
  11502. 8004a84: 75fb strb r3, [r7, #23]
  11503. break;
  11504. 8004a86: e000 b.n 8004a8a <HAL_RCCEx_PeriphCLKConfig+0xbb2>
  11505. break;
  11506. 8004a88: bf00 nop
  11507. }
  11508. if(ret == HAL_OK)
  11509. 8004a8a: 7dfb ldrb r3, [r7, #23]
  11510. 8004a8c: 2b00 cmp r3, #0
  11511. 8004a8e: d10a bne.n 8004aa6 <HAL_RCCEx_PeriphCLKConfig+0xbce>
  11512. {
  11513. /* Set the source of ADC clock*/
  11514. __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
  11515. 8004a90: 4b22 ldr r3, [pc, #136] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11516. 8004a92: 6d9b ldr r3, [r3, #88] ; 0x58
  11517. 8004a94: f423 3240 bic.w r2, r3, #196608 ; 0x30000
  11518. 8004a98: 687b ldr r3, [r7, #4]
  11519. 8004a9a: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c
  11520. 8004a9e: 491f ldr r1, [pc, #124] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11521. 8004aa0: 4313 orrs r3, r2
  11522. 8004aa2: 658b str r3, [r1, #88] ; 0x58
  11523. 8004aa4: e001 b.n 8004aaa <HAL_RCCEx_PeriphCLKConfig+0xbd2>
  11524. }
  11525. else
  11526. {
  11527. /* set overall return value */
  11528. status = ret;
  11529. 8004aa6: 7dfb ldrb r3, [r7, #23]
  11530. 8004aa8: 75bb strb r3, [r7, #22]
  11531. }
  11532. }
  11533. /*------------------------------ USB Configuration -------------------------*/
  11534. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
  11535. 8004aaa: 687b ldr r3, [r7, #4]
  11536. 8004aac: 681b ldr r3, [r3, #0]
  11537. 8004aae: f403 2380 and.w r3, r3, #262144 ; 0x40000
  11538. 8004ab2: 2b00 cmp r3, #0
  11539. 8004ab4: d036 beq.n 8004b24 <HAL_RCCEx_PeriphCLKConfig+0xc4c>
  11540. {
  11541. switch(PeriphClkInit->UsbClockSelection)
  11542. 8004ab6: 687b ldr r3, [r7, #4]
  11543. 8004ab8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
  11544. 8004abc: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000
  11545. 8004ac0: d01c beq.n 8004afc <HAL_RCCEx_PeriphCLKConfig+0xc24>
  11546. 8004ac2: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000
  11547. 8004ac6: d816 bhi.n 8004af6 <HAL_RCCEx_PeriphCLKConfig+0xc1e>
  11548. 8004ac8: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
  11549. 8004acc: d003 beq.n 8004ad6 <HAL_RCCEx_PeriphCLKConfig+0xbfe>
  11550. 8004ace: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000
  11551. 8004ad2: d007 beq.n 8004ae4 <HAL_RCCEx_PeriphCLKConfig+0xc0c>
  11552. 8004ad4: e00f b.n 8004af6 <HAL_RCCEx_PeriphCLKConfig+0xc1e>
  11553. {
  11554. case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/
  11555. /* Enable USB Clock output generated form System USB . */
  11556. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  11557. 8004ad6: 4b11 ldr r3, [pc, #68] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11558. 8004ad8: 6adb ldr r3, [r3, #44] ; 0x2c
  11559. 8004ada: 4a10 ldr r2, [pc, #64] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11560. 8004adc: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  11561. 8004ae0: 62d3 str r3, [r2, #44] ; 0x2c
  11562. /* USB clock source configuration done later after clock selection check */
  11563. break;
  11564. 8004ae2: e00c b.n 8004afe <HAL_RCCEx_PeriphCLKConfig+0xc26>
  11565. case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
  11566. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
  11567. 8004ae4: 687b ldr r3, [r7, #4]
  11568. 8004ae6: 3324 adds r3, #36 ; 0x24
  11569. 8004ae8: 2101 movs r1, #1
  11570. 8004aea: 4618 mov r0, r3
  11571. 8004aec: f000 f9a0 bl 8004e30 <RCCEx_PLL3_Config>
  11572. 8004af0: 4603 mov r3, r0
  11573. 8004af2: 75fb strb r3, [r7, #23]
  11574. /* USB clock source configuration done later after clock selection check */
  11575. break;
  11576. 8004af4: e003 b.n 8004afe <HAL_RCCEx_PeriphCLKConfig+0xc26>
  11577. /* HSI48 oscillator is used as source of USB clock */
  11578. /* USB clock source configuration done later after clock selection check */
  11579. break;
  11580. default:
  11581. ret = HAL_ERROR;
  11582. 8004af6: 2301 movs r3, #1
  11583. 8004af8: 75fb strb r3, [r7, #23]
  11584. break;
  11585. 8004afa: e000 b.n 8004afe <HAL_RCCEx_PeriphCLKConfig+0xc26>
  11586. break;
  11587. 8004afc: bf00 nop
  11588. }
  11589. if(ret == HAL_OK)
  11590. 8004afe: 7dfb ldrb r3, [r7, #23]
  11591. 8004b00: 2b00 cmp r3, #0
  11592. 8004b02: d10d bne.n 8004b20 <HAL_RCCEx_PeriphCLKConfig+0xc48>
  11593. {
  11594. /* Set the source of USB clock*/
  11595. __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
  11596. 8004b04: 4b05 ldr r3, [pc, #20] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11597. 8004b06: 6d5b ldr r3, [r3, #84] ; 0x54
  11598. 8004b08: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
  11599. 8004b0c: 687b ldr r3, [r7, #4]
  11600. 8004b0e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
  11601. 8004b12: 4902 ldr r1, [pc, #8] ; (8004b1c <HAL_RCCEx_PeriphCLKConfig+0xc44>)
  11602. 8004b14: 4313 orrs r3, r2
  11603. 8004b16: 654b str r3, [r1, #84] ; 0x54
  11604. 8004b18: e004 b.n 8004b24 <HAL_RCCEx_PeriphCLKConfig+0xc4c>
  11605. 8004b1a: bf00 nop
  11606. 8004b1c: 58024400 .word 0x58024400
  11607. }
  11608. else
  11609. {
  11610. /* set overall return value */
  11611. status = ret;
  11612. 8004b20: 7dfb ldrb r3, [r7, #23]
  11613. 8004b22: 75bb strb r3, [r7, #22]
  11614. }
  11615. }
  11616. /*------------------------------------- SDMMC Configuration ------------------------------------*/
  11617. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
  11618. 8004b24: 687b ldr r3, [r7, #4]
  11619. 8004b26: 681b ldr r3, [r3, #0]
  11620. 8004b28: f403 3380 and.w r3, r3, #65536 ; 0x10000
  11621. 8004b2c: 2b00 cmp r3, #0
  11622. 8004b2e: d029 beq.n 8004b84 <HAL_RCCEx_PeriphCLKConfig+0xcac>
  11623. {
  11624. /* Check the parameters */
  11625. assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
  11626. switch(PeriphClkInit->SdmmcClockSelection)
  11627. 8004b30: 687b ldr r3, [r7, #4]
  11628. 8004b32: 6cdb ldr r3, [r3, #76] ; 0x4c
  11629. 8004b34: 2b00 cmp r3, #0
  11630. 8004b36: d003 beq.n 8004b40 <HAL_RCCEx_PeriphCLKConfig+0xc68>
  11631. 8004b38: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
  11632. 8004b3c: d007 beq.n 8004b4e <HAL_RCCEx_PeriphCLKConfig+0xc76>
  11633. 8004b3e: e00f b.n 8004b60 <HAL_RCCEx_PeriphCLKConfig+0xc88>
  11634. {
  11635. case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/
  11636. /* Enable SDMMC Clock output generated form System PLL . */
  11637. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  11638. 8004b40: 4b61 ldr r3, [pc, #388] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11639. 8004b42: 6adb ldr r3, [r3, #44] ; 0x2c
  11640. 8004b44: 4a60 ldr r2, [pc, #384] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11641. 8004b46: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  11642. 8004b4a: 62d3 str r3, [r2, #44] ; 0x2c
  11643. /* SDMMC clock source configuration done later after clock selection check */
  11644. break;
  11645. 8004b4c: e00b b.n 8004b66 <HAL_RCCEx_PeriphCLKConfig+0xc8e>
  11646. case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
  11647. ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
  11648. 8004b4e: 687b ldr r3, [r7, #4]
  11649. 8004b50: 3304 adds r3, #4
  11650. 8004b52: 2102 movs r1, #2
  11651. 8004b54: 4618 mov r0, r3
  11652. 8004b56: f000 f8b9 bl 8004ccc <RCCEx_PLL2_Config>
  11653. 8004b5a: 4603 mov r3, r0
  11654. 8004b5c: 75fb strb r3, [r7, #23]
  11655. /* SDMMC clock source configuration done later after clock selection check */
  11656. break;
  11657. 8004b5e: e002 b.n 8004b66 <HAL_RCCEx_PeriphCLKConfig+0xc8e>
  11658. default:
  11659. ret = HAL_ERROR;
  11660. 8004b60: 2301 movs r3, #1
  11661. 8004b62: 75fb strb r3, [r7, #23]
  11662. break;
  11663. 8004b64: bf00 nop
  11664. }
  11665. if(ret == HAL_OK)
  11666. 8004b66: 7dfb ldrb r3, [r7, #23]
  11667. 8004b68: 2b00 cmp r3, #0
  11668. 8004b6a: d109 bne.n 8004b80 <HAL_RCCEx_PeriphCLKConfig+0xca8>
  11669. {
  11670. /* Set the source of SDMMC clock*/
  11671. __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
  11672. 8004b6c: 4b56 ldr r3, [pc, #344] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11673. 8004b6e: 6cdb ldr r3, [r3, #76] ; 0x4c
  11674. 8004b70: f423 3280 bic.w r2, r3, #65536 ; 0x10000
  11675. 8004b74: 687b ldr r3, [r7, #4]
  11676. 8004b76: 6cdb ldr r3, [r3, #76] ; 0x4c
  11677. 8004b78: 4953 ldr r1, [pc, #332] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11678. 8004b7a: 4313 orrs r3, r2
  11679. 8004b7c: 64cb str r3, [r1, #76] ; 0x4c
  11680. 8004b7e: e001 b.n 8004b84 <HAL_RCCEx_PeriphCLKConfig+0xcac>
  11681. }
  11682. else
  11683. {
  11684. /* set overall return value */
  11685. status = ret;
  11686. 8004b80: 7dfb ldrb r3, [r7, #23]
  11687. 8004b82: 75bb strb r3, [r7, #22]
  11688. }
  11689. }
  11690. #if defined(LTDC)
  11691. /*-------------------------------------- LTDC Configuration -----------------------------------*/
  11692. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
  11693. 8004b84: 687b ldr r3, [r7, #4]
  11694. 8004b86: 681b ldr r3, [r3, #0]
  11695. 8004b88: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
  11696. 8004b8c: 2b00 cmp r3, #0
  11697. 8004b8e: d00a beq.n 8004ba6 <HAL_RCCEx_PeriphCLKConfig+0xcce>
  11698. {
  11699. if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK)
  11700. 8004b90: 687b ldr r3, [r7, #4]
  11701. 8004b92: 3324 adds r3, #36 ; 0x24
  11702. 8004b94: 2102 movs r1, #2
  11703. 8004b96: 4618 mov r0, r3
  11704. 8004b98: f000 f94a bl 8004e30 <RCCEx_PLL3_Config>
  11705. 8004b9c: 4603 mov r3, r0
  11706. 8004b9e: 2b00 cmp r3, #0
  11707. 8004ba0: d001 beq.n 8004ba6 <HAL_RCCEx_PeriphCLKConfig+0xcce>
  11708. {
  11709. status=HAL_ERROR;
  11710. 8004ba2: 2301 movs r3, #1
  11711. 8004ba4: 75bb strb r3, [r7, #22]
  11712. }
  11713. }
  11714. #endif /* LTDC */
  11715. /*------------------------------ RNG Configuration -------------------------*/
  11716. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
  11717. 8004ba6: 687b ldr r3, [r7, #4]
  11718. 8004ba8: 681b ldr r3, [r3, #0]
  11719. 8004baa: f403 3300 and.w r3, r3, #131072 ; 0x20000
  11720. 8004bae: 2b00 cmp r3, #0
  11721. 8004bb0: d030 beq.n 8004c14 <HAL_RCCEx_PeriphCLKConfig+0xd3c>
  11722. {
  11723. switch(PeriphClkInit->RngClockSelection)
  11724. 8004bb2: 687b ldr r3, [r7, #4]
  11725. 8004bb4: 6f9b ldr r3, [r3, #120] ; 0x78
  11726. 8004bb6: f5b3 7f40 cmp.w r3, #768 ; 0x300
  11727. 8004bba: d017 beq.n 8004bec <HAL_RCCEx_PeriphCLKConfig+0xd14>
  11728. 8004bbc: f5b3 7f40 cmp.w r3, #768 ; 0x300
  11729. 8004bc0: d811 bhi.n 8004be6 <HAL_RCCEx_PeriphCLKConfig+0xd0e>
  11730. 8004bc2: f5b3 7f00 cmp.w r3, #512 ; 0x200
  11731. 8004bc6: d013 beq.n 8004bf0 <HAL_RCCEx_PeriphCLKConfig+0xd18>
  11732. 8004bc8: f5b3 7f00 cmp.w r3, #512 ; 0x200
  11733. 8004bcc: d80b bhi.n 8004be6 <HAL_RCCEx_PeriphCLKConfig+0xd0e>
  11734. 8004bce: 2b00 cmp r3, #0
  11735. 8004bd0: d010 beq.n 8004bf4 <HAL_RCCEx_PeriphCLKConfig+0xd1c>
  11736. 8004bd2: f5b3 7f80 cmp.w r3, #256 ; 0x100
  11737. 8004bd6: d106 bne.n 8004be6 <HAL_RCCEx_PeriphCLKConfig+0xd0e>
  11738. {
  11739. case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/
  11740. /* Enable RNG Clock output generated form System RNG . */
  11741. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  11742. 8004bd8: 4b3b ldr r3, [pc, #236] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11743. 8004bda: 6adb ldr r3, [r3, #44] ; 0x2c
  11744. 8004bdc: 4a3a ldr r2, [pc, #232] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11745. 8004bde: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  11746. 8004be2: 62d3 str r3, [r2, #44] ; 0x2c
  11747. /* RNG clock source configuration done later after clock selection check */
  11748. break;
  11749. 8004be4: e007 b.n 8004bf6 <HAL_RCCEx_PeriphCLKConfig+0xd1e>
  11750. /* HSI48 oscillator is used as source of RNG clock */
  11751. /* RNG clock source configuration done later after clock selection check */
  11752. break;
  11753. default:
  11754. ret = HAL_ERROR;
  11755. 8004be6: 2301 movs r3, #1
  11756. 8004be8: 75fb strb r3, [r7, #23]
  11757. break;
  11758. 8004bea: e004 b.n 8004bf6 <HAL_RCCEx_PeriphCLKConfig+0xd1e>
  11759. break;
  11760. 8004bec: bf00 nop
  11761. 8004bee: e002 b.n 8004bf6 <HAL_RCCEx_PeriphCLKConfig+0xd1e>
  11762. break;
  11763. 8004bf0: bf00 nop
  11764. 8004bf2: e000 b.n 8004bf6 <HAL_RCCEx_PeriphCLKConfig+0xd1e>
  11765. break;
  11766. 8004bf4: bf00 nop
  11767. }
  11768. if(ret == HAL_OK)
  11769. 8004bf6: 7dfb ldrb r3, [r7, #23]
  11770. 8004bf8: 2b00 cmp r3, #0
  11771. 8004bfa: d109 bne.n 8004c10 <HAL_RCCEx_PeriphCLKConfig+0xd38>
  11772. {
  11773. /* Set the source of RNG clock*/
  11774. __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
  11775. 8004bfc: 4b32 ldr r3, [pc, #200] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11776. 8004bfe: 6d5b ldr r3, [r3, #84] ; 0x54
  11777. 8004c00: f423 7240 bic.w r2, r3, #768 ; 0x300
  11778. 8004c04: 687b ldr r3, [r7, #4]
  11779. 8004c06: 6f9b ldr r3, [r3, #120] ; 0x78
  11780. 8004c08: 492f ldr r1, [pc, #188] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11781. 8004c0a: 4313 orrs r3, r2
  11782. 8004c0c: 654b str r3, [r1, #84] ; 0x54
  11783. 8004c0e: e001 b.n 8004c14 <HAL_RCCEx_PeriphCLKConfig+0xd3c>
  11784. }
  11785. else
  11786. {
  11787. /* set overall return value */
  11788. status = ret;
  11789. 8004c10: 7dfb ldrb r3, [r7, #23]
  11790. 8004c12: 75bb strb r3, [r7, #22]
  11791. }
  11792. }
  11793. /*------------------------------ SWPMI1 Configuration ------------------------*/
  11794. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
  11795. 8004c14: 687b ldr r3, [r7, #4]
  11796. 8004c16: 681b ldr r3, [r3, #0]
  11797. 8004c18: f403 1380 and.w r3, r3, #1048576 ; 0x100000
  11798. 8004c1c: 2b00 cmp r3, #0
  11799. 8004c1e: d008 beq.n 8004c32 <HAL_RCCEx_PeriphCLKConfig+0xd5a>
  11800. {
  11801. /* Check the parameters */
  11802. assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
  11803. /* Configure the SWPMI1 interface clock source */
  11804. __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
  11805. 8004c20: 4b29 ldr r3, [pc, #164] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11806. 8004c22: 6d1b ldr r3, [r3, #80] ; 0x50
  11807. 8004c24: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000
  11808. 8004c28: 687b ldr r3, [r7, #4]
  11809. 8004c2a: 6edb ldr r3, [r3, #108] ; 0x6c
  11810. 8004c2c: 4926 ldr r1, [pc, #152] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11811. 8004c2e: 4313 orrs r3, r2
  11812. 8004c30: 650b str r3, [r1, #80] ; 0x50
  11813. /* Configure the HRTIM1 clock source */
  11814. __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
  11815. }
  11816. #endif /*HRTIM1*/
  11817. /*------------------------------ DFSDM1 Configuration ------------------------*/
  11818. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
  11819. 8004c32: 687b ldr r3, [r7, #4]
  11820. 8004c34: 681b ldr r3, [r3, #0]
  11821. 8004c36: f403 1300 and.w r3, r3, #2097152 ; 0x200000
  11822. 8004c3a: 2b00 cmp r3, #0
  11823. 8004c3c: d008 beq.n 8004c50 <HAL_RCCEx_PeriphCLKConfig+0xd78>
  11824. {
  11825. /* Check the parameters */
  11826. assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
  11827. /* Configure the DFSDM1 interface clock source */
  11828. __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
  11829. 8004c3e: 4b22 ldr r3, [pc, #136] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11830. 8004c40: 6d1b ldr r3, [r3, #80] ; 0x50
  11831. 8004c42: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000
  11832. 8004c46: 687b ldr r3, [r7, #4]
  11833. 8004c48: 6e5b ldr r3, [r3, #100] ; 0x64
  11834. 8004c4a: 491f ldr r1, [pc, #124] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11835. 8004c4c: 4313 orrs r3, r2
  11836. 8004c4e: 650b str r3, [r1, #80] ; 0x50
  11837. __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
  11838. }
  11839. #endif /* DFSDM2 */
  11840. /*------------------------------------ TIM configuration --------------------------------------*/
  11841. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
  11842. 8004c50: 687b ldr r3, [r7, #4]
  11843. 8004c52: 681b ldr r3, [r3, #0]
  11844. 8004c54: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000
  11845. 8004c58: 2b00 cmp r3, #0
  11846. 8004c5a: d00d beq.n 8004c78 <HAL_RCCEx_PeriphCLKConfig+0xda0>
  11847. {
  11848. /* Check the parameters */
  11849. assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
  11850. /* Configure Timer Prescaler */
  11851. __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
  11852. 8004c5c: 4b1a ldr r3, [pc, #104] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11853. 8004c5e: 691b ldr r3, [r3, #16]
  11854. 8004c60: 4a19 ldr r2, [pc, #100] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11855. 8004c62: f423 4300 bic.w r3, r3, #32768 ; 0x8000
  11856. 8004c66: 6113 str r3, [r2, #16]
  11857. 8004c68: 4b17 ldr r3, [pc, #92] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11858. 8004c6a: 691a ldr r2, [r3, #16]
  11859. 8004c6c: 687b ldr r3, [r7, #4]
  11860. 8004c6e: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0
  11861. 8004c72: 4915 ldr r1, [pc, #84] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11862. 8004c74: 4313 orrs r3, r2
  11863. 8004c76: 610b str r3, [r1, #16]
  11864. }
  11865. /*------------------------------------ CKPER configuration --------------------------------------*/
  11866. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
  11867. 8004c78: 687b ldr r3, [r7, #4]
  11868. 8004c7a: 681b ldr r3, [r3, #0]
  11869. 8004c7c: 2b00 cmp r3, #0
  11870. 8004c7e: da08 bge.n 8004c92 <HAL_RCCEx_PeriphCLKConfig+0xdba>
  11871. {
  11872. /* Check the parameters */
  11873. assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
  11874. /* Configure the CKPER clock source */
  11875. __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
  11876. 8004c80: 4b11 ldr r3, [pc, #68] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11877. 8004c82: 6cdb ldr r3, [r3, #76] ; 0x4c
  11878. 8004c84: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000
  11879. 8004c88: 687b ldr r3, [r7, #4]
  11880. 8004c8a: 6d1b ldr r3, [r3, #80] ; 0x50
  11881. 8004c8c: 490e ldr r1, [pc, #56] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11882. 8004c8e: 4313 orrs r3, r2
  11883. 8004c90: 64cb str r3, [r1, #76] ; 0x4c
  11884. }
  11885. /*------------------------------ CEC Configuration ------------------------*/
  11886. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
  11887. 8004c92: 687b ldr r3, [r7, #4]
  11888. 8004c94: 681b ldr r3, [r3, #0]
  11889. 8004c96: f403 0300 and.w r3, r3, #8388608 ; 0x800000
  11890. 8004c9a: 2b00 cmp r3, #0
  11891. 8004c9c: d009 beq.n 8004cb2 <HAL_RCCEx_PeriphCLKConfig+0xdda>
  11892. {
  11893. /* Check the parameters */
  11894. assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
  11895. /* Configure the CEC interface clock source */
  11896. __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
  11897. 8004c9e: 4b0a ldr r3, [pc, #40] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11898. 8004ca0: 6d5b ldr r3, [r3, #84] ; 0x54
  11899. 8004ca2: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
  11900. 8004ca6: 687b ldr r3, [r7, #4]
  11901. 8004ca8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
  11902. 8004cac: 4906 ldr r1, [pc, #24] ; (8004cc8 <HAL_RCCEx_PeriphCLKConfig+0xdf0>)
  11903. 8004cae: 4313 orrs r3, r2
  11904. 8004cb0: 654b str r3, [r1, #84] ; 0x54
  11905. }
  11906. if (status == HAL_OK)
  11907. 8004cb2: 7dbb ldrb r3, [r7, #22]
  11908. 8004cb4: 2b00 cmp r3, #0
  11909. 8004cb6: d101 bne.n 8004cbc <HAL_RCCEx_PeriphCLKConfig+0xde4>
  11910. {
  11911. return HAL_OK;
  11912. 8004cb8: 2300 movs r3, #0
  11913. 8004cba: e000 b.n 8004cbe <HAL_RCCEx_PeriphCLKConfig+0xde6>
  11914. }
  11915. return HAL_ERROR;
  11916. 8004cbc: 2301 movs r3, #1
  11917. }
  11918. 8004cbe: 4618 mov r0, r3
  11919. 8004cc0: 3718 adds r7, #24
  11920. 8004cc2: 46bd mov sp, r7
  11921. 8004cc4: bd80 pop {r7, pc}
  11922. 8004cc6: bf00 nop
  11923. 8004cc8: 58024400 .word 0x58024400
  11924. 08004ccc <RCCEx_PLL2_Config>:
  11925. * @note PLL2 is temporary disabled to apply new parameters
  11926. *
  11927. * @retval HAL status
  11928. */
  11929. static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
  11930. {
  11931. 8004ccc: b580 push {r7, lr}
  11932. 8004cce: b084 sub sp, #16
  11933. 8004cd0: af00 add r7, sp, #0
  11934. 8004cd2: 6078 str r0, [r7, #4]
  11935. 8004cd4: 6039 str r1, [r7, #0]
  11936. uint32_t tickstart;
  11937. HAL_StatusTypeDef status = HAL_OK;
  11938. 8004cd6: 2300 movs r3, #0
  11939. 8004cd8: 73fb strb r3, [r7, #15]
  11940. assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
  11941. assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
  11942. assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
  11943. /* Check that PLL2 OSC clock source is already set */
  11944. if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  11945. 8004cda: 4b53 ldr r3, [pc, #332] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  11946. 8004cdc: 6a9b ldr r3, [r3, #40] ; 0x28
  11947. 8004cde: f003 0303 and.w r3, r3, #3
  11948. 8004ce2: 2b03 cmp r3, #3
  11949. 8004ce4: d101 bne.n 8004cea <RCCEx_PLL2_Config+0x1e>
  11950. {
  11951. return HAL_ERROR;
  11952. 8004ce6: 2301 movs r3, #1
  11953. 8004ce8: e099 b.n 8004e1e <RCCEx_PLL2_Config+0x152>
  11954. else
  11955. {
  11956. /* Disable PLL2. */
  11957. __HAL_RCC_PLL2_DISABLE();
  11958. 8004cea: 4b4f ldr r3, [pc, #316] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  11959. 8004cec: 681b ldr r3, [r3, #0]
  11960. 8004cee: 4a4e ldr r2, [pc, #312] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  11961. 8004cf0: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
  11962. 8004cf4: 6013 str r3, [r2, #0]
  11963. /* Get Start Tick*/
  11964. tickstart = HAL_GetTick();
  11965. 8004cf6: f7fc fcaf bl 8001658 <HAL_GetTick>
  11966. 8004cfa: 60b8 str r0, [r7, #8]
  11967. /* Wait till PLL is disabled */
  11968. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
  11969. 8004cfc: e008 b.n 8004d10 <RCCEx_PLL2_Config+0x44>
  11970. {
  11971. if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
  11972. 8004cfe: f7fc fcab bl 8001658 <HAL_GetTick>
  11973. 8004d02: 4602 mov r2, r0
  11974. 8004d04: 68bb ldr r3, [r7, #8]
  11975. 8004d06: 1ad3 subs r3, r2, r3
  11976. 8004d08: 2b02 cmp r3, #2
  11977. 8004d0a: d901 bls.n 8004d10 <RCCEx_PLL2_Config+0x44>
  11978. {
  11979. return HAL_TIMEOUT;
  11980. 8004d0c: 2303 movs r3, #3
  11981. 8004d0e: e086 b.n 8004e1e <RCCEx_PLL2_Config+0x152>
  11982. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
  11983. 8004d10: 4b45 ldr r3, [pc, #276] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  11984. 8004d12: 681b ldr r3, [r3, #0]
  11985. 8004d14: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
  11986. 8004d18: 2b00 cmp r3, #0
  11987. 8004d1a: d1f0 bne.n 8004cfe <RCCEx_PLL2_Config+0x32>
  11988. }
  11989. }
  11990. /* Configure PLL2 multiplication and division factors. */
  11991. __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
  11992. 8004d1c: 4b42 ldr r3, [pc, #264] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  11993. 8004d1e: 6a9b ldr r3, [r3, #40] ; 0x28
  11994. 8004d20: f423 327c bic.w r2, r3, #258048 ; 0x3f000
  11995. 8004d24: 687b ldr r3, [r7, #4]
  11996. 8004d26: 681b ldr r3, [r3, #0]
  11997. 8004d28: 031b lsls r3, r3, #12
  11998. 8004d2a: 493f ldr r1, [pc, #252] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  11999. 8004d2c: 4313 orrs r3, r2
  12000. 8004d2e: 628b str r3, [r1, #40] ; 0x28
  12001. 8004d30: 687b ldr r3, [r7, #4]
  12002. 8004d32: 685b ldr r3, [r3, #4]
  12003. 8004d34: 3b01 subs r3, #1
  12004. 8004d36: f3c3 0208 ubfx r2, r3, #0, #9
  12005. 8004d3a: 687b ldr r3, [r7, #4]
  12006. 8004d3c: 689b ldr r3, [r3, #8]
  12007. 8004d3e: 3b01 subs r3, #1
  12008. 8004d40: 025b lsls r3, r3, #9
  12009. 8004d42: b29b uxth r3, r3
  12010. 8004d44: 431a orrs r2, r3
  12011. 8004d46: 687b ldr r3, [r7, #4]
  12012. 8004d48: 68db ldr r3, [r3, #12]
  12013. 8004d4a: 3b01 subs r3, #1
  12014. 8004d4c: 041b lsls r3, r3, #16
  12015. 8004d4e: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000
  12016. 8004d52: 431a orrs r2, r3
  12017. 8004d54: 687b ldr r3, [r7, #4]
  12018. 8004d56: 691b ldr r3, [r3, #16]
  12019. 8004d58: 3b01 subs r3, #1
  12020. 8004d5a: 061b lsls r3, r3, #24
  12021. 8004d5c: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000
  12022. 8004d60: 4931 ldr r1, [pc, #196] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12023. 8004d62: 4313 orrs r3, r2
  12024. 8004d64: 638b str r3, [r1, #56] ; 0x38
  12025. pll2->PLL2P,
  12026. pll2->PLL2Q,
  12027. pll2->PLL2R);
  12028. /* Select PLL2 input reference frequency range: VCI */
  12029. __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
  12030. 8004d66: 4b30 ldr r3, [pc, #192] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12031. 8004d68: 6adb ldr r3, [r3, #44] ; 0x2c
  12032. 8004d6a: f023 02c0 bic.w r2, r3, #192 ; 0xc0
  12033. 8004d6e: 687b ldr r3, [r7, #4]
  12034. 8004d70: 695b ldr r3, [r3, #20]
  12035. 8004d72: 492d ldr r1, [pc, #180] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12036. 8004d74: 4313 orrs r3, r2
  12037. 8004d76: 62cb str r3, [r1, #44] ; 0x2c
  12038. /* Select PLL2 output frequency range : VCO */
  12039. __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
  12040. 8004d78: 4b2b ldr r3, [pc, #172] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12041. 8004d7a: 6adb ldr r3, [r3, #44] ; 0x2c
  12042. 8004d7c: f023 0220 bic.w r2, r3, #32
  12043. 8004d80: 687b ldr r3, [r7, #4]
  12044. 8004d82: 699b ldr r3, [r3, #24]
  12045. 8004d84: 4928 ldr r1, [pc, #160] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12046. 8004d86: 4313 orrs r3, r2
  12047. 8004d88: 62cb str r3, [r1, #44] ; 0x2c
  12048. /* Disable PLL2FRACN . */
  12049. __HAL_RCC_PLL2FRACN_DISABLE();
  12050. 8004d8a: 4b27 ldr r3, [pc, #156] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12051. 8004d8c: 6adb ldr r3, [r3, #44] ; 0x2c
  12052. 8004d8e: 4a26 ldr r2, [pc, #152] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12053. 8004d90: f023 0310 bic.w r3, r3, #16
  12054. 8004d94: 62d3 str r3, [r2, #44] ; 0x2c
  12055. /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
  12056. __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
  12057. 8004d96: 4b24 ldr r3, [pc, #144] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12058. 8004d98: 6bda ldr r2, [r3, #60] ; 0x3c
  12059. 8004d9a: 4b24 ldr r3, [pc, #144] ; (8004e2c <RCCEx_PLL2_Config+0x160>)
  12060. 8004d9c: 4013 ands r3, r2
  12061. 8004d9e: 687a ldr r2, [r7, #4]
  12062. 8004da0: 69d2 ldr r2, [r2, #28]
  12063. 8004da2: 00d2 lsls r2, r2, #3
  12064. 8004da4: 4920 ldr r1, [pc, #128] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12065. 8004da6: 4313 orrs r3, r2
  12066. 8004da8: 63cb str r3, [r1, #60] ; 0x3c
  12067. /* Enable PLL2FRACN . */
  12068. __HAL_RCC_PLL2FRACN_ENABLE();
  12069. 8004daa: 4b1f ldr r3, [pc, #124] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12070. 8004dac: 6adb ldr r3, [r3, #44] ; 0x2c
  12071. 8004dae: 4a1e ldr r2, [pc, #120] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12072. 8004db0: f043 0310 orr.w r3, r3, #16
  12073. 8004db4: 62d3 str r3, [r2, #44] ; 0x2c
  12074. /* Enable the PLL2 clock output */
  12075. if(Divider == DIVIDER_P_UPDATE)
  12076. 8004db6: 683b ldr r3, [r7, #0]
  12077. 8004db8: 2b00 cmp r3, #0
  12078. 8004dba: d106 bne.n 8004dca <RCCEx_PLL2_Config+0xfe>
  12079. {
  12080. __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
  12081. 8004dbc: 4b1a ldr r3, [pc, #104] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12082. 8004dbe: 6adb ldr r3, [r3, #44] ; 0x2c
  12083. 8004dc0: 4a19 ldr r2, [pc, #100] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12084. 8004dc2: f443 2300 orr.w r3, r3, #524288 ; 0x80000
  12085. 8004dc6: 62d3 str r3, [r2, #44] ; 0x2c
  12086. 8004dc8: e00f b.n 8004dea <RCCEx_PLL2_Config+0x11e>
  12087. }
  12088. else if(Divider == DIVIDER_Q_UPDATE)
  12089. 8004dca: 683b ldr r3, [r7, #0]
  12090. 8004dcc: 2b01 cmp r3, #1
  12091. 8004dce: d106 bne.n 8004dde <RCCEx_PLL2_Config+0x112>
  12092. {
  12093. __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
  12094. 8004dd0: 4b15 ldr r3, [pc, #84] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12095. 8004dd2: 6adb ldr r3, [r3, #44] ; 0x2c
  12096. 8004dd4: 4a14 ldr r2, [pc, #80] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12097. 8004dd6: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
  12098. 8004dda: 62d3 str r3, [r2, #44] ; 0x2c
  12099. 8004ddc: e005 b.n 8004dea <RCCEx_PLL2_Config+0x11e>
  12100. }
  12101. else
  12102. {
  12103. __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
  12104. 8004dde: 4b12 ldr r3, [pc, #72] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12105. 8004de0: 6adb ldr r3, [r3, #44] ; 0x2c
  12106. 8004de2: 4a11 ldr r2, [pc, #68] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12107. 8004de4: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
  12108. 8004de8: 62d3 str r3, [r2, #44] ; 0x2c
  12109. }
  12110. /* Enable PLL2. */
  12111. __HAL_RCC_PLL2_ENABLE();
  12112. 8004dea: 4b0f ldr r3, [pc, #60] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12113. 8004dec: 681b ldr r3, [r3, #0]
  12114. 8004dee: 4a0e ldr r2, [pc, #56] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12115. 8004df0: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
  12116. 8004df4: 6013 str r3, [r2, #0]
  12117. /* Get Start Tick*/
  12118. tickstart = HAL_GetTick();
  12119. 8004df6: f7fc fc2f bl 8001658 <HAL_GetTick>
  12120. 8004dfa: 60b8 str r0, [r7, #8]
  12121. /* Wait till PLL2 is ready */
  12122. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
  12123. 8004dfc: e008 b.n 8004e10 <RCCEx_PLL2_Config+0x144>
  12124. {
  12125. if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
  12126. 8004dfe: f7fc fc2b bl 8001658 <HAL_GetTick>
  12127. 8004e02: 4602 mov r2, r0
  12128. 8004e04: 68bb ldr r3, [r7, #8]
  12129. 8004e06: 1ad3 subs r3, r2, r3
  12130. 8004e08: 2b02 cmp r3, #2
  12131. 8004e0a: d901 bls.n 8004e10 <RCCEx_PLL2_Config+0x144>
  12132. {
  12133. return HAL_TIMEOUT;
  12134. 8004e0c: 2303 movs r3, #3
  12135. 8004e0e: e006 b.n 8004e1e <RCCEx_PLL2_Config+0x152>
  12136. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
  12137. 8004e10: 4b05 ldr r3, [pc, #20] ; (8004e28 <RCCEx_PLL2_Config+0x15c>)
  12138. 8004e12: 681b ldr r3, [r3, #0]
  12139. 8004e14: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
  12140. 8004e18: 2b00 cmp r3, #0
  12141. 8004e1a: d0f0 beq.n 8004dfe <RCCEx_PLL2_Config+0x132>
  12142. }
  12143. }
  12144. return status;
  12145. 8004e1c: 7bfb ldrb r3, [r7, #15]
  12146. }
  12147. 8004e1e: 4618 mov r0, r3
  12148. 8004e20: 3710 adds r7, #16
  12149. 8004e22: 46bd mov sp, r7
  12150. 8004e24: bd80 pop {r7, pc}
  12151. 8004e26: bf00 nop
  12152. 8004e28: 58024400 .word 0x58024400
  12153. 8004e2c: ffff0007 .word 0xffff0007
  12154. 08004e30 <RCCEx_PLL3_Config>:
  12155. * @note PLL3 is temporary disabled to apply new parameters
  12156. *
  12157. * @retval HAL status
  12158. */
  12159. static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
  12160. {
  12161. 8004e30: b580 push {r7, lr}
  12162. 8004e32: b084 sub sp, #16
  12163. 8004e34: af00 add r7, sp, #0
  12164. 8004e36: 6078 str r0, [r7, #4]
  12165. 8004e38: 6039 str r1, [r7, #0]
  12166. uint32_t tickstart;
  12167. HAL_StatusTypeDef status = HAL_OK;
  12168. 8004e3a: 2300 movs r3, #0
  12169. 8004e3c: 73fb strb r3, [r7, #15]
  12170. assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
  12171. assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
  12172. assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
  12173. /* Check that PLL3 OSC clock source is already set */
  12174. if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  12175. 8004e3e: 4b53 ldr r3, [pc, #332] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12176. 8004e40: 6a9b ldr r3, [r3, #40] ; 0x28
  12177. 8004e42: f003 0303 and.w r3, r3, #3
  12178. 8004e46: 2b03 cmp r3, #3
  12179. 8004e48: d101 bne.n 8004e4e <RCCEx_PLL3_Config+0x1e>
  12180. {
  12181. return HAL_ERROR;
  12182. 8004e4a: 2301 movs r3, #1
  12183. 8004e4c: e099 b.n 8004f82 <RCCEx_PLL3_Config+0x152>
  12184. else
  12185. {
  12186. /* Disable PLL3. */
  12187. __HAL_RCC_PLL3_DISABLE();
  12188. 8004e4e: 4b4f ldr r3, [pc, #316] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12189. 8004e50: 681b ldr r3, [r3, #0]
  12190. 8004e52: 4a4e ldr r2, [pc, #312] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12191. 8004e54: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
  12192. 8004e58: 6013 str r3, [r2, #0]
  12193. /* Get Start Tick*/
  12194. tickstart = HAL_GetTick();
  12195. 8004e5a: f7fc fbfd bl 8001658 <HAL_GetTick>
  12196. 8004e5e: 60b8 str r0, [r7, #8]
  12197. /* Wait till PLL3 is ready */
  12198. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
  12199. 8004e60: e008 b.n 8004e74 <RCCEx_PLL3_Config+0x44>
  12200. {
  12201. if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
  12202. 8004e62: f7fc fbf9 bl 8001658 <HAL_GetTick>
  12203. 8004e66: 4602 mov r2, r0
  12204. 8004e68: 68bb ldr r3, [r7, #8]
  12205. 8004e6a: 1ad3 subs r3, r2, r3
  12206. 8004e6c: 2b02 cmp r3, #2
  12207. 8004e6e: d901 bls.n 8004e74 <RCCEx_PLL3_Config+0x44>
  12208. {
  12209. return HAL_TIMEOUT;
  12210. 8004e70: 2303 movs r3, #3
  12211. 8004e72: e086 b.n 8004f82 <RCCEx_PLL3_Config+0x152>
  12212. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
  12213. 8004e74: 4b45 ldr r3, [pc, #276] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12214. 8004e76: 681b ldr r3, [r3, #0]
  12215. 8004e78: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
  12216. 8004e7c: 2b00 cmp r3, #0
  12217. 8004e7e: d1f0 bne.n 8004e62 <RCCEx_PLL3_Config+0x32>
  12218. }
  12219. }
  12220. /* Configure the PLL3 multiplication and division factors. */
  12221. __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
  12222. 8004e80: 4b42 ldr r3, [pc, #264] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12223. 8004e82: 6a9b ldr r3, [r3, #40] ; 0x28
  12224. 8004e84: f023 727c bic.w r2, r3, #66060288 ; 0x3f00000
  12225. 8004e88: 687b ldr r3, [r7, #4]
  12226. 8004e8a: 681b ldr r3, [r3, #0]
  12227. 8004e8c: 051b lsls r3, r3, #20
  12228. 8004e8e: 493f ldr r1, [pc, #252] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12229. 8004e90: 4313 orrs r3, r2
  12230. 8004e92: 628b str r3, [r1, #40] ; 0x28
  12231. 8004e94: 687b ldr r3, [r7, #4]
  12232. 8004e96: 685b ldr r3, [r3, #4]
  12233. 8004e98: 3b01 subs r3, #1
  12234. 8004e9a: f3c3 0208 ubfx r2, r3, #0, #9
  12235. 8004e9e: 687b ldr r3, [r7, #4]
  12236. 8004ea0: 689b ldr r3, [r3, #8]
  12237. 8004ea2: 3b01 subs r3, #1
  12238. 8004ea4: 025b lsls r3, r3, #9
  12239. 8004ea6: b29b uxth r3, r3
  12240. 8004ea8: 431a orrs r2, r3
  12241. 8004eaa: 687b ldr r3, [r7, #4]
  12242. 8004eac: 68db ldr r3, [r3, #12]
  12243. 8004eae: 3b01 subs r3, #1
  12244. 8004eb0: 041b lsls r3, r3, #16
  12245. 8004eb2: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000
  12246. 8004eb6: 431a orrs r2, r3
  12247. 8004eb8: 687b ldr r3, [r7, #4]
  12248. 8004eba: 691b ldr r3, [r3, #16]
  12249. 8004ebc: 3b01 subs r3, #1
  12250. 8004ebe: 061b lsls r3, r3, #24
  12251. 8004ec0: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000
  12252. 8004ec4: 4931 ldr r1, [pc, #196] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12253. 8004ec6: 4313 orrs r3, r2
  12254. 8004ec8: 640b str r3, [r1, #64] ; 0x40
  12255. pll3->PLL3P,
  12256. pll3->PLL3Q,
  12257. pll3->PLL3R);
  12258. /* Select PLL3 input reference frequency range: VCI */
  12259. __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
  12260. 8004eca: 4b30 ldr r3, [pc, #192] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12261. 8004ecc: 6adb ldr r3, [r3, #44] ; 0x2c
  12262. 8004ece: f423 6240 bic.w r2, r3, #3072 ; 0xc00
  12263. 8004ed2: 687b ldr r3, [r7, #4]
  12264. 8004ed4: 695b ldr r3, [r3, #20]
  12265. 8004ed6: 492d ldr r1, [pc, #180] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12266. 8004ed8: 4313 orrs r3, r2
  12267. 8004eda: 62cb str r3, [r1, #44] ; 0x2c
  12268. /* Select PLL3 output frequency range : VCO */
  12269. __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
  12270. 8004edc: 4b2b ldr r3, [pc, #172] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12271. 8004ede: 6adb ldr r3, [r3, #44] ; 0x2c
  12272. 8004ee0: f423 7200 bic.w r2, r3, #512 ; 0x200
  12273. 8004ee4: 687b ldr r3, [r7, #4]
  12274. 8004ee6: 699b ldr r3, [r3, #24]
  12275. 8004ee8: 4928 ldr r1, [pc, #160] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12276. 8004eea: 4313 orrs r3, r2
  12277. 8004eec: 62cb str r3, [r1, #44] ; 0x2c
  12278. /* Disable PLL3FRACN . */
  12279. __HAL_RCC_PLL3FRACN_DISABLE();
  12280. 8004eee: 4b27 ldr r3, [pc, #156] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12281. 8004ef0: 6adb ldr r3, [r3, #44] ; 0x2c
  12282. 8004ef2: 4a26 ldr r2, [pc, #152] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12283. 8004ef4: f423 7380 bic.w r3, r3, #256 ; 0x100
  12284. 8004ef8: 62d3 str r3, [r2, #44] ; 0x2c
  12285. /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
  12286. __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
  12287. 8004efa: 4b24 ldr r3, [pc, #144] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12288. 8004efc: 6c5a ldr r2, [r3, #68] ; 0x44
  12289. 8004efe: 4b24 ldr r3, [pc, #144] ; (8004f90 <RCCEx_PLL3_Config+0x160>)
  12290. 8004f00: 4013 ands r3, r2
  12291. 8004f02: 687a ldr r2, [r7, #4]
  12292. 8004f04: 69d2 ldr r2, [r2, #28]
  12293. 8004f06: 00d2 lsls r2, r2, #3
  12294. 8004f08: 4920 ldr r1, [pc, #128] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12295. 8004f0a: 4313 orrs r3, r2
  12296. 8004f0c: 644b str r3, [r1, #68] ; 0x44
  12297. /* Enable PLL3FRACN . */
  12298. __HAL_RCC_PLL3FRACN_ENABLE();
  12299. 8004f0e: 4b1f ldr r3, [pc, #124] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12300. 8004f10: 6adb ldr r3, [r3, #44] ; 0x2c
  12301. 8004f12: 4a1e ldr r2, [pc, #120] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12302. 8004f14: f443 7380 orr.w r3, r3, #256 ; 0x100
  12303. 8004f18: 62d3 str r3, [r2, #44] ; 0x2c
  12304. /* Enable the PLL3 clock output */
  12305. if(Divider == DIVIDER_P_UPDATE)
  12306. 8004f1a: 683b ldr r3, [r7, #0]
  12307. 8004f1c: 2b00 cmp r3, #0
  12308. 8004f1e: d106 bne.n 8004f2e <RCCEx_PLL3_Config+0xfe>
  12309. {
  12310. __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
  12311. 8004f20: 4b1a ldr r3, [pc, #104] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12312. 8004f22: 6adb ldr r3, [r3, #44] ; 0x2c
  12313. 8004f24: 4a19 ldr r2, [pc, #100] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12314. 8004f26: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
  12315. 8004f2a: 62d3 str r3, [r2, #44] ; 0x2c
  12316. 8004f2c: e00f b.n 8004f4e <RCCEx_PLL3_Config+0x11e>
  12317. }
  12318. else if(Divider == DIVIDER_Q_UPDATE)
  12319. 8004f2e: 683b ldr r3, [r7, #0]
  12320. 8004f30: 2b01 cmp r3, #1
  12321. 8004f32: d106 bne.n 8004f42 <RCCEx_PLL3_Config+0x112>
  12322. {
  12323. __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
  12324. 8004f34: 4b15 ldr r3, [pc, #84] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12325. 8004f36: 6adb ldr r3, [r3, #44] ; 0x2c
  12326. 8004f38: 4a14 ldr r2, [pc, #80] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12327. 8004f3a: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
  12328. 8004f3e: 62d3 str r3, [r2, #44] ; 0x2c
  12329. 8004f40: e005 b.n 8004f4e <RCCEx_PLL3_Config+0x11e>
  12330. }
  12331. else
  12332. {
  12333. __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
  12334. 8004f42: 4b12 ldr r3, [pc, #72] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12335. 8004f44: 6adb ldr r3, [r3, #44] ; 0x2c
  12336. 8004f46: 4a11 ldr r2, [pc, #68] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12337. 8004f48: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
  12338. 8004f4c: 62d3 str r3, [r2, #44] ; 0x2c
  12339. }
  12340. /* Enable PLL3. */
  12341. __HAL_RCC_PLL3_ENABLE();
  12342. 8004f4e: 4b0f ldr r3, [pc, #60] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12343. 8004f50: 681b ldr r3, [r3, #0]
  12344. 8004f52: 4a0e ldr r2, [pc, #56] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12345. 8004f54: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
  12346. 8004f58: 6013 str r3, [r2, #0]
  12347. /* Get Start Tick*/
  12348. tickstart = HAL_GetTick();
  12349. 8004f5a: f7fc fb7d bl 8001658 <HAL_GetTick>
  12350. 8004f5e: 60b8 str r0, [r7, #8]
  12351. /* Wait till PLL3 is ready */
  12352. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
  12353. 8004f60: e008 b.n 8004f74 <RCCEx_PLL3_Config+0x144>
  12354. {
  12355. if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
  12356. 8004f62: f7fc fb79 bl 8001658 <HAL_GetTick>
  12357. 8004f66: 4602 mov r2, r0
  12358. 8004f68: 68bb ldr r3, [r7, #8]
  12359. 8004f6a: 1ad3 subs r3, r2, r3
  12360. 8004f6c: 2b02 cmp r3, #2
  12361. 8004f6e: d901 bls.n 8004f74 <RCCEx_PLL3_Config+0x144>
  12362. {
  12363. return HAL_TIMEOUT;
  12364. 8004f70: 2303 movs r3, #3
  12365. 8004f72: e006 b.n 8004f82 <RCCEx_PLL3_Config+0x152>
  12366. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
  12367. 8004f74: 4b05 ldr r3, [pc, #20] ; (8004f8c <RCCEx_PLL3_Config+0x15c>)
  12368. 8004f76: 681b ldr r3, [r3, #0]
  12369. 8004f78: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
  12370. 8004f7c: 2b00 cmp r3, #0
  12371. 8004f7e: d0f0 beq.n 8004f62 <RCCEx_PLL3_Config+0x132>
  12372. }
  12373. }
  12374. return status;
  12375. 8004f80: 7bfb ldrb r3, [r7, #15]
  12376. }
  12377. 8004f82: 4618 mov r0, r3
  12378. 8004f84: 3710 adds r7, #16
  12379. 8004f86: 46bd mov sp, r7
  12380. 8004f88: bd80 pop {r7, pc}
  12381. 8004f8a: bf00 nop
  12382. 8004f8c: 58024400 .word 0x58024400
  12383. 8004f90: ffff0007 .word 0xffff0007
  12384. 08004f94 <HAL_TIM_Base_Init>:
  12385. * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  12386. * @param htim TIM Base handle
  12387. * @retval HAL status
  12388. */
  12389. HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
  12390. {
  12391. 8004f94: b580 push {r7, lr}
  12392. 8004f96: b082 sub sp, #8
  12393. 8004f98: af00 add r7, sp, #0
  12394. 8004f9a: 6078 str r0, [r7, #4]
  12395. /* Check the TIM handle allocation */
  12396. if (htim == NULL)
  12397. 8004f9c: 687b ldr r3, [r7, #4]
  12398. 8004f9e: 2b00 cmp r3, #0
  12399. 8004fa0: d101 bne.n 8004fa6 <HAL_TIM_Base_Init+0x12>
  12400. {
  12401. return HAL_ERROR;
  12402. 8004fa2: 2301 movs r3, #1
  12403. 8004fa4: e049 b.n 800503a <HAL_TIM_Base_Init+0xa6>
  12404. assert_param(IS_TIM_INSTANCE(htim->Instance));
  12405. assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  12406. assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  12407. assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  12408. if (htim->State == HAL_TIM_STATE_RESET)
  12409. 8004fa6: 687b ldr r3, [r7, #4]
  12410. 8004fa8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
  12411. 8004fac: b2db uxtb r3, r3
  12412. 8004fae: 2b00 cmp r3, #0
  12413. 8004fb0: d106 bne.n 8004fc0 <HAL_TIM_Base_Init+0x2c>
  12414. {
  12415. /* Allocate lock resource and initialize it */
  12416. htim->Lock = HAL_UNLOCKED;
  12417. 8004fb2: 687b ldr r3, [r7, #4]
  12418. 8004fb4: 2200 movs r2, #0
  12419. 8004fb6: f883 203c strb.w r2, [r3, #60] ; 0x3c
  12420. }
  12421. /* Init the low level hardware : GPIO, CLOCK, NVIC */
  12422. htim->Base_MspInitCallback(htim);
  12423. #else
  12424. /* Init the low level hardware : GPIO, CLOCK, NVIC */
  12425. HAL_TIM_Base_MspInit(htim);
  12426. 8004fba: 6878 ldr r0, [r7, #4]
  12427. 8004fbc: f7fc f8f8 bl 80011b0 <HAL_TIM_Base_MspInit>
  12428. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  12429. }
  12430. /* Set the TIM state */
  12431. htim->State = HAL_TIM_STATE_BUSY;
  12432. 8004fc0: 687b ldr r3, [r7, #4]
  12433. 8004fc2: 2202 movs r2, #2
  12434. 8004fc4: f883 203d strb.w r2, [r3, #61] ; 0x3d
  12435. /* Set the Time Base configuration */
  12436. TIM_Base_SetConfig(htim->Instance, &htim->Init);
  12437. 8004fc8: 687b ldr r3, [r7, #4]
  12438. 8004fca: 681a ldr r2, [r3, #0]
  12439. 8004fcc: 687b ldr r3, [r7, #4]
  12440. 8004fce: 3304 adds r3, #4
  12441. 8004fd0: 4619 mov r1, r3
  12442. 8004fd2: 4610 mov r0, r2
  12443. 8004fd4: f000 fafc bl 80055d0 <TIM_Base_SetConfig>
  12444. /* Initialize the DMA burst operation state */
  12445. htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  12446. 8004fd8: 687b ldr r3, [r7, #4]
  12447. 8004fda: 2201 movs r2, #1
  12448. 8004fdc: f883 2048 strb.w r2, [r3, #72] ; 0x48
  12449. /* Initialize the TIM channels state */
  12450. TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  12451. 8004fe0: 687b ldr r3, [r7, #4]
  12452. 8004fe2: 2201 movs r2, #1
  12453. 8004fe4: f883 203e strb.w r2, [r3, #62] ; 0x3e
  12454. 8004fe8: 687b ldr r3, [r7, #4]
  12455. 8004fea: 2201 movs r2, #1
  12456. 8004fec: f883 203f strb.w r2, [r3, #63] ; 0x3f
  12457. 8004ff0: 687b ldr r3, [r7, #4]
  12458. 8004ff2: 2201 movs r2, #1
  12459. 8004ff4: f883 2040 strb.w r2, [r3, #64] ; 0x40
  12460. 8004ff8: 687b ldr r3, [r7, #4]
  12461. 8004ffa: 2201 movs r2, #1
  12462. 8004ffc: f883 2041 strb.w r2, [r3, #65] ; 0x41
  12463. 8005000: 687b ldr r3, [r7, #4]
  12464. 8005002: 2201 movs r2, #1
  12465. 8005004: f883 2042 strb.w r2, [r3, #66] ; 0x42
  12466. 8005008: 687b ldr r3, [r7, #4]
  12467. 800500a: 2201 movs r2, #1
  12468. 800500c: f883 2043 strb.w r2, [r3, #67] ; 0x43
  12469. TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  12470. 8005010: 687b ldr r3, [r7, #4]
  12471. 8005012: 2201 movs r2, #1
  12472. 8005014: f883 2044 strb.w r2, [r3, #68] ; 0x44
  12473. 8005018: 687b ldr r3, [r7, #4]
  12474. 800501a: 2201 movs r2, #1
  12475. 800501c: f883 2045 strb.w r2, [r3, #69] ; 0x45
  12476. 8005020: 687b ldr r3, [r7, #4]
  12477. 8005022: 2201 movs r2, #1
  12478. 8005024: f883 2046 strb.w r2, [r3, #70] ; 0x46
  12479. 8005028: 687b ldr r3, [r7, #4]
  12480. 800502a: 2201 movs r2, #1
  12481. 800502c: f883 2047 strb.w r2, [r3, #71] ; 0x47
  12482. /* Initialize the TIM state*/
  12483. htim->State = HAL_TIM_STATE_READY;
  12484. 8005030: 687b ldr r3, [r7, #4]
  12485. 8005032: 2201 movs r2, #1
  12486. 8005034: f883 203d strb.w r2, [r3, #61] ; 0x3d
  12487. return HAL_OK;
  12488. 8005038: 2300 movs r3, #0
  12489. }
  12490. 800503a: 4618 mov r0, r3
  12491. 800503c: 3708 adds r7, #8
  12492. 800503e: 46bd mov sp, r7
  12493. 8005040: bd80 pop {r7, pc}
  12494. ...
  12495. 08005044 <HAL_TIM_Base_Start_IT>:
  12496. * @brief Starts the TIM Base generation in interrupt mode.
  12497. * @param htim TIM Base handle
  12498. * @retval HAL status
  12499. */
  12500. HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
  12501. {
  12502. 8005044: b480 push {r7}
  12503. 8005046: b085 sub sp, #20
  12504. 8005048: af00 add r7, sp, #0
  12505. 800504a: 6078 str r0, [r7, #4]
  12506. /* Check the parameters */
  12507. assert_param(IS_TIM_INSTANCE(htim->Instance));
  12508. /* Check the TIM state */
  12509. if (htim->State != HAL_TIM_STATE_READY)
  12510. 800504c: 687b ldr r3, [r7, #4]
  12511. 800504e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
  12512. 8005052: b2db uxtb r3, r3
  12513. 8005054: 2b01 cmp r3, #1
  12514. 8005056: d001 beq.n 800505c <HAL_TIM_Base_Start_IT+0x18>
  12515. {
  12516. return HAL_ERROR;
  12517. 8005058: 2301 movs r3, #1
  12518. 800505a: e05e b.n 800511a <HAL_TIM_Base_Start_IT+0xd6>
  12519. }
  12520. /* Set the TIM state */
  12521. htim->State = HAL_TIM_STATE_BUSY;
  12522. 800505c: 687b ldr r3, [r7, #4]
  12523. 800505e: 2202 movs r2, #2
  12524. 8005060: f883 203d strb.w r2, [r3, #61] ; 0x3d
  12525. /* Enable the TIM Update interrupt */
  12526. __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
  12527. 8005064: 687b ldr r3, [r7, #4]
  12528. 8005066: 681b ldr r3, [r3, #0]
  12529. 8005068: 68da ldr r2, [r3, #12]
  12530. 800506a: 687b ldr r3, [r7, #4]
  12531. 800506c: 681b ldr r3, [r3, #0]
  12532. 800506e: f042 0201 orr.w r2, r2, #1
  12533. 8005072: 60da str r2, [r3, #12]
  12534. /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  12535. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  12536. 8005074: 687b ldr r3, [r7, #4]
  12537. 8005076: 681b ldr r3, [r3, #0]
  12538. 8005078: 4a2b ldr r2, [pc, #172] ; (8005128 <HAL_TIM_Base_Start_IT+0xe4>)
  12539. 800507a: 4293 cmp r3, r2
  12540. 800507c: d02c beq.n 80050d8 <HAL_TIM_Base_Start_IT+0x94>
  12541. 800507e: 687b ldr r3, [r7, #4]
  12542. 8005080: 681b ldr r3, [r3, #0]
  12543. 8005082: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
  12544. 8005086: d027 beq.n 80050d8 <HAL_TIM_Base_Start_IT+0x94>
  12545. 8005088: 687b ldr r3, [r7, #4]
  12546. 800508a: 681b ldr r3, [r3, #0]
  12547. 800508c: 4a27 ldr r2, [pc, #156] ; (800512c <HAL_TIM_Base_Start_IT+0xe8>)
  12548. 800508e: 4293 cmp r3, r2
  12549. 8005090: d022 beq.n 80050d8 <HAL_TIM_Base_Start_IT+0x94>
  12550. 8005092: 687b ldr r3, [r7, #4]
  12551. 8005094: 681b ldr r3, [r3, #0]
  12552. 8005096: 4a26 ldr r2, [pc, #152] ; (8005130 <HAL_TIM_Base_Start_IT+0xec>)
  12553. 8005098: 4293 cmp r3, r2
  12554. 800509a: d01d beq.n 80050d8 <HAL_TIM_Base_Start_IT+0x94>
  12555. 800509c: 687b ldr r3, [r7, #4]
  12556. 800509e: 681b ldr r3, [r3, #0]
  12557. 80050a0: 4a24 ldr r2, [pc, #144] ; (8005134 <HAL_TIM_Base_Start_IT+0xf0>)
  12558. 80050a2: 4293 cmp r3, r2
  12559. 80050a4: d018 beq.n 80050d8 <HAL_TIM_Base_Start_IT+0x94>
  12560. 80050a6: 687b ldr r3, [r7, #4]
  12561. 80050a8: 681b ldr r3, [r3, #0]
  12562. 80050aa: 4a23 ldr r2, [pc, #140] ; (8005138 <HAL_TIM_Base_Start_IT+0xf4>)
  12563. 80050ac: 4293 cmp r3, r2
  12564. 80050ae: d013 beq.n 80050d8 <HAL_TIM_Base_Start_IT+0x94>
  12565. 80050b0: 687b ldr r3, [r7, #4]
  12566. 80050b2: 681b ldr r3, [r3, #0]
  12567. 80050b4: 4a21 ldr r2, [pc, #132] ; (800513c <HAL_TIM_Base_Start_IT+0xf8>)
  12568. 80050b6: 4293 cmp r3, r2
  12569. 80050b8: d00e beq.n 80050d8 <HAL_TIM_Base_Start_IT+0x94>
  12570. 80050ba: 687b ldr r3, [r7, #4]
  12571. 80050bc: 681b ldr r3, [r3, #0]
  12572. 80050be: 4a20 ldr r2, [pc, #128] ; (8005140 <HAL_TIM_Base_Start_IT+0xfc>)
  12573. 80050c0: 4293 cmp r3, r2
  12574. 80050c2: d009 beq.n 80050d8 <HAL_TIM_Base_Start_IT+0x94>
  12575. 80050c4: 687b ldr r3, [r7, #4]
  12576. 80050c6: 681b ldr r3, [r3, #0]
  12577. 80050c8: 4a1e ldr r2, [pc, #120] ; (8005144 <HAL_TIM_Base_Start_IT+0x100>)
  12578. 80050ca: 4293 cmp r3, r2
  12579. 80050cc: d004 beq.n 80050d8 <HAL_TIM_Base_Start_IT+0x94>
  12580. 80050ce: 687b ldr r3, [r7, #4]
  12581. 80050d0: 681b ldr r3, [r3, #0]
  12582. 80050d2: 4a1d ldr r2, [pc, #116] ; (8005148 <HAL_TIM_Base_Start_IT+0x104>)
  12583. 80050d4: 4293 cmp r3, r2
  12584. 80050d6: d115 bne.n 8005104 <HAL_TIM_Base_Start_IT+0xc0>
  12585. {
  12586. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  12587. 80050d8: 687b ldr r3, [r7, #4]
  12588. 80050da: 681b ldr r3, [r3, #0]
  12589. 80050dc: 689a ldr r2, [r3, #8]
  12590. 80050de: 4b1b ldr r3, [pc, #108] ; (800514c <HAL_TIM_Base_Start_IT+0x108>)
  12591. 80050e0: 4013 ands r3, r2
  12592. 80050e2: 60fb str r3, [r7, #12]
  12593. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  12594. 80050e4: 68fb ldr r3, [r7, #12]
  12595. 80050e6: 2b06 cmp r3, #6
  12596. 80050e8: d015 beq.n 8005116 <HAL_TIM_Base_Start_IT+0xd2>
  12597. 80050ea: 68fb ldr r3, [r7, #12]
  12598. 80050ec: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
  12599. 80050f0: d011 beq.n 8005116 <HAL_TIM_Base_Start_IT+0xd2>
  12600. {
  12601. __HAL_TIM_ENABLE(htim);
  12602. 80050f2: 687b ldr r3, [r7, #4]
  12603. 80050f4: 681b ldr r3, [r3, #0]
  12604. 80050f6: 681a ldr r2, [r3, #0]
  12605. 80050f8: 687b ldr r3, [r7, #4]
  12606. 80050fa: 681b ldr r3, [r3, #0]
  12607. 80050fc: f042 0201 orr.w r2, r2, #1
  12608. 8005100: 601a str r2, [r3, #0]
  12609. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  12610. 8005102: e008 b.n 8005116 <HAL_TIM_Base_Start_IT+0xd2>
  12611. }
  12612. }
  12613. else
  12614. {
  12615. __HAL_TIM_ENABLE(htim);
  12616. 8005104: 687b ldr r3, [r7, #4]
  12617. 8005106: 681b ldr r3, [r3, #0]
  12618. 8005108: 681a ldr r2, [r3, #0]
  12619. 800510a: 687b ldr r3, [r7, #4]
  12620. 800510c: 681b ldr r3, [r3, #0]
  12621. 800510e: f042 0201 orr.w r2, r2, #1
  12622. 8005112: 601a str r2, [r3, #0]
  12623. 8005114: e000 b.n 8005118 <HAL_TIM_Base_Start_IT+0xd4>
  12624. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  12625. 8005116: bf00 nop
  12626. }
  12627. /* Return function status */
  12628. return HAL_OK;
  12629. 8005118: 2300 movs r3, #0
  12630. }
  12631. 800511a: 4618 mov r0, r3
  12632. 800511c: 3714 adds r7, #20
  12633. 800511e: 46bd mov sp, r7
  12634. 8005120: f85d 7b04 ldr.w r7, [sp], #4
  12635. 8005124: 4770 bx lr
  12636. 8005126: bf00 nop
  12637. 8005128: 40010000 .word 0x40010000
  12638. 800512c: 40000400 .word 0x40000400
  12639. 8005130: 40000800 .word 0x40000800
  12640. 8005134: 40000c00 .word 0x40000c00
  12641. 8005138: 40010400 .word 0x40010400
  12642. 800513c: 40001800 .word 0x40001800
  12643. 8005140: 40014000 .word 0x40014000
  12644. 8005144: 4000e000 .word 0x4000e000
  12645. 8005148: 4000e400 .word 0x4000e400
  12646. 800514c: 00010007 .word 0x00010007
  12647. 08005150 <HAL_TIM_IRQHandler>:
  12648. * @brief This function handles TIM interrupts requests.
  12649. * @param htim TIM handle
  12650. * @retval None
  12651. */
  12652. void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
  12653. {
  12654. 8005150: b580 push {r7, lr}
  12655. 8005152: b082 sub sp, #8
  12656. 8005154: af00 add r7, sp, #0
  12657. 8005156: 6078 str r0, [r7, #4]
  12658. /* Capture compare 1 event */
  12659. if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
  12660. 8005158: 687b ldr r3, [r7, #4]
  12661. 800515a: 681b ldr r3, [r3, #0]
  12662. 800515c: 691b ldr r3, [r3, #16]
  12663. 800515e: f003 0302 and.w r3, r3, #2
  12664. 8005162: 2b02 cmp r3, #2
  12665. 8005164: d122 bne.n 80051ac <HAL_TIM_IRQHandler+0x5c>
  12666. {
  12667. if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
  12668. 8005166: 687b ldr r3, [r7, #4]
  12669. 8005168: 681b ldr r3, [r3, #0]
  12670. 800516a: 68db ldr r3, [r3, #12]
  12671. 800516c: f003 0302 and.w r3, r3, #2
  12672. 8005170: 2b02 cmp r3, #2
  12673. 8005172: d11b bne.n 80051ac <HAL_TIM_IRQHandler+0x5c>
  12674. {
  12675. {
  12676. __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
  12677. 8005174: 687b ldr r3, [r7, #4]
  12678. 8005176: 681b ldr r3, [r3, #0]
  12679. 8005178: f06f 0202 mvn.w r2, #2
  12680. 800517c: 611a str r2, [r3, #16]
  12681. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  12682. 800517e: 687b ldr r3, [r7, #4]
  12683. 8005180: 2201 movs r2, #1
  12684. 8005182: 771a strb r2, [r3, #28]
  12685. /* Input capture event */
  12686. if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
  12687. 8005184: 687b ldr r3, [r7, #4]
  12688. 8005186: 681b ldr r3, [r3, #0]
  12689. 8005188: 699b ldr r3, [r3, #24]
  12690. 800518a: f003 0303 and.w r3, r3, #3
  12691. 800518e: 2b00 cmp r3, #0
  12692. 8005190: d003 beq.n 800519a <HAL_TIM_IRQHandler+0x4a>
  12693. {
  12694. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  12695. htim->IC_CaptureCallback(htim);
  12696. #else
  12697. HAL_TIM_IC_CaptureCallback(htim);
  12698. 8005192: 6878 ldr r0, [r7, #4]
  12699. 8005194: f000 f9fe bl 8005594 <HAL_TIM_IC_CaptureCallback>
  12700. 8005198: e005 b.n 80051a6 <HAL_TIM_IRQHandler+0x56>
  12701. {
  12702. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  12703. htim->OC_DelayElapsedCallback(htim);
  12704. htim->PWM_PulseFinishedCallback(htim);
  12705. #else
  12706. HAL_TIM_OC_DelayElapsedCallback(htim);
  12707. 800519a: 6878 ldr r0, [r7, #4]
  12708. 800519c: f000 f9f0 bl 8005580 <HAL_TIM_OC_DelayElapsedCallback>
  12709. HAL_TIM_PWM_PulseFinishedCallback(htim);
  12710. 80051a0: 6878 ldr r0, [r7, #4]
  12711. 80051a2: f000 fa01 bl 80055a8 <HAL_TIM_PWM_PulseFinishedCallback>
  12712. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  12713. }
  12714. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  12715. 80051a6: 687b ldr r3, [r7, #4]
  12716. 80051a8: 2200 movs r2, #0
  12717. 80051aa: 771a strb r2, [r3, #28]
  12718. }
  12719. }
  12720. }
  12721. /* Capture compare 2 event */
  12722. if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
  12723. 80051ac: 687b ldr r3, [r7, #4]
  12724. 80051ae: 681b ldr r3, [r3, #0]
  12725. 80051b0: 691b ldr r3, [r3, #16]
  12726. 80051b2: f003 0304 and.w r3, r3, #4
  12727. 80051b6: 2b04 cmp r3, #4
  12728. 80051b8: d122 bne.n 8005200 <HAL_TIM_IRQHandler+0xb0>
  12729. {
  12730. if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
  12731. 80051ba: 687b ldr r3, [r7, #4]
  12732. 80051bc: 681b ldr r3, [r3, #0]
  12733. 80051be: 68db ldr r3, [r3, #12]
  12734. 80051c0: f003 0304 and.w r3, r3, #4
  12735. 80051c4: 2b04 cmp r3, #4
  12736. 80051c6: d11b bne.n 8005200 <HAL_TIM_IRQHandler+0xb0>
  12737. {
  12738. __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
  12739. 80051c8: 687b ldr r3, [r7, #4]
  12740. 80051ca: 681b ldr r3, [r3, #0]
  12741. 80051cc: f06f 0204 mvn.w r2, #4
  12742. 80051d0: 611a str r2, [r3, #16]
  12743. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  12744. 80051d2: 687b ldr r3, [r7, #4]
  12745. 80051d4: 2202 movs r2, #2
  12746. 80051d6: 771a strb r2, [r3, #28]
  12747. /* Input capture event */
  12748. if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
  12749. 80051d8: 687b ldr r3, [r7, #4]
  12750. 80051da: 681b ldr r3, [r3, #0]
  12751. 80051dc: 699b ldr r3, [r3, #24]
  12752. 80051de: f403 7340 and.w r3, r3, #768 ; 0x300
  12753. 80051e2: 2b00 cmp r3, #0
  12754. 80051e4: d003 beq.n 80051ee <HAL_TIM_IRQHandler+0x9e>
  12755. {
  12756. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  12757. htim->IC_CaptureCallback(htim);
  12758. #else
  12759. HAL_TIM_IC_CaptureCallback(htim);
  12760. 80051e6: 6878 ldr r0, [r7, #4]
  12761. 80051e8: f000 f9d4 bl 8005594 <HAL_TIM_IC_CaptureCallback>
  12762. 80051ec: e005 b.n 80051fa <HAL_TIM_IRQHandler+0xaa>
  12763. {
  12764. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  12765. htim->OC_DelayElapsedCallback(htim);
  12766. htim->PWM_PulseFinishedCallback(htim);
  12767. #else
  12768. HAL_TIM_OC_DelayElapsedCallback(htim);
  12769. 80051ee: 6878 ldr r0, [r7, #4]
  12770. 80051f0: f000 f9c6 bl 8005580 <HAL_TIM_OC_DelayElapsedCallback>
  12771. HAL_TIM_PWM_PulseFinishedCallback(htim);
  12772. 80051f4: 6878 ldr r0, [r7, #4]
  12773. 80051f6: f000 f9d7 bl 80055a8 <HAL_TIM_PWM_PulseFinishedCallback>
  12774. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  12775. }
  12776. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  12777. 80051fa: 687b ldr r3, [r7, #4]
  12778. 80051fc: 2200 movs r2, #0
  12779. 80051fe: 771a strb r2, [r3, #28]
  12780. }
  12781. }
  12782. /* Capture compare 3 event */
  12783. if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
  12784. 8005200: 687b ldr r3, [r7, #4]
  12785. 8005202: 681b ldr r3, [r3, #0]
  12786. 8005204: 691b ldr r3, [r3, #16]
  12787. 8005206: f003 0308 and.w r3, r3, #8
  12788. 800520a: 2b08 cmp r3, #8
  12789. 800520c: d122 bne.n 8005254 <HAL_TIM_IRQHandler+0x104>
  12790. {
  12791. if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
  12792. 800520e: 687b ldr r3, [r7, #4]
  12793. 8005210: 681b ldr r3, [r3, #0]
  12794. 8005212: 68db ldr r3, [r3, #12]
  12795. 8005214: f003 0308 and.w r3, r3, #8
  12796. 8005218: 2b08 cmp r3, #8
  12797. 800521a: d11b bne.n 8005254 <HAL_TIM_IRQHandler+0x104>
  12798. {
  12799. __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
  12800. 800521c: 687b ldr r3, [r7, #4]
  12801. 800521e: 681b ldr r3, [r3, #0]
  12802. 8005220: f06f 0208 mvn.w r2, #8
  12803. 8005224: 611a str r2, [r3, #16]
  12804. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  12805. 8005226: 687b ldr r3, [r7, #4]
  12806. 8005228: 2204 movs r2, #4
  12807. 800522a: 771a strb r2, [r3, #28]
  12808. /* Input capture event */
  12809. if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
  12810. 800522c: 687b ldr r3, [r7, #4]
  12811. 800522e: 681b ldr r3, [r3, #0]
  12812. 8005230: 69db ldr r3, [r3, #28]
  12813. 8005232: f003 0303 and.w r3, r3, #3
  12814. 8005236: 2b00 cmp r3, #0
  12815. 8005238: d003 beq.n 8005242 <HAL_TIM_IRQHandler+0xf2>
  12816. {
  12817. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  12818. htim->IC_CaptureCallback(htim);
  12819. #else
  12820. HAL_TIM_IC_CaptureCallback(htim);
  12821. 800523a: 6878 ldr r0, [r7, #4]
  12822. 800523c: f000 f9aa bl 8005594 <HAL_TIM_IC_CaptureCallback>
  12823. 8005240: e005 b.n 800524e <HAL_TIM_IRQHandler+0xfe>
  12824. {
  12825. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  12826. htim->OC_DelayElapsedCallback(htim);
  12827. htim->PWM_PulseFinishedCallback(htim);
  12828. #else
  12829. HAL_TIM_OC_DelayElapsedCallback(htim);
  12830. 8005242: 6878 ldr r0, [r7, #4]
  12831. 8005244: f000 f99c bl 8005580 <HAL_TIM_OC_DelayElapsedCallback>
  12832. HAL_TIM_PWM_PulseFinishedCallback(htim);
  12833. 8005248: 6878 ldr r0, [r7, #4]
  12834. 800524a: f000 f9ad bl 80055a8 <HAL_TIM_PWM_PulseFinishedCallback>
  12835. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  12836. }
  12837. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  12838. 800524e: 687b ldr r3, [r7, #4]
  12839. 8005250: 2200 movs r2, #0
  12840. 8005252: 771a strb r2, [r3, #28]
  12841. }
  12842. }
  12843. /* Capture compare 4 event */
  12844. if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
  12845. 8005254: 687b ldr r3, [r7, #4]
  12846. 8005256: 681b ldr r3, [r3, #0]
  12847. 8005258: 691b ldr r3, [r3, #16]
  12848. 800525a: f003 0310 and.w r3, r3, #16
  12849. 800525e: 2b10 cmp r3, #16
  12850. 8005260: d122 bne.n 80052a8 <HAL_TIM_IRQHandler+0x158>
  12851. {
  12852. if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
  12853. 8005262: 687b ldr r3, [r7, #4]
  12854. 8005264: 681b ldr r3, [r3, #0]
  12855. 8005266: 68db ldr r3, [r3, #12]
  12856. 8005268: f003 0310 and.w r3, r3, #16
  12857. 800526c: 2b10 cmp r3, #16
  12858. 800526e: d11b bne.n 80052a8 <HAL_TIM_IRQHandler+0x158>
  12859. {
  12860. __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
  12861. 8005270: 687b ldr r3, [r7, #4]
  12862. 8005272: 681b ldr r3, [r3, #0]
  12863. 8005274: f06f 0210 mvn.w r2, #16
  12864. 8005278: 611a str r2, [r3, #16]
  12865. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  12866. 800527a: 687b ldr r3, [r7, #4]
  12867. 800527c: 2208 movs r2, #8
  12868. 800527e: 771a strb r2, [r3, #28]
  12869. /* Input capture event */
  12870. if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
  12871. 8005280: 687b ldr r3, [r7, #4]
  12872. 8005282: 681b ldr r3, [r3, #0]
  12873. 8005284: 69db ldr r3, [r3, #28]
  12874. 8005286: f403 7340 and.w r3, r3, #768 ; 0x300
  12875. 800528a: 2b00 cmp r3, #0
  12876. 800528c: d003 beq.n 8005296 <HAL_TIM_IRQHandler+0x146>
  12877. {
  12878. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  12879. htim->IC_CaptureCallback(htim);
  12880. #else
  12881. HAL_TIM_IC_CaptureCallback(htim);
  12882. 800528e: 6878 ldr r0, [r7, #4]
  12883. 8005290: f000 f980 bl 8005594 <HAL_TIM_IC_CaptureCallback>
  12884. 8005294: e005 b.n 80052a2 <HAL_TIM_IRQHandler+0x152>
  12885. {
  12886. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  12887. htim->OC_DelayElapsedCallback(htim);
  12888. htim->PWM_PulseFinishedCallback(htim);
  12889. #else
  12890. HAL_TIM_OC_DelayElapsedCallback(htim);
  12891. 8005296: 6878 ldr r0, [r7, #4]
  12892. 8005298: f000 f972 bl 8005580 <HAL_TIM_OC_DelayElapsedCallback>
  12893. HAL_TIM_PWM_PulseFinishedCallback(htim);
  12894. 800529c: 6878 ldr r0, [r7, #4]
  12895. 800529e: f000 f983 bl 80055a8 <HAL_TIM_PWM_PulseFinishedCallback>
  12896. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  12897. }
  12898. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  12899. 80052a2: 687b ldr r3, [r7, #4]
  12900. 80052a4: 2200 movs r2, #0
  12901. 80052a6: 771a strb r2, [r3, #28]
  12902. }
  12903. }
  12904. /* TIM Update event */
  12905. if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
  12906. 80052a8: 687b ldr r3, [r7, #4]
  12907. 80052aa: 681b ldr r3, [r3, #0]
  12908. 80052ac: 691b ldr r3, [r3, #16]
  12909. 80052ae: f003 0301 and.w r3, r3, #1
  12910. 80052b2: 2b01 cmp r3, #1
  12911. 80052b4: d10e bne.n 80052d4 <HAL_TIM_IRQHandler+0x184>
  12912. {
  12913. if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
  12914. 80052b6: 687b ldr r3, [r7, #4]
  12915. 80052b8: 681b ldr r3, [r3, #0]
  12916. 80052ba: 68db ldr r3, [r3, #12]
  12917. 80052bc: f003 0301 and.w r3, r3, #1
  12918. 80052c0: 2b01 cmp r3, #1
  12919. 80052c2: d107 bne.n 80052d4 <HAL_TIM_IRQHandler+0x184>
  12920. {
  12921. __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
  12922. 80052c4: 687b ldr r3, [r7, #4]
  12923. 80052c6: 681b ldr r3, [r3, #0]
  12924. 80052c8: f06f 0201 mvn.w r2, #1
  12925. 80052cc: 611a str r2, [r3, #16]
  12926. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  12927. htim->PeriodElapsedCallback(htim);
  12928. #else
  12929. HAL_TIM_PeriodElapsedCallback(htim);
  12930. 80052ce: 6878 ldr r0, [r7, #4]
  12931. 80052d0: f7fb fb7c bl 80009cc <HAL_TIM_PeriodElapsedCallback>
  12932. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  12933. }
  12934. }
  12935. /* TIM Break input event */
  12936. if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
  12937. 80052d4: 687b ldr r3, [r7, #4]
  12938. 80052d6: 681b ldr r3, [r3, #0]
  12939. 80052d8: 691b ldr r3, [r3, #16]
  12940. 80052da: f003 0380 and.w r3, r3, #128 ; 0x80
  12941. 80052de: 2b80 cmp r3, #128 ; 0x80
  12942. 80052e0: d10e bne.n 8005300 <HAL_TIM_IRQHandler+0x1b0>
  12943. {
  12944. if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
  12945. 80052e2: 687b ldr r3, [r7, #4]
  12946. 80052e4: 681b ldr r3, [r3, #0]
  12947. 80052e6: 68db ldr r3, [r3, #12]
  12948. 80052e8: f003 0380 and.w r3, r3, #128 ; 0x80
  12949. 80052ec: 2b80 cmp r3, #128 ; 0x80
  12950. 80052ee: d107 bne.n 8005300 <HAL_TIM_IRQHandler+0x1b0>
  12951. {
  12952. __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
  12953. 80052f0: 687b ldr r3, [r7, #4]
  12954. 80052f2: 681b ldr r3, [r3, #0]
  12955. 80052f4: f06f 0280 mvn.w r2, #128 ; 0x80
  12956. 80052f8: 611a str r2, [r3, #16]
  12957. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  12958. htim->BreakCallback(htim);
  12959. #else
  12960. HAL_TIMEx_BreakCallback(htim);
  12961. 80052fa: 6878 ldr r0, [r7, #4]
  12962. 80052fc: f000 fb52 bl 80059a4 <HAL_TIMEx_BreakCallback>
  12963. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  12964. }
  12965. }
  12966. /* TIM Break2 input event */
  12967. if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
  12968. 8005300: 687b ldr r3, [r7, #4]
  12969. 8005302: 681b ldr r3, [r3, #0]
  12970. 8005304: 691b ldr r3, [r3, #16]
  12971. 8005306: f403 7380 and.w r3, r3, #256 ; 0x100
  12972. 800530a: f5b3 7f80 cmp.w r3, #256 ; 0x100
  12973. 800530e: d10e bne.n 800532e <HAL_TIM_IRQHandler+0x1de>
  12974. {
  12975. if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
  12976. 8005310: 687b ldr r3, [r7, #4]
  12977. 8005312: 681b ldr r3, [r3, #0]
  12978. 8005314: 68db ldr r3, [r3, #12]
  12979. 8005316: f003 0380 and.w r3, r3, #128 ; 0x80
  12980. 800531a: 2b80 cmp r3, #128 ; 0x80
  12981. 800531c: d107 bne.n 800532e <HAL_TIM_IRQHandler+0x1de>
  12982. {
  12983. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
  12984. 800531e: 687b ldr r3, [r7, #4]
  12985. 8005320: 681b ldr r3, [r3, #0]
  12986. 8005322: f46f 7280 mvn.w r2, #256 ; 0x100
  12987. 8005326: 611a str r2, [r3, #16]
  12988. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  12989. htim->Break2Callback(htim);
  12990. #else
  12991. HAL_TIMEx_Break2Callback(htim);
  12992. 8005328: 6878 ldr r0, [r7, #4]
  12993. 800532a: f000 fb45 bl 80059b8 <HAL_TIMEx_Break2Callback>
  12994. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  12995. }
  12996. }
  12997. /* TIM Trigger detection event */
  12998. if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
  12999. 800532e: 687b ldr r3, [r7, #4]
  13000. 8005330: 681b ldr r3, [r3, #0]
  13001. 8005332: 691b ldr r3, [r3, #16]
  13002. 8005334: f003 0340 and.w r3, r3, #64 ; 0x40
  13003. 8005338: 2b40 cmp r3, #64 ; 0x40
  13004. 800533a: d10e bne.n 800535a <HAL_TIM_IRQHandler+0x20a>
  13005. {
  13006. if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
  13007. 800533c: 687b ldr r3, [r7, #4]
  13008. 800533e: 681b ldr r3, [r3, #0]
  13009. 8005340: 68db ldr r3, [r3, #12]
  13010. 8005342: f003 0340 and.w r3, r3, #64 ; 0x40
  13011. 8005346: 2b40 cmp r3, #64 ; 0x40
  13012. 8005348: d107 bne.n 800535a <HAL_TIM_IRQHandler+0x20a>
  13013. {
  13014. __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
  13015. 800534a: 687b ldr r3, [r7, #4]
  13016. 800534c: 681b ldr r3, [r3, #0]
  13017. 800534e: f06f 0240 mvn.w r2, #64 ; 0x40
  13018. 8005352: 611a str r2, [r3, #16]
  13019. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  13020. htim->TriggerCallback(htim);
  13021. #else
  13022. HAL_TIM_TriggerCallback(htim);
  13023. 8005354: 6878 ldr r0, [r7, #4]
  13024. 8005356: f000 f931 bl 80055bc <HAL_TIM_TriggerCallback>
  13025. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  13026. }
  13027. }
  13028. /* TIM commutation event */
  13029. if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
  13030. 800535a: 687b ldr r3, [r7, #4]
  13031. 800535c: 681b ldr r3, [r3, #0]
  13032. 800535e: 691b ldr r3, [r3, #16]
  13033. 8005360: f003 0320 and.w r3, r3, #32
  13034. 8005364: 2b20 cmp r3, #32
  13035. 8005366: d10e bne.n 8005386 <HAL_TIM_IRQHandler+0x236>
  13036. {
  13037. if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
  13038. 8005368: 687b ldr r3, [r7, #4]
  13039. 800536a: 681b ldr r3, [r3, #0]
  13040. 800536c: 68db ldr r3, [r3, #12]
  13041. 800536e: f003 0320 and.w r3, r3, #32
  13042. 8005372: 2b20 cmp r3, #32
  13043. 8005374: d107 bne.n 8005386 <HAL_TIM_IRQHandler+0x236>
  13044. {
  13045. __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
  13046. 8005376: 687b ldr r3, [r7, #4]
  13047. 8005378: 681b ldr r3, [r3, #0]
  13048. 800537a: f06f 0220 mvn.w r2, #32
  13049. 800537e: 611a str r2, [r3, #16]
  13050. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  13051. htim->CommutationCallback(htim);
  13052. #else
  13053. HAL_TIMEx_CommutCallback(htim);
  13054. 8005380: 6878 ldr r0, [r7, #4]
  13055. 8005382: f000 fb05 bl 8005990 <HAL_TIMEx_CommutCallback>
  13056. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  13057. }
  13058. }
  13059. }
  13060. 8005386: bf00 nop
  13061. 8005388: 3708 adds r7, #8
  13062. 800538a: 46bd mov sp, r7
  13063. 800538c: bd80 pop {r7, pc}
  13064. ...
  13065. 08005390 <HAL_TIM_ConfigClockSource>:
  13066. * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
  13067. * contains the clock source information for the TIM peripheral.
  13068. * @retval HAL status
  13069. */
  13070. HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
  13071. {
  13072. 8005390: b580 push {r7, lr}
  13073. 8005392: b084 sub sp, #16
  13074. 8005394: af00 add r7, sp, #0
  13075. 8005396: 6078 str r0, [r7, #4]
  13076. 8005398: 6039 str r1, [r7, #0]
  13077. HAL_StatusTypeDef status = HAL_OK;
  13078. 800539a: 2300 movs r3, #0
  13079. 800539c: 73fb strb r3, [r7, #15]
  13080. uint32_t tmpsmcr;
  13081. /* Process Locked */
  13082. __HAL_LOCK(htim);
  13083. 800539e: 687b ldr r3, [r7, #4]
  13084. 80053a0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
  13085. 80053a4: 2b01 cmp r3, #1
  13086. 80053a6: d101 bne.n 80053ac <HAL_TIM_ConfigClockSource+0x1c>
  13087. 80053a8: 2302 movs r3, #2
  13088. 80053aa: e0dc b.n 8005566 <HAL_TIM_ConfigClockSource+0x1d6>
  13089. 80053ac: 687b ldr r3, [r7, #4]
  13090. 80053ae: 2201 movs r2, #1
  13091. 80053b0: f883 203c strb.w r2, [r3, #60] ; 0x3c
  13092. htim->State = HAL_TIM_STATE_BUSY;
  13093. 80053b4: 687b ldr r3, [r7, #4]
  13094. 80053b6: 2202 movs r2, #2
  13095. 80053b8: f883 203d strb.w r2, [r3, #61] ; 0x3d
  13096. /* Check the parameters */
  13097. assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
  13098. /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  13099. tmpsmcr = htim->Instance->SMCR;
  13100. 80053bc: 687b ldr r3, [r7, #4]
  13101. 80053be: 681b ldr r3, [r3, #0]
  13102. 80053c0: 689b ldr r3, [r3, #8]
  13103. 80053c2: 60bb str r3, [r7, #8]
  13104. tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
  13105. 80053c4: 68ba ldr r2, [r7, #8]
  13106. 80053c6: 4b6a ldr r3, [pc, #424] ; (8005570 <HAL_TIM_ConfigClockSource+0x1e0>)
  13107. 80053c8: 4013 ands r3, r2
  13108. 80053ca: 60bb str r3, [r7, #8]
  13109. tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  13110. 80053cc: 68bb ldr r3, [r7, #8]
  13111. 80053ce: f423 437f bic.w r3, r3, #65280 ; 0xff00
  13112. 80053d2: 60bb str r3, [r7, #8]
  13113. htim->Instance->SMCR = tmpsmcr;
  13114. 80053d4: 687b ldr r3, [r7, #4]
  13115. 80053d6: 681b ldr r3, [r3, #0]
  13116. 80053d8: 68ba ldr r2, [r7, #8]
  13117. 80053da: 609a str r2, [r3, #8]
  13118. switch (sClockSourceConfig->ClockSource)
  13119. 80053dc: 683b ldr r3, [r7, #0]
  13120. 80053de: 681b ldr r3, [r3, #0]
  13121. 80053e0: 4a64 ldr r2, [pc, #400] ; (8005574 <HAL_TIM_ConfigClockSource+0x1e4>)
  13122. 80053e2: 4293 cmp r3, r2
  13123. 80053e4: f000 80a9 beq.w 800553a <HAL_TIM_ConfigClockSource+0x1aa>
  13124. 80053e8: 4a62 ldr r2, [pc, #392] ; (8005574 <HAL_TIM_ConfigClockSource+0x1e4>)
  13125. 80053ea: 4293 cmp r3, r2
  13126. 80053ec: f200 80ae bhi.w 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13127. 80053f0: 4a61 ldr r2, [pc, #388] ; (8005578 <HAL_TIM_ConfigClockSource+0x1e8>)
  13128. 80053f2: 4293 cmp r3, r2
  13129. 80053f4: f000 80a1 beq.w 800553a <HAL_TIM_ConfigClockSource+0x1aa>
  13130. 80053f8: 4a5f ldr r2, [pc, #380] ; (8005578 <HAL_TIM_ConfigClockSource+0x1e8>)
  13131. 80053fa: 4293 cmp r3, r2
  13132. 80053fc: f200 80a6 bhi.w 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13133. 8005400: 4a5e ldr r2, [pc, #376] ; (800557c <HAL_TIM_ConfigClockSource+0x1ec>)
  13134. 8005402: 4293 cmp r3, r2
  13135. 8005404: f000 8099 beq.w 800553a <HAL_TIM_ConfigClockSource+0x1aa>
  13136. 8005408: 4a5c ldr r2, [pc, #368] ; (800557c <HAL_TIM_ConfigClockSource+0x1ec>)
  13137. 800540a: 4293 cmp r3, r2
  13138. 800540c: f200 809e bhi.w 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13139. 8005410: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010
  13140. 8005414: f000 8091 beq.w 800553a <HAL_TIM_ConfigClockSource+0x1aa>
  13141. 8005418: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010
  13142. 800541c: f200 8096 bhi.w 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13143. 8005420: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
  13144. 8005424: f000 8089 beq.w 800553a <HAL_TIM_ConfigClockSource+0x1aa>
  13145. 8005428: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
  13146. 800542c: f200 808e bhi.w 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13147. 8005430: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
  13148. 8005434: d03e beq.n 80054b4 <HAL_TIM_ConfigClockSource+0x124>
  13149. 8005436: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
  13150. 800543a: f200 8087 bhi.w 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13151. 800543e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  13152. 8005442: f000 8086 beq.w 8005552 <HAL_TIM_ConfigClockSource+0x1c2>
  13153. 8005446: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  13154. 800544a: d87f bhi.n 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13155. 800544c: 2b70 cmp r3, #112 ; 0x70
  13156. 800544e: d01a beq.n 8005486 <HAL_TIM_ConfigClockSource+0xf6>
  13157. 8005450: 2b70 cmp r3, #112 ; 0x70
  13158. 8005452: d87b bhi.n 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13159. 8005454: 2b60 cmp r3, #96 ; 0x60
  13160. 8005456: d050 beq.n 80054fa <HAL_TIM_ConfigClockSource+0x16a>
  13161. 8005458: 2b60 cmp r3, #96 ; 0x60
  13162. 800545a: d877 bhi.n 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13163. 800545c: 2b50 cmp r3, #80 ; 0x50
  13164. 800545e: d03c beq.n 80054da <HAL_TIM_ConfigClockSource+0x14a>
  13165. 8005460: 2b50 cmp r3, #80 ; 0x50
  13166. 8005462: d873 bhi.n 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13167. 8005464: 2b40 cmp r3, #64 ; 0x40
  13168. 8005466: d058 beq.n 800551a <HAL_TIM_ConfigClockSource+0x18a>
  13169. 8005468: 2b40 cmp r3, #64 ; 0x40
  13170. 800546a: d86f bhi.n 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13171. 800546c: 2b30 cmp r3, #48 ; 0x30
  13172. 800546e: d064 beq.n 800553a <HAL_TIM_ConfigClockSource+0x1aa>
  13173. 8005470: 2b30 cmp r3, #48 ; 0x30
  13174. 8005472: d86b bhi.n 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13175. 8005474: 2b20 cmp r3, #32
  13176. 8005476: d060 beq.n 800553a <HAL_TIM_ConfigClockSource+0x1aa>
  13177. 8005478: 2b20 cmp r3, #32
  13178. 800547a: d867 bhi.n 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13179. 800547c: 2b00 cmp r3, #0
  13180. 800547e: d05c beq.n 800553a <HAL_TIM_ConfigClockSource+0x1aa>
  13181. 8005480: 2b10 cmp r3, #16
  13182. 8005482: d05a beq.n 800553a <HAL_TIM_ConfigClockSource+0x1aa>
  13183. 8005484: e062 b.n 800554c <HAL_TIM_ConfigClockSource+0x1bc>
  13184. assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  13185. assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  13186. assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  13187. /* Configure the ETR Clock source */
  13188. TIM_ETR_SetConfig(htim->Instance,
  13189. 8005486: 687b ldr r3, [r7, #4]
  13190. 8005488: 6818 ldr r0, [r3, #0]
  13191. 800548a: 683b ldr r3, [r7, #0]
  13192. 800548c: 6899 ldr r1, [r3, #8]
  13193. 800548e: 683b ldr r3, [r7, #0]
  13194. 8005490: 685a ldr r2, [r3, #4]
  13195. 8005492: 683b ldr r3, [r7, #0]
  13196. 8005494: 68db ldr r3, [r3, #12]
  13197. 8005496: f000 f9bf bl 8005818 <TIM_ETR_SetConfig>
  13198. sClockSourceConfig->ClockPrescaler,
  13199. sClockSourceConfig->ClockPolarity,
  13200. sClockSourceConfig->ClockFilter);
  13201. /* Select the External clock mode1 and the ETRF trigger */
  13202. tmpsmcr = htim->Instance->SMCR;
  13203. 800549a: 687b ldr r3, [r7, #4]
  13204. 800549c: 681b ldr r3, [r3, #0]
  13205. 800549e: 689b ldr r3, [r3, #8]
  13206. 80054a0: 60bb str r3, [r7, #8]
  13207. tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
  13208. 80054a2: 68bb ldr r3, [r7, #8]
  13209. 80054a4: f043 0377 orr.w r3, r3, #119 ; 0x77
  13210. 80054a8: 60bb str r3, [r7, #8]
  13211. /* Write to TIMx SMCR */
  13212. htim->Instance->SMCR = tmpsmcr;
  13213. 80054aa: 687b ldr r3, [r7, #4]
  13214. 80054ac: 681b ldr r3, [r3, #0]
  13215. 80054ae: 68ba ldr r2, [r7, #8]
  13216. 80054b0: 609a str r2, [r3, #8]
  13217. break;
  13218. 80054b2: e04f b.n 8005554 <HAL_TIM_ConfigClockSource+0x1c4>
  13219. assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  13220. assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  13221. assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  13222. /* Configure the ETR Clock source */
  13223. TIM_ETR_SetConfig(htim->Instance,
  13224. 80054b4: 687b ldr r3, [r7, #4]
  13225. 80054b6: 6818 ldr r0, [r3, #0]
  13226. 80054b8: 683b ldr r3, [r7, #0]
  13227. 80054ba: 6899 ldr r1, [r3, #8]
  13228. 80054bc: 683b ldr r3, [r7, #0]
  13229. 80054be: 685a ldr r2, [r3, #4]
  13230. 80054c0: 683b ldr r3, [r7, #0]
  13231. 80054c2: 68db ldr r3, [r3, #12]
  13232. 80054c4: f000 f9a8 bl 8005818 <TIM_ETR_SetConfig>
  13233. sClockSourceConfig->ClockPrescaler,
  13234. sClockSourceConfig->ClockPolarity,
  13235. sClockSourceConfig->ClockFilter);
  13236. /* Enable the External clock mode2 */
  13237. htim->Instance->SMCR |= TIM_SMCR_ECE;
  13238. 80054c8: 687b ldr r3, [r7, #4]
  13239. 80054ca: 681b ldr r3, [r3, #0]
  13240. 80054cc: 689a ldr r2, [r3, #8]
  13241. 80054ce: 687b ldr r3, [r7, #4]
  13242. 80054d0: 681b ldr r3, [r3, #0]
  13243. 80054d2: f442 4280 orr.w r2, r2, #16384 ; 0x4000
  13244. 80054d6: 609a str r2, [r3, #8]
  13245. break;
  13246. 80054d8: e03c b.n 8005554 <HAL_TIM_ConfigClockSource+0x1c4>
  13247. /* Check TI1 input conditioning related parameters */
  13248. assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  13249. assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  13250. TIM_TI1_ConfigInputStage(htim->Instance,
  13251. 80054da: 687b ldr r3, [r7, #4]
  13252. 80054dc: 6818 ldr r0, [r3, #0]
  13253. 80054de: 683b ldr r3, [r7, #0]
  13254. 80054e0: 6859 ldr r1, [r3, #4]
  13255. 80054e2: 683b ldr r3, [r7, #0]
  13256. 80054e4: 68db ldr r3, [r3, #12]
  13257. 80054e6: 461a mov r2, r3
  13258. 80054e8: f000 f918 bl 800571c <TIM_TI1_ConfigInputStage>
  13259. sClockSourceConfig->ClockPolarity,
  13260. sClockSourceConfig->ClockFilter);
  13261. TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
  13262. 80054ec: 687b ldr r3, [r7, #4]
  13263. 80054ee: 681b ldr r3, [r3, #0]
  13264. 80054f0: 2150 movs r1, #80 ; 0x50
  13265. 80054f2: 4618 mov r0, r3
  13266. 80054f4: f000 f972 bl 80057dc <TIM_ITRx_SetConfig>
  13267. break;
  13268. 80054f8: e02c b.n 8005554 <HAL_TIM_ConfigClockSource+0x1c4>
  13269. /* Check TI2 input conditioning related parameters */
  13270. assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  13271. assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  13272. TIM_TI2_ConfigInputStage(htim->Instance,
  13273. 80054fa: 687b ldr r3, [r7, #4]
  13274. 80054fc: 6818 ldr r0, [r3, #0]
  13275. 80054fe: 683b ldr r3, [r7, #0]
  13276. 8005500: 6859 ldr r1, [r3, #4]
  13277. 8005502: 683b ldr r3, [r7, #0]
  13278. 8005504: 68db ldr r3, [r3, #12]
  13279. 8005506: 461a mov r2, r3
  13280. 8005508: f000 f937 bl 800577a <TIM_TI2_ConfigInputStage>
  13281. sClockSourceConfig->ClockPolarity,
  13282. sClockSourceConfig->ClockFilter);
  13283. TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
  13284. 800550c: 687b ldr r3, [r7, #4]
  13285. 800550e: 681b ldr r3, [r3, #0]
  13286. 8005510: 2160 movs r1, #96 ; 0x60
  13287. 8005512: 4618 mov r0, r3
  13288. 8005514: f000 f962 bl 80057dc <TIM_ITRx_SetConfig>
  13289. break;
  13290. 8005518: e01c b.n 8005554 <HAL_TIM_ConfigClockSource+0x1c4>
  13291. /* Check TI1 input conditioning related parameters */
  13292. assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  13293. assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  13294. TIM_TI1_ConfigInputStage(htim->Instance,
  13295. 800551a: 687b ldr r3, [r7, #4]
  13296. 800551c: 6818 ldr r0, [r3, #0]
  13297. 800551e: 683b ldr r3, [r7, #0]
  13298. 8005520: 6859 ldr r1, [r3, #4]
  13299. 8005522: 683b ldr r3, [r7, #0]
  13300. 8005524: 68db ldr r3, [r3, #12]
  13301. 8005526: 461a mov r2, r3
  13302. 8005528: f000 f8f8 bl 800571c <TIM_TI1_ConfigInputStage>
  13303. sClockSourceConfig->ClockPolarity,
  13304. sClockSourceConfig->ClockFilter);
  13305. TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
  13306. 800552c: 687b ldr r3, [r7, #4]
  13307. 800552e: 681b ldr r3, [r3, #0]
  13308. 8005530: 2140 movs r1, #64 ; 0x40
  13309. 8005532: 4618 mov r0, r3
  13310. 8005534: f000 f952 bl 80057dc <TIM_ITRx_SetConfig>
  13311. break;
  13312. 8005538: e00c b.n 8005554 <HAL_TIM_ConfigClockSource+0x1c4>
  13313. case TIM_CLOCKSOURCE_ITR8:
  13314. {
  13315. /* Check whether or not the timer instance supports internal trigger input */
  13316. assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
  13317. TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
  13318. 800553a: 687b ldr r3, [r7, #4]
  13319. 800553c: 681a ldr r2, [r3, #0]
  13320. 800553e: 683b ldr r3, [r7, #0]
  13321. 8005540: 681b ldr r3, [r3, #0]
  13322. 8005542: 4619 mov r1, r3
  13323. 8005544: 4610 mov r0, r2
  13324. 8005546: f000 f949 bl 80057dc <TIM_ITRx_SetConfig>
  13325. break;
  13326. 800554a: e003 b.n 8005554 <HAL_TIM_ConfigClockSource+0x1c4>
  13327. }
  13328. default:
  13329. status = HAL_ERROR;
  13330. 800554c: 2301 movs r3, #1
  13331. 800554e: 73fb strb r3, [r7, #15]
  13332. break;
  13333. 8005550: e000 b.n 8005554 <HAL_TIM_ConfigClockSource+0x1c4>
  13334. break;
  13335. 8005552: bf00 nop
  13336. }
  13337. htim->State = HAL_TIM_STATE_READY;
  13338. 8005554: 687b ldr r3, [r7, #4]
  13339. 8005556: 2201 movs r2, #1
  13340. 8005558: f883 203d strb.w r2, [r3, #61] ; 0x3d
  13341. __HAL_UNLOCK(htim);
  13342. 800555c: 687b ldr r3, [r7, #4]
  13343. 800555e: 2200 movs r2, #0
  13344. 8005560: f883 203c strb.w r2, [r3, #60] ; 0x3c
  13345. return status;
  13346. 8005564: 7bfb ldrb r3, [r7, #15]
  13347. }
  13348. 8005566: 4618 mov r0, r3
  13349. 8005568: 3710 adds r7, #16
  13350. 800556a: 46bd mov sp, r7
  13351. 800556c: bd80 pop {r7, pc}
  13352. 800556e: bf00 nop
  13353. 8005570: ffceff88 .word 0xffceff88
  13354. 8005574: 00100040 .word 0x00100040
  13355. 8005578: 00100030 .word 0x00100030
  13356. 800557c: 00100020 .word 0x00100020
  13357. 08005580 <HAL_TIM_OC_DelayElapsedCallback>:
  13358. * @brief Output Compare callback in non-blocking mode
  13359. * @param htim TIM OC handle
  13360. * @retval None
  13361. */
  13362. __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
  13363. {
  13364. 8005580: b480 push {r7}
  13365. 8005582: b083 sub sp, #12
  13366. 8005584: af00 add r7, sp, #0
  13367. 8005586: 6078 str r0, [r7, #4]
  13368. UNUSED(htim);
  13369. /* NOTE : This function should not be modified, when the callback is needed,
  13370. the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
  13371. */
  13372. }
  13373. 8005588: bf00 nop
  13374. 800558a: 370c adds r7, #12
  13375. 800558c: 46bd mov sp, r7
  13376. 800558e: f85d 7b04 ldr.w r7, [sp], #4
  13377. 8005592: 4770 bx lr
  13378. 08005594 <HAL_TIM_IC_CaptureCallback>:
  13379. * @brief Input Capture callback in non-blocking mode
  13380. * @param htim TIM IC handle
  13381. * @retval None
  13382. */
  13383. __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
  13384. {
  13385. 8005594: b480 push {r7}
  13386. 8005596: b083 sub sp, #12
  13387. 8005598: af00 add r7, sp, #0
  13388. 800559a: 6078 str r0, [r7, #4]
  13389. UNUSED(htim);
  13390. /* NOTE : This function should not be modified, when the callback is needed,
  13391. the HAL_TIM_IC_CaptureCallback could be implemented in the user file
  13392. */
  13393. }
  13394. 800559c: bf00 nop
  13395. 800559e: 370c adds r7, #12
  13396. 80055a0: 46bd mov sp, r7
  13397. 80055a2: f85d 7b04 ldr.w r7, [sp], #4
  13398. 80055a6: 4770 bx lr
  13399. 080055a8 <HAL_TIM_PWM_PulseFinishedCallback>:
  13400. * @brief PWM Pulse finished callback in non-blocking mode
  13401. * @param htim TIM handle
  13402. * @retval None
  13403. */
  13404. __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
  13405. {
  13406. 80055a8: b480 push {r7}
  13407. 80055aa: b083 sub sp, #12
  13408. 80055ac: af00 add r7, sp, #0
  13409. 80055ae: 6078 str r0, [r7, #4]
  13410. UNUSED(htim);
  13411. /* NOTE : This function should not be modified, when the callback is needed,
  13412. the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
  13413. */
  13414. }
  13415. 80055b0: bf00 nop
  13416. 80055b2: 370c adds r7, #12
  13417. 80055b4: 46bd mov sp, r7
  13418. 80055b6: f85d 7b04 ldr.w r7, [sp], #4
  13419. 80055ba: 4770 bx lr
  13420. 080055bc <HAL_TIM_TriggerCallback>:
  13421. * @brief Hall Trigger detection callback in non-blocking mode
  13422. * @param htim TIM handle
  13423. * @retval None
  13424. */
  13425. __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
  13426. {
  13427. 80055bc: b480 push {r7}
  13428. 80055be: b083 sub sp, #12
  13429. 80055c0: af00 add r7, sp, #0
  13430. 80055c2: 6078 str r0, [r7, #4]
  13431. UNUSED(htim);
  13432. /* NOTE : This function should not be modified, when the callback is needed,
  13433. the HAL_TIM_TriggerCallback could be implemented in the user file
  13434. */
  13435. }
  13436. 80055c4: bf00 nop
  13437. 80055c6: 370c adds r7, #12
  13438. 80055c8: 46bd mov sp, r7
  13439. 80055ca: f85d 7b04 ldr.w r7, [sp], #4
  13440. 80055ce: 4770 bx lr
  13441. 080055d0 <TIM_Base_SetConfig>:
  13442. * @param TIMx TIM peripheral
  13443. * @param Structure TIM Base configuration structure
  13444. * @retval None
  13445. */
  13446. void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
  13447. {
  13448. 80055d0: b480 push {r7}
  13449. 80055d2: b085 sub sp, #20
  13450. 80055d4: af00 add r7, sp, #0
  13451. 80055d6: 6078 str r0, [r7, #4]
  13452. 80055d8: 6039 str r1, [r7, #0]
  13453. uint32_t tmpcr1;
  13454. tmpcr1 = TIMx->CR1;
  13455. 80055da: 687b ldr r3, [r7, #4]
  13456. 80055dc: 681b ldr r3, [r3, #0]
  13457. 80055de: 60fb str r3, [r7, #12]
  13458. /* Set TIM Time Base Unit parameters ---------------------------------------*/
  13459. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  13460. 80055e0: 687b ldr r3, [r7, #4]
  13461. 80055e2: 4a44 ldr r2, [pc, #272] ; (80056f4 <TIM_Base_SetConfig+0x124>)
  13462. 80055e4: 4293 cmp r3, r2
  13463. 80055e6: d013 beq.n 8005610 <TIM_Base_SetConfig+0x40>
  13464. 80055e8: 687b ldr r3, [r7, #4]
  13465. 80055ea: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
  13466. 80055ee: d00f beq.n 8005610 <TIM_Base_SetConfig+0x40>
  13467. 80055f0: 687b ldr r3, [r7, #4]
  13468. 80055f2: 4a41 ldr r2, [pc, #260] ; (80056f8 <TIM_Base_SetConfig+0x128>)
  13469. 80055f4: 4293 cmp r3, r2
  13470. 80055f6: d00b beq.n 8005610 <TIM_Base_SetConfig+0x40>
  13471. 80055f8: 687b ldr r3, [r7, #4]
  13472. 80055fa: 4a40 ldr r2, [pc, #256] ; (80056fc <TIM_Base_SetConfig+0x12c>)
  13473. 80055fc: 4293 cmp r3, r2
  13474. 80055fe: d007 beq.n 8005610 <TIM_Base_SetConfig+0x40>
  13475. 8005600: 687b ldr r3, [r7, #4]
  13476. 8005602: 4a3f ldr r2, [pc, #252] ; (8005700 <TIM_Base_SetConfig+0x130>)
  13477. 8005604: 4293 cmp r3, r2
  13478. 8005606: d003 beq.n 8005610 <TIM_Base_SetConfig+0x40>
  13479. 8005608: 687b ldr r3, [r7, #4]
  13480. 800560a: 4a3e ldr r2, [pc, #248] ; (8005704 <TIM_Base_SetConfig+0x134>)
  13481. 800560c: 4293 cmp r3, r2
  13482. 800560e: d108 bne.n 8005622 <TIM_Base_SetConfig+0x52>
  13483. {
  13484. /* Select the Counter Mode */
  13485. tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
  13486. 8005610: 68fb ldr r3, [r7, #12]
  13487. 8005612: f023 0370 bic.w r3, r3, #112 ; 0x70
  13488. 8005616: 60fb str r3, [r7, #12]
  13489. tmpcr1 |= Structure->CounterMode;
  13490. 8005618: 683b ldr r3, [r7, #0]
  13491. 800561a: 685b ldr r3, [r3, #4]
  13492. 800561c: 68fa ldr r2, [r7, #12]
  13493. 800561e: 4313 orrs r3, r2
  13494. 8005620: 60fb str r3, [r7, #12]
  13495. }
  13496. if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  13497. 8005622: 687b ldr r3, [r7, #4]
  13498. 8005624: 4a33 ldr r2, [pc, #204] ; (80056f4 <TIM_Base_SetConfig+0x124>)
  13499. 8005626: 4293 cmp r3, r2
  13500. 8005628: d027 beq.n 800567a <TIM_Base_SetConfig+0xaa>
  13501. 800562a: 687b ldr r3, [r7, #4]
  13502. 800562c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
  13503. 8005630: d023 beq.n 800567a <TIM_Base_SetConfig+0xaa>
  13504. 8005632: 687b ldr r3, [r7, #4]
  13505. 8005634: 4a30 ldr r2, [pc, #192] ; (80056f8 <TIM_Base_SetConfig+0x128>)
  13506. 8005636: 4293 cmp r3, r2
  13507. 8005638: d01f beq.n 800567a <TIM_Base_SetConfig+0xaa>
  13508. 800563a: 687b ldr r3, [r7, #4]
  13509. 800563c: 4a2f ldr r2, [pc, #188] ; (80056fc <TIM_Base_SetConfig+0x12c>)
  13510. 800563e: 4293 cmp r3, r2
  13511. 8005640: d01b beq.n 800567a <TIM_Base_SetConfig+0xaa>
  13512. 8005642: 687b ldr r3, [r7, #4]
  13513. 8005644: 4a2e ldr r2, [pc, #184] ; (8005700 <TIM_Base_SetConfig+0x130>)
  13514. 8005646: 4293 cmp r3, r2
  13515. 8005648: d017 beq.n 800567a <TIM_Base_SetConfig+0xaa>
  13516. 800564a: 687b ldr r3, [r7, #4]
  13517. 800564c: 4a2d ldr r2, [pc, #180] ; (8005704 <TIM_Base_SetConfig+0x134>)
  13518. 800564e: 4293 cmp r3, r2
  13519. 8005650: d013 beq.n 800567a <TIM_Base_SetConfig+0xaa>
  13520. 8005652: 687b ldr r3, [r7, #4]
  13521. 8005654: 4a2c ldr r2, [pc, #176] ; (8005708 <TIM_Base_SetConfig+0x138>)
  13522. 8005656: 4293 cmp r3, r2
  13523. 8005658: d00f beq.n 800567a <TIM_Base_SetConfig+0xaa>
  13524. 800565a: 687b ldr r3, [r7, #4]
  13525. 800565c: 4a2b ldr r2, [pc, #172] ; (800570c <TIM_Base_SetConfig+0x13c>)
  13526. 800565e: 4293 cmp r3, r2
  13527. 8005660: d00b beq.n 800567a <TIM_Base_SetConfig+0xaa>
  13528. 8005662: 687b ldr r3, [r7, #4]
  13529. 8005664: 4a2a ldr r2, [pc, #168] ; (8005710 <TIM_Base_SetConfig+0x140>)
  13530. 8005666: 4293 cmp r3, r2
  13531. 8005668: d007 beq.n 800567a <TIM_Base_SetConfig+0xaa>
  13532. 800566a: 687b ldr r3, [r7, #4]
  13533. 800566c: 4a29 ldr r2, [pc, #164] ; (8005714 <TIM_Base_SetConfig+0x144>)
  13534. 800566e: 4293 cmp r3, r2
  13535. 8005670: d003 beq.n 800567a <TIM_Base_SetConfig+0xaa>
  13536. 8005672: 687b ldr r3, [r7, #4]
  13537. 8005674: 4a28 ldr r2, [pc, #160] ; (8005718 <TIM_Base_SetConfig+0x148>)
  13538. 8005676: 4293 cmp r3, r2
  13539. 8005678: d108 bne.n 800568c <TIM_Base_SetConfig+0xbc>
  13540. {
  13541. /* Set the clock division */
  13542. tmpcr1 &= ~TIM_CR1_CKD;
  13543. 800567a: 68fb ldr r3, [r7, #12]
  13544. 800567c: f423 7340 bic.w r3, r3, #768 ; 0x300
  13545. 8005680: 60fb str r3, [r7, #12]
  13546. tmpcr1 |= (uint32_t)Structure->ClockDivision;
  13547. 8005682: 683b ldr r3, [r7, #0]
  13548. 8005684: 68db ldr r3, [r3, #12]
  13549. 8005686: 68fa ldr r2, [r7, #12]
  13550. 8005688: 4313 orrs r3, r2
  13551. 800568a: 60fb str r3, [r7, #12]
  13552. }
  13553. /* Set the auto-reload preload */
  13554. MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  13555. 800568c: 68fb ldr r3, [r7, #12]
  13556. 800568e: f023 0280 bic.w r2, r3, #128 ; 0x80
  13557. 8005692: 683b ldr r3, [r7, #0]
  13558. 8005694: 695b ldr r3, [r3, #20]
  13559. 8005696: 4313 orrs r3, r2
  13560. 8005698: 60fb str r3, [r7, #12]
  13561. TIMx->CR1 = tmpcr1;
  13562. 800569a: 687b ldr r3, [r7, #4]
  13563. 800569c: 68fa ldr r2, [r7, #12]
  13564. 800569e: 601a str r2, [r3, #0]
  13565. /* Set the Autoreload value */
  13566. TIMx->ARR = (uint32_t)Structure->Period ;
  13567. 80056a0: 683b ldr r3, [r7, #0]
  13568. 80056a2: 689a ldr r2, [r3, #8]
  13569. 80056a4: 687b ldr r3, [r7, #4]
  13570. 80056a6: 62da str r2, [r3, #44] ; 0x2c
  13571. /* Set the Prescaler value */
  13572. TIMx->PSC = Structure->Prescaler;
  13573. 80056a8: 683b ldr r3, [r7, #0]
  13574. 80056aa: 681a ldr r2, [r3, #0]
  13575. 80056ac: 687b ldr r3, [r7, #4]
  13576. 80056ae: 629a str r2, [r3, #40] ; 0x28
  13577. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  13578. 80056b0: 687b ldr r3, [r7, #4]
  13579. 80056b2: 4a10 ldr r2, [pc, #64] ; (80056f4 <TIM_Base_SetConfig+0x124>)
  13580. 80056b4: 4293 cmp r3, r2
  13581. 80056b6: d00f beq.n 80056d8 <TIM_Base_SetConfig+0x108>
  13582. 80056b8: 687b ldr r3, [r7, #4]
  13583. 80056ba: 4a12 ldr r2, [pc, #72] ; (8005704 <TIM_Base_SetConfig+0x134>)
  13584. 80056bc: 4293 cmp r3, r2
  13585. 80056be: d00b beq.n 80056d8 <TIM_Base_SetConfig+0x108>
  13586. 80056c0: 687b ldr r3, [r7, #4]
  13587. 80056c2: 4a11 ldr r2, [pc, #68] ; (8005708 <TIM_Base_SetConfig+0x138>)
  13588. 80056c4: 4293 cmp r3, r2
  13589. 80056c6: d007 beq.n 80056d8 <TIM_Base_SetConfig+0x108>
  13590. 80056c8: 687b ldr r3, [r7, #4]
  13591. 80056ca: 4a10 ldr r2, [pc, #64] ; (800570c <TIM_Base_SetConfig+0x13c>)
  13592. 80056cc: 4293 cmp r3, r2
  13593. 80056ce: d003 beq.n 80056d8 <TIM_Base_SetConfig+0x108>
  13594. 80056d0: 687b ldr r3, [r7, #4]
  13595. 80056d2: 4a0f ldr r2, [pc, #60] ; (8005710 <TIM_Base_SetConfig+0x140>)
  13596. 80056d4: 4293 cmp r3, r2
  13597. 80056d6: d103 bne.n 80056e0 <TIM_Base_SetConfig+0x110>
  13598. {
  13599. /* Set the Repetition Counter value */
  13600. TIMx->RCR = Structure->RepetitionCounter;
  13601. 80056d8: 683b ldr r3, [r7, #0]
  13602. 80056da: 691a ldr r2, [r3, #16]
  13603. 80056dc: 687b ldr r3, [r7, #4]
  13604. 80056de: 631a str r2, [r3, #48] ; 0x30
  13605. }
  13606. /* Generate an update event to reload the Prescaler
  13607. and the repetition counter (only for advanced timer) value immediately */
  13608. TIMx->EGR = TIM_EGR_UG;
  13609. 80056e0: 687b ldr r3, [r7, #4]
  13610. 80056e2: 2201 movs r2, #1
  13611. 80056e4: 615a str r2, [r3, #20]
  13612. }
  13613. 80056e6: bf00 nop
  13614. 80056e8: 3714 adds r7, #20
  13615. 80056ea: 46bd mov sp, r7
  13616. 80056ec: f85d 7b04 ldr.w r7, [sp], #4
  13617. 80056f0: 4770 bx lr
  13618. 80056f2: bf00 nop
  13619. 80056f4: 40010000 .word 0x40010000
  13620. 80056f8: 40000400 .word 0x40000400
  13621. 80056fc: 40000800 .word 0x40000800
  13622. 8005700: 40000c00 .word 0x40000c00
  13623. 8005704: 40010400 .word 0x40010400
  13624. 8005708: 40014000 .word 0x40014000
  13625. 800570c: 40014400 .word 0x40014400
  13626. 8005710: 40014800 .word 0x40014800
  13627. 8005714: 4000e000 .word 0x4000e000
  13628. 8005718: 4000e400 .word 0x4000e400
  13629. 0800571c <TIM_TI1_ConfigInputStage>:
  13630. * @param TIM_ICFilter Specifies the Input Capture Filter.
  13631. * This parameter must be a value between 0x00 and 0x0F.
  13632. * @retval None
  13633. */
  13634. static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  13635. {
  13636. 800571c: b480 push {r7}
  13637. 800571e: b087 sub sp, #28
  13638. 8005720: af00 add r7, sp, #0
  13639. 8005722: 60f8 str r0, [r7, #12]
  13640. 8005724: 60b9 str r1, [r7, #8]
  13641. 8005726: 607a str r2, [r7, #4]
  13642. uint32_t tmpccmr1;
  13643. uint32_t tmpccer;
  13644. /* Disable the Channel 1: Reset the CC1E Bit */
  13645. tmpccer = TIMx->CCER;
  13646. 8005728: 68fb ldr r3, [r7, #12]
  13647. 800572a: 6a1b ldr r3, [r3, #32]
  13648. 800572c: 617b str r3, [r7, #20]
  13649. TIMx->CCER &= ~TIM_CCER_CC1E;
  13650. 800572e: 68fb ldr r3, [r7, #12]
  13651. 8005730: 6a1b ldr r3, [r3, #32]
  13652. 8005732: f023 0201 bic.w r2, r3, #1
  13653. 8005736: 68fb ldr r3, [r7, #12]
  13654. 8005738: 621a str r2, [r3, #32]
  13655. tmpccmr1 = TIMx->CCMR1;
  13656. 800573a: 68fb ldr r3, [r7, #12]
  13657. 800573c: 699b ldr r3, [r3, #24]
  13658. 800573e: 613b str r3, [r7, #16]
  13659. /* Set the filter */
  13660. tmpccmr1 &= ~TIM_CCMR1_IC1F;
  13661. 8005740: 693b ldr r3, [r7, #16]
  13662. 8005742: f023 03f0 bic.w r3, r3, #240 ; 0xf0
  13663. 8005746: 613b str r3, [r7, #16]
  13664. tmpccmr1 |= (TIM_ICFilter << 4U);
  13665. 8005748: 687b ldr r3, [r7, #4]
  13666. 800574a: 011b lsls r3, r3, #4
  13667. 800574c: 693a ldr r2, [r7, #16]
  13668. 800574e: 4313 orrs r3, r2
  13669. 8005750: 613b str r3, [r7, #16]
  13670. /* Select the Polarity and set the CC1E Bit */
  13671. tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  13672. 8005752: 697b ldr r3, [r7, #20]
  13673. 8005754: f023 030a bic.w r3, r3, #10
  13674. 8005758: 617b str r3, [r7, #20]
  13675. tmpccer |= TIM_ICPolarity;
  13676. 800575a: 697a ldr r2, [r7, #20]
  13677. 800575c: 68bb ldr r3, [r7, #8]
  13678. 800575e: 4313 orrs r3, r2
  13679. 8005760: 617b str r3, [r7, #20]
  13680. /* Write to TIMx CCMR1 and CCER registers */
  13681. TIMx->CCMR1 = tmpccmr1;
  13682. 8005762: 68fb ldr r3, [r7, #12]
  13683. 8005764: 693a ldr r2, [r7, #16]
  13684. 8005766: 619a str r2, [r3, #24]
  13685. TIMx->CCER = tmpccer;
  13686. 8005768: 68fb ldr r3, [r7, #12]
  13687. 800576a: 697a ldr r2, [r7, #20]
  13688. 800576c: 621a str r2, [r3, #32]
  13689. }
  13690. 800576e: bf00 nop
  13691. 8005770: 371c adds r7, #28
  13692. 8005772: 46bd mov sp, r7
  13693. 8005774: f85d 7b04 ldr.w r7, [sp], #4
  13694. 8005778: 4770 bx lr
  13695. 0800577a <TIM_TI2_ConfigInputStage>:
  13696. * @param TIM_ICFilter Specifies the Input Capture Filter.
  13697. * This parameter must be a value between 0x00 and 0x0F.
  13698. * @retval None
  13699. */
  13700. static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  13701. {
  13702. 800577a: b480 push {r7}
  13703. 800577c: b087 sub sp, #28
  13704. 800577e: af00 add r7, sp, #0
  13705. 8005780: 60f8 str r0, [r7, #12]
  13706. 8005782: 60b9 str r1, [r7, #8]
  13707. 8005784: 607a str r2, [r7, #4]
  13708. uint32_t tmpccmr1;
  13709. uint32_t tmpccer;
  13710. /* Disable the Channel 2: Reset the CC2E Bit */
  13711. TIMx->CCER &= ~TIM_CCER_CC2E;
  13712. 8005786: 68fb ldr r3, [r7, #12]
  13713. 8005788: 6a1b ldr r3, [r3, #32]
  13714. 800578a: f023 0210 bic.w r2, r3, #16
  13715. 800578e: 68fb ldr r3, [r7, #12]
  13716. 8005790: 621a str r2, [r3, #32]
  13717. tmpccmr1 = TIMx->CCMR1;
  13718. 8005792: 68fb ldr r3, [r7, #12]
  13719. 8005794: 699b ldr r3, [r3, #24]
  13720. 8005796: 617b str r3, [r7, #20]
  13721. tmpccer = TIMx->CCER;
  13722. 8005798: 68fb ldr r3, [r7, #12]
  13723. 800579a: 6a1b ldr r3, [r3, #32]
  13724. 800579c: 613b str r3, [r7, #16]
  13725. /* Set the filter */
  13726. tmpccmr1 &= ~TIM_CCMR1_IC2F;
  13727. 800579e: 697b ldr r3, [r7, #20]
  13728. 80057a0: f423 4370 bic.w r3, r3, #61440 ; 0xf000
  13729. 80057a4: 617b str r3, [r7, #20]
  13730. tmpccmr1 |= (TIM_ICFilter << 12U);
  13731. 80057a6: 687b ldr r3, [r7, #4]
  13732. 80057a8: 031b lsls r3, r3, #12
  13733. 80057aa: 697a ldr r2, [r7, #20]
  13734. 80057ac: 4313 orrs r3, r2
  13735. 80057ae: 617b str r3, [r7, #20]
  13736. /* Select the Polarity and set the CC2E Bit */
  13737. tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  13738. 80057b0: 693b ldr r3, [r7, #16]
  13739. 80057b2: f023 03a0 bic.w r3, r3, #160 ; 0xa0
  13740. 80057b6: 613b str r3, [r7, #16]
  13741. tmpccer |= (TIM_ICPolarity << 4U);
  13742. 80057b8: 68bb ldr r3, [r7, #8]
  13743. 80057ba: 011b lsls r3, r3, #4
  13744. 80057bc: 693a ldr r2, [r7, #16]
  13745. 80057be: 4313 orrs r3, r2
  13746. 80057c0: 613b str r3, [r7, #16]
  13747. /* Write to TIMx CCMR1 and CCER registers */
  13748. TIMx->CCMR1 = tmpccmr1 ;
  13749. 80057c2: 68fb ldr r3, [r7, #12]
  13750. 80057c4: 697a ldr r2, [r7, #20]
  13751. 80057c6: 619a str r2, [r3, #24]
  13752. TIMx->CCER = tmpccer;
  13753. 80057c8: 68fb ldr r3, [r7, #12]
  13754. 80057ca: 693a ldr r2, [r7, #16]
  13755. 80057cc: 621a str r2, [r3, #32]
  13756. }
  13757. 80057ce: bf00 nop
  13758. 80057d0: 371c adds r7, #28
  13759. 80057d2: 46bd mov sp, r7
  13760. 80057d4: f85d 7b04 ldr.w r7, [sp], #4
  13761. 80057d8: 4770 bx lr
  13762. ...
  13763. 080057dc <TIM_ITRx_SetConfig>:
  13764. * (*) Value not defined in all devices.
  13765. *
  13766. * @retval None
  13767. */
  13768. static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
  13769. {
  13770. 80057dc: b480 push {r7}
  13771. 80057de: b085 sub sp, #20
  13772. 80057e0: af00 add r7, sp, #0
  13773. 80057e2: 6078 str r0, [r7, #4]
  13774. 80057e4: 6039 str r1, [r7, #0]
  13775. uint32_t tmpsmcr;
  13776. /* Get the TIMx SMCR register value */
  13777. tmpsmcr = TIMx->SMCR;
  13778. 80057e6: 687b ldr r3, [r7, #4]
  13779. 80057e8: 689b ldr r3, [r3, #8]
  13780. 80057ea: 60fb str r3, [r7, #12]
  13781. /* Reset the TS Bits */
  13782. tmpsmcr &= ~TIM_SMCR_TS;
  13783. 80057ec: 68fa ldr r2, [r7, #12]
  13784. 80057ee: 4b09 ldr r3, [pc, #36] ; (8005814 <TIM_ITRx_SetConfig+0x38>)
  13785. 80057f0: 4013 ands r3, r2
  13786. 80057f2: 60fb str r3, [r7, #12]
  13787. /* Set the Input Trigger source and the slave mode*/
  13788. tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  13789. 80057f4: 683a ldr r2, [r7, #0]
  13790. 80057f6: 68fb ldr r3, [r7, #12]
  13791. 80057f8: 4313 orrs r3, r2
  13792. 80057fa: f043 0307 orr.w r3, r3, #7
  13793. 80057fe: 60fb str r3, [r7, #12]
  13794. /* Write to TIMx SMCR */
  13795. TIMx->SMCR = tmpsmcr;
  13796. 8005800: 687b ldr r3, [r7, #4]
  13797. 8005802: 68fa ldr r2, [r7, #12]
  13798. 8005804: 609a str r2, [r3, #8]
  13799. }
  13800. 8005806: bf00 nop
  13801. 8005808: 3714 adds r7, #20
  13802. 800580a: 46bd mov sp, r7
  13803. 800580c: f85d 7b04 ldr.w r7, [sp], #4
  13804. 8005810: 4770 bx lr
  13805. 8005812: bf00 nop
  13806. 8005814: ffcfff8f .word 0xffcfff8f
  13807. 08005818 <TIM_ETR_SetConfig>:
  13808. * This parameter must be a value between 0x00 and 0x0F
  13809. * @retval None
  13810. */
  13811. void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
  13812. uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
  13813. {
  13814. 8005818: b480 push {r7}
  13815. 800581a: b087 sub sp, #28
  13816. 800581c: af00 add r7, sp, #0
  13817. 800581e: 60f8 str r0, [r7, #12]
  13818. 8005820: 60b9 str r1, [r7, #8]
  13819. 8005822: 607a str r2, [r7, #4]
  13820. 8005824: 603b str r3, [r7, #0]
  13821. uint32_t tmpsmcr;
  13822. tmpsmcr = TIMx->SMCR;
  13823. 8005826: 68fb ldr r3, [r7, #12]
  13824. 8005828: 689b ldr r3, [r3, #8]
  13825. 800582a: 617b str r3, [r7, #20]
  13826. /* Reset the ETR Bits */
  13827. tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  13828. 800582c: 697b ldr r3, [r7, #20]
  13829. 800582e: f423 437f bic.w r3, r3, #65280 ; 0xff00
  13830. 8005832: 617b str r3, [r7, #20]
  13831. /* Set the Prescaler, the Filter value and the Polarity */
  13832. tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  13833. 8005834: 683b ldr r3, [r7, #0]
  13834. 8005836: 021a lsls r2, r3, #8
  13835. 8005838: 687b ldr r3, [r7, #4]
  13836. 800583a: 431a orrs r2, r3
  13837. 800583c: 68bb ldr r3, [r7, #8]
  13838. 800583e: 4313 orrs r3, r2
  13839. 8005840: 697a ldr r2, [r7, #20]
  13840. 8005842: 4313 orrs r3, r2
  13841. 8005844: 617b str r3, [r7, #20]
  13842. /* Write to TIMx SMCR */
  13843. TIMx->SMCR = tmpsmcr;
  13844. 8005846: 68fb ldr r3, [r7, #12]
  13845. 8005848: 697a ldr r2, [r7, #20]
  13846. 800584a: 609a str r2, [r3, #8]
  13847. }
  13848. 800584c: bf00 nop
  13849. 800584e: 371c adds r7, #28
  13850. 8005850: 46bd mov sp, r7
  13851. 8005852: f85d 7b04 ldr.w r7, [sp], #4
  13852. 8005856: 4770 bx lr
  13853. 08005858 <HAL_TIMEx_MasterConfigSynchronization>:
  13854. * mode.
  13855. * @retval HAL status
  13856. */
  13857. HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
  13858. TIM_MasterConfigTypeDef *sMasterConfig)
  13859. {
  13860. 8005858: b480 push {r7}
  13861. 800585a: b085 sub sp, #20
  13862. 800585c: af00 add r7, sp, #0
  13863. 800585e: 6078 str r0, [r7, #4]
  13864. 8005860: 6039 str r1, [r7, #0]
  13865. assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  13866. assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  13867. assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
  13868. /* Check input state */
  13869. __HAL_LOCK(htim);
  13870. 8005862: 687b ldr r3, [r7, #4]
  13871. 8005864: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
  13872. 8005868: 2b01 cmp r3, #1
  13873. 800586a: d101 bne.n 8005870 <HAL_TIMEx_MasterConfigSynchronization+0x18>
  13874. 800586c: 2302 movs r3, #2
  13875. 800586e: e077 b.n 8005960 <HAL_TIMEx_MasterConfigSynchronization+0x108>
  13876. 8005870: 687b ldr r3, [r7, #4]
  13877. 8005872: 2201 movs r2, #1
  13878. 8005874: f883 203c strb.w r2, [r3, #60] ; 0x3c
  13879. /* Change the handler state */
  13880. htim->State = HAL_TIM_STATE_BUSY;
  13881. 8005878: 687b ldr r3, [r7, #4]
  13882. 800587a: 2202 movs r2, #2
  13883. 800587c: f883 203d strb.w r2, [r3, #61] ; 0x3d
  13884. /* Get the TIMx CR2 register value */
  13885. tmpcr2 = htim->Instance->CR2;
  13886. 8005880: 687b ldr r3, [r7, #4]
  13887. 8005882: 681b ldr r3, [r3, #0]
  13888. 8005884: 685b ldr r3, [r3, #4]
  13889. 8005886: 60fb str r3, [r7, #12]
  13890. /* Get the TIMx SMCR register value */
  13891. tmpsmcr = htim->Instance->SMCR;
  13892. 8005888: 687b ldr r3, [r7, #4]
  13893. 800588a: 681b ldr r3, [r3, #0]
  13894. 800588c: 689b ldr r3, [r3, #8]
  13895. 800588e: 60bb str r3, [r7, #8]
  13896. /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
  13897. if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
  13898. 8005890: 687b ldr r3, [r7, #4]
  13899. 8005892: 681b ldr r3, [r3, #0]
  13900. 8005894: 4a35 ldr r2, [pc, #212] ; (800596c <HAL_TIMEx_MasterConfigSynchronization+0x114>)
  13901. 8005896: 4293 cmp r3, r2
  13902. 8005898: d004 beq.n 80058a4 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
  13903. 800589a: 687b ldr r3, [r7, #4]
  13904. 800589c: 681b ldr r3, [r3, #0]
  13905. 800589e: 4a34 ldr r2, [pc, #208] ; (8005970 <HAL_TIMEx_MasterConfigSynchronization+0x118>)
  13906. 80058a0: 4293 cmp r3, r2
  13907. 80058a2: d108 bne.n 80058b6 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
  13908. {
  13909. /* Check the parameters */
  13910. assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
  13911. /* Clear the MMS2 bits */
  13912. tmpcr2 &= ~TIM_CR2_MMS2;
  13913. 80058a4: 68fb ldr r3, [r7, #12]
  13914. 80058a6: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
  13915. 80058aa: 60fb str r3, [r7, #12]
  13916. /* Select the TRGO2 source*/
  13917. tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
  13918. 80058ac: 683b ldr r3, [r7, #0]
  13919. 80058ae: 685b ldr r3, [r3, #4]
  13920. 80058b0: 68fa ldr r2, [r7, #12]
  13921. 80058b2: 4313 orrs r3, r2
  13922. 80058b4: 60fb str r3, [r7, #12]
  13923. }
  13924. /* Reset the MMS Bits */
  13925. tmpcr2 &= ~TIM_CR2_MMS;
  13926. 80058b6: 68fb ldr r3, [r7, #12]
  13927. 80058b8: f023 0370 bic.w r3, r3, #112 ; 0x70
  13928. 80058bc: 60fb str r3, [r7, #12]
  13929. /* Select the TRGO source */
  13930. tmpcr2 |= sMasterConfig->MasterOutputTrigger;
  13931. 80058be: 683b ldr r3, [r7, #0]
  13932. 80058c0: 681b ldr r3, [r3, #0]
  13933. 80058c2: 68fa ldr r2, [r7, #12]
  13934. 80058c4: 4313 orrs r3, r2
  13935. 80058c6: 60fb str r3, [r7, #12]
  13936. /* Update TIMx CR2 */
  13937. htim->Instance->CR2 = tmpcr2;
  13938. 80058c8: 687b ldr r3, [r7, #4]
  13939. 80058ca: 681b ldr r3, [r3, #0]
  13940. 80058cc: 68fa ldr r2, [r7, #12]
  13941. 80058ce: 605a str r2, [r3, #4]
  13942. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  13943. 80058d0: 687b ldr r3, [r7, #4]
  13944. 80058d2: 681b ldr r3, [r3, #0]
  13945. 80058d4: 4a25 ldr r2, [pc, #148] ; (800596c <HAL_TIMEx_MasterConfigSynchronization+0x114>)
  13946. 80058d6: 4293 cmp r3, r2
  13947. 80058d8: d02c beq.n 8005934 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
  13948. 80058da: 687b ldr r3, [r7, #4]
  13949. 80058dc: 681b ldr r3, [r3, #0]
  13950. 80058de: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
  13951. 80058e2: d027 beq.n 8005934 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
  13952. 80058e4: 687b ldr r3, [r7, #4]
  13953. 80058e6: 681b ldr r3, [r3, #0]
  13954. 80058e8: 4a22 ldr r2, [pc, #136] ; (8005974 <HAL_TIMEx_MasterConfigSynchronization+0x11c>)
  13955. 80058ea: 4293 cmp r3, r2
  13956. 80058ec: d022 beq.n 8005934 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
  13957. 80058ee: 687b ldr r3, [r7, #4]
  13958. 80058f0: 681b ldr r3, [r3, #0]
  13959. 80058f2: 4a21 ldr r2, [pc, #132] ; (8005978 <HAL_TIMEx_MasterConfigSynchronization+0x120>)
  13960. 80058f4: 4293 cmp r3, r2
  13961. 80058f6: d01d beq.n 8005934 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
  13962. 80058f8: 687b ldr r3, [r7, #4]
  13963. 80058fa: 681b ldr r3, [r3, #0]
  13964. 80058fc: 4a1f ldr r2, [pc, #124] ; (800597c <HAL_TIMEx_MasterConfigSynchronization+0x124>)
  13965. 80058fe: 4293 cmp r3, r2
  13966. 8005900: d018 beq.n 8005934 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
  13967. 8005902: 687b ldr r3, [r7, #4]
  13968. 8005904: 681b ldr r3, [r3, #0]
  13969. 8005906: 4a1a ldr r2, [pc, #104] ; (8005970 <HAL_TIMEx_MasterConfigSynchronization+0x118>)
  13970. 8005908: 4293 cmp r3, r2
  13971. 800590a: d013 beq.n 8005934 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
  13972. 800590c: 687b ldr r3, [r7, #4]
  13973. 800590e: 681b ldr r3, [r3, #0]
  13974. 8005910: 4a1b ldr r2, [pc, #108] ; (8005980 <HAL_TIMEx_MasterConfigSynchronization+0x128>)
  13975. 8005912: 4293 cmp r3, r2
  13976. 8005914: d00e beq.n 8005934 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
  13977. 8005916: 687b ldr r3, [r7, #4]
  13978. 8005918: 681b ldr r3, [r3, #0]
  13979. 800591a: 4a1a ldr r2, [pc, #104] ; (8005984 <HAL_TIMEx_MasterConfigSynchronization+0x12c>)
  13980. 800591c: 4293 cmp r3, r2
  13981. 800591e: d009 beq.n 8005934 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
  13982. 8005920: 687b ldr r3, [r7, #4]
  13983. 8005922: 681b ldr r3, [r3, #0]
  13984. 8005924: 4a18 ldr r2, [pc, #96] ; (8005988 <HAL_TIMEx_MasterConfigSynchronization+0x130>)
  13985. 8005926: 4293 cmp r3, r2
  13986. 8005928: d004 beq.n 8005934 <HAL_TIMEx_MasterConfigSynchronization+0xdc>
  13987. 800592a: 687b ldr r3, [r7, #4]
  13988. 800592c: 681b ldr r3, [r3, #0]
  13989. 800592e: 4a17 ldr r2, [pc, #92] ; (800598c <HAL_TIMEx_MasterConfigSynchronization+0x134>)
  13990. 8005930: 4293 cmp r3, r2
  13991. 8005932: d10c bne.n 800594e <HAL_TIMEx_MasterConfigSynchronization+0xf6>
  13992. {
  13993. /* Reset the MSM Bit */
  13994. tmpsmcr &= ~TIM_SMCR_MSM;
  13995. 8005934: 68bb ldr r3, [r7, #8]
  13996. 8005936: f023 0380 bic.w r3, r3, #128 ; 0x80
  13997. 800593a: 60bb str r3, [r7, #8]
  13998. /* Set master mode */
  13999. tmpsmcr |= sMasterConfig->MasterSlaveMode;
  14000. 800593c: 683b ldr r3, [r7, #0]
  14001. 800593e: 689b ldr r3, [r3, #8]
  14002. 8005940: 68ba ldr r2, [r7, #8]
  14003. 8005942: 4313 orrs r3, r2
  14004. 8005944: 60bb str r3, [r7, #8]
  14005. /* Update TIMx SMCR */
  14006. htim->Instance->SMCR = tmpsmcr;
  14007. 8005946: 687b ldr r3, [r7, #4]
  14008. 8005948: 681b ldr r3, [r3, #0]
  14009. 800594a: 68ba ldr r2, [r7, #8]
  14010. 800594c: 609a str r2, [r3, #8]
  14011. }
  14012. /* Change the htim state */
  14013. htim->State = HAL_TIM_STATE_READY;
  14014. 800594e: 687b ldr r3, [r7, #4]
  14015. 8005950: 2201 movs r2, #1
  14016. 8005952: f883 203d strb.w r2, [r3, #61] ; 0x3d
  14017. __HAL_UNLOCK(htim);
  14018. 8005956: 687b ldr r3, [r7, #4]
  14019. 8005958: 2200 movs r2, #0
  14020. 800595a: f883 203c strb.w r2, [r3, #60] ; 0x3c
  14021. return HAL_OK;
  14022. 800595e: 2300 movs r3, #0
  14023. }
  14024. 8005960: 4618 mov r0, r3
  14025. 8005962: 3714 adds r7, #20
  14026. 8005964: 46bd mov sp, r7
  14027. 8005966: f85d 7b04 ldr.w r7, [sp], #4
  14028. 800596a: 4770 bx lr
  14029. 800596c: 40010000 .word 0x40010000
  14030. 8005970: 40010400 .word 0x40010400
  14031. 8005974: 40000400 .word 0x40000400
  14032. 8005978: 40000800 .word 0x40000800
  14033. 800597c: 40000c00 .word 0x40000c00
  14034. 8005980: 40001800 .word 0x40001800
  14035. 8005984: 40014000 .word 0x40014000
  14036. 8005988: 4000e000 .word 0x4000e000
  14037. 800598c: 4000e400 .word 0x4000e400
  14038. 08005990 <HAL_TIMEx_CommutCallback>:
  14039. * @brief Hall commutation changed callback in non-blocking mode
  14040. * @param htim TIM handle
  14041. * @retval None
  14042. */
  14043. __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
  14044. {
  14045. 8005990: b480 push {r7}
  14046. 8005992: b083 sub sp, #12
  14047. 8005994: af00 add r7, sp, #0
  14048. 8005996: 6078 str r0, [r7, #4]
  14049. UNUSED(htim);
  14050. /* NOTE : This function should not be modified, when the callback is needed,
  14051. the HAL_TIMEx_CommutCallback could be implemented in the user file
  14052. */
  14053. }
  14054. 8005998: bf00 nop
  14055. 800599a: 370c adds r7, #12
  14056. 800599c: 46bd mov sp, r7
  14057. 800599e: f85d 7b04 ldr.w r7, [sp], #4
  14058. 80059a2: 4770 bx lr
  14059. 080059a4 <HAL_TIMEx_BreakCallback>:
  14060. * @brief Hall Break detection callback in non-blocking mode
  14061. * @param htim TIM handle
  14062. * @retval None
  14063. */
  14064. __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
  14065. {
  14066. 80059a4: b480 push {r7}
  14067. 80059a6: b083 sub sp, #12
  14068. 80059a8: af00 add r7, sp, #0
  14069. 80059aa: 6078 str r0, [r7, #4]
  14070. UNUSED(htim);
  14071. /* NOTE : This function should not be modified, when the callback is needed,
  14072. the HAL_TIMEx_BreakCallback could be implemented in the user file
  14073. */
  14074. }
  14075. 80059ac: bf00 nop
  14076. 80059ae: 370c adds r7, #12
  14077. 80059b0: 46bd mov sp, r7
  14078. 80059b2: f85d 7b04 ldr.w r7, [sp], #4
  14079. 80059b6: 4770 bx lr
  14080. 080059b8 <HAL_TIMEx_Break2Callback>:
  14081. * @brief Hall Break2 detection callback in non blocking mode
  14082. * @param htim: TIM handle
  14083. * @retval None
  14084. */
  14085. __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
  14086. {
  14087. 80059b8: b480 push {r7}
  14088. 80059ba: b083 sub sp, #12
  14089. 80059bc: af00 add r7, sp, #0
  14090. 80059be: 6078 str r0, [r7, #4]
  14091. UNUSED(htim);
  14092. /* NOTE : This function Should not be modified, when the callback is needed,
  14093. the HAL_TIMEx_Break2Callback could be implemented in the user file
  14094. */
  14095. }
  14096. 80059c0: bf00 nop
  14097. 80059c2: 370c adds r7, #12
  14098. 80059c4: 46bd mov sp, r7
  14099. 80059c6: f85d 7b04 ldr.w r7, [sp], #4
  14100. 80059ca: 4770 bx lr
  14101. 080059cc <LL_GPIO_SetPinMode>:
  14102. * @arg @ref LL_GPIO_MODE_ALTERNATE
  14103. * @arg @ref LL_GPIO_MODE_ANALOG
  14104. * @retval None
  14105. */
  14106. __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
  14107. {
  14108. 80059cc: b480 push {r7}
  14109. 80059ce: b085 sub sp, #20
  14110. 80059d0: af00 add r7, sp, #0
  14111. 80059d2: 60f8 str r0, [r7, #12]
  14112. 80059d4: 60b9 str r1, [r7, #8]
  14113. 80059d6: 607a str r2, [r7, #4]
  14114. MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
  14115. 80059d8: 68fb ldr r3, [r7, #12]
  14116. 80059da: 6819 ldr r1, [r3, #0]
  14117. 80059dc: 68bb ldr r3, [r7, #8]
  14118. 80059de: fb03 f203 mul.w r2, r3, r3
  14119. 80059e2: 4613 mov r3, r2
  14120. 80059e4: 005b lsls r3, r3, #1
  14121. 80059e6: 4413 add r3, r2
  14122. 80059e8: 43db mvns r3, r3
  14123. 80059ea: ea01 0203 and.w r2, r1, r3
  14124. 80059ee: 68bb ldr r3, [r7, #8]
  14125. 80059f0: fb03 f303 mul.w r3, r3, r3
  14126. 80059f4: 6879 ldr r1, [r7, #4]
  14127. 80059f6: fb01 f303 mul.w r3, r1, r3
  14128. 80059fa: 431a orrs r2, r3
  14129. 80059fc: 68fb ldr r3, [r7, #12]
  14130. 80059fe: 601a str r2, [r3, #0]
  14131. }
  14132. 8005a00: bf00 nop
  14133. 8005a02: 3714 adds r7, #20
  14134. 8005a04: 46bd mov sp, r7
  14135. 8005a06: f85d 7b04 ldr.w r7, [sp], #4
  14136. 8005a0a: 4770 bx lr
  14137. 08005a0c <LL_GPIO_SetPinOutputType>:
  14138. * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
  14139. * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
  14140. * @retval None
  14141. */
  14142. __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
  14143. {
  14144. 8005a0c: b480 push {r7}
  14145. 8005a0e: b085 sub sp, #20
  14146. 8005a10: af00 add r7, sp, #0
  14147. 8005a12: 60f8 str r0, [r7, #12]
  14148. 8005a14: 60b9 str r1, [r7, #8]
  14149. 8005a16: 607a str r2, [r7, #4]
  14150. MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
  14151. 8005a18: 68fb ldr r3, [r7, #12]
  14152. 8005a1a: 685a ldr r2, [r3, #4]
  14153. 8005a1c: 68bb ldr r3, [r7, #8]
  14154. 8005a1e: 43db mvns r3, r3
  14155. 8005a20: 401a ands r2, r3
  14156. 8005a22: 68bb ldr r3, [r7, #8]
  14157. 8005a24: 6879 ldr r1, [r7, #4]
  14158. 8005a26: fb01 f303 mul.w r3, r1, r3
  14159. 8005a2a: 431a orrs r2, r3
  14160. 8005a2c: 68fb ldr r3, [r7, #12]
  14161. 8005a2e: 605a str r2, [r3, #4]
  14162. }
  14163. 8005a30: bf00 nop
  14164. 8005a32: 3714 adds r7, #20
  14165. 8005a34: 46bd mov sp, r7
  14166. 8005a36: f85d 7b04 ldr.w r7, [sp], #4
  14167. 8005a3a: 4770 bx lr
  14168. 08005a3c <LL_GPIO_SetPinSpeed>:
  14169. * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
  14170. * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
  14171. * @retval None
  14172. */
  14173. __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
  14174. {
  14175. 8005a3c: b480 push {r7}
  14176. 8005a3e: b085 sub sp, #20
  14177. 8005a40: af00 add r7, sp, #0
  14178. 8005a42: 60f8 str r0, [r7, #12]
  14179. 8005a44: 60b9 str r1, [r7, #8]
  14180. 8005a46: 607a str r2, [r7, #4]
  14181. MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed));
  14182. 8005a48: 68fb ldr r3, [r7, #12]
  14183. 8005a4a: 6899 ldr r1, [r3, #8]
  14184. 8005a4c: 68bb ldr r3, [r7, #8]
  14185. 8005a4e: fb03 f203 mul.w r2, r3, r3
  14186. 8005a52: 4613 mov r3, r2
  14187. 8005a54: 005b lsls r3, r3, #1
  14188. 8005a56: 4413 add r3, r2
  14189. 8005a58: 43db mvns r3, r3
  14190. 8005a5a: ea01 0203 and.w r2, r1, r3
  14191. 8005a5e: 68bb ldr r3, [r7, #8]
  14192. 8005a60: fb03 f303 mul.w r3, r3, r3
  14193. 8005a64: 6879 ldr r1, [r7, #4]
  14194. 8005a66: fb01 f303 mul.w r3, r1, r3
  14195. 8005a6a: 431a orrs r2, r3
  14196. 8005a6c: 68fb ldr r3, [r7, #12]
  14197. 8005a6e: 609a str r2, [r3, #8]
  14198. }
  14199. 8005a70: bf00 nop
  14200. 8005a72: 3714 adds r7, #20
  14201. 8005a74: 46bd mov sp, r7
  14202. 8005a76: f85d 7b04 ldr.w r7, [sp], #4
  14203. 8005a7a: 4770 bx lr
  14204. 08005a7c <LL_GPIO_SetPinPull>:
  14205. * @arg @ref LL_GPIO_PULL_UP
  14206. * @arg @ref LL_GPIO_PULL_DOWN
  14207. * @retval None
  14208. */
  14209. __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
  14210. {
  14211. 8005a7c: b480 push {r7}
  14212. 8005a7e: b085 sub sp, #20
  14213. 8005a80: af00 add r7, sp, #0
  14214. 8005a82: 60f8 str r0, [r7, #12]
  14215. 8005a84: 60b9 str r1, [r7, #8]
  14216. 8005a86: 607a str r2, [r7, #4]
  14217. MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
  14218. 8005a88: 68fb ldr r3, [r7, #12]
  14219. 8005a8a: 68d9 ldr r1, [r3, #12]
  14220. 8005a8c: 68bb ldr r3, [r7, #8]
  14221. 8005a8e: fb03 f203 mul.w r2, r3, r3
  14222. 8005a92: 4613 mov r3, r2
  14223. 8005a94: 005b lsls r3, r3, #1
  14224. 8005a96: 4413 add r3, r2
  14225. 8005a98: 43db mvns r3, r3
  14226. 8005a9a: ea01 0203 and.w r2, r1, r3
  14227. 8005a9e: 68bb ldr r3, [r7, #8]
  14228. 8005aa0: fb03 f303 mul.w r3, r3, r3
  14229. 8005aa4: 6879 ldr r1, [r7, #4]
  14230. 8005aa6: fb01 f303 mul.w r3, r1, r3
  14231. 8005aaa: 431a orrs r2, r3
  14232. 8005aac: 68fb ldr r3, [r7, #12]
  14233. 8005aae: 60da str r2, [r3, #12]
  14234. }
  14235. 8005ab0: bf00 nop
  14236. 8005ab2: 3714 adds r7, #20
  14237. 8005ab4: 46bd mov sp, r7
  14238. 8005ab6: f85d 7b04 ldr.w r7, [sp], #4
  14239. 8005aba: 4770 bx lr
  14240. 08005abc <LL_GPIO_SetAFPin_0_7>:
  14241. * @arg @ref LL_GPIO_AF_14
  14242. * @arg @ref LL_GPIO_AF_15
  14243. * @retval None
  14244. */
  14245. __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
  14246. {
  14247. 8005abc: b480 push {r7}
  14248. 8005abe: b085 sub sp, #20
  14249. 8005ac0: af00 add r7, sp, #0
  14250. 8005ac2: 60f8 str r0, [r7, #12]
  14251. 8005ac4: 60b9 str r1, [r7, #8]
  14252. 8005ac6: 607a str r2, [r7, #4]
  14253. MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
  14254. 8005ac8: 68fb ldr r3, [r7, #12]
  14255. 8005aca: 6a19 ldr r1, [r3, #32]
  14256. 8005acc: 68bb ldr r3, [r7, #8]
  14257. 8005ace: fb03 f303 mul.w r3, r3, r3
  14258. 8005ad2: 68ba ldr r2, [r7, #8]
  14259. 8005ad4: fb02 f303 mul.w r3, r2, r3
  14260. 8005ad8: 68ba ldr r2, [r7, #8]
  14261. 8005ada: fb02 f203 mul.w r2, r2, r3
  14262. 8005ade: 4613 mov r3, r2
  14263. 8005ae0: 011b lsls r3, r3, #4
  14264. 8005ae2: 1a9b subs r3, r3, r2
  14265. 8005ae4: 43db mvns r3, r3
  14266. 8005ae6: ea01 0203 and.w r2, r1, r3
  14267. 8005aea: 68bb ldr r3, [r7, #8]
  14268. 8005aec: fb03 f303 mul.w r3, r3, r3
  14269. 8005af0: 68b9 ldr r1, [r7, #8]
  14270. 8005af2: fb01 f303 mul.w r3, r1, r3
  14271. 8005af6: 68b9 ldr r1, [r7, #8]
  14272. 8005af8: fb01 f303 mul.w r3, r1, r3
  14273. 8005afc: 6879 ldr r1, [r7, #4]
  14274. 8005afe: fb01 f303 mul.w r3, r1, r3
  14275. 8005b02: 431a orrs r2, r3
  14276. 8005b04: 68fb ldr r3, [r7, #12]
  14277. 8005b06: 621a str r2, [r3, #32]
  14278. ((((Pin * Pin) * Pin) * Pin) * Alternate));
  14279. }
  14280. 8005b08: bf00 nop
  14281. 8005b0a: 3714 adds r7, #20
  14282. 8005b0c: 46bd mov sp, r7
  14283. 8005b0e: f85d 7b04 ldr.w r7, [sp], #4
  14284. 8005b12: 4770 bx lr
  14285. 08005b14 <LL_GPIO_SetAFPin_8_15>:
  14286. * @arg @ref LL_GPIO_AF_14
  14287. * @arg @ref LL_GPIO_AF_15
  14288. * @retval None
  14289. */
  14290. __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
  14291. {
  14292. 8005b14: b480 push {r7}
  14293. 8005b16: b085 sub sp, #20
  14294. 8005b18: af00 add r7, sp, #0
  14295. 8005b1a: 60f8 str r0, [r7, #12]
  14296. 8005b1c: 60b9 str r1, [r7, #8]
  14297. 8005b1e: 607a str r2, [r7, #4]
  14298. MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
  14299. 8005b20: 68fb ldr r3, [r7, #12]
  14300. 8005b22: 6a59 ldr r1, [r3, #36] ; 0x24
  14301. 8005b24: 68bb ldr r3, [r7, #8]
  14302. 8005b26: 0a1b lsrs r3, r3, #8
  14303. 8005b28: 68ba ldr r2, [r7, #8]
  14304. 8005b2a: 0a12 lsrs r2, r2, #8
  14305. 8005b2c: fb02 f303 mul.w r3, r2, r3
  14306. 8005b30: 68ba ldr r2, [r7, #8]
  14307. 8005b32: 0a12 lsrs r2, r2, #8
  14308. 8005b34: fb02 f303 mul.w r3, r2, r3
  14309. 8005b38: 68ba ldr r2, [r7, #8]
  14310. 8005b3a: 0a12 lsrs r2, r2, #8
  14311. 8005b3c: fb02 f203 mul.w r2, r2, r3
  14312. 8005b40: 4613 mov r3, r2
  14313. 8005b42: 011b lsls r3, r3, #4
  14314. 8005b44: 1a9b subs r3, r3, r2
  14315. 8005b46: 43db mvns r3, r3
  14316. 8005b48: ea01 0203 and.w r2, r1, r3
  14317. 8005b4c: 68bb ldr r3, [r7, #8]
  14318. 8005b4e: 0a1b lsrs r3, r3, #8
  14319. 8005b50: 68b9 ldr r1, [r7, #8]
  14320. 8005b52: 0a09 lsrs r1, r1, #8
  14321. 8005b54: fb01 f303 mul.w r3, r1, r3
  14322. 8005b58: 68b9 ldr r1, [r7, #8]
  14323. 8005b5a: 0a09 lsrs r1, r1, #8
  14324. 8005b5c: fb01 f303 mul.w r3, r1, r3
  14325. 8005b60: 68b9 ldr r1, [r7, #8]
  14326. 8005b62: 0a09 lsrs r1, r1, #8
  14327. 8005b64: fb01 f303 mul.w r3, r1, r3
  14328. 8005b68: 6879 ldr r1, [r7, #4]
  14329. 8005b6a: fb01 f303 mul.w r3, r1, r3
  14330. 8005b6e: 431a orrs r2, r3
  14331. 8005b70: 68fb ldr r3, [r7, #12]
  14332. 8005b72: 625a str r2, [r3, #36] ; 0x24
  14333. (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
  14334. }
  14335. 8005b74: bf00 nop
  14336. 8005b76: 3714 adds r7, #20
  14337. 8005b78: 46bd mov sp, r7
  14338. 8005b7a: f85d 7b04 ldr.w r7, [sp], #4
  14339. 8005b7e: 4770 bx lr
  14340. 08005b80 <LL_GPIO_Init>:
  14341. * @retval An ErrorStatus enumeration value:
  14342. * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
  14343. * - ERROR: Not applicable
  14344. */
  14345. ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
  14346. {
  14347. 8005b80: b580 push {r7, lr}
  14348. 8005b82: b088 sub sp, #32
  14349. 8005b84: af00 add r7, sp, #0
  14350. 8005b86: 6078 str r0, [r7, #4]
  14351. 8005b88: 6039 str r1, [r7, #0]
  14352. assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
  14353. assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
  14354. /* ------------------------- Configure the port pins ---------------- */
  14355. /* Initialize pinpos on first pin set */
  14356. pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
  14357. 8005b8a: 683b ldr r3, [r7, #0]
  14358. 8005b8c: 681b ldr r3, [r3, #0]
  14359. 8005b8e: 613b str r3, [r7, #16]
  14360. uint32_t result;
  14361. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  14362. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  14363. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  14364. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  14365. 8005b90: 693b ldr r3, [r7, #16]
  14366. 8005b92: fa93 f3a3 rbit r3, r3
  14367. 8005b96: 60fb str r3, [r7, #12]
  14368. result |= value & 1U;
  14369. s--;
  14370. }
  14371. result <<= s; /* shift when v's highest bits are zero */
  14372. #endif
  14373. return result;
  14374. 8005b98: 68fb ldr r3, [r7, #12]
  14375. 8005b9a: 617b str r3, [r7, #20]
  14376. optimisations using the logic "value was passed to __builtin_clz, so it
  14377. is non-zero".
  14378. ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
  14379. single CLZ instruction.
  14380. */
  14381. if (value == 0U)
  14382. 8005b9c: 697b ldr r3, [r7, #20]
  14383. 8005b9e: 2b00 cmp r3, #0
  14384. 8005ba0: d101 bne.n 8005ba6 <LL_GPIO_Init+0x26>
  14385. {
  14386. return 32U;
  14387. 8005ba2: 2320 movs r3, #32
  14388. 8005ba4: e003 b.n 8005bae <LL_GPIO_Init+0x2e>
  14389. }
  14390. return __builtin_clz(value);
  14391. 8005ba6: 697b ldr r3, [r7, #20]
  14392. 8005ba8: fab3 f383 clz r3, r3
  14393. 8005bac: b2db uxtb r3, r3
  14394. 8005bae: 61fb str r3, [r7, #28]
  14395. /* Configure the port pins */
  14396. while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
  14397. 8005bb0: e048 b.n 8005c44 <LL_GPIO_Init+0xc4>
  14398. {
  14399. /* Get current io position */
  14400. currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos);
  14401. 8005bb2: 683b ldr r3, [r7, #0]
  14402. 8005bb4: 681a ldr r2, [r3, #0]
  14403. 8005bb6: 2101 movs r1, #1
  14404. 8005bb8: 69fb ldr r3, [r7, #28]
  14405. 8005bba: fa01 f303 lsl.w r3, r1, r3
  14406. 8005bbe: 4013 ands r3, r2
  14407. 8005bc0: 61bb str r3, [r7, #24]
  14408. if (currentpin != 0x00000000U)
  14409. 8005bc2: 69bb ldr r3, [r7, #24]
  14410. 8005bc4: 2b00 cmp r3, #0
  14411. 8005bc6: d03a beq.n 8005c3e <LL_GPIO_Init+0xbe>
  14412. {
  14413. if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
  14414. 8005bc8: 683b ldr r3, [r7, #0]
  14415. 8005bca: 685b ldr r3, [r3, #4]
  14416. 8005bcc: 2b01 cmp r3, #1
  14417. 8005bce: d003 beq.n 8005bd8 <LL_GPIO_Init+0x58>
  14418. 8005bd0: 683b ldr r3, [r7, #0]
  14419. 8005bd2: 685b ldr r3, [r3, #4]
  14420. 8005bd4: 2b02 cmp r3, #2
  14421. 8005bd6: d10e bne.n 8005bf6 <LL_GPIO_Init+0x76>
  14422. {
  14423. /* Check Speed mode parameters */
  14424. assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
  14425. /* Speed mode configuration */
  14426. LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
  14427. 8005bd8: 683b ldr r3, [r7, #0]
  14428. 8005bda: 689b ldr r3, [r3, #8]
  14429. 8005bdc: 461a mov r2, r3
  14430. 8005bde: 69b9 ldr r1, [r7, #24]
  14431. 8005be0: 6878 ldr r0, [r7, #4]
  14432. 8005be2: f7ff ff2b bl 8005a3c <LL_GPIO_SetPinSpeed>
  14433. /* Check Output mode parameters */
  14434. assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
  14435. /* Output mode configuration*/
  14436. LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
  14437. 8005be6: 683b ldr r3, [r7, #0]
  14438. 8005be8: 6819 ldr r1, [r3, #0]
  14439. 8005bea: 683b ldr r3, [r7, #0]
  14440. 8005bec: 68db ldr r3, [r3, #12]
  14441. 8005bee: 461a mov r2, r3
  14442. 8005bf0: 6878 ldr r0, [r7, #4]
  14443. 8005bf2: f7ff ff0b bl 8005a0c <LL_GPIO_SetPinOutputType>
  14444. }
  14445. /* Pull-up Pull down resistor configuration*/
  14446. LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
  14447. 8005bf6: 683b ldr r3, [r7, #0]
  14448. 8005bf8: 691b ldr r3, [r3, #16]
  14449. 8005bfa: 461a mov r2, r3
  14450. 8005bfc: 69b9 ldr r1, [r7, #24]
  14451. 8005bfe: 6878 ldr r0, [r7, #4]
  14452. 8005c00: f7ff ff3c bl 8005a7c <LL_GPIO_SetPinPull>
  14453. if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
  14454. 8005c04: 683b ldr r3, [r7, #0]
  14455. 8005c06: 685b ldr r3, [r3, #4]
  14456. 8005c08: 2b02 cmp r3, #2
  14457. 8005c0a: d111 bne.n 8005c30 <LL_GPIO_Init+0xb0>
  14458. {
  14459. /* Check Alternate parameter */
  14460. assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
  14461. /* Alternate function configuration */
  14462. if (currentpin < LL_GPIO_PIN_8)
  14463. 8005c0c: 69bb ldr r3, [r7, #24]
  14464. 8005c0e: 2bff cmp r3, #255 ; 0xff
  14465. 8005c10: d807 bhi.n 8005c22 <LL_GPIO_Init+0xa2>
  14466. {
  14467. LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
  14468. 8005c12: 683b ldr r3, [r7, #0]
  14469. 8005c14: 695b ldr r3, [r3, #20]
  14470. 8005c16: 461a mov r2, r3
  14471. 8005c18: 69b9 ldr r1, [r7, #24]
  14472. 8005c1a: 6878 ldr r0, [r7, #4]
  14473. 8005c1c: f7ff ff4e bl 8005abc <LL_GPIO_SetAFPin_0_7>
  14474. 8005c20: e006 b.n 8005c30 <LL_GPIO_Init+0xb0>
  14475. }
  14476. else
  14477. {
  14478. LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
  14479. 8005c22: 683b ldr r3, [r7, #0]
  14480. 8005c24: 695b ldr r3, [r3, #20]
  14481. 8005c26: 461a mov r2, r3
  14482. 8005c28: 69b9 ldr r1, [r7, #24]
  14483. 8005c2a: 6878 ldr r0, [r7, #4]
  14484. 8005c2c: f7ff ff72 bl 8005b14 <LL_GPIO_SetAFPin_8_15>
  14485. }
  14486. }
  14487. /* Pin Mode configuration */
  14488. LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
  14489. 8005c30: 683b ldr r3, [r7, #0]
  14490. 8005c32: 685b ldr r3, [r3, #4]
  14491. 8005c34: 461a mov r2, r3
  14492. 8005c36: 69b9 ldr r1, [r7, #24]
  14493. 8005c38: 6878 ldr r0, [r7, #4]
  14494. 8005c3a: f7ff fec7 bl 80059cc <LL_GPIO_SetPinMode>
  14495. }
  14496. pinpos++;
  14497. 8005c3e: 69fb ldr r3, [r7, #28]
  14498. 8005c40: 3301 adds r3, #1
  14499. 8005c42: 61fb str r3, [r7, #28]
  14500. while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
  14501. 8005c44: 683b ldr r3, [r7, #0]
  14502. 8005c46: 681a ldr r2, [r3, #0]
  14503. 8005c48: 69fb ldr r3, [r7, #28]
  14504. 8005c4a: fa22 f303 lsr.w r3, r2, r3
  14505. 8005c4e: 2b00 cmp r3, #0
  14506. 8005c50: d1af bne.n 8005bb2 <LL_GPIO_Init+0x32>
  14507. }
  14508. return (SUCCESS);
  14509. 8005c52: 2300 movs r3, #0
  14510. }
  14511. 8005c54: 4618 mov r0, r3
  14512. 8005c56: 3720 adds r7, #32
  14513. 8005c58: 46bd mov sp, r7
  14514. 8005c5a: bd80 pop {r7, pc}
  14515. 08005c5c <LL_SPI_IsEnabled>:
  14516. {
  14517. 8005c5c: b480 push {r7}
  14518. 8005c5e: b083 sub sp, #12
  14519. 8005c60: af00 add r7, sp, #0
  14520. 8005c62: 6078 str r0, [r7, #4]
  14521. return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
  14522. 8005c64: 687b ldr r3, [r7, #4]
  14523. 8005c66: 681b ldr r3, [r3, #0]
  14524. 8005c68: f003 0301 and.w r3, r3, #1
  14525. 8005c6c: 2b01 cmp r3, #1
  14526. 8005c6e: d101 bne.n 8005c74 <LL_SPI_IsEnabled+0x18>
  14527. 8005c70: 2301 movs r3, #1
  14528. 8005c72: e000 b.n 8005c76 <LL_SPI_IsEnabled+0x1a>
  14529. 8005c74: 2300 movs r3, #0
  14530. }
  14531. 8005c76: 4618 mov r0, r3
  14532. 8005c78: 370c adds r7, #12
  14533. 8005c7a: 46bd mov sp, r7
  14534. 8005c7c: f85d 7b04 ldr.w r7, [sp], #4
  14535. 8005c80: 4770 bx lr
  14536. 08005c82 <LL_SPI_SetInternalSSLevel>:
  14537. {
  14538. 8005c82: b480 push {r7}
  14539. 8005c84: b083 sub sp, #12
  14540. 8005c86: af00 add r7, sp, #0
  14541. 8005c88: 6078 str r0, [r7, #4]
  14542. 8005c8a: 6039 str r1, [r7, #0]
  14543. MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
  14544. 8005c8c: 687b ldr r3, [r7, #4]
  14545. 8005c8e: 681b ldr r3, [r3, #0]
  14546. 8005c90: f423 5280 bic.w r2, r3, #4096 ; 0x1000
  14547. 8005c94: 683b ldr r3, [r7, #0]
  14548. 8005c96: 431a orrs r2, r3
  14549. 8005c98: 687b ldr r3, [r7, #4]
  14550. 8005c9a: 601a str r2, [r3, #0]
  14551. }
  14552. 8005c9c: bf00 nop
  14553. 8005c9e: 370c adds r7, #12
  14554. 8005ca0: 46bd mov sp, r7
  14555. 8005ca2: f85d 7b04 ldr.w r7, [sp], #4
  14556. 8005ca6: 4770 bx lr
  14557. 08005ca8 <LL_SPI_GetNSSPolarity>:
  14558. {
  14559. 8005ca8: b480 push {r7}
  14560. 8005caa: b083 sub sp, #12
  14561. 8005cac: af00 add r7, sp, #0
  14562. 8005cae: 6078 str r0, [r7, #4]
  14563. return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
  14564. 8005cb0: 687b ldr r3, [r7, #4]
  14565. 8005cb2: 68db ldr r3, [r3, #12]
  14566. 8005cb4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
  14567. }
  14568. 8005cb8: 4618 mov r0, r3
  14569. 8005cba: 370c adds r7, #12
  14570. 8005cbc: 46bd mov sp, r7
  14571. 8005cbe: f85d 7b04 ldr.w r7, [sp], #4
  14572. 8005cc2: 4770 bx lr
  14573. 08005cc4 <LL_SPI_SetCRCPolynomial>:
  14574. * @param SPIx SPI Instance
  14575. * @param CRCPoly 0..0xFFFFFFFF
  14576. * @retval None
  14577. */
  14578. __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
  14579. {
  14580. 8005cc4: b480 push {r7}
  14581. 8005cc6: b083 sub sp, #12
  14582. 8005cc8: af00 add r7, sp, #0
  14583. 8005cca: 6078 str r0, [r7, #4]
  14584. 8005ccc: 6039 str r1, [r7, #0]
  14585. WRITE_REG(SPIx->CRCPOLY, CRCPoly);
  14586. 8005cce: 687b ldr r3, [r7, #4]
  14587. 8005cd0: 683a ldr r2, [r7, #0]
  14588. 8005cd2: 641a str r2, [r3, #64] ; 0x40
  14589. }
  14590. 8005cd4: bf00 nop
  14591. 8005cd6: 370c adds r7, #12
  14592. 8005cd8: 46bd mov sp, r7
  14593. 8005cda: f85d 7b04 ldr.w r7, [sp], #4
  14594. 8005cde: 4770 bx lr
  14595. 08005ce0 <LL_SPI_Init>:
  14596. * @param SPIx SPI Instance
  14597. * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
  14598. * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
  14599. */
  14600. ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
  14601. {
  14602. 8005ce0: b580 push {r7, lr}
  14603. 8005ce2: b086 sub sp, #24
  14604. 8005ce4: af00 add r7, sp, #0
  14605. 8005ce6: 6078 str r0, [r7, #4]
  14606. 8005ce8: 6039 str r1, [r7, #0]
  14607. ErrorStatus status = ERROR;
  14608. 8005cea: 2301 movs r3, #1
  14609. 8005cec: 75fb strb r3, [r7, #23]
  14610. assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate));
  14611. assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
  14612. assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
  14613. /* Check the SPI instance is not enabled */
  14614. if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
  14615. 8005cee: 6878 ldr r0, [r7, #4]
  14616. 8005cf0: f7ff ffb4 bl 8005c5c <LL_SPI_IsEnabled>
  14617. 8005cf4: 4603 mov r3, r0
  14618. 8005cf6: 2b00 cmp r3, #0
  14619. 8005cf8: d169 bne.n 8005dce <LL_SPI_Init+0xee>
  14620. * Configure SPIx CFG1 with parameters:
  14621. * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits
  14622. * - CRC Computation Enable : SPI_CFG1_CRCEN bit
  14623. * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits
  14624. */
  14625. MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
  14626. 8005cfa: 687b ldr r3, [r7, #4]
  14627. 8005cfc: 689a ldr r2, [r3, #8]
  14628. 8005cfe: 4b36 ldr r3, [pc, #216] ; (8005dd8 <LL_SPI_Init+0xf8>)
  14629. 8005d00: 4013 ands r3, r2
  14630. 8005d02: 683a ldr r2, [r7, #0]
  14631. 8005d04: 6991 ldr r1, [r2, #24]
  14632. 8005d06: 683a ldr r2, [r7, #0]
  14633. 8005d08: 6a12 ldr r2, [r2, #32]
  14634. 8005d0a: 4311 orrs r1, r2
  14635. 8005d0c: 683a ldr r2, [r7, #0]
  14636. 8005d0e: 6892 ldr r2, [r2, #8]
  14637. 8005d10: 430a orrs r2, r1
  14638. 8005d12: 431a orrs r2, r3
  14639. 8005d14: 687b ldr r3, [r7, #4]
  14640. 8005d16: 609a str r2, [r3, #8]
  14641. SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
  14642. tmp_nss = SPI_InitStruct->NSS;
  14643. 8005d18: 683b ldr r3, [r7, #0]
  14644. 8005d1a: 695b ldr r3, [r3, #20]
  14645. 8005d1c: 613b str r3, [r7, #16]
  14646. tmp_mode = SPI_InitStruct->Mode;
  14647. 8005d1e: 683b ldr r3, [r7, #0]
  14648. 8005d20: 685b ldr r3, [r3, #4]
  14649. 8005d22: 60fb str r3, [r7, #12]
  14650. /* Checks to setup Internal SS signal level and avoid a MODF Error */
  14651. if ((tmp_nss == LL_SPI_NSS_SOFT) && (((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && \
  14652. 8005d24: 693b ldr r3, [r7, #16]
  14653. 8005d26: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
  14654. 8005d2a: d118 bne.n 8005d5e <LL_SPI_Init+0x7e>
  14655. 8005d2c: 6878 ldr r0, [r7, #4]
  14656. 8005d2e: f7ff ffbb bl 8005ca8 <LL_SPI_GetNSSPolarity>
  14657. 8005d32: 4603 mov r3, r0
  14658. 8005d34: 2b00 cmp r3, #0
  14659. 8005d36: d103 bne.n 8005d40 <LL_SPI_Init+0x60>
  14660. 8005d38: 68fb ldr r3, [r7, #12]
  14661. 8005d3a: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
  14662. 8005d3e: d009 beq.n 8005d54 <LL_SPI_Init+0x74>
  14663. (tmp_mode == LL_SPI_MODE_MASTER)) || \
  14664. ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && \
  14665. 8005d40: 6878 ldr r0, [r7, #4]
  14666. 8005d42: f7ff ffb1 bl 8005ca8 <LL_SPI_GetNSSPolarity>
  14667. 8005d46: 4603 mov r3, r0
  14668. (tmp_mode == LL_SPI_MODE_MASTER)) || \
  14669. 8005d48: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
  14670. 8005d4c: d107 bne.n 8005d5e <LL_SPI_Init+0x7e>
  14671. ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && \
  14672. 8005d4e: 68fb ldr r3, [r7, #12]
  14673. 8005d50: 2b00 cmp r3, #0
  14674. 8005d52: d104 bne.n 8005d5e <LL_SPI_Init+0x7e>
  14675. (tmp_mode == LL_SPI_MODE_SLAVE))))
  14676. {
  14677. LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
  14678. 8005d54: f44f 5180 mov.w r1, #4096 ; 0x1000
  14679. 8005d58: 6878 ldr r0, [r7, #4]
  14680. 8005d5a: f7ff ff92 bl 8005c82 <LL_SPI_SetInternalSSLevel>
  14681. * - ClockPhase : SPI_CFG2_CPHA bit
  14682. * - BitOrder : SPI_CFG2_LSBFRST bit
  14683. * - Master/Slave Mode : SPI_CFG2_MASTER bit
  14684. * - SPI Mode : SPI_CFG2_COMM[1:0] bits
  14685. */
  14686. MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE |
  14687. 8005d5e: 687b ldr r3, [r7, #4]
  14688. 8005d60: 68da ldr r2, [r3, #12]
  14689. 8005d62: 4b1e ldr r3, [pc, #120] ; (8005ddc <LL_SPI_Init+0xfc>)
  14690. 8005d64: 4013 ands r3, r2
  14691. 8005d66: 683a ldr r2, [r7, #0]
  14692. 8005d68: 6951 ldr r1, [r2, #20]
  14693. 8005d6a: 683a ldr r2, [r7, #0]
  14694. 8005d6c: 68d2 ldr r2, [r2, #12]
  14695. 8005d6e: 4311 orrs r1, r2
  14696. 8005d70: 683a ldr r2, [r7, #0]
  14697. 8005d72: 6912 ldr r2, [r2, #16]
  14698. 8005d74: 4311 orrs r1, r2
  14699. 8005d76: 683a ldr r2, [r7, #0]
  14700. 8005d78: 69d2 ldr r2, [r2, #28]
  14701. 8005d7a: 4311 orrs r1, r2
  14702. 8005d7c: 683a ldr r2, [r7, #0]
  14703. 8005d7e: 6852 ldr r2, [r2, #4]
  14704. 8005d80: 4311 orrs r1, r2
  14705. 8005d82: 683a ldr r2, [r7, #0]
  14706. 8005d84: 6812 ldr r2, [r2, #0]
  14707. 8005d86: f402 22c0 and.w r2, r2, #393216 ; 0x60000
  14708. 8005d8a: 430a orrs r2, r1
  14709. 8005d8c: 431a orrs r2, r3
  14710. 8005d8e: 687b ldr r3, [r7, #4]
  14711. 8005d90: 60da str r2, [r3, #12]
  14712. /*---------------------------- SPIx CR1 Configuration ------------------------
  14713. * Configure SPIx CR1 with parameter:
  14714. * - Half Duplex Direction : SPI_CR1_HDDIR bit
  14715. */
  14716. MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR);
  14717. 8005d92: 687b ldr r3, [r7, #4]
  14718. 8005d94: 681b ldr r3, [r3, #0]
  14719. 8005d96: f423 6200 bic.w r2, r3, #2048 ; 0x800
  14720. 8005d9a: 683b ldr r3, [r7, #0]
  14721. 8005d9c: 681b ldr r3, [r3, #0]
  14722. 8005d9e: f403 6300 and.w r3, r3, #2048 ; 0x800
  14723. 8005da2: 431a orrs r2, r3
  14724. 8005da4: 687b ldr r3, [r7, #4]
  14725. 8005da6: 601a str r2, [r3, #0]
  14726. /*---------------------------- SPIx CRCPOLY Configuration ----------------------
  14727. * Configure SPIx CRCPOLY with parameter:
  14728. * - CRCPoly : CRCPOLY[31:0] bits
  14729. */
  14730. if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
  14731. 8005da8: 683b ldr r3, [r7, #0]
  14732. 8005daa: 6a1b ldr r3, [r3, #32]
  14733. 8005dac: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
  14734. 8005db0: d105 bne.n 8005dbe <LL_SPI_Init+0xde>
  14735. {
  14736. assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
  14737. LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
  14738. 8005db2: 683b ldr r3, [r7, #0]
  14739. 8005db4: 6a5b ldr r3, [r3, #36] ; 0x24
  14740. 8005db6: 4619 mov r1, r3
  14741. 8005db8: 6878 ldr r0, [r7, #4]
  14742. 8005dba: f7ff ff83 bl 8005cc4 <LL_SPI_SetCRCPolynomial>
  14743. }
  14744. /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
  14745. CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
  14746. 8005dbe: 687b ldr r3, [r7, #4]
  14747. 8005dc0: 6d1b ldr r3, [r3, #80] ; 0x50
  14748. 8005dc2: f023 0201 bic.w r2, r3, #1
  14749. 8005dc6: 687b ldr r3, [r7, #4]
  14750. 8005dc8: 651a str r2, [r3, #80] ; 0x50
  14751. status = SUCCESS;
  14752. 8005dca: 2300 movs r3, #0
  14753. 8005dcc: 75fb strb r3, [r7, #23]
  14754. }
  14755. return status;
  14756. 8005dce: 7dfb ldrb r3, [r7, #23]
  14757. }
  14758. 8005dd0: 4618 mov r0, r3
  14759. 8005dd2: 3718 adds r7, #24
  14760. 8005dd4: 46bd mov sp, r7
  14761. 8005dd6: bd80 pop {r7, pc}
  14762. 8005dd8: 8fbfffe0 .word 0x8fbfffe0
  14763. 8005ddc: d839ffff .word 0xd839ffff
  14764. 08005de0 <USB_CoreInit>:
  14765. * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
  14766. * the configuration information for the specified USBx peripheral.
  14767. * @retval HAL status
  14768. */
  14769. HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
  14770. {
  14771. 8005de0: b084 sub sp, #16
  14772. 8005de2: b580 push {r7, lr}
  14773. 8005de4: b084 sub sp, #16
  14774. 8005de6: af00 add r7, sp, #0
  14775. 8005de8: 6078 str r0, [r7, #4]
  14776. 8005dea: f107 001c add.w r0, r7, #28
  14777. 8005dee: e880 000e stmia.w r0, {r1, r2, r3}
  14778. HAL_StatusTypeDef ret;
  14779. if (cfg.phy_itface == USB_OTG_ULPI_PHY)
  14780. 8005df2: 6b3b ldr r3, [r7, #48] ; 0x30
  14781. 8005df4: 2b01 cmp r3, #1
  14782. 8005df6: d120 bne.n 8005e3a <USB_CoreInit+0x5a>
  14783. {
  14784. USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
  14785. 8005df8: 687b ldr r3, [r7, #4]
  14786. 8005dfa: 6b9b ldr r3, [r3, #56] ; 0x38
  14787. 8005dfc: f423 3280 bic.w r2, r3, #65536 ; 0x10000
  14788. 8005e00: 687b ldr r3, [r7, #4]
  14789. 8005e02: 639a str r2, [r3, #56] ; 0x38
  14790. /* Init The ULPI Interface */
  14791. USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
  14792. 8005e04: 687b ldr r3, [r7, #4]
  14793. 8005e06: 68da ldr r2, [r3, #12]
  14794. 8005e08: 4b2a ldr r3, [pc, #168] ; (8005eb4 <USB_CoreInit+0xd4>)
  14795. 8005e0a: 4013 ands r3, r2
  14796. 8005e0c: 687a ldr r2, [r7, #4]
  14797. 8005e0e: 60d3 str r3, [r2, #12]
  14798. /* Select vbus source */
  14799. USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
  14800. 8005e10: 687b ldr r3, [r7, #4]
  14801. 8005e12: 68db ldr r3, [r3, #12]
  14802. 8005e14: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
  14803. 8005e18: 687b ldr r3, [r7, #4]
  14804. 8005e1a: 60da str r2, [r3, #12]
  14805. if (cfg.use_external_vbus == 1U)
  14806. 8005e1c: 6cfb ldr r3, [r7, #76] ; 0x4c
  14807. 8005e1e: 2b01 cmp r3, #1
  14808. 8005e20: d105 bne.n 8005e2e <USB_CoreInit+0x4e>
  14809. {
  14810. USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
  14811. 8005e22: 687b ldr r3, [r7, #4]
  14812. 8005e24: 68db ldr r3, [r3, #12]
  14813. 8005e26: f443 1280 orr.w r2, r3, #1048576 ; 0x100000
  14814. 8005e2a: 687b ldr r3, [r7, #4]
  14815. 8005e2c: 60da str r2, [r3, #12]
  14816. }
  14817. /* Reset after a PHY select */
  14818. ret = USB_CoreReset(USBx);
  14819. 8005e2e: 6878 ldr r0, [r7, #4]
  14820. 8005e30: f001 fb4e bl 80074d0 <USB_CoreReset>
  14821. 8005e34: 4603 mov r3, r0
  14822. 8005e36: 73fb strb r3, [r7, #15]
  14823. 8005e38: e01a b.n 8005e70 <USB_CoreInit+0x90>
  14824. }
  14825. else /* FS interface (embedded Phy) */
  14826. {
  14827. /* Select FS Embedded PHY */
  14828. USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
  14829. 8005e3a: 687b ldr r3, [r7, #4]
  14830. 8005e3c: 68db ldr r3, [r3, #12]
  14831. 8005e3e: f043 0240 orr.w r2, r3, #64 ; 0x40
  14832. 8005e42: 687b ldr r3, [r7, #4]
  14833. 8005e44: 60da str r2, [r3, #12]
  14834. /* Reset after a PHY select */
  14835. ret = USB_CoreReset(USBx);
  14836. 8005e46: 6878 ldr r0, [r7, #4]
  14837. 8005e48: f001 fb42 bl 80074d0 <USB_CoreReset>
  14838. 8005e4c: 4603 mov r3, r0
  14839. 8005e4e: 73fb strb r3, [r7, #15]
  14840. if (cfg.battery_charging_enable == 0U)
  14841. 8005e50: 6c3b ldr r3, [r7, #64] ; 0x40
  14842. 8005e52: 2b00 cmp r3, #0
  14843. 8005e54: d106 bne.n 8005e64 <USB_CoreInit+0x84>
  14844. {
  14845. /* Activate the USB Transceiver */
  14846. USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
  14847. 8005e56: 687b ldr r3, [r7, #4]
  14848. 8005e58: 6b9b ldr r3, [r3, #56] ; 0x38
  14849. 8005e5a: f443 3280 orr.w r2, r3, #65536 ; 0x10000
  14850. 8005e5e: 687b ldr r3, [r7, #4]
  14851. 8005e60: 639a str r2, [r3, #56] ; 0x38
  14852. 8005e62: e005 b.n 8005e70 <USB_CoreInit+0x90>
  14853. }
  14854. else
  14855. {
  14856. /* Deactivate the USB Transceiver */
  14857. USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
  14858. 8005e64: 687b ldr r3, [r7, #4]
  14859. 8005e66: 6b9b ldr r3, [r3, #56] ; 0x38
  14860. 8005e68: f423 3280 bic.w r2, r3, #65536 ; 0x10000
  14861. 8005e6c: 687b ldr r3, [r7, #4]
  14862. 8005e6e: 639a str r2, [r3, #56] ; 0x38
  14863. }
  14864. }
  14865. if (cfg.dma_enable == 1U)
  14866. 8005e70: 6abb ldr r3, [r7, #40] ; 0x28
  14867. 8005e72: 2b01 cmp r3, #1
  14868. 8005e74: d116 bne.n 8005ea4 <USB_CoreInit+0xc4>
  14869. {
  14870. /* make sure to reserve 18 fifo Locations for DMA buffers */
  14871. USBx->GDFIFOCFG &= ~(0xFFFFU << 16);
  14872. 8005e76: 687b ldr r3, [r7, #4]
  14873. 8005e78: 6ddb ldr r3, [r3, #92] ; 0x5c
  14874. 8005e7a: b29a uxth r2, r3
  14875. 8005e7c: 687b ldr r3, [r7, #4]
  14876. 8005e7e: 65da str r2, [r3, #92] ; 0x5c
  14877. USBx->GDFIFOCFG |= 0x3EEU << 16;
  14878. 8005e80: 687b ldr r3, [r7, #4]
  14879. 8005e82: 6dda ldr r2, [r3, #92] ; 0x5c
  14880. 8005e84: 4b0c ldr r3, [pc, #48] ; (8005eb8 <USB_CoreInit+0xd8>)
  14881. 8005e86: 4313 orrs r3, r2
  14882. 8005e88: 687a ldr r2, [r7, #4]
  14883. 8005e8a: 65d3 str r3, [r2, #92] ; 0x5c
  14884. USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
  14885. 8005e8c: 687b ldr r3, [r7, #4]
  14886. 8005e8e: 689b ldr r3, [r3, #8]
  14887. 8005e90: f043 0206 orr.w r2, r3, #6
  14888. 8005e94: 687b ldr r3, [r7, #4]
  14889. 8005e96: 609a str r2, [r3, #8]
  14890. USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
  14891. 8005e98: 687b ldr r3, [r7, #4]
  14892. 8005e9a: 689b ldr r3, [r3, #8]
  14893. 8005e9c: f043 0220 orr.w r2, r3, #32
  14894. 8005ea0: 687b ldr r3, [r7, #4]
  14895. 8005ea2: 609a str r2, [r3, #8]
  14896. }
  14897. return ret;
  14898. 8005ea4: 7bfb ldrb r3, [r7, #15]
  14899. }
  14900. 8005ea6: 4618 mov r0, r3
  14901. 8005ea8: 3710 adds r7, #16
  14902. 8005eaa: 46bd mov sp, r7
  14903. 8005eac: e8bd 4080 ldmia.w sp!, {r7, lr}
  14904. 8005eb0: b004 add sp, #16
  14905. 8005eb2: 4770 bx lr
  14906. 8005eb4: ffbdffbf .word 0xffbdffbf
  14907. 8005eb8: 03ee0000 .word 0x03ee0000
  14908. 08005ebc <USB_SetTurnaroundTime>:
  14909. * @param hclk: AHB clock frequency
  14910. * @retval USB turnaround time In PHY Clocks number
  14911. */
  14912. HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
  14913. uint32_t hclk, uint8_t speed)
  14914. {
  14915. 8005ebc: b480 push {r7}
  14916. 8005ebe: b087 sub sp, #28
  14917. 8005ec0: af00 add r7, sp, #0
  14918. 8005ec2: 60f8 str r0, [r7, #12]
  14919. 8005ec4: 60b9 str r1, [r7, #8]
  14920. 8005ec6: 4613 mov r3, r2
  14921. 8005ec8: 71fb strb r3, [r7, #7]
  14922. /* The USBTRD is configured according to the tables below, depending on AHB frequency
  14923. used by application. In the low AHB frequency range it is used to stretch enough the USB response
  14924. time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
  14925. latency to the Data FIFO */
  14926. if (speed == USBD_FS_SPEED)
  14927. 8005eca: 79fb ldrb r3, [r7, #7]
  14928. 8005ecc: 2b02 cmp r3, #2
  14929. 8005ece: d165 bne.n 8005f9c <USB_SetTurnaroundTime+0xe0>
  14930. {
  14931. if ((hclk >= 14200000U) && (hclk < 15000000U))
  14932. 8005ed0: 68bb ldr r3, [r7, #8]
  14933. 8005ed2: 4a41 ldr r2, [pc, #260] ; (8005fd8 <USB_SetTurnaroundTime+0x11c>)
  14934. 8005ed4: 4293 cmp r3, r2
  14935. 8005ed6: d906 bls.n 8005ee6 <USB_SetTurnaroundTime+0x2a>
  14936. 8005ed8: 68bb ldr r3, [r7, #8]
  14937. 8005eda: 4a40 ldr r2, [pc, #256] ; (8005fdc <USB_SetTurnaroundTime+0x120>)
  14938. 8005edc: 4293 cmp r3, r2
  14939. 8005ede: d202 bcs.n 8005ee6 <USB_SetTurnaroundTime+0x2a>
  14940. {
  14941. /* hclk Clock Range between 14.2-15 MHz */
  14942. UsbTrd = 0xFU;
  14943. 8005ee0: 230f movs r3, #15
  14944. 8005ee2: 617b str r3, [r7, #20]
  14945. 8005ee4: e062 b.n 8005fac <USB_SetTurnaroundTime+0xf0>
  14946. }
  14947. else if ((hclk >= 15000000U) && (hclk < 16000000U))
  14948. 8005ee6: 68bb ldr r3, [r7, #8]
  14949. 8005ee8: 4a3c ldr r2, [pc, #240] ; (8005fdc <USB_SetTurnaroundTime+0x120>)
  14950. 8005eea: 4293 cmp r3, r2
  14951. 8005eec: d306 bcc.n 8005efc <USB_SetTurnaroundTime+0x40>
  14952. 8005eee: 68bb ldr r3, [r7, #8]
  14953. 8005ef0: 4a3b ldr r2, [pc, #236] ; (8005fe0 <USB_SetTurnaroundTime+0x124>)
  14954. 8005ef2: 4293 cmp r3, r2
  14955. 8005ef4: d202 bcs.n 8005efc <USB_SetTurnaroundTime+0x40>
  14956. {
  14957. /* hclk Clock Range between 15-16 MHz */
  14958. UsbTrd = 0xEU;
  14959. 8005ef6: 230e movs r3, #14
  14960. 8005ef8: 617b str r3, [r7, #20]
  14961. 8005efa: e057 b.n 8005fac <USB_SetTurnaroundTime+0xf0>
  14962. }
  14963. else if ((hclk >= 16000000U) && (hclk < 17200000U))
  14964. 8005efc: 68bb ldr r3, [r7, #8]
  14965. 8005efe: 4a38 ldr r2, [pc, #224] ; (8005fe0 <USB_SetTurnaroundTime+0x124>)
  14966. 8005f00: 4293 cmp r3, r2
  14967. 8005f02: d306 bcc.n 8005f12 <USB_SetTurnaroundTime+0x56>
  14968. 8005f04: 68bb ldr r3, [r7, #8]
  14969. 8005f06: 4a37 ldr r2, [pc, #220] ; (8005fe4 <USB_SetTurnaroundTime+0x128>)
  14970. 8005f08: 4293 cmp r3, r2
  14971. 8005f0a: d202 bcs.n 8005f12 <USB_SetTurnaroundTime+0x56>
  14972. {
  14973. /* hclk Clock Range between 16-17.2 MHz */
  14974. UsbTrd = 0xDU;
  14975. 8005f0c: 230d movs r3, #13
  14976. 8005f0e: 617b str r3, [r7, #20]
  14977. 8005f10: e04c b.n 8005fac <USB_SetTurnaroundTime+0xf0>
  14978. }
  14979. else if ((hclk >= 17200000U) && (hclk < 18500000U))
  14980. 8005f12: 68bb ldr r3, [r7, #8]
  14981. 8005f14: 4a33 ldr r2, [pc, #204] ; (8005fe4 <USB_SetTurnaroundTime+0x128>)
  14982. 8005f16: 4293 cmp r3, r2
  14983. 8005f18: d306 bcc.n 8005f28 <USB_SetTurnaroundTime+0x6c>
  14984. 8005f1a: 68bb ldr r3, [r7, #8]
  14985. 8005f1c: 4a32 ldr r2, [pc, #200] ; (8005fe8 <USB_SetTurnaroundTime+0x12c>)
  14986. 8005f1e: 4293 cmp r3, r2
  14987. 8005f20: d802 bhi.n 8005f28 <USB_SetTurnaroundTime+0x6c>
  14988. {
  14989. /* hclk Clock Range between 17.2-18.5 MHz */
  14990. UsbTrd = 0xCU;
  14991. 8005f22: 230c movs r3, #12
  14992. 8005f24: 617b str r3, [r7, #20]
  14993. 8005f26: e041 b.n 8005fac <USB_SetTurnaroundTime+0xf0>
  14994. }
  14995. else if ((hclk >= 18500000U) && (hclk < 20000000U))
  14996. 8005f28: 68bb ldr r3, [r7, #8]
  14997. 8005f2a: 4a2f ldr r2, [pc, #188] ; (8005fe8 <USB_SetTurnaroundTime+0x12c>)
  14998. 8005f2c: 4293 cmp r3, r2
  14999. 8005f2e: d906 bls.n 8005f3e <USB_SetTurnaroundTime+0x82>
  15000. 8005f30: 68bb ldr r3, [r7, #8]
  15001. 8005f32: 4a2e ldr r2, [pc, #184] ; (8005fec <USB_SetTurnaroundTime+0x130>)
  15002. 8005f34: 4293 cmp r3, r2
  15003. 8005f36: d802 bhi.n 8005f3e <USB_SetTurnaroundTime+0x82>
  15004. {
  15005. /* hclk Clock Range between 18.5-20 MHz */
  15006. UsbTrd = 0xBU;
  15007. 8005f38: 230b movs r3, #11
  15008. 8005f3a: 617b str r3, [r7, #20]
  15009. 8005f3c: e036 b.n 8005fac <USB_SetTurnaroundTime+0xf0>
  15010. }
  15011. else if ((hclk >= 20000000U) && (hclk < 21800000U))
  15012. 8005f3e: 68bb ldr r3, [r7, #8]
  15013. 8005f40: 4a2a ldr r2, [pc, #168] ; (8005fec <USB_SetTurnaroundTime+0x130>)
  15014. 8005f42: 4293 cmp r3, r2
  15015. 8005f44: d906 bls.n 8005f54 <USB_SetTurnaroundTime+0x98>
  15016. 8005f46: 68bb ldr r3, [r7, #8]
  15017. 8005f48: 4a29 ldr r2, [pc, #164] ; (8005ff0 <USB_SetTurnaroundTime+0x134>)
  15018. 8005f4a: 4293 cmp r3, r2
  15019. 8005f4c: d802 bhi.n 8005f54 <USB_SetTurnaroundTime+0x98>
  15020. {
  15021. /* hclk Clock Range between 20-21.8 MHz */
  15022. UsbTrd = 0xAU;
  15023. 8005f4e: 230a movs r3, #10
  15024. 8005f50: 617b str r3, [r7, #20]
  15025. 8005f52: e02b b.n 8005fac <USB_SetTurnaroundTime+0xf0>
  15026. }
  15027. else if ((hclk >= 21800000U) && (hclk < 24000000U))
  15028. 8005f54: 68bb ldr r3, [r7, #8]
  15029. 8005f56: 4a26 ldr r2, [pc, #152] ; (8005ff0 <USB_SetTurnaroundTime+0x134>)
  15030. 8005f58: 4293 cmp r3, r2
  15031. 8005f5a: d906 bls.n 8005f6a <USB_SetTurnaroundTime+0xae>
  15032. 8005f5c: 68bb ldr r3, [r7, #8]
  15033. 8005f5e: 4a25 ldr r2, [pc, #148] ; (8005ff4 <USB_SetTurnaroundTime+0x138>)
  15034. 8005f60: 4293 cmp r3, r2
  15035. 8005f62: d202 bcs.n 8005f6a <USB_SetTurnaroundTime+0xae>
  15036. {
  15037. /* hclk Clock Range between 21.8-24 MHz */
  15038. UsbTrd = 0x9U;
  15039. 8005f64: 2309 movs r3, #9
  15040. 8005f66: 617b str r3, [r7, #20]
  15041. 8005f68: e020 b.n 8005fac <USB_SetTurnaroundTime+0xf0>
  15042. }
  15043. else if ((hclk >= 24000000U) && (hclk < 27700000U))
  15044. 8005f6a: 68bb ldr r3, [r7, #8]
  15045. 8005f6c: 4a21 ldr r2, [pc, #132] ; (8005ff4 <USB_SetTurnaroundTime+0x138>)
  15046. 8005f6e: 4293 cmp r3, r2
  15047. 8005f70: d306 bcc.n 8005f80 <USB_SetTurnaroundTime+0xc4>
  15048. 8005f72: 68bb ldr r3, [r7, #8]
  15049. 8005f74: 4a20 ldr r2, [pc, #128] ; (8005ff8 <USB_SetTurnaroundTime+0x13c>)
  15050. 8005f76: 4293 cmp r3, r2
  15051. 8005f78: d802 bhi.n 8005f80 <USB_SetTurnaroundTime+0xc4>
  15052. {
  15053. /* hclk Clock Range between 24-27.7 MHz */
  15054. UsbTrd = 0x8U;
  15055. 8005f7a: 2308 movs r3, #8
  15056. 8005f7c: 617b str r3, [r7, #20]
  15057. 8005f7e: e015 b.n 8005fac <USB_SetTurnaroundTime+0xf0>
  15058. }
  15059. else if ((hclk >= 27700000U) && (hclk < 32000000U))
  15060. 8005f80: 68bb ldr r3, [r7, #8]
  15061. 8005f82: 4a1d ldr r2, [pc, #116] ; (8005ff8 <USB_SetTurnaroundTime+0x13c>)
  15062. 8005f84: 4293 cmp r3, r2
  15063. 8005f86: d906 bls.n 8005f96 <USB_SetTurnaroundTime+0xda>
  15064. 8005f88: 68bb ldr r3, [r7, #8]
  15065. 8005f8a: 4a1c ldr r2, [pc, #112] ; (8005ffc <USB_SetTurnaroundTime+0x140>)
  15066. 8005f8c: 4293 cmp r3, r2
  15067. 8005f8e: d202 bcs.n 8005f96 <USB_SetTurnaroundTime+0xda>
  15068. {
  15069. /* hclk Clock Range between 27.7-32 MHz */
  15070. UsbTrd = 0x7U;
  15071. 8005f90: 2307 movs r3, #7
  15072. 8005f92: 617b str r3, [r7, #20]
  15073. 8005f94: e00a b.n 8005fac <USB_SetTurnaroundTime+0xf0>
  15074. }
  15075. else /* if(hclk >= 32000000) */
  15076. {
  15077. /* hclk Clock Range between 32-200 MHz */
  15078. UsbTrd = 0x6U;
  15079. 8005f96: 2306 movs r3, #6
  15080. 8005f98: 617b str r3, [r7, #20]
  15081. 8005f9a: e007 b.n 8005fac <USB_SetTurnaroundTime+0xf0>
  15082. }
  15083. }
  15084. else if (speed == USBD_HS_SPEED)
  15085. 8005f9c: 79fb ldrb r3, [r7, #7]
  15086. 8005f9e: 2b00 cmp r3, #0
  15087. 8005fa0: d102 bne.n 8005fa8 <USB_SetTurnaroundTime+0xec>
  15088. {
  15089. UsbTrd = USBD_HS_TRDT_VALUE;
  15090. 8005fa2: 2309 movs r3, #9
  15091. 8005fa4: 617b str r3, [r7, #20]
  15092. 8005fa6: e001 b.n 8005fac <USB_SetTurnaroundTime+0xf0>
  15093. }
  15094. else
  15095. {
  15096. UsbTrd = USBD_DEFAULT_TRDT_VALUE;
  15097. 8005fa8: 2309 movs r3, #9
  15098. 8005faa: 617b str r3, [r7, #20]
  15099. }
  15100. USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
  15101. 8005fac: 68fb ldr r3, [r7, #12]
  15102. 8005fae: 68db ldr r3, [r3, #12]
  15103. 8005fb0: f423 5270 bic.w r2, r3, #15360 ; 0x3c00
  15104. 8005fb4: 68fb ldr r3, [r7, #12]
  15105. 8005fb6: 60da str r2, [r3, #12]
  15106. USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
  15107. 8005fb8: 68fb ldr r3, [r7, #12]
  15108. 8005fba: 68da ldr r2, [r3, #12]
  15109. 8005fbc: 697b ldr r3, [r7, #20]
  15110. 8005fbe: 029b lsls r3, r3, #10
  15111. 8005fc0: f403 5370 and.w r3, r3, #15360 ; 0x3c00
  15112. 8005fc4: 431a orrs r2, r3
  15113. 8005fc6: 68fb ldr r3, [r7, #12]
  15114. 8005fc8: 60da str r2, [r3, #12]
  15115. return HAL_OK;
  15116. 8005fca: 2300 movs r3, #0
  15117. }
  15118. 8005fcc: 4618 mov r0, r3
  15119. 8005fce: 371c adds r7, #28
  15120. 8005fd0: 46bd mov sp, r7
  15121. 8005fd2: f85d 7b04 ldr.w r7, [sp], #4
  15122. 8005fd6: 4770 bx lr
  15123. 8005fd8: 00d8acbf .word 0x00d8acbf
  15124. 8005fdc: 00e4e1c0 .word 0x00e4e1c0
  15125. 8005fe0: 00f42400 .word 0x00f42400
  15126. 8005fe4: 01067380 .word 0x01067380
  15127. 8005fe8: 011a499f .word 0x011a499f
  15128. 8005fec: 01312cff .word 0x01312cff
  15129. 8005ff0: 014ca43f .word 0x014ca43f
  15130. 8005ff4: 016e3600 .word 0x016e3600
  15131. 8005ff8: 01a6ab1f .word 0x01a6ab1f
  15132. 8005ffc: 01e84800 .word 0x01e84800
  15133. 08006000 <USB_EnableGlobalInt>:
  15134. * Enables the controller's Global Int in the AHB Config reg
  15135. * @param USBx Selected device
  15136. * @retval HAL status
  15137. */
  15138. HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
  15139. {
  15140. 8006000: b480 push {r7}
  15141. 8006002: b083 sub sp, #12
  15142. 8006004: af00 add r7, sp, #0
  15143. 8006006: 6078 str r0, [r7, #4]
  15144. USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
  15145. 8006008: 687b ldr r3, [r7, #4]
  15146. 800600a: 689b ldr r3, [r3, #8]
  15147. 800600c: f043 0201 orr.w r2, r3, #1
  15148. 8006010: 687b ldr r3, [r7, #4]
  15149. 8006012: 609a str r2, [r3, #8]
  15150. return HAL_OK;
  15151. 8006014: 2300 movs r3, #0
  15152. }
  15153. 8006016: 4618 mov r0, r3
  15154. 8006018: 370c adds r7, #12
  15155. 800601a: 46bd mov sp, r7
  15156. 800601c: f85d 7b04 ldr.w r7, [sp], #4
  15157. 8006020: 4770 bx lr
  15158. 08006022 <USB_DisableGlobalInt>:
  15159. * Disable the controller's Global Int in the AHB Config reg
  15160. * @param USBx Selected device
  15161. * @retval HAL status
  15162. */
  15163. HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
  15164. {
  15165. 8006022: b480 push {r7}
  15166. 8006024: b083 sub sp, #12
  15167. 8006026: af00 add r7, sp, #0
  15168. 8006028: 6078 str r0, [r7, #4]
  15169. USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
  15170. 800602a: 687b ldr r3, [r7, #4]
  15171. 800602c: 689b ldr r3, [r3, #8]
  15172. 800602e: f023 0201 bic.w r2, r3, #1
  15173. 8006032: 687b ldr r3, [r7, #4]
  15174. 8006034: 609a str r2, [r3, #8]
  15175. return HAL_OK;
  15176. 8006036: 2300 movs r3, #0
  15177. }
  15178. 8006038: 4618 mov r0, r3
  15179. 800603a: 370c adds r7, #12
  15180. 800603c: 46bd mov sp, r7
  15181. 800603e: f85d 7b04 ldr.w r7, [sp], #4
  15182. 8006042: 4770 bx lr
  15183. 08006044 <USB_SetCurrentMode>:
  15184. * @arg USB_DEVICE_MODE Peripheral mode
  15185. * @arg USB_HOST_MODE Host mode
  15186. * @retval HAL status
  15187. */
  15188. HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
  15189. {
  15190. 8006044: b580 push {r7, lr}
  15191. 8006046: b084 sub sp, #16
  15192. 8006048: af00 add r7, sp, #0
  15193. 800604a: 6078 str r0, [r7, #4]
  15194. 800604c: 460b mov r3, r1
  15195. 800604e: 70fb strb r3, [r7, #3]
  15196. uint32_t ms = 0U;
  15197. 8006050: 2300 movs r3, #0
  15198. 8006052: 60fb str r3, [r7, #12]
  15199. USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
  15200. 8006054: 687b ldr r3, [r7, #4]
  15201. 8006056: 68db ldr r3, [r3, #12]
  15202. 8006058: f023 42c0 bic.w r2, r3, #1610612736 ; 0x60000000
  15203. 800605c: 687b ldr r3, [r7, #4]
  15204. 800605e: 60da str r2, [r3, #12]
  15205. if (mode == USB_HOST_MODE)
  15206. 8006060: 78fb ldrb r3, [r7, #3]
  15207. 8006062: 2b01 cmp r3, #1
  15208. 8006064: d115 bne.n 8006092 <USB_SetCurrentMode+0x4e>
  15209. {
  15210. USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
  15211. 8006066: 687b ldr r3, [r7, #4]
  15212. 8006068: 68db ldr r3, [r3, #12]
  15213. 800606a: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000
  15214. 800606e: 687b ldr r3, [r7, #4]
  15215. 8006070: 60da str r2, [r3, #12]
  15216. do
  15217. {
  15218. HAL_Delay(1U);
  15219. 8006072: 2001 movs r0, #1
  15220. 8006074: f7fb fafc bl 8001670 <HAL_Delay>
  15221. ms++;
  15222. 8006078: 68fb ldr r3, [r7, #12]
  15223. 800607a: 3301 adds r3, #1
  15224. 800607c: 60fb str r3, [r7, #12]
  15225. } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
  15226. 800607e: 6878 ldr r0, [r7, #4]
  15227. 8006080: f001 f995 bl 80073ae <USB_GetMode>
  15228. 8006084: 4603 mov r3, r0
  15229. 8006086: 2b01 cmp r3, #1
  15230. 8006088: d01e beq.n 80060c8 <USB_SetCurrentMode+0x84>
  15231. 800608a: 68fb ldr r3, [r7, #12]
  15232. 800608c: 2b31 cmp r3, #49 ; 0x31
  15233. 800608e: d9f0 bls.n 8006072 <USB_SetCurrentMode+0x2e>
  15234. 8006090: e01a b.n 80060c8 <USB_SetCurrentMode+0x84>
  15235. }
  15236. else if (mode == USB_DEVICE_MODE)
  15237. 8006092: 78fb ldrb r3, [r7, #3]
  15238. 8006094: 2b00 cmp r3, #0
  15239. 8006096: d115 bne.n 80060c4 <USB_SetCurrentMode+0x80>
  15240. {
  15241. USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
  15242. 8006098: 687b ldr r3, [r7, #4]
  15243. 800609a: 68db ldr r3, [r3, #12]
  15244. 800609c: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000
  15245. 80060a0: 687b ldr r3, [r7, #4]
  15246. 80060a2: 60da str r2, [r3, #12]
  15247. do
  15248. {
  15249. HAL_Delay(1U);
  15250. 80060a4: 2001 movs r0, #1
  15251. 80060a6: f7fb fae3 bl 8001670 <HAL_Delay>
  15252. ms++;
  15253. 80060aa: 68fb ldr r3, [r7, #12]
  15254. 80060ac: 3301 adds r3, #1
  15255. 80060ae: 60fb str r3, [r7, #12]
  15256. } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
  15257. 80060b0: 6878 ldr r0, [r7, #4]
  15258. 80060b2: f001 f97c bl 80073ae <USB_GetMode>
  15259. 80060b6: 4603 mov r3, r0
  15260. 80060b8: 2b00 cmp r3, #0
  15261. 80060ba: d005 beq.n 80060c8 <USB_SetCurrentMode+0x84>
  15262. 80060bc: 68fb ldr r3, [r7, #12]
  15263. 80060be: 2b31 cmp r3, #49 ; 0x31
  15264. 80060c0: d9f0 bls.n 80060a4 <USB_SetCurrentMode+0x60>
  15265. 80060c2: e001 b.n 80060c8 <USB_SetCurrentMode+0x84>
  15266. }
  15267. else
  15268. {
  15269. return HAL_ERROR;
  15270. 80060c4: 2301 movs r3, #1
  15271. 80060c6: e005 b.n 80060d4 <USB_SetCurrentMode+0x90>
  15272. }
  15273. if (ms == 50U)
  15274. 80060c8: 68fb ldr r3, [r7, #12]
  15275. 80060ca: 2b32 cmp r3, #50 ; 0x32
  15276. 80060cc: d101 bne.n 80060d2 <USB_SetCurrentMode+0x8e>
  15277. {
  15278. return HAL_ERROR;
  15279. 80060ce: 2301 movs r3, #1
  15280. 80060d0: e000 b.n 80060d4 <USB_SetCurrentMode+0x90>
  15281. }
  15282. return HAL_OK;
  15283. 80060d2: 2300 movs r3, #0
  15284. }
  15285. 80060d4: 4618 mov r0, r3
  15286. 80060d6: 3710 adds r7, #16
  15287. 80060d8: 46bd mov sp, r7
  15288. 80060da: bd80 pop {r7, pc}
  15289. 080060dc <USB_DevInit>:
  15290. * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
  15291. * the configuration information for the specified USBx peripheral.
  15292. * @retval HAL status
  15293. */
  15294. HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
  15295. {
  15296. 80060dc: b084 sub sp, #16
  15297. 80060de: b580 push {r7, lr}
  15298. 80060e0: b086 sub sp, #24
  15299. 80060e2: af00 add r7, sp, #0
  15300. 80060e4: 6078 str r0, [r7, #4]
  15301. 80060e6: f107 0024 add.w r0, r7, #36 ; 0x24
  15302. 80060ea: e880 000e stmia.w r0, {r1, r2, r3}
  15303. HAL_StatusTypeDef ret = HAL_OK;
  15304. 80060ee: 2300 movs r3, #0
  15305. 80060f0: 75fb strb r3, [r7, #23]
  15306. uint32_t USBx_BASE = (uint32_t)USBx;
  15307. 80060f2: 687b ldr r3, [r7, #4]
  15308. 80060f4: 60fb str r3, [r7, #12]
  15309. uint32_t i;
  15310. for (i = 0U; i < 15U; i++)
  15311. 80060f6: 2300 movs r3, #0
  15312. 80060f8: 613b str r3, [r7, #16]
  15313. 80060fa: e009 b.n 8006110 <USB_DevInit+0x34>
  15314. {
  15315. USBx->DIEPTXF[i] = 0U;
  15316. 80060fc: 687a ldr r2, [r7, #4]
  15317. 80060fe: 693b ldr r3, [r7, #16]
  15318. 8006100: 3340 adds r3, #64 ; 0x40
  15319. 8006102: 009b lsls r3, r3, #2
  15320. 8006104: 4413 add r3, r2
  15321. 8006106: 2200 movs r2, #0
  15322. 8006108: 605a str r2, [r3, #4]
  15323. for (i = 0U; i < 15U; i++)
  15324. 800610a: 693b ldr r3, [r7, #16]
  15325. 800610c: 3301 adds r3, #1
  15326. 800610e: 613b str r3, [r7, #16]
  15327. 8006110: 693b ldr r3, [r7, #16]
  15328. 8006112: 2b0e cmp r3, #14
  15329. 8006114: d9f2 bls.n 80060fc <USB_DevInit+0x20>
  15330. }
  15331. /* VBUS Sensing setup */
  15332. if (cfg.vbus_sensing_enable == 0U)
  15333. 8006116: 6cfb ldr r3, [r7, #76] ; 0x4c
  15334. 8006118: 2b00 cmp r3, #0
  15335. 800611a: d11c bne.n 8006156 <USB_DevInit+0x7a>
  15336. {
  15337. USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
  15338. 800611c: 68fb ldr r3, [r7, #12]
  15339. 800611e: f503 6300 add.w r3, r3, #2048 ; 0x800
  15340. 8006122: 685b ldr r3, [r3, #4]
  15341. 8006124: 68fa ldr r2, [r7, #12]
  15342. 8006126: f502 6200 add.w r2, r2, #2048 ; 0x800
  15343. 800612a: f043 0302 orr.w r3, r3, #2
  15344. 800612e: 6053 str r3, [r2, #4]
  15345. /* Deactivate VBUS Sensing B */
  15346. USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
  15347. 8006130: 687b ldr r3, [r7, #4]
  15348. 8006132: 6b9b ldr r3, [r3, #56] ; 0x38
  15349. 8006134: f423 1200 bic.w r2, r3, #2097152 ; 0x200000
  15350. 8006138: 687b ldr r3, [r7, #4]
  15351. 800613a: 639a str r2, [r3, #56] ; 0x38
  15352. /* B-peripheral session valid override enable */
  15353. USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
  15354. 800613c: 687b ldr r3, [r7, #4]
  15355. 800613e: 681b ldr r3, [r3, #0]
  15356. 8006140: f043 0240 orr.w r2, r3, #64 ; 0x40
  15357. 8006144: 687b ldr r3, [r7, #4]
  15358. 8006146: 601a str r2, [r3, #0]
  15359. USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
  15360. 8006148: 687b ldr r3, [r7, #4]
  15361. 800614a: 681b ldr r3, [r3, #0]
  15362. 800614c: f043 0280 orr.w r2, r3, #128 ; 0x80
  15363. 8006150: 687b ldr r3, [r7, #4]
  15364. 8006152: 601a str r2, [r3, #0]
  15365. 8006154: e005 b.n 8006162 <USB_DevInit+0x86>
  15366. }
  15367. else
  15368. {
  15369. /* Enable HW VBUS sensing */
  15370. USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
  15371. 8006156: 687b ldr r3, [r7, #4]
  15372. 8006158: 6b9b ldr r3, [r3, #56] ; 0x38
  15373. 800615a: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
  15374. 800615e: 687b ldr r3, [r7, #4]
  15375. 8006160: 639a str r2, [r3, #56] ; 0x38
  15376. }
  15377. /* Restart the Phy Clock */
  15378. USBx_PCGCCTL = 0U;
  15379. 8006162: 68fb ldr r3, [r7, #12]
  15380. 8006164: f503 6360 add.w r3, r3, #3584 ; 0xe00
  15381. 8006168: 461a mov r2, r3
  15382. 800616a: 2300 movs r3, #0
  15383. 800616c: 6013 str r3, [r2, #0]
  15384. /* Device mode configuration */
  15385. USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
  15386. 800616e: 68fb ldr r3, [r7, #12]
  15387. 8006170: f503 6300 add.w r3, r3, #2048 ; 0x800
  15388. 8006174: 4619 mov r1, r3
  15389. 8006176: 68fb ldr r3, [r7, #12]
  15390. 8006178: f503 6300 add.w r3, r3, #2048 ; 0x800
  15391. 800617c: 461a mov r2, r3
  15392. 800617e: 680b ldr r3, [r1, #0]
  15393. 8006180: 6013 str r3, [r2, #0]
  15394. if (cfg.phy_itface == USB_OTG_ULPI_PHY)
  15395. 8006182: 6bbb ldr r3, [r7, #56] ; 0x38
  15396. 8006184: 2b01 cmp r3, #1
  15397. 8006186: d10c bne.n 80061a2 <USB_DevInit+0xc6>
  15398. {
  15399. if (cfg.speed == USBD_HS_SPEED)
  15400. 8006188: 6afb ldr r3, [r7, #44] ; 0x2c
  15401. 800618a: 2b00 cmp r3, #0
  15402. 800618c: d104 bne.n 8006198 <USB_DevInit+0xbc>
  15403. {
  15404. /* Set Core speed to High speed mode */
  15405. (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
  15406. 800618e: 2100 movs r1, #0
  15407. 8006190: 6878 ldr r0, [r7, #4]
  15408. 8006192: f000 f961 bl 8006458 <USB_SetDevSpeed>
  15409. 8006196: e008 b.n 80061aa <USB_DevInit+0xce>
  15410. }
  15411. else
  15412. {
  15413. /* Set Core speed to Full speed mode */
  15414. (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
  15415. 8006198: 2101 movs r1, #1
  15416. 800619a: 6878 ldr r0, [r7, #4]
  15417. 800619c: f000 f95c bl 8006458 <USB_SetDevSpeed>
  15418. 80061a0: e003 b.n 80061aa <USB_DevInit+0xce>
  15419. }
  15420. }
  15421. else
  15422. {
  15423. /* Set Core speed to Full speed mode */
  15424. (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
  15425. 80061a2: 2103 movs r1, #3
  15426. 80061a4: 6878 ldr r0, [r7, #4]
  15427. 80061a6: f000 f957 bl 8006458 <USB_SetDevSpeed>
  15428. }
  15429. /* Flush the FIFOs */
  15430. if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
  15431. 80061aa: 2110 movs r1, #16
  15432. 80061ac: 6878 ldr r0, [r7, #4]
  15433. 80061ae: f000 f8f3 bl 8006398 <USB_FlushTxFifo>
  15434. 80061b2: 4603 mov r3, r0
  15435. 80061b4: 2b00 cmp r3, #0
  15436. 80061b6: d001 beq.n 80061bc <USB_DevInit+0xe0>
  15437. {
  15438. ret = HAL_ERROR;
  15439. 80061b8: 2301 movs r3, #1
  15440. 80061ba: 75fb strb r3, [r7, #23]
  15441. }
  15442. if (USB_FlushRxFifo(USBx) != HAL_OK)
  15443. 80061bc: 6878 ldr r0, [r7, #4]
  15444. 80061be: f000 f91d bl 80063fc <USB_FlushRxFifo>
  15445. 80061c2: 4603 mov r3, r0
  15446. 80061c4: 2b00 cmp r3, #0
  15447. 80061c6: d001 beq.n 80061cc <USB_DevInit+0xf0>
  15448. {
  15449. ret = HAL_ERROR;
  15450. 80061c8: 2301 movs r3, #1
  15451. 80061ca: 75fb strb r3, [r7, #23]
  15452. }
  15453. /* Clear all pending Device Interrupts */
  15454. USBx_DEVICE->DIEPMSK = 0U;
  15455. 80061cc: 68fb ldr r3, [r7, #12]
  15456. 80061ce: f503 6300 add.w r3, r3, #2048 ; 0x800
  15457. 80061d2: 461a mov r2, r3
  15458. 80061d4: 2300 movs r3, #0
  15459. 80061d6: 6113 str r3, [r2, #16]
  15460. USBx_DEVICE->DOEPMSK = 0U;
  15461. 80061d8: 68fb ldr r3, [r7, #12]
  15462. 80061da: f503 6300 add.w r3, r3, #2048 ; 0x800
  15463. 80061de: 461a mov r2, r3
  15464. 80061e0: 2300 movs r3, #0
  15465. 80061e2: 6153 str r3, [r2, #20]
  15466. USBx_DEVICE->DAINTMSK = 0U;
  15467. 80061e4: 68fb ldr r3, [r7, #12]
  15468. 80061e6: f503 6300 add.w r3, r3, #2048 ; 0x800
  15469. 80061ea: 461a mov r2, r3
  15470. 80061ec: 2300 movs r3, #0
  15471. 80061ee: 61d3 str r3, [r2, #28]
  15472. for (i = 0U; i < cfg.dev_endpoints; i++)
  15473. 80061f0: 2300 movs r3, #0
  15474. 80061f2: 613b str r3, [r7, #16]
  15475. 80061f4: e043 b.n 800627e <USB_DevInit+0x1a2>
  15476. {
  15477. if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
  15478. 80061f6: 693b ldr r3, [r7, #16]
  15479. 80061f8: 015a lsls r2, r3, #5
  15480. 80061fa: 68fb ldr r3, [r7, #12]
  15481. 80061fc: 4413 add r3, r2
  15482. 80061fe: f503 6310 add.w r3, r3, #2304 ; 0x900
  15483. 8006202: 681b ldr r3, [r3, #0]
  15484. 8006204: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000
  15485. 8006208: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
  15486. 800620c: d118 bne.n 8006240 <USB_DevInit+0x164>
  15487. {
  15488. if (i == 0U)
  15489. 800620e: 693b ldr r3, [r7, #16]
  15490. 8006210: 2b00 cmp r3, #0
  15491. 8006212: d10a bne.n 800622a <USB_DevInit+0x14e>
  15492. {
  15493. USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
  15494. 8006214: 693b ldr r3, [r7, #16]
  15495. 8006216: 015a lsls r2, r3, #5
  15496. 8006218: 68fb ldr r3, [r7, #12]
  15497. 800621a: 4413 add r3, r2
  15498. 800621c: f503 6310 add.w r3, r3, #2304 ; 0x900
  15499. 8006220: 461a mov r2, r3
  15500. 8006222: f04f 6300 mov.w r3, #134217728 ; 0x8000000
  15501. 8006226: 6013 str r3, [r2, #0]
  15502. 8006228: e013 b.n 8006252 <USB_DevInit+0x176>
  15503. }
  15504. else
  15505. {
  15506. USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
  15507. 800622a: 693b ldr r3, [r7, #16]
  15508. 800622c: 015a lsls r2, r3, #5
  15509. 800622e: 68fb ldr r3, [r7, #12]
  15510. 8006230: 4413 add r3, r2
  15511. 8006232: f503 6310 add.w r3, r3, #2304 ; 0x900
  15512. 8006236: 461a mov r2, r3
  15513. 8006238: f04f 4390 mov.w r3, #1207959552 ; 0x48000000
  15514. 800623c: 6013 str r3, [r2, #0]
  15515. 800623e: e008 b.n 8006252 <USB_DevInit+0x176>
  15516. }
  15517. }
  15518. else
  15519. {
  15520. USBx_INEP(i)->DIEPCTL = 0U;
  15521. 8006240: 693b ldr r3, [r7, #16]
  15522. 8006242: 015a lsls r2, r3, #5
  15523. 8006244: 68fb ldr r3, [r7, #12]
  15524. 8006246: 4413 add r3, r2
  15525. 8006248: f503 6310 add.w r3, r3, #2304 ; 0x900
  15526. 800624c: 461a mov r2, r3
  15527. 800624e: 2300 movs r3, #0
  15528. 8006250: 6013 str r3, [r2, #0]
  15529. }
  15530. USBx_INEP(i)->DIEPTSIZ = 0U;
  15531. 8006252: 693b ldr r3, [r7, #16]
  15532. 8006254: 015a lsls r2, r3, #5
  15533. 8006256: 68fb ldr r3, [r7, #12]
  15534. 8006258: 4413 add r3, r2
  15535. 800625a: f503 6310 add.w r3, r3, #2304 ; 0x900
  15536. 800625e: 461a mov r2, r3
  15537. 8006260: 2300 movs r3, #0
  15538. 8006262: 6113 str r3, [r2, #16]
  15539. USBx_INEP(i)->DIEPINT = 0xFB7FU;
  15540. 8006264: 693b ldr r3, [r7, #16]
  15541. 8006266: 015a lsls r2, r3, #5
  15542. 8006268: 68fb ldr r3, [r7, #12]
  15543. 800626a: 4413 add r3, r2
  15544. 800626c: f503 6310 add.w r3, r3, #2304 ; 0x900
  15545. 8006270: 461a mov r2, r3
  15546. 8006272: f64f 337f movw r3, #64383 ; 0xfb7f
  15547. 8006276: 6093 str r3, [r2, #8]
  15548. for (i = 0U; i < cfg.dev_endpoints; i++)
  15549. 8006278: 693b ldr r3, [r7, #16]
  15550. 800627a: 3301 adds r3, #1
  15551. 800627c: 613b str r3, [r7, #16]
  15552. 800627e: 6a7b ldr r3, [r7, #36] ; 0x24
  15553. 8006280: 693a ldr r2, [r7, #16]
  15554. 8006282: 429a cmp r2, r3
  15555. 8006284: d3b7 bcc.n 80061f6 <USB_DevInit+0x11a>
  15556. }
  15557. for (i = 0U; i < cfg.dev_endpoints; i++)
  15558. 8006286: 2300 movs r3, #0
  15559. 8006288: 613b str r3, [r7, #16]
  15560. 800628a: e043 b.n 8006314 <USB_DevInit+0x238>
  15561. {
  15562. if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
  15563. 800628c: 693b ldr r3, [r7, #16]
  15564. 800628e: 015a lsls r2, r3, #5
  15565. 8006290: 68fb ldr r3, [r7, #12]
  15566. 8006292: 4413 add r3, r2
  15567. 8006294: f503 6330 add.w r3, r3, #2816 ; 0xb00
  15568. 8006298: 681b ldr r3, [r3, #0]
  15569. 800629a: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000
  15570. 800629e: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
  15571. 80062a2: d118 bne.n 80062d6 <USB_DevInit+0x1fa>
  15572. {
  15573. if (i == 0U)
  15574. 80062a4: 693b ldr r3, [r7, #16]
  15575. 80062a6: 2b00 cmp r3, #0
  15576. 80062a8: d10a bne.n 80062c0 <USB_DevInit+0x1e4>
  15577. {
  15578. USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
  15579. 80062aa: 693b ldr r3, [r7, #16]
  15580. 80062ac: 015a lsls r2, r3, #5
  15581. 80062ae: 68fb ldr r3, [r7, #12]
  15582. 80062b0: 4413 add r3, r2
  15583. 80062b2: f503 6330 add.w r3, r3, #2816 ; 0xb00
  15584. 80062b6: 461a mov r2, r3
  15585. 80062b8: f04f 6300 mov.w r3, #134217728 ; 0x8000000
  15586. 80062bc: 6013 str r3, [r2, #0]
  15587. 80062be: e013 b.n 80062e8 <USB_DevInit+0x20c>
  15588. }
  15589. else
  15590. {
  15591. USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
  15592. 80062c0: 693b ldr r3, [r7, #16]
  15593. 80062c2: 015a lsls r2, r3, #5
  15594. 80062c4: 68fb ldr r3, [r7, #12]
  15595. 80062c6: 4413 add r3, r2
  15596. 80062c8: f503 6330 add.w r3, r3, #2816 ; 0xb00
  15597. 80062cc: 461a mov r2, r3
  15598. 80062ce: f04f 4390 mov.w r3, #1207959552 ; 0x48000000
  15599. 80062d2: 6013 str r3, [r2, #0]
  15600. 80062d4: e008 b.n 80062e8 <USB_DevInit+0x20c>
  15601. }
  15602. }
  15603. else
  15604. {
  15605. USBx_OUTEP(i)->DOEPCTL = 0U;
  15606. 80062d6: 693b ldr r3, [r7, #16]
  15607. 80062d8: 015a lsls r2, r3, #5
  15608. 80062da: 68fb ldr r3, [r7, #12]
  15609. 80062dc: 4413 add r3, r2
  15610. 80062de: f503 6330 add.w r3, r3, #2816 ; 0xb00
  15611. 80062e2: 461a mov r2, r3
  15612. 80062e4: 2300 movs r3, #0
  15613. 80062e6: 6013 str r3, [r2, #0]
  15614. }
  15615. USBx_OUTEP(i)->DOEPTSIZ = 0U;
  15616. 80062e8: 693b ldr r3, [r7, #16]
  15617. 80062ea: 015a lsls r2, r3, #5
  15618. 80062ec: 68fb ldr r3, [r7, #12]
  15619. 80062ee: 4413 add r3, r2
  15620. 80062f0: f503 6330 add.w r3, r3, #2816 ; 0xb00
  15621. 80062f4: 461a mov r2, r3
  15622. 80062f6: 2300 movs r3, #0
  15623. 80062f8: 6113 str r3, [r2, #16]
  15624. USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
  15625. 80062fa: 693b ldr r3, [r7, #16]
  15626. 80062fc: 015a lsls r2, r3, #5
  15627. 80062fe: 68fb ldr r3, [r7, #12]
  15628. 8006300: 4413 add r3, r2
  15629. 8006302: f503 6330 add.w r3, r3, #2816 ; 0xb00
  15630. 8006306: 461a mov r2, r3
  15631. 8006308: f64f 337f movw r3, #64383 ; 0xfb7f
  15632. 800630c: 6093 str r3, [r2, #8]
  15633. for (i = 0U; i < cfg.dev_endpoints; i++)
  15634. 800630e: 693b ldr r3, [r7, #16]
  15635. 8006310: 3301 adds r3, #1
  15636. 8006312: 613b str r3, [r7, #16]
  15637. 8006314: 6a7b ldr r3, [r7, #36] ; 0x24
  15638. 8006316: 693a ldr r2, [r7, #16]
  15639. 8006318: 429a cmp r2, r3
  15640. 800631a: d3b7 bcc.n 800628c <USB_DevInit+0x1b0>
  15641. }
  15642. USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
  15643. 800631c: 68fb ldr r3, [r7, #12]
  15644. 800631e: f503 6300 add.w r3, r3, #2048 ; 0x800
  15645. 8006322: 691b ldr r3, [r3, #16]
  15646. 8006324: 68fa ldr r2, [r7, #12]
  15647. 8006326: f502 6200 add.w r2, r2, #2048 ; 0x800
  15648. 800632a: f423 7380 bic.w r3, r3, #256 ; 0x100
  15649. 800632e: 6113 str r3, [r2, #16]
  15650. /* Disable all interrupts. */
  15651. USBx->GINTMSK = 0U;
  15652. 8006330: 687b ldr r3, [r7, #4]
  15653. 8006332: 2200 movs r2, #0
  15654. 8006334: 619a str r2, [r3, #24]
  15655. /* Clear any pending interrupts */
  15656. USBx->GINTSTS = 0xBFFFFFFFU;
  15657. 8006336: 687b ldr r3, [r7, #4]
  15658. 8006338: f06f 4280 mvn.w r2, #1073741824 ; 0x40000000
  15659. 800633c: 615a str r2, [r3, #20]
  15660. /* Enable the common interrupts */
  15661. if (cfg.dma_enable == 0U)
  15662. 800633e: 6b3b ldr r3, [r7, #48] ; 0x30
  15663. 8006340: 2b00 cmp r3, #0
  15664. 8006342: d105 bne.n 8006350 <USB_DevInit+0x274>
  15665. {
  15666. USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
  15667. 8006344: 687b ldr r3, [r7, #4]
  15668. 8006346: 699b ldr r3, [r3, #24]
  15669. 8006348: f043 0210 orr.w r2, r3, #16
  15670. 800634c: 687b ldr r3, [r7, #4]
  15671. 800634e: 619a str r2, [r3, #24]
  15672. }
  15673. /* Enable interrupts matching to the Device mode ONLY */
  15674. USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
  15675. 8006350: 687b ldr r3, [r7, #4]
  15676. 8006352: 699a ldr r2, [r3, #24]
  15677. 8006354: 4b0e ldr r3, [pc, #56] ; (8006390 <USB_DevInit+0x2b4>)
  15678. 8006356: 4313 orrs r3, r2
  15679. 8006358: 687a ldr r2, [r7, #4]
  15680. 800635a: 6193 str r3, [r2, #24]
  15681. USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
  15682. USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
  15683. USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
  15684. if (cfg.Sof_enable != 0U)
  15685. 800635c: 6bfb ldr r3, [r7, #60] ; 0x3c
  15686. 800635e: 2b00 cmp r3, #0
  15687. 8006360: d005 beq.n 800636e <USB_DevInit+0x292>
  15688. {
  15689. USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
  15690. 8006362: 687b ldr r3, [r7, #4]
  15691. 8006364: 699b ldr r3, [r3, #24]
  15692. 8006366: f043 0208 orr.w r2, r3, #8
  15693. 800636a: 687b ldr r3, [r7, #4]
  15694. 800636c: 619a str r2, [r3, #24]
  15695. }
  15696. if (cfg.vbus_sensing_enable == 1U)
  15697. 800636e: 6cfb ldr r3, [r7, #76] ; 0x4c
  15698. 8006370: 2b01 cmp r3, #1
  15699. 8006372: d105 bne.n 8006380 <USB_DevInit+0x2a4>
  15700. {
  15701. USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
  15702. 8006374: 687b ldr r3, [r7, #4]
  15703. 8006376: 699a ldr r2, [r3, #24]
  15704. 8006378: 4b06 ldr r3, [pc, #24] ; (8006394 <USB_DevInit+0x2b8>)
  15705. 800637a: 4313 orrs r3, r2
  15706. 800637c: 687a ldr r2, [r7, #4]
  15707. 800637e: 6193 str r3, [r2, #24]
  15708. }
  15709. return ret;
  15710. 8006380: 7dfb ldrb r3, [r7, #23]
  15711. }
  15712. 8006382: 4618 mov r0, r3
  15713. 8006384: 3718 adds r7, #24
  15714. 8006386: 46bd mov sp, r7
  15715. 8006388: e8bd 4080 ldmia.w sp!, {r7, lr}
  15716. 800638c: b004 add sp, #16
  15717. 800638e: 4770 bx lr
  15718. 8006390: 803c3800 .word 0x803c3800
  15719. 8006394: 40000004 .word 0x40000004
  15720. 08006398 <USB_FlushTxFifo>:
  15721. * This parameter can be a value from 1 to 15
  15722. 15 means Flush all Tx FIFOs
  15723. * @retval HAL status
  15724. */
  15725. HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
  15726. {
  15727. 8006398: b480 push {r7}
  15728. 800639a: b085 sub sp, #20
  15729. 800639c: af00 add r7, sp, #0
  15730. 800639e: 6078 str r0, [r7, #4]
  15731. 80063a0: 6039 str r1, [r7, #0]
  15732. __IO uint32_t count = 0U;
  15733. 80063a2: 2300 movs r3, #0
  15734. 80063a4: 60fb str r3, [r7, #12]
  15735. /* Wait for AHB master IDLE state. */
  15736. do
  15737. {
  15738. if (++count > 200000U)
  15739. 80063a6: 68fb ldr r3, [r7, #12]
  15740. 80063a8: 3301 adds r3, #1
  15741. 80063aa: 60fb str r3, [r7, #12]
  15742. 80063ac: 4a12 ldr r2, [pc, #72] ; (80063f8 <USB_FlushTxFifo+0x60>)
  15743. 80063ae: 4293 cmp r3, r2
  15744. 80063b0: d901 bls.n 80063b6 <USB_FlushTxFifo+0x1e>
  15745. {
  15746. return HAL_TIMEOUT;
  15747. 80063b2: 2303 movs r3, #3
  15748. 80063b4: e01a b.n 80063ec <USB_FlushTxFifo+0x54>
  15749. }
  15750. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
  15751. 80063b6: 687b ldr r3, [r7, #4]
  15752. 80063b8: 691b ldr r3, [r3, #16]
  15753. 80063ba: 2b00 cmp r3, #0
  15754. 80063bc: daf3 bge.n 80063a6 <USB_FlushTxFifo+0xe>
  15755. /* Flush TX Fifo */
  15756. count = 0U;
  15757. 80063be: 2300 movs r3, #0
  15758. 80063c0: 60fb str r3, [r7, #12]
  15759. USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
  15760. 80063c2: 683b ldr r3, [r7, #0]
  15761. 80063c4: 019b lsls r3, r3, #6
  15762. 80063c6: f043 0220 orr.w r2, r3, #32
  15763. 80063ca: 687b ldr r3, [r7, #4]
  15764. 80063cc: 611a str r2, [r3, #16]
  15765. do
  15766. {
  15767. if (++count > 200000U)
  15768. 80063ce: 68fb ldr r3, [r7, #12]
  15769. 80063d0: 3301 adds r3, #1
  15770. 80063d2: 60fb str r3, [r7, #12]
  15771. 80063d4: 4a08 ldr r2, [pc, #32] ; (80063f8 <USB_FlushTxFifo+0x60>)
  15772. 80063d6: 4293 cmp r3, r2
  15773. 80063d8: d901 bls.n 80063de <USB_FlushTxFifo+0x46>
  15774. {
  15775. return HAL_TIMEOUT;
  15776. 80063da: 2303 movs r3, #3
  15777. 80063dc: e006 b.n 80063ec <USB_FlushTxFifo+0x54>
  15778. }
  15779. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
  15780. 80063de: 687b ldr r3, [r7, #4]
  15781. 80063e0: 691b ldr r3, [r3, #16]
  15782. 80063e2: f003 0320 and.w r3, r3, #32
  15783. 80063e6: 2b20 cmp r3, #32
  15784. 80063e8: d0f1 beq.n 80063ce <USB_FlushTxFifo+0x36>
  15785. return HAL_OK;
  15786. 80063ea: 2300 movs r3, #0
  15787. }
  15788. 80063ec: 4618 mov r0, r3
  15789. 80063ee: 3714 adds r7, #20
  15790. 80063f0: 46bd mov sp, r7
  15791. 80063f2: f85d 7b04 ldr.w r7, [sp], #4
  15792. 80063f6: 4770 bx lr
  15793. 80063f8: 00030d40 .word 0x00030d40
  15794. 080063fc <USB_FlushRxFifo>:
  15795. * @brief USB_FlushRxFifo Flush Rx FIFO
  15796. * @param USBx Selected device
  15797. * @retval HAL status
  15798. */
  15799. HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
  15800. {
  15801. 80063fc: b480 push {r7}
  15802. 80063fe: b085 sub sp, #20
  15803. 8006400: af00 add r7, sp, #0
  15804. 8006402: 6078 str r0, [r7, #4]
  15805. __IO uint32_t count = 0U;
  15806. 8006404: 2300 movs r3, #0
  15807. 8006406: 60fb str r3, [r7, #12]
  15808. /* Wait for AHB master IDLE state. */
  15809. do
  15810. {
  15811. if (++count > 200000U)
  15812. 8006408: 68fb ldr r3, [r7, #12]
  15813. 800640a: 3301 adds r3, #1
  15814. 800640c: 60fb str r3, [r7, #12]
  15815. 800640e: 4a11 ldr r2, [pc, #68] ; (8006454 <USB_FlushRxFifo+0x58>)
  15816. 8006410: 4293 cmp r3, r2
  15817. 8006412: d901 bls.n 8006418 <USB_FlushRxFifo+0x1c>
  15818. {
  15819. return HAL_TIMEOUT;
  15820. 8006414: 2303 movs r3, #3
  15821. 8006416: e017 b.n 8006448 <USB_FlushRxFifo+0x4c>
  15822. }
  15823. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
  15824. 8006418: 687b ldr r3, [r7, #4]
  15825. 800641a: 691b ldr r3, [r3, #16]
  15826. 800641c: 2b00 cmp r3, #0
  15827. 800641e: daf3 bge.n 8006408 <USB_FlushRxFifo+0xc>
  15828. /* Flush RX Fifo */
  15829. count = 0U;
  15830. 8006420: 2300 movs r3, #0
  15831. 8006422: 60fb str r3, [r7, #12]
  15832. USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
  15833. 8006424: 687b ldr r3, [r7, #4]
  15834. 8006426: 2210 movs r2, #16
  15835. 8006428: 611a str r2, [r3, #16]
  15836. do
  15837. {
  15838. if (++count > 200000U)
  15839. 800642a: 68fb ldr r3, [r7, #12]
  15840. 800642c: 3301 adds r3, #1
  15841. 800642e: 60fb str r3, [r7, #12]
  15842. 8006430: 4a08 ldr r2, [pc, #32] ; (8006454 <USB_FlushRxFifo+0x58>)
  15843. 8006432: 4293 cmp r3, r2
  15844. 8006434: d901 bls.n 800643a <USB_FlushRxFifo+0x3e>
  15845. {
  15846. return HAL_TIMEOUT;
  15847. 8006436: 2303 movs r3, #3
  15848. 8006438: e006 b.n 8006448 <USB_FlushRxFifo+0x4c>
  15849. }
  15850. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
  15851. 800643a: 687b ldr r3, [r7, #4]
  15852. 800643c: 691b ldr r3, [r3, #16]
  15853. 800643e: f003 0310 and.w r3, r3, #16
  15854. 8006442: 2b10 cmp r3, #16
  15855. 8006444: d0f1 beq.n 800642a <USB_FlushRxFifo+0x2e>
  15856. return HAL_OK;
  15857. 8006446: 2300 movs r3, #0
  15858. }
  15859. 8006448: 4618 mov r0, r3
  15860. 800644a: 3714 adds r7, #20
  15861. 800644c: 46bd mov sp, r7
  15862. 800644e: f85d 7b04 ldr.w r7, [sp], #4
  15863. 8006452: 4770 bx lr
  15864. 8006454: 00030d40 .word 0x00030d40
  15865. 08006458 <USB_SetDevSpeed>:
  15866. * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
  15867. * @arg USB_OTG_SPEED_FULL: Full speed mode
  15868. * @retval Hal status
  15869. */
  15870. HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
  15871. {
  15872. 8006458: b480 push {r7}
  15873. 800645a: b085 sub sp, #20
  15874. 800645c: af00 add r7, sp, #0
  15875. 800645e: 6078 str r0, [r7, #4]
  15876. 8006460: 460b mov r3, r1
  15877. 8006462: 70fb strb r3, [r7, #3]
  15878. uint32_t USBx_BASE = (uint32_t)USBx;
  15879. 8006464: 687b ldr r3, [r7, #4]
  15880. 8006466: 60fb str r3, [r7, #12]
  15881. USBx_DEVICE->DCFG |= speed;
  15882. 8006468: 68fb ldr r3, [r7, #12]
  15883. 800646a: f503 6300 add.w r3, r3, #2048 ; 0x800
  15884. 800646e: 681a ldr r2, [r3, #0]
  15885. 8006470: 78fb ldrb r3, [r7, #3]
  15886. 8006472: 68f9 ldr r1, [r7, #12]
  15887. 8006474: f501 6100 add.w r1, r1, #2048 ; 0x800
  15888. 8006478: 4313 orrs r3, r2
  15889. 800647a: 600b str r3, [r1, #0]
  15890. return HAL_OK;
  15891. 800647c: 2300 movs r3, #0
  15892. }
  15893. 800647e: 4618 mov r0, r3
  15894. 8006480: 3714 adds r7, #20
  15895. 8006482: 46bd mov sp, r7
  15896. 8006484: f85d 7b04 ldr.w r7, [sp], #4
  15897. 8006488: 4770 bx lr
  15898. 0800648a <USB_GetDevSpeed>:
  15899. * This parameter can be one of these values:
  15900. * @arg USBD_HS_SPEED: High speed mode
  15901. * @arg USBD_FS_SPEED: Full speed mode
  15902. */
  15903. uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
  15904. {
  15905. 800648a: b480 push {r7}
  15906. 800648c: b087 sub sp, #28
  15907. 800648e: af00 add r7, sp, #0
  15908. 8006490: 6078 str r0, [r7, #4]
  15909. uint32_t USBx_BASE = (uint32_t)USBx;
  15910. 8006492: 687b ldr r3, [r7, #4]
  15911. 8006494: 613b str r3, [r7, #16]
  15912. uint8_t speed;
  15913. uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
  15914. 8006496: 693b ldr r3, [r7, #16]
  15915. 8006498: f503 6300 add.w r3, r3, #2048 ; 0x800
  15916. 800649c: 689b ldr r3, [r3, #8]
  15917. 800649e: f003 0306 and.w r3, r3, #6
  15918. 80064a2: 60fb str r3, [r7, #12]
  15919. if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
  15920. 80064a4: 68fb ldr r3, [r7, #12]
  15921. 80064a6: 2b00 cmp r3, #0
  15922. 80064a8: d102 bne.n 80064b0 <USB_GetDevSpeed+0x26>
  15923. {
  15924. speed = USBD_HS_SPEED;
  15925. 80064aa: 2300 movs r3, #0
  15926. 80064ac: 75fb strb r3, [r7, #23]
  15927. 80064ae: e00a b.n 80064c6 <USB_GetDevSpeed+0x3c>
  15928. }
  15929. else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
  15930. 80064b0: 68fb ldr r3, [r7, #12]
  15931. 80064b2: 2b02 cmp r3, #2
  15932. 80064b4: d002 beq.n 80064bc <USB_GetDevSpeed+0x32>
  15933. 80064b6: 68fb ldr r3, [r7, #12]
  15934. 80064b8: 2b06 cmp r3, #6
  15935. 80064ba: d102 bne.n 80064c2 <USB_GetDevSpeed+0x38>
  15936. (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
  15937. {
  15938. speed = USBD_FS_SPEED;
  15939. 80064bc: 2302 movs r3, #2
  15940. 80064be: 75fb strb r3, [r7, #23]
  15941. 80064c0: e001 b.n 80064c6 <USB_GetDevSpeed+0x3c>
  15942. }
  15943. else
  15944. {
  15945. speed = 0xFU;
  15946. 80064c2: 230f movs r3, #15
  15947. 80064c4: 75fb strb r3, [r7, #23]
  15948. }
  15949. return speed;
  15950. 80064c6: 7dfb ldrb r3, [r7, #23]
  15951. }
  15952. 80064c8: 4618 mov r0, r3
  15953. 80064ca: 371c adds r7, #28
  15954. 80064cc: 46bd mov sp, r7
  15955. 80064ce: f85d 7b04 ldr.w r7, [sp], #4
  15956. 80064d2: 4770 bx lr
  15957. 080064d4 <USB_ActivateEndpoint>:
  15958. * @param USBx Selected device
  15959. * @param ep pointer to endpoint structure
  15960. * @retval HAL status
  15961. */
  15962. HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
  15963. {
  15964. 80064d4: b480 push {r7}
  15965. 80064d6: b085 sub sp, #20
  15966. 80064d8: af00 add r7, sp, #0
  15967. 80064da: 6078 str r0, [r7, #4]
  15968. 80064dc: 6039 str r1, [r7, #0]
  15969. uint32_t USBx_BASE = (uint32_t)USBx;
  15970. 80064de: 687b ldr r3, [r7, #4]
  15971. 80064e0: 60fb str r3, [r7, #12]
  15972. uint32_t epnum = (uint32_t)ep->num;
  15973. 80064e2: 683b ldr r3, [r7, #0]
  15974. 80064e4: 781b ldrb r3, [r3, #0]
  15975. 80064e6: 60bb str r3, [r7, #8]
  15976. if (ep->is_in == 1U)
  15977. 80064e8: 683b ldr r3, [r7, #0]
  15978. 80064ea: 785b ldrb r3, [r3, #1]
  15979. 80064ec: 2b01 cmp r3, #1
  15980. 80064ee: d139 bne.n 8006564 <USB_ActivateEndpoint+0x90>
  15981. {
  15982. USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
  15983. 80064f0: 68fb ldr r3, [r7, #12]
  15984. 80064f2: f503 6300 add.w r3, r3, #2048 ; 0x800
  15985. 80064f6: 69da ldr r2, [r3, #28]
  15986. 80064f8: 683b ldr r3, [r7, #0]
  15987. 80064fa: 781b ldrb r3, [r3, #0]
  15988. 80064fc: f003 030f and.w r3, r3, #15
  15989. 8006500: 2101 movs r1, #1
  15990. 8006502: fa01 f303 lsl.w r3, r1, r3
  15991. 8006506: b29b uxth r3, r3
  15992. 8006508: 68f9 ldr r1, [r7, #12]
  15993. 800650a: f501 6100 add.w r1, r1, #2048 ; 0x800
  15994. 800650e: 4313 orrs r3, r2
  15995. 8006510: 61cb str r3, [r1, #28]
  15996. if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
  15997. 8006512: 68bb ldr r3, [r7, #8]
  15998. 8006514: 015a lsls r2, r3, #5
  15999. 8006516: 68fb ldr r3, [r7, #12]
  16000. 8006518: 4413 add r3, r2
  16001. 800651a: f503 6310 add.w r3, r3, #2304 ; 0x900
  16002. 800651e: 681b ldr r3, [r3, #0]
  16003. 8006520: f403 4300 and.w r3, r3, #32768 ; 0x8000
  16004. 8006524: 2b00 cmp r3, #0
  16005. 8006526: d153 bne.n 80065d0 <USB_ActivateEndpoint+0xfc>
  16006. {
  16007. USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
  16008. 8006528: 68bb ldr r3, [r7, #8]
  16009. 800652a: 015a lsls r2, r3, #5
  16010. 800652c: 68fb ldr r3, [r7, #12]
  16011. 800652e: 4413 add r3, r2
  16012. 8006530: f503 6310 add.w r3, r3, #2304 ; 0x900
  16013. 8006534: 681a ldr r2, [r3, #0]
  16014. 8006536: 683b ldr r3, [r7, #0]
  16015. 8006538: 689b ldr r3, [r3, #8]
  16016. 800653a: f3c3 010a ubfx r1, r3, #0, #11
  16017. ((uint32_t)ep->type << 18) | (epnum << 22) |
  16018. 800653e: 683b ldr r3, [r7, #0]
  16019. 8006540: 78db ldrb r3, [r3, #3]
  16020. 8006542: 049b lsls r3, r3, #18
  16021. USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
  16022. 8006544: 4319 orrs r1, r3
  16023. ((uint32_t)ep->type << 18) | (epnum << 22) |
  16024. 8006546: 68bb ldr r3, [r7, #8]
  16025. 8006548: 059b lsls r3, r3, #22
  16026. 800654a: 430b orrs r3, r1
  16027. USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
  16028. 800654c: 431a orrs r2, r3
  16029. 800654e: 68bb ldr r3, [r7, #8]
  16030. 8006550: 0159 lsls r1, r3, #5
  16031. 8006552: 68fb ldr r3, [r7, #12]
  16032. 8006554: 440b add r3, r1
  16033. 8006556: f503 6310 add.w r3, r3, #2304 ; 0x900
  16034. 800655a: 4619 mov r1, r3
  16035. 800655c: 4b20 ldr r3, [pc, #128] ; (80065e0 <USB_ActivateEndpoint+0x10c>)
  16036. 800655e: 4313 orrs r3, r2
  16037. 8006560: 600b str r3, [r1, #0]
  16038. 8006562: e035 b.n 80065d0 <USB_ActivateEndpoint+0xfc>
  16039. USB_OTG_DIEPCTL_USBAEP;
  16040. }
  16041. }
  16042. else
  16043. {
  16044. USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
  16045. 8006564: 68fb ldr r3, [r7, #12]
  16046. 8006566: f503 6300 add.w r3, r3, #2048 ; 0x800
  16047. 800656a: 69da ldr r2, [r3, #28]
  16048. 800656c: 683b ldr r3, [r7, #0]
  16049. 800656e: 781b ldrb r3, [r3, #0]
  16050. 8006570: f003 030f and.w r3, r3, #15
  16051. 8006574: 2101 movs r1, #1
  16052. 8006576: fa01 f303 lsl.w r3, r1, r3
  16053. 800657a: 041b lsls r3, r3, #16
  16054. 800657c: 68f9 ldr r1, [r7, #12]
  16055. 800657e: f501 6100 add.w r1, r1, #2048 ; 0x800
  16056. 8006582: 4313 orrs r3, r2
  16057. 8006584: 61cb str r3, [r1, #28]
  16058. if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
  16059. 8006586: 68bb ldr r3, [r7, #8]
  16060. 8006588: 015a lsls r2, r3, #5
  16061. 800658a: 68fb ldr r3, [r7, #12]
  16062. 800658c: 4413 add r3, r2
  16063. 800658e: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16064. 8006592: 681b ldr r3, [r3, #0]
  16065. 8006594: f403 4300 and.w r3, r3, #32768 ; 0x8000
  16066. 8006598: 2b00 cmp r3, #0
  16067. 800659a: d119 bne.n 80065d0 <USB_ActivateEndpoint+0xfc>
  16068. {
  16069. USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
  16070. 800659c: 68bb ldr r3, [r7, #8]
  16071. 800659e: 015a lsls r2, r3, #5
  16072. 80065a0: 68fb ldr r3, [r7, #12]
  16073. 80065a2: 4413 add r3, r2
  16074. 80065a4: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16075. 80065a8: 681a ldr r2, [r3, #0]
  16076. 80065aa: 683b ldr r3, [r7, #0]
  16077. 80065ac: 689b ldr r3, [r3, #8]
  16078. 80065ae: f3c3 010a ubfx r1, r3, #0, #11
  16079. ((uint32_t)ep->type << 18) |
  16080. 80065b2: 683b ldr r3, [r7, #0]
  16081. 80065b4: 78db ldrb r3, [r3, #3]
  16082. 80065b6: 049b lsls r3, r3, #18
  16083. USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
  16084. 80065b8: 430b orrs r3, r1
  16085. 80065ba: 431a orrs r2, r3
  16086. 80065bc: 68bb ldr r3, [r7, #8]
  16087. 80065be: 0159 lsls r1, r3, #5
  16088. 80065c0: 68fb ldr r3, [r7, #12]
  16089. 80065c2: 440b add r3, r1
  16090. 80065c4: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16091. 80065c8: 4619 mov r1, r3
  16092. 80065ca: 4b05 ldr r3, [pc, #20] ; (80065e0 <USB_ActivateEndpoint+0x10c>)
  16093. 80065cc: 4313 orrs r3, r2
  16094. 80065ce: 600b str r3, [r1, #0]
  16095. USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
  16096. USB_OTG_DOEPCTL_USBAEP;
  16097. }
  16098. }
  16099. return HAL_OK;
  16100. 80065d0: 2300 movs r3, #0
  16101. }
  16102. 80065d2: 4618 mov r0, r3
  16103. 80065d4: 3714 adds r7, #20
  16104. 80065d6: 46bd mov sp, r7
  16105. 80065d8: f85d 7b04 ldr.w r7, [sp], #4
  16106. 80065dc: 4770 bx lr
  16107. 80065de: bf00 nop
  16108. 80065e0: 10008000 .word 0x10008000
  16109. 080065e4 <USB_DeactivateEndpoint>:
  16110. * @param USBx Selected device
  16111. * @param ep pointer to endpoint structure
  16112. * @retval HAL status
  16113. */
  16114. HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
  16115. {
  16116. 80065e4: b480 push {r7}
  16117. 80065e6: b085 sub sp, #20
  16118. 80065e8: af00 add r7, sp, #0
  16119. 80065ea: 6078 str r0, [r7, #4]
  16120. 80065ec: 6039 str r1, [r7, #0]
  16121. uint32_t USBx_BASE = (uint32_t)USBx;
  16122. 80065ee: 687b ldr r3, [r7, #4]
  16123. 80065f0: 60fb str r3, [r7, #12]
  16124. uint32_t epnum = (uint32_t)ep->num;
  16125. 80065f2: 683b ldr r3, [r7, #0]
  16126. 80065f4: 781b ldrb r3, [r3, #0]
  16127. 80065f6: 60bb str r3, [r7, #8]
  16128. /* Read DEPCTLn register */
  16129. if (ep->is_in == 1U)
  16130. 80065f8: 683b ldr r3, [r7, #0]
  16131. 80065fa: 785b ldrb r3, [r3, #1]
  16132. 80065fc: 2b01 cmp r3, #1
  16133. 80065fe: d161 bne.n 80066c4 <USB_DeactivateEndpoint+0xe0>
  16134. {
  16135. if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
  16136. 8006600: 68bb ldr r3, [r7, #8]
  16137. 8006602: 015a lsls r2, r3, #5
  16138. 8006604: 68fb ldr r3, [r7, #12]
  16139. 8006606: 4413 add r3, r2
  16140. 8006608: f503 6310 add.w r3, r3, #2304 ; 0x900
  16141. 800660c: 681b ldr r3, [r3, #0]
  16142. 800660e: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000
  16143. 8006612: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
  16144. 8006616: d11f bne.n 8006658 <USB_DeactivateEndpoint+0x74>
  16145. {
  16146. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
  16147. 8006618: 68bb ldr r3, [r7, #8]
  16148. 800661a: 015a lsls r2, r3, #5
  16149. 800661c: 68fb ldr r3, [r7, #12]
  16150. 800661e: 4413 add r3, r2
  16151. 8006620: f503 6310 add.w r3, r3, #2304 ; 0x900
  16152. 8006624: 681b ldr r3, [r3, #0]
  16153. 8006626: 68ba ldr r2, [r7, #8]
  16154. 8006628: 0151 lsls r1, r2, #5
  16155. 800662a: 68fa ldr r2, [r7, #12]
  16156. 800662c: 440a add r2, r1
  16157. 800662e: f502 6210 add.w r2, r2, #2304 ; 0x900
  16158. 8006632: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000
  16159. 8006636: 6013 str r3, [r2, #0]
  16160. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
  16161. 8006638: 68bb ldr r3, [r7, #8]
  16162. 800663a: 015a lsls r2, r3, #5
  16163. 800663c: 68fb ldr r3, [r7, #12]
  16164. 800663e: 4413 add r3, r2
  16165. 8006640: f503 6310 add.w r3, r3, #2304 ; 0x900
  16166. 8006644: 681b ldr r3, [r3, #0]
  16167. 8006646: 68ba ldr r2, [r7, #8]
  16168. 8006648: 0151 lsls r1, r2, #5
  16169. 800664a: 68fa ldr r2, [r7, #12]
  16170. 800664c: 440a add r2, r1
  16171. 800664e: f502 6210 add.w r2, r2, #2304 ; 0x900
  16172. 8006652: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000
  16173. 8006656: 6013 str r3, [r2, #0]
  16174. }
  16175. USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
  16176. 8006658: 68fb ldr r3, [r7, #12]
  16177. 800665a: f503 6300 add.w r3, r3, #2048 ; 0x800
  16178. 800665e: 6bda ldr r2, [r3, #60] ; 0x3c
  16179. 8006660: 683b ldr r3, [r7, #0]
  16180. 8006662: 781b ldrb r3, [r3, #0]
  16181. 8006664: f003 030f and.w r3, r3, #15
  16182. 8006668: 2101 movs r1, #1
  16183. 800666a: fa01 f303 lsl.w r3, r1, r3
  16184. 800666e: b29b uxth r3, r3
  16185. 8006670: 43db mvns r3, r3
  16186. 8006672: 68f9 ldr r1, [r7, #12]
  16187. 8006674: f501 6100 add.w r1, r1, #2048 ; 0x800
  16188. 8006678: 4013 ands r3, r2
  16189. 800667a: 63cb str r3, [r1, #60] ; 0x3c
  16190. USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
  16191. 800667c: 68fb ldr r3, [r7, #12]
  16192. 800667e: f503 6300 add.w r3, r3, #2048 ; 0x800
  16193. 8006682: 69da ldr r2, [r3, #28]
  16194. 8006684: 683b ldr r3, [r7, #0]
  16195. 8006686: 781b ldrb r3, [r3, #0]
  16196. 8006688: f003 030f and.w r3, r3, #15
  16197. 800668c: 2101 movs r1, #1
  16198. 800668e: fa01 f303 lsl.w r3, r1, r3
  16199. 8006692: b29b uxth r3, r3
  16200. 8006694: 43db mvns r3, r3
  16201. 8006696: 68f9 ldr r1, [r7, #12]
  16202. 8006698: f501 6100 add.w r1, r1, #2048 ; 0x800
  16203. 800669c: 4013 ands r3, r2
  16204. 800669e: 61cb str r3, [r1, #28]
  16205. USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
  16206. 80066a0: 68bb ldr r3, [r7, #8]
  16207. 80066a2: 015a lsls r2, r3, #5
  16208. 80066a4: 68fb ldr r3, [r7, #12]
  16209. 80066a6: 4413 add r3, r2
  16210. 80066a8: f503 6310 add.w r3, r3, #2304 ; 0x900
  16211. 80066ac: 681a ldr r2, [r3, #0]
  16212. 80066ae: 68bb ldr r3, [r7, #8]
  16213. 80066b0: 0159 lsls r1, r3, #5
  16214. 80066b2: 68fb ldr r3, [r7, #12]
  16215. 80066b4: 440b add r3, r1
  16216. 80066b6: f503 6310 add.w r3, r3, #2304 ; 0x900
  16217. 80066ba: 4619 mov r1, r3
  16218. 80066bc: 4b35 ldr r3, [pc, #212] ; (8006794 <USB_DeactivateEndpoint+0x1b0>)
  16219. 80066be: 4013 ands r3, r2
  16220. 80066c0: 600b str r3, [r1, #0]
  16221. 80066c2: e060 b.n 8006786 <USB_DeactivateEndpoint+0x1a2>
  16222. USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
  16223. USB_OTG_DIEPCTL_EPTYP);
  16224. }
  16225. else
  16226. {
  16227. if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
  16228. 80066c4: 68bb ldr r3, [r7, #8]
  16229. 80066c6: 015a lsls r2, r3, #5
  16230. 80066c8: 68fb ldr r3, [r7, #12]
  16231. 80066ca: 4413 add r3, r2
  16232. 80066cc: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16233. 80066d0: 681b ldr r3, [r3, #0]
  16234. 80066d2: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000
  16235. 80066d6: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
  16236. 80066da: d11f bne.n 800671c <USB_DeactivateEndpoint+0x138>
  16237. {
  16238. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
  16239. 80066dc: 68bb ldr r3, [r7, #8]
  16240. 80066de: 015a lsls r2, r3, #5
  16241. 80066e0: 68fb ldr r3, [r7, #12]
  16242. 80066e2: 4413 add r3, r2
  16243. 80066e4: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16244. 80066e8: 681b ldr r3, [r3, #0]
  16245. 80066ea: 68ba ldr r2, [r7, #8]
  16246. 80066ec: 0151 lsls r1, r2, #5
  16247. 80066ee: 68fa ldr r2, [r7, #12]
  16248. 80066f0: 440a add r2, r1
  16249. 80066f2: f502 6230 add.w r2, r2, #2816 ; 0xb00
  16250. 80066f6: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000
  16251. 80066fa: 6013 str r3, [r2, #0]
  16252. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
  16253. 80066fc: 68bb ldr r3, [r7, #8]
  16254. 80066fe: 015a lsls r2, r3, #5
  16255. 8006700: 68fb ldr r3, [r7, #12]
  16256. 8006702: 4413 add r3, r2
  16257. 8006704: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16258. 8006708: 681b ldr r3, [r3, #0]
  16259. 800670a: 68ba ldr r2, [r7, #8]
  16260. 800670c: 0151 lsls r1, r2, #5
  16261. 800670e: 68fa ldr r2, [r7, #12]
  16262. 8006710: 440a add r2, r1
  16263. 8006712: f502 6230 add.w r2, r2, #2816 ; 0xb00
  16264. 8006716: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000
  16265. 800671a: 6013 str r3, [r2, #0]
  16266. }
  16267. USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
  16268. 800671c: 68fb ldr r3, [r7, #12]
  16269. 800671e: f503 6300 add.w r3, r3, #2048 ; 0x800
  16270. 8006722: 6bda ldr r2, [r3, #60] ; 0x3c
  16271. 8006724: 683b ldr r3, [r7, #0]
  16272. 8006726: 781b ldrb r3, [r3, #0]
  16273. 8006728: f003 030f and.w r3, r3, #15
  16274. 800672c: 2101 movs r1, #1
  16275. 800672e: fa01 f303 lsl.w r3, r1, r3
  16276. 8006732: 041b lsls r3, r3, #16
  16277. 8006734: 43db mvns r3, r3
  16278. 8006736: 68f9 ldr r1, [r7, #12]
  16279. 8006738: f501 6100 add.w r1, r1, #2048 ; 0x800
  16280. 800673c: 4013 ands r3, r2
  16281. 800673e: 63cb str r3, [r1, #60] ; 0x3c
  16282. USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
  16283. 8006740: 68fb ldr r3, [r7, #12]
  16284. 8006742: f503 6300 add.w r3, r3, #2048 ; 0x800
  16285. 8006746: 69da ldr r2, [r3, #28]
  16286. 8006748: 683b ldr r3, [r7, #0]
  16287. 800674a: 781b ldrb r3, [r3, #0]
  16288. 800674c: f003 030f and.w r3, r3, #15
  16289. 8006750: 2101 movs r1, #1
  16290. 8006752: fa01 f303 lsl.w r3, r1, r3
  16291. 8006756: 041b lsls r3, r3, #16
  16292. 8006758: 43db mvns r3, r3
  16293. 800675a: 68f9 ldr r1, [r7, #12]
  16294. 800675c: f501 6100 add.w r1, r1, #2048 ; 0x800
  16295. 8006760: 4013 ands r3, r2
  16296. 8006762: 61cb str r3, [r1, #28]
  16297. USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
  16298. 8006764: 68bb ldr r3, [r7, #8]
  16299. 8006766: 015a lsls r2, r3, #5
  16300. 8006768: 68fb ldr r3, [r7, #12]
  16301. 800676a: 4413 add r3, r2
  16302. 800676c: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16303. 8006770: 681a ldr r2, [r3, #0]
  16304. 8006772: 68bb ldr r3, [r7, #8]
  16305. 8006774: 0159 lsls r1, r3, #5
  16306. 8006776: 68fb ldr r3, [r7, #12]
  16307. 8006778: 440b add r3, r1
  16308. 800677a: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16309. 800677e: 4619 mov r1, r3
  16310. 8006780: 4b05 ldr r3, [pc, #20] ; (8006798 <USB_DeactivateEndpoint+0x1b4>)
  16311. 8006782: 4013 ands r3, r2
  16312. 8006784: 600b str r3, [r1, #0]
  16313. USB_OTG_DOEPCTL_MPSIZ |
  16314. USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
  16315. USB_OTG_DOEPCTL_EPTYP);
  16316. }
  16317. return HAL_OK;
  16318. 8006786: 2300 movs r3, #0
  16319. }
  16320. 8006788: 4618 mov r0, r3
  16321. 800678a: 3714 adds r7, #20
  16322. 800678c: 46bd mov sp, r7
  16323. 800678e: f85d 7b04 ldr.w r7, [sp], #4
  16324. 8006792: 4770 bx lr
  16325. 8006794: ec337800 .word 0xec337800
  16326. 8006798: eff37800 .word 0xeff37800
  16327. 0800679c <USB_EPStartXfer>:
  16328. * 0 : DMA feature not used
  16329. * 1 : DMA feature used
  16330. * @retval HAL status
  16331. */
  16332. HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
  16333. {
  16334. 800679c: b580 push {r7, lr}
  16335. 800679e: b08a sub sp, #40 ; 0x28
  16336. 80067a0: af02 add r7, sp, #8
  16337. 80067a2: 60f8 str r0, [r7, #12]
  16338. 80067a4: 60b9 str r1, [r7, #8]
  16339. 80067a6: 4613 mov r3, r2
  16340. 80067a8: 71fb strb r3, [r7, #7]
  16341. uint32_t USBx_BASE = (uint32_t)USBx;
  16342. 80067aa: 68fb ldr r3, [r7, #12]
  16343. 80067ac: 61fb str r3, [r7, #28]
  16344. uint32_t epnum = (uint32_t)ep->num;
  16345. 80067ae: 68bb ldr r3, [r7, #8]
  16346. 80067b0: 781b ldrb r3, [r3, #0]
  16347. 80067b2: 61bb str r3, [r7, #24]
  16348. uint16_t pktcnt;
  16349. /* IN endpoint */
  16350. if (ep->is_in == 1U)
  16351. 80067b4: 68bb ldr r3, [r7, #8]
  16352. 80067b6: 785b ldrb r3, [r3, #1]
  16353. 80067b8: 2b01 cmp r3, #1
  16354. 80067ba: f040 8163 bne.w 8006a84 <USB_EPStartXfer+0x2e8>
  16355. {
  16356. /* Zero Length Packet? */
  16357. if (ep->xfer_len == 0U)
  16358. 80067be: 68bb ldr r3, [r7, #8]
  16359. 80067c0: 695b ldr r3, [r3, #20]
  16360. 80067c2: 2b00 cmp r3, #0
  16361. 80067c4: d132 bne.n 800682c <USB_EPStartXfer+0x90>
  16362. {
  16363. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
  16364. 80067c6: 69bb ldr r3, [r7, #24]
  16365. 80067c8: 015a lsls r2, r3, #5
  16366. 80067ca: 69fb ldr r3, [r7, #28]
  16367. 80067cc: 4413 add r3, r2
  16368. 80067ce: f503 6310 add.w r3, r3, #2304 ; 0x900
  16369. 80067d2: 691a ldr r2, [r3, #16]
  16370. 80067d4: 69bb ldr r3, [r7, #24]
  16371. 80067d6: 0159 lsls r1, r3, #5
  16372. 80067d8: 69fb ldr r3, [r7, #28]
  16373. 80067da: 440b add r3, r1
  16374. 80067dc: f503 6310 add.w r3, r3, #2304 ; 0x900
  16375. 80067e0: 4619 mov r1, r3
  16376. 80067e2: 4ba5 ldr r3, [pc, #660] ; (8006a78 <USB_EPStartXfer+0x2dc>)
  16377. 80067e4: 4013 ands r3, r2
  16378. 80067e6: 610b str r3, [r1, #16]
  16379. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
  16380. 80067e8: 69bb ldr r3, [r7, #24]
  16381. 80067ea: 015a lsls r2, r3, #5
  16382. 80067ec: 69fb ldr r3, [r7, #28]
  16383. 80067ee: 4413 add r3, r2
  16384. 80067f0: f503 6310 add.w r3, r3, #2304 ; 0x900
  16385. 80067f4: 691b ldr r3, [r3, #16]
  16386. 80067f6: 69ba ldr r2, [r7, #24]
  16387. 80067f8: 0151 lsls r1, r2, #5
  16388. 80067fa: 69fa ldr r2, [r7, #28]
  16389. 80067fc: 440a add r2, r1
  16390. 80067fe: f502 6210 add.w r2, r2, #2304 ; 0x900
  16391. 8006802: f443 2300 orr.w r3, r3, #524288 ; 0x80000
  16392. 8006806: 6113 str r3, [r2, #16]
  16393. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
  16394. 8006808: 69bb ldr r3, [r7, #24]
  16395. 800680a: 015a lsls r2, r3, #5
  16396. 800680c: 69fb ldr r3, [r7, #28]
  16397. 800680e: 4413 add r3, r2
  16398. 8006810: f503 6310 add.w r3, r3, #2304 ; 0x900
  16399. 8006814: 691a ldr r2, [r3, #16]
  16400. 8006816: 69bb ldr r3, [r7, #24]
  16401. 8006818: 0159 lsls r1, r3, #5
  16402. 800681a: 69fb ldr r3, [r7, #28]
  16403. 800681c: 440b add r3, r1
  16404. 800681e: f503 6310 add.w r3, r3, #2304 ; 0x900
  16405. 8006822: 4619 mov r1, r3
  16406. 8006824: 4b95 ldr r3, [pc, #596] ; (8006a7c <USB_EPStartXfer+0x2e0>)
  16407. 8006826: 4013 ands r3, r2
  16408. 8006828: 610b str r3, [r1, #16]
  16409. 800682a: e074 b.n 8006916 <USB_EPStartXfer+0x17a>
  16410. /* Program the transfer size and packet count
  16411. * as follows: xfersize = N * maxpacket +
  16412. * short_packet pktcnt = N + (short_packet
  16413. * exist ? 1 : 0)
  16414. */
  16415. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
  16416. 800682c: 69bb ldr r3, [r7, #24]
  16417. 800682e: 015a lsls r2, r3, #5
  16418. 8006830: 69fb ldr r3, [r7, #28]
  16419. 8006832: 4413 add r3, r2
  16420. 8006834: f503 6310 add.w r3, r3, #2304 ; 0x900
  16421. 8006838: 691a ldr r2, [r3, #16]
  16422. 800683a: 69bb ldr r3, [r7, #24]
  16423. 800683c: 0159 lsls r1, r3, #5
  16424. 800683e: 69fb ldr r3, [r7, #28]
  16425. 8006840: 440b add r3, r1
  16426. 8006842: f503 6310 add.w r3, r3, #2304 ; 0x900
  16427. 8006846: 4619 mov r1, r3
  16428. 8006848: 4b8c ldr r3, [pc, #560] ; (8006a7c <USB_EPStartXfer+0x2e0>)
  16429. 800684a: 4013 ands r3, r2
  16430. 800684c: 610b str r3, [r1, #16]
  16431. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
  16432. 800684e: 69bb ldr r3, [r7, #24]
  16433. 8006850: 015a lsls r2, r3, #5
  16434. 8006852: 69fb ldr r3, [r7, #28]
  16435. 8006854: 4413 add r3, r2
  16436. 8006856: f503 6310 add.w r3, r3, #2304 ; 0x900
  16437. 800685a: 691a ldr r2, [r3, #16]
  16438. 800685c: 69bb ldr r3, [r7, #24]
  16439. 800685e: 0159 lsls r1, r3, #5
  16440. 8006860: 69fb ldr r3, [r7, #28]
  16441. 8006862: 440b add r3, r1
  16442. 8006864: f503 6310 add.w r3, r3, #2304 ; 0x900
  16443. 8006868: 4619 mov r1, r3
  16444. 800686a: 4b83 ldr r3, [pc, #524] ; (8006a78 <USB_EPStartXfer+0x2dc>)
  16445. 800686c: 4013 ands r3, r2
  16446. 800686e: 610b str r3, [r1, #16]
  16447. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
  16448. 8006870: 69bb ldr r3, [r7, #24]
  16449. 8006872: 015a lsls r2, r3, #5
  16450. 8006874: 69fb ldr r3, [r7, #28]
  16451. 8006876: 4413 add r3, r2
  16452. 8006878: f503 6310 add.w r3, r3, #2304 ; 0x900
  16453. 800687c: 691a ldr r2, [r3, #16]
  16454. (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
  16455. 800687e: 68bb ldr r3, [r7, #8]
  16456. 8006880: 6959 ldr r1, [r3, #20]
  16457. 8006882: 68bb ldr r3, [r7, #8]
  16458. 8006884: 689b ldr r3, [r3, #8]
  16459. 8006886: 440b add r3, r1
  16460. 8006888: 1e59 subs r1, r3, #1
  16461. 800688a: 68bb ldr r3, [r7, #8]
  16462. 800688c: 689b ldr r3, [r3, #8]
  16463. 800688e: fbb1 f3f3 udiv r3, r1, r3
  16464. 8006892: 04d9 lsls r1, r3, #19
  16465. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
  16466. 8006894: 4b7a ldr r3, [pc, #488] ; (8006a80 <USB_EPStartXfer+0x2e4>)
  16467. 8006896: 400b ands r3, r1
  16468. 8006898: 69b9 ldr r1, [r7, #24]
  16469. 800689a: 0148 lsls r0, r1, #5
  16470. 800689c: 69f9 ldr r1, [r7, #28]
  16471. 800689e: 4401 add r1, r0
  16472. 80068a0: f501 6110 add.w r1, r1, #2304 ; 0x900
  16473. 80068a4: 4313 orrs r3, r2
  16474. 80068a6: 610b str r3, [r1, #16]
  16475. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
  16476. 80068a8: 69bb ldr r3, [r7, #24]
  16477. 80068aa: 015a lsls r2, r3, #5
  16478. 80068ac: 69fb ldr r3, [r7, #28]
  16479. 80068ae: 4413 add r3, r2
  16480. 80068b0: f503 6310 add.w r3, r3, #2304 ; 0x900
  16481. 80068b4: 691a ldr r2, [r3, #16]
  16482. 80068b6: 68bb ldr r3, [r7, #8]
  16483. 80068b8: 695b ldr r3, [r3, #20]
  16484. 80068ba: f3c3 0312 ubfx r3, r3, #0, #19
  16485. 80068be: 69b9 ldr r1, [r7, #24]
  16486. 80068c0: 0148 lsls r0, r1, #5
  16487. 80068c2: 69f9 ldr r1, [r7, #28]
  16488. 80068c4: 4401 add r1, r0
  16489. 80068c6: f501 6110 add.w r1, r1, #2304 ; 0x900
  16490. 80068ca: 4313 orrs r3, r2
  16491. 80068cc: 610b str r3, [r1, #16]
  16492. if (ep->type == EP_TYPE_ISOC)
  16493. 80068ce: 68bb ldr r3, [r7, #8]
  16494. 80068d0: 78db ldrb r3, [r3, #3]
  16495. 80068d2: 2b01 cmp r3, #1
  16496. 80068d4: d11f bne.n 8006916 <USB_EPStartXfer+0x17a>
  16497. {
  16498. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
  16499. 80068d6: 69bb ldr r3, [r7, #24]
  16500. 80068d8: 015a lsls r2, r3, #5
  16501. 80068da: 69fb ldr r3, [r7, #28]
  16502. 80068dc: 4413 add r3, r2
  16503. 80068de: f503 6310 add.w r3, r3, #2304 ; 0x900
  16504. 80068e2: 691b ldr r3, [r3, #16]
  16505. 80068e4: 69ba ldr r2, [r7, #24]
  16506. 80068e6: 0151 lsls r1, r2, #5
  16507. 80068e8: 69fa ldr r2, [r7, #28]
  16508. 80068ea: 440a add r2, r1
  16509. 80068ec: f502 6210 add.w r2, r2, #2304 ; 0x900
  16510. 80068f0: f023 43c0 bic.w r3, r3, #1610612736 ; 0x60000000
  16511. 80068f4: 6113 str r3, [r2, #16]
  16512. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
  16513. 80068f6: 69bb ldr r3, [r7, #24]
  16514. 80068f8: 015a lsls r2, r3, #5
  16515. 80068fa: 69fb ldr r3, [r7, #28]
  16516. 80068fc: 4413 add r3, r2
  16517. 80068fe: f503 6310 add.w r3, r3, #2304 ; 0x900
  16518. 8006902: 691b ldr r3, [r3, #16]
  16519. 8006904: 69ba ldr r2, [r7, #24]
  16520. 8006906: 0151 lsls r1, r2, #5
  16521. 8006908: 69fa ldr r2, [r7, #28]
  16522. 800690a: 440a add r2, r1
  16523. 800690c: f502 6210 add.w r2, r2, #2304 ; 0x900
  16524. 8006910: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
  16525. 8006914: 6113 str r3, [r2, #16]
  16526. }
  16527. }
  16528. if (dma == 1U)
  16529. 8006916: 79fb ldrb r3, [r7, #7]
  16530. 8006918: 2b01 cmp r3, #1
  16531. 800691a: d14b bne.n 80069b4 <USB_EPStartXfer+0x218>
  16532. {
  16533. if ((uint32_t)ep->dma_addr != 0U)
  16534. 800691c: 68bb ldr r3, [r7, #8]
  16535. 800691e: 691b ldr r3, [r3, #16]
  16536. 8006920: 2b00 cmp r3, #0
  16537. 8006922: d009 beq.n 8006938 <USB_EPStartXfer+0x19c>
  16538. {
  16539. USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
  16540. 8006924: 69bb ldr r3, [r7, #24]
  16541. 8006926: 015a lsls r2, r3, #5
  16542. 8006928: 69fb ldr r3, [r7, #28]
  16543. 800692a: 4413 add r3, r2
  16544. 800692c: f503 6310 add.w r3, r3, #2304 ; 0x900
  16545. 8006930: 461a mov r2, r3
  16546. 8006932: 68bb ldr r3, [r7, #8]
  16547. 8006934: 691b ldr r3, [r3, #16]
  16548. 8006936: 6153 str r3, [r2, #20]
  16549. }
  16550. if (ep->type == EP_TYPE_ISOC)
  16551. 8006938: 68bb ldr r3, [r7, #8]
  16552. 800693a: 78db ldrb r3, [r3, #3]
  16553. 800693c: 2b01 cmp r3, #1
  16554. 800693e: d128 bne.n 8006992 <USB_EPStartXfer+0x1f6>
  16555. {
  16556. if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
  16557. 8006940: 69fb ldr r3, [r7, #28]
  16558. 8006942: f503 6300 add.w r3, r3, #2048 ; 0x800
  16559. 8006946: 689b ldr r3, [r3, #8]
  16560. 8006948: f403 7380 and.w r3, r3, #256 ; 0x100
  16561. 800694c: 2b00 cmp r3, #0
  16562. 800694e: d110 bne.n 8006972 <USB_EPStartXfer+0x1d6>
  16563. {
  16564. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
  16565. 8006950: 69bb ldr r3, [r7, #24]
  16566. 8006952: 015a lsls r2, r3, #5
  16567. 8006954: 69fb ldr r3, [r7, #28]
  16568. 8006956: 4413 add r3, r2
  16569. 8006958: f503 6310 add.w r3, r3, #2304 ; 0x900
  16570. 800695c: 681b ldr r3, [r3, #0]
  16571. 800695e: 69ba ldr r2, [r7, #24]
  16572. 8006960: 0151 lsls r1, r2, #5
  16573. 8006962: 69fa ldr r2, [r7, #28]
  16574. 8006964: 440a add r2, r1
  16575. 8006966: f502 6210 add.w r2, r2, #2304 ; 0x900
  16576. 800696a: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
  16577. 800696e: 6013 str r3, [r2, #0]
  16578. 8006970: e00f b.n 8006992 <USB_EPStartXfer+0x1f6>
  16579. }
  16580. else
  16581. {
  16582. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
  16583. 8006972: 69bb ldr r3, [r7, #24]
  16584. 8006974: 015a lsls r2, r3, #5
  16585. 8006976: 69fb ldr r3, [r7, #28]
  16586. 8006978: 4413 add r3, r2
  16587. 800697a: f503 6310 add.w r3, r3, #2304 ; 0x900
  16588. 800697e: 681b ldr r3, [r3, #0]
  16589. 8006980: 69ba ldr r2, [r7, #24]
  16590. 8006982: 0151 lsls r1, r2, #5
  16591. 8006984: 69fa ldr r2, [r7, #28]
  16592. 8006986: 440a add r2, r1
  16593. 8006988: f502 6210 add.w r2, r2, #2304 ; 0x900
  16594. 800698c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
  16595. 8006990: 6013 str r3, [r2, #0]
  16596. }
  16597. }
  16598. /* EP enable, IN data in FIFO */
  16599. USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
  16600. 8006992: 69bb ldr r3, [r7, #24]
  16601. 8006994: 015a lsls r2, r3, #5
  16602. 8006996: 69fb ldr r3, [r7, #28]
  16603. 8006998: 4413 add r3, r2
  16604. 800699a: f503 6310 add.w r3, r3, #2304 ; 0x900
  16605. 800699e: 681b ldr r3, [r3, #0]
  16606. 80069a0: 69ba ldr r2, [r7, #24]
  16607. 80069a2: 0151 lsls r1, r2, #5
  16608. 80069a4: 69fa ldr r2, [r7, #28]
  16609. 80069a6: 440a add r2, r1
  16610. 80069a8: f502 6210 add.w r2, r2, #2304 ; 0x900
  16611. 80069ac: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000
  16612. 80069b0: 6013 str r3, [r2, #0]
  16613. 80069b2: e133 b.n 8006c1c <USB_EPStartXfer+0x480>
  16614. }
  16615. else
  16616. {
  16617. /* EP enable, IN data in FIFO */
  16618. USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
  16619. 80069b4: 69bb ldr r3, [r7, #24]
  16620. 80069b6: 015a lsls r2, r3, #5
  16621. 80069b8: 69fb ldr r3, [r7, #28]
  16622. 80069ba: 4413 add r3, r2
  16623. 80069bc: f503 6310 add.w r3, r3, #2304 ; 0x900
  16624. 80069c0: 681b ldr r3, [r3, #0]
  16625. 80069c2: 69ba ldr r2, [r7, #24]
  16626. 80069c4: 0151 lsls r1, r2, #5
  16627. 80069c6: 69fa ldr r2, [r7, #28]
  16628. 80069c8: 440a add r2, r1
  16629. 80069ca: f502 6210 add.w r2, r2, #2304 ; 0x900
  16630. 80069ce: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000
  16631. 80069d2: 6013 str r3, [r2, #0]
  16632. if (ep->type != EP_TYPE_ISOC)
  16633. 80069d4: 68bb ldr r3, [r7, #8]
  16634. 80069d6: 78db ldrb r3, [r3, #3]
  16635. 80069d8: 2b01 cmp r3, #1
  16636. 80069da: d015 beq.n 8006a08 <USB_EPStartXfer+0x26c>
  16637. {
  16638. /* Enable the Tx FIFO Empty Interrupt for this EP */
  16639. if (ep->xfer_len > 0U)
  16640. 80069dc: 68bb ldr r3, [r7, #8]
  16641. 80069de: 695b ldr r3, [r3, #20]
  16642. 80069e0: 2b00 cmp r3, #0
  16643. 80069e2: f000 811b beq.w 8006c1c <USB_EPStartXfer+0x480>
  16644. {
  16645. USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
  16646. 80069e6: 69fb ldr r3, [r7, #28]
  16647. 80069e8: f503 6300 add.w r3, r3, #2048 ; 0x800
  16648. 80069ec: 6b5a ldr r2, [r3, #52] ; 0x34
  16649. 80069ee: 68bb ldr r3, [r7, #8]
  16650. 80069f0: 781b ldrb r3, [r3, #0]
  16651. 80069f2: f003 030f and.w r3, r3, #15
  16652. 80069f6: 2101 movs r1, #1
  16653. 80069f8: fa01 f303 lsl.w r3, r1, r3
  16654. 80069fc: 69f9 ldr r1, [r7, #28]
  16655. 80069fe: f501 6100 add.w r1, r1, #2048 ; 0x800
  16656. 8006a02: 4313 orrs r3, r2
  16657. 8006a04: 634b str r3, [r1, #52] ; 0x34
  16658. 8006a06: e109 b.n 8006c1c <USB_EPStartXfer+0x480>
  16659. }
  16660. }
  16661. else
  16662. {
  16663. if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
  16664. 8006a08: 69fb ldr r3, [r7, #28]
  16665. 8006a0a: f503 6300 add.w r3, r3, #2048 ; 0x800
  16666. 8006a0e: 689b ldr r3, [r3, #8]
  16667. 8006a10: f403 7380 and.w r3, r3, #256 ; 0x100
  16668. 8006a14: 2b00 cmp r3, #0
  16669. 8006a16: d110 bne.n 8006a3a <USB_EPStartXfer+0x29e>
  16670. {
  16671. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
  16672. 8006a18: 69bb ldr r3, [r7, #24]
  16673. 8006a1a: 015a lsls r2, r3, #5
  16674. 8006a1c: 69fb ldr r3, [r7, #28]
  16675. 8006a1e: 4413 add r3, r2
  16676. 8006a20: f503 6310 add.w r3, r3, #2304 ; 0x900
  16677. 8006a24: 681b ldr r3, [r3, #0]
  16678. 8006a26: 69ba ldr r2, [r7, #24]
  16679. 8006a28: 0151 lsls r1, r2, #5
  16680. 8006a2a: 69fa ldr r2, [r7, #28]
  16681. 8006a2c: 440a add r2, r1
  16682. 8006a2e: f502 6210 add.w r2, r2, #2304 ; 0x900
  16683. 8006a32: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
  16684. 8006a36: 6013 str r3, [r2, #0]
  16685. 8006a38: e00f b.n 8006a5a <USB_EPStartXfer+0x2be>
  16686. }
  16687. else
  16688. {
  16689. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
  16690. 8006a3a: 69bb ldr r3, [r7, #24]
  16691. 8006a3c: 015a lsls r2, r3, #5
  16692. 8006a3e: 69fb ldr r3, [r7, #28]
  16693. 8006a40: 4413 add r3, r2
  16694. 8006a42: f503 6310 add.w r3, r3, #2304 ; 0x900
  16695. 8006a46: 681b ldr r3, [r3, #0]
  16696. 8006a48: 69ba ldr r2, [r7, #24]
  16697. 8006a4a: 0151 lsls r1, r2, #5
  16698. 8006a4c: 69fa ldr r2, [r7, #28]
  16699. 8006a4e: 440a add r2, r1
  16700. 8006a50: f502 6210 add.w r2, r2, #2304 ; 0x900
  16701. 8006a54: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
  16702. 8006a58: 6013 str r3, [r2, #0]
  16703. }
  16704. (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
  16705. 8006a5a: 68bb ldr r3, [r7, #8]
  16706. 8006a5c: 68d9 ldr r1, [r3, #12]
  16707. 8006a5e: 68bb ldr r3, [r7, #8]
  16708. 8006a60: 781a ldrb r2, [r3, #0]
  16709. 8006a62: 68bb ldr r3, [r7, #8]
  16710. 8006a64: 695b ldr r3, [r3, #20]
  16711. 8006a66: b298 uxth r0, r3
  16712. 8006a68: 79fb ldrb r3, [r7, #7]
  16713. 8006a6a: 9300 str r3, [sp, #0]
  16714. 8006a6c: 4603 mov r3, r0
  16715. 8006a6e: 68f8 ldr r0, [r7, #12]
  16716. 8006a70: f000 fa38 bl 8006ee4 <USB_WritePacket>
  16717. 8006a74: e0d2 b.n 8006c1c <USB_EPStartXfer+0x480>
  16718. 8006a76: bf00 nop
  16719. 8006a78: e007ffff .word 0xe007ffff
  16720. 8006a7c: fff80000 .word 0xfff80000
  16721. 8006a80: 1ff80000 .word 0x1ff80000
  16722. {
  16723. /* Program the transfer size and packet count as follows:
  16724. * pktcnt = N
  16725. * xfersize = N * maxpacket
  16726. */
  16727. USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
  16728. 8006a84: 69bb ldr r3, [r7, #24]
  16729. 8006a86: 015a lsls r2, r3, #5
  16730. 8006a88: 69fb ldr r3, [r7, #28]
  16731. 8006a8a: 4413 add r3, r2
  16732. 8006a8c: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16733. 8006a90: 691a ldr r2, [r3, #16]
  16734. 8006a92: 69bb ldr r3, [r7, #24]
  16735. 8006a94: 0159 lsls r1, r3, #5
  16736. 8006a96: 69fb ldr r3, [r7, #28]
  16737. 8006a98: 440b add r3, r1
  16738. 8006a9a: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16739. 8006a9e: 4619 mov r1, r3
  16740. 8006aa0: 4b61 ldr r3, [pc, #388] ; (8006c28 <USB_EPStartXfer+0x48c>)
  16741. 8006aa2: 4013 ands r3, r2
  16742. 8006aa4: 610b str r3, [r1, #16]
  16743. USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
  16744. 8006aa6: 69bb ldr r3, [r7, #24]
  16745. 8006aa8: 015a lsls r2, r3, #5
  16746. 8006aaa: 69fb ldr r3, [r7, #28]
  16747. 8006aac: 4413 add r3, r2
  16748. 8006aae: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16749. 8006ab2: 691a ldr r2, [r3, #16]
  16750. 8006ab4: 69bb ldr r3, [r7, #24]
  16751. 8006ab6: 0159 lsls r1, r3, #5
  16752. 8006ab8: 69fb ldr r3, [r7, #28]
  16753. 8006aba: 440b add r3, r1
  16754. 8006abc: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16755. 8006ac0: 4619 mov r1, r3
  16756. 8006ac2: 4b5a ldr r3, [pc, #360] ; (8006c2c <USB_EPStartXfer+0x490>)
  16757. 8006ac4: 4013 ands r3, r2
  16758. 8006ac6: 610b str r3, [r1, #16]
  16759. if (ep->xfer_len == 0U)
  16760. 8006ac8: 68bb ldr r3, [r7, #8]
  16761. 8006aca: 695b ldr r3, [r3, #20]
  16762. 8006acc: 2b00 cmp r3, #0
  16763. 8006ace: d123 bne.n 8006b18 <USB_EPStartXfer+0x37c>
  16764. {
  16765. USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
  16766. 8006ad0: 69bb ldr r3, [r7, #24]
  16767. 8006ad2: 015a lsls r2, r3, #5
  16768. 8006ad4: 69fb ldr r3, [r7, #28]
  16769. 8006ad6: 4413 add r3, r2
  16770. 8006ad8: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16771. 8006adc: 691a ldr r2, [r3, #16]
  16772. 8006ade: 68bb ldr r3, [r7, #8]
  16773. 8006ae0: 689b ldr r3, [r3, #8]
  16774. 8006ae2: f3c3 0312 ubfx r3, r3, #0, #19
  16775. 8006ae6: 69b9 ldr r1, [r7, #24]
  16776. 8006ae8: 0148 lsls r0, r1, #5
  16777. 8006aea: 69f9 ldr r1, [r7, #28]
  16778. 8006aec: 4401 add r1, r0
  16779. 8006aee: f501 6130 add.w r1, r1, #2816 ; 0xb00
  16780. 8006af2: 4313 orrs r3, r2
  16781. 8006af4: 610b str r3, [r1, #16]
  16782. USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
  16783. 8006af6: 69bb ldr r3, [r7, #24]
  16784. 8006af8: 015a lsls r2, r3, #5
  16785. 8006afa: 69fb ldr r3, [r7, #28]
  16786. 8006afc: 4413 add r3, r2
  16787. 8006afe: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16788. 8006b02: 691b ldr r3, [r3, #16]
  16789. 8006b04: 69ba ldr r2, [r7, #24]
  16790. 8006b06: 0151 lsls r1, r2, #5
  16791. 8006b08: 69fa ldr r2, [r7, #28]
  16792. 8006b0a: 440a add r2, r1
  16793. 8006b0c: f502 6230 add.w r2, r2, #2816 ; 0xb00
  16794. 8006b10: f443 2300 orr.w r3, r3, #524288 ; 0x80000
  16795. 8006b14: 6113 str r3, [r2, #16]
  16796. 8006b16: e033 b.n 8006b80 <USB_EPStartXfer+0x3e4>
  16797. }
  16798. else
  16799. {
  16800. pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
  16801. 8006b18: 68bb ldr r3, [r7, #8]
  16802. 8006b1a: 695a ldr r2, [r3, #20]
  16803. 8006b1c: 68bb ldr r3, [r7, #8]
  16804. 8006b1e: 689b ldr r3, [r3, #8]
  16805. 8006b20: 4413 add r3, r2
  16806. 8006b22: 1e5a subs r2, r3, #1
  16807. 8006b24: 68bb ldr r3, [r7, #8]
  16808. 8006b26: 689b ldr r3, [r3, #8]
  16809. 8006b28: fbb2 f3f3 udiv r3, r2, r3
  16810. 8006b2c: 82fb strh r3, [r7, #22]
  16811. USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
  16812. 8006b2e: 69bb ldr r3, [r7, #24]
  16813. 8006b30: 015a lsls r2, r3, #5
  16814. 8006b32: 69fb ldr r3, [r7, #28]
  16815. 8006b34: 4413 add r3, r2
  16816. 8006b36: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16817. 8006b3a: 691a ldr r2, [r3, #16]
  16818. 8006b3c: 8afb ldrh r3, [r7, #22]
  16819. 8006b3e: 04d9 lsls r1, r3, #19
  16820. 8006b40: 4b3b ldr r3, [pc, #236] ; (8006c30 <USB_EPStartXfer+0x494>)
  16821. 8006b42: 400b ands r3, r1
  16822. 8006b44: 69b9 ldr r1, [r7, #24]
  16823. 8006b46: 0148 lsls r0, r1, #5
  16824. 8006b48: 69f9 ldr r1, [r7, #28]
  16825. 8006b4a: 4401 add r1, r0
  16826. 8006b4c: f501 6130 add.w r1, r1, #2816 ; 0xb00
  16827. 8006b50: 4313 orrs r3, r2
  16828. 8006b52: 610b str r3, [r1, #16]
  16829. USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
  16830. 8006b54: 69bb ldr r3, [r7, #24]
  16831. 8006b56: 015a lsls r2, r3, #5
  16832. 8006b58: 69fb ldr r3, [r7, #28]
  16833. 8006b5a: 4413 add r3, r2
  16834. 8006b5c: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16835. 8006b60: 691a ldr r2, [r3, #16]
  16836. 8006b62: 68bb ldr r3, [r7, #8]
  16837. 8006b64: 689b ldr r3, [r3, #8]
  16838. 8006b66: 8af9 ldrh r1, [r7, #22]
  16839. 8006b68: fb01 f303 mul.w r3, r1, r3
  16840. 8006b6c: f3c3 0312 ubfx r3, r3, #0, #19
  16841. 8006b70: 69b9 ldr r1, [r7, #24]
  16842. 8006b72: 0148 lsls r0, r1, #5
  16843. 8006b74: 69f9 ldr r1, [r7, #28]
  16844. 8006b76: 4401 add r1, r0
  16845. 8006b78: f501 6130 add.w r1, r1, #2816 ; 0xb00
  16846. 8006b7c: 4313 orrs r3, r2
  16847. 8006b7e: 610b str r3, [r1, #16]
  16848. }
  16849. if (dma == 1U)
  16850. 8006b80: 79fb ldrb r3, [r7, #7]
  16851. 8006b82: 2b01 cmp r3, #1
  16852. 8006b84: d10d bne.n 8006ba2 <USB_EPStartXfer+0x406>
  16853. {
  16854. if ((uint32_t)ep->xfer_buff != 0U)
  16855. 8006b86: 68bb ldr r3, [r7, #8]
  16856. 8006b88: 68db ldr r3, [r3, #12]
  16857. 8006b8a: 2b00 cmp r3, #0
  16858. 8006b8c: d009 beq.n 8006ba2 <USB_EPStartXfer+0x406>
  16859. {
  16860. USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
  16861. 8006b8e: 68bb ldr r3, [r7, #8]
  16862. 8006b90: 68d9 ldr r1, [r3, #12]
  16863. 8006b92: 69bb ldr r3, [r7, #24]
  16864. 8006b94: 015a lsls r2, r3, #5
  16865. 8006b96: 69fb ldr r3, [r7, #28]
  16866. 8006b98: 4413 add r3, r2
  16867. 8006b9a: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16868. 8006b9e: 460a mov r2, r1
  16869. 8006ba0: 615a str r2, [r3, #20]
  16870. }
  16871. }
  16872. if (ep->type == EP_TYPE_ISOC)
  16873. 8006ba2: 68bb ldr r3, [r7, #8]
  16874. 8006ba4: 78db ldrb r3, [r3, #3]
  16875. 8006ba6: 2b01 cmp r3, #1
  16876. 8006ba8: d128 bne.n 8006bfc <USB_EPStartXfer+0x460>
  16877. {
  16878. if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
  16879. 8006baa: 69fb ldr r3, [r7, #28]
  16880. 8006bac: f503 6300 add.w r3, r3, #2048 ; 0x800
  16881. 8006bb0: 689b ldr r3, [r3, #8]
  16882. 8006bb2: f403 7380 and.w r3, r3, #256 ; 0x100
  16883. 8006bb6: 2b00 cmp r3, #0
  16884. 8006bb8: d110 bne.n 8006bdc <USB_EPStartXfer+0x440>
  16885. {
  16886. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
  16887. 8006bba: 69bb ldr r3, [r7, #24]
  16888. 8006bbc: 015a lsls r2, r3, #5
  16889. 8006bbe: 69fb ldr r3, [r7, #28]
  16890. 8006bc0: 4413 add r3, r2
  16891. 8006bc2: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16892. 8006bc6: 681b ldr r3, [r3, #0]
  16893. 8006bc8: 69ba ldr r2, [r7, #24]
  16894. 8006bca: 0151 lsls r1, r2, #5
  16895. 8006bcc: 69fa ldr r2, [r7, #28]
  16896. 8006bce: 440a add r2, r1
  16897. 8006bd0: f502 6230 add.w r2, r2, #2816 ; 0xb00
  16898. 8006bd4: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
  16899. 8006bd8: 6013 str r3, [r2, #0]
  16900. 8006bda: e00f b.n 8006bfc <USB_EPStartXfer+0x460>
  16901. }
  16902. else
  16903. {
  16904. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
  16905. 8006bdc: 69bb ldr r3, [r7, #24]
  16906. 8006bde: 015a lsls r2, r3, #5
  16907. 8006be0: 69fb ldr r3, [r7, #28]
  16908. 8006be2: 4413 add r3, r2
  16909. 8006be4: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16910. 8006be8: 681b ldr r3, [r3, #0]
  16911. 8006bea: 69ba ldr r2, [r7, #24]
  16912. 8006bec: 0151 lsls r1, r2, #5
  16913. 8006bee: 69fa ldr r2, [r7, #28]
  16914. 8006bf0: 440a add r2, r1
  16915. 8006bf2: f502 6230 add.w r2, r2, #2816 ; 0xb00
  16916. 8006bf6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
  16917. 8006bfa: 6013 str r3, [r2, #0]
  16918. }
  16919. }
  16920. /* EP enable */
  16921. USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
  16922. 8006bfc: 69bb ldr r3, [r7, #24]
  16923. 8006bfe: 015a lsls r2, r3, #5
  16924. 8006c00: 69fb ldr r3, [r7, #28]
  16925. 8006c02: 4413 add r3, r2
  16926. 8006c04: f503 6330 add.w r3, r3, #2816 ; 0xb00
  16927. 8006c08: 681b ldr r3, [r3, #0]
  16928. 8006c0a: 69ba ldr r2, [r7, #24]
  16929. 8006c0c: 0151 lsls r1, r2, #5
  16930. 8006c0e: 69fa ldr r2, [r7, #28]
  16931. 8006c10: 440a add r2, r1
  16932. 8006c12: f502 6230 add.w r2, r2, #2816 ; 0xb00
  16933. 8006c16: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000
  16934. 8006c1a: 6013 str r3, [r2, #0]
  16935. }
  16936. return HAL_OK;
  16937. 8006c1c: 2300 movs r3, #0
  16938. }
  16939. 8006c1e: 4618 mov r0, r3
  16940. 8006c20: 3720 adds r7, #32
  16941. 8006c22: 46bd mov sp, r7
  16942. 8006c24: bd80 pop {r7, pc}
  16943. 8006c26: bf00 nop
  16944. 8006c28: fff80000 .word 0xfff80000
  16945. 8006c2c: e007ffff .word 0xe007ffff
  16946. 8006c30: 1ff80000 .word 0x1ff80000
  16947. 08006c34 <USB_EP0StartXfer>:
  16948. * 0 : DMA feature not used
  16949. * 1 : DMA feature used
  16950. * @retval HAL status
  16951. */
  16952. HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
  16953. {
  16954. 8006c34: b480 push {r7}
  16955. 8006c36: b087 sub sp, #28
  16956. 8006c38: af00 add r7, sp, #0
  16957. 8006c3a: 60f8 str r0, [r7, #12]
  16958. 8006c3c: 60b9 str r1, [r7, #8]
  16959. 8006c3e: 4613 mov r3, r2
  16960. 8006c40: 71fb strb r3, [r7, #7]
  16961. uint32_t USBx_BASE = (uint32_t)USBx;
  16962. 8006c42: 68fb ldr r3, [r7, #12]
  16963. 8006c44: 617b str r3, [r7, #20]
  16964. uint32_t epnum = (uint32_t)ep->num;
  16965. 8006c46: 68bb ldr r3, [r7, #8]
  16966. 8006c48: 781b ldrb r3, [r3, #0]
  16967. 8006c4a: 613b str r3, [r7, #16]
  16968. /* IN endpoint */
  16969. if (ep->is_in == 1U)
  16970. 8006c4c: 68bb ldr r3, [r7, #8]
  16971. 8006c4e: 785b ldrb r3, [r3, #1]
  16972. 8006c50: 2b01 cmp r3, #1
  16973. 8006c52: f040 80cd bne.w 8006df0 <USB_EP0StartXfer+0x1bc>
  16974. {
  16975. /* Zero Length Packet? */
  16976. if (ep->xfer_len == 0U)
  16977. 8006c56: 68bb ldr r3, [r7, #8]
  16978. 8006c58: 695b ldr r3, [r3, #20]
  16979. 8006c5a: 2b00 cmp r3, #0
  16980. 8006c5c: d132 bne.n 8006cc4 <USB_EP0StartXfer+0x90>
  16981. {
  16982. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
  16983. 8006c5e: 693b ldr r3, [r7, #16]
  16984. 8006c60: 015a lsls r2, r3, #5
  16985. 8006c62: 697b ldr r3, [r7, #20]
  16986. 8006c64: 4413 add r3, r2
  16987. 8006c66: f503 6310 add.w r3, r3, #2304 ; 0x900
  16988. 8006c6a: 691a ldr r2, [r3, #16]
  16989. 8006c6c: 693b ldr r3, [r7, #16]
  16990. 8006c6e: 0159 lsls r1, r3, #5
  16991. 8006c70: 697b ldr r3, [r7, #20]
  16992. 8006c72: 440b add r3, r1
  16993. 8006c74: f503 6310 add.w r3, r3, #2304 ; 0x900
  16994. 8006c78: 4619 mov r1, r3
  16995. 8006c7a: 4b98 ldr r3, [pc, #608] ; (8006edc <USB_EP0StartXfer+0x2a8>)
  16996. 8006c7c: 4013 ands r3, r2
  16997. 8006c7e: 610b str r3, [r1, #16]
  16998. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
  16999. 8006c80: 693b ldr r3, [r7, #16]
  17000. 8006c82: 015a lsls r2, r3, #5
  17001. 8006c84: 697b ldr r3, [r7, #20]
  17002. 8006c86: 4413 add r3, r2
  17003. 8006c88: f503 6310 add.w r3, r3, #2304 ; 0x900
  17004. 8006c8c: 691b ldr r3, [r3, #16]
  17005. 8006c8e: 693a ldr r2, [r7, #16]
  17006. 8006c90: 0151 lsls r1, r2, #5
  17007. 8006c92: 697a ldr r2, [r7, #20]
  17008. 8006c94: 440a add r2, r1
  17009. 8006c96: f502 6210 add.w r2, r2, #2304 ; 0x900
  17010. 8006c9a: f443 2300 orr.w r3, r3, #524288 ; 0x80000
  17011. 8006c9e: 6113 str r3, [r2, #16]
  17012. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
  17013. 8006ca0: 693b ldr r3, [r7, #16]
  17014. 8006ca2: 015a lsls r2, r3, #5
  17015. 8006ca4: 697b ldr r3, [r7, #20]
  17016. 8006ca6: 4413 add r3, r2
  17017. 8006ca8: f503 6310 add.w r3, r3, #2304 ; 0x900
  17018. 8006cac: 691a ldr r2, [r3, #16]
  17019. 8006cae: 693b ldr r3, [r7, #16]
  17020. 8006cb0: 0159 lsls r1, r3, #5
  17021. 8006cb2: 697b ldr r3, [r7, #20]
  17022. 8006cb4: 440b add r3, r1
  17023. 8006cb6: f503 6310 add.w r3, r3, #2304 ; 0x900
  17024. 8006cba: 4619 mov r1, r3
  17025. 8006cbc: 4b88 ldr r3, [pc, #544] ; (8006ee0 <USB_EP0StartXfer+0x2ac>)
  17026. 8006cbe: 4013 ands r3, r2
  17027. 8006cc0: 610b str r3, [r1, #16]
  17028. 8006cc2: e04e b.n 8006d62 <USB_EP0StartXfer+0x12e>
  17029. /* Program the transfer size and packet count
  17030. * as follows: xfersize = N * maxpacket +
  17031. * short_packet pktcnt = N + (short_packet
  17032. * exist ? 1 : 0)
  17033. */
  17034. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
  17035. 8006cc4: 693b ldr r3, [r7, #16]
  17036. 8006cc6: 015a lsls r2, r3, #5
  17037. 8006cc8: 697b ldr r3, [r7, #20]
  17038. 8006cca: 4413 add r3, r2
  17039. 8006ccc: f503 6310 add.w r3, r3, #2304 ; 0x900
  17040. 8006cd0: 691a ldr r2, [r3, #16]
  17041. 8006cd2: 693b ldr r3, [r7, #16]
  17042. 8006cd4: 0159 lsls r1, r3, #5
  17043. 8006cd6: 697b ldr r3, [r7, #20]
  17044. 8006cd8: 440b add r3, r1
  17045. 8006cda: f503 6310 add.w r3, r3, #2304 ; 0x900
  17046. 8006cde: 4619 mov r1, r3
  17047. 8006ce0: 4b7f ldr r3, [pc, #508] ; (8006ee0 <USB_EP0StartXfer+0x2ac>)
  17048. 8006ce2: 4013 ands r3, r2
  17049. 8006ce4: 610b str r3, [r1, #16]
  17050. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
  17051. 8006ce6: 693b ldr r3, [r7, #16]
  17052. 8006ce8: 015a lsls r2, r3, #5
  17053. 8006cea: 697b ldr r3, [r7, #20]
  17054. 8006cec: 4413 add r3, r2
  17055. 8006cee: f503 6310 add.w r3, r3, #2304 ; 0x900
  17056. 8006cf2: 691a ldr r2, [r3, #16]
  17057. 8006cf4: 693b ldr r3, [r7, #16]
  17058. 8006cf6: 0159 lsls r1, r3, #5
  17059. 8006cf8: 697b ldr r3, [r7, #20]
  17060. 8006cfa: 440b add r3, r1
  17061. 8006cfc: f503 6310 add.w r3, r3, #2304 ; 0x900
  17062. 8006d00: 4619 mov r1, r3
  17063. 8006d02: 4b76 ldr r3, [pc, #472] ; (8006edc <USB_EP0StartXfer+0x2a8>)
  17064. 8006d04: 4013 ands r3, r2
  17065. 8006d06: 610b str r3, [r1, #16]
  17066. if (ep->xfer_len > ep->maxpacket)
  17067. 8006d08: 68bb ldr r3, [r7, #8]
  17068. 8006d0a: 695a ldr r2, [r3, #20]
  17069. 8006d0c: 68bb ldr r3, [r7, #8]
  17070. 8006d0e: 689b ldr r3, [r3, #8]
  17071. 8006d10: 429a cmp r2, r3
  17072. 8006d12: d903 bls.n 8006d1c <USB_EP0StartXfer+0xe8>
  17073. {
  17074. ep->xfer_len = ep->maxpacket;
  17075. 8006d14: 68bb ldr r3, [r7, #8]
  17076. 8006d16: 689a ldr r2, [r3, #8]
  17077. 8006d18: 68bb ldr r3, [r7, #8]
  17078. 8006d1a: 615a str r2, [r3, #20]
  17079. }
  17080. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
  17081. 8006d1c: 693b ldr r3, [r7, #16]
  17082. 8006d1e: 015a lsls r2, r3, #5
  17083. 8006d20: 697b ldr r3, [r7, #20]
  17084. 8006d22: 4413 add r3, r2
  17085. 8006d24: f503 6310 add.w r3, r3, #2304 ; 0x900
  17086. 8006d28: 691b ldr r3, [r3, #16]
  17087. 8006d2a: 693a ldr r2, [r7, #16]
  17088. 8006d2c: 0151 lsls r1, r2, #5
  17089. 8006d2e: 697a ldr r2, [r7, #20]
  17090. 8006d30: 440a add r2, r1
  17091. 8006d32: f502 6210 add.w r2, r2, #2304 ; 0x900
  17092. 8006d36: f443 2300 orr.w r3, r3, #524288 ; 0x80000
  17093. 8006d3a: 6113 str r3, [r2, #16]
  17094. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
  17095. 8006d3c: 693b ldr r3, [r7, #16]
  17096. 8006d3e: 015a lsls r2, r3, #5
  17097. 8006d40: 697b ldr r3, [r7, #20]
  17098. 8006d42: 4413 add r3, r2
  17099. 8006d44: f503 6310 add.w r3, r3, #2304 ; 0x900
  17100. 8006d48: 691a ldr r2, [r3, #16]
  17101. 8006d4a: 68bb ldr r3, [r7, #8]
  17102. 8006d4c: 695b ldr r3, [r3, #20]
  17103. 8006d4e: f3c3 0312 ubfx r3, r3, #0, #19
  17104. 8006d52: 6939 ldr r1, [r7, #16]
  17105. 8006d54: 0148 lsls r0, r1, #5
  17106. 8006d56: 6979 ldr r1, [r7, #20]
  17107. 8006d58: 4401 add r1, r0
  17108. 8006d5a: f501 6110 add.w r1, r1, #2304 ; 0x900
  17109. 8006d5e: 4313 orrs r3, r2
  17110. 8006d60: 610b str r3, [r1, #16]
  17111. }
  17112. if (dma == 1U)
  17113. 8006d62: 79fb ldrb r3, [r7, #7]
  17114. 8006d64: 2b01 cmp r3, #1
  17115. 8006d66: d11e bne.n 8006da6 <USB_EP0StartXfer+0x172>
  17116. {
  17117. if ((uint32_t)ep->dma_addr != 0U)
  17118. 8006d68: 68bb ldr r3, [r7, #8]
  17119. 8006d6a: 691b ldr r3, [r3, #16]
  17120. 8006d6c: 2b00 cmp r3, #0
  17121. 8006d6e: d009 beq.n 8006d84 <USB_EP0StartXfer+0x150>
  17122. {
  17123. USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
  17124. 8006d70: 693b ldr r3, [r7, #16]
  17125. 8006d72: 015a lsls r2, r3, #5
  17126. 8006d74: 697b ldr r3, [r7, #20]
  17127. 8006d76: 4413 add r3, r2
  17128. 8006d78: f503 6310 add.w r3, r3, #2304 ; 0x900
  17129. 8006d7c: 461a mov r2, r3
  17130. 8006d7e: 68bb ldr r3, [r7, #8]
  17131. 8006d80: 691b ldr r3, [r3, #16]
  17132. 8006d82: 6153 str r3, [r2, #20]
  17133. }
  17134. /* EP enable, IN data in FIFO */
  17135. USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
  17136. 8006d84: 693b ldr r3, [r7, #16]
  17137. 8006d86: 015a lsls r2, r3, #5
  17138. 8006d88: 697b ldr r3, [r7, #20]
  17139. 8006d8a: 4413 add r3, r2
  17140. 8006d8c: f503 6310 add.w r3, r3, #2304 ; 0x900
  17141. 8006d90: 681b ldr r3, [r3, #0]
  17142. 8006d92: 693a ldr r2, [r7, #16]
  17143. 8006d94: 0151 lsls r1, r2, #5
  17144. 8006d96: 697a ldr r2, [r7, #20]
  17145. 8006d98: 440a add r2, r1
  17146. 8006d9a: f502 6210 add.w r2, r2, #2304 ; 0x900
  17147. 8006d9e: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000
  17148. 8006da2: 6013 str r3, [r2, #0]
  17149. 8006da4: e092 b.n 8006ecc <USB_EP0StartXfer+0x298>
  17150. }
  17151. else
  17152. {
  17153. /* EP enable, IN data in FIFO */
  17154. USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
  17155. 8006da6: 693b ldr r3, [r7, #16]
  17156. 8006da8: 015a lsls r2, r3, #5
  17157. 8006daa: 697b ldr r3, [r7, #20]
  17158. 8006dac: 4413 add r3, r2
  17159. 8006dae: f503 6310 add.w r3, r3, #2304 ; 0x900
  17160. 8006db2: 681b ldr r3, [r3, #0]
  17161. 8006db4: 693a ldr r2, [r7, #16]
  17162. 8006db6: 0151 lsls r1, r2, #5
  17163. 8006db8: 697a ldr r2, [r7, #20]
  17164. 8006dba: 440a add r2, r1
  17165. 8006dbc: f502 6210 add.w r2, r2, #2304 ; 0x900
  17166. 8006dc0: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000
  17167. 8006dc4: 6013 str r3, [r2, #0]
  17168. /* Enable the Tx FIFO Empty Interrupt for this EP */
  17169. if (ep->xfer_len > 0U)
  17170. 8006dc6: 68bb ldr r3, [r7, #8]
  17171. 8006dc8: 695b ldr r3, [r3, #20]
  17172. 8006dca: 2b00 cmp r3, #0
  17173. 8006dcc: d07e beq.n 8006ecc <USB_EP0StartXfer+0x298>
  17174. {
  17175. USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
  17176. 8006dce: 697b ldr r3, [r7, #20]
  17177. 8006dd0: f503 6300 add.w r3, r3, #2048 ; 0x800
  17178. 8006dd4: 6b5a ldr r2, [r3, #52] ; 0x34
  17179. 8006dd6: 68bb ldr r3, [r7, #8]
  17180. 8006dd8: 781b ldrb r3, [r3, #0]
  17181. 8006dda: f003 030f and.w r3, r3, #15
  17182. 8006dde: 2101 movs r1, #1
  17183. 8006de0: fa01 f303 lsl.w r3, r1, r3
  17184. 8006de4: 6979 ldr r1, [r7, #20]
  17185. 8006de6: f501 6100 add.w r1, r1, #2048 ; 0x800
  17186. 8006dea: 4313 orrs r3, r2
  17187. 8006dec: 634b str r3, [r1, #52] ; 0x34
  17188. 8006dee: e06d b.n 8006ecc <USB_EP0StartXfer+0x298>
  17189. {
  17190. /* Program the transfer size and packet count as follows:
  17191. * pktcnt = N
  17192. * xfersize = N * maxpacket
  17193. */
  17194. USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
  17195. 8006df0: 693b ldr r3, [r7, #16]
  17196. 8006df2: 015a lsls r2, r3, #5
  17197. 8006df4: 697b ldr r3, [r7, #20]
  17198. 8006df6: 4413 add r3, r2
  17199. 8006df8: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17200. 8006dfc: 691a ldr r2, [r3, #16]
  17201. 8006dfe: 693b ldr r3, [r7, #16]
  17202. 8006e00: 0159 lsls r1, r3, #5
  17203. 8006e02: 697b ldr r3, [r7, #20]
  17204. 8006e04: 440b add r3, r1
  17205. 8006e06: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17206. 8006e0a: 4619 mov r1, r3
  17207. 8006e0c: 4b34 ldr r3, [pc, #208] ; (8006ee0 <USB_EP0StartXfer+0x2ac>)
  17208. 8006e0e: 4013 ands r3, r2
  17209. 8006e10: 610b str r3, [r1, #16]
  17210. USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
  17211. 8006e12: 693b ldr r3, [r7, #16]
  17212. 8006e14: 015a lsls r2, r3, #5
  17213. 8006e16: 697b ldr r3, [r7, #20]
  17214. 8006e18: 4413 add r3, r2
  17215. 8006e1a: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17216. 8006e1e: 691a ldr r2, [r3, #16]
  17217. 8006e20: 693b ldr r3, [r7, #16]
  17218. 8006e22: 0159 lsls r1, r3, #5
  17219. 8006e24: 697b ldr r3, [r7, #20]
  17220. 8006e26: 440b add r3, r1
  17221. 8006e28: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17222. 8006e2c: 4619 mov r1, r3
  17223. 8006e2e: 4b2b ldr r3, [pc, #172] ; (8006edc <USB_EP0StartXfer+0x2a8>)
  17224. 8006e30: 4013 ands r3, r2
  17225. 8006e32: 610b str r3, [r1, #16]
  17226. if (ep->xfer_len > 0U)
  17227. 8006e34: 68bb ldr r3, [r7, #8]
  17228. 8006e36: 695b ldr r3, [r3, #20]
  17229. 8006e38: 2b00 cmp r3, #0
  17230. 8006e3a: d003 beq.n 8006e44 <USB_EP0StartXfer+0x210>
  17231. {
  17232. ep->xfer_len = ep->maxpacket;
  17233. 8006e3c: 68bb ldr r3, [r7, #8]
  17234. 8006e3e: 689a ldr r2, [r3, #8]
  17235. 8006e40: 68bb ldr r3, [r7, #8]
  17236. 8006e42: 615a str r2, [r3, #20]
  17237. }
  17238. USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
  17239. 8006e44: 693b ldr r3, [r7, #16]
  17240. 8006e46: 015a lsls r2, r3, #5
  17241. 8006e48: 697b ldr r3, [r7, #20]
  17242. 8006e4a: 4413 add r3, r2
  17243. 8006e4c: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17244. 8006e50: 691b ldr r3, [r3, #16]
  17245. 8006e52: 693a ldr r2, [r7, #16]
  17246. 8006e54: 0151 lsls r1, r2, #5
  17247. 8006e56: 697a ldr r2, [r7, #20]
  17248. 8006e58: 440a add r2, r1
  17249. 8006e5a: f502 6230 add.w r2, r2, #2816 ; 0xb00
  17250. 8006e5e: f443 2300 orr.w r3, r3, #524288 ; 0x80000
  17251. 8006e62: 6113 str r3, [r2, #16]
  17252. USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
  17253. 8006e64: 693b ldr r3, [r7, #16]
  17254. 8006e66: 015a lsls r2, r3, #5
  17255. 8006e68: 697b ldr r3, [r7, #20]
  17256. 8006e6a: 4413 add r3, r2
  17257. 8006e6c: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17258. 8006e70: 691a ldr r2, [r3, #16]
  17259. 8006e72: 68bb ldr r3, [r7, #8]
  17260. 8006e74: 689b ldr r3, [r3, #8]
  17261. 8006e76: f3c3 0312 ubfx r3, r3, #0, #19
  17262. 8006e7a: 6939 ldr r1, [r7, #16]
  17263. 8006e7c: 0148 lsls r0, r1, #5
  17264. 8006e7e: 6979 ldr r1, [r7, #20]
  17265. 8006e80: 4401 add r1, r0
  17266. 8006e82: f501 6130 add.w r1, r1, #2816 ; 0xb00
  17267. 8006e86: 4313 orrs r3, r2
  17268. 8006e88: 610b str r3, [r1, #16]
  17269. if (dma == 1U)
  17270. 8006e8a: 79fb ldrb r3, [r7, #7]
  17271. 8006e8c: 2b01 cmp r3, #1
  17272. 8006e8e: d10d bne.n 8006eac <USB_EP0StartXfer+0x278>
  17273. {
  17274. if ((uint32_t)ep->xfer_buff != 0U)
  17275. 8006e90: 68bb ldr r3, [r7, #8]
  17276. 8006e92: 68db ldr r3, [r3, #12]
  17277. 8006e94: 2b00 cmp r3, #0
  17278. 8006e96: d009 beq.n 8006eac <USB_EP0StartXfer+0x278>
  17279. {
  17280. USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
  17281. 8006e98: 68bb ldr r3, [r7, #8]
  17282. 8006e9a: 68d9 ldr r1, [r3, #12]
  17283. 8006e9c: 693b ldr r3, [r7, #16]
  17284. 8006e9e: 015a lsls r2, r3, #5
  17285. 8006ea0: 697b ldr r3, [r7, #20]
  17286. 8006ea2: 4413 add r3, r2
  17287. 8006ea4: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17288. 8006ea8: 460a mov r2, r1
  17289. 8006eaa: 615a str r2, [r3, #20]
  17290. }
  17291. }
  17292. /* EP enable */
  17293. USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
  17294. 8006eac: 693b ldr r3, [r7, #16]
  17295. 8006eae: 015a lsls r2, r3, #5
  17296. 8006eb0: 697b ldr r3, [r7, #20]
  17297. 8006eb2: 4413 add r3, r2
  17298. 8006eb4: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17299. 8006eb8: 681b ldr r3, [r3, #0]
  17300. 8006eba: 693a ldr r2, [r7, #16]
  17301. 8006ebc: 0151 lsls r1, r2, #5
  17302. 8006ebe: 697a ldr r2, [r7, #20]
  17303. 8006ec0: 440a add r2, r1
  17304. 8006ec2: f502 6230 add.w r2, r2, #2816 ; 0xb00
  17305. 8006ec6: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000
  17306. 8006eca: 6013 str r3, [r2, #0]
  17307. }
  17308. return HAL_OK;
  17309. 8006ecc: 2300 movs r3, #0
  17310. }
  17311. 8006ece: 4618 mov r0, r3
  17312. 8006ed0: 371c adds r7, #28
  17313. 8006ed2: 46bd mov sp, r7
  17314. 8006ed4: f85d 7b04 ldr.w r7, [sp], #4
  17315. 8006ed8: 4770 bx lr
  17316. 8006eda: bf00 nop
  17317. 8006edc: e007ffff .word 0xe007ffff
  17318. 8006ee0: fff80000 .word 0xfff80000
  17319. 08006ee4 <USB_WritePacket>:
  17320. * 1 : DMA feature used
  17321. * @retval HAL status
  17322. */
  17323. HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
  17324. uint8_t ch_ep_num, uint16_t len, uint8_t dma)
  17325. {
  17326. 8006ee4: b480 push {r7}
  17327. 8006ee6: b089 sub sp, #36 ; 0x24
  17328. 8006ee8: af00 add r7, sp, #0
  17329. 8006eea: 60f8 str r0, [r7, #12]
  17330. 8006eec: 60b9 str r1, [r7, #8]
  17331. 8006eee: 4611 mov r1, r2
  17332. 8006ef0: 461a mov r2, r3
  17333. 8006ef2: 460b mov r3, r1
  17334. 8006ef4: 71fb strb r3, [r7, #7]
  17335. 8006ef6: 4613 mov r3, r2
  17336. 8006ef8: 80bb strh r3, [r7, #4]
  17337. uint32_t USBx_BASE = (uint32_t)USBx;
  17338. 8006efa: 68fb ldr r3, [r7, #12]
  17339. 8006efc: 617b str r3, [r7, #20]
  17340. uint8_t *pSrc = src;
  17341. 8006efe: 68bb ldr r3, [r7, #8]
  17342. 8006f00: 61fb str r3, [r7, #28]
  17343. uint32_t count32b;
  17344. uint32_t i;
  17345. if (dma == 0U)
  17346. 8006f02: f897 3028 ldrb.w r3, [r7, #40] ; 0x28
  17347. 8006f06: 2b00 cmp r3, #0
  17348. 8006f08: d123 bne.n 8006f52 <USB_WritePacket+0x6e>
  17349. {
  17350. count32b = ((uint32_t)len + 3U) / 4U;
  17351. 8006f0a: 88bb ldrh r3, [r7, #4]
  17352. 8006f0c: 3303 adds r3, #3
  17353. 8006f0e: 089b lsrs r3, r3, #2
  17354. 8006f10: 613b str r3, [r7, #16]
  17355. for (i = 0U; i < count32b; i++)
  17356. 8006f12: 2300 movs r3, #0
  17357. 8006f14: 61bb str r3, [r7, #24]
  17358. 8006f16: e018 b.n 8006f4a <USB_WritePacket+0x66>
  17359. {
  17360. USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
  17361. 8006f18: 79fb ldrb r3, [r7, #7]
  17362. 8006f1a: 031a lsls r2, r3, #12
  17363. 8006f1c: 697b ldr r3, [r7, #20]
  17364. 8006f1e: 4413 add r3, r2
  17365. 8006f20: f503 5380 add.w r3, r3, #4096 ; 0x1000
  17366. 8006f24: 461a mov r2, r3
  17367. 8006f26: 69fb ldr r3, [r7, #28]
  17368. 8006f28: 681b ldr r3, [r3, #0]
  17369. 8006f2a: 6013 str r3, [r2, #0]
  17370. pSrc++;
  17371. 8006f2c: 69fb ldr r3, [r7, #28]
  17372. 8006f2e: 3301 adds r3, #1
  17373. 8006f30: 61fb str r3, [r7, #28]
  17374. pSrc++;
  17375. 8006f32: 69fb ldr r3, [r7, #28]
  17376. 8006f34: 3301 adds r3, #1
  17377. 8006f36: 61fb str r3, [r7, #28]
  17378. pSrc++;
  17379. 8006f38: 69fb ldr r3, [r7, #28]
  17380. 8006f3a: 3301 adds r3, #1
  17381. 8006f3c: 61fb str r3, [r7, #28]
  17382. pSrc++;
  17383. 8006f3e: 69fb ldr r3, [r7, #28]
  17384. 8006f40: 3301 adds r3, #1
  17385. 8006f42: 61fb str r3, [r7, #28]
  17386. for (i = 0U; i < count32b; i++)
  17387. 8006f44: 69bb ldr r3, [r7, #24]
  17388. 8006f46: 3301 adds r3, #1
  17389. 8006f48: 61bb str r3, [r7, #24]
  17390. 8006f4a: 69ba ldr r2, [r7, #24]
  17391. 8006f4c: 693b ldr r3, [r7, #16]
  17392. 8006f4e: 429a cmp r2, r3
  17393. 8006f50: d3e2 bcc.n 8006f18 <USB_WritePacket+0x34>
  17394. }
  17395. }
  17396. return HAL_OK;
  17397. 8006f52: 2300 movs r3, #0
  17398. }
  17399. 8006f54: 4618 mov r0, r3
  17400. 8006f56: 3724 adds r7, #36 ; 0x24
  17401. 8006f58: 46bd mov sp, r7
  17402. 8006f5a: f85d 7b04 ldr.w r7, [sp], #4
  17403. 8006f5e: 4770 bx lr
  17404. 08006f60 <USB_ReadPacket>:
  17405. * @param dest source pointer
  17406. * @param len Number of bytes to read
  17407. * @retval pointer to destination buffer
  17408. */
  17409. void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
  17410. {
  17411. 8006f60: b480 push {r7}
  17412. 8006f62: b08b sub sp, #44 ; 0x2c
  17413. 8006f64: af00 add r7, sp, #0
  17414. 8006f66: 60f8 str r0, [r7, #12]
  17415. 8006f68: 60b9 str r1, [r7, #8]
  17416. 8006f6a: 4613 mov r3, r2
  17417. 8006f6c: 80fb strh r3, [r7, #6]
  17418. uint32_t USBx_BASE = (uint32_t)USBx;
  17419. 8006f6e: 68fb ldr r3, [r7, #12]
  17420. 8006f70: 61bb str r3, [r7, #24]
  17421. uint8_t *pDest = dest;
  17422. 8006f72: 68bb ldr r3, [r7, #8]
  17423. 8006f74: 627b str r3, [r7, #36] ; 0x24
  17424. uint32_t pData;
  17425. uint32_t i;
  17426. uint32_t count32b = (uint32_t)len >> 2U;
  17427. 8006f76: 88fb ldrh r3, [r7, #6]
  17428. 8006f78: 089b lsrs r3, r3, #2
  17429. 8006f7a: b29b uxth r3, r3
  17430. 8006f7c: 617b str r3, [r7, #20]
  17431. uint16_t remaining_bytes = len % 4U;
  17432. 8006f7e: 88fb ldrh r3, [r7, #6]
  17433. 8006f80: f003 0303 and.w r3, r3, #3
  17434. 8006f84: 83fb strh r3, [r7, #30]
  17435. for (i = 0U; i < count32b; i++)
  17436. 8006f86: 2300 movs r3, #0
  17437. 8006f88: 623b str r3, [r7, #32]
  17438. 8006f8a: e014 b.n 8006fb6 <USB_ReadPacket+0x56>
  17439. {
  17440. __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
  17441. 8006f8c: 69bb ldr r3, [r7, #24]
  17442. 8006f8e: f503 5380 add.w r3, r3, #4096 ; 0x1000
  17443. 8006f92: 681a ldr r2, [r3, #0]
  17444. 8006f94: 6a7b ldr r3, [r7, #36] ; 0x24
  17445. 8006f96: 601a str r2, [r3, #0]
  17446. pDest++;
  17447. 8006f98: 6a7b ldr r3, [r7, #36] ; 0x24
  17448. 8006f9a: 3301 adds r3, #1
  17449. 8006f9c: 627b str r3, [r7, #36] ; 0x24
  17450. pDest++;
  17451. 8006f9e: 6a7b ldr r3, [r7, #36] ; 0x24
  17452. 8006fa0: 3301 adds r3, #1
  17453. 8006fa2: 627b str r3, [r7, #36] ; 0x24
  17454. pDest++;
  17455. 8006fa4: 6a7b ldr r3, [r7, #36] ; 0x24
  17456. 8006fa6: 3301 adds r3, #1
  17457. 8006fa8: 627b str r3, [r7, #36] ; 0x24
  17458. pDest++;
  17459. 8006faa: 6a7b ldr r3, [r7, #36] ; 0x24
  17460. 8006fac: 3301 adds r3, #1
  17461. 8006fae: 627b str r3, [r7, #36] ; 0x24
  17462. for (i = 0U; i < count32b; i++)
  17463. 8006fb0: 6a3b ldr r3, [r7, #32]
  17464. 8006fb2: 3301 adds r3, #1
  17465. 8006fb4: 623b str r3, [r7, #32]
  17466. 8006fb6: 6a3a ldr r2, [r7, #32]
  17467. 8006fb8: 697b ldr r3, [r7, #20]
  17468. 8006fba: 429a cmp r2, r3
  17469. 8006fbc: d3e6 bcc.n 8006f8c <USB_ReadPacket+0x2c>
  17470. }
  17471. /* When Number of data is not word aligned, read the remaining byte */
  17472. if (remaining_bytes != 0U)
  17473. 8006fbe: 8bfb ldrh r3, [r7, #30]
  17474. 8006fc0: 2b00 cmp r3, #0
  17475. 8006fc2: d01e beq.n 8007002 <USB_ReadPacket+0xa2>
  17476. {
  17477. i = 0U;
  17478. 8006fc4: 2300 movs r3, #0
  17479. 8006fc6: 623b str r3, [r7, #32]
  17480. __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
  17481. 8006fc8: 69bb ldr r3, [r7, #24]
  17482. 8006fca: f503 5380 add.w r3, r3, #4096 ; 0x1000
  17483. 8006fce: 461a mov r2, r3
  17484. 8006fd0: f107 0310 add.w r3, r7, #16
  17485. 8006fd4: 6812 ldr r2, [r2, #0]
  17486. 8006fd6: 601a str r2, [r3, #0]
  17487. do
  17488. {
  17489. *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
  17490. 8006fd8: 693a ldr r2, [r7, #16]
  17491. 8006fda: 6a3b ldr r3, [r7, #32]
  17492. 8006fdc: b2db uxtb r3, r3
  17493. 8006fde: 00db lsls r3, r3, #3
  17494. 8006fe0: fa22 f303 lsr.w r3, r2, r3
  17495. 8006fe4: b2da uxtb r2, r3
  17496. 8006fe6: 6a7b ldr r3, [r7, #36] ; 0x24
  17497. 8006fe8: 701a strb r2, [r3, #0]
  17498. i++;
  17499. 8006fea: 6a3b ldr r3, [r7, #32]
  17500. 8006fec: 3301 adds r3, #1
  17501. 8006fee: 623b str r3, [r7, #32]
  17502. pDest++;
  17503. 8006ff0: 6a7b ldr r3, [r7, #36] ; 0x24
  17504. 8006ff2: 3301 adds r3, #1
  17505. 8006ff4: 627b str r3, [r7, #36] ; 0x24
  17506. remaining_bytes--;
  17507. 8006ff6: 8bfb ldrh r3, [r7, #30]
  17508. 8006ff8: 3b01 subs r3, #1
  17509. 8006ffa: 83fb strh r3, [r7, #30]
  17510. } while (remaining_bytes != 0U);
  17511. 8006ffc: 8bfb ldrh r3, [r7, #30]
  17512. 8006ffe: 2b00 cmp r3, #0
  17513. 8007000: d1ea bne.n 8006fd8 <USB_ReadPacket+0x78>
  17514. }
  17515. return ((void *)pDest);
  17516. 8007002: 6a7b ldr r3, [r7, #36] ; 0x24
  17517. }
  17518. 8007004: 4618 mov r0, r3
  17519. 8007006: 372c adds r7, #44 ; 0x2c
  17520. 8007008: 46bd mov sp, r7
  17521. 800700a: f85d 7b04 ldr.w r7, [sp], #4
  17522. 800700e: 4770 bx lr
  17523. 08007010 <USB_EPSetStall>:
  17524. * @param USBx Selected device
  17525. * @param ep pointer to endpoint structure
  17526. * @retval HAL status
  17527. */
  17528. HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
  17529. {
  17530. 8007010: b480 push {r7}
  17531. 8007012: b085 sub sp, #20
  17532. 8007014: af00 add r7, sp, #0
  17533. 8007016: 6078 str r0, [r7, #4]
  17534. 8007018: 6039 str r1, [r7, #0]
  17535. uint32_t USBx_BASE = (uint32_t)USBx;
  17536. 800701a: 687b ldr r3, [r7, #4]
  17537. 800701c: 60fb str r3, [r7, #12]
  17538. uint32_t epnum = (uint32_t)ep->num;
  17539. 800701e: 683b ldr r3, [r7, #0]
  17540. 8007020: 781b ldrb r3, [r3, #0]
  17541. 8007022: 60bb str r3, [r7, #8]
  17542. if (ep->is_in == 1U)
  17543. 8007024: 683b ldr r3, [r7, #0]
  17544. 8007026: 785b ldrb r3, [r3, #1]
  17545. 8007028: 2b01 cmp r3, #1
  17546. 800702a: d12c bne.n 8007086 <USB_EPSetStall+0x76>
  17547. {
  17548. if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
  17549. 800702c: 68bb ldr r3, [r7, #8]
  17550. 800702e: 015a lsls r2, r3, #5
  17551. 8007030: 68fb ldr r3, [r7, #12]
  17552. 8007032: 4413 add r3, r2
  17553. 8007034: f503 6310 add.w r3, r3, #2304 ; 0x900
  17554. 8007038: 681b ldr r3, [r3, #0]
  17555. 800703a: 2b00 cmp r3, #0
  17556. 800703c: db12 blt.n 8007064 <USB_EPSetStall+0x54>
  17557. 800703e: 68bb ldr r3, [r7, #8]
  17558. 8007040: 2b00 cmp r3, #0
  17559. 8007042: d00f beq.n 8007064 <USB_EPSetStall+0x54>
  17560. {
  17561. USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
  17562. 8007044: 68bb ldr r3, [r7, #8]
  17563. 8007046: 015a lsls r2, r3, #5
  17564. 8007048: 68fb ldr r3, [r7, #12]
  17565. 800704a: 4413 add r3, r2
  17566. 800704c: f503 6310 add.w r3, r3, #2304 ; 0x900
  17567. 8007050: 681b ldr r3, [r3, #0]
  17568. 8007052: 68ba ldr r2, [r7, #8]
  17569. 8007054: 0151 lsls r1, r2, #5
  17570. 8007056: 68fa ldr r2, [r7, #12]
  17571. 8007058: 440a add r2, r1
  17572. 800705a: f502 6210 add.w r2, r2, #2304 ; 0x900
  17573. 800705e: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000
  17574. 8007062: 6013 str r3, [r2, #0]
  17575. }
  17576. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
  17577. 8007064: 68bb ldr r3, [r7, #8]
  17578. 8007066: 015a lsls r2, r3, #5
  17579. 8007068: 68fb ldr r3, [r7, #12]
  17580. 800706a: 4413 add r3, r2
  17581. 800706c: f503 6310 add.w r3, r3, #2304 ; 0x900
  17582. 8007070: 681b ldr r3, [r3, #0]
  17583. 8007072: 68ba ldr r2, [r7, #8]
  17584. 8007074: 0151 lsls r1, r2, #5
  17585. 8007076: 68fa ldr r2, [r7, #12]
  17586. 8007078: 440a add r2, r1
  17587. 800707a: f502 6210 add.w r2, r2, #2304 ; 0x900
  17588. 800707e: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
  17589. 8007082: 6013 str r3, [r2, #0]
  17590. 8007084: e02b b.n 80070de <USB_EPSetStall+0xce>
  17591. }
  17592. else
  17593. {
  17594. if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
  17595. 8007086: 68bb ldr r3, [r7, #8]
  17596. 8007088: 015a lsls r2, r3, #5
  17597. 800708a: 68fb ldr r3, [r7, #12]
  17598. 800708c: 4413 add r3, r2
  17599. 800708e: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17600. 8007092: 681b ldr r3, [r3, #0]
  17601. 8007094: 2b00 cmp r3, #0
  17602. 8007096: db12 blt.n 80070be <USB_EPSetStall+0xae>
  17603. 8007098: 68bb ldr r3, [r7, #8]
  17604. 800709a: 2b00 cmp r3, #0
  17605. 800709c: d00f beq.n 80070be <USB_EPSetStall+0xae>
  17606. {
  17607. USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
  17608. 800709e: 68bb ldr r3, [r7, #8]
  17609. 80070a0: 015a lsls r2, r3, #5
  17610. 80070a2: 68fb ldr r3, [r7, #12]
  17611. 80070a4: 4413 add r3, r2
  17612. 80070a6: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17613. 80070aa: 681b ldr r3, [r3, #0]
  17614. 80070ac: 68ba ldr r2, [r7, #8]
  17615. 80070ae: 0151 lsls r1, r2, #5
  17616. 80070b0: 68fa ldr r2, [r7, #12]
  17617. 80070b2: 440a add r2, r1
  17618. 80070b4: f502 6230 add.w r2, r2, #2816 ; 0xb00
  17619. 80070b8: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000
  17620. 80070bc: 6013 str r3, [r2, #0]
  17621. }
  17622. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
  17623. 80070be: 68bb ldr r3, [r7, #8]
  17624. 80070c0: 015a lsls r2, r3, #5
  17625. 80070c2: 68fb ldr r3, [r7, #12]
  17626. 80070c4: 4413 add r3, r2
  17627. 80070c6: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17628. 80070ca: 681b ldr r3, [r3, #0]
  17629. 80070cc: 68ba ldr r2, [r7, #8]
  17630. 80070ce: 0151 lsls r1, r2, #5
  17631. 80070d0: 68fa ldr r2, [r7, #12]
  17632. 80070d2: 440a add r2, r1
  17633. 80070d4: f502 6230 add.w r2, r2, #2816 ; 0xb00
  17634. 80070d8: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
  17635. 80070dc: 6013 str r3, [r2, #0]
  17636. }
  17637. return HAL_OK;
  17638. 80070de: 2300 movs r3, #0
  17639. }
  17640. 80070e0: 4618 mov r0, r3
  17641. 80070e2: 3714 adds r7, #20
  17642. 80070e4: 46bd mov sp, r7
  17643. 80070e6: f85d 7b04 ldr.w r7, [sp], #4
  17644. 80070ea: 4770 bx lr
  17645. 080070ec <USB_EPClearStall>:
  17646. * @param USBx Selected device
  17647. * @param ep pointer to endpoint structure
  17648. * @retval HAL status
  17649. */
  17650. HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
  17651. {
  17652. 80070ec: b480 push {r7}
  17653. 80070ee: b085 sub sp, #20
  17654. 80070f0: af00 add r7, sp, #0
  17655. 80070f2: 6078 str r0, [r7, #4]
  17656. 80070f4: 6039 str r1, [r7, #0]
  17657. uint32_t USBx_BASE = (uint32_t)USBx;
  17658. 80070f6: 687b ldr r3, [r7, #4]
  17659. 80070f8: 60fb str r3, [r7, #12]
  17660. uint32_t epnum = (uint32_t)ep->num;
  17661. 80070fa: 683b ldr r3, [r7, #0]
  17662. 80070fc: 781b ldrb r3, [r3, #0]
  17663. 80070fe: 60bb str r3, [r7, #8]
  17664. if (ep->is_in == 1U)
  17665. 8007100: 683b ldr r3, [r7, #0]
  17666. 8007102: 785b ldrb r3, [r3, #1]
  17667. 8007104: 2b01 cmp r3, #1
  17668. 8007106: d128 bne.n 800715a <USB_EPClearStall+0x6e>
  17669. {
  17670. USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
  17671. 8007108: 68bb ldr r3, [r7, #8]
  17672. 800710a: 015a lsls r2, r3, #5
  17673. 800710c: 68fb ldr r3, [r7, #12]
  17674. 800710e: 4413 add r3, r2
  17675. 8007110: f503 6310 add.w r3, r3, #2304 ; 0x900
  17676. 8007114: 681b ldr r3, [r3, #0]
  17677. 8007116: 68ba ldr r2, [r7, #8]
  17678. 8007118: 0151 lsls r1, r2, #5
  17679. 800711a: 68fa ldr r2, [r7, #12]
  17680. 800711c: 440a add r2, r1
  17681. 800711e: f502 6210 add.w r2, r2, #2304 ; 0x900
  17682. 8007122: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
  17683. 8007126: 6013 str r3, [r2, #0]
  17684. if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
  17685. 8007128: 683b ldr r3, [r7, #0]
  17686. 800712a: 78db ldrb r3, [r3, #3]
  17687. 800712c: 2b03 cmp r3, #3
  17688. 800712e: d003 beq.n 8007138 <USB_EPClearStall+0x4c>
  17689. 8007130: 683b ldr r3, [r7, #0]
  17690. 8007132: 78db ldrb r3, [r3, #3]
  17691. 8007134: 2b02 cmp r3, #2
  17692. 8007136: d138 bne.n 80071aa <USB_EPClearStall+0xbe>
  17693. {
  17694. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
  17695. 8007138: 68bb ldr r3, [r7, #8]
  17696. 800713a: 015a lsls r2, r3, #5
  17697. 800713c: 68fb ldr r3, [r7, #12]
  17698. 800713e: 4413 add r3, r2
  17699. 8007140: f503 6310 add.w r3, r3, #2304 ; 0x900
  17700. 8007144: 681b ldr r3, [r3, #0]
  17701. 8007146: 68ba ldr r2, [r7, #8]
  17702. 8007148: 0151 lsls r1, r2, #5
  17703. 800714a: 68fa ldr r2, [r7, #12]
  17704. 800714c: 440a add r2, r1
  17705. 800714e: f502 6210 add.w r2, r2, #2304 ; 0x900
  17706. 8007152: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
  17707. 8007156: 6013 str r3, [r2, #0]
  17708. 8007158: e027 b.n 80071aa <USB_EPClearStall+0xbe>
  17709. }
  17710. }
  17711. else
  17712. {
  17713. USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
  17714. 800715a: 68bb ldr r3, [r7, #8]
  17715. 800715c: 015a lsls r2, r3, #5
  17716. 800715e: 68fb ldr r3, [r7, #12]
  17717. 8007160: 4413 add r3, r2
  17718. 8007162: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17719. 8007166: 681b ldr r3, [r3, #0]
  17720. 8007168: 68ba ldr r2, [r7, #8]
  17721. 800716a: 0151 lsls r1, r2, #5
  17722. 800716c: 68fa ldr r2, [r7, #12]
  17723. 800716e: 440a add r2, r1
  17724. 8007170: f502 6230 add.w r2, r2, #2816 ; 0xb00
  17725. 8007174: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
  17726. 8007178: 6013 str r3, [r2, #0]
  17727. if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
  17728. 800717a: 683b ldr r3, [r7, #0]
  17729. 800717c: 78db ldrb r3, [r3, #3]
  17730. 800717e: 2b03 cmp r3, #3
  17731. 8007180: d003 beq.n 800718a <USB_EPClearStall+0x9e>
  17732. 8007182: 683b ldr r3, [r7, #0]
  17733. 8007184: 78db ldrb r3, [r3, #3]
  17734. 8007186: 2b02 cmp r3, #2
  17735. 8007188: d10f bne.n 80071aa <USB_EPClearStall+0xbe>
  17736. {
  17737. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
  17738. 800718a: 68bb ldr r3, [r7, #8]
  17739. 800718c: 015a lsls r2, r3, #5
  17740. 800718e: 68fb ldr r3, [r7, #12]
  17741. 8007190: 4413 add r3, r2
  17742. 8007192: f503 6330 add.w r3, r3, #2816 ; 0xb00
  17743. 8007196: 681b ldr r3, [r3, #0]
  17744. 8007198: 68ba ldr r2, [r7, #8]
  17745. 800719a: 0151 lsls r1, r2, #5
  17746. 800719c: 68fa ldr r2, [r7, #12]
  17747. 800719e: 440a add r2, r1
  17748. 80071a0: f502 6230 add.w r2, r2, #2816 ; 0xb00
  17749. 80071a4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
  17750. 80071a8: 6013 str r3, [r2, #0]
  17751. }
  17752. }
  17753. return HAL_OK;
  17754. 80071aa: 2300 movs r3, #0
  17755. }
  17756. 80071ac: 4618 mov r0, r3
  17757. 80071ae: 3714 adds r7, #20
  17758. 80071b0: 46bd mov sp, r7
  17759. 80071b2: f85d 7b04 ldr.w r7, [sp], #4
  17760. 80071b6: 4770 bx lr
  17761. 080071b8 <USB_SetDevAddress>:
  17762. * @param address new device address to be assigned
  17763. * This parameter can be a value from 0 to 255
  17764. * @retval HAL status
  17765. */
  17766. HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
  17767. {
  17768. 80071b8: b480 push {r7}
  17769. 80071ba: b085 sub sp, #20
  17770. 80071bc: af00 add r7, sp, #0
  17771. 80071be: 6078 str r0, [r7, #4]
  17772. 80071c0: 460b mov r3, r1
  17773. 80071c2: 70fb strb r3, [r7, #3]
  17774. uint32_t USBx_BASE = (uint32_t)USBx;
  17775. 80071c4: 687b ldr r3, [r7, #4]
  17776. 80071c6: 60fb str r3, [r7, #12]
  17777. USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
  17778. 80071c8: 68fb ldr r3, [r7, #12]
  17779. 80071ca: f503 6300 add.w r3, r3, #2048 ; 0x800
  17780. 80071ce: 681b ldr r3, [r3, #0]
  17781. 80071d0: 68fa ldr r2, [r7, #12]
  17782. 80071d2: f502 6200 add.w r2, r2, #2048 ; 0x800
  17783. 80071d6: f423 63fe bic.w r3, r3, #2032 ; 0x7f0
  17784. 80071da: 6013 str r3, [r2, #0]
  17785. USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
  17786. 80071dc: 68fb ldr r3, [r7, #12]
  17787. 80071de: f503 6300 add.w r3, r3, #2048 ; 0x800
  17788. 80071e2: 681a ldr r2, [r3, #0]
  17789. 80071e4: 78fb ldrb r3, [r7, #3]
  17790. 80071e6: 011b lsls r3, r3, #4
  17791. 80071e8: f403 63fe and.w r3, r3, #2032 ; 0x7f0
  17792. 80071ec: 68f9 ldr r1, [r7, #12]
  17793. 80071ee: f501 6100 add.w r1, r1, #2048 ; 0x800
  17794. 80071f2: 4313 orrs r3, r2
  17795. 80071f4: 600b str r3, [r1, #0]
  17796. return HAL_OK;
  17797. 80071f6: 2300 movs r3, #0
  17798. }
  17799. 80071f8: 4618 mov r0, r3
  17800. 80071fa: 3714 adds r7, #20
  17801. 80071fc: 46bd mov sp, r7
  17802. 80071fe: f85d 7b04 ldr.w r7, [sp], #4
  17803. 8007202: 4770 bx lr
  17804. 08007204 <USB_DevConnect>:
  17805. * @brief USB_DevConnect : Connect the USB device by enabling Rpu
  17806. * @param USBx Selected device
  17807. * @retval HAL status
  17808. */
  17809. HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
  17810. {
  17811. 8007204: b480 push {r7}
  17812. 8007206: b085 sub sp, #20
  17813. 8007208: af00 add r7, sp, #0
  17814. 800720a: 6078 str r0, [r7, #4]
  17815. uint32_t USBx_BASE = (uint32_t)USBx;
  17816. 800720c: 687b ldr r3, [r7, #4]
  17817. 800720e: 60fb str r3, [r7, #12]
  17818. /* In case phy is stopped, ensure to ungate and restore the phy CLK */
  17819. USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
  17820. 8007210: 68fb ldr r3, [r7, #12]
  17821. 8007212: f503 6360 add.w r3, r3, #3584 ; 0xe00
  17822. 8007216: 681b ldr r3, [r3, #0]
  17823. 8007218: 68fa ldr r2, [r7, #12]
  17824. 800721a: f502 6260 add.w r2, r2, #3584 ; 0xe00
  17825. 800721e: f023 0303 bic.w r3, r3, #3
  17826. 8007222: 6013 str r3, [r2, #0]
  17827. USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
  17828. 8007224: 68fb ldr r3, [r7, #12]
  17829. 8007226: f503 6300 add.w r3, r3, #2048 ; 0x800
  17830. 800722a: 685b ldr r3, [r3, #4]
  17831. 800722c: 68fa ldr r2, [r7, #12]
  17832. 800722e: f502 6200 add.w r2, r2, #2048 ; 0x800
  17833. 8007232: f023 0302 bic.w r3, r3, #2
  17834. 8007236: 6053 str r3, [r2, #4]
  17835. return HAL_OK;
  17836. 8007238: 2300 movs r3, #0
  17837. }
  17838. 800723a: 4618 mov r0, r3
  17839. 800723c: 3714 adds r7, #20
  17840. 800723e: 46bd mov sp, r7
  17841. 8007240: f85d 7b04 ldr.w r7, [sp], #4
  17842. 8007244: 4770 bx lr
  17843. 08007246 <USB_DevDisconnect>:
  17844. * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
  17845. * @param USBx Selected device
  17846. * @retval HAL status
  17847. */
  17848. HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
  17849. {
  17850. 8007246: b480 push {r7}
  17851. 8007248: b085 sub sp, #20
  17852. 800724a: af00 add r7, sp, #0
  17853. 800724c: 6078 str r0, [r7, #4]
  17854. uint32_t USBx_BASE = (uint32_t)USBx;
  17855. 800724e: 687b ldr r3, [r7, #4]
  17856. 8007250: 60fb str r3, [r7, #12]
  17857. /* In case phy is stopped, ensure to ungate and restore the phy CLK */
  17858. USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
  17859. 8007252: 68fb ldr r3, [r7, #12]
  17860. 8007254: f503 6360 add.w r3, r3, #3584 ; 0xe00
  17861. 8007258: 681b ldr r3, [r3, #0]
  17862. 800725a: 68fa ldr r2, [r7, #12]
  17863. 800725c: f502 6260 add.w r2, r2, #3584 ; 0xe00
  17864. 8007260: f023 0303 bic.w r3, r3, #3
  17865. 8007264: 6013 str r3, [r2, #0]
  17866. USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
  17867. 8007266: 68fb ldr r3, [r7, #12]
  17868. 8007268: f503 6300 add.w r3, r3, #2048 ; 0x800
  17869. 800726c: 685b ldr r3, [r3, #4]
  17870. 800726e: 68fa ldr r2, [r7, #12]
  17871. 8007270: f502 6200 add.w r2, r2, #2048 ; 0x800
  17872. 8007274: f043 0302 orr.w r3, r3, #2
  17873. 8007278: 6053 str r3, [r2, #4]
  17874. return HAL_OK;
  17875. 800727a: 2300 movs r3, #0
  17876. }
  17877. 800727c: 4618 mov r0, r3
  17878. 800727e: 3714 adds r7, #20
  17879. 8007280: 46bd mov sp, r7
  17880. 8007282: f85d 7b04 ldr.w r7, [sp], #4
  17881. 8007286: 4770 bx lr
  17882. 08007288 <USB_ReadInterrupts>:
  17883. * @brief USB_ReadInterrupts: return the global USB interrupt status
  17884. * @param USBx Selected device
  17885. * @retval HAL status
  17886. */
  17887. uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
  17888. {
  17889. 8007288: b480 push {r7}
  17890. 800728a: b085 sub sp, #20
  17891. 800728c: af00 add r7, sp, #0
  17892. 800728e: 6078 str r0, [r7, #4]
  17893. uint32_t tmpreg;
  17894. tmpreg = USBx->GINTSTS;
  17895. 8007290: 687b ldr r3, [r7, #4]
  17896. 8007292: 695b ldr r3, [r3, #20]
  17897. 8007294: 60fb str r3, [r7, #12]
  17898. tmpreg &= USBx->GINTMSK;
  17899. 8007296: 687b ldr r3, [r7, #4]
  17900. 8007298: 699b ldr r3, [r3, #24]
  17901. 800729a: 68fa ldr r2, [r7, #12]
  17902. 800729c: 4013 ands r3, r2
  17903. 800729e: 60fb str r3, [r7, #12]
  17904. return tmpreg;
  17905. 80072a0: 68fb ldr r3, [r7, #12]
  17906. }
  17907. 80072a2: 4618 mov r0, r3
  17908. 80072a4: 3714 adds r7, #20
  17909. 80072a6: 46bd mov sp, r7
  17910. 80072a8: f85d 7b04 ldr.w r7, [sp], #4
  17911. 80072ac: 4770 bx lr
  17912. 080072ae <USB_ReadDevAllOutEpInterrupt>:
  17913. * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
  17914. * @param USBx Selected device
  17915. * @retval HAL status
  17916. */
  17917. uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
  17918. {
  17919. 80072ae: b480 push {r7}
  17920. 80072b0: b085 sub sp, #20
  17921. 80072b2: af00 add r7, sp, #0
  17922. 80072b4: 6078 str r0, [r7, #4]
  17923. uint32_t USBx_BASE = (uint32_t)USBx;
  17924. 80072b6: 687b ldr r3, [r7, #4]
  17925. 80072b8: 60fb str r3, [r7, #12]
  17926. uint32_t tmpreg;
  17927. tmpreg = USBx_DEVICE->DAINT;
  17928. 80072ba: 68fb ldr r3, [r7, #12]
  17929. 80072bc: f503 6300 add.w r3, r3, #2048 ; 0x800
  17930. 80072c0: 699b ldr r3, [r3, #24]
  17931. 80072c2: 60bb str r3, [r7, #8]
  17932. tmpreg &= USBx_DEVICE->DAINTMSK;
  17933. 80072c4: 68fb ldr r3, [r7, #12]
  17934. 80072c6: f503 6300 add.w r3, r3, #2048 ; 0x800
  17935. 80072ca: 69db ldr r3, [r3, #28]
  17936. 80072cc: 68ba ldr r2, [r7, #8]
  17937. 80072ce: 4013 ands r3, r2
  17938. 80072d0: 60bb str r3, [r7, #8]
  17939. return ((tmpreg & 0xffff0000U) >> 16);
  17940. 80072d2: 68bb ldr r3, [r7, #8]
  17941. 80072d4: 0c1b lsrs r3, r3, #16
  17942. }
  17943. 80072d6: 4618 mov r0, r3
  17944. 80072d8: 3714 adds r7, #20
  17945. 80072da: 46bd mov sp, r7
  17946. 80072dc: f85d 7b04 ldr.w r7, [sp], #4
  17947. 80072e0: 4770 bx lr
  17948. 080072e2 <USB_ReadDevAllInEpInterrupt>:
  17949. * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
  17950. * @param USBx Selected device
  17951. * @retval HAL status
  17952. */
  17953. uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
  17954. {
  17955. 80072e2: b480 push {r7}
  17956. 80072e4: b085 sub sp, #20
  17957. 80072e6: af00 add r7, sp, #0
  17958. 80072e8: 6078 str r0, [r7, #4]
  17959. uint32_t USBx_BASE = (uint32_t)USBx;
  17960. 80072ea: 687b ldr r3, [r7, #4]
  17961. 80072ec: 60fb str r3, [r7, #12]
  17962. uint32_t tmpreg;
  17963. tmpreg = USBx_DEVICE->DAINT;
  17964. 80072ee: 68fb ldr r3, [r7, #12]
  17965. 80072f0: f503 6300 add.w r3, r3, #2048 ; 0x800
  17966. 80072f4: 699b ldr r3, [r3, #24]
  17967. 80072f6: 60bb str r3, [r7, #8]
  17968. tmpreg &= USBx_DEVICE->DAINTMSK;
  17969. 80072f8: 68fb ldr r3, [r7, #12]
  17970. 80072fa: f503 6300 add.w r3, r3, #2048 ; 0x800
  17971. 80072fe: 69db ldr r3, [r3, #28]
  17972. 8007300: 68ba ldr r2, [r7, #8]
  17973. 8007302: 4013 ands r3, r2
  17974. 8007304: 60bb str r3, [r7, #8]
  17975. return ((tmpreg & 0xFFFFU));
  17976. 8007306: 68bb ldr r3, [r7, #8]
  17977. 8007308: b29b uxth r3, r3
  17978. }
  17979. 800730a: 4618 mov r0, r3
  17980. 800730c: 3714 adds r7, #20
  17981. 800730e: 46bd mov sp, r7
  17982. 8007310: f85d 7b04 ldr.w r7, [sp], #4
  17983. 8007314: 4770 bx lr
  17984. 08007316 <USB_ReadDevOutEPInterrupt>:
  17985. * @param epnum endpoint number
  17986. * This parameter can be a value from 0 to 15
  17987. * @retval Device OUT EP Interrupt register
  17988. */
  17989. uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
  17990. {
  17991. 8007316: b480 push {r7}
  17992. 8007318: b085 sub sp, #20
  17993. 800731a: af00 add r7, sp, #0
  17994. 800731c: 6078 str r0, [r7, #4]
  17995. 800731e: 460b mov r3, r1
  17996. 8007320: 70fb strb r3, [r7, #3]
  17997. uint32_t USBx_BASE = (uint32_t)USBx;
  17998. 8007322: 687b ldr r3, [r7, #4]
  17999. 8007324: 60fb str r3, [r7, #12]
  18000. uint32_t tmpreg;
  18001. tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
  18002. 8007326: 78fb ldrb r3, [r7, #3]
  18003. 8007328: 015a lsls r2, r3, #5
  18004. 800732a: 68fb ldr r3, [r7, #12]
  18005. 800732c: 4413 add r3, r2
  18006. 800732e: f503 6330 add.w r3, r3, #2816 ; 0xb00
  18007. 8007332: 689b ldr r3, [r3, #8]
  18008. 8007334: 60bb str r3, [r7, #8]
  18009. tmpreg &= USBx_DEVICE->DOEPMSK;
  18010. 8007336: 68fb ldr r3, [r7, #12]
  18011. 8007338: f503 6300 add.w r3, r3, #2048 ; 0x800
  18012. 800733c: 695b ldr r3, [r3, #20]
  18013. 800733e: 68ba ldr r2, [r7, #8]
  18014. 8007340: 4013 ands r3, r2
  18015. 8007342: 60bb str r3, [r7, #8]
  18016. return tmpreg;
  18017. 8007344: 68bb ldr r3, [r7, #8]
  18018. }
  18019. 8007346: 4618 mov r0, r3
  18020. 8007348: 3714 adds r7, #20
  18021. 800734a: 46bd mov sp, r7
  18022. 800734c: f85d 7b04 ldr.w r7, [sp], #4
  18023. 8007350: 4770 bx lr
  18024. 08007352 <USB_ReadDevInEPInterrupt>:
  18025. * @param epnum endpoint number
  18026. * This parameter can be a value from 0 to 15
  18027. * @retval Device IN EP Interrupt register
  18028. */
  18029. uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
  18030. {
  18031. 8007352: b480 push {r7}
  18032. 8007354: b087 sub sp, #28
  18033. 8007356: af00 add r7, sp, #0
  18034. 8007358: 6078 str r0, [r7, #4]
  18035. 800735a: 460b mov r3, r1
  18036. 800735c: 70fb strb r3, [r7, #3]
  18037. uint32_t USBx_BASE = (uint32_t)USBx;
  18038. 800735e: 687b ldr r3, [r7, #4]
  18039. 8007360: 617b str r3, [r7, #20]
  18040. uint32_t tmpreg;
  18041. uint32_t msk;
  18042. uint32_t emp;
  18043. msk = USBx_DEVICE->DIEPMSK;
  18044. 8007362: 697b ldr r3, [r7, #20]
  18045. 8007364: f503 6300 add.w r3, r3, #2048 ; 0x800
  18046. 8007368: 691b ldr r3, [r3, #16]
  18047. 800736a: 613b str r3, [r7, #16]
  18048. emp = USBx_DEVICE->DIEPEMPMSK;
  18049. 800736c: 697b ldr r3, [r7, #20]
  18050. 800736e: f503 6300 add.w r3, r3, #2048 ; 0x800
  18051. 8007372: 6b5b ldr r3, [r3, #52] ; 0x34
  18052. 8007374: 60fb str r3, [r7, #12]
  18053. msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
  18054. 8007376: 78fb ldrb r3, [r7, #3]
  18055. 8007378: f003 030f and.w r3, r3, #15
  18056. 800737c: 68fa ldr r2, [r7, #12]
  18057. 800737e: fa22 f303 lsr.w r3, r2, r3
  18058. 8007382: 01db lsls r3, r3, #7
  18059. 8007384: b2db uxtb r3, r3
  18060. 8007386: 693a ldr r2, [r7, #16]
  18061. 8007388: 4313 orrs r3, r2
  18062. 800738a: 613b str r3, [r7, #16]
  18063. tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
  18064. 800738c: 78fb ldrb r3, [r7, #3]
  18065. 800738e: 015a lsls r2, r3, #5
  18066. 8007390: 697b ldr r3, [r7, #20]
  18067. 8007392: 4413 add r3, r2
  18068. 8007394: f503 6310 add.w r3, r3, #2304 ; 0x900
  18069. 8007398: 689b ldr r3, [r3, #8]
  18070. 800739a: 693a ldr r2, [r7, #16]
  18071. 800739c: 4013 ands r3, r2
  18072. 800739e: 60bb str r3, [r7, #8]
  18073. return tmpreg;
  18074. 80073a0: 68bb ldr r3, [r7, #8]
  18075. }
  18076. 80073a2: 4618 mov r0, r3
  18077. 80073a4: 371c adds r7, #28
  18078. 80073a6: 46bd mov sp, r7
  18079. 80073a8: f85d 7b04 ldr.w r7, [sp], #4
  18080. 80073ac: 4770 bx lr
  18081. 080073ae <USB_GetMode>:
  18082. * This parameter can be one of these values:
  18083. * 0 : Host
  18084. * 1 : Device
  18085. */
  18086. uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
  18087. {
  18088. 80073ae: b480 push {r7}
  18089. 80073b0: b083 sub sp, #12
  18090. 80073b2: af00 add r7, sp, #0
  18091. 80073b4: 6078 str r0, [r7, #4]
  18092. return ((USBx->GINTSTS) & 0x1U);
  18093. 80073b6: 687b ldr r3, [r7, #4]
  18094. 80073b8: 695b ldr r3, [r3, #20]
  18095. 80073ba: f003 0301 and.w r3, r3, #1
  18096. }
  18097. 80073be: 4618 mov r0, r3
  18098. 80073c0: 370c adds r7, #12
  18099. 80073c2: 46bd mov sp, r7
  18100. 80073c4: f85d 7b04 ldr.w r7, [sp], #4
  18101. 80073c8: 4770 bx lr
  18102. ...
  18103. 080073cc <USB_ActivateSetup>:
  18104. * @brief Activate EP0 for Setup transactions
  18105. * @param USBx Selected device
  18106. * @retval HAL status
  18107. */
  18108. HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
  18109. {
  18110. 80073cc: b480 push {r7}
  18111. 80073ce: b085 sub sp, #20
  18112. 80073d0: af00 add r7, sp, #0
  18113. 80073d2: 6078 str r0, [r7, #4]
  18114. uint32_t USBx_BASE = (uint32_t)USBx;
  18115. 80073d4: 687b ldr r3, [r7, #4]
  18116. 80073d6: 60fb str r3, [r7, #12]
  18117. /* Set the MPS of the IN EP0 to 64 bytes */
  18118. USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
  18119. 80073d8: 68fb ldr r3, [r7, #12]
  18120. 80073da: f503 6310 add.w r3, r3, #2304 ; 0x900
  18121. 80073de: 681a ldr r2, [r3, #0]
  18122. 80073e0: 68fb ldr r3, [r7, #12]
  18123. 80073e2: f503 6310 add.w r3, r3, #2304 ; 0x900
  18124. 80073e6: 4619 mov r1, r3
  18125. 80073e8: 4b09 ldr r3, [pc, #36] ; (8007410 <USB_ActivateSetup+0x44>)
  18126. 80073ea: 4013 ands r3, r2
  18127. 80073ec: 600b str r3, [r1, #0]
  18128. USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
  18129. 80073ee: 68fb ldr r3, [r7, #12]
  18130. 80073f0: f503 6300 add.w r3, r3, #2048 ; 0x800
  18131. 80073f4: 685b ldr r3, [r3, #4]
  18132. 80073f6: 68fa ldr r2, [r7, #12]
  18133. 80073f8: f502 6200 add.w r2, r2, #2048 ; 0x800
  18134. 80073fc: f443 7380 orr.w r3, r3, #256 ; 0x100
  18135. 8007400: 6053 str r3, [r2, #4]
  18136. return HAL_OK;
  18137. 8007402: 2300 movs r3, #0
  18138. }
  18139. 8007404: 4618 mov r0, r3
  18140. 8007406: 3714 adds r7, #20
  18141. 8007408: 46bd mov sp, r7
  18142. 800740a: f85d 7b04 ldr.w r7, [sp], #4
  18143. 800740e: 4770 bx lr
  18144. 8007410: fffff800 .word 0xfffff800
  18145. 08007414 <USB_EP0_OutStart>:
  18146. * 1 : DMA feature used
  18147. * @param psetup pointer to setup packet
  18148. * @retval HAL status
  18149. */
  18150. HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
  18151. {
  18152. 8007414: b480 push {r7}
  18153. 8007416: b087 sub sp, #28
  18154. 8007418: af00 add r7, sp, #0
  18155. 800741a: 60f8 str r0, [r7, #12]
  18156. 800741c: 460b mov r3, r1
  18157. 800741e: 607a str r2, [r7, #4]
  18158. 8007420: 72fb strb r3, [r7, #11]
  18159. uint32_t USBx_BASE = (uint32_t)USBx;
  18160. 8007422: 68fb ldr r3, [r7, #12]
  18161. 8007424: 617b str r3, [r7, #20]
  18162. uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
  18163. 8007426: 68fb ldr r3, [r7, #12]
  18164. 8007428: 333c adds r3, #60 ; 0x3c
  18165. 800742a: 3304 adds r3, #4
  18166. 800742c: 681b ldr r3, [r3, #0]
  18167. 800742e: 613b str r3, [r7, #16]
  18168. if (gSNPSiD > USB_OTG_CORE_ID_300A)
  18169. 8007430: 693b ldr r3, [r7, #16]
  18170. 8007432: 4a26 ldr r2, [pc, #152] ; (80074cc <USB_EP0_OutStart+0xb8>)
  18171. 8007434: 4293 cmp r3, r2
  18172. 8007436: d90a bls.n 800744e <USB_EP0_OutStart+0x3a>
  18173. {
  18174. if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
  18175. 8007438: 697b ldr r3, [r7, #20]
  18176. 800743a: f503 6330 add.w r3, r3, #2816 ; 0xb00
  18177. 800743e: 681b ldr r3, [r3, #0]
  18178. 8007440: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000
  18179. 8007444: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
  18180. 8007448: d101 bne.n 800744e <USB_EP0_OutStart+0x3a>
  18181. {
  18182. return HAL_OK;
  18183. 800744a: 2300 movs r3, #0
  18184. 800744c: e037 b.n 80074be <USB_EP0_OutStart+0xaa>
  18185. }
  18186. }
  18187. USBx_OUTEP(0U)->DOEPTSIZ = 0U;
  18188. 800744e: 697b ldr r3, [r7, #20]
  18189. 8007450: f503 6330 add.w r3, r3, #2816 ; 0xb00
  18190. 8007454: 461a mov r2, r3
  18191. 8007456: 2300 movs r3, #0
  18192. 8007458: 6113 str r3, [r2, #16]
  18193. USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
  18194. 800745a: 697b ldr r3, [r7, #20]
  18195. 800745c: f503 6330 add.w r3, r3, #2816 ; 0xb00
  18196. 8007460: 691b ldr r3, [r3, #16]
  18197. 8007462: 697a ldr r2, [r7, #20]
  18198. 8007464: f502 6230 add.w r2, r2, #2816 ; 0xb00
  18199. 8007468: f443 2300 orr.w r3, r3, #524288 ; 0x80000
  18200. 800746c: 6113 str r3, [r2, #16]
  18201. USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
  18202. 800746e: 697b ldr r3, [r7, #20]
  18203. 8007470: f503 6330 add.w r3, r3, #2816 ; 0xb00
  18204. 8007474: 691b ldr r3, [r3, #16]
  18205. 8007476: 697a ldr r2, [r7, #20]
  18206. 8007478: f502 6230 add.w r2, r2, #2816 ; 0xb00
  18207. 800747c: f043 0318 orr.w r3, r3, #24
  18208. 8007480: 6113 str r3, [r2, #16]
  18209. USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
  18210. 8007482: 697b ldr r3, [r7, #20]
  18211. 8007484: f503 6330 add.w r3, r3, #2816 ; 0xb00
  18212. 8007488: 691b ldr r3, [r3, #16]
  18213. 800748a: 697a ldr r2, [r7, #20]
  18214. 800748c: f502 6230 add.w r2, r2, #2816 ; 0xb00
  18215. 8007490: f043 43c0 orr.w r3, r3, #1610612736 ; 0x60000000
  18216. 8007494: 6113 str r3, [r2, #16]
  18217. if (dma == 1U)
  18218. 8007496: 7afb ldrb r3, [r7, #11]
  18219. 8007498: 2b01 cmp r3, #1
  18220. 800749a: d10f bne.n 80074bc <USB_EP0_OutStart+0xa8>
  18221. {
  18222. USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
  18223. 800749c: 697b ldr r3, [r7, #20]
  18224. 800749e: f503 6330 add.w r3, r3, #2816 ; 0xb00
  18225. 80074a2: 461a mov r2, r3
  18226. 80074a4: 687b ldr r3, [r7, #4]
  18227. 80074a6: 6153 str r3, [r2, #20]
  18228. /* EP enable */
  18229. USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
  18230. 80074a8: 697b ldr r3, [r7, #20]
  18231. 80074aa: f503 6330 add.w r3, r3, #2816 ; 0xb00
  18232. 80074ae: 681b ldr r3, [r3, #0]
  18233. 80074b0: 697a ldr r2, [r7, #20]
  18234. 80074b2: f502 6230 add.w r2, r2, #2816 ; 0xb00
  18235. 80074b6: f043 2380 orr.w r3, r3, #2147516416 ; 0x80008000
  18236. 80074ba: 6013 str r3, [r2, #0]
  18237. }
  18238. return HAL_OK;
  18239. 80074bc: 2300 movs r3, #0
  18240. }
  18241. 80074be: 4618 mov r0, r3
  18242. 80074c0: 371c adds r7, #28
  18243. 80074c2: 46bd mov sp, r7
  18244. 80074c4: f85d 7b04 ldr.w r7, [sp], #4
  18245. 80074c8: 4770 bx lr
  18246. 80074ca: bf00 nop
  18247. 80074cc: 4f54300a .word 0x4f54300a
  18248. 080074d0 <USB_CoreReset>:
  18249. * @brief Reset the USB Core (needed after USB clock settings change)
  18250. * @param USBx Selected device
  18251. * @retval HAL status
  18252. */
  18253. static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
  18254. {
  18255. 80074d0: b480 push {r7}
  18256. 80074d2: b085 sub sp, #20
  18257. 80074d4: af00 add r7, sp, #0
  18258. 80074d6: 6078 str r0, [r7, #4]
  18259. __IO uint32_t count = 0U;
  18260. 80074d8: 2300 movs r3, #0
  18261. 80074da: 60fb str r3, [r7, #12]
  18262. /* Wait for AHB master IDLE state. */
  18263. do
  18264. {
  18265. if (++count > 200000U)
  18266. 80074dc: 68fb ldr r3, [r7, #12]
  18267. 80074de: 3301 adds r3, #1
  18268. 80074e0: 60fb str r3, [r7, #12]
  18269. 80074e2: 4a13 ldr r2, [pc, #76] ; (8007530 <USB_CoreReset+0x60>)
  18270. 80074e4: 4293 cmp r3, r2
  18271. 80074e6: d901 bls.n 80074ec <USB_CoreReset+0x1c>
  18272. {
  18273. return HAL_TIMEOUT;
  18274. 80074e8: 2303 movs r3, #3
  18275. 80074ea: e01a b.n 8007522 <USB_CoreReset+0x52>
  18276. }
  18277. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
  18278. 80074ec: 687b ldr r3, [r7, #4]
  18279. 80074ee: 691b ldr r3, [r3, #16]
  18280. 80074f0: 2b00 cmp r3, #0
  18281. 80074f2: daf3 bge.n 80074dc <USB_CoreReset+0xc>
  18282. /* Core Soft Reset */
  18283. count = 0U;
  18284. 80074f4: 2300 movs r3, #0
  18285. 80074f6: 60fb str r3, [r7, #12]
  18286. USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
  18287. 80074f8: 687b ldr r3, [r7, #4]
  18288. 80074fa: 691b ldr r3, [r3, #16]
  18289. 80074fc: f043 0201 orr.w r2, r3, #1
  18290. 8007500: 687b ldr r3, [r7, #4]
  18291. 8007502: 611a str r2, [r3, #16]
  18292. do
  18293. {
  18294. if (++count > 200000U)
  18295. 8007504: 68fb ldr r3, [r7, #12]
  18296. 8007506: 3301 adds r3, #1
  18297. 8007508: 60fb str r3, [r7, #12]
  18298. 800750a: 4a09 ldr r2, [pc, #36] ; (8007530 <USB_CoreReset+0x60>)
  18299. 800750c: 4293 cmp r3, r2
  18300. 800750e: d901 bls.n 8007514 <USB_CoreReset+0x44>
  18301. {
  18302. return HAL_TIMEOUT;
  18303. 8007510: 2303 movs r3, #3
  18304. 8007512: e006 b.n 8007522 <USB_CoreReset+0x52>
  18305. }
  18306. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
  18307. 8007514: 687b ldr r3, [r7, #4]
  18308. 8007516: 691b ldr r3, [r3, #16]
  18309. 8007518: f003 0301 and.w r3, r3, #1
  18310. 800751c: 2b01 cmp r3, #1
  18311. 800751e: d0f1 beq.n 8007504 <USB_CoreReset+0x34>
  18312. return HAL_OK;
  18313. 8007520: 2300 movs r3, #0
  18314. }
  18315. 8007522: 4618 mov r0, r3
  18316. 8007524: 3714 adds r7, #20
  18317. 8007526: 46bd mov sp, r7
  18318. 8007528: f85d 7b04 ldr.w r7, [sp], #4
  18319. 800752c: 4770 bx lr
  18320. 800752e: bf00 nop
  18321. 8007530: 00030d40 .word 0x00030d40
  18322. 08007534 <USBD_CDC_Init>:
  18323. * @param pdev: device instance
  18324. * @param cfgidx: Configuration index
  18325. * @retval status
  18326. */
  18327. static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
  18328. {
  18329. 8007534: b580 push {r7, lr}
  18330. 8007536: b084 sub sp, #16
  18331. 8007538: af00 add r7, sp, #0
  18332. 800753a: 6078 str r0, [r7, #4]
  18333. 800753c: 460b mov r3, r1
  18334. 800753e: 70fb strb r3, [r7, #3]
  18335. UNUSED(cfgidx);
  18336. USBD_CDC_HandleTypeDef *hcdc;
  18337. hcdc = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef));
  18338. 8007540: f44f 7007 mov.w r0, #540 ; 0x21c
  18339. 8007544: f002 f986 bl 8009854 <USBD_static_malloc>
  18340. 8007548: 60f8 str r0, [r7, #12]
  18341. if (hcdc == NULL)
  18342. 800754a: 68fb ldr r3, [r7, #12]
  18343. 800754c: 2b00 cmp r3, #0
  18344. 800754e: d105 bne.n 800755c <USBD_CDC_Init+0x28>
  18345. {
  18346. pdev->pClassData = NULL;
  18347. 8007550: 687b ldr r3, [r7, #4]
  18348. 8007552: 2200 movs r2, #0
  18349. 8007554: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc
  18350. return (uint8_t)USBD_EMEM;
  18351. 8007558: 2302 movs r3, #2
  18352. 800755a: e066 b.n 800762a <USBD_CDC_Init+0xf6>
  18353. }
  18354. pdev->pClassData = (void *)hcdc;
  18355. 800755c: 687b ldr r3, [r7, #4]
  18356. 800755e: 68fa ldr r2, [r7, #12]
  18357. 8007560: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc
  18358. if (pdev->dev_speed == USBD_SPEED_HIGH)
  18359. 8007564: 687b ldr r3, [r7, #4]
  18360. 8007566: 7c1b ldrb r3, [r3, #16]
  18361. 8007568: 2b00 cmp r3, #0
  18362. 800756a: d119 bne.n 80075a0 <USBD_CDC_Init+0x6c>
  18363. {
  18364. /* Open EP IN */
  18365. (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
  18366. 800756c: f44f 7300 mov.w r3, #512 ; 0x200
  18367. 8007570: 2202 movs r2, #2
  18368. 8007572: 2181 movs r1, #129 ; 0x81
  18369. 8007574: 6878 ldr r0, [r7, #4]
  18370. 8007576: f002 f84a bl 800960e <USBD_LL_OpenEP>
  18371. CDC_DATA_HS_IN_PACKET_SIZE);
  18372. pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
  18373. 800757a: 687b ldr r3, [r7, #4]
  18374. 800757c: 2201 movs r2, #1
  18375. 800757e: 871a strh r2, [r3, #56] ; 0x38
  18376. /* Open EP OUT */
  18377. (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
  18378. 8007580: f44f 7300 mov.w r3, #512 ; 0x200
  18379. 8007584: 2202 movs r2, #2
  18380. 8007586: 2101 movs r1, #1
  18381. 8007588: 6878 ldr r0, [r7, #4]
  18382. 800758a: f002 f840 bl 800960e <USBD_LL_OpenEP>
  18383. CDC_DATA_HS_OUT_PACKET_SIZE);
  18384. pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
  18385. 800758e: 687b ldr r3, [r7, #4]
  18386. 8007590: 2201 movs r2, #1
  18387. 8007592: f8a3 2178 strh.w r2, [r3, #376] ; 0x178
  18388. /* Set bInterval for CDC CMD Endpoint */
  18389. pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_HS_BINTERVAL;
  18390. 8007596: 687b ldr r3, [r7, #4]
  18391. 8007598: 2210 movs r2, #16
  18392. 800759a: f8a3 204e strh.w r2, [r3, #78] ; 0x4e
  18393. 800759e: e016 b.n 80075ce <USBD_CDC_Init+0x9a>
  18394. }
  18395. else
  18396. {
  18397. /* Open EP IN */
  18398. (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
  18399. 80075a0: 2340 movs r3, #64 ; 0x40
  18400. 80075a2: 2202 movs r2, #2
  18401. 80075a4: 2181 movs r1, #129 ; 0x81
  18402. 80075a6: 6878 ldr r0, [r7, #4]
  18403. 80075a8: f002 f831 bl 800960e <USBD_LL_OpenEP>
  18404. CDC_DATA_FS_IN_PACKET_SIZE);
  18405. pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
  18406. 80075ac: 687b ldr r3, [r7, #4]
  18407. 80075ae: 2201 movs r2, #1
  18408. 80075b0: 871a strh r2, [r3, #56] ; 0x38
  18409. /* Open EP OUT */
  18410. (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
  18411. 80075b2: 2340 movs r3, #64 ; 0x40
  18412. 80075b4: 2202 movs r2, #2
  18413. 80075b6: 2101 movs r1, #1
  18414. 80075b8: 6878 ldr r0, [r7, #4]
  18415. 80075ba: f002 f828 bl 800960e <USBD_LL_OpenEP>
  18416. CDC_DATA_FS_OUT_PACKET_SIZE);
  18417. pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
  18418. 80075be: 687b ldr r3, [r7, #4]
  18419. 80075c0: 2201 movs r2, #1
  18420. 80075c2: f8a3 2178 strh.w r2, [r3, #376] ; 0x178
  18421. /* Set bInterval for CMD Endpoint */
  18422. pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_FS_BINTERVAL;
  18423. 80075c6: 687b ldr r3, [r7, #4]
  18424. 80075c8: 2210 movs r2, #16
  18425. 80075ca: f8a3 204e strh.w r2, [r3, #78] ; 0x4e
  18426. }
  18427. /* Open Command IN EP */
  18428. (void)USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE);
  18429. 80075ce: 2308 movs r3, #8
  18430. 80075d0: 2203 movs r2, #3
  18431. 80075d2: 2182 movs r1, #130 ; 0x82
  18432. 80075d4: 6878 ldr r0, [r7, #4]
  18433. 80075d6: f002 f81a bl 800960e <USBD_LL_OpenEP>
  18434. pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U;
  18435. 80075da: 687b ldr r3, [r7, #4]
  18436. 80075dc: 2201 movs r2, #1
  18437. 80075de: f8a3 204c strh.w r2, [r3, #76] ; 0x4c
  18438. /* Init physical Interface components */
  18439. ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();
  18440. 80075e2: 687b ldr r3, [r7, #4]
  18441. 80075e4: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
  18442. 80075e8: 681b ldr r3, [r3, #0]
  18443. 80075ea: 4798 blx r3
  18444. /* Init Xfer states */
  18445. hcdc->TxState = 0U;
  18446. 80075ec: 68fb ldr r3, [r7, #12]
  18447. 80075ee: 2200 movs r2, #0
  18448. 80075f0: f8c3 2214 str.w r2, [r3, #532] ; 0x214
  18449. hcdc->RxState = 0U;
  18450. 80075f4: 68fb ldr r3, [r7, #12]
  18451. 80075f6: 2200 movs r2, #0
  18452. 80075f8: f8c3 2218 str.w r2, [r3, #536] ; 0x218
  18453. if (pdev->dev_speed == USBD_SPEED_HIGH)
  18454. 80075fc: 687b ldr r3, [r7, #4]
  18455. 80075fe: 7c1b ldrb r3, [r3, #16]
  18456. 8007600: 2b00 cmp r3, #0
  18457. 8007602: d109 bne.n 8007618 <USBD_CDC_Init+0xe4>
  18458. {
  18459. /* Prepare Out endpoint to receive next packet */
  18460. (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
  18461. 8007604: 68fb ldr r3, [r7, #12]
  18462. 8007606: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
  18463. 800760a: f44f 7300 mov.w r3, #512 ; 0x200
  18464. 800760e: 2101 movs r1, #1
  18465. 8007610: 6878 ldr r0, [r7, #4]
  18466. 8007612: f002 f8eb bl 80097ec <USBD_LL_PrepareReceive>
  18467. 8007616: e007 b.n 8007628 <USBD_CDC_Init+0xf4>
  18468. CDC_DATA_HS_OUT_PACKET_SIZE);
  18469. }
  18470. else
  18471. {
  18472. /* Prepare Out endpoint to receive next packet */
  18473. (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
  18474. 8007618: 68fb ldr r3, [r7, #12]
  18475. 800761a: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
  18476. 800761e: 2340 movs r3, #64 ; 0x40
  18477. 8007620: 2101 movs r1, #1
  18478. 8007622: 6878 ldr r0, [r7, #4]
  18479. 8007624: f002 f8e2 bl 80097ec <USBD_LL_PrepareReceive>
  18480. CDC_DATA_FS_OUT_PACKET_SIZE);
  18481. }
  18482. return (uint8_t)USBD_OK;
  18483. 8007628: 2300 movs r3, #0
  18484. }
  18485. 800762a: 4618 mov r0, r3
  18486. 800762c: 3710 adds r7, #16
  18487. 800762e: 46bd mov sp, r7
  18488. 8007630: bd80 pop {r7, pc}
  18489. 08007632 <USBD_CDC_DeInit>:
  18490. * @param pdev: device instance
  18491. * @param cfgidx: Configuration index
  18492. * @retval status
  18493. */
  18494. static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
  18495. {
  18496. 8007632: b580 push {r7, lr}
  18497. 8007634: b082 sub sp, #8
  18498. 8007636: af00 add r7, sp, #0
  18499. 8007638: 6078 str r0, [r7, #4]
  18500. 800763a: 460b mov r3, r1
  18501. 800763c: 70fb strb r3, [r7, #3]
  18502. UNUSED(cfgidx);
  18503. /* Close EP IN */
  18504. (void)USBD_LL_CloseEP(pdev, CDC_IN_EP);
  18505. 800763e: 2181 movs r1, #129 ; 0x81
  18506. 8007640: 6878 ldr r0, [r7, #4]
  18507. 8007642: f002 f80a bl 800965a <USBD_LL_CloseEP>
  18508. pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U;
  18509. 8007646: 687b ldr r3, [r7, #4]
  18510. 8007648: 2200 movs r2, #0
  18511. 800764a: 871a strh r2, [r3, #56] ; 0x38
  18512. /* Close EP OUT */
  18513. (void)USBD_LL_CloseEP(pdev, CDC_OUT_EP);
  18514. 800764c: 2101 movs r1, #1
  18515. 800764e: 6878 ldr r0, [r7, #4]
  18516. 8007650: f002 f803 bl 800965a <USBD_LL_CloseEP>
  18517. pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U;
  18518. 8007654: 687b ldr r3, [r7, #4]
  18519. 8007656: 2200 movs r2, #0
  18520. 8007658: f8a3 2178 strh.w r2, [r3, #376] ; 0x178
  18521. /* Close Command IN EP */
  18522. (void)USBD_LL_CloseEP(pdev, CDC_CMD_EP);
  18523. 800765c: 2182 movs r1, #130 ; 0x82
  18524. 800765e: 6878 ldr r0, [r7, #4]
  18525. 8007660: f001 fffb bl 800965a <USBD_LL_CloseEP>
  18526. pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U;
  18527. 8007664: 687b ldr r3, [r7, #4]
  18528. 8007666: 2200 movs r2, #0
  18529. 8007668: f8a3 204c strh.w r2, [r3, #76] ; 0x4c
  18530. pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = 0U;
  18531. 800766c: 687b ldr r3, [r7, #4]
  18532. 800766e: 2200 movs r2, #0
  18533. 8007670: f8a3 204e strh.w r2, [r3, #78] ; 0x4e
  18534. /* DeInit physical Interface components */
  18535. if (pdev->pClassData != NULL)
  18536. 8007674: 687b ldr r3, [r7, #4]
  18537. 8007676: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  18538. 800767a: 2b00 cmp r3, #0
  18539. 800767c: d00e beq.n 800769c <USBD_CDC_DeInit+0x6a>
  18540. {
  18541. ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();
  18542. 800767e: 687b ldr r3, [r7, #4]
  18543. 8007680: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
  18544. 8007684: 685b ldr r3, [r3, #4]
  18545. 8007686: 4798 blx r3
  18546. (void)USBD_free(pdev->pClassData);
  18547. 8007688: 687b ldr r3, [r7, #4]
  18548. 800768a: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  18549. 800768e: 4618 mov r0, r3
  18550. 8007690: f002 f8ee bl 8009870 <USBD_static_free>
  18551. pdev->pClassData = NULL;
  18552. 8007694: 687b ldr r3, [r7, #4]
  18553. 8007696: 2200 movs r2, #0
  18554. 8007698: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc
  18555. }
  18556. return (uint8_t)USBD_OK;
  18557. 800769c: 2300 movs r3, #0
  18558. }
  18559. 800769e: 4618 mov r0, r3
  18560. 80076a0: 3708 adds r7, #8
  18561. 80076a2: 46bd mov sp, r7
  18562. 80076a4: bd80 pop {r7, pc}
  18563. ...
  18564. 080076a8 <USBD_CDC_Setup>:
  18565. * @param req: usb requests
  18566. * @retval status
  18567. */
  18568. static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev,
  18569. USBD_SetupReqTypedef *req)
  18570. {
  18571. 80076a8: b580 push {r7, lr}
  18572. 80076aa: b086 sub sp, #24
  18573. 80076ac: af00 add r7, sp, #0
  18574. 80076ae: 6078 str r0, [r7, #4]
  18575. 80076b0: 6039 str r1, [r7, #0]
  18576. USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
  18577. 80076b2: 687b ldr r3, [r7, #4]
  18578. 80076b4: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  18579. 80076b8: 613b str r3, [r7, #16]
  18580. uint16_t len;
  18581. uint8_t ifalt = 0U;
  18582. 80076ba: 2300 movs r3, #0
  18583. 80076bc: 737b strb r3, [r7, #13]
  18584. uint16_t status_info = 0U;
  18585. 80076be: 2300 movs r3, #0
  18586. 80076c0: 817b strh r3, [r7, #10]
  18587. USBD_StatusTypeDef ret = USBD_OK;
  18588. 80076c2: 2300 movs r3, #0
  18589. 80076c4: 75fb strb r3, [r7, #23]
  18590. if (hcdc == NULL)
  18591. 80076c6: 693b ldr r3, [r7, #16]
  18592. 80076c8: 2b00 cmp r3, #0
  18593. 80076ca: d101 bne.n 80076d0 <USBD_CDC_Setup+0x28>
  18594. {
  18595. return (uint8_t)USBD_FAIL;
  18596. 80076cc: 2303 movs r3, #3
  18597. 80076ce: e0af b.n 8007830 <USBD_CDC_Setup+0x188>
  18598. }
  18599. switch (req->bmRequest & USB_REQ_TYPE_MASK)
  18600. 80076d0: 683b ldr r3, [r7, #0]
  18601. 80076d2: 781b ldrb r3, [r3, #0]
  18602. 80076d4: f003 0360 and.w r3, r3, #96 ; 0x60
  18603. 80076d8: 2b00 cmp r3, #0
  18604. 80076da: d03f beq.n 800775c <USBD_CDC_Setup+0xb4>
  18605. 80076dc: 2b20 cmp r3, #32
  18606. 80076de: f040 809f bne.w 8007820 <USBD_CDC_Setup+0x178>
  18607. {
  18608. case USB_REQ_TYPE_CLASS:
  18609. if (req->wLength != 0U)
  18610. 80076e2: 683b ldr r3, [r7, #0]
  18611. 80076e4: 88db ldrh r3, [r3, #6]
  18612. 80076e6: 2b00 cmp r3, #0
  18613. 80076e8: d02e beq.n 8007748 <USBD_CDC_Setup+0xa0>
  18614. {
  18615. if ((req->bmRequest & 0x80U) != 0U)
  18616. 80076ea: 683b ldr r3, [r7, #0]
  18617. 80076ec: 781b ldrb r3, [r3, #0]
  18618. 80076ee: b25b sxtb r3, r3
  18619. 80076f0: 2b00 cmp r3, #0
  18620. 80076f2: da16 bge.n 8007722 <USBD_CDC_Setup+0x7a>
  18621. {
  18622. ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
  18623. 80076f4: 687b ldr r3, [r7, #4]
  18624. 80076f6: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
  18625. 80076fa: 689b ldr r3, [r3, #8]
  18626. 80076fc: 683a ldr r2, [r7, #0]
  18627. 80076fe: 7850 ldrb r0, [r2, #1]
  18628. (uint8_t *)hcdc->data,
  18629. 8007700: 6939 ldr r1, [r7, #16]
  18630. ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
  18631. 8007702: 683a ldr r2, [r7, #0]
  18632. 8007704: 88d2 ldrh r2, [r2, #6]
  18633. 8007706: 4798 blx r3
  18634. req->wLength);
  18635. len = MIN(CDC_REQ_MAX_DATA_SIZE, req->wLength);
  18636. 8007708: 683b ldr r3, [r7, #0]
  18637. 800770a: 88db ldrh r3, [r3, #6]
  18638. 800770c: 2b07 cmp r3, #7
  18639. 800770e: bf28 it cs
  18640. 8007710: 2307 movcs r3, #7
  18641. 8007712: 81fb strh r3, [r7, #14]
  18642. (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, len);
  18643. 8007714: 693b ldr r3, [r7, #16]
  18644. 8007716: 89fa ldrh r2, [r7, #14]
  18645. 8007718: 4619 mov r1, r3
  18646. 800771a: 6878 ldr r0, [r7, #4]
  18647. 800771c: f001 fb19 bl 8008d52 <USBD_CtlSendData>
  18648. else
  18649. {
  18650. ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
  18651. (uint8_t *)req, 0U);
  18652. }
  18653. break;
  18654. 8007720: e085 b.n 800782e <USBD_CDC_Setup+0x186>
  18655. hcdc->CmdOpCode = req->bRequest;
  18656. 8007722: 683b ldr r3, [r7, #0]
  18657. 8007724: 785a ldrb r2, [r3, #1]
  18658. 8007726: 693b ldr r3, [r7, #16]
  18659. 8007728: f883 2200 strb.w r2, [r3, #512] ; 0x200
  18660. hcdc->CmdLength = (uint8_t)req->wLength;
  18661. 800772c: 683b ldr r3, [r7, #0]
  18662. 800772e: 88db ldrh r3, [r3, #6]
  18663. 8007730: b2da uxtb r2, r3
  18664. 8007732: 693b ldr r3, [r7, #16]
  18665. 8007734: f883 2201 strb.w r2, [r3, #513] ; 0x201
  18666. (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, req->wLength);
  18667. 8007738: 6939 ldr r1, [r7, #16]
  18668. 800773a: 683b ldr r3, [r7, #0]
  18669. 800773c: 88db ldrh r3, [r3, #6]
  18670. 800773e: 461a mov r2, r3
  18671. 8007740: 6878 ldr r0, [r7, #4]
  18672. 8007742: f001 fb32 bl 8008daa <USBD_CtlPrepareRx>
  18673. break;
  18674. 8007746: e072 b.n 800782e <USBD_CDC_Setup+0x186>
  18675. ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
  18676. 8007748: 687b ldr r3, [r7, #4]
  18677. 800774a: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
  18678. 800774e: 689b ldr r3, [r3, #8]
  18679. 8007750: 683a ldr r2, [r7, #0]
  18680. 8007752: 7850 ldrb r0, [r2, #1]
  18681. 8007754: 2200 movs r2, #0
  18682. 8007756: 6839 ldr r1, [r7, #0]
  18683. 8007758: 4798 blx r3
  18684. break;
  18685. 800775a: e068 b.n 800782e <USBD_CDC_Setup+0x186>
  18686. case USB_REQ_TYPE_STANDARD:
  18687. switch (req->bRequest)
  18688. 800775c: 683b ldr r3, [r7, #0]
  18689. 800775e: 785b ldrb r3, [r3, #1]
  18690. 8007760: 2b0b cmp r3, #11
  18691. 8007762: d852 bhi.n 800780a <USBD_CDC_Setup+0x162>
  18692. 8007764: a201 add r2, pc, #4 ; (adr r2, 800776c <USBD_CDC_Setup+0xc4>)
  18693. 8007766: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  18694. 800776a: bf00 nop
  18695. 800776c: 0800779d .word 0x0800779d
  18696. 8007770: 08007819 .word 0x08007819
  18697. 8007774: 0800780b .word 0x0800780b
  18698. 8007778: 0800780b .word 0x0800780b
  18699. 800777c: 0800780b .word 0x0800780b
  18700. 8007780: 0800780b .word 0x0800780b
  18701. 8007784: 0800780b .word 0x0800780b
  18702. 8007788: 0800780b .word 0x0800780b
  18703. 800778c: 0800780b .word 0x0800780b
  18704. 8007790: 0800780b .word 0x0800780b
  18705. 8007794: 080077c7 .word 0x080077c7
  18706. 8007798: 080077f1 .word 0x080077f1
  18707. {
  18708. case USB_REQ_GET_STATUS:
  18709. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  18710. 800779c: 687b ldr r3, [r7, #4]
  18711. 800779e: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  18712. 80077a2: b2db uxtb r3, r3
  18713. 80077a4: 2b03 cmp r3, #3
  18714. 80077a6: d107 bne.n 80077b8 <USBD_CDC_Setup+0x110>
  18715. {
  18716. (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
  18717. 80077a8: f107 030a add.w r3, r7, #10
  18718. 80077ac: 2202 movs r2, #2
  18719. 80077ae: 4619 mov r1, r3
  18720. 80077b0: 6878 ldr r0, [r7, #4]
  18721. 80077b2: f001 face bl 8008d52 <USBD_CtlSendData>
  18722. else
  18723. {
  18724. USBD_CtlError(pdev, req);
  18725. ret = USBD_FAIL;
  18726. }
  18727. break;
  18728. 80077b6: e032 b.n 800781e <USBD_CDC_Setup+0x176>
  18729. USBD_CtlError(pdev, req);
  18730. 80077b8: 6839 ldr r1, [r7, #0]
  18731. 80077ba: 6878 ldr r0, [r7, #4]
  18732. 80077bc: f001 fa58 bl 8008c70 <USBD_CtlError>
  18733. ret = USBD_FAIL;
  18734. 80077c0: 2303 movs r3, #3
  18735. 80077c2: 75fb strb r3, [r7, #23]
  18736. break;
  18737. 80077c4: e02b b.n 800781e <USBD_CDC_Setup+0x176>
  18738. case USB_REQ_GET_INTERFACE:
  18739. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  18740. 80077c6: 687b ldr r3, [r7, #4]
  18741. 80077c8: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  18742. 80077cc: b2db uxtb r3, r3
  18743. 80077ce: 2b03 cmp r3, #3
  18744. 80077d0: d107 bne.n 80077e2 <USBD_CDC_Setup+0x13a>
  18745. {
  18746. (void)USBD_CtlSendData(pdev, &ifalt, 1U);
  18747. 80077d2: f107 030d add.w r3, r7, #13
  18748. 80077d6: 2201 movs r2, #1
  18749. 80077d8: 4619 mov r1, r3
  18750. 80077da: 6878 ldr r0, [r7, #4]
  18751. 80077dc: f001 fab9 bl 8008d52 <USBD_CtlSendData>
  18752. else
  18753. {
  18754. USBD_CtlError(pdev, req);
  18755. ret = USBD_FAIL;
  18756. }
  18757. break;
  18758. 80077e0: e01d b.n 800781e <USBD_CDC_Setup+0x176>
  18759. USBD_CtlError(pdev, req);
  18760. 80077e2: 6839 ldr r1, [r7, #0]
  18761. 80077e4: 6878 ldr r0, [r7, #4]
  18762. 80077e6: f001 fa43 bl 8008c70 <USBD_CtlError>
  18763. ret = USBD_FAIL;
  18764. 80077ea: 2303 movs r3, #3
  18765. 80077ec: 75fb strb r3, [r7, #23]
  18766. break;
  18767. 80077ee: e016 b.n 800781e <USBD_CDC_Setup+0x176>
  18768. case USB_REQ_SET_INTERFACE:
  18769. if (pdev->dev_state != USBD_STATE_CONFIGURED)
  18770. 80077f0: 687b ldr r3, [r7, #4]
  18771. 80077f2: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  18772. 80077f6: b2db uxtb r3, r3
  18773. 80077f8: 2b03 cmp r3, #3
  18774. 80077fa: d00f beq.n 800781c <USBD_CDC_Setup+0x174>
  18775. {
  18776. USBD_CtlError(pdev, req);
  18777. 80077fc: 6839 ldr r1, [r7, #0]
  18778. 80077fe: 6878 ldr r0, [r7, #4]
  18779. 8007800: f001 fa36 bl 8008c70 <USBD_CtlError>
  18780. ret = USBD_FAIL;
  18781. 8007804: 2303 movs r3, #3
  18782. 8007806: 75fb strb r3, [r7, #23]
  18783. }
  18784. break;
  18785. 8007808: e008 b.n 800781c <USBD_CDC_Setup+0x174>
  18786. case USB_REQ_CLEAR_FEATURE:
  18787. break;
  18788. default:
  18789. USBD_CtlError(pdev, req);
  18790. 800780a: 6839 ldr r1, [r7, #0]
  18791. 800780c: 6878 ldr r0, [r7, #4]
  18792. 800780e: f001 fa2f bl 8008c70 <USBD_CtlError>
  18793. ret = USBD_FAIL;
  18794. 8007812: 2303 movs r3, #3
  18795. 8007814: 75fb strb r3, [r7, #23]
  18796. break;
  18797. 8007816: e002 b.n 800781e <USBD_CDC_Setup+0x176>
  18798. break;
  18799. 8007818: bf00 nop
  18800. 800781a: e008 b.n 800782e <USBD_CDC_Setup+0x186>
  18801. break;
  18802. 800781c: bf00 nop
  18803. }
  18804. break;
  18805. 800781e: e006 b.n 800782e <USBD_CDC_Setup+0x186>
  18806. default:
  18807. USBD_CtlError(pdev, req);
  18808. 8007820: 6839 ldr r1, [r7, #0]
  18809. 8007822: 6878 ldr r0, [r7, #4]
  18810. 8007824: f001 fa24 bl 8008c70 <USBD_CtlError>
  18811. ret = USBD_FAIL;
  18812. 8007828: 2303 movs r3, #3
  18813. 800782a: 75fb strb r3, [r7, #23]
  18814. break;
  18815. 800782c: bf00 nop
  18816. }
  18817. return (uint8_t)ret;
  18818. 800782e: 7dfb ldrb r3, [r7, #23]
  18819. }
  18820. 8007830: 4618 mov r0, r3
  18821. 8007832: 3718 adds r7, #24
  18822. 8007834: 46bd mov sp, r7
  18823. 8007836: bd80 pop {r7, pc}
  18824. 08007838 <USBD_CDC_DataIn>:
  18825. * @param pdev: device instance
  18826. * @param epnum: endpoint number
  18827. * @retval status
  18828. */
  18829. static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
  18830. {
  18831. 8007838: b580 push {r7, lr}
  18832. 800783a: b084 sub sp, #16
  18833. 800783c: af00 add r7, sp, #0
  18834. 800783e: 6078 str r0, [r7, #4]
  18835. 8007840: 460b mov r3, r1
  18836. 8007842: 70fb strb r3, [r7, #3]
  18837. USBD_CDC_HandleTypeDef *hcdc;
  18838. PCD_HandleTypeDef *hpcd = pdev->pData;
  18839. 8007844: 687b ldr r3, [r7, #4]
  18840. 8007846: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4
  18841. 800784a: 60fb str r3, [r7, #12]
  18842. if (pdev->pClassData == NULL)
  18843. 800784c: 687b ldr r3, [r7, #4]
  18844. 800784e: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  18845. 8007852: 2b00 cmp r3, #0
  18846. 8007854: d101 bne.n 800785a <USBD_CDC_DataIn+0x22>
  18847. {
  18848. return (uint8_t)USBD_FAIL;
  18849. 8007856: 2303 movs r3, #3
  18850. 8007858: e04f b.n 80078fa <USBD_CDC_DataIn+0xc2>
  18851. }
  18852. hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
  18853. 800785a: 687b ldr r3, [r7, #4]
  18854. 800785c: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  18855. 8007860: 60bb str r3, [r7, #8]
  18856. if ((pdev->ep_in[epnum].total_length > 0U) &&
  18857. 8007862: 78fa ldrb r2, [r7, #3]
  18858. 8007864: 6879 ldr r1, [r7, #4]
  18859. 8007866: 4613 mov r3, r2
  18860. 8007868: 009b lsls r3, r3, #2
  18861. 800786a: 4413 add r3, r2
  18862. 800786c: 009b lsls r3, r3, #2
  18863. 800786e: 440b add r3, r1
  18864. 8007870: 3318 adds r3, #24
  18865. 8007872: 681b ldr r3, [r3, #0]
  18866. 8007874: 2b00 cmp r3, #0
  18867. 8007876: d029 beq.n 80078cc <USBD_CDC_DataIn+0x94>
  18868. ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U))
  18869. 8007878: 78fa ldrb r2, [r7, #3]
  18870. 800787a: 6879 ldr r1, [r7, #4]
  18871. 800787c: 4613 mov r3, r2
  18872. 800787e: 009b lsls r3, r3, #2
  18873. 8007880: 4413 add r3, r2
  18874. 8007882: 009b lsls r3, r3, #2
  18875. 8007884: 440b add r3, r1
  18876. 8007886: 3318 adds r3, #24
  18877. 8007888: 681a ldr r2, [r3, #0]
  18878. 800788a: 78f9 ldrb r1, [r7, #3]
  18879. 800788c: 68f8 ldr r0, [r7, #12]
  18880. 800788e: 460b mov r3, r1
  18881. 8007890: 00db lsls r3, r3, #3
  18882. 8007892: 1a5b subs r3, r3, r1
  18883. 8007894: 009b lsls r3, r3, #2
  18884. 8007896: 4403 add r3, r0
  18885. 8007898: 3344 adds r3, #68 ; 0x44
  18886. 800789a: 681b ldr r3, [r3, #0]
  18887. 800789c: fbb2 f1f3 udiv r1, r2, r3
  18888. 80078a0: fb03 f301 mul.w r3, r3, r1
  18889. 80078a4: 1ad3 subs r3, r2, r3
  18890. if ((pdev->ep_in[epnum].total_length > 0U) &&
  18891. 80078a6: 2b00 cmp r3, #0
  18892. 80078a8: d110 bne.n 80078cc <USBD_CDC_DataIn+0x94>
  18893. {
  18894. /* Update the packet total length */
  18895. pdev->ep_in[epnum].total_length = 0U;
  18896. 80078aa: 78fa ldrb r2, [r7, #3]
  18897. 80078ac: 6879 ldr r1, [r7, #4]
  18898. 80078ae: 4613 mov r3, r2
  18899. 80078b0: 009b lsls r3, r3, #2
  18900. 80078b2: 4413 add r3, r2
  18901. 80078b4: 009b lsls r3, r3, #2
  18902. 80078b6: 440b add r3, r1
  18903. 80078b8: 3318 adds r3, #24
  18904. 80078ba: 2200 movs r2, #0
  18905. 80078bc: 601a str r2, [r3, #0]
  18906. /* Send ZLP */
  18907. (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U);
  18908. 80078be: 78f9 ldrb r1, [r7, #3]
  18909. 80078c0: 2300 movs r3, #0
  18910. 80078c2: 2200 movs r2, #0
  18911. 80078c4: 6878 ldr r0, [r7, #4]
  18912. 80078c6: f001 ff70 bl 80097aa <USBD_LL_Transmit>
  18913. 80078ca: e015 b.n 80078f8 <USBD_CDC_DataIn+0xc0>
  18914. }
  18915. else
  18916. {
  18917. hcdc->TxState = 0U;
  18918. 80078cc: 68bb ldr r3, [r7, #8]
  18919. 80078ce: 2200 movs r2, #0
  18920. 80078d0: f8c3 2214 str.w r2, [r3, #532] ; 0x214
  18921. if (((USBD_CDC_ItfTypeDef *)pdev->pUserData)->TransmitCplt != NULL)
  18922. 80078d4: 687b ldr r3, [r7, #4]
  18923. 80078d6: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
  18924. 80078da: 691b ldr r3, [r3, #16]
  18925. 80078dc: 2b00 cmp r3, #0
  18926. 80078de: d00b beq.n 80078f8 <USBD_CDC_DataIn+0xc0>
  18927. {
  18928. ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum);
  18929. 80078e0: 687b ldr r3, [r7, #4]
  18930. 80078e2: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
  18931. 80078e6: 691b ldr r3, [r3, #16]
  18932. 80078e8: 68ba ldr r2, [r7, #8]
  18933. 80078ea: f8d2 0208 ldr.w r0, [r2, #520] ; 0x208
  18934. 80078ee: 68ba ldr r2, [r7, #8]
  18935. 80078f0: f502 7104 add.w r1, r2, #528 ; 0x210
  18936. 80078f4: 78fa ldrb r2, [r7, #3]
  18937. 80078f6: 4798 blx r3
  18938. }
  18939. }
  18940. return (uint8_t)USBD_OK;
  18941. 80078f8: 2300 movs r3, #0
  18942. }
  18943. 80078fa: 4618 mov r0, r3
  18944. 80078fc: 3710 adds r7, #16
  18945. 80078fe: 46bd mov sp, r7
  18946. 8007900: bd80 pop {r7, pc}
  18947. 08007902 <USBD_CDC_DataOut>:
  18948. * @param pdev: device instance
  18949. * @param epnum: endpoint number
  18950. * @retval status
  18951. */
  18952. static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
  18953. {
  18954. 8007902: b580 push {r7, lr}
  18955. 8007904: b084 sub sp, #16
  18956. 8007906: af00 add r7, sp, #0
  18957. 8007908: 6078 str r0, [r7, #4]
  18958. 800790a: 460b mov r3, r1
  18959. 800790c: 70fb strb r3, [r7, #3]
  18960. USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
  18961. 800790e: 687b ldr r3, [r7, #4]
  18962. 8007910: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  18963. 8007914: 60fb str r3, [r7, #12]
  18964. if (pdev->pClassData == NULL)
  18965. 8007916: 687b ldr r3, [r7, #4]
  18966. 8007918: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  18967. 800791c: 2b00 cmp r3, #0
  18968. 800791e: d101 bne.n 8007924 <USBD_CDC_DataOut+0x22>
  18969. {
  18970. return (uint8_t)USBD_FAIL;
  18971. 8007920: 2303 movs r3, #3
  18972. 8007922: e015 b.n 8007950 <USBD_CDC_DataOut+0x4e>
  18973. }
  18974. /* Get the received data length */
  18975. hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum);
  18976. 8007924: 78fb ldrb r3, [r7, #3]
  18977. 8007926: 4619 mov r1, r3
  18978. 8007928: 6878 ldr r0, [r7, #4]
  18979. 800792a: f001 ff80 bl 800982e <USBD_LL_GetRxDataSize>
  18980. 800792e: 4602 mov r2, r0
  18981. 8007930: 68fb ldr r3, [r7, #12]
  18982. 8007932: f8c3 220c str.w r2, [r3, #524] ; 0x20c
  18983. /* USB data will be immediately processed, this allow next USB traffic being
  18984. NAKed till the end of the application Xfer */
  18985. ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength);
  18986. 8007936: 687b ldr r3, [r7, #4]
  18987. 8007938: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
  18988. 800793c: 68db ldr r3, [r3, #12]
  18989. 800793e: 68fa ldr r2, [r7, #12]
  18990. 8007940: f8d2 0204 ldr.w r0, [r2, #516] ; 0x204
  18991. 8007944: 68fa ldr r2, [r7, #12]
  18992. 8007946: f502 7203 add.w r2, r2, #524 ; 0x20c
  18993. 800794a: 4611 mov r1, r2
  18994. 800794c: 4798 blx r3
  18995. return (uint8_t)USBD_OK;
  18996. 800794e: 2300 movs r3, #0
  18997. }
  18998. 8007950: 4618 mov r0, r3
  18999. 8007952: 3710 adds r7, #16
  19000. 8007954: 46bd mov sp, r7
  19001. 8007956: bd80 pop {r7, pc}
  19002. 08007958 <USBD_CDC_EP0_RxReady>:
  19003. * Handle EP0 Rx Ready event
  19004. * @param pdev: device instance
  19005. * @retval status
  19006. */
  19007. static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev)
  19008. {
  19009. 8007958: b580 push {r7, lr}
  19010. 800795a: b084 sub sp, #16
  19011. 800795c: af00 add r7, sp, #0
  19012. 800795e: 6078 str r0, [r7, #4]
  19013. USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
  19014. 8007960: 687b ldr r3, [r7, #4]
  19015. 8007962: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  19016. 8007966: 60fb str r3, [r7, #12]
  19017. if (hcdc == NULL)
  19018. 8007968: 68fb ldr r3, [r7, #12]
  19019. 800796a: 2b00 cmp r3, #0
  19020. 800796c: d101 bne.n 8007972 <USBD_CDC_EP0_RxReady+0x1a>
  19021. {
  19022. return (uint8_t)USBD_FAIL;
  19023. 800796e: 2303 movs r3, #3
  19024. 8007970: e01b b.n 80079aa <USBD_CDC_EP0_RxReady+0x52>
  19025. }
  19026. if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU))
  19027. 8007972: 687b ldr r3, [r7, #4]
  19028. 8007974: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
  19029. 8007978: 2b00 cmp r3, #0
  19030. 800797a: d015 beq.n 80079a8 <USBD_CDC_EP0_RxReady+0x50>
  19031. 800797c: 68fb ldr r3, [r7, #12]
  19032. 800797e: f893 3200 ldrb.w r3, [r3, #512] ; 0x200
  19033. 8007982: 2bff cmp r3, #255 ; 0xff
  19034. 8007984: d010 beq.n 80079a8 <USBD_CDC_EP0_RxReady+0x50>
  19035. {
  19036. ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
  19037. 8007986: 687b ldr r3, [r7, #4]
  19038. 8007988: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
  19039. 800798c: 689b ldr r3, [r3, #8]
  19040. 800798e: 68fa ldr r2, [r7, #12]
  19041. 8007990: f892 0200 ldrb.w r0, [r2, #512] ; 0x200
  19042. (uint8_t *)hcdc->data,
  19043. 8007994: 68f9 ldr r1, [r7, #12]
  19044. (uint16_t)hcdc->CmdLength);
  19045. 8007996: 68fa ldr r2, [r7, #12]
  19046. 8007998: f892 2201 ldrb.w r2, [r2, #513] ; 0x201
  19047. ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
  19048. 800799c: b292 uxth r2, r2
  19049. 800799e: 4798 blx r3
  19050. hcdc->CmdOpCode = 0xFFU;
  19051. 80079a0: 68fb ldr r3, [r7, #12]
  19052. 80079a2: 22ff movs r2, #255 ; 0xff
  19053. 80079a4: f883 2200 strb.w r2, [r3, #512] ; 0x200
  19054. }
  19055. return (uint8_t)USBD_OK;
  19056. 80079a8: 2300 movs r3, #0
  19057. }
  19058. 80079aa: 4618 mov r0, r3
  19059. 80079ac: 3710 adds r7, #16
  19060. 80079ae: 46bd mov sp, r7
  19061. 80079b0: bd80 pop {r7, pc}
  19062. ...
  19063. 080079b4 <USBD_CDC_GetFSCfgDesc>:
  19064. * @param speed : current device speed
  19065. * @param length : pointer data length
  19066. * @retval pointer to descriptor buffer
  19067. */
  19068. static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length)
  19069. {
  19070. 80079b4: b480 push {r7}
  19071. 80079b6: b083 sub sp, #12
  19072. 80079b8: af00 add r7, sp, #0
  19073. 80079ba: 6078 str r0, [r7, #4]
  19074. *length = (uint16_t)sizeof(USBD_CDC_CfgFSDesc);
  19075. 80079bc: 687b ldr r3, [r7, #4]
  19076. 80079be: 2243 movs r2, #67 ; 0x43
  19077. 80079c0: 801a strh r2, [r3, #0]
  19078. return USBD_CDC_CfgFSDesc;
  19079. 80079c2: 4b03 ldr r3, [pc, #12] ; (80079d0 <USBD_CDC_GetFSCfgDesc+0x1c>)
  19080. }
  19081. 80079c4: 4618 mov r0, r3
  19082. 80079c6: 370c adds r7, #12
  19083. 80079c8: 46bd mov sp, r7
  19084. 80079ca: f85d 7b04 ldr.w r7, [sp], #4
  19085. 80079ce: 4770 bx lr
  19086. 80079d0: 24000098 .word 0x24000098
  19087. 080079d4 <USBD_CDC_GetHSCfgDesc>:
  19088. * @param speed : current device speed
  19089. * @param length : pointer data length
  19090. * @retval pointer to descriptor buffer
  19091. */
  19092. static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length)
  19093. {
  19094. 80079d4: b480 push {r7}
  19095. 80079d6: b083 sub sp, #12
  19096. 80079d8: af00 add r7, sp, #0
  19097. 80079da: 6078 str r0, [r7, #4]
  19098. *length = (uint16_t)sizeof(USBD_CDC_CfgHSDesc);
  19099. 80079dc: 687b ldr r3, [r7, #4]
  19100. 80079de: 2243 movs r2, #67 ; 0x43
  19101. 80079e0: 801a strh r2, [r3, #0]
  19102. return USBD_CDC_CfgHSDesc;
  19103. 80079e2: 4b03 ldr r3, [pc, #12] ; (80079f0 <USBD_CDC_GetHSCfgDesc+0x1c>)
  19104. }
  19105. 80079e4: 4618 mov r0, r3
  19106. 80079e6: 370c adds r7, #12
  19107. 80079e8: 46bd mov sp, r7
  19108. 80079ea: f85d 7b04 ldr.w r7, [sp], #4
  19109. 80079ee: 4770 bx lr
  19110. 80079f0: 24000054 .word 0x24000054
  19111. 080079f4 <USBD_CDC_GetOtherSpeedCfgDesc>:
  19112. * @param speed : current device speed
  19113. * @param length : pointer data length
  19114. * @retval pointer to descriptor buffer
  19115. */
  19116. static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length)
  19117. {
  19118. 80079f4: b480 push {r7}
  19119. 80079f6: b083 sub sp, #12
  19120. 80079f8: af00 add r7, sp, #0
  19121. 80079fa: 6078 str r0, [r7, #4]
  19122. *length = (uint16_t)sizeof(USBD_CDC_OtherSpeedCfgDesc);
  19123. 80079fc: 687b ldr r3, [r7, #4]
  19124. 80079fe: 2243 movs r2, #67 ; 0x43
  19125. 8007a00: 801a strh r2, [r3, #0]
  19126. return USBD_CDC_OtherSpeedCfgDesc;
  19127. 8007a02: 4b03 ldr r3, [pc, #12] ; (8007a10 <USBD_CDC_GetOtherSpeedCfgDesc+0x1c>)
  19128. }
  19129. 8007a04: 4618 mov r0, r3
  19130. 8007a06: 370c adds r7, #12
  19131. 8007a08: 46bd mov sp, r7
  19132. 8007a0a: f85d 7b04 ldr.w r7, [sp], #4
  19133. 8007a0e: 4770 bx lr
  19134. 8007a10: 240000dc .word 0x240000dc
  19135. 08007a14 <USBD_CDC_GetDeviceQualifierDescriptor>:
  19136. * return Device Qualifier descriptor
  19137. * @param length : pointer data length
  19138. * @retval pointer to descriptor buffer
  19139. */
  19140. uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length)
  19141. {
  19142. 8007a14: b480 push {r7}
  19143. 8007a16: b083 sub sp, #12
  19144. 8007a18: af00 add r7, sp, #0
  19145. 8007a1a: 6078 str r0, [r7, #4]
  19146. *length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc);
  19147. 8007a1c: 687b ldr r3, [r7, #4]
  19148. 8007a1e: 220a movs r2, #10
  19149. 8007a20: 801a strh r2, [r3, #0]
  19150. return USBD_CDC_DeviceQualifierDesc;
  19151. 8007a22: 4b03 ldr r3, [pc, #12] ; (8007a30 <USBD_CDC_GetDeviceQualifierDescriptor+0x1c>)
  19152. }
  19153. 8007a24: 4618 mov r0, r3
  19154. 8007a26: 370c adds r7, #12
  19155. 8007a28: 46bd mov sp, r7
  19156. 8007a2a: f85d 7b04 ldr.w r7, [sp], #4
  19157. 8007a2e: 4770 bx lr
  19158. 8007a30: 24000010 .word 0x24000010
  19159. 08007a34 <USBD_CDC_RegisterInterface>:
  19160. * @param fops: CD Interface callback
  19161. * @retval status
  19162. */
  19163. uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev,
  19164. USBD_CDC_ItfTypeDef *fops)
  19165. {
  19166. 8007a34: b480 push {r7}
  19167. 8007a36: b083 sub sp, #12
  19168. 8007a38: af00 add r7, sp, #0
  19169. 8007a3a: 6078 str r0, [r7, #4]
  19170. 8007a3c: 6039 str r1, [r7, #0]
  19171. if (fops == NULL)
  19172. 8007a3e: 683b ldr r3, [r7, #0]
  19173. 8007a40: 2b00 cmp r3, #0
  19174. 8007a42: d101 bne.n 8007a48 <USBD_CDC_RegisterInterface+0x14>
  19175. {
  19176. return (uint8_t)USBD_FAIL;
  19177. 8007a44: 2303 movs r3, #3
  19178. 8007a46: e004 b.n 8007a52 <USBD_CDC_RegisterInterface+0x1e>
  19179. }
  19180. pdev->pUserData = fops;
  19181. 8007a48: 687b ldr r3, [r7, #4]
  19182. 8007a4a: 683a ldr r2, [r7, #0]
  19183. 8007a4c: f8c3 22c0 str.w r2, [r3, #704] ; 0x2c0
  19184. return (uint8_t)USBD_OK;
  19185. 8007a50: 2300 movs r3, #0
  19186. }
  19187. 8007a52: 4618 mov r0, r3
  19188. 8007a54: 370c adds r7, #12
  19189. 8007a56: 46bd mov sp, r7
  19190. 8007a58: f85d 7b04 ldr.w r7, [sp], #4
  19191. 8007a5c: 4770 bx lr
  19192. 08007a5e <USBD_CDC_SetTxBuffer>:
  19193. * @param pbuff: Tx Buffer
  19194. * @retval status
  19195. */
  19196. uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev,
  19197. uint8_t *pbuff, uint32_t length)
  19198. {
  19199. 8007a5e: b480 push {r7}
  19200. 8007a60: b087 sub sp, #28
  19201. 8007a62: af00 add r7, sp, #0
  19202. 8007a64: 60f8 str r0, [r7, #12]
  19203. 8007a66: 60b9 str r1, [r7, #8]
  19204. 8007a68: 607a str r2, [r7, #4]
  19205. USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
  19206. 8007a6a: 68fb ldr r3, [r7, #12]
  19207. 8007a6c: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  19208. 8007a70: 617b str r3, [r7, #20]
  19209. if (hcdc == NULL)
  19210. 8007a72: 697b ldr r3, [r7, #20]
  19211. 8007a74: 2b00 cmp r3, #0
  19212. 8007a76: d101 bne.n 8007a7c <USBD_CDC_SetTxBuffer+0x1e>
  19213. {
  19214. return (uint8_t)USBD_FAIL;
  19215. 8007a78: 2303 movs r3, #3
  19216. 8007a7a: e008 b.n 8007a8e <USBD_CDC_SetTxBuffer+0x30>
  19217. }
  19218. hcdc->TxBuffer = pbuff;
  19219. 8007a7c: 697b ldr r3, [r7, #20]
  19220. 8007a7e: 68ba ldr r2, [r7, #8]
  19221. 8007a80: f8c3 2208 str.w r2, [r3, #520] ; 0x208
  19222. hcdc->TxLength = length;
  19223. 8007a84: 697b ldr r3, [r7, #20]
  19224. 8007a86: 687a ldr r2, [r7, #4]
  19225. 8007a88: f8c3 2210 str.w r2, [r3, #528] ; 0x210
  19226. return (uint8_t)USBD_OK;
  19227. 8007a8c: 2300 movs r3, #0
  19228. }
  19229. 8007a8e: 4618 mov r0, r3
  19230. 8007a90: 371c adds r7, #28
  19231. 8007a92: 46bd mov sp, r7
  19232. 8007a94: f85d 7b04 ldr.w r7, [sp], #4
  19233. 8007a98: 4770 bx lr
  19234. 08007a9a <USBD_CDC_SetRxBuffer>:
  19235. * @param pdev: device instance
  19236. * @param pbuff: Rx Buffer
  19237. * @retval status
  19238. */
  19239. uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff)
  19240. {
  19241. 8007a9a: b480 push {r7}
  19242. 8007a9c: b085 sub sp, #20
  19243. 8007a9e: af00 add r7, sp, #0
  19244. 8007aa0: 6078 str r0, [r7, #4]
  19245. 8007aa2: 6039 str r1, [r7, #0]
  19246. USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
  19247. 8007aa4: 687b ldr r3, [r7, #4]
  19248. 8007aa6: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  19249. 8007aaa: 60fb str r3, [r7, #12]
  19250. if (hcdc == NULL)
  19251. 8007aac: 68fb ldr r3, [r7, #12]
  19252. 8007aae: 2b00 cmp r3, #0
  19253. 8007ab0: d101 bne.n 8007ab6 <USBD_CDC_SetRxBuffer+0x1c>
  19254. {
  19255. return (uint8_t)USBD_FAIL;
  19256. 8007ab2: 2303 movs r3, #3
  19257. 8007ab4: e004 b.n 8007ac0 <USBD_CDC_SetRxBuffer+0x26>
  19258. }
  19259. hcdc->RxBuffer = pbuff;
  19260. 8007ab6: 68fb ldr r3, [r7, #12]
  19261. 8007ab8: 683a ldr r2, [r7, #0]
  19262. 8007aba: f8c3 2204 str.w r2, [r3, #516] ; 0x204
  19263. return (uint8_t)USBD_OK;
  19264. 8007abe: 2300 movs r3, #0
  19265. }
  19266. 8007ac0: 4618 mov r0, r3
  19267. 8007ac2: 3714 adds r7, #20
  19268. 8007ac4: 46bd mov sp, r7
  19269. 8007ac6: f85d 7b04 ldr.w r7, [sp], #4
  19270. 8007aca: 4770 bx lr
  19271. 08007acc <USBD_CDC_TransmitPacket>:
  19272. * Transmit packet on IN endpoint
  19273. * @param pdev: device instance
  19274. * @retval status
  19275. */
  19276. uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
  19277. {
  19278. 8007acc: b580 push {r7, lr}
  19279. 8007ace: b084 sub sp, #16
  19280. 8007ad0: af00 add r7, sp, #0
  19281. 8007ad2: 6078 str r0, [r7, #4]
  19282. USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
  19283. 8007ad4: 687b ldr r3, [r7, #4]
  19284. 8007ad6: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  19285. 8007ada: 60bb str r3, [r7, #8]
  19286. USBD_StatusTypeDef ret = USBD_BUSY;
  19287. 8007adc: 2301 movs r3, #1
  19288. 8007ade: 73fb strb r3, [r7, #15]
  19289. if (pdev->pClassData == NULL)
  19290. 8007ae0: 687b ldr r3, [r7, #4]
  19291. 8007ae2: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  19292. 8007ae6: 2b00 cmp r3, #0
  19293. 8007ae8: d101 bne.n 8007aee <USBD_CDC_TransmitPacket+0x22>
  19294. {
  19295. return (uint8_t)USBD_FAIL;
  19296. 8007aea: 2303 movs r3, #3
  19297. 8007aec: e01a b.n 8007b24 <USBD_CDC_TransmitPacket+0x58>
  19298. }
  19299. if (hcdc->TxState == 0U)
  19300. 8007aee: 68bb ldr r3, [r7, #8]
  19301. 8007af0: f8d3 3214 ldr.w r3, [r3, #532] ; 0x214
  19302. 8007af4: 2b00 cmp r3, #0
  19303. 8007af6: d114 bne.n 8007b22 <USBD_CDC_TransmitPacket+0x56>
  19304. {
  19305. /* Tx Transfer in progress */
  19306. hcdc->TxState = 1U;
  19307. 8007af8: 68bb ldr r3, [r7, #8]
  19308. 8007afa: 2201 movs r2, #1
  19309. 8007afc: f8c3 2214 str.w r2, [r3, #532] ; 0x214
  19310. /* Update the packet total length */
  19311. pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength;
  19312. 8007b00: 68bb ldr r3, [r7, #8]
  19313. 8007b02: f8d3 2210 ldr.w r2, [r3, #528] ; 0x210
  19314. 8007b06: 687b ldr r3, [r7, #4]
  19315. 8007b08: 62da str r2, [r3, #44] ; 0x2c
  19316. /* Transmit next packet */
  19317. (void)USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer, hcdc->TxLength);
  19318. 8007b0a: 68bb ldr r3, [r7, #8]
  19319. 8007b0c: f8d3 2208 ldr.w r2, [r3, #520] ; 0x208
  19320. 8007b10: 68bb ldr r3, [r7, #8]
  19321. 8007b12: f8d3 3210 ldr.w r3, [r3, #528] ; 0x210
  19322. 8007b16: 2181 movs r1, #129 ; 0x81
  19323. 8007b18: 6878 ldr r0, [r7, #4]
  19324. 8007b1a: f001 fe46 bl 80097aa <USBD_LL_Transmit>
  19325. ret = USBD_OK;
  19326. 8007b1e: 2300 movs r3, #0
  19327. 8007b20: 73fb strb r3, [r7, #15]
  19328. }
  19329. return (uint8_t)ret;
  19330. 8007b22: 7bfb ldrb r3, [r7, #15]
  19331. }
  19332. 8007b24: 4618 mov r0, r3
  19333. 8007b26: 3710 adds r7, #16
  19334. 8007b28: 46bd mov sp, r7
  19335. 8007b2a: bd80 pop {r7, pc}
  19336. 08007b2c <USBD_CDC_ReceivePacket>:
  19337. * prepare OUT Endpoint for reception
  19338. * @param pdev: device instance
  19339. * @retval status
  19340. */
  19341. uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)
  19342. {
  19343. 8007b2c: b580 push {r7, lr}
  19344. 8007b2e: b084 sub sp, #16
  19345. 8007b30: af00 add r7, sp, #0
  19346. 8007b32: 6078 str r0, [r7, #4]
  19347. USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
  19348. 8007b34: 687b ldr r3, [r7, #4]
  19349. 8007b36: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  19350. 8007b3a: 60fb str r3, [r7, #12]
  19351. if (pdev->pClassData == NULL)
  19352. 8007b3c: 687b ldr r3, [r7, #4]
  19353. 8007b3e: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  19354. 8007b42: 2b00 cmp r3, #0
  19355. 8007b44: d101 bne.n 8007b4a <USBD_CDC_ReceivePacket+0x1e>
  19356. {
  19357. return (uint8_t)USBD_FAIL;
  19358. 8007b46: 2303 movs r3, #3
  19359. 8007b48: e016 b.n 8007b78 <USBD_CDC_ReceivePacket+0x4c>
  19360. }
  19361. if (pdev->dev_speed == USBD_SPEED_HIGH)
  19362. 8007b4a: 687b ldr r3, [r7, #4]
  19363. 8007b4c: 7c1b ldrb r3, [r3, #16]
  19364. 8007b4e: 2b00 cmp r3, #0
  19365. 8007b50: d109 bne.n 8007b66 <USBD_CDC_ReceivePacket+0x3a>
  19366. {
  19367. /* Prepare Out endpoint to receive next packet */
  19368. (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
  19369. 8007b52: 68fb ldr r3, [r7, #12]
  19370. 8007b54: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
  19371. 8007b58: f44f 7300 mov.w r3, #512 ; 0x200
  19372. 8007b5c: 2101 movs r1, #1
  19373. 8007b5e: 6878 ldr r0, [r7, #4]
  19374. 8007b60: f001 fe44 bl 80097ec <USBD_LL_PrepareReceive>
  19375. 8007b64: e007 b.n 8007b76 <USBD_CDC_ReceivePacket+0x4a>
  19376. CDC_DATA_HS_OUT_PACKET_SIZE);
  19377. }
  19378. else
  19379. {
  19380. /* Prepare Out endpoint to receive next packet */
  19381. (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
  19382. 8007b66: 68fb ldr r3, [r7, #12]
  19383. 8007b68: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
  19384. 8007b6c: 2340 movs r3, #64 ; 0x40
  19385. 8007b6e: 2101 movs r1, #1
  19386. 8007b70: 6878 ldr r0, [r7, #4]
  19387. 8007b72: f001 fe3b bl 80097ec <USBD_LL_PrepareReceive>
  19388. CDC_DATA_FS_OUT_PACKET_SIZE);
  19389. }
  19390. return (uint8_t)USBD_OK;
  19391. 8007b76: 2300 movs r3, #0
  19392. }
  19393. 8007b78: 4618 mov r0, r3
  19394. 8007b7a: 3710 adds r7, #16
  19395. 8007b7c: 46bd mov sp, r7
  19396. 8007b7e: bd80 pop {r7, pc}
  19397. 08007b80 <USBD_Init>:
  19398. * @param id: Low level core index
  19399. * @retval None
  19400. */
  19401. USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
  19402. USBD_DescriptorsTypeDef *pdesc, uint8_t id)
  19403. {
  19404. 8007b80: b580 push {r7, lr}
  19405. 8007b82: b086 sub sp, #24
  19406. 8007b84: af00 add r7, sp, #0
  19407. 8007b86: 60f8 str r0, [r7, #12]
  19408. 8007b88: 60b9 str r1, [r7, #8]
  19409. 8007b8a: 4613 mov r3, r2
  19410. 8007b8c: 71fb strb r3, [r7, #7]
  19411. USBD_StatusTypeDef ret;
  19412. /* Check whether the USB Host handle is valid */
  19413. if (pdev == NULL)
  19414. 8007b8e: 68fb ldr r3, [r7, #12]
  19415. 8007b90: 2b00 cmp r3, #0
  19416. 8007b92: d101 bne.n 8007b98 <USBD_Init+0x18>
  19417. {
  19418. #if (USBD_DEBUG_LEVEL > 1U)
  19419. USBD_ErrLog("Invalid Device handle");
  19420. #endif
  19421. return USBD_FAIL;
  19422. 8007b94: 2303 movs r3, #3
  19423. 8007b96: e01f b.n 8007bd8 <USBD_Init+0x58>
  19424. }
  19425. /* Unlink previous class resources */
  19426. pdev->pClass = NULL;
  19427. 8007b98: 68fb ldr r3, [r7, #12]
  19428. 8007b9a: 2200 movs r2, #0
  19429. 8007b9c: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8
  19430. pdev->pUserData = NULL;
  19431. 8007ba0: 68fb ldr r3, [r7, #12]
  19432. 8007ba2: 2200 movs r2, #0
  19433. 8007ba4: f8c3 22c0 str.w r2, [r3, #704] ; 0x2c0
  19434. pdev->pConfDesc = NULL;
  19435. 8007ba8: 68fb ldr r3, [r7, #12]
  19436. 8007baa: 2200 movs r2, #0
  19437. 8007bac: f8c3 22cc str.w r2, [r3, #716] ; 0x2cc
  19438. /* Assign USBD Descriptors */
  19439. if (pdesc != NULL)
  19440. 8007bb0: 68bb ldr r3, [r7, #8]
  19441. 8007bb2: 2b00 cmp r3, #0
  19442. 8007bb4: d003 beq.n 8007bbe <USBD_Init+0x3e>
  19443. {
  19444. pdev->pDesc = pdesc;
  19445. 8007bb6: 68fb ldr r3, [r7, #12]
  19446. 8007bb8: 68ba ldr r2, [r7, #8]
  19447. 8007bba: f8c3 22b4 str.w r2, [r3, #692] ; 0x2b4
  19448. }
  19449. /* Set Device initial State */
  19450. pdev->dev_state = USBD_STATE_DEFAULT;
  19451. 8007bbe: 68fb ldr r3, [r7, #12]
  19452. 8007bc0: 2201 movs r2, #1
  19453. 8007bc2: f883 229c strb.w r2, [r3, #668] ; 0x29c
  19454. pdev->id = id;
  19455. 8007bc6: 68fb ldr r3, [r7, #12]
  19456. 8007bc8: 79fa ldrb r2, [r7, #7]
  19457. 8007bca: 701a strb r2, [r3, #0]
  19458. /* Initialize low level driver */
  19459. ret = USBD_LL_Init(pdev);
  19460. 8007bcc: 68f8 ldr r0, [r7, #12]
  19461. 8007bce: f001 fcad bl 800952c <USBD_LL_Init>
  19462. 8007bd2: 4603 mov r3, r0
  19463. 8007bd4: 75fb strb r3, [r7, #23]
  19464. return ret;
  19465. 8007bd6: 7dfb ldrb r3, [r7, #23]
  19466. }
  19467. 8007bd8: 4618 mov r0, r3
  19468. 8007bda: 3718 adds r7, #24
  19469. 8007bdc: 46bd mov sp, r7
  19470. 8007bde: bd80 pop {r7, pc}
  19471. 08007be0 <USBD_RegisterClass>:
  19472. * @param pDevice : Device Handle
  19473. * @param pclass: Class handle
  19474. * @retval USBD Status
  19475. */
  19476. USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
  19477. {
  19478. 8007be0: b580 push {r7, lr}
  19479. 8007be2: b084 sub sp, #16
  19480. 8007be4: af00 add r7, sp, #0
  19481. 8007be6: 6078 str r0, [r7, #4]
  19482. 8007be8: 6039 str r1, [r7, #0]
  19483. uint16_t len = 0U;
  19484. 8007bea: 2300 movs r3, #0
  19485. 8007bec: 81fb strh r3, [r7, #14]
  19486. if (pclass == NULL)
  19487. 8007bee: 683b ldr r3, [r7, #0]
  19488. 8007bf0: 2b00 cmp r3, #0
  19489. 8007bf2: d101 bne.n 8007bf8 <USBD_RegisterClass+0x18>
  19490. {
  19491. #if (USBD_DEBUG_LEVEL > 1U)
  19492. USBD_ErrLog("Invalid Class handle");
  19493. #endif
  19494. return USBD_FAIL;
  19495. 8007bf4: 2303 movs r3, #3
  19496. 8007bf6: e016 b.n 8007c26 <USBD_RegisterClass+0x46>
  19497. }
  19498. /* link the class to the USB Device handle */
  19499. pdev->pClass = pclass;
  19500. 8007bf8: 687b ldr r3, [r7, #4]
  19501. 8007bfa: 683a ldr r2, [r7, #0]
  19502. 8007bfc: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8
  19503. if (pdev->pClass->GetHSConfigDescriptor != NULL)
  19504. {
  19505. pdev->pConfDesc = (void *)pdev->pClass->GetHSConfigDescriptor(&len);
  19506. }
  19507. #else /* Default USE_USB_FS */
  19508. if (pdev->pClass->GetFSConfigDescriptor != NULL)
  19509. 8007c00: 687b ldr r3, [r7, #4]
  19510. 8007c02: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  19511. 8007c06: 6adb ldr r3, [r3, #44] ; 0x2c
  19512. 8007c08: 2b00 cmp r3, #0
  19513. 8007c0a: d00b beq.n 8007c24 <USBD_RegisterClass+0x44>
  19514. {
  19515. pdev->pConfDesc = (void *)pdev->pClass->GetFSConfigDescriptor(&len);
  19516. 8007c0c: 687b ldr r3, [r7, #4]
  19517. 8007c0e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  19518. 8007c12: 6adb ldr r3, [r3, #44] ; 0x2c
  19519. 8007c14: f107 020e add.w r2, r7, #14
  19520. 8007c18: 4610 mov r0, r2
  19521. 8007c1a: 4798 blx r3
  19522. 8007c1c: 4602 mov r2, r0
  19523. 8007c1e: 687b ldr r3, [r7, #4]
  19524. 8007c20: f8c3 22cc str.w r2, [r3, #716] ; 0x2cc
  19525. }
  19526. #endif /* USE_USB_FS */
  19527. return USBD_OK;
  19528. 8007c24: 2300 movs r3, #0
  19529. }
  19530. 8007c26: 4618 mov r0, r3
  19531. 8007c28: 3710 adds r7, #16
  19532. 8007c2a: 46bd mov sp, r7
  19533. 8007c2c: bd80 pop {r7, pc}
  19534. 08007c2e <USBD_Start>:
  19535. * Start the USB Device Core.
  19536. * @param pdev: Device Handle
  19537. * @retval USBD Status
  19538. */
  19539. USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
  19540. {
  19541. 8007c2e: b580 push {r7, lr}
  19542. 8007c30: b082 sub sp, #8
  19543. 8007c32: af00 add r7, sp, #0
  19544. 8007c34: 6078 str r0, [r7, #4]
  19545. /* Start the low level driver */
  19546. return USBD_LL_Start(pdev);
  19547. 8007c36: 6878 ldr r0, [r7, #4]
  19548. 8007c38: f001 fcce bl 80095d8 <USBD_LL_Start>
  19549. 8007c3c: 4603 mov r3, r0
  19550. }
  19551. 8007c3e: 4618 mov r0, r3
  19552. 8007c40: 3708 adds r7, #8
  19553. 8007c42: 46bd mov sp, r7
  19554. 8007c44: bd80 pop {r7, pc}
  19555. 08007c46 <USBD_RunTestMode>:
  19556. * Launch test mode process
  19557. * @param pdev: device instance
  19558. * @retval status
  19559. */
  19560. USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
  19561. {
  19562. 8007c46: b480 push {r7}
  19563. 8007c48: b083 sub sp, #12
  19564. 8007c4a: af00 add r7, sp, #0
  19565. 8007c4c: 6078 str r0, [r7, #4]
  19566. /* Prevent unused argument compilation warning */
  19567. UNUSED(pdev);
  19568. return USBD_OK;
  19569. 8007c4e: 2300 movs r3, #0
  19570. }
  19571. 8007c50: 4618 mov r0, r3
  19572. 8007c52: 370c adds r7, #12
  19573. 8007c54: 46bd mov sp, r7
  19574. 8007c56: f85d 7b04 ldr.w r7, [sp], #4
  19575. 8007c5a: 4770 bx lr
  19576. 08007c5c <USBD_SetClassConfig>:
  19577. * @param cfgidx: configuration index
  19578. * @retval status
  19579. */
  19580. USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
  19581. {
  19582. 8007c5c: b580 push {r7, lr}
  19583. 8007c5e: b084 sub sp, #16
  19584. 8007c60: af00 add r7, sp, #0
  19585. 8007c62: 6078 str r0, [r7, #4]
  19586. 8007c64: 460b mov r3, r1
  19587. 8007c66: 70fb strb r3, [r7, #3]
  19588. USBD_StatusTypeDef ret = USBD_FAIL;
  19589. 8007c68: 2303 movs r3, #3
  19590. 8007c6a: 73fb strb r3, [r7, #15]
  19591. if (pdev->pClass != NULL)
  19592. 8007c6c: 687b ldr r3, [r7, #4]
  19593. 8007c6e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  19594. 8007c72: 2b00 cmp r3, #0
  19595. 8007c74: d009 beq.n 8007c8a <USBD_SetClassConfig+0x2e>
  19596. {
  19597. /* Set configuration and Start the Class */
  19598. ret = (USBD_StatusTypeDef)pdev->pClass->Init(pdev, cfgidx);
  19599. 8007c76: 687b ldr r3, [r7, #4]
  19600. 8007c78: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  19601. 8007c7c: 681b ldr r3, [r3, #0]
  19602. 8007c7e: 78fa ldrb r2, [r7, #3]
  19603. 8007c80: 4611 mov r1, r2
  19604. 8007c82: 6878 ldr r0, [r7, #4]
  19605. 8007c84: 4798 blx r3
  19606. 8007c86: 4603 mov r3, r0
  19607. 8007c88: 73fb strb r3, [r7, #15]
  19608. }
  19609. return ret;
  19610. 8007c8a: 7bfb ldrb r3, [r7, #15]
  19611. }
  19612. 8007c8c: 4618 mov r0, r3
  19613. 8007c8e: 3710 adds r7, #16
  19614. 8007c90: 46bd mov sp, r7
  19615. 8007c92: bd80 pop {r7, pc}
  19616. 08007c94 <USBD_ClrClassConfig>:
  19617. * @param pdev: device instance
  19618. * @param cfgidx: configuration index
  19619. * @retval status: USBD_StatusTypeDef
  19620. */
  19621. USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
  19622. {
  19623. 8007c94: b580 push {r7, lr}
  19624. 8007c96: b082 sub sp, #8
  19625. 8007c98: af00 add r7, sp, #0
  19626. 8007c9a: 6078 str r0, [r7, #4]
  19627. 8007c9c: 460b mov r3, r1
  19628. 8007c9e: 70fb strb r3, [r7, #3]
  19629. /* Clear configuration and De-initialize the Class process */
  19630. if (pdev->pClass != NULL)
  19631. 8007ca0: 687b ldr r3, [r7, #4]
  19632. 8007ca2: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  19633. 8007ca6: 2b00 cmp r3, #0
  19634. 8007ca8: d007 beq.n 8007cba <USBD_ClrClassConfig+0x26>
  19635. {
  19636. pdev->pClass->DeInit(pdev, cfgidx);
  19637. 8007caa: 687b ldr r3, [r7, #4]
  19638. 8007cac: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  19639. 8007cb0: 685b ldr r3, [r3, #4]
  19640. 8007cb2: 78fa ldrb r2, [r7, #3]
  19641. 8007cb4: 4611 mov r1, r2
  19642. 8007cb6: 6878 ldr r0, [r7, #4]
  19643. 8007cb8: 4798 blx r3
  19644. }
  19645. return USBD_OK;
  19646. 8007cba: 2300 movs r3, #0
  19647. }
  19648. 8007cbc: 4618 mov r0, r3
  19649. 8007cbe: 3708 adds r7, #8
  19650. 8007cc0: 46bd mov sp, r7
  19651. 8007cc2: bd80 pop {r7, pc}
  19652. 08007cc4 <USBD_LL_SetupStage>:
  19653. * Handle the setup stage
  19654. * @param pdev: device instance
  19655. * @retval status
  19656. */
  19657. USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
  19658. {
  19659. 8007cc4: b580 push {r7, lr}
  19660. 8007cc6: b084 sub sp, #16
  19661. 8007cc8: af00 add r7, sp, #0
  19662. 8007cca: 6078 str r0, [r7, #4]
  19663. 8007ccc: 6039 str r1, [r7, #0]
  19664. USBD_StatusTypeDef ret;
  19665. USBD_ParseSetupRequest(&pdev->request, psetup);
  19666. 8007cce: 687b ldr r3, [r7, #4]
  19667. 8007cd0: f203 23aa addw r3, r3, #682 ; 0x2aa
  19668. 8007cd4: 6839 ldr r1, [r7, #0]
  19669. 8007cd6: 4618 mov r0, r3
  19670. 8007cd8: f000 ff90 bl 8008bfc <USBD_ParseSetupRequest>
  19671. pdev->ep0_state = USBD_EP0_SETUP;
  19672. 8007cdc: 687b ldr r3, [r7, #4]
  19673. 8007cde: 2201 movs r2, #1
  19674. 8007ce0: f8c3 2294 str.w r2, [r3, #660] ; 0x294
  19675. pdev->ep0_data_len = pdev->request.wLength;
  19676. 8007ce4: 687b ldr r3, [r7, #4]
  19677. 8007ce6: f8b3 32b0 ldrh.w r3, [r3, #688] ; 0x2b0
  19678. 8007cea: 461a mov r2, r3
  19679. 8007cec: 687b ldr r3, [r7, #4]
  19680. 8007cee: f8c3 2298 str.w r2, [r3, #664] ; 0x298
  19681. switch (pdev->request.bmRequest & 0x1FU)
  19682. 8007cf2: 687b ldr r3, [r7, #4]
  19683. 8007cf4: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa
  19684. 8007cf8: f003 031f and.w r3, r3, #31
  19685. 8007cfc: 2b02 cmp r3, #2
  19686. 8007cfe: d01a beq.n 8007d36 <USBD_LL_SetupStage+0x72>
  19687. 8007d00: 2b02 cmp r3, #2
  19688. 8007d02: d822 bhi.n 8007d4a <USBD_LL_SetupStage+0x86>
  19689. 8007d04: 2b00 cmp r3, #0
  19690. 8007d06: d002 beq.n 8007d0e <USBD_LL_SetupStage+0x4a>
  19691. 8007d08: 2b01 cmp r3, #1
  19692. 8007d0a: d00a beq.n 8007d22 <USBD_LL_SetupStage+0x5e>
  19693. 8007d0c: e01d b.n 8007d4a <USBD_LL_SetupStage+0x86>
  19694. {
  19695. case USB_REQ_RECIPIENT_DEVICE:
  19696. ret = USBD_StdDevReq(pdev, &pdev->request);
  19697. 8007d0e: 687b ldr r3, [r7, #4]
  19698. 8007d10: f203 23aa addw r3, r3, #682 ; 0x2aa
  19699. 8007d14: 4619 mov r1, r3
  19700. 8007d16: 6878 ldr r0, [r7, #4]
  19701. 8007d18: f000 fa62 bl 80081e0 <USBD_StdDevReq>
  19702. 8007d1c: 4603 mov r3, r0
  19703. 8007d1e: 73fb strb r3, [r7, #15]
  19704. break;
  19705. 8007d20: e020 b.n 8007d64 <USBD_LL_SetupStage+0xa0>
  19706. case USB_REQ_RECIPIENT_INTERFACE:
  19707. ret = USBD_StdItfReq(pdev, &pdev->request);
  19708. 8007d22: 687b ldr r3, [r7, #4]
  19709. 8007d24: f203 23aa addw r3, r3, #682 ; 0x2aa
  19710. 8007d28: 4619 mov r1, r3
  19711. 8007d2a: 6878 ldr r0, [r7, #4]
  19712. 8007d2c: f000 fac6 bl 80082bc <USBD_StdItfReq>
  19713. 8007d30: 4603 mov r3, r0
  19714. 8007d32: 73fb strb r3, [r7, #15]
  19715. break;
  19716. 8007d34: e016 b.n 8007d64 <USBD_LL_SetupStage+0xa0>
  19717. case USB_REQ_RECIPIENT_ENDPOINT:
  19718. ret = USBD_StdEPReq(pdev, &pdev->request);
  19719. 8007d36: 687b ldr r3, [r7, #4]
  19720. 8007d38: f203 23aa addw r3, r3, #682 ; 0x2aa
  19721. 8007d3c: 4619 mov r1, r3
  19722. 8007d3e: 6878 ldr r0, [r7, #4]
  19723. 8007d40: f000 fb05 bl 800834e <USBD_StdEPReq>
  19724. 8007d44: 4603 mov r3, r0
  19725. 8007d46: 73fb strb r3, [r7, #15]
  19726. break;
  19727. 8007d48: e00c b.n 8007d64 <USBD_LL_SetupStage+0xa0>
  19728. default:
  19729. ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
  19730. 8007d4a: 687b ldr r3, [r7, #4]
  19731. 8007d4c: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa
  19732. 8007d50: f023 037f bic.w r3, r3, #127 ; 0x7f
  19733. 8007d54: b2db uxtb r3, r3
  19734. 8007d56: 4619 mov r1, r3
  19735. 8007d58: 6878 ldr r0, [r7, #4]
  19736. 8007d5a: f001 fc9d bl 8009698 <USBD_LL_StallEP>
  19737. 8007d5e: 4603 mov r3, r0
  19738. 8007d60: 73fb strb r3, [r7, #15]
  19739. break;
  19740. 8007d62: bf00 nop
  19741. }
  19742. return ret;
  19743. 8007d64: 7bfb ldrb r3, [r7, #15]
  19744. }
  19745. 8007d66: 4618 mov r0, r3
  19746. 8007d68: 3710 adds r7, #16
  19747. 8007d6a: 46bd mov sp, r7
  19748. 8007d6c: bd80 pop {r7, pc}
  19749. 08007d6e <USBD_LL_DataOutStage>:
  19750. * @param pdata: data pointer
  19751. * @retval status
  19752. */
  19753. USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
  19754. uint8_t epnum, uint8_t *pdata)
  19755. {
  19756. 8007d6e: b580 push {r7, lr}
  19757. 8007d70: b086 sub sp, #24
  19758. 8007d72: af00 add r7, sp, #0
  19759. 8007d74: 60f8 str r0, [r7, #12]
  19760. 8007d76: 460b mov r3, r1
  19761. 8007d78: 607a str r2, [r7, #4]
  19762. 8007d7a: 72fb strb r3, [r7, #11]
  19763. USBD_EndpointTypeDef *pep;
  19764. USBD_StatusTypeDef ret;
  19765. if (epnum == 0U)
  19766. 8007d7c: 7afb ldrb r3, [r7, #11]
  19767. 8007d7e: 2b00 cmp r3, #0
  19768. 8007d80: d138 bne.n 8007df4 <USBD_LL_DataOutStage+0x86>
  19769. {
  19770. pep = &pdev->ep_out[0];
  19771. 8007d82: 68fb ldr r3, [r7, #12]
  19772. 8007d84: f503 73aa add.w r3, r3, #340 ; 0x154
  19773. 8007d88: 613b str r3, [r7, #16]
  19774. if (pdev->ep0_state == USBD_EP0_DATA_OUT)
  19775. 8007d8a: 68fb ldr r3, [r7, #12]
  19776. 8007d8c: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294
  19777. 8007d90: 2b03 cmp r3, #3
  19778. 8007d92: d14a bne.n 8007e2a <USBD_LL_DataOutStage+0xbc>
  19779. {
  19780. if (pep->rem_length > pep->maxpacket)
  19781. 8007d94: 693b ldr r3, [r7, #16]
  19782. 8007d96: 689a ldr r2, [r3, #8]
  19783. 8007d98: 693b ldr r3, [r7, #16]
  19784. 8007d9a: 68db ldr r3, [r3, #12]
  19785. 8007d9c: 429a cmp r2, r3
  19786. 8007d9e: d913 bls.n 8007dc8 <USBD_LL_DataOutStage+0x5a>
  19787. {
  19788. pep->rem_length -= pep->maxpacket;
  19789. 8007da0: 693b ldr r3, [r7, #16]
  19790. 8007da2: 689a ldr r2, [r3, #8]
  19791. 8007da4: 693b ldr r3, [r7, #16]
  19792. 8007da6: 68db ldr r3, [r3, #12]
  19793. 8007da8: 1ad2 subs r2, r2, r3
  19794. 8007daa: 693b ldr r3, [r7, #16]
  19795. 8007dac: 609a str r2, [r3, #8]
  19796. (void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket));
  19797. 8007dae: 693b ldr r3, [r7, #16]
  19798. 8007db0: 68da ldr r2, [r3, #12]
  19799. 8007db2: 693b ldr r3, [r7, #16]
  19800. 8007db4: 689b ldr r3, [r3, #8]
  19801. 8007db6: 4293 cmp r3, r2
  19802. 8007db8: bf28 it cs
  19803. 8007dba: 4613 movcs r3, r2
  19804. 8007dbc: 461a mov r2, r3
  19805. 8007dbe: 6879 ldr r1, [r7, #4]
  19806. 8007dc0: 68f8 ldr r0, [r7, #12]
  19807. 8007dc2: f001 f80f bl 8008de4 <USBD_CtlContinueRx>
  19808. 8007dc6: e030 b.n 8007e2a <USBD_LL_DataOutStage+0xbc>
  19809. }
  19810. else
  19811. {
  19812. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  19813. 8007dc8: 68fb ldr r3, [r7, #12]
  19814. 8007dca: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  19815. 8007dce: b2db uxtb r3, r3
  19816. 8007dd0: 2b03 cmp r3, #3
  19817. 8007dd2: d10b bne.n 8007dec <USBD_LL_DataOutStage+0x7e>
  19818. {
  19819. if (pdev->pClass->EP0_RxReady != NULL)
  19820. 8007dd4: 68fb ldr r3, [r7, #12]
  19821. 8007dd6: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  19822. 8007dda: 691b ldr r3, [r3, #16]
  19823. 8007ddc: 2b00 cmp r3, #0
  19824. 8007dde: d005 beq.n 8007dec <USBD_LL_DataOutStage+0x7e>
  19825. {
  19826. pdev->pClass->EP0_RxReady(pdev);
  19827. 8007de0: 68fb ldr r3, [r7, #12]
  19828. 8007de2: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  19829. 8007de6: 691b ldr r3, [r3, #16]
  19830. 8007de8: 68f8 ldr r0, [r7, #12]
  19831. 8007dea: 4798 blx r3
  19832. }
  19833. }
  19834. (void)USBD_CtlSendStatus(pdev);
  19835. 8007dec: 68f8 ldr r0, [r7, #12]
  19836. 8007dee: f001 f80a bl 8008e06 <USBD_CtlSendStatus>
  19837. 8007df2: e01a b.n 8007e2a <USBD_LL_DataOutStage+0xbc>
  19838. #endif
  19839. }
  19840. }
  19841. else
  19842. {
  19843. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  19844. 8007df4: 68fb ldr r3, [r7, #12]
  19845. 8007df6: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  19846. 8007dfa: b2db uxtb r3, r3
  19847. 8007dfc: 2b03 cmp r3, #3
  19848. 8007dfe: d114 bne.n 8007e2a <USBD_LL_DataOutStage+0xbc>
  19849. {
  19850. if (pdev->pClass->DataOut != NULL)
  19851. 8007e00: 68fb ldr r3, [r7, #12]
  19852. 8007e02: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  19853. 8007e06: 699b ldr r3, [r3, #24]
  19854. 8007e08: 2b00 cmp r3, #0
  19855. 8007e0a: d00e beq.n 8007e2a <USBD_LL_DataOutStage+0xbc>
  19856. {
  19857. ret = (USBD_StatusTypeDef)pdev->pClass->DataOut(pdev, epnum);
  19858. 8007e0c: 68fb ldr r3, [r7, #12]
  19859. 8007e0e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  19860. 8007e12: 699b ldr r3, [r3, #24]
  19861. 8007e14: 7afa ldrb r2, [r7, #11]
  19862. 8007e16: 4611 mov r1, r2
  19863. 8007e18: 68f8 ldr r0, [r7, #12]
  19864. 8007e1a: 4798 blx r3
  19865. 8007e1c: 4603 mov r3, r0
  19866. 8007e1e: 75fb strb r3, [r7, #23]
  19867. if (ret != USBD_OK)
  19868. 8007e20: 7dfb ldrb r3, [r7, #23]
  19869. 8007e22: 2b00 cmp r3, #0
  19870. 8007e24: d001 beq.n 8007e2a <USBD_LL_DataOutStage+0xbc>
  19871. {
  19872. return ret;
  19873. 8007e26: 7dfb ldrb r3, [r7, #23]
  19874. 8007e28: e000 b.n 8007e2c <USBD_LL_DataOutStage+0xbe>
  19875. }
  19876. }
  19877. }
  19878. }
  19879. return USBD_OK;
  19880. 8007e2a: 2300 movs r3, #0
  19881. }
  19882. 8007e2c: 4618 mov r0, r3
  19883. 8007e2e: 3718 adds r7, #24
  19884. 8007e30: 46bd mov sp, r7
  19885. 8007e32: bd80 pop {r7, pc}
  19886. 08007e34 <USBD_LL_DataInStage>:
  19887. * @param epnum: endpoint index
  19888. * @retval status
  19889. */
  19890. USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
  19891. uint8_t epnum, uint8_t *pdata)
  19892. {
  19893. 8007e34: b580 push {r7, lr}
  19894. 8007e36: b086 sub sp, #24
  19895. 8007e38: af00 add r7, sp, #0
  19896. 8007e3a: 60f8 str r0, [r7, #12]
  19897. 8007e3c: 460b mov r3, r1
  19898. 8007e3e: 607a str r2, [r7, #4]
  19899. 8007e40: 72fb strb r3, [r7, #11]
  19900. USBD_EndpointTypeDef *pep;
  19901. USBD_StatusTypeDef ret;
  19902. if (epnum == 0U)
  19903. 8007e42: 7afb ldrb r3, [r7, #11]
  19904. 8007e44: 2b00 cmp r3, #0
  19905. 8007e46: d16b bne.n 8007f20 <USBD_LL_DataInStage+0xec>
  19906. {
  19907. pep = &pdev->ep_in[0];
  19908. 8007e48: 68fb ldr r3, [r7, #12]
  19909. 8007e4a: 3314 adds r3, #20
  19910. 8007e4c: 613b str r3, [r7, #16]
  19911. if (pdev->ep0_state == USBD_EP0_DATA_IN)
  19912. 8007e4e: 68fb ldr r3, [r7, #12]
  19913. 8007e50: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294
  19914. 8007e54: 2b02 cmp r3, #2
  19915. 8007e56: d156 bne.n 8007f06 <USBD_LL_DataInStage+0xd2>
  19916. {
  19917. if (pep->rem_length > pep->maxpacket)
  19918. 8007e58: 693b ldr r3, [r7, #16]
  19919. 8007e5a: 689a ldr r2, [r3, #8]
  19920. 8007e5c: 693b ldr r3, [r7, #16]
  19921. 8007e5e: 68db ldr r3, [r3, #12]
  19922. 8007e60: 429a cmp r2, r3
  19923. 8007e62: d914 bls.n 8007e8e <USBD_LL_DataInStage+0x5a>
  19924. {
  19925. pep->rem_length -= pep->maxpacket;
  19926. 8007e64: 693b ldr r3, [r7, #16]
  19927. 8007e66: 689a ldr r2, [r3, #8]
  19928. 8007e68: 693b ldr r3, [r7, #16]
  19929. 8007e6a: 68db ldr r3, [r3, #12]
  19930. 8007e6c: 1ad2 subs r2, r2, r3
  19931. 8007e6e: 693b ldr r3, [r7, #16]
  19932. 8007e70: 609a str r2, [r3, #8]
  19933. (void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length);
  19934. 8007e72: 693b ldr r3, [r7, #16]
  19935. 8007e74: 689b ldr r3, [r3, #8]
  19936. 8007e76: 461a mov r2, r3
  19937. 8007e78: 6879 ldr r1, [r7, #4]
  19938. 8007e7a: 68f8 ldr r0, [r7, #12]
  19939. 8007e7c: f000 ff84 bl 8008d88 <USBD_CtlContinueSendData>
  19940. /* Prepare endpoint for premature end of transfer */
  19941. (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
  19942. 8007e80: 2300 movs r3, #0
  19943. 8007e82: 2200 movs r2, #0
  19944. 8007e84: 2100 movs r1, #0
  19945. 8007e86: 68f8 ldr r0, [r7, #12]
  19946. 8007e88: f001 fcb0 bl 80097ec <USBD_LL_PrepareReceive>
  19947. 8007e8c: e03b b.n 8007f06 <USBD_LL_DataInStage+0xd2>
  19948. }
  19949. else
  19950. {
  19951. /* last packet is MPS multiple, so send ZLP packet */
  19952. if ((pep->maxpacket == pep->rem_length) &&
  19953. 8007e8e: 693b ldr r3, [r7, #16]
  19954. 8007e90: 68da ldr r2, [r3, #12]
  19955. 8007e92: 693b ldr r3, [r7, #16]
  19956. 8007e94: 689b ldr r3, [r3, #8]
  19957. 8007e96: 429a cmp r2, r3
  19958. 8007e98: d11c bne.n 8007ed4 <USBD_LL_DataInStage+0xa0>
  19959. (pep->total_length >= pep->maxpacket) &&
  19960. 8007e9a: 693b ldr r3, [r7, #16]
  19961. 8007e9c: 685a ldr r2, [r3, #4]
  19962. 8007e9e: 693b ldr r3, [r7, #16]
  19963. 8007ea0: 68db ldr r3, [r3, #12]
  19964. if ((pep->maxpacket == pep->rem_length) &&
  19965. 8007ea2: 429a cmp r2, r3
  19966. 8007ea4: d316 bcc.n 8007ed4 <USBD_LL_DataInStage+0xa0>
  19967. (pep->total_length < pdev->ep0_data_len))
  19968. 8007ea6: 693b ldr r3, [r7, #16]
  19969. 8007ea8: 685a ldr r2, [r3, #4]
  19970. 8007eaa: 68fb ldr r3, [r7, #12]
  19971. 8007eac: f8d3 3298 ldr.w r3, [r3, #664] ; 0x298
  19972. (pep->total_length >= pep->maxpacket) &&
  19973. 8007eb0: 429a cmp r2, r3
  19974. 8007eb2: d20f bcs.n 8007ed4 <USBD_LL_DataInStage+0xa0>
  19975. {
  19976. (void)USBD_CtlContinueSendData(pdev, NULL, 0U);
  19977. 8007eb4: 2200 movs r2, #0
  19978. 8007eb6: 2100 movs r1, #0
  19979. 8007eb8: 68f8 ldr r0, [r7, #12]
  19980. 8007eba: f000 ff65 bl 8008d88 <USBD_CtlContinueSendData>
  19981. pdev->ep0_data_len = 0U;
  19982. 8007ebe: 68fb ldr r3, [r7, #12]
  19983. 8007ec0: 2200 movs r2, #0
  19984. 8007ec2: f8c3 2298 str.w r2, [r3, #664] ; 0x298
  19985. /* Prepare endpoint for premature end of transfer */
  19986. (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
  19987. 8007ec6: 2300 movs r3, #0
  19988. 8007ec8: 2200 movs r2, #0
  19989. 8007eca: 2100 movs r1, #0
  19990. 8007ecc: 68f8 ldr r0, [r7, #12]
  19991. 8007ece: f001 fc8d bl 80097ec <USBD_LL_PrepareReceive>
  19992. 8007ed2: e018 b.n 8007f06 <USBD_LL_DataInStage+0xd2>
  19993. }
  19994. else
  19995. {
  19996. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  19997. 8007ed4: 68fb ldr r3, [r7, #12]
  19998. 8007ed6: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  19999. 8007eda: b2db uxtb r3, r3
  20000. 8007edc: 2b03 cmp r3, #3
  20001. 8007ede: d10b bne.n 8007ef8 <USBD_LL_DataInStage+0xc4>
  20002. {
  20003. if (pdev->pClass->EP0_TxSent != NULL)
  20004. 8007ee0: 68fb ldr r3, [r7, #12]
  20005. 8007ee2: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20006. 8007ee6: 68db ldr r3, [r3, #12]
  20007. 8007ee8: 2b00 cmp r3, #0
  20008. 8007eea: d005 beq.n 8007ef8 <USBD_LL_DataInStage+0xc4>
  20009. {
  20010. pdev->pClass->EP0_TxSent(pdev);
  20011. 8007eec: 68fb ldr r3, [r7, #12]
  20012. 8007eee: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20013. 8007ef2: 68db ldr r3, [r3, #12]
  20014. 8007ef4: 68f8 ldr r0, [r7, #12]
  20015. 8007ef6: 4798 blx r3
  20016. }
  20017. }
  20018. (void)USBD_LL_StallEP(pdev, 0x80U);
  20019. 8007ef8: 2180 movs r1, #128 ; 0x80
  20020. 8007efa: 68f8 ldr r0, [r7, #12]
  20021. 8007efc: f001 fbcc bl 8009698 <USBD_LL_StallEP>
  20022. (void)USBD_CtlReceiveStatus(pdev);
  20023. 8007f00: 68f8 ldr r0, [r7, #12]
  20024. 8007f02: f000 ff93 bl 8008e2c <USBD_CtlReceiveStatus>
  20025. (void)USBD_LL_StallEP(pdev, 0x80U);
  20026. }
  20027. #endif
  20028. }
  20029. if (pdev->dev_test_mode == 1U)
  20030. 8007f06: 68fb ldr r3, [r7, #12]
  20031. 8007f08: f893 32a0 ldrb.w r3, [r3, #672] ; 0x2a0
  20032. 8007f0c: 2b01 cmp r3, #1
  20033. 8007f0e: d122 bne.n 8007f56 <USBD_LL_DataInStage+0x122>
  20034. {
  20035. (void)USBD_RunTestMode(pdev);
  20036. 8007f10: 68f8 ldr r0, [r7, #12]
  20037. 8007f12: f7ff fe98 bl 8007c46 <USBD_RunTestMode>
  20038. pdev->dev_test_mode = 0U;
  20039. 8007f16: 68fb ldr r3, [r7, #12]
  20040. 8007f18: 2200 movs r2, #0
  20041. 8007f1a: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0
  20042. 8007f1e: e01a b.n 8007f56 <USBD_LL_DataInStage+0x122>
  20043. }
  20044. }
  20045. else
  20046. {
  20047. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  20048. 8007f20: 68fb ldr r3, [r7, #12]
  20049. 8007f22: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  20050. 8007f26: b2db uxtb r3, r3
  20051. 8007f28: 2b03 cmp r3, #3
  20052. 8007f2a: d114 bne.n 8007f56 <USBD_LL_DataInStage+0x122>
  20053. {
  20054. if (pdev->pClass->DataIn != NULL)
  20055. 8007f2c: 68fb ldr r3, [r7, #12]
  20056. 8007f2e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20057. 8007f32: 695b ldr r3, [r3, #20]
  20058. 8007f34: 2b00 cmp r3, #0
  20059. 8007f36: d00e beq.n 8007f56 <USBD_LL_DataInStage+0x122>
  20060. {
  20061. ret = (USBD_StatusTypeDef)pdev->pClass->DataIn(pdev, epnum);
  20062. 8007f38: 68fb ldr r3, [r7, #12]
  20063. 8007f3a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20064. 8007f3e: 695b ldr r3, [r3, #20]
  20065. 8007f40: 7afa ldrb r2, [r7, #11]
  20066. 8007f42: 4611 mov r1, r2
  20067. 8007f44: 68f8 ldr r0, [r7, #12]
  20068. 8007f46: 4798 blx r3
  20069. 8007f48: 4603 mov r3, r0
  20070. 8007f4a: 75fb strb r3, [r7, #23]
  20071. if (ret != USBD_OK)
  20072. 8007f4c: 7dfb ldrb r3, [r7, #23]
  20073. 8007f4e: 2b00 cmp r3, #0
  20074. 8007f50: d001 beq.n 8007f56 <USBD_LL_DataInStage+0x122>
  20075. {
  20076. return ret;
  20077. 8007f52: 7dfb ldrb r3, [r7, #23]
  20078. 8007f54: e000 b.n 8007f58 <USBD_LL_DataInStage+0x124>
  20079. }
  20080. }
  20081. }
  20082. }
  20083. return USBD_OK;
  20084. 8007f56: 2300 movs r3, #0
  20085. }
  20086. 8007f58: 4618 mov r0, r3
  20087. 8007f5a: 3718 adds r7, #24
  20088. 8007f5c: 46bd mov sp, r7
  20089. 8007f5e: bd80 pop {r7, pc}
  20090. 08007f60 <USBD_LL_Reset>:
  20091. * @param pdev: device instance
  20092. * @retval status
  20093. */
  20094. USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
  20095. {
  20096. 8007f60: b580 push {r7, lr}
  20097. 8007f62: b082 sub sp, #8
  20098. 8007f64: af00 add r7, sp, #0
  20099. 8007f66: 6078 str r0, [r7, #4]
  20100. /* Upon Reset call user call back */
  20101. pdev->dev_state = USBD_STATE_DEFAULT;
  20102. 8007f68: 687b ldr r3, [r7, #4]
  20103. 8007f6a: 2201 movs r2, #1
  20104. 8007f6c: f883 229c strb.w r2, [r3, #668] ; 0x29c
  20105. pdev->ep0_state = USBD_EP0_IDLE;
  20106. 8007f70: 687b ldr r3, [r7, #4]
  20107. 8007f72: 2200 movs r2, #0
  20108. 8007f74: f8c3 2294 str.w r2, [r3, #660] ; 0x294
  20109. pdev->dev_config = 0U;
  20110. 8007f78: 687b ldr r3, [r7, #4]
  20111. 8007f7a: 2200 movs r2, #0
  20112. 8007f7c: 605a str r2, [r3, #4]
  20113. pdev->dev_remote_wakeup = 0U;
  20114. 8007f7e: 687b ldr r3, [r7, #4]
  20115. 8007f80: 2200 movs r2, #0
  20116. 8007f82: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4
  20117. if (pdev->pClass == NULL)
  20118. 8007f86: 687b ldr r3, [r7, #4]
  20119. 8007f88: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20120. 8007f8c: 2b00 cmp r3, #0
  20121. 8007f8e: d101 bne.n 8007f94 <USBD_LL_Reset+0x34>
  20122. {
  20123. return USBD_FAIL;
  20124. 8007f90: 2303 movs r3, #3
  20125. 8007f92: e02f b.n 8007ff4 <USBD_LL_Reset+0x94>
  20126. }
  20127. if (pdev->pClassData != NULL)
  20128. 8007f94: 687b ldr r3, [r7, #4]
  20129. 8007f96: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  20130. 8007f9a: 2b00 cmp r3, #0
  20131. 8007f9c: d00f beq.n 8007fbe <USBD_LL_Reset+0x5e>
  20132. {
  20133. if (pdev->pClass->DeInit != NULL)
  20134. 8007f9e: 687b ldr r3, [r7, #4]
  20135. 8007fa0: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20136. 8007fa4: 685b ldr r3, [r3, #4]
  20137. 8007fa6: 2b00 cmp r3, #0
  20138. 8007fa8: d009 beq.n 8007fbe <USBD_LL_Reset+0x5e>
  20139. {
  20140. (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
  20141. 8007faa: 687b ldr r3, [r7, #4]
  20142. 8007fac: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20143. 8007fb0: 685b ldr r3, [r3, #4]
  20144. 8007fb2: 687a ldr r2, [r7, #4]
  20145. 8007fb4: 6852 ldr r2, [r2, #4]
  20146. 8007fb6: b2d2 uxtb r2, r2
  20147. 8007fb8: 4611 mov r1, r2
  20148. 8007fba: 6878 ldr r0, [r7, #4]
  20149. 8007fbc: 4798 blx r3
  20150. }
  20151. }
  20152. /* Open EP0 OUT */
  20153. (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
  20154. 8007fbe: 2340 movs r3, #64 ; 0x40
  20155. 8007fc0: 2200 movs r2, #0
  20156. 8007fc2: 2100 movs r1, #0
  20157. 8007fc4: 6878 ldr r0, [r7, #4]
  20158. 8007fc6: f001 fb22 bl 800960e <USBD_LL_OpenEP>
  20159. pdev->ep_out[0x00U & 0xFU].is_used = 1U;
  20160. 8007fca: 687b ldr r3, [r7, #4]
  20161. 8007fcc: 2201 movs r2, #1
  20162. 8007fce: f8a3 2164 strh.w r2, [r3, #356] ; 0x164
  20163. pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
  20164. 8007fd2: 687b ldr r3, [r7, #4]
  20165. 8007fd4: 2240 movs r2, #64 ; 0x40
  20166. 8007fd6: f8c3 2160 str.w r2, [r3, #352] ; 0x160
  20167. /* Open EP0 IN */
  20168. (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
  20169. 8007fda: 2340 movs r3, #64 ; 0x40
  20170. 8007fdc: 2200 movs r2, #0
  20171. 8007fde: 2180 movs r1, #128 ; 0x80
  20172. 8007fe0: 6878 ldr r0, [r7, #4]
  20173. 8007fe2: f001 fb14 bl 800960e <USBD_LL_OpenEP>
  20174. pdev->ep_in[0x80U & 0xFU].is_used = 1U;
  20175. 8007fe6: 687b ldr r3, [r7, #4]
  20176. 8007fe8: 2201 movs r2, #1
  20177. 8007fea: 849a strh r2, [r3, #36] ; 0x24
  20178. pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
  20179. 8007fec: 687b ldr r3, [r7, #4]
  20180. 8007fee: 2240 movs r2, #64 ; 0x40
  20181. 8007ff0: 621a str r2, [r3, #32]
  20182. return USBD_OK;
  20183. 8007ff2: 2300 movs r3, #0
  20184. }
  20185. 8007ff4: 4618 mov r0, r3
  20186. 8007ff6: 3708 adds r7, #8
  20187. 8007ff8: 46bd mov sp, r7
  20188. 8007ffa: bd80 pop {r7, pc}
  20189. 08007ffc <USBD_LL_SetSpeed>:
  20190. * @param pdev: device instance
  20191. * @retval status
  20192. */
  20193. USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
  20194. USBD_SpeedTypeDef speed)
  20195. {
  20196. 8007ffc: b480 push {r7}
  20197. 8007ffe: b083 sub sp, #12
  20198. 8008000: af00 add r7, sp, #0
  20199. 8008002: 6078 str r0, [r7, #4]
  20200. 8008004: 460b mov r3, r1
  20201. 8008006: 70fb strb r3, [r7, #3]
  20202. pdev->dev_speed = speed;
  20203. 8008008: 687b ldr r3, [r7, #4]
  20204. 800800a: 78fa ldrb r2, [r7, #3]
  20205. 800800c: 741a strb r2, [r3, #16]
  20206. return USBD_OK;
  20207. 800800e: 2300 movs r3, #0
  20208. }
  20209. 8008010: 4618 mov r0, r3
  20210. 8008012: 370c adds r7, #12
  20211. 8008014: 46bd mov sp, r7
  20212. 8008016: f85d 7b04 ldr.w r7, [sp], #4
  20213. 800801a: 4770 bx lr
  20214. 0800801c <USBD_LL_Suspend>:
  20215. * @param pdev: device instance
  20216. * @retval status
  20217. */
  20218. USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
  20219. {
  20220. 800801c: b480 push {r7}
  20221. 800801e: b083 sub sp, #12
  20222. 8008020: af00 add r7, sp, #0
  20223. 8008022: 6078 str r0, [r7, #4]
  20224. pdev->dev_old_state = pdev->dev_state;
  20225. 8008024: 687b ldr r3, [r7, #4]
  20226. 8008026: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  20227. 800802a: b2da uxtb r2, r3
  20228. 800802c: 687b ldr r3, [r7, #4]
  20229. 800802e: f883 229d strb.w r2, [r3, #669] ; 0x29d
  20230. pdev->dev_state = USBD_STATE_SUSPENDED;
  20231. 8008032: 687b ldr r3, [r7, #4]
  20232. 8008034: 2204 movs r2, #4
  20233. 8008036: f883 229c strb.w r2, [r3, #668] ; 0x29c
  20234. return USBD_OK;
  20235. 800803a: 2300 movs r3, #0
  20236. }
  20237. 800803c: 4618 mov r0, r3
  20238. 800803e: 370c adds r7, #12
  20239. 8008040: 46bd mov sp, r7
  20240. 8008042: f85d 7b04 ldr.w r7, [sp], #4
  20241. 8008046: 4770 bx lr
  20242. 08008048 <USBD_LL_Resume>:
  20243. * @param pdev: device instance
  20244. * @retval status
  20245. */
  20246. USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
  20247. {
  20248. 8008048: b480 push {r7}
  20249. 800804a: b083 sub sp, #12
  20250. 800804c: af00 add r7, sp, #0
  20251. 800804e: 6078 str r0, [r7, #4]
  20252. if (pdev->dev_state == USBD_STATE_SUSPENDED)
  20253. 8008050: 687b ldr r3, [r7, #4]
  20254. 8008052: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  20255. 8008056: b2db uxtb r3, r3
  20256. 8008058: 2b04 cmp r3, #4
  20257. 800805a: d106 bne.n 800806a <USBD_LL_Resume+0x22>
  20258. {
  20259. pdev->dev_state = pdev->dev_old_state;
  20260. 800805c: 687b ldr r3, [r7, #4]
  20261. 800805e: f893 329d ldrb.w r3, [r3, #669] ; 0x29d
  20262. 8008062: b2da uxtb r2, r3
  20263. 8008064: 687b ldr r3, [r7, #4]
  20264. 8008066: f883 229c strb.w r2, [r3, #668] ; 0x29c
  20265. }
  20266. return USBD_OK;
  20267. 800806a: 2300 movs r3, #0
  20268. }
  20269. 800806c: 4618 mov r0, r3
  20270. 800806e: 370c adds r7, #12
  20271. 8008070: 46bd mov sp, r7
  20272. 8008072: f85d 7b04 ldr.w r7, [sp], #4
  20273. 8008076: 4770 bx lr
  20274. 08008078 <USBD_LL_SOF>:
  20275. * @param pdev: device instance
  20276. * @retval status
  20277. */
  20278. USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
  20279. {
  20280. 8008078: b580 push {r7, lr}
  20281. 800807a: b082 sub sp, #8
  20282. 800807c: af00 add r7, sp, #0
  20283. 800807e: 6078 str r0, [r7, #4]
  20284. if (pdev->pClass == NULL)
  20285. 8008080: 687b ldr r3, [r7, #4]
  20286. 8008082: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20287. 8008086: 2b00 cmp r3, #0
  20288. 8008088: d101 bne.n 800808e <USBD_LL_SOF+0x16>
  20289. {
  20290. return USBD_FAIL;
  20291. 800808a: 2303 movs r3, #3
  20292. 800808c: e012 b.n 80080b4 <USBD_LL_SOF+0x3c>
  20293. }
  20294. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  20295. 800808e: 687b ldr r3, [r7, #4]
  20296. 8008090: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  20297. 8008094: b2db uxtb r3, r3
  20298. 8008096: 2b03 cmp r3, #3
  20299. 8008098: d10b bne.n 80080b2 <USBD_LL_SOF+0x3a>
  20300. {
  20301. if (pdev->pClass->SOF != NULL)
  20302. 800809a: 687b ldr r3, [r7, #4]
  20303. 800809c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20304. 80080a0: 69db ldr r3, [r3, #28]
  20305. 80080a2: 2b00 cmp r3, #0
  20306. 80080a4: d005 beq.n 80080b2 <USBD_LL_SOF+0x3a>
  20307. {
  20308. (void)pdev->pClass->SOF(pdev);
  20309. 80080a6: 687b ldr r3, [r7, #4]
  20310. 80080a8: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20311. 80080ac: 69db ldr r3, [r3, #28]
  20312. 80080ae: 6878 ldr r0, [r7, #4]
  20313. 80080b0: 4798 blx r3
  20314. }
  20315. }
  20316. return USBD_OK;
  20317. 80080b2: 2300 movs r3, #0
  20318. }
  20319. 80080b4: 4618 mov r0, r3
  20320. 80080b6: 3708 adds r7, #8
  20321. 80080b8: 46bd mov sp, r7
  20322. 80080ba: bd80 pop {r7, pc}
  20323. 080080bc <USBD_LL_IsoINIncomplete>:
  20324. * @param pdev: device instance
  20325. * @retval status
  20326. */
  20327. USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
  20328. uint8_t epnum)
  20329. {
  20330. 80080bc: b580 push {r7, lr}
  20331. 80080be: b082 sub sp, #8
  20332. 80080c0: af00 add r7, sp, #0
  20333. 80080c2: 6078 str r0, [r7, #4]
  20334. 80080c4: 460b mov r3, r1
  20335. 80080c6: 70fb strb r3, [r7, #3]
  20336. if (pdev->pClass == NULL)
  20337. 80080c8: 687b ldr r3, [r7, #4]
  20338. 80080ca: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20339. 80080ce: 2b00 cmp r3, #0
  20340. 80080d0: d101 bne.n 80080d6 <USBD_LL_IsoINIncomplete+0x1a>
  20341. {
  20342. return USBD_FAIL;
  20343. 80080d2: 2303 movs r3, #3
  20344. 80080d4: e014 b.n 8008100 <USBD_LL_IsoINIncomplete+0x44>
  20345. }
  20346. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  20347. 80080d6: 687b ldr r3, [r7, #4]
  20348. 80080d8: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  20349. 80080dc: b2db uxtb r3, r3
  20350. 80080de: 2b03 cmp r3, #3
  20351. 80080e0: d10d bne.n 80080fe <USBD_LL_IsoINIncomplete+0x42>
  20352. {
  20353. if (pdev->pClass->IsoINIncomplete != NULL)
  20354. 80080e2: 687b ldr r3, [r7, #4]
  20355. 80080e4: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20356. 80080e8: 6a1b ldr r3, [r3, #32]
  20357. 80080ea: 2b00 cmp r3, #0
  20358. 80080ec: d007 beq.n 80080fe <USBD_LL_IsoINIncomplete+0x42>
  20359. {
  20360. (void)pdev->pClass->IsoINIncomplete(pdev, epnum);
  20361. 80080ee: 687b ldr r3, [r7, #4]
  20362. 80080f0: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20363. 80080f4: 6a1b ldr r3, [r3, #32]
  20364. 80080f6: 78fa ldrb r2, [r7, #3]
  20365. 80080f8: 4611 mov r1, r2
  20366. 80080fa: 6878 ldr r0, [r7, #4]
  20367. 80080fc: 4798 blx r3
  20368. }
  20369. }
  20370. return USBD_OK;
  20371. 80080fe: 2300 movs r3, #0
  20372. }
  20373. 8008100: 4618 mov r0, r3
  20374. 8008102: 3708 adds r7, #8
  20375. 8008104: 46bd mov sp, r7
  20376. 8008106: bd80 pop {r7, pc}
  20377. 08008108 <USBD_LL_IsoOUTIncomplete>:
  20378. * @param pdev: device instance
  20379. * @retval status
  20380. */
  20381. USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
  20382. uint8_t epnum)
  20383. {
  20384. 8008108: b580 push {r7, lr}
  20385. 800810a: b082 sub sp, #8
  20386. 800810c: af00 add r7, sp, #0
  20387. 800810e: 6078 str r0, [r7, #4]
  20388. 8008110: 460b mov r3, r1
  20389. 8008112: 70fb strb r3, [r7, #3]
  20390. if (pdev->pClass == NULL)
  20391. 8008114: 687b ldr r3, [r7, #4]
  20392. 8008116: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20393. 800811a: 2b00 cmp r3, #0
  20394. 800811c: d101 bne.n 8008122 <USBD_LL_IsoOUTIncomplete+0x1a>
  20395. {
  20396. return USBD_FAIL;
  20397. 800811e: 2303 movs r3, #3
  20398. 8008120: e014 b.n 800814c <USBD_LL_IsoOUTIncomplete+0x44>
  20399. }
  20400. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  20401. 8008122: 687b ldr r3, [r7, #4]
  20402. 8008124: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  20403. 8008128: b2db uxtb r3, r3
  20404. 800812a: 2b03 cmp r3, #3
  20405. 800812c: d10d bne.n 800814a <USBD_LL_IsoOUTIncomplete+0x42>
  20406. {
  20407. if (pdev->pClass->IsoOUTIncomplete != NULL)
  20408. 800812e: 687b ldr r3, [r7, #4]
  20409. 8008130: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20410. 8008134: 6a5b ldr r3, [r3, #36] ; 0x24
  20411. 8008136: 2b00 cmp r3, #0
  20412. 8008138: d007 beq.n 800814a <USBD_LL_IsoOUTIncomplete+0x42>
  20413. {
  20414. (void)pdev->pClass->IsoOUTIncomplete(pdev, epnum);
  20415. 800813a: 687b ldr r3, [r7, #4]
  20416. 800813c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20417. 8008140: 6a5b ldr r3, [r3, #36] ; 0x24
  20418. 8008142: 78fa ldrb r2, [r7, #3]
  20419. 8008144: 4611 mov r1, r2
  20420. 8008146: 6878 ldr r0, [r7, #4]
  20421. 8008148: 4798 blx r3
  20422. }
  20423. }
  20424. return USBD_OK;
  20425. 800814a: 2300 movs r3, #0
  20426. }
  20427. 800814c: 4618 mov r0, r3
  20428. 800814e: 3708 adds r7, #8
  20429. 8008150: 46bd mov sp, r7
  20430. 8008152: bd80 pop {r7, pc}
  20431. 08008154 <USBD_LL_DevConnected>:
  20432. * Handle device connection event
  20433. * @param pdev: device instance
  20434. * @retval status
  20435. */
  20436. USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
  20437. {
  20438. 8008154: b480 push {r7}
  20439. 8008156: b083 sub sp, #12
  20440. 8008158: af00 add r7, sp, #0
  20441. 800815a: 6078 str r0, [r7, #4]
  20442. /* Prevent unused argument compilation warning */
  20443. UNUSED(pdev);
  20444. return USBD_OK;
  20445. 800815c: 2300 movs r3, #0
  20446. }
  20447. 800815e: 4618 mov r0, r3
  20448. 8008160: 370c adds r7, #12
  20449. 8008162: 46bd mov sp, r7
  20450. 8008164: f85d 7b04 ldr.w r7, [sp], #4
  20451. 8008168: 4770 bx lr
  20452. 0800816a <USBD_LL_DevDisconnected>:
  20453. * Handle device disconnection event
  20454. * @param pdev: device instance
  20455. * @retval status
  20456. */
  20457. USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
  20458. {
  20459. 800816a: b580 push {r7, lr}
  20460. 800816c: b082 sub sp, #8
  20461. 800816e: af00 add r7, sp, #0
  20462. 8008170: 6078 str r0, [r7, #4]
  20463. /* Free Class Resources */
  20464. pdev->dev_state = USBD_STATE_DEFAULT;
  20465. 8008172: 687b ldr r3, [r7, #4]
  20466. 8008174: 2201 movs r2, #1
  20467. 8008176: f883 229c strb.w r2, [r3, #668] ; 0x29c
  20468. if (pdev->pClass != NULL)
  20469. 800817a: 687b ldr r3, [r7, #4]
  20470. 800817c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20471. 8008180: 2b00 cmp r3, #0
  20472. 8008182: d009 beq.n 8008198 <USBD_LL_DevDisconnected+0x2e>
  20473. {
  20474. (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
  20475. 8008184: 687b ldr r3, [r7, #4]
  20476. 8008186: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20477. 800818a: 685b ldr r3, [r3, #4]
  20478. 800818c: 687a ldr r2, [r7, #4]
  20479. 800818e: 6852 ldr r2, [r2, #4]
  20480. 8008190: b2d2 uxtb r2, r2
  20481. 8008192: 4611 mov r1, r2
  20482. 8008194: 6878 ldr r0, [r7, #4]
  20483. 8008196: 4798 blx r3
  20484. }
  20485. return USBD_OK;
  20486. 8008198: 2300 movs r3, #0
  20487. }
  20488. 800819a: 4618 mov r0, r3
  20489. 800819c: 3708 adds r7, #8
  20490. 800819e: 46bd mov sp, r7
  20491. 80081a0: bd80 pop {r7, pc}
  20492. 080081a2 <SWAPBYTE>:
  20493. /** @defgroup USBD_DEF_Exported_Macros
  20494. * @{
  20495. */
  20496. __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
  20497. {
  20498. 80081a2: b480 push {r7}
  20499. 80081a4: b087 sub sp, #28
  20500. 80081a6: af00 add r7, sp, #0
  20501. 80081a8: 6078 str r0, [r7, #4]
  20502. uint16_t _SwapVal, _Byte1, _Byte2;
  20503. uint8_t *_pbuff = addr;
  20504. 80081aa: 687b ldr r3, [r7, #4]
  20505. 80081ac: 617b str r3, [r7, #20]
  20506. _Byte1 = *(uint8_t *)_pbuff;
  20507. 80081ae: 697b ldr r3, [r7, #20]
  20508. 80081b0: 781b ldrb r3, [r3, #0]
  20509. 80081b2: 827b strh r3, [r7, #18]
  20510. _pbuff++;
  20511. 80081b4: 697b ldr r3, [r7, #20]
  20512. 80081b6: 3301 adds r3, #1
  20513. 80081b8: 617b str r3, [r7, #20]
  20514. _Byte2 = *(uint8_t *)_pbuff;
  20515. 80081ba: 697b ldr r3, [r7, #20]
  20516. 80081bc: 781b ldrb r3, [r3, #0]
  20517. 80081be: 823b strh r3, [r7, #16]
  20518. _SwapVal = (_Byte2 << 8) | _Byte1;
  20519. 80081c0: 8a3b ldrh r3, [r7, #16]
  20520. 80081c2: 021b lsls r3, r3, #8
  20521. 80081c4: b21a sxth r2, r3
  20522. 80081c6: f9b7 3012 ldrsh.w r3, [r7, #18]
  20523. 80081ca: 4313 orrs r3, r2
  20524. 80081cc: b21b sxth r3, r3
  20525. 80081ce: 81fb strh r3, [r7, #14]
  20526. return _SwapVal;
  20527. 80081d0: 89fb ldrh r3, [r7, #14]
  20528. }
  20529. 80081d2: 4618 mov r0, r3
  20530. 80081d4: 371c adds r7, #28
  20531. 80081d6: 46bd mov sp, r7
  20532. 80081d8: f85d 7b04 ldr.w r7, [sp], #4
  20533. 80081dc: 4770 bx lr
  20534. ...
  20535. 080081e0 <USBD_StdDevReq>:
  20536. * @param pdev: device instance
  20537. * @param req: usb request
  20538. * @retval status
  20539. */
  20540. USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
  20541. {
  20542. 80081e0: b580 push {r7, lr}
  20543. 80081e2: b084 sub sp, #16
  20544. 80081e4: af00 add r7, sp, #0
  20545. 80081e6: 6078 str r0, [r7, #4]
  20546. 80081e8: 6039 str r1, [r7, #0]
  20547. USBD_StatusTypeDef ret = USBD_OK;
  20548. 80081ea: 2300 movs r3, #0
  20549. 80081ec: 73fb strb r3, [r7, #15]
  20550. switch (req->bmRequest & USB_REQ_TYPE_MASK)
  20551. 80081ee: 683b ldr r3, [r7, #0]
  20552. 80081f0: 781b ldrb r3, [r3, #0]
  20553. 80081f2: f003 0360 and.w r3, r3, #96 ; 0x60
  20554. 80081f6: 2b40 cmp r3, #64 ; 0x40
  20555. 80081f8: d005 beq.n 8008206 <USBD_StdDevReq+0x26>
  20556. 80081fa: 2b40 cmp r3, #64 ; 0x40
  20557. 80081fc: d853 bhi.n 80082a6 <USBD_StdDevReq+0xc6>
  20558. 80081fe: 2b00 cmp r3, #0
  20559. 8008200: d00b beq.n 800821a <USBD_StdDevReq+0x3a>
  20560. 8008202: 2b20 cmp r3, #32
  20561. 8008204: d14f bne.n 80082a6 <USBD_StdDevReq+0xc6>
  20562. {
  20563. case USB_REQ_TYPE_CLASS:
  20564. case USB_REQ_TYPE_VENDOR:
  20565. ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
  20566. 8008206: 687b ldr r3, [r7, #4]
  20567. 8008208: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20568. 800820c: 689b ldr r3, [r3, #8]
  20569. 800820e: 6839 ldr r1, [r7, #0]
  20570. 8008210: 6878 ldr r0, [r7, #4]
  20571. 8008212: 4798 blx r3
  20572. 8008214: 4603 mov r3, r0
  20573. 8008216: 73fb strb r3, [r7, #15]
  20574. break;
  20575. 8008218: e04a b.n 80082b0 <USBD_StdDevReq+0xd0>
  20576. case USB_REQ_TYPE_STANDARD:
  20577. switch (req->bRequest)
  20578. 800821a: 683b ldr r3, [r7, #0]
  20579. 800821c: 785b ldrb r3, [r3, #1]
  20580. 800821e: 2b09 cmp r3, #9
  20581. 8008220: d83b bhi.n 800829a <USBD_StdDevReq+0xba>
  20582. 8008222: a201 add r2, pc, #4 ; (adr r2, 8008228 <USBD_StdDevReq+0x48>)
  20583. 8008224: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  20584. 8008228: 0800827d .word 0x0800827d
  20585. 800822c: 08008291 .word 0x08008291
  20586. 8008230: 0800829b .word 0x0800829b
  20587. 8008234: 08008287 .word 0x08008287
  20588. 8008238: 0800829b .word 0x0800829b
  20589. 800823c: 0800825b .word 0x0800825b
  20590. 8008240: 08008251 .word 0x08008251
  20591. 8008244: 0800829b .word 0x0800829b
  20592. 8008248: 08008273 .word 0x08008273
  20593. 800824c: 08008265 .word 0x08008265
  20594. {
  20595. case USB_REQ_GET_DESCRIPTOR:
  20596. USBD_GetDescriptor(pdev, req);
  20597. 8008250: 6839 ldr r1, [r7, #0]
  20598. 8008252: 6878 ldr r0, [r7, #4]
  20599. 8008254: f000 f9de bl 8008614 <USBD_GetDescriptor>
  20600. break;
  20601. 8008258: e024 b.n 80082a4 <USBD_StdDevReq+0xc4>
  20602. case USB_REQ_SET_ADDRESS:
  20603. USBD_SetAddress(pdev, req);
  20604. 800825a: 6839 ldr r1, [r7, #0]
  20605. 800825c: 6878 ldr r0, [r7, #4]
  20606. 800825e: f000 fb43 bl 80088e8 <USBD_SetAddress>
  20607. break;
  20608. 8008262: e01f b.n 80082a4 <USBD_StdDevReq+0xc4>
  20609. case USB_REQ_SET_CONFIGURATION:
  20610. ret = USBD_SetConfig(pdev, req);
  20611. 8008264: 6839 ldr r1, [r7, #0]
  20612. 8008266: 6878 ldr r0, [r7, #4]
  20613. 8008268: f000 fb82 bl 8008970 <USBD_SetConfig>
  20614. 800826c: 4603 mov r3, r0
  20615. 800826e: 73fb strb r3, [r7, #15]
  20616. break;
  20617. 8008270: e018 b.n 80082a4 <USBD_StdDevReq+0xc4>
  20618. case USB_REQ_GET_CONFIGURATION:
  20619. USBD_GetConfig(pdev, req);
  20620. 8008272: 6839 ldr r1, [r7, #0]
  20621. 8008274: 6878 ldr r0, [r7, #4]
  20622. 8008276: f000 fc21 bl 8008abc <USBD_GetConfig>
  20623. break;
  20624. 800827a: e013 b.n 80082a4 <USBD_StdDevReq+0xc4>
  20625. case USB_REQ_GET_STATUS:
  20626. USBD_GetStatus(pdev, req);
  20627. 800827c: 6839 ldr r1, [r7, #0]
  20628. 800827e: 6878 ldr r0, [r7, #4]
  20629. 8008280: f000 fc52 bl 8008b28 <USBD_GetStatus>
  20630. break;
  20631. 8008284: e00e b.n 80082a4 <USBD_StdDevReq+0xc4>
  20632. case USB_REQ_SET_FEATURE:
  20633. USBD_SetFeature(pdev, req);
  20634. 8008286: 6839 ldr r1, [r7, #0]
  20635. 8008288: 6878 ldr r0, [r7, #4]
  20636. 800828a: f000 fc81 bl 8008b90 <USBD_SetFeature>
  20637. break;
  20638. 800828e: e009 b.n 80082a4 <USBD_StdDevReq+0xc4>
  20639. case USB_REQ_CLEAR_FEATURE:
  20640. USBD_ClrFeature(pdev, req);
  20641. 8008290: 6839 ldr r1, [r7, #0]
  20642. 8008292: 6878 ldr r0, [r7, #4]
  20643. 8008294: f000 fc90 bl 8008bb8 <USBD_ClrFeature>
  20644. break;
  20645. 8008298: e004 b.n 80082a4 <USBD_StdDevReq+0xc4>
  20646. default:
  20647. USBD_CtlError(pdev, req);
  20648. 800829a: 6839 ldr r1, [r7, #0]
  20649. 800829c: 6878 ldr r0, [r7, #4]
  20650. 800829e: f000 fce7 bl 8008c70 <USBD_CtlError>
  20651. break;
  20652. 80082a2: bf00 nop
  20653. }
  20654. break;
  20655. 80082a4: e004 b.n 80082b0 <USBD_StdDevReq+0xd0>
  20656. default:
  20657. USBD_CtlError(pdev, req);
  20658. 80082a6: 6839 ldr r1, [r7, #0]
  20659. 80082a8: 6878 ldr r0, [r7, #4]
  20660. 80082aa: f000 fce1 bl 8008c70 <USBD_CtlError>
  20661. break;
  20662. 80082ae: bf00 nop
  20663. }
  20664. return ret;
  20665. 80082b0: 7bfb ldrb r3, [r7, #15]
  20666. }
  20667. 80082b2: 4618 mov r0, r3
  20668. 80082b4: 3710 adds r7, #16
  20669. 80082b6: 46bd mov sp, r7
  20670. 80082b8: bd80 pop {r7, pc}
  20671. 80082ba: bf00 nop
  20672. 080082bc <USBD_StdItfReq>:
  20673. * @param pdev: device instance
  20674. * @param req: usb request
  20675. * @retval status
  20676. */
  20677. USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
  20678. {
  20679. 80082bc: b580 push {r7, lr}
  20680. 80082be: b084 sub sp, #16
  20681. 80082c0: af00 add r7, sp, #0
  20682. 80082c2: 6078 str r0, [r7, #4]
  20683. 80082c4: 6039 str r1, [r7, #0]
  20684. USBD_StatusTypeDef ret = USBD_OK;
  20685. 80082c6: 2300 movs r3, #0
  20686. 80082c8: 73fb strb r3, [r7, #15]
  20687. switch (req->bmRequest & USB_REQ_TYPE_MASK)
  20688. 80082ca: 683b ldr r3, [r7, #0]
  20689. 80082cc: 781b ldrb r3, [r3, #0]
  20690. 80082ce: f003 0360 and.w r3, r3, #96 ; 0x60
  20691. 80082d2: 2b40 cmp r3, #64 ; 0x40
  20692. 80082d4: d005 beq.n 80082e2 <USBD_StdItfReq+0x26>
  20693. 80082d6: 2b40 cmp r3, #64 ; 0x40
  20694. 80082d8: d82f bhi.n 800833a <USBD_StdItfReq+0x7e>
  20695. 80082da: 2b00 cmp r3, #0
  20696. 80082dc: d001 beq.n 80082e2 <USBD_StdItfReq+0x26>
  20697. 80082de: 2b20 cmp r3, #32
  20698. 80082e0: d12b bne.n 800833a <USBD_StdItfReq+0x7e>
  20699. {
  20700. case USB_REQ_TYPE_CLASS:
  20701. case USB_REQ_TYPE_VENDOR:
  20702. case USB_REQ_TYPE_STANDARD:
  20703. switch (pdev->dev_state)
  20704. 80082e2: 687b ldr r3, [r7, #4]
  20705. 80082e4: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  20706. 80082e8: b2db uxtb r3, r3
  20707. 80082ea: 3b01 subs r3, #1
  20708. 80082ec: 2b02 cmp r3, #2
  20709. 80082ee: d81d bhi.n 800832c <USBD_StdItfReq+0x70>
  20710. {
  20711. case USBD_STATE_DEFAULT:
  20712. case USBD_STATE_ADDRESSED:
  20713. case USBD_STATE_CONFIGURED:
  20714. if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
  20715. 80082f0: 683b ldr r3, [r7, #0]
  20716. 80082f2: 889b ldrh r3, [r3, #4]
  20717. 80082f4: b2db uxtb r3, r3
  20718. 80082f6: 2b01 cmp r3, #1
  20719. 80082f8: d813 bhi.n 8008322 <USBD_StdItfReq+0x66>
  20720. {
  20721. ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
  20722. 80082fa: 687b ldr r3, [r7, #4]
  20723. 80082fc: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20724. 8008300: 689b ldr r3, [r3, #8]
  20725. 8008302: 6839 ldr r1, [r7, #0]
  20726. 8008304: 6878 ldr r0, [r7, #4]
  20727. 8008306: 4798 blx r3
  20728. 8008308: 4603 mov r3, r0
  20729. 800830a: 73fb strb r3, [r7, #15]
  20730. if ((req->wLength == 0U) && (ret == USBD_OK))
  20731. 800830c: 683b ldr r3, [r7, #0]
  20732. 800830e: 88db ldrh r3, [r3, #6]
  20733. 8008310: 2b00 cmp r3, #0
  20734. 8008312: d110 bne.n 8008336 <USBD_StdItfReq+0x7a>
  20735. 8008314: 7bfb ldrb r3, [r7, #15]
  20736. 8008316: 2b00 cmp r3, #0
  20737. 8008318: d10d bne.n 8008336 <USBD_StdItfReq+0x7a>
  20738. {
  20739. (void)USBD_CtlSendStatus(pdev);
  20740. 800831a: 6878 ldr r0, [r7, #4]
  20741. 800831c: f000 fd73 bl 8008e06 <USBD_CtlSendStatus>
  20742. }
  20743. else
  20744. {
  20745. USBD_CtlError(pdev, req);
  20746. }
  20747. break;
  20748. 8008320: e009 b.n 8008336 <USBD_StdItfReq+0x7a>
  20749. USBD_CtlError(pdev, req);
  20750. 8008322: 6839 ldr r1, [r7, #0]
  20751. 8008324: 6878 ldr r0, [r7, #4]
  20752. 8008326: f000 fca3 bl 8008c70 <USBD_CtlError>
  20753. break;
  20754. 800832a: e004 b.n 8008336 <USBD_StdItfReq+0x7a>
  20755. default:
  20756. USBD_CtlError(pdev, req);
  20757. 800832c: 6839 ldr r1, [r7, #0]
  20758. 800832e: 6878 ldr r0, [r7, #4]
  20759. 8008330: f000 fc9e bl 8008c70 <USBD_CtlError>
  20760. break;
  20761. 8008334: e000 b.n 8008338 <USBD_StdItfReq+0x7c>
  20762. break;
  20763. 8008336: bf00 nop
  20764. }
  20765. break;
  20766. 8008338: e004 b.n 8008344 <USBD_StdItfReq+0x88>
  20767. default:
  20768. USBD_CtlError(pdev, req);
  20769. 800833a: 6839 ldr r1, [r7, #0]
  20770. 800833c: 6878 ldr r0, [r7, #4]
  20771. 800833e: f000 fc97 bl 8008c70 <USBD_CtlError>
  20772. break;
  20773. 8008342: bf00 nop
  20774. }
  20775. return ret;
  20776. 8008344: 7bfb ldrb r3, [r7, #15]
  20777. }
  20778. 8008346: 4618 mov r0, r3
  20779. 8008348: 3710 adds r7, #16
  20780. 800834a: 46bd mov sp, r7
  20781. 800834c: bd80 pop {r7, pc}
  20782. 0800834e <USBD_StdEPReq>:
  20783. * @param pdev: device instance
  20784. * @param req: usb request
  20785. * @retval status
  20786. */
  20787. USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
  20788. {
  20789. 800834e: b580 push {r7, lr}
  20790. 8008350: b084 sub sp, #16
  20791. 8008352: af00 add r7, sp, #0
  20792. 8008354: 6078 str r0, [r7, #4]
  20793. 8008356: 6039 str r1, [r7, #0]
  20794. USBD_EndpointTypeDef *pep;
  20795. uint8_t ep_addr;
  20796. USBD_StatusTypeDef ret = USBD_OK;
  20797. 8008358: 2300 movs r3, #0
  20798. 800835a: 73fb strb r3, [r7, #15]
  20799. ep_addr = LOBYTE(req->wIndex);
  20800. 800835c: 683b ldr r3, [r7, #0]
  20801. 800835e: 889b ldrh r3, [r3, #4]
  20802. 8008360: 73bb strb r3, [r7, #14]
  20803. switch (req->bmRequest & USB_REQ_TYPE_MASK)
  20804. 8008362: 683b ldr r3, [r7, #0]
  20805. 8008364: 781b ldrb r3, [r3, #0]
  20806. 8008366: f003 0360 and.w r3, r3, #96 ; 0x60
  20807. 800836a: 2b40 cmp r3, #64 ; 0x40
  20808. 800836c: d007 beq.n 800837e <USBD_StdEPReq+0x30>
  20809. 800836e: 2b40 cmp r3, #64 ; 0x40
  20810. 8008370: f200 8145 bhi.w 80085fe <USBD_StdEPReq+0x2b0>
  20811. 8008374: 2b00 cmp r3, #0
  20812. 8008376: d00c beq.n 8008392 <USBD_StdEPReq+0x44>
  20813. 8008378: 2b20 cmp r3, #32
  20814. 800837a: f040 8140 bne.w 80085fe <USBD_StdEPReq+0x2b0>
  20815. {
  20816. case USB_REQ_TYPE_CLASS:
  20817. case USB_REQ_TYPE_VENDOR:
  20818. ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
  20819. 800837e: 687b ldr r3, [r7, #4]
  20820. 8008380: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20821. 8008384: 689b ldr r3, [r3, #8]
  20822. 8008386: 6839 ldr r1, [r7, #0]
  20823. 8008388: 6878 ldr r0, [r7, #4]
  20824. 800838a: 4798 blx r3
  20825. 800838c: 4603 mov r3, r0
  20826. 800838e: 73fb strb r3, [r7, #15]
  20827. break;
  20828. 8008390: e13a b.n 8008608 <USBD_StdEPReq+0x2ba>
  20829. case USB_REQ_TYPE_STANDARD:
  20830. switch (req->bRequest)
  20831. 8008392: 683b ldr r3, [r7, #0]
  20832. 8008394: 785b ldrb r3, [r3, #1]
  20833. 8008396: 2b03 cmp r3, #3
  20834. 8008398: d007 beq.n 80083aa <USBD_StdEPReq+0x5c>
  20835. 800839a: 2b03 cmp r3, #3
  20836. 800839c: f300 8129 bgt.w 80085f2 <USBD_StdEPReq+0x2a4>
  20837. 80083a0: 2b00 cmp r3, #0
  20838. 80083a2: d07f beq.n 80084a4 <USBD_StdEPReq+0x156>
  20839. 80083a4: 2b01 cmp r3, #1
  20840. 80083a6: d03c beq.n 8008422 <USBD_StdEPReq+0xd4>
  20841. 80083a8: e123 b.n 80085f2 <USBD_StdEPReq+0x2a4>
  20842. {
  20843. case USB_REQ_SET_FEATURE:
  20844. switch (pdev->dev_state)
  20845. 80083aa: 687b ldr r3, [r7, #4]
  20846. 80083ac: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  20847. 80083b0: b2db uxtb r3, r3
  20848. 80083b2: 2b02 cmp r3, #2
  20849. 80083b4: d002 beq.n 80083bc <USBD_StdEPReq+0x6e>
  20850. 80083b6: 2b03 cmp r3, #3
  20851. 80083b8: d016 beq.n 80083e8 <USBD_StdEPReq+0x9a>
  20852. 80083ba: e02c b.n 8008416 <USBD_StdEPReq+0xc8>
  20853. {
  20854. case USBD_STATE_ADDRESSED:
  20855. if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
  20856. 80083bc: 7bbb ldrb r3, [r7, #14]
  20857. 80083be: 2b00 cmp r3, #0
  20858. 80083c0: d00d beq.n 80083de <USBD_StdEPReq+0x90>
  20859. 80083c2: 7bbb ldrb r3, [r7, #14]
  20860. 80083c4: 2b80 cmp r3, #128 ; 0x80
  20861. 80083c6: d00a beq.n 80083de <USBD_StdEPReq+0x90>
  20862. {
  20863. (void)USBD_LL_StallEP(pdev, ep_addr);
  20864. 80083c8: 7bbb ldrb r3, [r7, #14]
  20865. 80083ca: 4619 mov r1, r3
  20866. 80083cc: 6878 ldr r0, [r7, #4]
  20867. 80083ce: f001 f963 bl 8009698 <USBD_LL_StallEP>
  20868. (void)USBD_LL_StallEP(pdev, 0x80U);
  20869. 80083d2: 2180 movs r1, #128 ; 0x80
  20870. 80083d4: 6878 ldr r0, [r7, #4]
  20871. 80083d6: f001 f95f bl 8009698 <USBD_LL_StallEP>
  20872. 80083da: bf00 nop
  20873. }
  20874. else
  20875. {
  20876. USBD_CtlError(pdev, req);
  20877. }
  20878. break;
  20879. 80083dc: e020 b.n 8008420 <USBD_StdEPReq+0xd2>
  20880. USBD_CtlError(pdev, req);
  20881. 80083de: 6839 ldr r1, [r7, #0]
  20882. 80083e0: 6878 ldr r0, [r7, #4]
  20883. 80083e2: f000 fc45 bl 8008c70 <USBD_CtlError>
  20884. break;
  20885. 80083e6: e01b b.n 8008420 <USBD_StdEPReq+0xd2>
  20886. case USBD_STATE_CONFIGURED:
  20887. if (req->wValue == USB_FEATURE_EP_HALT)
  20888. 80083e8: 683b ldr r3, [r7, #0]
  20889. 80083ea: 885b ldrh r3, [r3, #2]
  20890. 80083ec: 2b00 cmp r3, #0
  20891. 80083ee: d10e bne.n 800840e <USBD_StdEPReq+0xc0>
  20892. {
  20893. if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
  20894. 80083f0: 7bbb ldrb r3, [r7, #14]
  20895. 80083f2: 2b00 cmp r3, #0
  20896. 80083f4: d00b beq.n 800840e <USBD_StdEPReq+0xc0>
  20897. 80083f6: 7bbb ldrb r3, [r7, #14]
  20898. 80083f8: 2b80 cmp r3, #128 ; 0x80
  20899. 80083fa: d008 beq.n 800840e <USBD_StdEPReq+0xc0>
  20900. 80083fc: 683b ldr r3, [r7, #0]
  20901. 80083fe: 88db ldrh r3, [r3, #6]
  20902. 8008400: 2b00 cmp r3, #0
  20903. 8008402: d104 bne.n 800840e <USBD_StdEPReq+0xc0>
  20904. {
  20905. (void)USBD_LL_StallEP(pdev, ep_addr);
  20906. 8008404: 7bbb ldrb r3, [r7, #14]
  20907. 8008406: 4619 mov r1, r3
  20908. 8008408: 6878 ldr r0, [r7, #4]
  20909. 800840a: f001 f945 bl 8009698 <USBD_LL_StallEP>
  20910. }
  20911. }
  20912. (void)USBD_CtlSendStatus(pdev);
  20913. 800840e: 6878 ldr r0, [r7, #4]
  20914. 8008410: f000 fcf9 bl 8008e06 <USBD_CtlSendStatus>
  20915. break;
  20916. 8008414: e004 b.n 8008420 <USBD_StdEPReq+0xd2>
  20917. default:
  20918. USBD_CtlError(pdev, req);
  20919. 8008416: 6839 ldr r1, [r7, #0]
  20920. 8008418: 6878 ldr r0, [r7, #4]
  20921. 800841a: f000 fc29 bl 8008c70 <USBD_CtlError>
  20922. break;
  20923. 800841e: bf00 nop
  20924. }
  20925. break;
  20926. 8008420: e0ec b.n 80085fc <USBD_StdEPReq+0x2ae>
  20927. case USB_REQ_CLEAR_FEATURE:
  20928. switch (pdev->dev_state)
  20929. 8008422: 687b ldr r3, [r7, #4]
  20930. 8008424: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  20931. 8008428: b2db uxtb r3, r3
  20932. 800842a: 2b02 cmp r3, #2
  20933. 800842c: d002 beq.n 8008434 <USBD_StdEPReq+0xe6>
  20934. 800842e: 2b03 cmp r3, #3
  20935. 8008430: d016 beq.n 8008460 <USBD_StdEPReq+0x112>
  20936. 8008432: e030 b.n 8008496 <USBD_StdEPReq+0x148>
  20937. {
  20938. case USBD_STATE_ADDRESSED:
  20939. if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
  20940. 8008434: 7bbb ldrb r3, [r7, #14]
  20941. 8008436: 2b00 cmp r3, #0
  20942. 8008438: d00d beq.n 8008456 <USBD_StdEPReq+0x108>
  20943. 800843a: 7bbb ldrb r3, [r7, #14]
  20944. 800843c: 2b80 cmp r3, #128 ; 0x80
  20945. 800843e: d00a beq.n 8008456 <USBD_StdEPReq+0x108>
  20946. {
  20947. (void)USBD_LL_StallEP(pdev, ep_addr);
  20948. 8008440: 7bbb ldrb r3, [r7, #14]
  20949. 8008442: 4619 mov r1, r3
  20950. 8008444: 6878 ldr r0, [r7, #4]
  20951. 8008446: f001 f927 bl 8009698 <USBD_LL_StallEP>
  20952. (void)USBD_LL_StallEP(pdev, 0x80U);
  20953. 800844a: 2180 movs r1, #128 ; 0x80
  20954. 800844c: 6878 ldr r0, [r7, #4]
  20955. 800844e: f001 f923 bl 8009698 <USBD_LL_StallEP>
  20956. 8008452: bf00 nop
  20957. }
  20958. else
  20959. {
  20960. USBD_CtlError(pdev, req);
  20961. }
  20962. break;
  20963. 8008454: e025 b.n 80084a2 <USBD_StdEPReq+0x154>
  20964. USBD_CtlError(pdev, req);
  20965. 8008456: 6839 ldr r1, [r7, #0]
  20966. 8008458: 6878 ldr r0, [r7, #4]
  20967. 800845a: f000 fc09 bl 8008c70 <USBD_CtlError>
  20968. break;
  20969. 800845e: e020 b.n 80084a2 <USBD_StdEPReq+0x154>
  20970. case USBD_STATE_CONFIGURED:
  20971. if (req->wValue == USB_FEATURE_EP_HALT)
  20972. 8008460: 683b ldr r3, [r7, #0]
  20973. 8008462: 885b ldrh r3, [r3, #2]
  20974. 8008464: 2b00 cmp r3, #0
  20975. 8008466: d11b bne.n 80084a0 <USBD_StdEPReq+0x152>
  20976. {
  20977. if ((ep_addr & 0x7FU) != 0x00U)
  20978. 8008468: 7bbb ldrb r3, [r7, #14]
  20979. 800846a: f003 037f and.w r3, r3, #127 ; 0x7f
  20980. 800846e: 2b00 cmp r3, #0
  20981. 8008470: d004 beq.n 800847c <USBD_StdEPReq+0x12e>
  20982. {
  20983. (void)USBD_LL_ClearStallEP(pdev, ep_addr);
  20984. 8008472: 7bbb ldrb r3, [r7, #14]
  20985. 8008474: 4619 mov r1, r3
  20986. 8008476: 6878 ldr r0, [r7, #4]
  20987. 8008478: f001 f92d bl 80096d6 <USBD_LL_ClearStallEP>
  20988. }
  20989. (void)USBD_CtlSendStatus(pdev);
  20990. 800847c: 6878 ldr r0, [r7, #4]
  20991. 800847e: f000 fcc2 bl 8008e06 <USBD_CtlSendStatus>
  20992. ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
  20993. 8008482: 687b ldr r3, [r7, #4]
  20994. 8008484: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  20995. 8008488: 689b ldr r3, [r3, #8]
  20996. 800848a: 6839 ldr r1, [r7, #0]
  20997. 800848c: 6878 ldr r0, [r7, #4]
  20998. 800848e: 4798 blx r3
  20999. 8008490: 4603 mov r3, r0
  21000. 8008492: 73fb strb r3, [r7, #15]
  21001. }
  21002. break;
  21003. 8008494: e004 b.n 80084a0 <USBD_StdEPReq+0x152>
  21004. default:
  21005. USBD_CtlError(pdev, req);
  21006. 8008496: 6839 ldr r1, [r7, #0]
  21007. 8008498: 6878 ldr r0, [r7, #4]
  21008. 800849a: f000 fbe9 bl 8008c70 <USBD_CtlError>
  21009. break;
  21010. 800849e: e000 b.n 80084a2 <USBD_StdEPReq+0x154>
  21011. break;
  21012. 80084a0: bf00 nop
  21013. }
  21014. break;
  21015. 80084a2: e0ab b.n 80085fc <USBD_StdEPReq+0x2ae>
  21016. case USB_REQ_GET_STATUS:
  21017. switch (pdev->dev_state)
  21018. 80084a4: 687b ldr r3, [r7, #4]
  21019. 80084a6: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  21020. 80084aa: b2db uxtb r3, r3
  21021. 80084ac: 2b02 cmp r3, #2
  21022. 80084ae: d002 beq.n 80084b6 <USBD_StdEPReq+0x168>
  21023. 80084b0: 2b03 cmp r3, #3
  21024. 80084b2: d032 beq.n 800851a <USBD_StdEPReq+0x1cc>
  21025. 80084b4: e097 b.n 80085e6 <USBD_StdEPReq+0x298>
  21026. {
  21027. case USBD_STATE_ADDRESSED:
  21028. if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
  21029. 80084b6: 7bbb ldrb r3, [r7, #14]
  21030. 80084b8: 2b00 cmp r3, #0
  21031. 80084ba: d007 beq.n 80084cc <USBD_StdEPReq+0x17e>
  21032. 80084bc: 7bbb ldrb r3, [r7, #14]
  21033. 80084be: 2b80 cmp r3, #128 ; 0x80
  21034. 80084c0: d004 beq.n 80084cc <USBD_StdEPReq+0x17e>
  21035. {
  21036. USBD_CtlError(pdev, req);
  21037. 80084c2: 6839 ldr r1, [r7, #0]
  21038. 80084c4: 6878 ldr r0, [r7, #4]
  21039. 80084c6: f000 fbd3 bl 8008c70 <USBD_CtlError>
  21040. break;
  21041. 80084ca: e091 b.n 80085f0 <USBD_StdEPReq+0x2a2>
  21042. }
  21043. pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
  21044. 80084cc: f997 300e ldrsb.w r3, [r7, #14]
  21045. 80084d0: 2b00 cmp r3, #0
  21046. 80084d2: da0b bge.n 80084ec <USBD_StdEPReq+0x19e>
  21047. 80084d4: 7bbb ldrb r3, [r7, #14]
  21048. 80084d6: f003 027f and.w r2, r3, #127 ; 0x7f
  21049. 80084da: 4613 mov r3, r2
  21050. 80084dc: 009b lsls r3, r3, #2
  21051. 80084de: 4413 add r3, r2
  21052. 80084e0: 009b lsls r3, r3, #2
  21053. 80084e2: 3310 adds r3, #16
  21054. 80084e4: 687a ldr r2, [r7, #4]
  21055. 80084e6: 4413 add r3, r2
  21056. 80084e8: 3304 adds r3, #4
  21057. 80084ea: e00b b.n 8008504 <USBD_StdEPReq+0x1b6>
  21058. &pdev->ep_out[ep_addr & 0x7FU];
  21059. 80084ec: 7bbb ldrb r3, [r7, #14]
  21060. 80084ee: f003 027f and.w r2, r3, #127 ; 0x7f
  21061. pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
  21062. 80084f2: 4613 mov r3, r2
  21063. 80084f4: 009b lsls r3, r3, #2
  21064. 80084f6: 4413 add r3, r2
  21065. 80084f8: 009b lsls r3, r3, #2
  21066. 80084fa: f503 73a8 add.w r3, r3, #336 ; 0x150
  21067. 80084fe: 687a ldr r2, [r7, #4]
  21068. 8008500: 4413 add r3, r2
  21069. 8008502: 3304 adds r3, #4
  21070. 8008504: 60bb str r3, [r7, #8]
  21071. pep->status = 0x0000U;
  21072. 8008506: 68bb ldr r3, [r7, #8]
  21073. 8008508: 2200 movs r2, #0
  21074. 800850a: 601a str r2, [r3, #0]
  21075. (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
  21076. 800850c: 68bb ldr r3, [r7, #8]
  21077. 800850e: 2202 movs r2, #2
  21078. 8008510: 4619 mov r1, r3
  21079. 8008512: 6878 ldr r0, [r7, #4]
  21080. 8008514: f000 fc1d bl 8008d52 <USBD_CtlSendData>
  21081. break;
  21082. 8008518: e06a b.n 80085f0 <USBD_StdEPReq+0x2a2>
  21083. case USBD_STATE_CONFIGURED:
  21084. if ((ep_addr & 0x80U) == 0x80U)
  21085. 800851a: f997 300e ldrsb.w r3, [r7, #14]
  21086. 800851e: 2b00 cmp r3, #0
  21087. 8008520: da11 bge.n 8008546 <USBD_StdEPReq+0x1f8>
  21088. {
  21089. if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
  21090. 8008522: 7bbb ldrb r3, [r7, #14]
  21091. 8008524: f003 020f and.w r2, r3, #15
  21092. 8008528: 6879 ldr r1, [r7, #4]
  21093. 800852a: 4613 mov r3, r2
  21094. 800852c: 009b lsls r3, r3, #2
  21095. 800852e: 4413 add r3, r2
  21096. 8008530: 009b lsls r3, r3, #2
  21097. 8008532: 440b add r3, r1
  21098. 8008534: 3324 adds r3, #36 ; 0x24
  21099. 8008536: 881b ldrh r3, [r3, #0]
  21100. 8008538: 2b00 cmp r3, #0
  21101. 800853a: d117 bne.n 800856c <USBD_StdEPReq+0x21e>
  21102. {
  21103. USBD_CtlError(pdev, req);
  21104. 800853c: 6839 ldr r1, [r7, #0]
  21105. 800853e: 6878 ldr r0, [r7, #4]
  21106. 8008540: f000 fb96 bl 8008c70 <USBD_CtlError>
  21107. break;
  21108. 8008544: e054 b.n 80085f0 <USBD_StdEPReq+0x2a2>
  21109. }
  21110. }
  21111. else
  21112. {
  21113. if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
  21114. 8008546: 7bbb ldrb r3, [r7, #14]
  21115. 8008548: f003 020f and.w r2, r3, #15
  21116. 800854c: 6879 ldr r1, [r7, #4]
  21117. 800854e: 4613 mov r3, r2
  21118. 8008550: 009b lsls r3, r3, #2
  21119. 8008552: 4413 add r3, r2
  21120. 8008554: 009b lsls r3, r3, #2
  21121. 8008556: 440b add r3, r1
  21122. 8008558: f503 73b2 add.w r3, r3, #356 ; 0x164
  21123. 800855c: 881b ldrh r3, [r3, #0]
  21124. 800855e: 2b00 cmp r3, #0
  21125. 8008560: d104 bne.n 800856c <USBD_StdEPReq+0x21e>
  21126. {
  21127. USBD_CtlError(pdev, req);
  21128. 8008562: 6839 ldr r1, [r7, #0]
  21129. 8008564: 6878 ldr r0, [r7, #4]
  21130. 8008566: f000 fb83 bl 8008c70 <USBD_CtlError>
  21131. break;
  21132. 800856a: e041 b.n 80085f0 <USBD_StdEPReq+0x2a2>
  21133. }
  21134. }
  21135. pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
  21136. 800856c: f997 300e ldrsb.w r3, [r7, #14]
  21137. 8008570: 2b00 cmp r3, #0
  21138. 8008572: da0b bge.n 800858c <USBD_StdEPReq+0x23e>
  21139. 8008574: 7bbb ldrb r3, [r7, #14]
  21140. 8008576: f003 027f and.w r2, r3, #127 ; 0x7f
  21141. 800857a: 4613 mov r3, r2
  21142. 800857c: 009b lsls r3, r3, #2
  21143. 800857e: 4413 add r3, r2
  21144. 8008580: 009b lsls r3, r3, #2
  21145. 8008582: 3310 adds r3, #16
  21146. 8008584: 687a ldr r2, [r7, #4]
  21147. 8008586: 4413 add r3, r2
  21148. 8008588: 3304 adds r3, #4
  21149. 800858a: e00b b.n 80085a4 <USBD_StdEPReq+0x256>
  21150. &pdev->ep_out[ep_addr & 0x7FU];
  21151. 800858c: 7bbb ldrb r3, [r7, #14]
  21152. 800858e: f003 027f and.w r2, r3, #127 ; 0x7f
  21153. pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
  21154. 8008592: 4613 mov r3, r2
  21155. 8008594: 009b lsls r3, r3, #2
  21156. 8008596: 4413 add r3, r2
  21157. 8008598: 009b lsls r3, r3, #2
  21158. 800859a: f503 73a8 add.w r3, r3, #336 ; 0x150
  21159. 800859e: 687a ldr r2, [r7, #4]
  21160. 80085a0: 4413 add r3, r2
  21161. 80085a2: 3304 adds r3, #4
  21162. 80085a4: 60bb str r3, [r7, #8]
  21163. if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
  21164. 80085a6: 7bbb ldrb r3, [r7, #14]
  21165. 80085a8: 2b00 cmp r3, #0
  21166. 80085aa: d002 beq.n 80085b2 <USBD_StdEPReq+0x264>
  21167. 80085ac: 7bbb ldrb r3, [r7, #14]
  21168. 80085ae: 2b80 cmp r3, #128 ; 0x80
  21169. 80085b0: d103 bne.n 80085ba <USBD_StdEPReq+0x26c>
  21170. {
  21171. pep->status = 0x0000U;
  21172. 80085b2: 68bb ldr r3, [r7, #8]
  21173. 80085b4: 2200 movs r2, #0
  21174. 80085b6: 601a str r2, [r3, #0]
  21175. 80085b8: e00e b.n 80085d8 <USBD_StdEPReq+0x28a>
  21176. }
  21177. else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
  21178. 80085ba: 7bbb ldrb r3, [r7, #14]
  21179. 80085bc: 4619 mov r1, r3
  21180. 80085be: 6878 ldr r0, [r7, #4]
  21181. 80085c0: f001 f8a8 bl 8009714 <USBD_LL_IsStallEP>
  21182. 80085c4: 4603 mov r3, r0
  21183. 80085c6: 2b00 cmp r3, #0
  21184. 80085c8: d003 beq.n 80085d2 <USBD_StdEPReq+0x284>
  21185. {
  21186. pep->status = 0x0001U;
  21187. 80085ca: 68bb ldr r3, [r7, #8]
  21188. 80085cc: 2201 movs r2, #1
  21189. 80085ce: 601a str r2, [r3, #0]
  21190. 80085d0: e002 b.n 80085d8 <USBD_StdEPReq+0x28a>
  21191. }
  21192. else
  21193. {
  21194. pep->status = 0x0000U;
  21195. 80085d2: 68bb ldr r3, [r7, #8]
  21196. 80085d4: 2200 movs r2, #0
  21197. 80085d6: 601a str r2, [r3, #0]
  21198. }
  21199. (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
  21200. 80085d8: 68bb ldr r3, [r7, #8]
  21201. 80085da: 2202 movs r2, #2
  21202. 80085dc: 4619 mov r1, r3
  21203. 80085de: 6878 ldr r0, [r7, #4]
  21204. 80085e0: f000 fbb7 bl 8008d52 <USBD_CtlSendData>
  21205. break;
  21206. 80085e4: e004 b.n 80085f0 <USBD_StdEPReq+0x2a2>
  21207. default:
  21208. USBD_CtlError(pdev, req);
  21209. 80085e6: 6839 ldr r1, [r7, #0]
  21210. 80085e8: 6878 ldr r0, [r7, #4]
  21211. 80085ea: f000 fb41 bl 8008c70 <USBD_CtlError>
  21212. break;
  21213. 80085ee: bf00 nop
  21214. }
  21215. break;
  21216. 80085f0: e004 b.n 80085fc <USBD_StdEPReq+0x2ae>
  21217. default:
  21218. USBD_CtlError(pdev, req);
  21219. 80085f2: 6839 ldr r1, [r7, #0]
  21220. 80085f4: 6878 ldr r0, [r7, #4]
  21221. 80085f6: f000 fb3b bl 8008c70 <USBD_CtlError>
  21222. break;
  21223. 80085fa: bf00 nop
  21224. }
  21225. break;
  21226. 80085fc: e004 b.n 8008608 <USBD_StdEPReq+0x2ba>
  21227. default:
  21228. USBD_CtlError(pdev, req);
  21229. 80085fe: 6839 ldr r1, [r7, #0]
  21230. 8008600: 6878 ldr r0, [r7, #4]
  21231. 8008602: f000 fb35 bl 8008c70 <USBD_CtlError>
  21232. break;
  21233. 8008606: bf00 nop
  21234. }
  21235. return ret;
  21236. 8008608: 7bfb ldrb r3, [r7, #15]
  21237. }
  21238. 800860a: 4618 mov r0, r3
  21239. 800860c: 3710 adds r7, #16
  21240. 800860e: 46bd mov sp, r7
  21241. 8008610: bd80 pop {r7, pc}
  21242. ...
  21243. 08008614 <USBD_GetDescriptor>:
  21244. * @param pdev: device instance
  21245. * @param req: usb request
  21246. * @retval status
  21247. */
  21248. static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
  21249. {
  21250. 8008614: b580 push {r7, lr}
  21251. 8008616: b084 sub sp, #16
  21252. 8008618: af00 add r7, sp, #0
  21253. 800861a: 6078 str r0, [r7, #4]
  21254. 800861c: 6039 str r1, [r7, #0]
  21255. uint16_t len = 0U;
  21256. 800861e: 2300 movs r3, #0
  21257. 8008620: 813b strh r3, [r7, #8]
  21258. uint8_t *pbuf = NULL;
  21259. 8008622: 2300 movs r3, #0
  21260. 8008624: 60fb str r3, [r7, #12]
  21261. uint8_t err = 0U;
  21262. 8008626: 2300 movs r3, #0
  21263. 8008628: 72fb strb r3, [r7, #11]
  21264. switch (req->wValue >> 8)
  21265. 800862a: 683b ldr r3, [r7, #0]
  21266. 800862c: 885b ldrh r3, [r3, #2]
  21267. 800862e: 0a1b lsrs r3, r3, #8
  21268. 8008630: b29b uxth r3, r3
  21269. 8008632: 3b01 subs r3, #1
  21270. 8008634: 2b06 cmp r3, #6
  21271. 8008636: f200 8128 bhi.w 800888a <USBD_GetDescriptor+0x276>
  21272. 800863a: a201 add r2, pc, #4 ; (adr r2, 8008640 <USBD_GetDescriptor+0x2c>)
  21273. 800863c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  21274. 8008640: 0800865d .word 0x0800865d
  21275. 8008644: 08008675 .word 0x08008675
  21276. 8008648: 080086b5 .word 0x080086b5
  21277. 800864c: 0800888b .word 0x0800888b
  21278. 8008650: 0800888b .word 0x0800888b
  21279. 8008654: 0800882b .word 0x0800882b
  21280. 8008658: 08008857 .word 0x08008857
  21281. err++;
  21282. }
  21283. break;
  21284. #endif
  21285. case USB_DESC_TYPE_DEVICE:
  21286. pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
  21287. 800865c: 687b ldr r3, [r7, #4]
  21288. 800865e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21289. 8008662: 681b ldr r3, [r3, #0]
  21290. 8008664: 687a ldr r2, [r7, #4]
  21291. 8008666: 7c12 ldrb r2, [r2, #16]
  21292. 8008668: f107 0108 add.w r1, r7, #8
  21293. 800866c: 4610 mov r0, r2
  21294. 800866e: 4798 blx r3
  21295. 8008670: 60f8 str r0, [r7, #12]
  21296. break;
  21297. 8008672: e112 b.n 800889a <USBD_GetDescriptor+0x286>
  21298. case USB_DESC_TYPE_CONFIGURATION:
  21299. if (pdev->dev_speed == USBD_SPEED_HIGH)
  21300. 8008674: 687b ldr r3, [r7, #4]
  21301. 8008676: 7c1b ldrb r3, [r3, #16]
  21302. 8008678: 2b00 cmp r3, #0
  21303. 800867a: d10d bne.n 8008698 <USBD_GetDescriptor+0x84>
  21304. {
  21305. pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
  21306. 800867c: 687b ldr r3, [r7, #4]
  21307. 800867e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  21308. 8008682: 6a9b ldr r3, [r3, #40] ; 0x28
  21309. 8008684: f107 0208 add.w r2, r7, #8
  21310. 8008688: 4610 mov r0, r2
  21311. 800868a: 4798 blx r3
  21312. 800868c: 60f8 str r0, [r7, #12]
  21313. pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
  21314. 800868e: 68fb ldr r3, [r7, #12]
  21315. 8008690: 3301 adds r3, #1
  21316. 8008692: 2202 movs r2, #2
  21317. 8008694: 701a strb r2, [r3, #0]
  21318. else
  21319. {
  21320. pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
  21321. pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
  21322. }
  21323. break;
  21324. 8008696: e100 b.n 800889a <USBD_GetDescriptor+0x286>
  21325. pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
  21326. 8008698: 687b ldr r3, [r7, #4]
  21327. 800869a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  21328. 800869e: 6adb ldr r3, [r3, #44] ; 0x2c
  21329. 80086a0: f107 0208 add.w r2, r7, #8
  21330. 80086a4: 4610 mov r0, r2
  21331. 80086a6: 4798 blx r3
  21332. 80086a8: 60f8 str r0, [r7, #12]
  21333. pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
  21334. 80086aa: 68fb ldr r3, [r7, #12]
  21335. 80086ac: 3301 adds r3, #1
  21336. 80086ae: 2202 movs r2, #2
  21337. 80086b0: 701a strb r2, [r3, #0]
  21338. break;
  21339. 80086b2: e0f2 b.n 800889a <USBD_GetDescriptor+0x286>
  21340. case USB_DESC_TYPE_STRING:
  21341. switch ((uint8_t)(req->wValue))
  21342. 80086b4: 683b ldr r3, [r7, #0]
  21343. 80086b6: 885b ldrh r3, [r3, #2]
  21344. 80086b8: b2db uxtb r3, r3
  21345. 80086ba: 2b05 cmp r3, #5
  21346. 80086bc: f200 80ac bhi.w 8008818 <USBD_GetDescriptor+0x204>
  21347. 80086c0: a201 add r2, pc, #4 ; (adr r2, 80086c8 <USBD_GetDescriptor+0xb4>)
  21348. 80086c2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  21349. 80086c6: bf00 nop
  21350. 80086c8: 080086e1 .word 0x080086e1
  21351. 80086cc: 08008715 .word 0x08008715
  21352. 80086d0: 08008749 .word 0x08008749
  21353. 80086d4: 0800877d .word 0x0800877d
  21354. 80086d8: 080087b1 .word 0x080087b1
  21355. 80086dc: 080087e5 .word 0x080087e5
  21356. {
  21357. case USBD_IDX_LANGID_STR:
  21358. if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
  21359. 80086e0: 687b ldr r3, [r7, #4]
  21360. 80086e2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21361. 80086e6: 685b ldr r3, [r3, #4]
  21362. 80086e8: 2b00 cmp r3, #0
  21363. 80086ea: d00b beq.n 8008704 <USBD_GetDescriptor+0xf0>
  21364. {
  21365. pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
  21366. 80086ec: 687b ldr r3, [r7, #4]
  21367. 80086ee: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21368. 80086f2: 685b ldr r3, [r3, #4]
  21369. 80086f4: 687a ldr r2, [r7, #4]
  21370. 80086f6: 7c12 ldrb r2, [r2, #16]
  21371. 80086f8: f107 0108 add.w r1, r7, #8
  21372. 80086fc: 4610 mov r0, r2
  21373. 80086fe: 4798 blx r3
  21374. 8008700: 60f8 str r0, [r7, #12]
  21375. else
  21376. {
  21377. USBD_CtlError(pdev, req);
  21378. err++;
  21379. }
  21380. break;
  21381. 8008702: e091 b.n 8008828 <USBD_GetDescriptor+0x214>
  21382. USBD_CtlError(pdev, req);
  21383. 8008704: 6839 ldr r1, [r7, #0]
  21384. 8008706: 6878 ldr r0, [r7, #4]
  21385. 8008708: f000 fab2 bl 8008c70 <USBD_CtlError>
  21386. err++;
  21387. 800870c: 7afb ldrb r3, [r7, #11]
  21388. 800870e: 3301 adds r3, #1
  21389. 8008710: 72fb strb r3, [r7, #11]
  21390. break;
  21391. 8008712: e089 b.n 8008828 <USBD_GetDescriptor+0x214>
  21392. case USBD_IDX_MFC_STR:
  21393. if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
  21394. 8008714: 687b ldr r3, [r7, #4]
  21395. 8008716: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21396. 800871a: 689b ldr r3, [r3, #8]
  21397. 800871c: 2b00 cmp r3, #0
  21398. 800871e: d00b beq.n 8008738 <USBD_GetDescriptor+0x124>
  21399. {
  21400. pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
  21401. 8008720: 687b ldr r3, [r7, #4]
  21402. 8008722: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21403. 8008726: 689b ldr r3, [r3, #8]
  21404. 8008728: 687a ldr r2, [r7, #4]
  21405. 800872a: 7c12 ldrb r2, [r2, #16]
  21406. 800872c: f107 0108 add.w r1, r7, #8
  21407. 8008730: 4610 mov r0, r2
  21408. 8008732: 4798 blx r3
  21409. 8008734: 60f8 str r0, [r7, #12]
  21410. else
  21411. {
  21412. USBD_CtlError(pdev, req);
  21413. err++;
  21414. }
  21415. break;
  21416. 8008736: e077 b.n 8008828 <USBD_GetDescriptor+0x214>
  21417. USBD_CtlError(pdev, req);
  21418. 8008738: 6839 ldr r1, [r7, #0]
  21419. 800873a: 6878 ldr r0, [r7, #4]
  21420. 800873c: f000 fa98 bl 8008c70 <USBD_CtlError>
  21421. err++;
  21422. 8008740: 7afb ldrb r3, [r7, #11]
  21423. 8008742: 3301 adds r3, #1
  21424. 8008744: 72fb strb r3, [r7, #11]
  21425. break;
  21426. 8008746: e06f b.n 8008828 <USBD_GetDescriptor+0x214>
  21427. case USBD_IDX_PRODUCT_STR:
  21428. if (pdev->pDesc->GetProductStrDescriptor != NULL)
  21429. 8008748: 687b ldr r3, [r7, #4]
  21430. 800874a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21431. 800874e: 68db ldr r3, [r3, #12]
  21432. 8008750: 2b00 cmp r3, #0
  21433. 8008752: d00b beq.n 800876c <USBD_GetDescriptor+0x158>
  21434. {
  21435. pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
  21436. 8008754: 687b ldr r3, [r7, #4]
  21437. 8008756: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21438. 800875a: 68db ldr r3, [r3, #12]
  21439. 800875c: 687a ldr r2, [r7, #4]
  21440. 800875e: 7c12 ldrb r2, [r2, #16]
  21441. 8008760: f107 0108 add.w r1, r7, #8
  21442. 8008764: 4610 mov r0, r2
  21443. 8008766: 4798 blx r3
  21444. 8008768: 60f8 str r0, [r7, #12]
  21445. else
  21446. {
  21447. USBD_CtlError(pdev, req);
  21448. err++;
  21449. }
  21450. break;
  21451. 800876a: e05d b.n 8008828 <USBD_GetDescriptor+0x214>
  21452. USBD_CtlError(pdev, req);
  21453. 800876c: 6839 ldr r1, [r7, #0]
  21454. 800876e: 6878 ldr r0, [r7, #4]
  21455. 8008770: f000 fa7e bl 8008c70 <USBD_CtlError>
  21456. err++;
  21457. 8008774: 7afb ldrb r3, [r7, #11]
  21458. 8008776: 3301 adds r3, #1
  21459. 8008778: 72fb strb r3, [r7, #11]
  21460. break;
  21461. 800877a: e055 b.n 8008828 <USBD_GetDescriptor+0x214>
  21462. case USBD_IDX_SERIAL_STR:
  21463. if (pdev->pDesc->GetSerialStrDescriptor != NULL)
  21464. 800877c: 687b ldr r3, [r7, #4]
  21465. 800877e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21466. 8008782: 691b ldr r3, [r3, #16]
  21467. 8008784: 2b00 cmp r3, #0
  21468. 8008786: d00b beq.n 80087a0 <USBD_GetDescriptor+0x18c>
  21469. {
  21470. pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
  21471. 8008788: 687b ldr r3, [r7, #4]
  21472. 800878a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21473. 800878e: 691b ldr r3, [r3, #16]
  21474. 8008790: 687a ldr r2, [r7, #4]
  21475. 8008792: 7c12 ldrb r2, [r2, #16]
  21476. 8008794: f107 0108 add.w r1, r7, #8
  21477. 8008798: 4610 mov r0, r2
  21478. 800879a: 4798 blx r3
  21479. 800879c: 60f8 str r0, [r7, #12]
  21480. else
  21481. {
  21482. USBD_CtlError(pdev, req);
  21483. err++;
  21484. }
  21485. break;
  21486. 800879e: e043 b.n 8008828 <USBD_GetDescriptor+0x214>
  21487. USBD_CtlError(pdev, req);
  21488. 80087a0: 6839 ldr r1, [r7, #0]
  21489. 80087a2: 6878 ldr r0, [r7, #4]
  21490. 80087a4: f000 fa64 bl 8008c70 <USBD_CtlError>
  21491. err++;
  21492. 80087a8: 7afb ldrb r3, [r7, #11]
  21493. 80087aa: 3301 adds r3, #1
  21494. 80087ac: 72fb strb r3, [r7, #11]
  21495. break;
  21496. 80087ae: e03b b.n 8008828 <USBD_GetDescriptor+0x214>
  21497. case USBD_IDX_CONFIG_STR:
  21498. if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
  21499. 80087b0: 687b ldr r3, [r7, #4]
  21500. 80087b2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21501. 80087b6: 695b ldr r3, [r3, #20]
  21502. 80087b8: 2b00 cmp r3, #0
  21503. 80087ba: d00b beq.n 80087d4 <USBD_GetDescriptor+0x1c0>
  21504. {
  21505. pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
  21506. 80087bc: 687b ldr r3, [r7, #4]
  21507. 80087be: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21508. 80087c2: 695b ldr r3, [r3, #20]
  21509. 80087c4: 687a ldr r2, [r7, #4]
  21510. 80087c6: 7c12 ldrb r2, [r2, #16]
  21511. 80087c8: f107 0108 add.w r1, r7, #8
  21512. 80087cc: 4610 mov r0, r2
  21513. 80087ce: 4798 blx r3
  21514. 80087d0: 60f8 str r0, [r7, #12]
  21515. else
  21516. {
  21517. USBD_CtlError(pdev, req);
  21518. err++;
  21519. }
  21520. break;
  21521. 80087d2: e029 b.n 8008828 <USBD_GetDescriptor+0x214>
  21522. USBD_CtlError(pdev, req);
  21523. 80087d4: 6839 ldr r1, [r7, #0]
  21524. 80087d6: 6878 ldr r0, [r7, #4]
  21525. 80087d8: f000 fa4a bl 8008c70 <USBD_CtlError>
  21526. err++;
  21527. 80087dc: 7afb ldrb r3, [r7, #11]
  21528. 80087de: 3301 adds r3, #1
  21529. 80087e0: 72fb strb r3, [r7, #11]
  21530. break;
  21531. 80087e2: e021 b.n 8008828 <USBD_GetDescriptor+0x214>
  21532. case USBD_IDX_INTERFACE_STR:
  21533. if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
  21534. 80087e4: 687b ldr r3, [r7, #4]
  21535. 80087e6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21536. 80087ea: 699b ldr r3, [r3, #24]
  21537. 80087ec: 2b00 cmp r3, #0
  21538. 80087ee: d00b beq.n 8008808 <USBD_GetDescriptor+0x1f4>
  21539. {
  21540. pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
  21541. 80087f0: 687b ldr r3, [r7, #4]
  21542. 80087f2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
  21543. 80087f6: 699b ldr r3, [r3, #24]
  21544. 80087f8: 687a ldr r2, [r7, #4]
  21545. 80087fa: 7c12 ldrb r2, [r2, #16]
  21546. 80087fc: f107 0108 add.w r1, r7, #8
  21547. 8008800: 4610 mov r0, r2
  21548. 8008802: 4798 blx r3
  21549. 8008804: 60f8 str r0, [r7, #12]
  21550. else
  21551. {
  21552. USBD_CtlError(pdev, req);
  21553. err++;
  21554. }
  21555. break;
  21556. 8008806: e00f b.n 8008828 <USBD_GetDescriptor+0x214>
  21557. USBD_CtlError(pdev, req);
  21558. 8008808: 6839 ldr r1, [r7, #0]
  21559. 800880a: 6878 ldr r0, [r7, #4]
  21560. 800880c: f000 fa30 bl 8008c70 <USBD_CtlError>
  21561. err++;
  21562. 8008810: 7afb ldrb r3, [r7, #11]
  21563. 8008812: 3301 adds r3, #1
  21564. 8008814: 72fb strb r3, [r7, #11]
  21565. break;
  21566. 8008816: e007 b.n 8008828 <USBD_GetDescriptor+0x214>
  21567. err++;
  21568. }
  21569. #endif
  21570. #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
  21571. USBD_CtlError(pdev, req);
  21572. 8008818: 6839 ldr r1, [r7, #0]
  21573. 800881a: 6878 ldr r0, [r7, #4]
  21574. 800881c: f000 fa28 bl 8008c70 <USBD_CtlError>
  21575. err++;
  21576. 8008820: 7afb ldrb r3, [r7, #11]
  21577. 8008822: 3301 adds r3, #1
  21578. 8008824: 72fb strb r3, [r7, #11]
  21579. #endif
  21580. break;
  21581. 8008826: bf00 nop
  21582. }
  21583. break;
  21584. 8008828: e037 b.n 800889a <USBD_GetDescriptor+0x286>
  21585. case USB_DESC_TYPE_DEVICE_QUALIFIER:
  21586. if (pdev->dev_speed == USBD_SPEED_HIGH)
  21587. 800882a: 687b ldr r3, [r7, #4]
  21588. 800882c: 7c1b ldrb r3, [r3, #16]
  21589. 800882e: 2b00 cmp r3, #0
  21590. 8008830: d109 bne.n 8008846 <USBD_GetDescriptor+0x232>
  21591. {
  21592. pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
  21593. 8008832: 687b ldr r3, [r7, #4]
  21594. 8008834: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  21595. 8008838: 6b5b ldr r3, [r3, #52] ; 0x34
  21596. 800883a: f107 0208 add.w r2, r7, #8
  21597. 800883e: 4610 mov r0, r2
  21598. 8008840: 4798 blx r3
  21599. 8008842: 60f8 str r0, [r7, #12]
  21600. else
  21601. {
  21602. USBD_CtlError(pdev, req);
  21603. err++;
  21604. }
  21605. break;
  21606. 8008844: e029 b.n 800889a <USBD_GetDescriptor+0x286>
  21607. USBD_CtlError(pdev, req);
  21608. 8008846: 6839 ldr r1, [r7, #0]
  21609. 8008848: 6878 ldr r0, [r7, #4]
  21610. 800884a: f000 fa11 bl 8008c70 <USBD_CtlError>
  21611. err++;
  21612. 800884e: 7afb ldrb r3, [r7, #11]
  21613. 8008850: 3301 adds r3, #1
  21614. 8008852: 72fb strb r3, [r7, #11]
  21615. break;
  21616. 8008854: e021 b.n 800889a <USBD_GetDescriptor+0x286>
  21617. case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
  21618. if (pdev->dev_speed == USBD_SPEED_HIGH)
  21619. 8008856: 687b ldr r3, [r7, #4]
  21620. 8008858: 7c1b ldrb r3, [r3, #16]
  21621. 800885a: 2b00 cmp r3, #0
  21622. 800885c: d10d bne.n 800887a <USBD_GetDescriptor+0x266>
  21623. {
  21624. pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
  21625. 800885e: 687b ldr r3, [r7, #4]
  21626. 8008860: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
  21627. 8008864: 6b1b ldr r3, [r3, #48] ; 0x30
  21628. 8008866: f107 0208 add.w r2, r7, #8
  21629. 800886a: 4610 mov r0, r2
  21630. 800886c: 4798 blx r3
  21631. 800886e: 60f8 str r0, [r7, #12]
  21632. pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
  21633. 8008870: 68fb ldr r3, [r7, #12]
  21634. 8008872: 3301 adds r3, #1
  21635. 8008874: 2207 movs r2, #7
  21636. 8008876: 701a strb r2, [r3, #0]
  21637. else
  21638. {
  21639. USBD_CtlError(pdev, req);
  21640. err++;
  21641. }
  21642. break;
  21643. 8008878: e00f b.n 800889a <USBD_GetDescriptor+0x286>
  21644. USBD_CtlError(pdev, req);
  21645. 800887a: 6839 ldr r1, [r7, #0]
  21646. 800887c: 6878 ldr r0, [r7, #4]
  21647. 800887e: f000 f9f7 bl 8008c70 <USBD_CtlError>
  21648. err++;
  21649. 8008882: 7afb ldrb r3, [r7, #11]
  21650. 8008884: 3301 adds r3, #1
  21651. 8008886: 72fb strb r3, [r7, #11]
  21652. break;
  21653. 8008888: e007 b.n 800889a <USBD_GetDescriptor+0x286>
  21654. default:
  21655. USBD_CtlError(pdev, req);
  21656. 800888a: 6839 ldr r1, [r7, #0]
  21657. 800888c: 6878 ldr r0, [r7, #4]
  21658. 800888e: f000 f9ef bl 8008c70 <USBD_CtlError>
  21659. err++;
  21660. 8008892: 7afb ldrb r3, [r7, #11]
  21661. 8008894: 3301 adds r3, #1
  21662. 8008896: 72fb strb r3, [r7, #11]
  21663. break;
  21664. 8008898: bf00 nop
  21665. }
  21666. if (err != 0U)
  21667. 800889a: 7afb ldrb r3, [r7, #11]
  21668. 800889c: 2b00 cmp r3, #0
  21669. 800889e: d11e bne.n 80088de <USBD_GetDescriptor+0x2ca>
  21670. {
  21671. return;
  21672. }
  21673. if (req->wLength != 0U)
  21674. 80088a0: 683b ldr r3, [r7, #0]
  21675. 80088a2: 88db ldrh r3, [r3, #6]
  21676. 80088a4: 2b00 cmp r3, #0
  21677. 80088a6: d016 beq.n 80088d6 <USBD_GetDescriptor+0x2c2>
  21678. {
  21679. if (len != 0U)
  21680. 80088a8: 893b ldrh r3, [r7, #8]
  21681. 80088aa: 2b00 cmp r3, #0
  21682. 80088ac: d00e beq.n 80088cc <USBD_GetDescriptor+0x2b8>
  21683. {
  21684. len = MIN(len, req->wLength);
  21685. 80088ae: 683b ldr r3, [r7, #0]
  21686. 80088b0: 88da ldrh r2, [r3, #6]
  21687. 80088b2: 893b ldrh r3, [r7, #8]
  21688. 80088b4: 4293 cmp r3, r2
  21689. 80088b6: bf28 it cs
  21690. 80088b8: 4613 movcs r3, r2
  21691. 80088ba: b29b uxth r3, r3
  21692. 80088bc: 813b strh r3, [r7, #8]
  21693. (void)USBD_CtlSendData(pdev, pbuf, len);
  21694. 80088be: 893b ldrh r3, [r7, #8]
  21695. 80088c0: 461a mov r2, r3
  21696. 80088c2: 68f9 ldr r1, [r7, #12]
  21697. 80088c4: 6878 ldr r0, [r7, #4]
  21698. 80088c6: f000 fa44 bl 8008d52 <USBD_CtlSendData>
  21699. 80088ca: e009 b.n 80088e0 <USBD_GetDescriptor+0x2cc>
  21700. }
  21701. else
  21702. {
  21703. USBD_CtlError(pdev, req);
  21704. 80088cc: 6839 ldr r1, [r7, #0]
  21705. 80088ce: 6878 ldr r0, [r7, #4]
  21706. 80088d0: f000 f9ce bl 8008c70 <USBD_CtlError>
  21707. 80088d4: e004 b.n 80088e0 <USBD_GetDescriptor+0x2cc>
  21708. }
  21709. }
  21710. else
  21711. {
  21712. (void)USBD_CtlSendStatus(pdev);
  21713. 80088d6: 6878 ldr r0, [r7, #4]
  21714. 80088d8: f000 fa95 bl 8008e06 <USBD_CtlSendStatus>
  21715. 80088dc: e000 b.n 80088e0 <USBD_GetDescriptor+0x2cc>
  21716. return;
  21717. 80088de: bf00 nop
  21718. }
  21719. }
  21720. 80088e0: 3710 adds r7, #16
  21721. 80088e2: 46bd mov sp, r7
  21722. 80088e4: bd80 pop {r7, pc}
  21723. 80088e6: bf00 nop
  21724. 080088e8 <USBD_SetAddress>:
  21725. * @param pdev: device instance
  21726. * @param req: usb request
  21727. * @retval status
  21728. */
  21729. static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
  21730. {
  21731. 80088e8: b580 push {r7, lr}
  21732. 80088ea: b084 sub sp, #16
  21733. 80088ec: af00 add r7, sp, #0
  21734. 80088ee: 6078 str r0, [r7, #4]
  21735. 80088f0: 6039 str r1, [r7, #0]
  21736. uint8_t dev_addr;
  21737. if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
  21738. 80088f2: 683b ldr r3, [r7, #0]
  21739. 80088f4: 889b ldrh r3, [r3, #4]
  21740. 80088f6: 2b00 cmp r3, #0
  21741. 80088f8: d131 bne.n 800895e <USBD_SetAddress+0x76>
  21742. 80088fa: 683b ldr r3, [r7, #0]
  21743. 80088fc: 88db ldrh r3, [r3, #6]
  21744. 80088fe: 2b00 cmp r3, #0
  21745. 8008900: d12d bne.n 800895e <USBD_SetAddress+0x76>
  21746. 8008902: 683b ldr r3, [r7, #0]
  21747. 8008904: 885b ldrh r3, [r3, #2]
  21748. 8008906: 2b7f cmp r3, #127 ; 0x7f
  21749. 8008908: d829 bhi.n 800895e <USBD_SetAddress+0x76>
  21750. {
  21751. dev_addr = (uint8_t)(req->wValue) & 0x7FU;
  21752. 800890a: 683b ldr r3, [r7, #0]
  21753. 800890c: 885b ldrh r3, [r3, #2]
  21754. 800890e: b2db uxtb r3, r3
  21755. 8008910: f003 037f and.w r3, r3, #127 ; 0x7f
  21756. 8008914: 73fb strb r3, [r7, #15]
  21757. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  21758. 8008916: 687b ldr r3, [r7, #4]
  21759. 8008918: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  21760. 800891c: b2db uxtb r3, r3
  21761. 800891e: 2b03 cmp r3, #3
  21762. 8008920: d104 bne.n 800892c <USBD_SetAddress+0x44>
  21763. {
  21764. USBD_CtlError(pdev, req);
  21765. 8008922: 6839 ldr r1, [r7, #0]
  21766. 8008924: 6878 ldr r0, [r7, #4]
  21767. 8008926: f000 f9a3 bl 8008c70 <USBD_CtlError>
  21768. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  21769. 800892a: e01d b.n 8008968 <USBD_SetAddress+0x80>
  21770. }
  21771. else
  21772. {
  21773. pdev->dev_address = dev_addr;
  21774. 800892c: 687b ldr r3, [r7, #4]
  21775. 800892e: 7bfa ldrb r2, [r7, #15]
  21776. 8008930: f883 229e strb.w r2, [r3, #670] ; 0x29e
  21777. (void)USBD_LL_SetUSBAddress(pdev, dev_addr);
  21778. 8008934: 7bfb ldrb r3, [r7, #15]
  21779. 8008936: 4619 mov r1, r3
  21780. 8008938: 6878 ldr r0, [r7, #4]
  21781. 800893a: f000 ff17 bl 800976c <USBD_LL_SetUSBAddress>
  21782. (void)USBD_CtlSendStatus(pdev);
  21783. 800893e: 6878 ldr r0, [r7, #4]
  21784. 8008940: f000 fa61 bl 8008e06 <USBD_CtlSendStatus>
  21785. if (dev_addr != 0U)
  21786. 8008944: 7bfb ldrb r3, [r7, #15]
  21787. 8008946: 2b00 cmp r3, #0
  21788. 8008948: d004 beq.n 8008954 <USBD_SetAddress+0x6c>
  21789. {
  21790. pdev->dev_state = USBD_STATE_ADDRESSED;
  21791. 800894a: 687b ldr r3, [r7, #4]
  21792. 800894c: 2202 movs r2, #2
  21793. 800894e: f883 229c strb.w r2, [r3, #668] ; 0x29c
  21794. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  21795. 8008952: e009 b.n 8008968 <USBD_SetAddress+0x80>
  21796. }
  21797. else
  21798. {
  21799. pdev->dev_state = USBD_STATE_DEFAULT;
  21800. 8008954: 687b ldr r3, [r7, #4]
  21801. 8008956: 2201 movs r2, #1
  21802. 8008958: f883 229c strb.w r2, [r3, #668] ; 0x29c
  21803. if (pdev->dev_state == USBD_STATE_CONFIGURED)
  21804. 800895c: e004 b.n 8008968 <USBD_SetAddress+0x80>
  21805. }
  21806. }
  21807. }
  21808. else
  21809. {
  21810. USBD_CtlError(pdev, req);
  21811. 800895e: 6839 ldr r1, [r7, #0]
  21812. 8008960: 6878 ldr r0, [r7, #4]
  21813. 8008962: f000 f985 bl 8008c70 <USBD_CtlError>
  21814. }
  21815. }
  21816. 8008966: bf00 nop
  21817. 8008968: bf00 nop
  21818. 800896a: 3710 adds r7, #16
  21819. 800896c: 46bd mov sp, r7
  21820. 800896e: bd80 pop {r7, pc}
  21821. 08008970 <USBD_SetConfig>:
  21822. * @param pdev: device instance
  21823. * @param req: usb request
  21824. * @retval status
  21825. */
  21826. static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
  21827. {
  21828. 8008970: b580 push {r7, lr}
  21829. 8008972: b084 sub sp, #16
  21830. 8008974: af00 add r7, sp, #0
  21831. 8008976: 6078 str r0, [r7, #4]
  21832. 8008978: 6039 str r1, [r7, #0]
  21833. USBD_StatusTypeDef ret = USBD_OK;
  21834. 800897a: 2300 movs r3, #0
  21835. 800897c: 73fb strb r3, [r7, #15]
  21836. static uint8_t cfgidx;
  21837. cfgidx = (uint8_t)(req->wValue);
  21838. 800897e: 683b ldr r3, [r7, #0]
  21839. 8008980: 885b ldrh r3, [r3, #2]
  21840. 8008982: b2da uxtb r2, r3
  21841. 8008984: 4b4c ldr r3, [pc, #304] ; (8008ab8 <USBD_SetConfig+0x148>)
  21842. 8008986: 701a strb r2, [r3, #0]
  21843. if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
  21844. 8008988: 4b4b ldr r3, [pc, #300] ; (8008ab8 <USBD_SetConfig+0x148>)
  21845. 800898a: 781b ldrb r3, [r3, #0]
  21846. 800898c: 2b01 cmp r3, #1
  21847. 800898e: d905 bls.n 800899c <USBD_SetConfig+0x2c>
  21848. {
  21849. USBD_CtlError(pdev, req);
  21850. 8008990: 6839 ldr r1, [r7, #0]
  21851. 8008992: 6878 ldr r0, [r7, #4]
  21852. 8008994: f000 f96c bl 8008c70 <USBD_CtlError>
  21853. return USBD_FAIL;
  21854. 8008998: 2303 movs r3, #3
  21855. 800899a: e088 b.n 8008aae <USBD_SetConfig+0x13e>
  21856. }
  21857. switch (pdev->dev_state)
  21858. 800899c: 687b ldr r3, [r7, #4]
  21859. 800899e: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  21860. 80089a2: b2db uxtb r3, r3
  21861. 80089a4: 2b02 cmp r3, #2
  21862. 80089a6: d002 beq.n 80089ae <USBD_SetConfig+0x3e>
  21863. 80089a8: 2b03 cmp r3, #3
  21864. 80089aa: d025 beq.n 80089f8 <USBD_SetConfig+0x88>
  21865. 80089ac: e071 b.n 8008a92 <USBD_SetConfig+0x122>
  21866. {
  21867. case USBD_STATE_ADDRESSED:
  21868. if (cfgidx != 0U)
  21869. 80089ae: 4b42 ldr r3, [pc, #264] ; (8008ab8 <USBD_SetConfig+0x148>)
  21870. 80089b0: 781b ldrb r3, [r3, #0]
  21871. 80089b2: 2b00 cmp r3, #0
  21872. 80089b4: d01c beq.n 80089f0 <USBD_SetConfig+0x80>
  21873. {
  21874. pdev->dev_config = cfgidx;
  21875. 80089b6: 4b40 ldr r3, [pc, #256] ; (8008ab8 <USBD_SetConfig+0x148>)
  21876. 80089b8: 781b ldrb r3, [r3, #0]
  21877. 80089ba: 461a mov r2, r3
  21878. 80089bc: 687b ldr r3, [r7, #4]
  21879. 80089be: 605a str r2, [r3, #4]
  21880. ret = USBD_SetClassConfig(pdev, cfgidx);
  21881. 80089c0: 4b3d ldr r3, [pc, #244] ; (8008ab8 <USBD_SetConfig+0x148>)
  21882. 80089c2: 781b ldrb r3, [r3, #0]
  21883. 80089c4: 4619 mov r1, r3
  21884. 80089c6: 6878 ldr r0, [r7, #4]
  21885. 80089c8: f7ff f948 bl 8007c5c <USBD_SetClassConfig>
  21886. 80089cc: 4603 mov r3, r0
  21887. 80089ce: 73fb strb r3, [r7, #15]
  21888. if (ret != USBD_OK)
  21889. 80089d0: 7bfb ldrb r3, [r7, #15]
  21890. 80089d2: 2b00 cmp r3, #0
  21891. 80089d4: d004 beq.n 80089e0 <USBD_SetConfig+0x70>
  21892. {
  21893. USBD_CtlError(pdev, req);
  21894. 80089d6: 6839 ldr r1, [r7, #0]
  21895. 80089d8: 6878 ldr r0, [r7, #4]
  21896. 80089da: f000 f949 bl 8008c70 <USBD_CtlError>
  21897. }
  21898. else
  21899. {
  21900. (void)USBD_CtlSendStatus(pdev);
  21901. }
  21902. break;
  21903. 80089de: e065 b.n 8008aac <USBD_SetConfig+0x13c>
  21904. (void)USBD_CtlSendStatus(pdev);
  21905. 80089e0: 6878 ldr r0, [r7, #4]
  21906. 80089e2: f000 fa10 bl 8008e06 <USBD_CtlSendStatus>
  21907. pdev->dev_state = USBD_STATE_CONFIGURED;
  21908. 80089e6: 687b ldr r3, [r7, #4]
  21909. 80089e8: 2203 movs r2, #3
  21910. 80089ea: f883 229c strb.w r2, [r3, #668] ; 0x29c
  21911. break;
  21912. 80089ee: e05d b.n 8008aac <USBD_SetConfig+0x13c>
  21913. (void)USBD_CtlSendStatus(pdev);
  21914. 80089f0: 6878 ldr r0, [r7, #4]
  21915. 80089f2: f000 fa08 bl 8008e06 <USBD_CtlSendStatus>
  21916. break;
  21917. 80089f6: e059 b.n 8008aac <USBD_SetConfig+0x13c>
  21918. case USBD_STATE_CONFIGURED:
  21919. if (cfgidx == 0U)
  21920. 80089f8: 4b2f ldr r3, [pc, #188] ; (8008ab8 <USBD_SetConfig+0x148>)
  21921. 80089fa: 781b ldrb r3, [r3, #0]
  21922. 80089fc: 2b00 cmp r3, #0
  21923. 80089fe: d112 bne.n 8008a26 <USBD_SetConfig+0xb6>
  21924. {
  21925. pdev->dev_state = USBD_STATE_ADDRESSED;
  21926. 8008a00: 687b ldr r3, [r7, #4]
  21927. 8008a02: 2202 movs r2, #2
  21928. 8008a04: f883 229c strb.w r2, [r3, #668] ; 0x29c
  21929. pdev->dev_config = cfgidx;
  21930. 8008a08: 4b2b ldr r3, [pc, #172] ; (8008ab8 <USBD_SetConfig+0x148>)
  21931. 8008a0a: 781b ldrb r3, [r3, #0]
  21932. 8008a0c: 461a mov r2, r3
  21933. 8008a0e: 687b ldr r3, [r7, #4]
  21934. 8008a10: 605a str r2, [r3, #4]
  21935. (void)USBD_ClrClassConfig(pdev, cfgidx);
  21936. 8008a12: 4b29 ldr r3, [pc, #164] ; (8008ab8 <USBD_SetConfig+0x148>)
  21937. 8008a14: 781b ldrb r3, [r3, #0]
  21938. 8008a16: 4619 mov r1, r3
  21939. 8008a18: 6878 ldr r0, [r7, #4]
  21940. 8008a1a: f7ff f93b bl 8007c94 <USBD_ClrClassConfig>
  21941. (void)USBD_CtlSendStatus(pdev);
  21942. 8008a1e: 6878 ldr r0, [r7, #4]
  21943. 8008a20: f000 f9f1 bl 8008e06 <USBD_CtlSendStatus>
  21944. }
  21945. else
  21946. {
  21947. (void)USBD_CtlSendStatus(pdev);
  21948. }
  21949. break;
  21950. 8008a24: e042 b.n 8008aac <USBD_SetConfig+0x13c>
  21951. else if (cfgidx != pdev->dev_config)
  21952. 8008a26: 4b24 ldr r3, [pc, #144] ; (8008ab8 <USBD_SetConfig+0x148>)
  21953. 8008a28: 781b ldrb r3, [r3, #0]
  21954. 8008a2a: 461a mov r2, r3
  21955. 8008a2c: 687b ldr r3, [r7, #4]
  21956. 8008a2e: 685b ldr r3, [r3, #4]
  21957. 8008a30: 429a cmp r2, r3
  21958. 8008a32: d02a beq.n 8008a8a <USBD_SetConfig+0x11a>
  21959. (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
  21960. 8008a34: 687b ldr r3, [r7, #4]
  21961. 8008a36: 685b ldr r3, [r3, #4]
  21962. 8008a38: b2db uxtb r3, r3
  21963. 8008a3a: 4619 mov r1, r3
  21964. 8008a3c: 6878 ldr r0, [r7, #4]
  21965. 8008a3e: f7ff f929 bl 8007c94 <USBD_ClrClassConfig>
  21966. pdev->dev_config = cfgidx;
  21967. 8008a42: 4b1d ldr r3, [pc, #116] ; (8008ab8 <USBD_SetConfig+0x148>)
  21968. 8008a44: 781b ldrb r3, [r3, #0]
  21969. 8008a46: 461a mov r2, r3
  21970. 8008a48: 687b ldr r3, [r7, #4]
  21971. 8008a4a: 605a str r2, [r3, #4]
  21972. ret = USBD_SetClassConfig(pdev, cfgidx);
  21973. 8008a4c: 4b1a ldr r3, [pc, #104] ; (8008ab8 <USBD_SetConfig+0x148>)
  21974. 8008a4e: 781b ldrb r3, [r3, #0]
  21975. 8008a50: 4619 mov r1, r3
  21976. 8008a52: 6878 ldr r0, [r7, #4]
  21977. 8008a54: f7ff f902 bl 8007c5c <USBD_SetClassConfig>
  21978. 8008a58: 4603 mov r3, r0
  21979. 8008a5a: 73fb strb r3, [r7, #15]
  21980. if (ret != USBD_OK)
  21981. 8008a5c: 7bfb ldrb r3, [r7, #15]
  21982. 8008a5e: 2b00 cmp r3, #0
  21983. 8008a60: d00f beq.n 8008a82 <USBD_SetConfig+0x112>
  21984. USBD_CtlError(pdev, req);
  21985. 8008a62: 6839 ldr r1, [r7, #0]
  21986. 8008a64: 6878 ldr r0, [r7, #4]
  21987. 8008a66: f000 f903 bl 8008c70 <USBD_CtlError>
  21988. (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
  21989. 8008a6a: 687b ldr r3, [r7, #4]
  21990. 8008a6c: 685b ldr r3, [r3, #4]
  21991. 8008a6e: b2db uxtb r3, r3
  21992. 8008a70: 4619 mov r1, r3
  21993. 8008a72: 6878 ldr r0, [r7, #4]
  21994. 8008a74: f7ff f90e bl 8007c94 <USBD_ClrClassConfig>
  21995. pdev->dev_state = USBD_STATE_ADDRESSED;
  21996. 8008a78: 687b ldr r3, [r7, #4]
  21997. 8008a7a: 2202 movs r2, #2
  21998. 8008a7c: f883 229c strb.w r2, [r3, #668] ; 0x29c
  21999. break;
  22000. 8008a80: e014 b.n 8008aac <USBD_SetConfig+0x13c>
  22001. (void)USBD_CtlSendStatus(pdev);
  22002. 8008a82: 6878 ldr r0, [r7, #4]
  22003. 8008a84: f000 f9bf bl 8008e06 <USBD_CtlSendStatus>
  22004. break;
  22005. 8008a88: e010 b.n 8008aac <USBD_SetConfig+0x13c>
  22006. (void)USBD_CtlSendStatus(pdev);
  22007. 8008a8a: 6878 ldr r0, [r7, #4]
  22008. 8008a8c: f000 f9bb bl 8008e06 <USBD_CtlSendStatus>
  22009. break;
  22010. 8008a90: e00c b.n 8008aac <USBD_SetConfig+0x13c>
  22011. default:
  22012. USBD_CtlError(pdev, req);
  22013. 8008a92: 6839 ldr r1, [r7, #0]
  22014. 8008a94: 6878 ldr r0, [r7, #4]
  22015. 8008a96: f000 f8eb bl 8008c70 <USBD_CtlError>
  22016. (void)USBD_ClrClassConfig(pdev, cfgidx);
  22017. 8008a9a: 4b07 ldr r3, [pc, #28] ; (8008ab8 <USBD_SetConfig+0x148>)
  22018. 8008a9c: 781b ldrb r3, [r3, #0]
  22019. 8008a9e: 4619 mov r1, r3
  22020. 8008aa0: 6878 ldr r0, [r7, #4]
  22021. 8008aa2: f7ff f8f7 bl 8007c94 <USBD_ClrClassConfig>
  22022. ret = USBD_FAIL;
  22023. 8008aa6: 2303 movs r3, #3
  22024. 8008aa8: 73fb strb r3, [r7, #15]
  22025. break;
  22026. 8008aaa: bf00 nop
  22027. }
  22028. return ret;
  22029. 8008aac: 7bfb ldrb r3, [r7, #15]
  22030. }
  22031. 8008aae: 4618 mov r0, r3
  22032. 8008ab0: 3710 adds r7, #16
  22033. 8008ab2: 46bd mov sp, r7
  22034. 8008ab4: bd80 pop {r7, pc}
  22035. 8008ab6: bf00 nop
  22036. 8008ab8: 240011b4 .word 0x240011b4
  22037. 08008abc <USBD_GetConfig>:
  22038. * @param pdev: device instance
  22039. * @param req: usb request
  22040. * @retval status
  22041. */
  22042. static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
  22043. {
  22044. 8008abc: b580 push {r7, lr}
  22045. 8008abe: b082 sub sp, #8
  22046. 8008ac0: af00 add r7, sp, #0
  22047. 8008ac2: 6078 str r0, [r7, #4]
  22048. 8008ac4: 6039 str r1, [r7, #0]
  22049. if (req->wLength != 1U)
  22050. 8008ac6: 683b ldr r3, [r7, #0]
  22051. 8008ac8: 88db ldrh r3, [r3, #6]
  22052. 8008aca: 2b01 cmp r3, #1
  22053. 8008acc: d004 beq.n 8008ad8 <USBD_GetConfig+0x1c>
  22054. {
  22055. USBD_CtlError(pdev, req);
  22056. 8008ace: 6839 ldr r1, [r7, #0]
  22057. 8008ad0: 6878 ldr r0, [r7, #4]
  22058. 8008ad2: f000 f8cd bl 8008c70 <USBD_CtlError>
  22059. default:
  22060. USBD_CtlError(pdev, req);
  22061. break;
  22062. }
  22063. }
  22064. }
  22065. 8008ad6: e023 b.n 8008b20 <USBD_GetConfig+0x64>
  22066. switch (pdev->dev_state)
  22067. 8008ad8: 687b ldr r3, [r7, #4]
  22068. 8008ada: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  22069. 8008ade: b2db uxtb r3, r3
  22070. 8008ae0: 2b02 cmp r3, #2
  22071. 8008ae2: dc02 bgt.n 8008aea <USBD_GetConfig+0x2e>
  22072. 8008ae4: 2b00 cmp r3, #0
  22073. 8008ae6: dc03 bgt.n 8008af0 <USBD_GetConfig+0x34>
  22074. 8008ae8: e015 b.n 8008b16 <USBD_GetConfig+0x5a>
  22075. 8008aea: 2b03 cmp r3, #3
  22076. 8008aec: d00b beq.n 8008b06 <USBD_GetConfig+0x4a>
  22077. 8008aee: e012 b.n 8008b16 <USBD_GetConfig+0x5a>
  22078. pdev->dev_default_config = 0U;
  22079. 8008af0: 687b ldr r3, [r7, #4]
  22080. 8008af2: 2200 movs r2, #0
  22081. 8008af4: 609a str r2, [r3, #8]
  22082. (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
  22083. 8008af6: 687b ldr r3, [r7, #4]
  22084. 8008af8: 3308 adds r3, #8
  22085. 8008afa: 2201 movs r2, #1
  22086. 8008afc: 4619 mov r1, r3
  22087. 8008afe: 6878 ldr r0, [r7, #4]
  22088. 8008b00: f000 f927 bl 8008d52 <USBD_CtlSendData>
  22089. break;
  22090. 8008b04: e00c b.n 8008b20 <USBD_GetConfig+0x64>
  22091. (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
  22092. 8008b06: 687b ldr r3, [r7, #4]
  22093. 8008b08: 3304 adds r3, #4
  22094. 8008b0a: 2201 movs r2, #1
  22095. 8008b0c: 4619 mov r1, r3
  22096. 8008b0e: 6878 ldr r0, [r7, #4]
  22097. 8008b10: f000 f91f bl 8008d52 <USBD_CtlSendData>
  22098. break;
  22099. 8008b14: e004 b.n 8008b20 <USBD_GetConfig+0x64>
  22100. USBD_CtlError(pdev, req);
  22101. 8008b16: 6839 ldr r1, [r7, #0]
  22102. 8008b18: 6878 ldr r0, [r7, #4]
  22103. 8008b1a: f000 f8a9 bl 8008c70 <USBD_CtlError>
  22104. break;
  22105. 8008b1e: bf00 nop
  22106. }
  22107. 8008b20: bf00 nop
  22108. 8008b22: 3708 adds r7, #8
  22109. 8008b24: 46bd mov sp, r7
  22110. 8008b26: bd80 pop {r7, pc}
  22111. 08008b28 <USBD_GetStatus>:
  22112. * @param pdev: device instance
  22113. * @param req: usb request
  22114. * @retval status
  22115. */
  22116. static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
  22117. {
  22118. 8008b28: b580 push {r7, lr}
  22119. 8008b2a: b082 sub sp, #8
  22120. 8008b2c: af00 add r7, sp, #0
  22121. 8008b2e: 6078 str r0, [r7, #4]
  22122. 8008b30: 6039 str r1, [r7, #0]
  22123. switch (pdev->dev_state)
  22124. 8008b32: 687b ldr r3, [r7, #4]
  22125. 8008b34: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  22126. 8008b38: b2db uxtb r3, r3
  22127. 8008b3a: 3b01 subs r3, #1
  22128. 8008b3c: 2b02 cmp r3, #2
  22129. 8008b3e: d81e bhi.n 8008b7e <USBD_GetStatus+0x56>
  22130. {
  22131. case USBD_STATE_DEFAULT:
  22132. case USBD_STATE_ADDRESSED:
  22133. case USBD_STATE_CONFIGURED:
  22134. if (req->wLength != 0x2U)
  22135. 8008b40: 683b ldr r3, [r7, #0]
  22136. 8008b42: 88db ldrh r3, [r3, #6]
  22137. 8008b44: 2b02 cmp r3, #2
  22138. 8008b46: d004 beq.n 8008b52 <USBD_GetStatus+0x2a>
  22139. {
  22140. USBD_CtlError(pdev, req);
  22141. 8008b48: 6839 ldr r1, [r7, #0]
  22142. 8008b4a: 6878 ldr r0, [r7, #4]
  22143. 8008b4c: f000 f890 bl 8008c70 <USBD_CtlError>
  22144. break;
  22145. 8008b50: e01a b.n 8008b88 <USBD_GetStatus+0x60>
  22146. }
  22147. #if (USBD_SELF_POWERED == 1U)
  22148. pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
  22149. 8008b52: 687b ldr r3, [r7, #4]
  22150. 8008b54: 2201 movs r2, #1
  22151. 8008b56: 60da str r2, [r3, #12]
  22152. #else
  22153. pdev->dev_config_status = 0U;
  22154. #endif
  22155. if (pdev->dev_remote_wakeup != 0U)
  22156. 8008b58: 687b ldr r3, [r7, #4]
  22157. 8008b5a: f8d3 32a4 ldr.w r3, [r3, #676] ; 0x2a4
  22158. 8008b5e: 2b00 cmp r3, #0
  22159. 8008b60: d005 beq.n 8008b6e <USBD_GetStatus+0x46>
  22160. {
  22161. pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
  22162. 8008b62: 687b ldr r3, [r7, #4]
  22163. 8008b64: 68db ldr r3, [r3, #12]
  22164. 8008b66: f043 0202 orr.w r2, r3, #2
  22165. 8008b6a: 687b ldr r3, [r7, #4]
  22166. 8008b6c: 60da str r2, [r3, #12]
  22167. }
  22168. (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
  22169. 8008b6e: 687b ldr r3, [r7, #4]
  22170. 8008b70: 330c adds r3, #12
  22171. 8008b72: 2202 movs r2, #2
  22172. 8008b74: 4619 mov r1, r3
  22173. 8008b76: 6878 ldr r0, [r7, #4]
  22174. 8008b78: f000 f8eb bl 8008d52 <USBD_CtlSendData>
  22175. break;
  22176. 8008b7c: e004 b.n 8008b88 <USBD_GetStatus+0x60>
  22177. default:
  22178. USBD_CtlError(pdev, req);
  22179. 8008b7e: 6839 ldr r1, [r7, #0]
  22180. 8008b80: 6878 ldr r0, [r7, #4]
  22181. 8008b82: f000 f875 bl 8008c70 <USBD_CtlError>
  22182. break;
  22183. 8008b86: bf00 nop
  22184. }
  22185. }
  22186. 8008b88: bf00 nop
  22187. 8008b8a: 3708 adds r7, #8
  22188. 8008b8c: 46bd mov sp, r7
  22189. 8008b8e: bd80 pop {r7, pc}
  22190. 08008b90 <USBD_SetFeature>:
  22191. * @param pdev: device instance
  22192. * @param req: usb request
  22193. * @retval status
  22194. */
  22195. static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
  22196. {
  22197. 8008b90: b580 push {r7, lr}
  22198. 8008b92: b082 sub sp, #8
  22199. 8008b94: af00 add r7, sp, #0
  22200. 8008b96: 6078 str r0, [r7, #4]
  22201. 8008b98: 6039 str r1, [r7, #0]
  22202. if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
  22203. 8008b9a: 683b ldr r3, [r7, #0]
  22204. 8008b9c: 885b ldrh r3, [r3, #2]
  22205. 8008b9e: 2b01 cmp r3, #1
  22206. 8008ba0: d106 bne.n 8008bb0 <USBD_SetFeature+0x20>
  22207. {
  22208. pdev->dev_remote_wakeup = 1U;
  22209. 8008ba2: 687b ldr r3, [r7, #4]
  22210. 8008ba4: 2201 movs r2, #1
  22211. 8008ba6: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4
  22212. (void)USBD_CtlSendStatus(pdev);
  22213. 8008baa: 6878 ldr r0, [r7, #4]
  22214. 8008bac: f000 f92b bl 8008e06 <USBD_CtlSendStatus>
  22215. }
  22216. }
  22217. 8008bb0: bf00 nop
  22218. 8008bb2: 3708 adds r7, #8
  22219. 8008bb4: 46bd mov sp, r7
  22220. 8008bb6: bd80 pop {r7, pc}
  22221. 08008bb8 <USBD_ClrFeature>:
  22222. * @param pdev: device instance
  22223. * @param req: usb request
  22224. * @retval status
  22225. */
  22226. static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
  22227. {
  22228. 8008bb8: b580 push {r7, lr}
  22229. 8008bba: b082 sub sp, #8
  22230. 8008bbc: af00 add r7, sp, #0
  22231. 8008bbe: 6078 str r0, [r7, #4]
  22232. 8008bc0: 6039 str r1, [r7, #0]
  22233. switch (pdev->dev_state)
  22234. 8008bc2: 687b ldr r3, [r7, #4]
  22235. 8008bc4: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
  22236. 8008bc8: b2db uxtb r3, r3
  22237. 8008bca: 3b01 subs r3, #1
  22238. 8008bcc: 2b02 cmp r3, #2
  22239. 8008bce: d80b bhi.n 8008be8 <USBD_ClrFeature+0x30>
  22240. {
  22241. case USBD_STATE_DEFAULT:
  22242. case USBD_STATE_ADDRESSED:
  22243. case USBD_STATE_CONFIGURED:
  22244. if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
  22245. 8008bd0: 683b ldr r3, [r7, #0]
  22246. 8008bd2: 885b ldrh r3, [r3, #2]
  22247. 8008bd4: 2b01 cmp r3, #1
  22248. 8008bd6: d10c bne.n 8008bf2 <USBD_ClrFeature+0x3a>
  22249. {
  22250. pdev->dev_remote_wakeup = 0U;
  22251. 8008bd8: 687b ldr r3, [r7, #4]
  22252. 8008bda: 2200 movs r2, #0
  22253. 8008bdc: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4
  22254. (void)USBD_CtlSendStatus(pdev);
  22255. 8008be0: 6878 ldr r0, [r7, #4]
  22256. 8008be2: f000 f910 bl 8008e06 <USBD_CtlSendStatus>
  22257. }
  22258. break;
  22259. 8008be6: e004 b.n 8008bf2 <USBD_ClrFeature+0x3a>
  22260. default:
  22261. USBD_CtlError(pdev, req);
  22262. 8008be8: 6839 ldr r1, [r7, #0]
  22263. 8008bea: 6878 ldr r0, [r7, #4]
  22264. 8008bec: f000 f840 bl 8008c70 <USBD_CtlError>
  22265. break;
  22266. 8008bf0: e000 b.n 8008bf4 <USBD_ClrFeature+0x3c>
  22267. break;
  22268. 8008bf2: bf00 nop
  22269. }
  22270. }
  22271. 8008bf4: bf00 nop
  22272. 8008bf6: 3708 adds r7, #8
  22273. 8008bf8: 46bd mov sp, r7
  22274. 8008bfa: bd80 pop {r7, pc}
  22275. 08008bfc <USBD_ParseSetupRequest>:
  22276. * @param pdev: device instance
  22277. * @param req: usb request
  22278. * @retval None
  22279. */
  22280. void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
  22281. {
  22282. 8008bfc: b580 push {r7, lr}
  22283. 8008bfe: b084 sub sp, #16
  22284. 8008c00: af00 add r7, sp, #0
  22285. 8008c02: 6078 str r0, [r7, #4]
  22286. 8008c04: 6039 str r1, [r7, #0]
  22287. uint8_t *pbuff = pdata;
  22288. 8008c06: 683b ldr r3, [r7, #0]
  22289. 8008c08: 60fb str r3, [r7, #12]
  22290. req->bmRequest = *(uint8_t *)(pbuff);
  22291. 8008c0a: 68fb ldr r3, [r7, #12]
  22292. 8008c0c: 781a ldrb r2, [r3, #0]
  22293. 8008c0e: 687b ldr r3, [r7, #4]
  22294. 8008c10: 701a strb r2, [r3, #0]
  22295. pbuff++;
  22296. 8008c12: 68fb ldr r3, [r7, #12]
  22297. 8008c14: 3301 adds r3, #1
  22298. 8008c16: 60fb str r3, [r7, #12]
  22299. req->bRequest = *(uint8_t *)(pbuff);
  22300. 8008c18: 68fb ldr r3, [r7, #12]
  22301. 8008c1a: 781a ldrb r2, [r3, #0]
  22302. 8008c1c: 687b ldr r3, [r7, #4]
  22303. 8008c1e: 705a strb r2, [r3, #1]
  22304. pbuff++;
  22305. 8008c20: 68fb ldr r3, [r7, #12]
  22306. 8008c22: 3301 adds r3, #1
  22307. 8008c24: 60fb str r3, [r7, #12]
  22308. req->wValue = SWAPBYTE(pbuff);
  22309. 8008c26: 68f8 ldr r0, [r7, #12]
  22310. 8008c28: f7ff fabb bl 80081a2 <SWAPBYTE>
  22311. 8008c2c: 4603 mov r3, r0
  22312. 8008c2e: 461a mov r2, r3
  22313. 8008c30: 687b ldr r3, [r7, #4]
  22314. 8008c32: 805a strh r2, [r3, #2]
  22315. pbuff++;
  22316. 8008c34: 68fb ldr r3, [r7, #12]
  22317. 8008c36: 3301 adds r3, #1
  22318. 8008c38: 60fb str r3, [r7, #12]
  22319. pbuff++;
  22320. 8008c3a: 68fb ldr r3, [r7, #12]
  22321. 8008c3c: 3301 adds r3, #1
  22322. 8008c3e: 60fb str r3, [r7, #12]
  22323. req->wIndex = SWAPBYTE(pbuff);
  22324. 8008c40: 68f8 ldr r0, [r7, #12]
  22325. 8008c42: f7ff faae bl 80081a2 <SWAPBYTE>
  22326. 8008c46: 4603 mov r3, r0
  22327. 8008c48: 461a mov r2, r3
  22328. 8008c4a: 687b ldr r3, [r7, #4]
  22329. 8008c4c: 809a strh r2, [r3, #4]
  22330. pbuff++;
  22331. 8008c4e: 68fb ldr r3, [r7, #12]
  22332. 8008c50: 3301 adds r3, #1
  22333. 8008c52: 60fb str r3, [r7, #12]
  22334. pbuff++;
  22335. 8008c54: 68fb ldr r3, [r7, #12]
  22336. 8008c56: 3301 adds r3, #1
  22337. 8008c58: 60fb str r3, [r7, #12]
  22338. req->wLength = SWAPBYTE(pbuff);
  22339. 8008c5a: 68f8 ldr r0, [r7, #12]
  22340. 8008c5c: f7ff faa1 bl 80081a2 <SWAPBYTE>
  22341. 8008c60: 4603 mov r3, r0
  22342. 8008c62: 461a mov r2, r3
  22343. 8008c64: 687b ldr r3, [r7, #4]
  22344. 8008c66: 80da strh r2, [r3, #6]
  22345. }
  22346. 8008c68: bf00 nop
  22347. 8008c6a: 3710 adds r7, #16
  22348. 8008c6c: 46bd mov sp, r7
  22349. 8008c6e: bd80 pop {r7, pc}
  22350. 08008c70 <USBD_CtlError>:
  22351. * @param pdev: device instance
  22352. * @param req: usb request
  22353. * @retval None
  22354. */
  22355. void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
  22356. {
  22357. 8008c70: b580 push {r7, lr}
  22358. 8008c72: b082 sub sp, #8
  22359. 8008c74: af00 add r7, sp, #0
  22360. 8008c76: 6078 str r0, [r7, #4]
  22361. 8008c78: 6039 str r1, [r7, #0]
  22362. UNUSED(req);
  22363. (void)USBD_LL_StallEP(pdev, 0x80U);
  22364. 8008c7a: 2180 movs r1, #128 ; 0x80
  22365. 8008c7c: 6878 ldr r0, [r7, #4]
  22366. 8008c7e: f000 fd0b bl 8009698 <USBD_LL_StallEP>
  22367. (void)USBD_LL_StallEP(pdev, 0U);
  22368. 8008c82: 2100 movs r1, #0
  22369. 8008c84: 6878 ldr r0, [r7, #4]
  22370. 8008c86: f000 fd07 bl 8009698 <USBD_LL_StallEP>
  22371. }
  22372. 8008c8a: bf00 nop
  22373. 8008c8c: 3708 adds r7, #8
  22374. 8008c8e: 46bd mov sp, r7
  22375. 8008c90: bd80 pop {r7, pc}
  22376. 08008c92 <USBD_GetString>:
  22377. * @param unicode : Formatted string buffer (unicode)
  22378. * @param len : descriptor length
  22379. * @retval None
  22380. */
  22381. void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
  22382. {
  22383. 8008c92: b580 push {r7, lr}
  22384. 8008c94: b086 sub sp, #24
  22385. 8008c96: af00 add r7, sp, #0
  22386. 8008c98: 60f8 str r0, [r7, #12]
  22387. 8008c9a: 60b9 str r1, [r7, #8]
  22388. 8008c9c: 607a str r2, [r7, #4]
  22389. uint8_t idx = 0U;
  22390. 8008c9e: 2300 movs r3, #0
  22391. 8008ca0: 75fb strb r3, [r7, #23]
  22392. uint8_t *pdesc;
  22393. if (desc == NULL)
  22394. 8008ca2: 68fb ldr r3, [r7, #12]
  22395. 8008ca4: 2b00 cmp r3, #0
  22396. 8008ca6: d036 beq.n 8008d16 <USBD_GetString+0x84>
  22397. {
  22398. return;
  22399. }
  22400. pdesc = desc;
  22401. 8008ca8: 68fb ldr r3, [r7, #12]
  22402. 8008caa: 613b str r3, [r7, #16]
  22403. *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U;
  22404. 8008cac: 6938 ldr r0, [r7, #16]
  22405. 8008cae: f000 f836 bl 8008d1e <USBD_GetLen>
  22406. 8008cb2: 4603 mov r3, r0
  22407. 8008cb4: 3301 adds r3, #1
  22408. 8008cb6: b29b uxth r3, r3
  22409. 8008cb8: 005b lsls r3, r3, #1
  22410. 8008cba: b29a uxth r2, r3
  22411. 8008cbc: 687b ldr r3, [r7, #4]
  22412. 8008cbe: 801a strh r2, [r3, #0]
  22413. unicode[idx] = *(uint8_t *)len;
  22414. 8008cc0: 7dfb ldrb r3, [r7, #23]
  22415. 8008cc2: 68ba ldr r2, [r7, #8]
  22416. 8008cc4: 4413 add r3, r2
  22417. 8008cc6: 687a ldr r2, [r7, #4]
  22418. 8008cc8: 7812 ldrb r2, [r2, #0]
  22419. 8008cca: 701a strb r2, [r3, #0]
  22420. idx++;
  22421. 8008ccc: 7dfb ldrb r3, [r7, #23]
  22422. 8008cce: 3301 adds r3, #1
  22423. 8008cd0: 75fb strb r3, [r7, #23]
  22424. unicode[idx] = USB_DESC_TYPE_STRING;
  22425. 8008cd2: 7dfb ldrb r3, [r7, #23]
  22426. 8008cd4: 68ba ldr r2, [r7, #8]
  22427. 8008cd6: 4413 add r3, r2
  22428. 8008cd8: 2203 movs r2, #3
  22429. 8008cda: 701a strb r2, [r3, #0]
  22430. idx++;
  22431. 8008cdc: 7dfb ldrb r3, [r7, #23]
  22432. 8008cde: 3301 adds r3, #1
  22433. 8008ce0: 75fb strb r3, [r7, #23]
  22434. while (*pdesc != (uint8_t)'\0')
  22435. 8008ce2: e013 b.n 8008d0c <USBD_GetString+0x7a>
  22436. {
  22437. unicode[idx] = *pdesc;
  22438. 8008ce4: 7dfb ldrb r3, [r7, #23]
  22439. 8008ce6: 68ba ldr r2, [r7, #8]
  22440. 8008ce8: 4413 add r3, r2
  22441. 8008cea: 693a ldr r2, [r7, #16]
  22442. 8008cec: 7812 ldrb r2, [r2, #0]
  22443. 8008cee: 701a strb r2, [r3, #0]
  22444. pdesc++;
  22445. 8008cf0: 693b ldr r3, [r7, #16]
  22446. 8008cf2: 3301 adds r3, #1
  22447. 8008cf4: 613b str r3, [r7, #16]
  22448. idx++;
  22449. 8008cf6: 7dfb ldrb r3, [r7, #23]
  22450. 8008cf8: 3301 adds r3, #1
  22451. 8008cfa: 75fb strb r3, [r7, #23]
  22452. unicode[idx] = 0U;
  22453. 8008cfc: 7dfb ldrb r3, [r7, #23]
  22454. 8008cfe: 68ba ldr r2, [r7, #8]
  22455. 8008d00: 4413 add r3, r2
  22456. 8008d02: 2200 movs r2, #0
  22457. 8008d04: 701a strb r2, [r3, #0]
  22458. idx++;
  22459. 8008d06: 7dfb ldrb r3, [r7, #23]
  22460. 8008d08: 3301 adds r3, #1
  22461. 8008d0a: 75fb strb r3, [r7, #23]
  22462. while (*pdesc != (uint8_t)'\0')
  22463. 8008d0c: 693b ldr r3, [r7, #16]
  22464. 8008d0e: 781b ldrb r3, [r3, #0]
  22465. 8008d10: 2b00 cmp r3, #0
  22466. 8008d12: d1e7 bne.n 8008ce4 <USBD_GetString+0x52>
  22467. 8008d14: e000 b.n 8008d18 <USBD_GetString+0x86>
  22468. return;
  22469. 8008d16: bf00 nop
  22470. }
  22471. }
  22472. 8008d18: 3718 adds r7, #24
  22473. 8008d1a: 46bd mov sp, r7
  22474. 8008d1c: bd80 pop {r7, pc}
  22475. 08008d1e <USBD_GetLen>:
  22476. * return the string length
  22477. * @param buf : pointer to the ascii string buffer
  22478. * @retval string length
  22479. */
  22480. static uint8_t USBD_GetLen(uint8_t *buf)
  22481. {
  22482. 8008d1e: b480 push {r7}
  22483. 8008d20: b085 sub sp, #20
  22484. 8008d22: af00 add r7, sp, #0
  22485. 8008d24: 6078 str r0, [r7, #4]
  22486. uint8_t len = 0U;
  22487. 8008d26: 2300 movs r3, #0
  22488. 8008d28: 73fb strb r3, [r7, #15]
  22489. uint8_t *pbuff = buf;
  22490. 8008d2a: 687b ldr r3, [r7, #4]
  22491. 8008d2c: 60bb str r3, [r7, #8]
  22492. while (*pbuff != (uint8_t)'\0')
  22493. 8008d2e: e005 b.n 8008d3c <USBD_GetLen+0x1e>
  22494. {
  22495. len++;
  22496. 8008d30: 7bfb ldrb r3, [r7, #15]
  22497. 8008d32: 3301 adds r3, #1
  22498. 8008d34: 73fb strb r3, [r7, #15]
  22499. pbuff++;
  22500. 8008d36: 68bb ldr r3, [r7, #8]
  22501. 8008d38: 3301 adds r3, #1
  22502. 8008d3a: 60bb str r3, [r7, #8]
  22503. while (*pbuff != (uint8_t)'\0')
  22504. 8008d3c: 68bb ldr r3, [r7, #8]
  22505. 8008d3e: 781b ldrb r3, [r3, #0]
  22506. 8008d40: 2b00 cmp r3, #0
  22507. 8008d42: d1f5 bne.n 8008d30 <USBD_GetLen+0x12>
  22508. }
  22509. return len;
  22510. 8008d44: 7bfb ldrb r3, [r7, #15]
  22511. }
  22512. 8008d46: 4618 mov r0, r3
  22513. 8008d48: 3714 adds r7, #20
  22514. 8008d4a: 46bd mov sp, r7
  22515. 8008d4c: f85d 7b04 ldr.w r7, [sp], #4
  22516. 8008d50: 4770 bx lr
  22517. 08008d52 <USBD_CtlSendData>:
  22518. * @param len: length of data to be sent
  22519. * @retval status
  22520. */
  22521. USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
  22522. uint8_t *pbuf, uint32_t len)
  22523. {
  22524. 8008d52: b580 push {r7, lr}
  22525. 8008d54: b084 sub sp, #16
  22526. 8008d56: af00 add r7, sp, #0
  22527. 8008d58: 60f8 str r0, [r7, #12]
  22528. 8008d5a: 60b9 str r1, [r7, #8]
  22529. 8008d5c: 607a str r2, [r7, #4]
  22530. /* Set EP0 State */
  22531. pdev->ep0_state = USBD_EP0_DATA_IN;
  22532. 8008d5e: 68fb ldr r3, [r7, #12]
  22533. 8008d60: 2202 movs r2, #2
  22534. 8008d62: f8c3 2294 str.w r2, [r3, #660] ; 0x294
  22535. pdev->ep_in[0].total_length = len;
  22536. 8008d66: 68fb ldr r3, [r7, #12]
  22537. 8008d68: 687a ldr r2, [r7, #4]
  22538. 8008d6a: 619a str r2, [r3, #24]
  22539. #ifdef USBD_AVOID_PACKET_SPLIT_MPS
  22540. pdev->ep_in[0].rem_length = 0U;
  22541. #else
  22542. pdev->ep_in[0].rem_length = len;
  22543. 8008d6c: 68fb ldr r3, [r7, #12]
  22544. 8008d6e: 687a ldr r2, [r7, #4]
  22545. 8008d70: 61da str r2, [r3, #28]
  22546. #endif
  22547. /* Start the transfer */
  22548. (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
  22549. 8008d72: 687b ldr r3, [r7, #4]
  22550. 8008d74: 68ba ldr r2, [r7, #8]
  22551. 8008d76: 2100 movs r1, #0
  22552. 8008d78: 68f8 ldr r0, [r7, #12]
  22553. 8008d7a: f000 fd16 bl 80097aa <USBD_LL_Transmit>
  22554. return USBD_OK;
  22555. 8008d7e: 2300 movs r3, #0
  22556. }
  22557. 8008d80: 4618 mov r0, r3
  22558. 8008d82: 3710 adds r7, #16
  22559. 8008d84: 46bd mov sp, r7
  22560. 8008d86: bd80 pop {r7, pc}
  22561. 08008d88 <USBD_CtlContinueSendData>:
  22562. * @param len: length of data to be sent
  22563. * @retval status
  22564. */
  22565. USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
  22566. uint8_t *pbuf, uint32_t len)
  22567. {
  22568. 8008d88: b580 push {r7, lr}
  22569. 8008d8a: b084 sub sp, #16
  22570. 8008d8c: af00 add r7, sp, #0
  22571. 8008d8e: 60f8 str r0, [r7, #12]
  22572. 8008d90: 60b9 str r1, [r7, #8]
  22573. 8008d92: 607a str r2, [r7, #4]
  22574. /* Start the next transfer */
  22575. (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
  22576. 8008d94: 687b ldr r3, [r7, #4]
  22577. 8008d96: 68ba ldr r2, [r7, #8]
  22578. 8008d98: 2100 movs r1, #0
  22579. 8008d9a: 68f8 ldr r0, [r7, #12]
  22580. 8008d9c: f000 fd05 bl 80097aa <USBD_LL_Transmit>
  22581. return USBD_OK;
  22582. 8008da0: 2300 movs r3, #0
  22583. }
  22584. 8008da2: 4618 mov r0, r3
  22585. 8008da4: 3710 adds r7, #16
  22586. 8008da6: 46bd mov sp, r7
  22587. 8008da8: bd80 pop {r7, pc}
  22588. 08008daa <USBD_CtlPrepareRx>:
  22589. * @param len: length of data to be received
  22590. * @retval status
  22591. */
  22592. USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
  22593. uint8_t *pbuf, uint32_t len)
  22594. {
  22595. 8008daa: b580 push {r7, lr}
  22596. 8008dac: b084 sub sp, #16
  22597. 8008dae: af00 add r7, sp, #0
  22598. 8008db0: 60f8 str r0, [r7, #12]
  22599. 8008db2: 60b9 str r1, [r7, #8]
  22600. 8008db4: 607a str r2, [r7, #4]
  22601. /* Set EP0 State */
  22602. pdev->ep0_state = USBD_EP0_DATA_OUT;
  22603. 8008db6: 68fb ldr r3, [r7, #12]
  22604. 8008db8: 2203 movs r2, #3
  22605. 8008dba: f8c3 2294 str.w r2, [r3, #660] ; 0x294
  22606. pdev->ep_out[0].total_length = len;
  22607. 8008dbe: 68fb ldr r3, [r7, #12]
  22608. 8008dc0: 687a ldr r2, [r7, #4]
  22609. 8008dc2: f8c3 2158 str.w r2, [r3, #344] ; 0x158
  22610. #ifdef USBD_AVOID_PACKET_SPLIT_MPS
  22611. pdev->ep_out[0].rem_length = 0U;
  22612. #else
  22613. pdev->ep_out[0].rem_length = len;
  22614. 8008dc6: 68fb ldr r3, [r7, #12]
  22615. 8008dc8: 687a ldr r2, [r7, #4]
  22616. 8008dca: f8c3 215c str.w r2, [r3, #348] ; 0x15c
  22617. #endif
  22618. /* Start the transfer */
  22619. (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
  22620. 8008dce: 687b ldr r3, [r7, #4]
  22621. 8008dd0: 68ba ldr r2, [r7, #8]
  22622. 8008dd2: 2100 movs r1, #0
  22623. 8008dd4: 68f8 ldr r0, [r7, #12]
  22624. 8008dd6: f000 fd09 bl 80097ec <USBD_LL_PrepareReceive>
  22625. return USBD_OK;
  22626. 8008dda: 2300 movs r3, #0
  22627. }
  22628. 8008ddc: 4618 mov r0, r3
  22629. 8008dde: 3710 adds r7, #16
  22630. 8008de0: 46bd mov sp, r7
  22631. 8008de2: bd80 pop {r7, pc}
  22632. 08008de4 <USBD_CtlContinueRx>:
  22633. * @param len: length of data to be received
  22634. * @retval status
  22635. */
  22636. USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
  22637. uint8_t *pbuf, uint32_t len)
  22638. {
  22639. 8008de4: b580 push {r7, lr}
  22640. 8008de6: b084 sub sp, #16
  22641. 8008de8: af00 add r7, sp, #0
  22642. 8008dea: 60f8 str r0, [r7, #12]
  22643. 8008dec: 60b9 str r1, [r7, #8]
  22644. 8008dee: 607a str r2, [r7, #4]
  22645. (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
  22646. 8008df0: 687b ldr r3, [r7, #4]
  22647. 8008df2: 68ba ldr r2, [r7, #8]
  22648. 8008df4: 2100 movs r1, #0
  22649. 8008df6: 68f8 ldr r0, [r7, #12]
  22650. 8008df8: f000 fcf8 bl 80097ec <USBD_LL_PrepareReceive>
  22651. return USBD_OK;
  22652. 8008dfc: 2300 movs r3, #0
  22653. }
  22654. 8008dfe: 4618 mov r0, r3
  22655. 8008e00: 3710 adds r7, #16
  22656. 8008e02: 46bd mov sp, r7
  22657. 8008e04: bd80 pop {r7, pc}
  22658. 08008e06 <USBD_CtlSendStatus>:
  22659. * send zero lzngth packet on the ctl pipe
  22660. * @param pdev: device instance
  22661. * @retval status
  22662. */
  22663. USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
  22664. {
  22665. 8008e06: b580 push {r7, lr}
  22666. 8008e08: b082 sub sp, #8
  22667. 8008e0a: af00 add r7, sp, #0
  22668. 8008e0c: 6078 str r0, [r7, #4]
  22669. /* Set EP0 State */
  22670. pdev->ep0_state = USBD_EP0_STATUS_IN;
  22671. 8008e0e: 687b ldr r3, [r7, #4]
  22672. 8008e10: 2204 movs r2, #4
  22673. 8008e12: f8c3 2294 str.w r2, [r3, #660] ; 0x294
  22674. /* Start the transfer */
  22675. (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
  22676. 8008e16: 2300 movs r3, #0
  22677. 8008e18: 2200 movs r2, #0
  22678. 8008e1a: 2100 movs r1, #0
  22679. 8008e1c: 6878 ldr r0, [r7, #4]
  22680. 8008e1e: f000 fcc4 bl 80097aa <USBD_LL_Transmit>
  22681. return USBD_OK;
  22682. 8008e22: 2300 movs r3, #0
  22683. }
  22684. 8008e24: 4618 mov r0, r3
  22685. 8008e26: 3708 adds r7, #8
  22686. 8008e28: 46bd mov sp, r7
  22687. 8008e2a: bd80 pop {r7, pc}
  22688. 08008e2c <USBD_CtlReceiveStatus>:
  22689. * receive zero lzngth packet on the ctl pipe
  22690. * @param pdev: device instance
  22691. * @retval status
  22692. */
  22693. USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
  22694. {
  22695. 8008e2c: b580 push {r7, lr}
  22696. 8008e2e: b082 sub sp, #8
  22697. 8008e30: af00 add r7, sp, #0
  22698. 8008e32: 6078 str r0, [r7, #4]
  22699. /* Set EP0 State */
  22700. pdev->ep0_state = USBD_EP0_STATUS_OUT;
  22701. 8008e34: 687b ldr r3, [r7, #4]
  22702. 8008e36: 2205 movs r2, #5
  22703. 8008e38: f8c3 2294 str.w r2, [r3, #660] ; 0x294
  22704. /* Start the transfer */
  22705. (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
  22706. 8008e3c: 2300 movs r3, #0
  22707. 8008e3e: 2200 movs r2, #0
  22708. 8008e40: 2100 movs r1, #0
  22709. 8008e42: 6878 ldr r0, [r7, #4]
  22710. 8008e44: f000 fcd2 bl 80097ec <USBD_LL_PrepareReceive>
  22711. return USBD_OK;
  22712. 8008e48: 2300 movs r3, #0
  22713. }
  22714. 8008e4a: 4618 mov r0, r3
  22715. 8008e4c: 3708 adds r7, #8
  22716. 8008e4e: 46bd mov sp, r7
  22717. 8008e50: bd80 pop {r7, pc}
  22718. ...
  22719. 08008e54 <MX_USB_DEVICE_Init>:
  22720. /**
  22721. * Init USB device Library, add supported class and start the library
  22722. * @retval None
  22723. */
  22724. void MX_USB_DEVICE_Init(void)
  22725. {
  22726. 8008e54: b580 push {r7, lr}
  22727. 8008e56: af00 add r7, sp, #0
  22728. /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
  22729. /* USER CODE END USB_DEVICE_Init_PreTreatment */
  22730. /* Init Device Library, add supported class and start the library. */
  22731. if (USBD_Init(&hUsbDeviceHS, &HS_Desc, DEVICE_HS) != USBD_OK)
  22732. 8008e58: 2201 movs r2, #1
  22733. 8008e5a: 4913 ldr r1, [pc, #76] ; (8008ea8 <MX_USB_DEVICE_Init+0x54>)
  22734. 8008e5c: 4813 ldr r0, [pc, #76] ; (8008eac <MX_USB_DEVICE_Init+0x58>)
  22735. 8008e5e: f7fe fe8f bl 8007b80 <USBD_Init>
  22736. 8008e62: 4603 mov r3, r0
  22737. 8008e64: 2b00 cmp r3, #0
  22738. 8008e66: d001 beq.n 8008e6c <MX_USB_DEVICE_Init+0x18>
  22739. {
  22740. Error_Handler();
  22741. 8008e68: f7f8 f982 bl 8001170 <Error_Handler>
  22742. }
  22743. if (USBD_RegisterClass(&hUsbDeviceHS, &USBD_CDC) != USBD_OK)
  22744. 8008e6c: 4910 ldr r1, [pc, #64] ; (8008eb0 <MX_USB_DEVICE_Init+0x5c>)
  22745. 8008e6e: 480f ldr r0, [pc, #60] ; (8008eac <MX_USB_DEVICE_Init+0x58>)
  22746. 8008e70: f7fe feb6 bl 8007be0 <USBD_RegisterClass>
  22747. 8008e74: 4603 mov r3, r0
  22748. 8008e76: 2b00 cmp r3, #0
  22749. 8008e78: d001 beq.n 8008e7e <MX_USB_DEVICE_Init+0x2a>
  22750. {
  22751. Error_Handler();
  22752. 8008e7a: f7f8 f979 bl 8001170 <Error_Handler>
  22753. }
  22754. if (USBD_CDC_RegisterInterface(&hUsbDeviceHS, &USBD_Interface_fops_HS) != USBD_OK)
  22755. 8008e7e: 490d ldr r1, [pc, #52] ; (8008eb4 <MX_USB_DEVICE_Init+0x60>)
  22756. 8008e80: 480a ldr r0, [pc, #40] ; (8008eac <MX_USB_DEVICE_Init+0x58>)
  22757. 8008e82: f7fe fdd7 bl 8007a34 <USBD_CDC_RegisterInterface>
  22758. 8008e86: 4603 mov r3, r0
  22759. 8008e88: 2b00 cmp r3, #0
  22760. 8008e8a: d001 beq.n 8008e90 <MX_USB_DEVICE_Init+0x3c>
  22761. {
  22762. Error_Handler();
  22763. 8008e8c: f7f8 f970 bl 8001170 <Error_Handler>
  22764. }
  22765. if (USBD_Start(&hUsbDeviceHS) != USBD_OK)
  22766. 8008e90: 4806 ldr r0, [pc, #24] ; (8008eac <MX_USB_DEVICE_Init+0x58>)
  22767. 8008e92: f7fe fecc bl 8007c2e <USBD_Start>
  22768. 8008e96: 4603 mov r3, r0
  22769. 8008e98: 2b00 cmp r3, #0
  22770. 8008e9a: d001 beq.n 8008ea0 <MX_USB_DEVICE_Init+0x4c>
  22771. {
  22772. Error_Handler();
  22773. 8008e9c: f7f8 f968 bl 8001170 <Error_Handler>
  22774. }
  22775. /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
  22776. HAL_PWREx_EnableUSBVoltageDetector();
  22777. 8008ea0: f7fa f8fe bl 80030a0 <HAL_PWREx_EnableUSBVoltageDetector>
  22778. /* USER CODE END USB_DEVICE_Init_PostTreatment */
  22779. }
  22780. 8008ea4: bf00 nop
  22781. 8008ea6: bd80 pop {r7, pc}
  22782. 8008ea8: 24000134 .word 0x24000134
  22783. 8008eac: 24001430 .word 0x24001430
  22784. 8008eb0: 2400001c .word 0x2400001c
  22785. 8008eb4: 24000120 .word 0x24000120
  22786. 08008eb8 <CDC_Init_HS>:
  22787. /**
  22788. * @brief Initializes the CDC media low layer over the USB HS IP
  22789. * @retval USBD_OK if all operations are OK else USBD_FAIL
  22790. */
  22791. static int8_t CDC_Init_HS(void)
  22792. {
  22793. 8008eb8: b580 push {r7, lr}
  22794. 8008eba: af00 add r7, sp, #0
  22795. /* USER CODE BEGIN 8 */
  22796. /* Set Application Buffers */
  22797. USBD_CDC_SetTxBuffer(&hUsbDeviceHS, UserTxBufferHS, 0);
  22798. 8008ebc: 2200 movs r2, #0
  22799. 8008ebe: 4905 ldr r1, [pc, #20] ; (8008ed4 <CDC_Init_HS+0x1c>)
  22800. 8008ec0: 4805 ldr r0, [pc, #20] ; (8008ed8 <CDC_Init_HS+0x20>)
  22801. 8008ec2: f7fe fdcc bl 8007a5e <USBD_CDC_SetTxBuffer>
  22802. USBD_CDC_SetRxBuffer(&hUsbDeviceHS, UserRxBufferHS);
  22803. 8008ec6: 4905 ldr r1, [pc, #20] ; (8008edc <CDC_Init_HS+0x24>)
  22804. 8008ec8: 4803 ldr r0, [pc, #12] ; (8008ed8 <CDC_Init_HS+0x20>)
  22805. 8008eca: f7fe fde6 bl 8007a9a <USBD_CDC_SetRxBuffer>
  22806. return (USBD_OK);
  22807. 8008ece: 2300 movs r3, #0
  22808. /* USER CODE END 8 */
  22809. }
  22810. 8008ed0: 4618 mov r0, r3
  22811. 8008ed2: bd80 pop {r7, pc}
  22812. 8008ed4: 24001f00 .word 0x24001f00
  22813. 8008ed8: 24001430 .word 0x24001430
  22814. 8008edc: 24001700 .word 0x24001700
  22815. 08008ee0 <CDC_DeInit_HS>:
  22816. * @brief DeInitializes the CDC media low layer
  22817. * @param None
  22818. * @retval USBD_OK if all operations are OK else USBD_FAIL
  22819. */
  22820. static int8_t CDC_DeInit_HS(void)
  22821. {
  22822. 8008ee0: b480 push {r7}
  22823. 8008ee2: af00 add r7, sp, #0
  22824. /* USER CODE BEGIN 9 */
  22825. return (USBD_OK);
  22826. 8008ee4: 2300 movs r3, #0
  22827. /* USER CODE END 9 */
  22828. }
  22829. 8008ee6: 4618 mov r0, r3
  22830. 8008ee8: 46bd mov sp, r7
  22831. 8008eea: f85d 7b04 ldr.w r7, [sp], #4
  22832. 8008eee: 4770 bx lr
  22833. 08008ef0 <CDC_Control_HS>:
  22834. * @param pbuf: Buffer containing command data (request parameters)
  22835. * @param length: Number of data to be sent (in bytes)
  22836. * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
  22837. */
  22838. static int8_t CDC_Control_HS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
  22839. {
  22840. 8008ef0: b480 push {r7}
  22841. 8008ef2: b083 sub sp, #12
  22842. 8008ef4: af00 add r7, sp, #0
  22843. 8008ef6: 4603 mov r3, r0
  22844. 8008ef8: 6039 str r1, [r7, #0]
  22845. 8008efa: 71fb strb r3, [r7, #7]
  22846. 8008efc: 4613 mov r3, r2
  22847. 8008efe: 80bb strh r3, [r7, #4]
  22848. /* USER CODE BEGIN 10 */
  22849. switch(cmd)
  22850. 8008f00: 79fb ldrb r3, [r7, #7]
  22851. 8008f02: 2b23 cmp r3, #35 ; 0x23
  22852. 8008f04: d84a bhi.n 8008f9c <CDC_Control_HS+0xac>
  22853. 8008f06: a201 add r2, pc, #4 ; (adr r2, 8008f0c <CDC_Control_HS+0x1c>)
  22854. 8008f08: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  22855. 8008f0c: 08008f9d .word 0x08008f9d
  22856. 8008f10: 08008f9d .word 0x08008f9d
  22857. 8008f14: 08008f9d .word 0x08008f9d
  22858. 8008f18: 08008f9d .word 0x08008f9d
  22859. 8008f1c: 08008f9d .word 0x08008f9d
  22860. 8008f20: 08008f9d .word 0x08008f9d
  22861. 8008f24: 08008f9d .word 0x08008f9d
  22862. 8008f28: 08008f9d .word 0x08008f9d
  22863. 8008f2c: 08008f9d .word 0x08008f9d
  22864. 8008f30: 08008f9d .word 0x08008f9d
  22865. 8008f34: 08008f9d .word 0x08008f9d
  22866. 8008f38: 08008f9d .word 0x08008f9d
  22867. 8008f3c: 08008f9d .word 0x08008f9d
  22868. 8008f40: 08008f9d .word 0x08008f9d
  22869. 8008f44: 08008f9d .word 0x08008f9d
  22870. 8008f48: 08008f9d .word 0x08008f9d
  22871. 8008f4c: 08008f9d .word 0x08008f9d
  22872. 8008f50: 08008f9d .word 0x08008f9d
  22873. 8008f54: 08008f9d .word 0x08008f9d
  22874. 8008f58: 08008f9d .word 0x08008f9d
  22875. 8008f5c: 08008f9d .word 0x08008f9d
  22876. 8008f60: 08008f9d .word 0x08008f9d
  22877. 8008f64: 08008f9d .word 0x08008f9d
  22878. 8008f68: 08008f9d .word 0x08008f9d
  22879. 8008f6c: 08008f9d .word 0x08008f9d
  22880. 8008f70: 08008f9d .word 0x08008f9d
  22881. 8008f74: 08008f9d .word 0x08008f9d
  22882. 8008f78: 08008f9d .word 0x08008f9d
  22883. 8008f7c: 08008f9d .word 0x08008f9d
  22884. 8008f80: 08008f9d .word 0x08008f9d
  22885. 8008f84: 08008f9d .word 0x08008f9d
  22886. 8008f88: 08008f9d .word 0x08008f9d
  22887. 8008f8c: 08008f9d .word 0x08008f9d
  22888. 8008f90: 08008f9d .word 0x08008f9d
  22889. 8008f94: 08008f9d .word 0x08008f9d
  22890. 8008f98: 08008f9d .word 0x08008f9d
  22891. case CDC_SEND_BREAK:
  22892. break;
  22893. default:
  22894. break;
  22895. 8008f9c: bf00 nop
  22896. }
  22897. return (USBD_OK);
  22898. 8008f9e: 2300 movs r3, #0
  22899. /* USER CODE END 10 */
  22900. }
  22901. 8008fa0: 4618 mov r0, r3
  22902. 8008fa2: 370c adds r7, #12
  22903. 8008fa4: 46bd mov sp, r7
  22904. 8008fa6: f85d 7b04 ldr.w r7, [sp], #4
  22905. 8008faa: 4770 bx lr
  22906. 08008fac <CDC_Receive_HS>:
  22907. * @param Buf: Buffer of data to be received
  22908. * @param Len: Number of data received (in bytes)
  22909. * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAILL
  22910. */
  22911. static int8_t CDC_Receive_HS(uint8_t* Buf, uint32_t *Len)
  22912. {
  22913. 8008fac: b580 push {r7, lr}
  22914. 8008fae: b082 sub sp, #8
  22915. 8008fb0: af00 add r7, sp, #0
  22916. 8008fb2: 6078 str r0, [r7, #4]
  22917. 8008fb4: 6039 str r1, [r7, #0]
  22918. /* USER CODE BEGIN 11 */
  22919. USBD_CDC_SetRxBuffer(&hUsbDeviceHS, &Buf[0]);
  22920. 8008fb6: 6879 ldr r1, [r7, #4]
  22921. 8008fb8: 4805 ldr r0, [pc, #20] ; (8008fd0 <CDC_Receive_HS+0x24>)
  22922. 8008fba: f7fe fd6e bl 8007a9a <USBD_CDC_SetRxBuffer>
  22923. USBD_CDC_ReceivePacket(&hUsbDeviceHS);
  22924. 8008fbe: 4804 ldr r0, [pc, #16] ; (8008fd0 <CDC_Receive_HS+0x24>)
  22925. 8008fc0: f7fe fdb4 bl 8007b2c <USBD_CDC_ReceivePacket>
  22926. return (USBD_OK);
  22927. 8008fc4: 2300 movs r3, #0
  22928. /* USER CODE END 11 */
  22929. }
  22930. 8008fc6: 4618 mov r0, r3
  22931. 8008fc8: 3708 adds r7, #8
  22932. 8008fca: 46bd mov sp, r7
  22933. 8008fcc: bd80 pop {r7, pc}
  22934. 8008fce: bf00 nop
  22935. 8008fd0: 24001430 .word 0x24001430
  22936. 08008fd4 <CDC_Transmit_HS>:
  22937. * @param Buf: Buffer of data to be sent
  22938. * @param Len: Number of data to be sent (in bytes)
  22939. * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
  22940. */
  22941. uint8_t CDC_Transmit_HS(uint8_t* Buf, uint16_t Len)
  22942. {
  22943. 8008fd4: b580 push {r7, lr}
  22944. 8008fd6: b084 sub sp, #16
  22945. 8008fd8: af00 add r7, sp, #0
  22946. 8008fda: 6078 str r0, [r7, #4]
  22947. 8008fdc: 460b mov r3, r1
  22948. 8008fde: 807b strh r3, [r7, #2]
  22949. uint8_t result = USBD_OK;
  22950. 8008fe0: 2300 movs r3, #0
  22951. 8008fe2: 73fb strb r3, [r7, #15]
  22952. /* USER CODE BEGIN 12 */
  22953. USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceHS.pClassData;
  22954. 8008fe4: 4b0d ldr r3, [pc, #52] ; (800901c <CDC_Transmit_HS+0x48>)
  22955. 8008fe6: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
  22956. 8008fea: 60bb str r3, [r7, #8]
  22957. if (hcdc->TxState != 0){
  22958. 8008fec: 68bb ldr r3, [r7, #8]
  22959. 8008fee: f8d3 3214 ldr.w r3, [r3, #532] ; 0x214
  22960. 8008ff2: 2b00 cmp r3, #0
  22961. 8008ff4: d001 beq.n 8008ffa <CDC_Transmit_HS+0x26>
  22962. return USBD_BUSY;
  22963. 8008ff6: 2301 movs r3, #1
  22964. 8008ff8: e00b b.n 8009012 <CDC_Transmit_HS+0x3e>
  22965. }
  22966. USBD_CDC_SetTxBuffer(&hUsbDeviceHS, Buf, Len);
  22967. 8008ffa: 887b ldrh r3, [r7, #2]
  22968. 8008ffc: 461a mov r2, r3
  22969. 8008ffe: 6879 ldr r1, [r7, #4]
  22970. 8009000: 4806 ldr r0, [pc, #24] ; (800901c <CDC_Transmit_HS+0x48>)
  22971. 8009002: f7fe fd2c bl 8007a5e <USBD_CDC_SetTxBuffer>
  22972. result = USBD_CDC_TransmitPacket(&hUsbDeviceHS);
  22973. 8009006: 4805 ldr r0, [pc, #20] ; (800901c <CDC_Transmit_HS+0x48>)
  22974. 8009008: f7fe fd60 bl 8007acc <USBD_CDC_TransmitPacket>
  22975. 800900c: 4603 mov r3, r0
  22976. 800900e: 73fb strb r3, [r7, #15]
  22977. /* USER CODE END 12 */
  22978. return result;
  22979. 8009010: 7bfb ldrb r3, [r7, #15]
  22980. }
  22981. 8009012: 4618 mov r0, r3
  22982. 8009014: 3710 adds r7, #16
  22983. 8009016: 46bd mov sp, r7
  22984. 8009018: bd80 pop {r7, pc}
  22985. 800901a: bf00 nop
  22986. 800901c: 24001430 .word 0x24001430
  22987. 08009020 <CDC_TransmitCplt_HS>:
  22988. * @param Buf: Buffer of data to be received
  22989. * @param Len: Number of data received (in bytes)
  22990. * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
  22991. */
  22992. static int8_t CDC_TransmitCplt_HS(uint8_t *Buf, uint32_t *Len, uint8_t epnum)
  22993. {
  22994. 8009020: b480 push {r7}
  22995. 8009022: b087 sub sp, #28
  22996. 8009024: af00 add r7, sp, #0
  22997. 8009026: 60f8 str r0, [r7, #12]
  22998. 8009028: 60b9 str r1, [r7, #8]
  22999. 800902a: 4613 mov r3, r2
  23000. 800902c: 71fb strb r3, [r7, #7]
  23001. uint8_t result = USBD_OK;
  23002. 800902e: 2300 movs r3, #0
  23003. 8009030: 75fb strb r3, [r7, #23]
  23004. /* USER CODE BEGIN 14 */
  23005. UNUSED(Buf);
  23006. UNUSED(Len);
  23007. UNUSED(epnum);
  23008. /* USER CODE END 14 */
  23009. return result;
  23010. 8009032: f997 3017 ldrsb.w r3, [r7, #23]
  23011. }
  23012. 8009036: 4618 mov r0, r3
  23013. 8009038: 371c adds r7, #28
  23014. 800903a: 46bd mov sp, r7
  23015. 800903c: f85d 7b04 ldr.w r7, [sp], #4
  23016. 8009040: 4770 bx lr
  23017. ...
  23018. 08009044 <USBD_HS_DeviceDescriptor>:
  23019. * @param speed : Current device speed
  23020. * @param length : Pointer to data length variable
  23021. * @retval Pointer to descriptor buffer
  23022. */
  23023. uint8_t * USBD_HS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
  23024. {
  23025. 8009044: b480 push {r7}
  23026. 8009046: b083 sub sp, #12
  23027. 8009048: af00 add r7, sp, #0
  23028. 800904a: 4603 mov r3, r0
  23029. 800904c: 6039 str r1, [r7, #0]
  23030. 800904e: 71fb strb r3, [r7, #7]
  23031. UNUSED(speed);
  23032. *length = sizeof(USBD_HS_DeviceDesc);
  23033. 8009050: 683b ldr r3, [r7, #0]
  23034. 8009052: 2212 movs r2, #18
  23035. 8009054: 801a strh r2, [r3, #0]
  23036. return USBD_HS_DeviceDesc;
  23037. 8009056: 4b03 ldr r3, [pc, #12] ; (8009064 <USBD_HS_DeviceDescriptor+0x20>)
  23038. }
  23039. 8009058: 4618 mov r0, r3
  23040. 800905a: 370c adds r7, #12
  23041. 800905c: 46bd mov sp, r7
  23042. 800905e: f85d 7b04 ldr.w r7, [sp], #4
  23043. 8009062: 4770 bx lr
  23044. 8009064: 24000150 .word 0x24000150
  23045. 08009068 <USBD_HS_LangIDStrDescriptor>:
  23046. * @param speed : Current device speed
  23047. * @param length : Pointer to data length variable
  23048. * @retval Pointer to descriptor buffer
  23049. */
  23050. uint8_t * USBD_HS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
  23051. {
  23052. 8009068: b480 push {r7}
  23053. 800906a: b083 sub sp, #12
  23054. 800906c: af00 add r7, sp, #0
  23055. 800906e: 4603 mov r3, r0
  23056. 8009070: 6039 str r1, [r7, #0]
  23057. 8009072: 71fb strb r3, [r7, #7]
  23058. UNUSED(speed);
  23059. *length = sizeof(USBD_LangIDDesc);
  23060. 8009074: 683b ldr r3, [r7, #0]
  23061. 8009076: 2204 movs r2, #4
  23062. 8009078: 801a strh r2, [r3, #0]
  23063. return USBD_LangIDDesc;
  23064. 800907a: 4b03 ldr r3, [pc, #12] ; (8009088 <USBD_HS_LangIDStrDescriptor+0x20>)
  23065. }
  23066. 800907c: 4618 mov r0, r3
  23067. 800907e: 370c adds r7, #12
  23068. 8009080: 46bd mov sp, r7
  23069. 8009082: f85d 7b04 ldr.w r7, [sp], #4
  23070. 8009086: 4770 bx lr
  23071. 8009088: 24000164 .word 0x24000164
  23072. 0800908c <USBD_HS_ProductStrDescriptor>:
  23073. * @param speed : current device speed
  23074. * @param length : pointer to data length variable
  23075. * @retval pointer to descriptor buffer
  23076. */
  23077. uint8_t * USBD_HS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
  23078. {
  23079. 800908c: b580 push {r7, lr}
  23080. 800908e: b082 sub sp, #8
  23081. 8009090: af00 add r7, sp, #0
  23082. 8009092: 4603 mov r3, r0
  23083. 8009094: 6039 str r1, [r7, #0]
  23084. 8009096: 71fb strb r3, [r7, #7]
  23085. if(speed == 0)
  23086. 8009098: 79fb ldrb r3, [r7, #7]
  23087. 800909a: 2b00 cmp r3, #0
  23088. 800909c: d105 bne.n 80090aa <USBD_HS_ProductStrDescriptor+0x1e>
  23089. {
  23090. USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_HS, USBD_StrDesc, length);
  23091. 800909e: 683a ldr r2, [r7, #0]
  23092. 80090a0: 4907 ldr r1, [pc, #28] ; (80090c0 <USBD_HS_ProductStrDescriptor+0x34>)
  23093. 80090a2: 4808 ldr r0, [pc, #32] ; (80090c4 <USBD_HS_ProductStrDescriptor+0x38>)
  23094. 80090a4: f7ff fdf5 bl 8008c92 <USBD_GetString>
  23095. 80090a8: e004 b.n 80090b4 <USBD_HS_ProductStrDescriptor+0x28>
  23096. }
  23097. else
  23098. {
  23099. USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_HS, USBD_StrDesc, length);
  23100. 80090aa: 683a ldr r2, [r7, #0]
  23101. 80090ac: 4904 ldr r1, [pc, #16] ; (80090c0 <USBD_HS_ProductStrDescriptor+0x34>)
  23102. 80090ae: 4805 ldr r0, [pc, #20] ; (80090c4 <USBD_HS_ProductStrDescriptor+0x38>)
  23103. 80090b0: f7ff fdef bl 8008c92 <USBD_GetString>
  23104. }
  23105. return USBD_StrDesc;
  23106. 80090b4: 4b02 ldr r3, [pc, #8] ; (80090c0 <USBD_HS_ProductStrDescriptor+0x34>)
  23107. }
  23108. 80090b6: 4618 mov r0, r3
  23109. 80090b8: 3708 adds r7, #8
  23110. 80090ba: 46bd mov sp, r7
  23111. 80090bc: bd80 pop {r7, pc}
  23112. 80090be: bf00 nop
  23113. 80090c0: 24002700 .word 0x24002700
  23114. 80090c4: 0800a8e8 .word 0x0800a8e8
  23115. 080090c8 <USBD_HS_ManufacturerStrDescriptor>:
  23116. * @param speed : Current device speed
  23117. * @param length : Pointer to data length variable
  23118. * @retval Pointer to descriptor buffer
  23119. */
  23120. uint8_t * USBD_HS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
  23121. {
  23122. 80090c8: b580 push {r7, lr}
  23123. 80090ca: b082 sub sp, #8
  23124. 80090cc: af00 add r7, sp, #0
  23125. 80090ce: 4603 mov r3, r0
  23126. 80090d0: 6039 str r1, [r7, #0]
  23127. 80090d2: 71fb strb r3, [r7, #7]
  23128. UNUSED(speed);
  23129. USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
  23130. 80090d4: 683a ldr r2, [r7, #0]
  23131. 80090d6: 4904 ldr r1, [pc, #16] ; (80090e8 <USBD_HS_ManufacturerStrDescriptor+0x20>)
  23132. 80090d8: 4804 ldr r0, [pc, #16] ; (80090ec <USBD_HS_ManufacturerStrDescriptor+0x24>)
  23133. 80090da: f7ff fdda bl 8008c92 <USBD_GetString>
  23134. return USBD_StrDesc;
  23135. 80090de: 4b02 ldr r3, [pc, #8] ; (80090e8 <USBD_HS_ManufacturerStrDescriptor+0x20>)
  23136. }
  23137. 80090e0: 4618 mov r0, r3
  23138. 80090e2: 3708 adds r7, #8
  23139. 80090e4: 46bd mov sp, r7
  23140. 80090e6: bd80 pop {r7, pc}
  23141. 80090e8: 24002700 .word 0x24002700
  23142. 80090ec: 0800a900 .word 0x0800a900
  23143. 080090f0 <USBD_HS_SerialStrDescriptor>:
  23144. * @param speed : Current device speed
  23145. * @param length : Pointer to data length variable
  23146. * @retval Pointer to descriptor buffer
  23147. */
  23148. uint8_t * USBD_HS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
  23149. {
  23150. 80090f0: b580 push {r7, lr}
  23151. 80090f2: b082 sub sp, #8
  23152. 80090f4: af00 add r7, sp, #0
  23153. 80090f6: 4603 mov r3, r0
  23154. 80090f8: 6039 str r1, [r7, #0]
  23155. 80090fa: 71fb strb r3, [r7, #7]
  23156. UNUSED(speed);
  23157. *length = USB_SIZ_STRING_SERIAL;
  23158. 80090fc: 683b ldr r3, [r7, #0]
  23159. 80090fe: 221a movs r2, #26
  23160. 8009100: 801a strh r2, [r3, #0]
  23161. /* Update the serial number string descriptor with the data from the unique
  23162. * ID */
  23163. Get_SerialNum();
  23164. 8009102: f000 f843 bl 800918c <Get_SerialNum>
  23165. /* USER CODE BEGIN USBD_HS_SerialStrDescriptor */
  23166. /* USER CODE END USBD_HS_SerialStrDescriptor */
  23167. return (uint8_t *) USBD_StringSerial;
  23168. 8009106: 4b02 ldr r3, [pc, #8] ; (8009110 <USBD_HS_SerialStrDescriptor+0x20>)
  23169. }
  23170. 8009108: 4618 mov r0, r3
  23171. 800910a: 3708 adds r7, #8
  23172. 800910c: 46bd mov sp, r7
  23173. 800910e: bd80 pop {r7, pc}
  23174. 8009110: 24000168 .word 0x24000168
  23175. 08009114 <USBD_HS_ConfigStrDescriptor>:
  23176. * @param speed : Current device speed
  23177. * @param length : Pointer to data length variable
  23178. * @retval Pointer to descriptor buffer
  23179. */
  23180. uint8_t * USBD_HS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
  23181. {
  23182. 8009114: b580 push {r7, lr}
  23183. 8009116: b082 sub sp, #8
  23184. 8009118: af00 add r7, sp, #0
  23185. 800911a: 4603 mov r3, r0
  23186. 800911c: 6039 str r1, [r7, #0]
  23187. 800911e: 71fb strb r3, [r7, #7]
  23188. if(speed == USBD_SPEED_HIGH)
  23189. 8009120: 79fb ldrb r3, [r7, #7]
  23190. 8009122: 2b00 cmp r3, #0
  23191. 8009124: d105 bne.n 8009132 <USBD_HS_ConfigStrDescriptor+0x1e>
  23192. {
  23193. USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_HS, USBD_StrDesc, length);
  23194. 8009126: 683a ldr r2, [r7, #0]
  23195. 8009128: 4907 ldr r1, [pc, #28] ; (8009148 <USBD_HS_ConfigStrDescriptor+0x34>)
  23196. 800912a: 4808 ldr r0, [pc, #32] ; (800914c <USBD_HS_ConfigStrDescriptor+0x38>)
  23197. 800912c: f7ff fdb1 bl 8008c92 <USBD_GetString>
  23198. 8009130: e004 b.n 800913c <USBD_HS_ConfigStrDescriptor+0x28>
  23199. }
  23200. else
  23201. {
  23202. USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_HS, USBD_StrDesc, length);
  23203. 8009132: 683a ldr r2, [r7, #0]
  23204. 8009134: 4904 ldr r1, [pc, #16] ; (8009148 <USBD_HS_ConfigStrDescriptor+0x34>)
  23205. 8009136: 4805 ldr r0, [pc, #20] ; (800914c <USBD_HS_ConfigStrDescriptor+0x38>)
  23206. 8009138: f7ff fdab bl 8008c92 <USBD_GetString>
  23207. }
  23208. return USBD_StrDesc;
  23209. 800913c: 4b02 ldr r3, [pc, #8] ; (8009148 <USBD_HS_ConfigStrDescriptor+0x34>)
  23210. }
  23211. 800913e: 4618 mov r0, r3
  23212. 8009140: 3708 adds r7, #8
  23213. 8009142: 46bd mov sp, r7
  23214. 8009144: bd80 pop {r7, pc}
  23215. 8009146: bf00 nop
  23216. 8009148: 24002700 .word 0x24002700
  23217. 800914c: 0800a914 .word 0x0800a914
  23218. 08009150 <USBD_HS_InterfaceStrDescriptor>:
  23219. * @param speed : Current device speed
  23220. * @param length : Pointer to data length variable
  23221. * @retval Pointer to descriptor buffer
  23222. */
  23223. uint8_t * USBD_HS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
  23224. {
  23225. 8009150: b580 push {r7, lr}
  23226. 8009152: b082 sub sp, #8
  23227. 8009154: af00 add r7, sp, #0
  23228. 8009156: 4603 mov r3, r0
  23229. 8009158: 6039 str r1, [r7, #0]
  23230. 800915a: 71fb strb r3, [r7, #7]
  23231. if(speed == 0)
  23232. 800915c: 79fb ldrb r3, [r7, #7]
  23233. 800915e: 2b00 cmp r3, #0
  23234. 8009160: d105 bne.n 800916e <USBD_HS_InterfaceStrDescriptor+0x1e>
  23235. {
  23236. USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_HS, USBD_StrDesc, length);
  23237. 8009162: 683a ldr r2, [r7, #0]
  23238. 8009164: 4907 ldr r1, [pc, #28] ; (8009184 <USBD_HS_InterfaceStrDescriptor+0x34>)
  23239. 8009166: 4808 ldr r0, [pc, #32] ; (8009188 <USBD_HS_InterfaceStrDescriptor+0x38>)
  23240. 8009168: f7ff fd93 bl 8008c92 <USBD_GetString>
  23241. 800916c: e004 b.n 8009178 <USBD_HS_InterfaceStrDescriptor+0x28>
  23242. }
  23243. else
  23244. {
  23245. USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_HS, USBD_StrDesc, length);
  23246. 800916e: 683a ldr r2, [r7, #0]
  23247. 8009170: 4904 ldr r1, [pc, #16] ; (8009184 <USBD_HS_InterfaceStrDescriptor+0x34>)
  23248. 8009172: 4805 ldr r0, [pc, #20] ; (8009188 <USBD_HS_InterfaceStrDescriptor+0x38>)
  23249. 8009174: f7ff fd8d bl 8008c92 <USBD_GetString>
  23250. }
  23251. return USBD_StrDesc;
  23252. 8009178: 4b02 ldr r3, [pc, #8] ; (8009184 <USBD_HS_InterfaceStrDescriptor+0x34>)
  23253. }
  23254. 800917a: 4618 mov r0, r3
  23255. 800917c: 3708 adds r7, #8
  23256. 800917e: 46bd mov sp, r7
  23257. 8009180: bd80 pop {r7, pc}
  23258. 8009182: bf00 nop
  23259. 8009184: 24002700 .word 0x24002700
  23260. 8009188: 0800a920 .word 0x0800a920
  23261. 0800918c <Get_SerialNum>:
  23262. * @brief Create the serial number string descriptor
  23263. * @param None
  23264. * @retval None
  23265. */
  23266. static void Get_SerialNum(void)
  23267. {
  23268. 800918c: b580 push {r7, lr}
  23269. 800918e: b084 sub sp, #16
  23270. 8009190: af00 add r7, sp, #0
  23271. uint32_t deviceserial0, deviceserial1, deviceserial2;
  23272. deviceserial0 = *(uint32_t *) DEVICE_ID1;
  23273. 8009192: 4b0f ldr r3, [pc, #60] ; (80091d0 <Get_SerialNum+0x44>)
  23274. 8009194: 681b ldr r3, [r3, #0]
  23275. 8009196: 60fb str r3, [r7, #12]
  23276. deviceserial1 = *(uint32_t *) DEVICE_ID2;
  23277. 8009198: 4b0e ldr r3, [pc, #56] ; (80091d4 <Get_SerialNum+0x48>)
  23278. 800919a: 681b ldr r3, [r3, #0]
  23279. 800919c: 60bb str r3, [r7, #8]
  23280. deviceserial2 = *(uint32_t *) DEVICE_ID3;
  23281. 800919e: 4b0e ldr r3, [pc, #56] ; (80091d8 <Get_SerialNum+0x4c>)
  23282. 80091a0: 681b ldr r3, [r3, #0]
  23283. 80091a2: 607b str r3, [r7, #4]
  23284. deviceserial0 += deviceserial2;
  23285. 80091a4: 68fa ldr r2, [r7, #12]
  23286. 80091a6: 687b ldr r3, [r7, #4]
  23287. 80091a8: 4413 add r3, r2
  23288. 80091aa: 60fb str r3, [r7, #12]
  23289. if (deviceserial0 != 0)
  23290. 80091ac: 68fb ldr r3, [r7, #12]
  23291. 80091ae: 2b00 cmp r3, #0
  23292. 80091b0: d009 beq.n 80091c6 <Get_SerialNum+0x3a>
  23293. {
  23294. IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
  23295. 80091b2: 2208 movs r2, #8
  23296. 80091b4: 4909 ldr r1, [pc, #36] ; (80091dc <Get_SerialNum+0x50>)
  23297. 80091b6: 68f8 ldr r0, [r7, #12]
  23298. 80091b8: f000 f814 bl 80091e4 <IntToUnicode>
  23299. IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
  23300. 80091bc: 2204 movs r2, #4
  23301. 80091be: 4908 ldr r1, [pc, #32] ; (80091e0 <Get_SerialNum+0x54>)
  23302. 80091c0: 68b8 ldr r0, [r7, #8]
  23303. 80091c2: f000 f80f bl 80091e4 <IntToUnicode>
  23304. }
  23305. }
  23306. 80091c6: bf00 nop
  23307. 80091c8: 3710 adds r7, #16
  23308. 80091ca: 46bd mov sp, r7
  23309. 80091cc: bd80 pop {r7, pc}
  23310. 80091ce: bf00 nop
  23311. 80091d0: 1ff1e800 .word 0x1ff1e800
  23312. 80091d4: 1ff1e804 .word 0x1ff1e804
  23313. 80091d8: 1ff1e808 .word 0x1ff1e808
  23314. 80091dc: 2400016a .word 0x2400016a
  23315. 80091e0: 2400017a .word 0x2400017a
  23316. 080091e4 <IntToUnicode>:
  23317. * @param pbuf: pointer to the buffer
  23318. * @param len: buffer length
  23319. * @retval None
  23320. */
  23321. static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
  23322. {
  23323. 80091e4: b480 push {r7}
  23324. 80091e6: b087 sub sp, #28
  23325. 80091e8: af00 add r7, sp, #0
  23326. 80091ea: 60f8 str r0, [r7, #12]
  23327. 80091ec: 60b9 str r1, [r7, #8]
  23328. 80091ee: 4613 mov r3, r2
  23329. 80091f0: 71fb strb r3, [r7, #7]
  23330. uint8_t idx = 0;
  23331. 80091f2: 2300 movs r3, #0
  23332. 80091f4: 75fb strb r3, [r7, #23]
  23333. for (idx = 0; idx < len; idx++)
  23334. 80091f6: 2300 movs r3, #0
  23335. 80091f8: 75fb strb r3, [r7, #23]
  23336. 80091fa: e027 b.n 800924c <IntToUnicode+0x68>
  23337. {
  23338. if (((value >> 28)) < 0xA)
  23339. 80091fc: 68fb ldr r3, [r7, #12]
  23340. 80091fe: 0f1b lsrs r3, r3, #28
  23341. 8009200: 2b09 cmp r3, #9
  23342. 8009202: d80b bhi.n 800921c <IntToUnicode+0x38>
  23343. {
  23344. pbuf[2 * idx] = (value >> 28) + '0';
  23345. 8009204: 68fb ldr r3, [r7, #12]
  23346. 8009206: 0f1b lsrs r3, r3, #28
  23347. 8009208: b2da uxtb r2, r3
  23348. 800920a: 7dfb ldrb r3, [r7, #23]
  23349. 800920c: 005b lsls r3, r3, #1
  23350. 800920e: 4619 mov r1, r3
  23351. 8009210: 68bb ldr r3, [r7, #8]
  23352. 8009212: 440b add r3, r1
  23353. 8009214: 3230 adds r2, #48 ; 0x30
  23354. 8009216: b2d2 uxtb r2, r2
  23355. 8009218: 701a strb r2, [r3, #0]
  23356. 800921a: e00a b.n 8009232 <IntToUnicode+0x4e>
  23357. }
  23358. else
  23359. {
  23360. pbuf[2 * idx] = (value >> 28) + 'A' - 10;
  23361. 800921c: 68fb ldr r3, [r7, #12]
  23362. 800921e: 0f1b lsrs r3, r3, #28
  23363. 8009220: b2da uxtb r2, r3
  23364. 8009222: 7dfb ldrb r3, [r7, #23]
  23365. 8009224: 005b lsls r3, r3, #1
  23366. 8009226: 4619 mov r1, r3
  23367. 8009228: 68bb ldr r3, [r7, #8]
  23368. 800922a: 440b add r3, r1
  23369. 800922c: 3237 adds r2, #55 ; 0x37
  23370. 800922e: b2d2 uxtb r2, r2
  23371. 8009230: 701a strb r2, [r3, #0]
  23372. }
  23373. value = value << 4;
  23374. 8009232: 68fb ldr r3, [r7, #12]
  23375. 8009234: 011b lsls r3, r3, #4
  23376. 8009236: 60fb str r3, [r7, #12]
  23377. pbuf[2 * idx + 1] = 0;
  23378. 8009238: 7dfb ldrb r3, [r7, #23]
  23379. 800923a: 005b lsls r3, r3, #1
  23380. 800923c: 3301 adds r3, #1
  23381. 800923e: 68ba ldr r2, [r7, #8]
  23382. 8009240: 4413 add r3, r2
  23383. 8009242: 2200 movs r2, #0
  23384. 8009244: 701a strb r2, [r3, #0]
  23385. for (idx = 0; idx < len; idx++)
  23386. 8009246: 7dfb ldrb r3, [r7, #23]
  23387. 8009248: 3301 adds r3, #1
  23388. 800924a: 75fb strb r3, [r7, #23]
  23389. 800924c: 7dfa ldrb r2, [r7, #23]
  23390. 800924e: 79fb ldrb r3, [r7, #7]
  23391. 8009250: 429a cmp r2, r3
  23392. 8009252: d3d3 bcc.n 80091fc <IntToUnicode+0x18>
  23393. }
  23394. }
  23395. 8009254: bf00 nop
  23396. 8009256: bf00 nop
  23397. 8009258: 371c adds r7, #28
  23398. 800925a: 46bd mov sp, r7
  23399. 800925c: f85d 7b04 ldr.w r7, [sp], #4
  23400. 8009260: 4770 bx lr
  23401. ...
  23402. 08009264 <HAL_PCD_MspInit>:
  23403. LL Driver Callbacks (PCD -> USB Device Library)
  23404. *******************************************************************************/
  23405. /* MSP Init */
  23406. void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
  23407. {
  23408. 8009264: b580 push {r7, lr}
  23409. 8009266: b0b6 sub sp, #216 ; 0xd8
  23410. 8009268: af00 add r7, sp, #0
  23411. 800926a: 6078 str r0, [r7, #4]
  23412. GPIO_InitTypeDef GPIO_InitStruct = {0};
  23413. 800926c: f107 03c4 add.w r3, r7, #196 ; 0xc4
  23414. 8009270: 2200 movs r2, #0
  23415. 8009272: 601a str r2, [r3, #0]
  23416. 8009274: 605a str r2, [r3, #4]
  23417. 8009276: 609a str r2, [r3, #8]
  23418. 8009278: 60da str r2, [r3, #12]
  23419. 800927a: 611a str r2, [r3, #16]
  23420. RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
  23421. 800927c: f107 0310 add.w r3, r7, #16
  23422. 8009280: 22b4 movs r2, #180 ; 0xb4
  23423. 8009282: 2100 movs r1, #0
  23424. 8009284: 4618 mov r0, r3
  23425. 8009286: f000 fb83 bl 8009990 <memset>
  23426. if(pcdHandle->Instance==USB_OTG_HS)
  23427. 800928a: 687b ldr r3, [r7, #4]
  23428. 800928c: 681b ldr r3, [r3, #0]
  23429. 800928e: 4a2b ldr r2, [pc, #172] ; (800933c <HAL_PCD_MspInit+0xd8>)
  23430. 8009290: 4293 cmp r3, r2
  23431. 8009292: d14e bne.n 8009332 <HAL_PCD_MspInit+0xce>
  23432. /* USER CODE BEGIN USB_OTG_HS_MspInit 0 */
  23433. /* USER CODE END USB_OTG_HS_MspInit 0 */
  23434. /** Initializes the peripherals clock
  23435. */
  23436. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
  23437. 8009294: f44f 2380 mov.w r3, #262144 ; 0x40000
  23438. 8009298: 613b str r3, [r7, #16]
  23439. PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
  23440. 800929a: f44f 1340 mov.w r3, #3145728 ; 0x300000
  23441. 800929e: f8c7 3090 str.w r3, [r7, #144] ; 0x90
  23442. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  23443. 80092a2: f107 0310 add.w r3, r7, #16
  23444. 80092a6: 4618 mov r0, r3
  23445. 80092a8: f7fa fe16 bl 8003ed8 <HAL_RCCEx_PeriphCLKConfig>
  23446. 80092ac: 4603 mov r3, r0
  23447. 80092ae: 2b00 cmp r3, #0
  23448. 80092b0: d001 beq.n 80092b6 <HAL_PCD_MspInit+0x52>
  23449. {
  23450. Error_Handler();
  23451. 80092b2: f7f7 ff5d bl 8001170 <Error_Handler>
  23452. }
  23453. /** Enable USB Voltage detector
  23454. */
  23455. HAL_PWREx_EnableUSBVoltageDetector();
  23456. 80092b6: f7f9 fef3 bl 80030a0 <HAL_PWREx_EnableUSBVoltageDetector>
  23457. __HAL_RCC_GPIOA_CLK_ENABLE();
  23458. 80092ba: 4b21 ldr r3, [pc, #132] ; (8009340 <HAL_PCD_MspInit+0xdc>)
  23459. 80092bc: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  23460. 80092c0: 4a1f ldr r2, [pc, #124] ; (8009340 <HAL_PCD_MspInit+0xdc>)
  23461. 80092c2: f043 0301 orr.w r3, r3, #1
  23462. 80092c6: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0
  23463. 80092ca: 4b1d ldr r3, [pc, #116] ; (8009340 <HAL_PCD_MspInit+0xdc>)
  23464. 80092cc: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
  23465. 80092d0: f003 0301 and.w r3, r3, #1
  23466. 80092d4: 60fb str r3, [r7, #12]
  23467. 80092d6: 68fb ldr r3, [r7, #12]
  23468. /**USB_OTG_HS GPIO Configuration
  23469. PA10 ------> USB_OTG_HS_ID
  23470. */
  23471. GPIO_InitStruct.Pin = USB_FS_ID_Pin;
  23472. 80092d8: f44f 6380 mov.w r3, #1024 ; 0x400
  23473. 80092dc: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
  23474. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  23475. 80092e0: 2302 movs r3, #2
  23476. 80092e2: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
  23477. GPIO_InitStruct.Pull = GPIO_NOPULL;
  23478. 80092e6: 2300 movs r3, #0
  23479. 80092e8: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
  23480. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  23481. 80092ec: 2300 movs r3, #0
  23482. 80092ee: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
  23483. GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_HS;
  23484. 80092f2: 230a movs r3, #10
  23485. 80092f4: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4
  23486. HAL_GPIO_Init(USB_FS_ID_GPIO_Port, &GPIO_InitStruct);
  23487. 80092f8: f107 03c4 add.w r3, r7, #196 ; 0xc4
  23488. 80092fc: 4619 mov r1, r3
  23489. 80092fe: 4811 ldr r0, [pc, #68] ; (8009344 <HAL_PCD_MspInit+0xe0>)
  23490. 8009300: f7f8 faea bl 80018d8 <HAL_GPIO_Init>
  23491. /* Peripheral clock enable */
  23492. __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
  23493. 8009304: 4b0e ldr r3, [pc, #56] ; (8009340 <HAL_PCD_MspInit+0xdc>)
  23494. 8009306: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8
  23495. 800930a: 4a0d ldr r2, [pc, #52] ; (8009340 <HAL_PCD_MspInit+0xdc>)
  23496. 800930c: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
  23497. 8009310: f8c2 30d8 str.w r3, [r2, #216] ; 0xd8
  23498. 8009314: 4b0a ldr r3, [pc, #40] ; (8009340 <HAL_PCD_MspInit+0xdc>)
  23499. 8009316: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8
  23500. 800931a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
  23501. 800931e: 60bb str r3, [r7, #8]
  23502. 8009320: 68bb ldr r3, [r7, #8]
  23503. /* Peripheral interrupt init */
  23504. HAL_NVIC_SetPriority(OTG_HS_IRQn, 0, 0);
  23505. 8009322: 2200 movs r2, #0
  23506. 8009324: 2100 movs r1, #0
  23507. 8009326: 204d movs r0, #77 ; 0x4d
  23508. 8009328: f7f8 faa1 bl 800186e <HAL_NVIC_SetPriority>
  23509. HAL_NVIC_EnableIRQ(OTG_HS_IRQn);
  23510. 800932c: 204d movs r0, #77 ; 0x4d
  23511. 800932e: f7f8 fab8 bl 80018a2 <HAL_NVIC_EnableIRQ>
  23512. /* USER CODE BEGIN USB_OTG_HS_MspInit 1 */
  23513. /* USER CODE END USB_OTG_HS_MspInit 1 */
  23514. }
  23515. }
  23516. 8009332: bf00 nop
  23517. 8009334: 37d8 adds r7, #216 ; 0xd8
  23518. 8009336: 46bd mov sp, r7
  23519. 8009338: bd80 pop {r7, pc}
  23520. 800933a: bf00 nop
  23521. 800933c: 40040000 .word 0x40040000
  23522. 8009340: 58024400 .word 0x58024400
  23523. 8009344: 58020000 .word 0x58020000
  23524. 08009348 <HAL_PCD_SetupStageCallback>:
  23525. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  23526. static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
  23527. #else
  23528. void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
  23529. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23530. {
  23531. 8009348: b580 push {r7, lr}
  23532. 800934a: b082 sub sp, #8
  23533. 800934c: af00 add r7, sp, #0
  23534. 800934e: 6078 str r0, [r7, #4]
  23535. USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
  23536. 8009350: 687b ldr r3, [r7, #4]
  23537. 8009352: f8d3 2404 ldr.w r2, [r3, #1028] ; 0x404
  23538. 8009356: 687b ldr r3, [r7, #4]
  23539. 8009358: f503 7371 add.w r3, r3, #964 ; 0x3c4
  23540. 800935c: 4619 mov r1, r3
  23541. 800935e: 4610 mov r0, r2
  23542. 8009360: f7fe fcb0 bl 8007cc4 <USBD_LL_SetupStage>
  23543. }
  23544. 8009364: bf00 nop
  23545. 8009366: 3708 adds r7, #8
  23546. 8009368: 46bd mov sp, r7
  23547. 800936a: bd80 pop {r7, pc}
  23548. 0800936c <HAL_PCD_DataOutStageCallback>:
  23549. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  23550. static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
  23551. #else
  23552. void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
  23553. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23554. {
  23555. 800936c: b580 push {r7, lr}
  23556. 800936e: b082 sub sp, #8
  23557. 8009370: af00 add r7, sp, #0
  23558. 8009372: 6078 str r0, [r7, #4]
  23559. 8009374: 460b mov r3, r1
  23560. 8009376: 70fb strb r3, [r7, #3]
  23561. USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
  23562. 8009378: 687b ldr r3, [r7, #4]
  23563. 800937a: f8d3 0404 ldr.w r0, [r3, #1028] ; 0x404
  23564. 800937e: 78fa ldrb r2, [r7, #3]
  23565. 8009380: 6879 ldr r1, [r7, #4]
  23566. 8009382: 4613 mov r3, r2
  23567. 8009384: 00db lsls r3, r3, #3
  23568. 8009386: 1a9b subs r3, r3, r2
  23569. 8009388: 009b lsls r3, r3, #2
  23570. 800938a: 440b add r3, r1
  23571. 800938c: f503 7302 add.w r3, r3, #520 ; 0x208
  23572. 8009390: 681a ldr r2, [r3, #0]
  23573. 8009392: 78fb ldrb r3, [r7, #3]
  23574. 8009394: 4619 mov r1, r3
  23575. 8009396: f7fe fcea bl 8007d6e <USBD_LL_DataOutStage>
  23576. }
  23577. 800939a: bf00 nop
  23578. 800939c: 3708 adds r7, #8
  23579. 800939e: 46bd mov sp, r7
  23580. 80093a0: bd80 pop {r7, pc}
  23581. 080093a2 <HAL_PCD_DataInStageCallback>:
  23582. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  23583. static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
  23584. #else
  23585. void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
  23586. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23587. {
  23588. 80093a2: b580 push {r7, lr}
  23589. 80093a4: b082 sub sp, #8
  23590. 80093a6: af00 add r7, sp, #0
  23591. 80093a8: 6078 str r0, [r7, #4]
  23592. 80093aa: 460b mov r3, r1
  23593. 80093ac: 70fb strb r3, [r7, #3]
  23594. USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
  23595. 80093ae: 687b ldr r3, [r7, #4]
  23596. 80093b0: f8d3 0404 ldr.w r0, [r3, #1028] ; 0x404
  23597. 80093b4: 78fa ldrb r2, [r7, #3]
  23598. 80093b6: 6879 ldr r1, [r7, #4]
  23599. 80093b8: 4613 mov r3, r2
  23600. 80093ba: 00db lsls r3, r3, #3
  23601. 80093bc: 1a9b subs r3, r3, r2
  23602. 80093be: 009b lsls r3, r3, #2
  23603. 80093c0: 440b add r3, r1
  23604. 80093c2: 3348 adds r3, #72 ; 0x48
  23605. 80093c4: 681a ldr r2, [r3, #0]
  23606. 80093c6: 78fb ldrb r3, [r7, #3]
  23607. 80093c8: 4619 mov r1, r3
  23608. 80093ca: f7fe fd33 bl 8007e34 <USBD_LL_DataInStage>
  23609. }
  23610. 80093ce: bf00 nop
  23611. 80093d0: 3708 adds r7, #8
  23612. 80093d2: 46bd mov sp, r7
  23613. 80093d4: bd80 pop {r7, pc}
  23614. 080093d6 <HAL_PCD_SOFCallback>:
  23615. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  23616. static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
  23617. #else
  23618. void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
  23619. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23620. {
  23621. 80093d6: b580 push {r7, lr}
  23622. 80093d8: b082 sub sp, #8
  23623. 80093da: af00 add r7, sp, #0
  23624. 80093dc: 6078 str r0, [r7, #4]
  23625. USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
  23626. 80093de: 687b ldr r3, [r7, #4]
  23627. 80093e0: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404
  23628. 80093e4: 4618 mov r0, r3
  23629. 80093e6: f7fe fe47 bl 8008078 <USBD_LL_SOF>
  23630. }
  23631. 80093ea: bf00 nop
  23632. 80093ec: 3708 adds r7, #8
  23633. 80093ee: 46bd mov sp, r7
  23634. 80093f0: bd80 pop {r7, pc}
  23635. 080093f2 <HAL_PCD_ResetCallback>:
  23636. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  23637. static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
  23638. #else
  23639. void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
  23640. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23641. {
  23642. 80093f2: b580 push {r7, lr}
  23643. 80093f4: b084 sub sp, #16
  23644. 80093f6: af00 add r7, sp, #0
  23645. 80093f8: 6078 str r0, [r7, #4]
  23646. USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
  23647. 80093fa: 2301 movs r3, #1
  23648. 80093fc: 73fb strb r3, [r7, #15]
  23649. if ( hpcd->Init.speed == PCD_SPEED_HIGH)
  23650. 80093fe: 687b ldr r3, [r7, #4]
  23651. 8009400: 68db ldr r3, [r3, #12]
  23652. 8009402: 2b00 cmp r3, #0
  23653. 8009404: d102 bne.n 800940c <HAL_PCD_ResetCallback+0x1a>
  23654. {
  23655. speed = USBD_SPEED_HIGH;
  23656. 8009406: 2300 movs r3, #0
  23657. 8009408: 73fb strb r3, [r7, #15]
  23658. 800940a: e008 b.n 800941e <HAL_PCD_ResetCallback+0x2c>
  23659. }
  23660. else if ( hpcd->Init.speed == PCD_SPEED_FULL)
  23661. 800940c: 687b ldr r3, [r7, #4]
  23662. 800940e: 68db ldr r3, [r3, #12]
  23663. 8009410: 2b02 cmp r3, #2
  23664. 8009412: d102 bne.n 800941a <HAL_PCD_ResetCallback+0x28>
  23665. {
  23666. speed = USBD_SPEED_FULL;
  23667. 8009414: 2301 movs r3, #1
  23668. 8009416: 73fb strb r3, [r7, #15]
  23669. 8009418: e001 b.n 800941e <HAL_PCD_ResetCallback+0x2c>
  23670. }
  23671. else
  23672. {
  23673. Error_Handler();
  23674. 800941a: f7f7 fea9 bl 8001170 <Error_Handler>
  23675. }
  23676. /* Set Speed. */
  23677. USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
  23678. 800941e: 687b ldr r3, [r7, #4]
  23679. 8009420: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404
  23680. 8009424: 7bfa ldrb r2, [r7, #15]
  23681. 8009426: 4611 mov r1, r2
  23682. 8009428: 4618 mov r0, r3
  23683. 800942a: f7fe fde7 bl 8007ffc <USBD_LL_SetSpeed>
  23684. /* Reset Device. */
  23685. USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
  23686. 800942e: 687b ldr r3, [r7, #4]
  23687. 8009430: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404
  23688. 8009434: 4618 mov r0, r3
  23689. 8009436: f7fe fd93 bl 8007f60 <USBD_LL_Reset>
  23690. }
  23691. 800943a: bf00 nop
  23692. 800943c: 3710 adds r7, #16
  23693. 800943e: 46bd mov sp, r7
  23694. 8009440: bd80 pop {r7, pc}
  23695. ...
  23696. 08009444 <HAL_PCD_SuspendCallback>:
  23697. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  23698. static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
  23699. #else
  23700. void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
  23701. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23702. {
  23703. 8009444: b580 push {r7, lr}
  23704. 8009446: b082 sub sp, #8
  23705. 8009448: af00 add r7, sp, #0
  23706. 800944a: 6078 str r0, [r7, #4]
  23707. /* Inform USB library that core enters in suspend Mode. */
  23708. USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
  23709. 800944c: 687b ldr r3, [r7, #4]
  23710. 800944e: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404
  23711. 8009452: 4618 mov r0, r3
  23712. 8009454: f7fe fde2 bl 800801c <USBD_LL_Suspend>
  23713. __HAL_PCD_GATE_PHYCLOCK(hpcd);
  23714. 8009458: 687b ldr r3, [r7, #4]
  23715. 800945a: 681b ldr r3, [r3, #0]
  23716. 800945c: f503 6360 add.w r3, r3, #3584 ; 0xe00
  23717. 8009460: 681b ldr r3, [r3, #0]
  23718. 8009462: 687a ldr r2, [r7, #4]
  23719. 8009464: 6812 ldr r2, [r2, #0]
  23720. 8009466: f502 6260 add.w r2, r2, #3584 ; 0xe00
  23721. 800946a: f043 0301 orr.w r3, r3, #1
  23722. 800946e: 6013 str r3, [r2, #0]
  23723. /* Enter in STOP mode. */
  23724. /* USER CODE BEGIN 2 */
  23725. if (hpcd->Init.low_power_enable)
  23726. 8009470: 687b ldr r3, [r7, #4]
  23727. 8009472: 6a1b ldr r3, [r3, #32]
  23728. 8009474: 2b00 cmp r3, #0
  23729. 8009476: d005 beq.n 8009484 <HAL_PCD_SuspendCallback+0x40>
  23730. {
  23731. /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
  23732. SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
  23733. 8009478: 4b04 ldr r3, [pc, #16] ; (800948c <HAL_PCD_SuspendCallback+0x48>)
  23734. 800947a: 691b ldr r3, [r3, #16]
  23735. 800947c: 4a03 ldr r2, [pc, #12] ; (800948c <HAL_PCD_SuspendCallback+0x48>)
  23736. 800947e: f043 0306 orr.w r3, r3, #6
  23737. 8009482: 6113 str r3, [r2, #16]
  23738. }
  23739. /* USER CODE END 2 */
  23740. }
  23741. 8009484: bf00 nop
  23742. 8009486: 3708 adds r7, #8
  23743. 8009488: 46bd mov sp, r7
  23744. 800948a: bd80 pop {r7, pc}
  23745. 800948c: e000ed00 .word 0xe000ed00
  23746. 08009490 <HAL_PCD_ResumeCallback>:
  23747. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  23748. static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
  23749. #else
  23750. void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
  23751. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23752. {
  23753. 8009490: b580 push {r7, lr}
  23754. 8009492: b082 sub sp, #8
  23755. 8009494: af00 add r7, sp, #0
  23756. 8009496: 6078 str r0, [r7, #4]
  23757. /* USER CODE BEGIN 3 */
  23758. /* USER CODE END 3 */
  23759. USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
  23760. 8009498: 687b ldr r3, [r7, #4]
  23761. 800949a: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404
  23762. 800949e: 4618 mov r0, r3
  23763. 80094a0: f7fe fdd2 bl 8008048 <USBD_LL_Resume>
  23764. }
  23765. 80094a4: bf00 nop
  23766. 80094a6: 3708 adds r7, #8
  23767. 80094a8: 46bd mov sp, r7
  23768. 80094aa: bd80 pop {r7, pc}
  23769. 080094ac <HAL_PCD_ISOOUTIncompleteCallback>:
  23770. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  23771. static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
  23772. #else
  23773. void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
  23774. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23775. {
  23776. 80094ac: b580 push {r7, lr}
  23777. 80094ae: b082 sub sp, #8
  23778. 80094b0: af00 add r7, sp, #0
  23779. 80094b2: 6078 str r0, [r7, #4]
  23780. 80094b4: 460b mov r3, r1
  23781. 80094b6: 70fb strb r3, [r7, #3]
  23782. USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
  23783. 80094b8: 687b ldr r3, [r7, #4]
  23784. 80094ba: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404
  23785. 80094be: 78fa ldrb r2, [r7, #3]
  23786. 80094c0: 4611 mov r1, r2
  23787. 80094c2: 4618 mov r0, r3
  23788. 80094c4: f7fe fe20 bl 8008108 <USBD_LL_IsoOUTIncomplete>
  23789. }
  23790. 80094c8: bf00 nop
  23791. 80094ca: 3708 adds r7, #8
  23792. 80094cc: 46bd mov sp, r7
  23793. 80094ce: bd80 pop {r7, pc}
  23794. 080094d0 <HAL_PCD_ISOINIncompleteCallback>:
  23795. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  23796. static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
  23797. #else
  23798. void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
  23799. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23800. {
  23801. 80094d0: b580 push {r7, lr}
  23802. 80094d2: b082 sub sp, #8
  23803. 80094d4: af00 add r7, sp, #0
  23804. 80094d6: 6078 str r0, [r7, #4]
  23805. 80094d8: 460b mov r3, r1
  23806. 80094da: 70fb strb r3, [r7, #3]
  23807. USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
  23808. 80094dc: 687b ldr r3, [r7, #4]
  23809. 80094de: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404
  23810. 80094e2: 78fa ldrb r2, [r7, #3]
  23811. 80094e4: 4611 mov r1, r2
  23812. 80094e6: 4618 mov r0, r3
  23813. 80094e8: f7fe fde8 bl 80080bc <USBD_LL_IsoINIncomplete>
  23814. }
  23815. 80094ec: bf00 nop
  23816. 80094ee: 3708 adds r7, #8
  23817. 80094f0: 46bd mov sp, r7
  23818. 80094f2: bd80 pop {r7, pc}
  23819. 080094f4 <HAL_PCD_ConnectCallback>:
  23820. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  23821. static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
  23822. #else
  23823. void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
  23824. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23825. {
  23826. 80094f4: b580 push {r7, lr}
  23827. 80094f6: b082 sub sp, #8
  23828. 80094f8: af00 add r7, sp, #0
  23829. 80094fa: 6078 str r0, [r7, #4]
  23830. USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
  23831. 80094fc: 687b ldr r3, [r7, #4]
  23832. 80094fe: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404
  23833. 8009502: 4618 mov r0, r3
  23834. 8009504: f7fe fe26 bl 8008154 <USBD_LL_DevConnected>
  23835. }
  23836. 8009508: bf00 nop
  23837. 800950a: 3708 adds r7, #8
  23838. 800950c: 46bd mov sp, r7
  23839. 800950e: bd80 pop {r7, pc}
  23840. 08009510 <HAL_PCD_DisconnectCallback>:
  23841. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  23842. static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
  23843. #else
  23844. void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
  23845. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23846. {
  23847. 8009510: b580 push {r7, lr}
  23848. 8009512: b082 sub sp, #8
  23849. 8009514: af00 add r7, sp, #0
  23850. 8009516: 6078 str r0, [r7, #4]
  23851. USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
  23852. 8009518: 687b ldr r3, [r7, #4]
  23853. 800951a: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404
  23854. 800951e: 4618 mov r0, r3
  23855. 8009520: f7fe fe23 bl 800816a <USBD_LL_DevDisconnected>
  23856. }
  23857. 8009524: bf00 nop
  23858. 8009526: 3708 adds r7, #8
  23859. 8009528: 46bd mov sp, r7
  23860. 800952a: bd80 pop {r7, pc}
  23861. 0800952c <USBD_LL_Init>:
  23862. * @brief Initializes the low level portion of the device driver.
  23863. * @param pdev: Device handle
  23864. * @retval USBD status
  23865. */
  23866. USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
  23867. {
  23868. 800952c: b580 push {r7, lr}
  23869. 800952e: b082 sub sp, #8
  23870. 8009530: af00 add r7, sp, #0
  23871. 8009532: 6078 str r0, [r7, #4]
  23872. /* Init USB Ip. */
  23873. if (pdev->id == DEVICE_HS) {
  23874. 8009534: 687b ldr r3, [r7, #4]
  23875. 8009536: 781b ldrb r3, [r3, #0]
  23876. 8009538: 2b01 cmp r3, #1
  23877. 800953a: d143 bne.n 80095c4 <USBD_LL_Init+0x98>
  23878. /* Link the driver to the stack. */
  23879. hpcd_USB_OTG_HS.pData = pdev;
  23880. 800953c: 4a24 ldr r2, [pc, #144] ; (80095d0 <USBD_LL_Init+0xa4>)
  23881. 800953e: 687b ldr r3, [r7, #4]
  23882. 8009540: f8c2 3404 str.w r3, [r2, #1028] ; 0x404
  23883. pdev->pData = &hpcd_USB_OTG_HS;
  23884. 8009544: 687b ldr r3, [r7, #4]
  23885. 8009546: 4a22 ldr r2, [pc, #136] ; (80095d0 <USBD_LL_Init+0xa4>)
  23886. 8009548: f8c3 22c4 str.w r2, [r3, #708] ; 0x2c4
  23887. hpcd_USB_OTG_HS.Instance = USB_OTG_HS;
  23888. 800954c: 4b20 ldr r3, [pc, #128] ; (80095d0 <USBD_LL_Init+0xa4>)
  23889. 800954e: 4a21 ldr r2, [pc, #132] ; (80095d4 <USBD_LL_Init+0xa8>)
  23890. 8009550: 601a str r2, [r3, #0]
  23891. hpcd_USB_OTG_HS.Init.dev_endpoints = 9;
  23892. 8009552: 4b1f ldr r3, [pc, #124] ; (80095d0 <USBD_LL_Init+0xa4>)
  23893. 8009554: 2209 movs r2, #9
  23894. 8009556: 605a str r2, [r3, #4]
  23895. hpcd_USB_OTG_HS.Init.speed = PCD_SPEED_FULL;
  23896. 8009558: 4b1d ldr r3, [pc, #116] ; (80095d0 <USBD_LL_Init+0xa4>)
  23897. 800955a: 2202 movs r2, #2
  23898. 800955c: 60da str r2, [r3, #12]
  23899. hpcd_USB_OTG_HS.Init.dma_enable = DISABLE;
  23900. 800955e: 4b1c ldr r3, [pc, #112] ; (80095d0 <USBD_LL_Init+0xa4>)
  23901. 8009560: 2200 movs r2, #0
  23902. 8009562: 611a str r2, [r3, #16]
  23903. hpcd_USB_OTG_HS.Init.phy_itface = USB_OTG_EMBEDDED_PHY;
  23904. 8009564: 4b1a ldr r3, [pc, #104] ; (80095d0 <USBD_LL_Init+0xa4>)
  23905. 8009566: 2202 movs r2, #2
  23906. 8009568: 619a str r2, [r3, #24]
  23907. hpcd_USB_OTG_HS.Init.Sof_enable = DISABLE;
  23908. 800956a: 4b19 ldr r3, [pc, #100] ; (80095d0 <USBD_LL_Init+0xa4>)
  23909. 800956c: 2200 movs r2, #0
  23910. 800956e: 61da str r2, [r3, #28]
  23911. hpcd_USB_OTG_HS.Init.low_power_enable = DISABLE;
  23912. 8009570: 4b17 ldr r3, [pc, #92] ; (80095d0 <USBD_LL_Init+0xa4>)
  23913. 8009572: 2200 movs r2, #0
  23914. 8009574: 621a str r2, [r3, #32]
  23915. hpcd_USB_OTG_HS.Init.lpm_enable = DISABLE;
  23916. 8009576: 4b16 ldr r3, [pc, #88] ; (80095d0 <USBD_LL_Init+0xa4>)
  23917. 8009578: 2200 movs r2, #0
  23918. 800957a: 625a str r2, [r3, #36] ; 0x24
  23919. hpcd_USB_OTG_HS.Init.battery_charging_enable = ENABLE;
  23920. 800957c: 4b14 ldr r3, [pc, #80] ; (80095d0 <USBD_LL_Init+0xa4>)
  23921. 800957e: 2201 movs r2, #1
  23922. 8009580: 629a str r2, [r3, #40] ; 0x28
  23923. hpcd_USB_OTG_HS.Init.vbus_sensing_enable = DISABLE;
  23924. 8009582: 4b13 ldr r3, [pc, #76] ; (80095d0 <USBD_LL_Init+0xa4>)
  23925. 8009584: 2200 movs r2, #0
  23926. 8009586: 62da str r2, [r3, #44] ; 0x2c
  23927. hpcd_USB_OTG_HS.Init.use_dedicated_ep1 = DISABLE;
  23928. 8009588: 4b11 ldr r3, [pc, #68] ; (80095d0 <USBD_LL_Init+0xa4>)
  23929. 800958a: 2200 movs r2, #0
  23930. 800958c: 631a str r2, [r3, #48] ; 0x30
  23931. hpcd_USB_OTG_HS.Init.use_external_vbus = DISABLE;
  23932. 800958e: 4b10 ldr r3, [pc, #64] ; (80095d0 <USBD_LL_Init+0xa4>)
  23933. 8009590: 2200 movs r2, #0
  23934. 8009592: 635a str r2, [r3, #52] ; 0x34
  23935. if (HAL_PCD_Init(&hpcd_USB_OTG_HS) != HAL_OK)
  23936. 8009594: 480e ldr r0, [pc, #56] ; (80095d0 <USBD_LL_Init+0xa4>)
  23937. 8009596: f7f8 fb7a bl 8001c8e <HAL_PCD_Init>
  23938. 800959a: 4603 mov r3, r0
  23939. 800959c: 2b00 cmp r3, #0
  23940. 800959e: d001 beq.n 80095a4 <USBD_LL_Init+0x78>
  23941. {
  23942. Error_Handler( );
  23943. 80095a0: f7f7 fde6 bl 8001170 <Error_Handler>
  23944. HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_HS, PCD_DataInStageCallback);
  23945. HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOOUTIncompleteCallback);
  23946. HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOINIncompleteCallback);
  23947. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  23948. /* USER CODE BEGIN TxRx_Configuration */
  23949. HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_HS, 0x200);
  23950. 80095a4: f44f 7100 mov.w r1, #512 ; 0x200
  23951. 80095a8: 4809 ldr r0, [pc, #36] ; (80095d0 <USBD_LL_Init+0xa4>)
  23952. 80095aa: f7f9 fcfe bl 8002faa <HAL_PCDEx_SetRxFiFo>
  23953. HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x80);
  23954. 80095ae: 2280 movs r2, #128 ; 0x80
  23955. 80095b0: 2100 movs r1, #0
  23956. 80095b2: 4807 ldr r0, [pc, #28] ; (80095d0 <USBD_LL_Init+0xa4>)
  23957. 80095b4: f7f9 fcb2 bl 8002f1c <HAL_PCDEx_SetTxFiFo>
  23958. HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x174);
  23959. 80095b8: f44f 72ba mov.w r2, #372 ; 0x174
  23960. 80095bc: 2101 movs r1, #1
  23961. 80095be: 4804 ldr r0, [pc, #16] ; (80095d0 <USBD_LL_Init+0xa4>)
  23962. 80095c0: f7f9 fcac bl 8002f1c <HAL_PCDEx_SetTxFiFo>
  23963. /* USER CODE END TxRx_Configuration */
  23964. }
  23965. return USBD_OK;
  23966. 80095c4: 2300 movs r3, #0
  23967. }
  23968. 80095c6: 4618 mov r0, r3
  23969. 80095c8: 3708 adds r7, #8
  23970. 80095ca: 46bd mov sp, r7
  23971. 80095cc: bd80 pop {r7, pc}
  23972. 80095ce: bf00 nop
  23973. 80095d0: 24002900 .word 0x24002900
  23974. 80095d4: 40040000 .word 0x40040000
  23975. 080095d8 <USBD_LL_Start>:
  23976. * @brief Starts the low level portion of the device driver.
  23977. * @param pdev: Device handle
  23978. * @retval USBD status
  23979. */
  23980. USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
  23981. {
  23982. 80095d8: b580 push {r7, lr}
  23983. 80095da: b084 sub sp, #16
  23984. 80095dc: af00 add r7, sp, #0
  23985. 80095de: 6078 str r0, [r7, #4]
  23986. HAL_StatusTypeDef hal_status = HAL_OK;
  23987. 80095e0: 2300 movs r3, #0
  23988. 80095e2: 73fb strb r3, [r7, #15]
  23989. USBD_StatusTypeDef usb_status = USBD_OK;
  23990. 80095e4: 2300 movs r3, #0
  23991. 80095e6: 73bb strb r3, [r7, #14]
  23992. hal_status = HAL_PCD_Start(pdev->pData);
  23993. 80095e8: 687b ldr r3, [r7, #4]
  23994. 80095ea: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4
  23995. 80095ee: 4618 mov r0, r3
  23996. 80095f0: f7f8 fc71 bl 8001ed6 <HAL_PCD_Start>
  23997. 80095f4: 4603 mov r3, r0
  23998. 80095f6: 73fb strb r3, [r7, #15]
  23999. usb_status = USBD_Get_USB_Status(hal_status);
  24000. 80095f8: 7bfb ldrb r3, [r7, #15]
  24001. 80095fa: 4618 mov r0, r3
  24002. 80095fc: f000 f942 bl 8009884 <USBD_Get_USB_Status>
  24003. 8009600: 4603 mov r3, r0
  24004. 8009602: 73bb strb r3, [r7, #14]
  24005. return usb_status;
  24006. 8009604: 7bbb ldrb r3, [r7, #14]
  24007. }
  24008. 8009606: 4618 mov r0, r3
  24009. 8009608: 3710 adds r7, #16
  24010. 800960a: 46bd mov sp, r7
  24011. 800960c: bd80 pop {r7, pc}
  24012. 0800960e <USBD_LL_OpenEP>:
  24013. * @param ep_type: Endpoint type
  24014. * @param ep_mps: Endpoint max packet size
  24015. * @retval USBD status
  24016. */
  24017. USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
  24018. {
  24019. 800960e: b580 push {r7, lr}
  24020. 8009610: b084 sub sp, #16
  24021. 8009612: af00 add r7, sp, #0
  24022. 8009614: 6078 str r0, [r7, #4]
  24023. 8009616: 4608 mov r0, r1
  24024. 8009618: 4611 mov r1, r2
  24025. 800961a: 461a mov r2, r3
  24026. 800961c: 4603 mov r3, r0
  24027. 800961e: 70fb strb r3, [r7, #3]
  24028. 8009620: 460b mov r3, r1
  24029. 8009622: 70bb strb r3, [r7, #2]
  24030. 8009624: 4613 mov r3, r2
  24031. 8009626: 803b strh r3, [r7, #0]
  24032. HAL_StatusTypeDef hal_status = HAL_OK;
  24033. 8009628: 2300 movs r3, #0
  24034. 800962a: 73fb strb r3, [r7, #15]
  24035. USBD_StatusTypeDef usb_status = USBD_OK;
  24036. 800962c: 2300 movs r3, #0
  24037. 800962e: 73bb strb r3, [r7, #14]
  24038. hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
  24039. 8009630: 687b ldr r3, [r7, #4]
  24040. 8009632: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4
  24041. 8009636: 78bb ldrb r3, [r7, #2]
  24042. 8009638: 883a ldrh r2, [r7, #0]
  24043. 800963a: 78f9 ldrb r1, [r7, #3]
  24044. 800963c: f7f9 f876 bl 800272c <HAL_PCD_EP_Open>
  24045. 8009640: 4603 mov r3, r0
  24046. 8009642: 73fb strb r3, [r7, #15]
  24047. usb_status = USBD_Get_USB_Status(hal_status);
  24048. 8009644: 7bfb ldrb r3, [r7, #15]
  24049. 8009646: 4618 mov r0, r3
  24050. 8009648: f000 f91c bl 8009884 <USBD_Get_USB_Status>
  24051. 800964c: 4603 mov r3, r0
  24052. 800964e: 73bb strb r3, [r7, #14]
  24053. return usb_status;
  24054. 8009650: 7bbb ldrb r3, [r7, #14]
  24055. }
  24056. 8009652: 4618 mov r0, r3
  24057. 8009654: 3710 adds r7, #16
  24058. 8009656: 46bd mov sp, r7
  24059. 8009658: bd80 pop {r7, pc}
  24060. 0800965a <USBD_LL_CloseEP>:
  24061. * @param pdev: Device handle
  24062. * @param ep_addr: Endpoint number
  24063. * @retval USBD status
  24064. */
  24065. USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
  24066. {
  24067. 800965a: b580 push {r7, lr}
  24068. 800965c: b084 sub sp, #16
  24069. 800965e: af00 add r7, sp, #0
  24070. 8009660: 6078 str r0, [r7, #4]
  24071. 8009662: 460b mov r3, r1
  24072. 8009664: 70fb strb r3, [r7, #3]
  24073. HAL_StatusTypeDef hal_status = HAL_OK;
  24074. 8009666: 2300 movs r3, #0
  24075. 8009668: 73fb strb r3, [r7, #15]
  24076. USBD_StatusTypeDef usb_status = USBD_OK;
  24077. 800966a: 2300 movs r3, #0
  24078. 800966c: 73bb strb r3, [r7, #14]
  24079. hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
  24080. 800966e: 687b ldr r3, [r7, #4]
  24081. 8009670: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4
  24082. 8009674: 78fa ldrb r2, [r7, #3]
  24083. 8009676: 4611 mov r1, r2
  24084. 8009678: 4618 mov r0, r3
  24085. 800967a: f7f9 f8bf bl 80027fc <HAL_PCD_EP_Close>
  24086. 800967e: 4603 mov r3, r0
  24087. 8009680: 73fb strb r3, [r7, #15]
  24088. usb_status = USBD_Get_USB_Status(hal_status);
  24089. 8009682: 7bfb ldrb r3, [r7, #15]
  24090. 8009684: 4618 mov r0, r3
  24091. 8009686: f000 f8fd bl 8009884 <USBD_Get_USB_Status>
  24092. 800968a: 4603 mov r3, r0
  24093. 800968c: 73bb strb r3, [r7, #14]
  24094. return usb_status;
  24095. 800968e: 7bbb ldrb r3, [r7, #14]
  24096. }
  24097. 8009690: 4618 mov r0, r3
  24098. 8009692: 3710 adds r7, #16
  24099. 8009694: 46bd mov sp, r7
  24100. 8009696: bd80 pop {r7, pc}
  24101. 08009698 <USBD_LL_StallEP>:
  24102. * @param pdev: Device handle
  24103. * @param ep_addr: Endpoint number
  24104. * @retval USBD status
  24105. */
  24106. USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
  24107. {
  24108. 8009698: b580 push {r7, lr}
  24109. 800969a: b084 sub sp, #16
  24110. 800969c: af00 add r7, sp, #0
  24111. 800969e: 6078 str r0, [r7, #4]
  24112. 80096a0: 460b mov r3, r1
  24113. 80096a2: 70fb strb r3, [r7, #3]
  24114. HAL_StatusTypeDef hal_status = HAL_OK;
  24115. 80096a4: 2300 movs r3, #0
  24116. 80096a6: 73fb strb r3, [r7, #15]
  24117. USBD_StatusTypeDef usb_status = USBD_OK;
  24118. 80096a8: 2300 movs r3, #0
  24119. 80096aa: 73bb strb r3, [r7, #14]
  24120. hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
  24121. 80096ac: 687b ldr r3, [r7, #4]
  24122. 80096ae: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4
  24123. 80096b2: 78fa ldrb r2, [r7, #3]
  24124. 80096b4: 4611 mov r1, r2
  24125. 80096b6: 4618 mov r0, r3
  24126. 80096b8: f7f9 f997 bl 80029ea <HAL_PCD_EP_SetStall>
  24127. 80096bc: 4603 mov r3, r0
  24128. 80096be: 73fb strb r3, [r7, #15]
  24129. usb_status = USBD_Get_USB_Status(hal_status);
  24130. 80096c0: 7bfb ldrb r3, [r7, #15]
  24131. 80096c2: 4618 mov r0, r3
  24132. 80096c4: f000 f8de bl 8009884 <USBD_Get_USB_Status>
  24133. 80096c8: 4603 mov r3, r0
  24134. 80096ca: 73bb strb r3, [r7, #14]
  24135. return usb_status;
  24136. 80096cc: 7bbb ldrb r3, [r7, #14]
  24137. }
  24138. 80096ce: 4618 mov r0, r3
  24139. 80096d0: 3710 adds r7, #16
  24140. 80096d2: 46bd mov sp, r7
  24141. 80096d4: bd80 pop {r7, pc}
  24142. 080096d6 <USBD_LL_ClearStallEP>:
  24143. * @param pdev: Device handle
  24144. * @param ep_addr: Endpoint number
  24145. * @retval USBD status
  24146. */
  24147. USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
  24148. {
  24149. 80096d6: b580 push {r7, lr}
  24150. 80096d8: b084 sub sp, #16
  24151. 80096da: af00 add r7, sp, #0
  24152. 80096dc: 6078 str r0, [r7, #4]
  24153. 80096de: 460b mov r3, r1
  24154. 80096e0: 70fb strb r3, [r7, #3]
  24155. HAL_StatusTypeDef hal_status = HAL_OK;
  24156. 80096e2: 2300 movs r3, #0
  24157. 80096e4: 73fb strb r3, [r7, #15]
  24158. USBD_StatusTypeDef usb_status = USBD_OK;
  24159. 80096e6: 2300 movs r3, #0
  24160. 80096e8: 73bb strb r3, [r7, #14]
  24161. hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
  24162. 80096ea: 687b ldr r3, [r7, #4]
  24163. 80096ec: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4
  24164. 80096f0: 78fa ldrb r2, [r7, #3]
  24165. 80096f2: 4611 mov r1, r2
  24166. 80096f4: 4618 mov r0, r3
  24167. 80096f6: f7f9 f9dc bl 8002ab2 <HAL_PCD_EP_ClrStall>
  24168. 80096fa: 4603 mov r3, r0
  24169. 80096fc: 73fb strb r3, [r7, #15]
  24170. usb_status = USBD_Get_USB_Status(hal_status);
  24171. 80096fe: 7bfb ldrb r3, [r7, #15]
  24172. 8009700: 4618 mov r0, r3
  24173. 8009702: f000 f8bf bl 8009884 <USBD_Get_USB_Status>
  24174. 8009706: 4603 mov r3, r0
  24175. 8009708: 73bb strb r3, [r7, #14]
  24176. return usb_status;
  24177. 800970a: 7bbb ldrb r3, [r7, #14]
  24178. }
  24179. 800970c: 4618 mov r0, r3
  24180. 800970e: 3710 adds r7, #16
  24181. 8009710: 46bd mov sp, r7
  24182. 8009712: bd80 pop {r7, pc}
  24183. 08009714 <USBD_LL_IsStallEP>:
  24184. * @param pdev: Device handle
  24185. * @param ep_addr: Endpoint number
  24186. * @retval Stall (1: Yes, 0: No)
  24187. */
  24188. uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
  24189. {
  24190. 8009714: b480 push {r7}
  24191. 8009716: b085 sub sp, #20
  24192. 8009718: af00 add r7, sp, #0
  24193. 800971a: 6078 str r0, [r7, #4]
  24194. 800971c: 460b mov r3, r1
  24195. 800971e: 70fb strb r3, [r7, #3]
  24196. PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
  24197. 8009720: 687b ldr r3, [r7, #4]
  24198. 8009722: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4
  24199. 8009726: 60fb str r3, [r7, #12]
  24200. if((ep_addr & 0x80) == 0x80)
  24201. 8009728: f997 3003 ldrsb.w r3, [r7, #3]
  24202. 800972c: 2b00 cmp r3, #0
  24203. 800972e: da0b bge.n 8009748 <USBD_LL_IsStallEP+0x34>
  24204. {
  24205. return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
  24206. 8009730: 78fb ldrb r3, [r7, #3]
  24207. 8009732: f003 027f and.w r2, r3, #127 ; 0x7f
  24208. 8009736: 68f9 ldr r1, [r7, #12]
  24209. 8009738: 4613 mov r3, r2
  24210. 800973a: 00db lsls r3, r3, #3
  24211. 800973c: 1a9b subs r3, r3, r2
  24212. 800973e: 009b lsls r3, r3, #2
  24213. 8009740: 440b add r3, r1
  24214. 8009742: 333e adds r3, #62 ; 0x3e
  24215. 8009744: 781b ldrb r3, [r3, #0]
  24216. 8009746: e00b b.n 8009760 <USBD_LL_IsStallEP+0x4c>
  24217. }
  24218. else
  24219. {
  24220. return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
  24221. 8009748: 78fb ldrb r3, [r7, #3]
  24222. 800974a: f003 027f and.w r2, r3, #127 ; 0x7f
  24223. 800974e: 68f9 ldr r1, [r7, #12]
  24224. 8009750: 4613 mov r3, r2
  24225. 8009752: 00db lsls r3, r3, #3
  24226. 8009754: 1a9b subs r3, r3, r2
  24227. 8009756: 009b lsls r3, r3, #2
  24228. 8009758: 440b add r3, r1
  24229. 800975a: f503 73ff add.w r3, r3, #510 ; 0x1fe
  24230. 800975e: 781b ldrb r3, [r3, #0]
  24231. }
  24232. }
  24233. 8009760: 4618 mov r0, r3
  24234. 8009762: 3714 adds r7, #20
  24235. 8009764: 46bd mov sp, r7
  24236. 8009766: f85d 7b04 ldr.w r7, [sp], #4
  24237. 800976a: 4770 bx lr
  24238. 0800976c <USBD_LL_SetUSBAddress>:
  24239. * @param pdev: Device handle
  24240. * @param dev_addr: Device address
  24241. * @retval USBD status
  24242. */
  24243. USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
  24244. {
  24245. 800976c: b580 push {r7, lr}
  24246. 800976e: b084 sub sp, #16
  24247. 8009770: af00 add r7, sp, #0
  24248. 8009772: 6078 str r0, [r7, #4]
  24249. 8009774: 460b mov r3, r1
  24250. 8009776: 70fb strb r3, [r7, #3]
  24251. HAL_StatusTypeDef hal_status = HAL_OK;
  24252. 8009778: 2300 movs r3, #0
  24253. 800977a: 73fb strb r3, [r7, #15]
  24254. USBD_StatusTypeDef usb_status = USBD_OK;
  24255. 800977c: 2300 movs r3, #0
  24256. 800977e: 73bb strb r3, [r7, #14]
  24257. hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
  24258. 8009780: 687b ldr r3, [r7, #4]
  24259. 8009782: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4
  24260. 8009786: 78fa ldrb r2, [r7, #3]
  24261. 8009788: 4611 mov r1, r2
  24262. 800978a: 4618 mov r0, r3
  24263. 800978c: f7f8 ffa9 bl 80026e2 <HAL_PCD_SetAddress>
  24264. 8009790: 4603 mov r3, r0
  24265. 8009792: 73fb strb r3, [r7, #15]
  24266. usb_status = USBD_Get_USB_Status(hal_status);
  24267. 8009794: 7bfb ldrb r3, [r7, #15]
  24268. 8009796: 4618 mov r0, r3
  24269. 8009798: f000 f874 bl 8009884 <USBD_Get_USB_Status>
  24270. 800979c: 4603 mov r3, r0
  24271. 800979e: 73bb strb r3, [r7, #14]
  24272. return usb_status;
  24273. 80097a0: 7bbb ldrb r3, [r7, #14]
  24274. }
  24275. 80097a2: 4618 mov r0, r3
  24276. 80097a4: 3710 adds r7, #16
  24277. 80097a6: 46bd mov sp, r7
  24278. 80097a8: bd80 pop {r7, pc}
  24279. 080097aa <USBD_LL_Transmit>:
  24280. * @param pbuf: Pointer to data to be sent
  24281. * @param size: Data size
  24282. * @retval USBD status
  24283. */
  24284. USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
  24285. {
  24286. 80097aa: b580 push {r7, lr}
  24287. 80097ac: b086 sub sp, #24
  24288. 80097ae: af00 add r7, sp, #0
  24289. 80097b0: 60f8 str r0, [r7, #12]
  24290. 80097b2: 607a str r2, [r7, #4]
  24291. 80097b4: 603b str r3, [r7, #0]
  24292. 80097b6: 460b mov r3, r1
  24293. 80097b8: 72fb strb r3, [r7, #11]
  24294. HAL_StatusTypeDef hal_status = HAL_OK;
  24295. 80097ba: 2300 movs r3, #0
  24296. 80097bc: 75fb strb r3, [r7, #23]
  24297. USBD_StatusTypeDef usb_status = USBD_OK;
  24298. 80097be: 2300 movs r3, #0
  24299. 80097c0: 75bb strb r3, [r7, #22]
  24300. hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
  24301. 80097c2: 68fb ldr r3, [r7, #12]
  24302. 80097c4: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4
  24303. 80097c8: 7af9 ldrb r1, [r7, #11]
  24304. 80097ca: 683b ldr r3, [r7, #0]
  24305. 80097cc: 687a ldr r2, [r7, #4]
  24306. 80097ce: f7f9 f8c2 bl 8002956 <HAL_PCD_EP_Transmit>
  24307. 80097d2: 4603 mov r3, r0
  24308. 80097d4: 75fb strb r3, [r7, #23]
  24309. usb_status = USBD_Get_USB_Status(hal_status);
  24310. 80097d6: 7dfb ldrb r3, [r7, #23]
  24311. 80097d8: 4618 mov r0, r3
  24312. 80097da: f000 f853 bl 8009884 <USBD_Get_USB_Status>
  24313. 80097de: 4603 mov r3, r0
  24314. 80097e0: 75bb strb r3, [r7, #22]
  24315. return usb_status;
  24316. 80097e2: 7dbb ldrb r3, [r7, #22]
  24317. }
  24318. 80097e4: 4618 mov r0, r3
  24319. 80097e6: 3718 adds r7, #24
  24320. 80097e8: 46bd mov sp, r7
  24321. 80097ea: bd80 pop {r7, pc}
  24322. 080097ec <USBD_LL_PrepareReceive>:
  24323. * @param pbuf: Pointer to data to be received
  24324. * @param size: Data size
  24325. * @retval USBD status
  24326. */
  24327. USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
  24328. {
  24329. 80097ec: b580 push {r7, lr}
  24330. 80097ee: b086 sub sp, #24
  24331. 80097f0: af00 add r7, sp, #0
  24332. 80097f2: 60f8 str r0, [r7, #12]
  24333. 80097f4: 607a str r2, [r7, #4]
  24334. 80097f6: 603b str r3, [r7, #0]
  24335. 80097f8: 460b mov r3, r1
  24336. 80097fa: 72fb strb r3, [r7, #11]
  24337. HAL_StatusTypeDef hal_status = HAL_OK;
  24338. 80097fc: 2300 movs r3, #0
  24339. 80097fe: 75fb strb r3, [r7, #23]
  24340. USBD_StatusTypeDef usb_status = USBD_OK;
  24341. 8009800: 2300 movs r3, #0
  24342. 8009802: 75bb strb r3, [r7, #22]
  24343. hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
  24344. 8009804: 68fb ldr r3, [r7, #12]
  24345. 8009806: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4
  24346. 800980a: 7af9 ldrb r1, [r7, #11]
  24347. 800980c: 683b ldr r3, [r7, #0]
  24348. 800980e: 687a ldr r2, [r7, #4]
  24349. 8009810: f7f9 f83e bl 8002890 <HAL_PCD_EP_Receive>
  24350. 8009814: 4603 mov r3, r0
  24351. 8009816: 75fb strb r3, [r7, #23]
  24352. usb_status = USBD_Get_USB_Status(hal_status);
  24353. 8009818: 7dfb ldrb r3, [r7, #23]
  24354. 800981a: 4618 mov r0, r3
  24355. 800981c: f000 f832 bl 8009884 <USBD_Get_USB_Status>
  24356. 8009820: 4603 mov r3, r0
  24357. 8009822: 75bb strb r3, [r7, #22]
  24358. return usb_status;
  24359. 8009824: 7dbb ldrb r3, [r7, #22]
  24360. }
  24361. 8009826: 4618 mov r0, r3
  24362. 8009828: 3718 adds r7, #24
  24363. 800982a: 46bd mov sp, r7
  24364. 800982c: bd80 pop {r7, pc}
  24365. 0800982e <USBD_LL_GetRxDataSize>:
  24366. * @param pdev: Device handle
  24367. * @param ep_addr: Endpoint number
  24368. * @retval Received Data Size
  24369. */
  24370. uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
  24371. {
  24372. 800982e: b580 push {r7, lr}
  24373. 8009830: b082 sub sp, #8
  24374. 8009832: af00 add r7, sp, #0
  24375. 8009834: 6078 str r0, [r7, #4]
  24376. 8009836: 460b mov r3, r1
  24377. 8009838: 70fb strb r3, [r7, #3]
  24378. return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
  24379. 800983a: 687b ldr r3, [r7, #4]
  24380. 800983c: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4
  24381. 8009840: 78fa ldrb r2, [r7, #3]
  24382. 8009842: 4611 mov r1, r2
  24383. 8009844: 4618 mov r0, r3
  24384. 8009846: f7f9 f86e bl 8002926 <HAL_PCD_EP_GetRxCount>
  24385. 800984a: 4603 mov r3, r0
  24386. }
  24387. 800984c: 4618 mov r0, r3
  24388. 800984e: 3708 adds r7, #8
  24389. 8009850: 46bd mov sp, r7
  24390. 8009852: bd80 pop {r7, pc}
  24391. 08009854 <USBD_static_malloc>:
  24392. * @brief Static single allocation.
  24393. * @param size: Size of allocated memory
  24394. * @retval None
  24395. */
  24396. void *USBD_static_malloc(uint32_t size)
  24397. {
  24398. 8009854: b480 push {r7}
  24399. 8009856: b083 sub sp, #12
  24400. 8009858: af00 add r7, sp, #0
  24401. 800985a: 6078 str r0, [r7, #4]
  24402. static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */
  24403. return mem;
  24404. 800985c: 4b03 ldr r3, [pc, #12] ; (800986c <USBD_static_malloc+0x18>)
  24405. }
  24406. 800985e: 4618 mov r0, r3
  24407. 8009860: 370c adds r7, #12
  24408. 8009862: 46bd mov sp, r7
  24409. 8009864: f85d 7b04 ldr.w r7, [sp], #4
  24410. 8009868: 4770 bx lr
  24411. 800986a: bf00 nop
  24412. 800986c: 240011b8 .word 0x240011b8
  24413. 08009870 <USBD_static_free>:
  24414. * @brief Dummy memory free
  24415. * @param p: Pointer to allocated memory address
  24416. * @retval None
  24417. */
  24418. void USBD_static_free(void *p)
  24419. {
  24420. 8009870: b480 push {r7}
  24421. 8009872: b083 sub sp, #12
  24422. 8009874: af00 add r7, sp, #0
  24423. 8009876: 6078 str r0, [r7, #4]
  24424. }
  24425. 8009878: bf00 nop
  24426. 800987a: 370c adds r7, #12
  24427. 800987c: 46bd mov sp, r7
  24428. 800987e: f85d 7b04 ldr.w r7, [sp], #4
  24429. 8009882: 4770 bx lr
  24430. 08009884 <USBD_Get_USB_Status>:
  24431. * @brief Returns the USB status depending on the HAL status:
  24432. * @param hal_status: HAL status
  24433. * @retval USB status
  24434. */
  24435. USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
  24436. {
  24437. 8009884: b480 push {r7}
  24438. 8009886: b085 sub sp, #20
  24439. 8009888: af00 add r7, sp, #0
  24440. 800988a: 4603 mov r3, r0
  24441. 800988c: 71fb strb r3, [r7, #7]
  24442. USBD_StatusTypeDef usb_status = USBD_OK;
  24443. 800988e: 2300 movs r3, #0
  24444. 8009890: 73fb strb r3, [r7, #15]
  24445. switch (hal_status)
  24446. 8009892: 79fb ldrb r3, [r7, #7]
  24447. 8009894: 2b03 cmp r3, #3
  24448. 8009896: d817 bhi.n 80098c8 <USBD_Get_USB_Status+0x44>
  24449. 8009898: a201 add r2, pc, #4 ; (adr r2, 80098a0 <USBD_Get_USB_Status+0x1c>)
  24450. 800989a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  24451. 800989e: bf00 nop
  24452. 80098a0: 080098b1 .word 0x080098b1
  24453. 80098a4: 080098b7 .word 0x080098b7
  24454. 80098a8: 080098bd .word 0x080098bd
  24455. 80098ac: 080098c3 .word 0x080098c3
  24456. {
  24457. case HAL_OK :
  24458. usb_status = USBD_OK;
  24459. 80098b0: 2300 movs r3, #0
  24460. 80098b2: 73fb strb r3, [r7, #15]
  24461. break;
  24462. 80098b4: e00b b.n 80098ce <USBD_Get_USB_Status+0x4a>
  24463. case HAL_ERROR :
  24464. usb_status = USBD_FAIL;
  24465. 80098b6: 2303 movs r3, #3
  24466. 80098b8: 73fb strb r3, [r7, #15]
  24467. break;
  24468. 80098ba: e008 b.n 80098ce <USBD_Get_USB_Status+0x4a>
  24469. case HAL_BUSY :
  24470. usb_status = USBD_BUSY;
  24471. 80098bc: 2301 movs r3, #1
  24472. 80098be: 73fb strb r3, [r7, #15]
  24473. break;
  24474. 80098c0: e005 b.n 80098ce <USBD_Get_USB_Status+0x4a>
  24475. case HAL_TIMEOUT :
  24476. usb_status = USBD_FAIL;
  24477. 80098c2: 2303 movs r3, #3
  24478. 80098c4: 73fb strb r3, [r7, #15]
  24479. break;
  24480. 80098c6: e002 b.n 80098ce <USBD_Get_USB_Status+0x4a>
  24481. default :
  24482. usb_status = USBD_FAIL;
  24483. 80098c8: 2303 movs r3, #3
  24484. 80098ca: 73fb strb r3, [r7, #15]
  24485. break;
  24486. 80098cc: bf00 nop
  24487. }
  24488. return usb_status;
  24489. 80098ce: 7bfb ldrb r3, [r7, #15]
  24490. }
  24491. 80098d0: 4618 mov r0, r3
  24492. 80098d2: 3714 adds r7, #20
  24493. 80098d4: 46bd mov sp, r7
  24494. 80098d6: f85d 7b04 ldr.w r7, [sp], #4
  24495. 80098da: 4770 bx lr
  24496. 080098dc <__assert_func>:
  24497. 80098dc: b51f push {r0, r1, r2, r3, r4, lr}
  24498. 80098de: 4614 mov r4, r2
  24499. 80098e0: 461a mov r2, r3
  24500. 80098e2: 4b09 ldr r3, [pc, #36] ; (8009908 <__assert_func+0x2c>)
  24501. 80098e4: 681b ldr r3, [r3, #0]
  24502. 80098e6: 4605 mov r5, r0
  24503. 80098e8: 68d8 ldr r0, [r3, #12]
  24504. 80098ea: b14c cbz r4, 8009900 <__assert_func+0x24>
  24505. 80098ec: 4b07 ldr r3, [pc, #28] ; (800990c <__assert_func+0x30>)
  24506. 80098ee: 9100 str r1, [sp, #0]
  24507. 80098f0: e9cd 3401 strd r3, r4, [sp, #4]
  24508. 80098f4: 4906 ldr r1, [pc, #24] ; (8009910 <__assert_func+0x34>)
  24509. 80098f6: 462b mov r3, r5
  24510. 80098f8: f000 f814 bl 8009924 <fiprintf>
  24511. 80098fc: f000 fbfe bl 800a0fc <abort>
  24512. 8009900: 4b04 ldr r3, [pc, #16] ; (8009914 <__assert_func+0x38>)
  24513. 8009902: 461c mov r4, r3
  24514. 8009904: e7f3 b.n 80098ee <__assert_func+0x12>
  24515. 8009906: bf00 nop
  24516. 8009908: 24000184 .word 0x24000184
  24517. 800990c: 0800aa20 .word 0x0800aa20
  24518. 8009910: 0800aa2d .word 0x0800aa2d
  24519. 8009914: 0800aa5b .word 0x0800aa5b
  24520. 08009918 <__errno>:
  24521. 8009918: 4b01 ldr r3, [pc, #4] ; (8009920 <__errno+0x8>)
  24522. 800991a: 6818 ldr r0, [r3, #0]
  24523. 800991c: 4770 bx lr
  24524. 800991e: bf00 nop
  24525. 8009920: 24000184 .word 0x24000184
  24526. 08009924 <fiprintf>:
  24527. 8009924: b40e push {r1, r2, r3}
  24528. 8009926: b503 push {r0, r1, lr}
  24529. 8009928: 4601 mov r1, r0
  24530. 800992a: ab03 add r3, sp, #12
  24531. 800992c: 4805 ldr r0, [pc, #20] ; (8009944 <fiprintf+0x20>)
  24532. 800992e: f853 2b04 ldr.w r2, [r3], #4
  24533. 8009932: 6800 ldr r0, [r0, #0]
  24534. 8009934: 9301 str r3, [sp, #4]
  24535. 8009936: f000 f85d bl 80099f4 <_vfiprintf_r>
  24536. 800993a: b002 add sp, #8
  24537. 800993c: f85d eb04 ldr.w lr, [sp], #4
  24538. 8009940: b003 add sp, #12
  24539. 8009942: 4770 bx lr
  24540. 8009944: 24000184 .word 0x24000184
  24541. 08009948 <__libc_init_array>:
  24542. 8009948: b570 push {r4, r5, r6, lr}
  24543. 800994a: 4d0d ldr r5, [pc, #52] ; (8009980 <__libc_init_array+0x38>)
  24544. 800994c: 4c0d ldr r4, [pc, #52] ; (8009984 <__libc_init_array+0x3c>)
  24545. 800994e: 1b64 subs r4, r4, r5
  24546. 8009950: 10a4 asrs r4, r4, #2
  24547. 8009952: 2600 movs r6, #0
  24548. 8009954: 42a6 cmp r6, r4
  24549. 8009956: d109 bne.n 800996c <__libc_init_array+0x24>
  24550. 8009958: 4d0b ldr r5, [pc, #44] ; (8009988 <__libc_init_array+0x40>)
  24551. 800995a: 4c0c ldr r4, [pc, #48] ; (800998c <__libc_init_array+0x44>)
  24552. 800995c: f000 ffaa bl 800a8b4 <_init>
  24553. 8009960: 1b64 subs r4, r4, r5
  24554. 8009962: 10a4 asrs r4, r4, #2
  24555. 8009964: 2600 movs r6, #0
  24556. 8009966: 42a6 cmp r6, r4
  24557. 8009968: d105 bne.n 8009976 <__libc_init_array+0x2e>
  24558. 800996a: bd70 pop {r4, r5, r6, pc}
  24559. 800996c: f855 3b04 ldr.w r3, [r5], #4
  24560. 8009970: 4798 blx r3
  24561. 8009972: 3601 adds r6, #1
  24562. 8009974: e7ee b.n 8009954 <__libc_init_array+0xc>
  24563. 8009976: f855 3b04 ldr.w r3, [r5], #4
  24564. 800997a: 4798 blx r3
  24565. 800997c: 3601 adds r6, #1
  24566. 800997e: e7f2 b.n 8009966 <__libc_init_array+0x1e>
  24567. 8009980: 0800aaf4 .word 0x0800aaf4
  24568. 8009984: 0800aaf4 .word 0x0800aaf4
  24569. 8009988: 0800aaf4 .word 0x0800aaf4
  24570. 800998c: 0800aaf8 .word 0x0800aaf8
  24571. 08009990 <memset>:
  24572. 8009990: 4402 add r2, r0
  24573. 8009992: 4603 mov r3, r0
  24574. 8009994: 4293 cmp r3, r2
  24575. 8009996: d100 bne.n 800999a <memset+0xa>
  24576. 8009998: 4770 bx lr
  24577. 800999a: f803 1b01 strb.w r1, [r3], #1
  24578. 800999e: e7f9 b.n 8009994 <memset+0x4>
  24579. 080099a0 <__sfputc_r>:
  24580. 80099a0: 6893 ldr r3, [r2, #8]
  24581. 80099a2: 3b01 subs r3, #1
  24582. 80099a4: 2b00 cmp r3, #0
  24583. 80099a6: b410 push {r4}
  24584. 80099a8: 6093 str r3, [r2, #8]
  24585. 80099aa: da08 bge.n 80099be <__sfputc_r+0x1e>
  24586. 80099ac: 6994 ldr r4, [r2, #24]
  24587. 80099ae: 42a3 cmp r3, r4
  24588. 80099b0: db01 blt.n 80099b6 <__sfputc_r+0x16>
  24589. 80099b2: 290a cmp r1, #10
  24590. 80099b4: d103 bne.n 80099be <__sfputc_r+0x1e>
  24591. 80099b6: f85d 4b04 ldr.w r4, [sp], #4
  24592. 80099ba: f000 badf b.w 8009f7c <__swbuf_r>
  24593. 80099be: 6813 ldr r3, [r2, #0]
  24594. 80099c0: 1c58 adds r0, r3, #1
  24595. 80099c2: 6010 str r0, [r2, #0]
  24596. 80099c4: 7019 strb r1, [r3, #0]
  24597. 80099c6: 4608 mov r0, r1
  24598. 80099c8: f85d 4b04 ldr.w r4, [sp], #4
  24599. 80099cc: 4770 bx lr
  24600. 080099ce <__sfputs_r>:
  24601. 80099ce: b5f8 push {r3, r4, r5, r6, r7, lr}
  24602. 80099d0: 4606 mov r6, r0
  24603. 80099d2: 460f mov r7, r1
  24604. 80099d4: 4614 mov r4, r2
  24605. 80099d6: 18d5 adds r5, r2, r3
  24606. 80099d8: 42ac cmp r4, r5
  24607. 80099da: d101 bne.n 80099e0 <__sfputs_r+0x12>
  24608. 80099dc: 2000 movs r0, #0
  24609. 80099de: e007 b.n 80099f0 <__sfputs_r+0x22>
  24610. 80099e0: f814 1b01 ldrb.w r1, [r4], #1
  24611. 80099e4: 463a mov r2, r7
  24612. 80099e6: 4630 mov r0, r6
  24613. 80099e8: f7ff ffda bl 80099a0 <__sfputc_r>
  24614. 80099ec: 1c43 adds r3, r0, #1
  24615. 80099ee: d1f3 bne.n 80099d8 <__sfputs_r+0xa>
  24616. 80099f0: bdf8 pop {r3, r4, r5, r6, r7, pc}
  24617. ...
  24618. 080099f4 <_vfiprintf_r>:
  24619. 80099f4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  24620. 80099f8: 460d mov r5, r1
  24621. 80099fa: b09d sub sp, #116 ; 0x74
  24622. 80099fc: 4614 mov r4, r2
  24623. 80099fe: 4698 mov r8, r3
  24624. 8009a00: 4606 mov r6, r0
  24625. 8009a02: b118 cbz r0, 8009a0c <_vfiprintf_r+0x18>
  24626. 8009a04: 6983 ldr r3, [r0, #24]
  24627. 8009a06: b90b cbnz r3, 8009a0c <_vfiprintf_r+0x18>
  24628. 8009a08: f000 fc9a bl 800a340 <__sinit>
  24629. 8009a0c: 4b89 ldr r3, [pc, #548] ; (8009c34 <_vfiprintf_r+0x240>)
  24630. 8009a0e: 429d cmp r5, r3
  24631. 8009a10: d11b bne.n 8009a4a <_vfiprintf_r+0x56>
  24632. 8009a12: 6875 ldr r5, [r6, #4]
  24633. 8009a14: 6e6b ldr r3, [r5, #100] ; 0x64
  24634. 8009a16: 07d9 lsls r1, r3, #31
  24635. 8009a18: d405 bmi.n 8009a26 <_vfiprintf_r+0x32>
  24636. 8009a1a: 89ab ldrh r3, [r5, #12]
  24637. 8009a1c: 059a lsls r2, r3, #22
  24638. 8009a1e: d402 bmi.n 8009a26 <_vfiprintf_r+0x32>
  24639. 8009a20: 6da8 ldr r0, [r5, #88] ; 0x58
  24640. 8009a22: f000 fd2b bl 800a47c <__retarget_lock_acquire_recursive>
  24641. 8009a26: 89ab ldrh r3, [r5, #12]
  24642. 8009a28: 071b lsls r3, r3, #28
  24643. 8009a2a: d501 bpl.n 8009a30 <_vfiprintf_r+0x3c>
  24644. 8009a2c: 692b ldr r3, [r5, #16]
  24645. 8009a2e: b9eb cbnz r3, 8009a6c <_vfiprintf_r+0x78>
  24646. 8009a30: 4629 mov r1, r5
  24647. 8009a32: 4630 mov r0, r6
  24648. 8009a34: f000 faf4 bl 800a020 <__swsetup_r>
  24649. 8009a38: b1c0 cbz r0, 8009a6c <_vfiprintf_r+0x78>
  24650. 8009a3a: 6e6b ldr r3, [r5, #100] ; 0x64
  24651. 8009a3c: 07dc lsls r4, r3, #31
  24652. 8009a3e: d50e bpl.n 8009a5e <_vfiprintf_r+0x6a>
  24653. 8009a40: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
  24654. 8009a44: b01d add sp, #116 ; 0x74
  24655. 8009a46: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  24656. 8009a4a: 4b7b ldr r3, [pc, #492] ; (8009c38 <_vfiprintf_r+0x244>)
  24657. 8009a4c: 429d cmp r5, r3
  24658. 8009a4e: d101 bne.n 8009a54 <_vfiprintf_r+0x60>
  24659. 8009a50: 68b5 ldr r5, [r6, #8]
  24660. 8009a52: e7df b.n 8009a14 <_vfiprintf_r+0x20>
  24661. 8009a54: 4b79 ldr r3, [pc, #484] ; (8009c3c <_vfiprintf_r+0x248>)
  24662. 8009a56: 429d cmp r5, r3
  24663. 8009a58: bf08 it eq
  24664. 8009a5a: 68f5 ldreq r5, [r6, #12]
  24665. 8009a5c: e7da b.n 8009a14 <_vfiprintf_r+0x20>
  24666. 8009a5e: 89ab ldrh r3, [r5, #12]
  24667. 8009a60: 0598 lsls r0, r3, #22
  24668. 8009a62: d4ed bmi.n 8009a40 <_vfiprintf_r+0x4c>
  24669. 8009a64: 6da8 ldr r0, [r5, #88] ; 0x58
  24670. 8009a66: f000 fd0a bl 800a47e <__retarget_lock_release_recursive>
  24671. 8009a6a: e7e9 b.n 8009a40 <_vfiprintf_r+0x4c>
  24672. 8009a6c: 2300 movs r3, #0
  24673. 8009a6e: 9309 str r3, [sp, #36] ; 0x24
  24674. 8009a70: 2320 movs r3, #32
  24675. 8009a72: f88d 3029 strb.w r3, [sp, #41] ; 0x29
  24676. 8009a76: f8cd 800c str.w r8, [sp, #12]
  24677. 8009a7a: 2330 movs r3, #48 ; 0x30
  24678. 8009a7c: f8df 81c0 ldr.w r8, [pc, #448] ; 8009c40 <_vfiprintf_r+0x24c>
  24679. 8009a80: f88d 302a strb.w r3, [sp, #42] ; 0x2a
  24680. 8009a84: f04f 0901 mov.w r9, #1
  24681. 8009a88: 4623 mov r3, r4
  24682. 8009a8a: 469a mov sl, r3
  24683. 8009a8c: f813 2b01 ldrb.w r2, [r3], #1
  24684. 8009a90: b10a cbz r2, 8009a96 <_vfiprintf_r+0xa2>
  24685. 8009a92: 2a25 cmp r2, #37 ; 0x25
  24686. 8009a94: d1f9 bne.n 8009a8a <_vfiprintf_r+0x96>
  24687. 8009a96: ebba 0b04 subs.w fp, sl, r4
  24688. 8009a9a: d00b beq.n 8009ab4 <_vfiprintf_r+0xc0>
  24689. 8009a9c: 465b mov r3, fp
  24690. 8009a9e: 4622 mov r2, r4
  24691. 8009aa0: 4629 mov r1, r5
  24692. 8009aa2: 4630 mov r0, r6
  24693. 8009aa4: f7ff ff93 bl 80099ce <__sfputs_r>
  24694. 8009aa8: 3001 adds r0, #1
  24695. 8009aaa: f000 80aa beq.w 8009c02 <_vfiprintf_r+0x20e>
  24696. 8009aae: 9a09 ldr r2, [sp, #36] ; 0x24
  24697. 8009ab0: 445a add r2, fp
  24698. 8009ab2: 9209 str r2, [sp, #36] ; 0x24
  24699. 8009ab4: f89a 3000 ldrb.w r3, [sl]
  24700. 8009ab8: 2b00 cmp r3, #0
  24701. 8009aba: f000 80a2 beq.w 8009c02 <_vfiprintf_r+0x20e>
  24702. 8009abe: 2300 movs r3, #0
  24703. 8009ac0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
  24704. 8009ac4: e9cd 2305 strd r2, r3, [sp, #20]
  24705. 8009ac8: f10a 0a01 add.w sl, sl, #1
  24706. 8009acc: 9304 str r3, [sp, #16]
  24707. 8009ace: 9307 str r3, [sp, #28]
  24708. 8009ad0: f88d 3053 strb.w r3, [sp, #83] ; 0x53
  24709. 8009ad4: 931a str r3, [sp, #104] ; 0x68
  24710. 8009ad6: 4654 mov r4, sl
  24711. 8009ad8: 2205 movs r2, #5
  24712. 8009ada: f814 1b01 ldrb.w r1, [r4], #1
  24713. 8009ade: 4858 ldr r0, [pc, #352] ; (8009c40 <_vfiprintf_r+0x24c>)
  24714. 8009ae0: f7f6 fc16 bl 8000310 <memchr>
  24715. 8009ae4: 9a04 ldr r2, [sp, #16]
  24716. 8009ae6: b9d8 cbnz r0, 8009b20 <_vfiprintf_r+0x12c>
  24717. 8009ae8: 06d1 lsls r1, r2, #27
  24718. 8009aea: bf44 itt mi
  24719. 8009aec: 2320 movmi r3, #32
  24720. 8009aee: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
  24721. 8009af2: 0713 lsls r3, r2, #28
  24722. 8009af4: bf44 itt mi
  24723. 8009af6: 232b movmi r3, #43 ; 0x2b
  24724. 8009af8: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
  24725. 8009afc: f89a 3000 ldrb.w r3, [sl]
  24726. 8009b00: 2b2a cmp r3, #42 ; 0x2a
  24727. 8009b02: d015 beq.n 8009b30 <_vfiprintf_r+0x13c>
  24728. 8009b04: 9a07 ldr r2, [sp, #28]
  24729. 8009b06: 4654 mov r4, sl
  24730. 8009b08: 2000 movs r0, #0
  24731. 8009b0a: f04f 0c0a mov.w ip, #10
  24732. 8009b0e: 4621 mov r1, r4
  24733. 8009b10: f811 3b01 ldrb.w r3, [r1], #1
  24734. 8009b14: 3b30 subs r3, #48 ; 0x30
  24735. 8009b16: 2b09 cmp r3, #9
  24736. 8009b18: d94e bls.n 8009bb8 <_vfiprintf_r+0x1c4>
  24737. 8009b1a: b1b0 cbz r0, 8009b4a <_vfiprintf_r+0x156>
  24738. 8009b1c: 9207 str r2, [sp, #28]
  24739. 8009b1e: e014 b.n 8009b4a <_vfiprintf_r+0x156>
  24740. 8009b20: eba0 0308 sub.w r3, r0, r8
  24741. 8009b24: fa09 f303 lsl.w r3, r9, r3
  24742. 8009b28: 4313 orrs r3, r2
  24743. 8009b2a: 9304 str r3, [sp, #16]
  24744. 8009b2c: 46a2 mov sl, r4
  24745. 8009b2e: e7d2 b.n 8009ad6 <_vfiprintf_r+0xe2>
  24746. 8009b30: 9b03 ldr r3, [sp, #12]
  24747. 8009b32: 1d19 adds r1, r3, #4
  24748. 8009b34: 681b ldr r3, [r3, #0]
  24749. 8009b36: 9103 str r1, [sp, #12]
  24750. 8009b38: 2b00 cmp r3, #0
  24751. 8009b3a: bfbb ittet lt
  24752. 8009b3c: 425b neglt r3, r3
  24753. 8009b3e: f042 0202 orrlt.w r2, r2, #2
  24754. 8009b42: 9307 strge r3, [sp, #28]
  24755. 8009b44: 9307 strlt r3, [sp, #28]
  24756. 8009b46: bfb8 it lt
  24757. 8009b48: 9204 strlt r2, [sp, #16]
  24758. 8009b4a: 7823 ldrb r3, [r4, #0]
  24759. 8009b4c: 2b2e cmp r3, #46 ; 0x2e
  24760. 8009b4e: d10c bne.n 8009b6a <_vfiprintf_r+0x176>
  24761. 8009b50: 7863 ldrb r3, [r4, #1]
  24762. 8009b52: 2b2a cmp r3, #42 ; 0x2a
  24763. 8009b54: d135 bne.n 8009bc2 <_vfiprintf_r+0x1ce>
  24764. 8009b56: 9b03 ldr r3, [sp, #12]
  24765. 8009b58: 1d1a adds r2, r3, #4
  24766. 8009b5a: 681b ldr r3, [r3, #0]
  24767. 8009b5c: 9203 str r2, [sp, #12]
  24768. 8009b5e: 2b00 cmp r3, #0
  24769. 8009b60: bfb8 it lt
  24770. 8009b62: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff
  24771. 8009b66: 3402 adds r4, #2
  24772. 8009b68: 9305 str r3, [sp, #20]
  24773. 8009b6a: f8df a0e4 ldr.w sl, [pc, #228] ; 8009c50 <_vfiprintf_r+0x25c>
  24774. 8009b6e: 7821 ldrb r1, [r4, #0]
  24775. 8009b70: 2203 movs r2, #3
  24776. 8009b72: 4650 mov r0, sl
  24777. 8009b74: f7f6 fbcc bl 8000310 <memchr>
  24778. 8009b78: b140 cbz r0, 8009b8c <_vfiprintf_r+0x198>
  24779. 8009b7a: 2340 movs r3, #64 ; 0x40
  24780. 8009b7c: eba0 000a sub.w r0, r0, sl
  24781. 8009b80: fa03 f000 lsl.w r0, r3, r0
  24782. 8009b84: 9b04 ldr r3, [sp, #16]
  24783. 8009b86: 4303 orrs r3, r0
  24784. 8009b88: 3401 adds r4, #1
  24785. 8009b8a: 9304 str r3, [sp, #16]
  24786. 8009b8c: f814 1b01 ldrb.w r1, [r4], #1
  24787. 8009b90: 482c ldr r0, [pc, #176] ; (8009c44 <_vfiprintf_r+0x250>)
  24788. 8009b92: f88d 1028 strb.w r1, [sp, #40] ; 0x28
  24789. 8009b96: 2206 movs r2, #6
  24790. 8009b98: f7f6 fbba bl 8000310 <memchr>
  24791. 8009b9c: 2800 cmp r0, #0
  24792. 8009b9e: d03f beq.n 8009c20 <_vfiprintf_r+0x22c>
  24793. 8009ba0: 4b29 ldr r3, [pc, #164] ; (8009c48 <_vfiprintf_r+0x254>)
  24794. 8009ba2: bb1b cbnz r3, 8009bec <_vfiprintf_r+0x1f8>
  24795. 8009ba4: 9b03 ldr r3, [sp, #12]
  24796. 8009ba6: 3307 adds r3, #7
  24797. 8009ba8: f023 0307 bic.w r3, r3, #7
  24798. 8009bac: 3308 adds r3, #8
  24799. 8009bae: 9303 str r3, [sp, #12]
  24800. 8009bb0: 9b09 ldr r3, [sp, #36] ; 0x24
  24801. 8009bb2: 443b add r3, r7
  24802. 8009bb4: 9309 str r3, [sp, #36] ; 0x24
  24803. 8009bb6: e767 b.n 8009a88 <_vfiprintf_r+0x94>
  24804. 8009bb8: fb0c 3202 mla r2, ip, r2, r3
  24805. 8009bbc: 460c mov r4, r1
  24806. 8009bbe: 2001 movs r0, #1
  24807. 8009bc0: e7a5 b.n 8009b0e <_vfiprintf_r+0x11a>
  24808. 8009bc2: 2300 movs r3, #0
  24809. 8009bc4: 3401 adds r4, #1
  24810. 8009bc6: 9305 str r3, [sp, #20]
  24811. 8009bc8: 4619 mov r1, r3
  24812. 8009bca: f04f 0c0a mov.w ip, #10
  24813. 8009bce: 4620 mov r0, r4
  24814. 8009bd0: f810 2b01 ldrb.w r2, [r0], #1
  24815. 8009bd4: 3a30 subs r2, #48 ; 0x30
  24816. 8009bd6: 2a09 cmp r2, #9
  24817. 8009bd8: d903 bls.n 8009be2 <_vfiprintf_r+0x1ee>
  24818. 8009bda: 2b00 cmp r3, #0
  24819. 8009bdc: d0c5 beq.n 8009b6a <_vfiprintf_r+0x176>
  24820. 8009bde: 9105 str r1, [sp, #20]
  24821. 8009be0: e7c3 b.n 8009b6a <_vfiprintf_r+0x176>
  24822. 8009be2: fb0c 2101 mla r1, ip, r1, r2
  24823. 8009be6: 4604 mov r4, r0
  24824. 8009be8: 2301 movs r3, #1
  24825. 8009bea: e7f0 b.n 8009bce <_vfiprintf_r+0x1da>
  24826. 8009bec: ab03 add r3, sp, #12
  24827. 8009bee: 9300 str r3, [sp, #0]
  24828. 8009bf0: 462a mov r2, r5
  24829. 8009bf2: 4b16 ldr r3, [pc, #88] ; (8009c4c <_vfiprintf_r+0x258>)
  24830. 8009bf4: a904 add r1, sp, #16
  24831. 8009bf6: 4630 mov r0, r6
  24832. 8009bf8: f3af 8000 nop.w
  24833. 8009bfc: 4607 mov r7, r0
  24834. 8009bfe: 1c78 adds r0, r7, #1
  24835. 8009c00: d1d6 bne.n 8009bb0 <_vfiprintf_r+0x1bc>
  24836. 8009c02: 6e6b ldr r3, [r5, #100] ; 0x64
  24837. 8009c04: 07d9 lsls r1, r3, #31
  24838. 8009c06: d405 bmi.n 8009c14 <_vfiprintf_r+0x220>
  24839. 8009c08: 89ab ldrh r3, [r5, #12]
  24840. 8009c0a: 059a lsls r2, r3, #22
  24841. 8009c0c: d402 bmi.n 8009c14 <_vfiprintf_r+0x220>
  24842. 8009c0e: 6da8 ldr r0, [r5, #88] ; 0x58
  24843. 8009c10: f000 fc35 bl 800a47e <__retarget_lock_release_recursive>
  24844. 8009c14: 89ab ldrh r3, [r5, #12]
  24845. 8009c16: 065b lsls r3, r3, #25
  24846. 8009c18: f53f af12 bmi.w 8009a40 <_vfiprintf_r+0x4c>
  24847. 8009c1c: 9809 ldr r0, [sp, #36] ; 0x24
  24848. 8009c1e: e711 b.n 8009a44 <_vfiprintf_r+0x50>
  24849. 8009c20: ab03 add r3, sp, #12
  24850. 8009c22: 9300 str r3, [sp, #0]
  24851. 8009c24: 462a mov r2, r5
  24852. 8009c26: 4b09 ldr r3, [pc, #36] ; (8009c4c <_vfiprintf_r+0x258>)
  24853. 8009c28: a904 add r1, sp, #16
  24854. 8009c2a: 4630 mov r0, r6
  24855. 8009c2c: f000 f880 bl 8009d30 <_printf_i>
  24856. 8009c30: e7e4 b.n 8009bfc <_vfiprintf_r+0x208>
  24857. 8009c32: bf00 nop
  24858. 8009c34: 0800aab4 .word 0x0800aab4
  24859. 8009c38: 0800aad4 .word 0x0800aad4
  24860. 8009c3c: 0800aa94 .word 0x0800aa94
  24861. 8009c40: 0800aa60 .word 0x0800aa60
  24862. 8009c44: 0800aa6a .word 0x0800aa6a
  24863. 8009c48: 00000000 .word 0x00000000
  24864. 8009c4c: 080099cf .word 0x080099cf
  24865. 8009c50: 0800aa66 .word 0x0800aa66
  24866. 08009c54 <_printf_common>:
  24867. 8009c54: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  24868. 8009c58: 4616 mov r6, r2
  24869. 8009c5a: 4699 mov r9, r3
  24870. 8009c5c: 688a ldr r2, [r1, #8]
  24871. 8009c5e: 690b ldr r3, [r1, #16]
  24872. 8009c60: f8dd 8020 ldr.w r8, [sp, #32]
  24873. 8009c64: 4293 cmp r3, r2
  24874. 8009c66: bfb8 it lt
  24875. 8009c68: 4613 movlt r3, r2
  24876. 8009c6a: 6033 str r3, [r6, #0]
  24877. 8009c6c: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
  24878. 8009c70: 4607 mov r7, r0
  24879. 8009c72: 460c mov r4, r1
  24880. 8009c74: b10a cbz r2, 8009c7a <_printf_common+0x26>
  24881. 8009c76: 3301 adds r3, #1
  24882. 8009c78: 6033 str r3, [r6, #0]
  24883. 8009c7a: 6823 ldr r3, [r4, #0]
  24884. 8009c7c: 0699 lsls r1, r3, #26
  24885. 8009c7e: bf42 ittt mi
  24886. 8009c80: 6833 ldrmi r3, [r6, #0]
  24887. 8009c82: 3302 addmi r3, #2
  24888. 8009c84: 6033 strmi r3, [r6, #0]
  24889. 8009c86: 6825 ldr r5, [r4, #0]
  24890. 8009c88: f015 0506 ands.w r5, r5, #6
  24891. 8009c8c: d106 bne.n 8009c9c <_printf_common+0x48>
  24892. 8009c8e: f104 0a19 add.w sl, r4, #25
  24893. 8009c92: 68e3 ldr r3, [r4, #12]
  24894. 8009c94: 6832 ldr r2, [r6, #0]
  24895. 8009c96: 1a9b subs r3, r3, r2
  24896. 8009c98: 42ab cmp r3, r5
  24897. 8009c9a: dc26 bgt.n 8009cea <_printf_common+0x96>
  24898. 8009c9c: f894 2043 ldrb.w r2, [r4, #67] ; 0x43
  24899. 8009ca0: 1e13 subs r3, r2, #0
  24900. 8009ca2: 6822 ldr r2, [r4, #0]
  24901. 8009ca4: bf18 it ne
  24902. 8009ca6: 2301 movne r3, #1
  24903. 8009ca8: 0692 lsls r2, r2, #26
  24904. 8009caa: d42b bmi.n 8009d04 <_printf_common+0xb0>
  24905. 8009cac: f104 0243 add.w r2, r4, #67 ; 0x43
  24906. 8009cb0: 4649 mov r1, r9
  24907. 8009cb2: 4638 mov r0, r7
  24908. 8009cb4: 47c0 blx r8
  24909. 8009cb6: 3001 adds r0, #1
  24910. 8009cb8: d01e beq.n 8009cf8 <_printf_common+0xa4>
  24911. 8009cba: 6823 ldr r3, [r4, #0]
  24912. 8009cbc: 68e5 ldr r5, [r4, #12]
  24913. 8009cbe: 6832 ldr r2, [r6, #0]
  24914. 8009cc0: f003 0306 and.w r3, r3, #6
  24915. 8009cc4: 2b04 cmp r3, #4
  24916. 8009cc6: bf08 it eq
  24917. 8009cc8: 1aad subeq r5, r5, r2
  24918. 8009cca: 68a3 ldr r3, [r4, #8]
  24919. 8009ccc: 6922 ldr r2, [r4, #16]
  24920. 8009cce: bf0c ite eq
  24921. 8009cd0: ea25 75e5 biceq.w r5, r5, r5, asr #31
  24922. 8009cd4: 2500 movne r5, #0
  24923. 8009cd6: 4293 cmp r3, r2
  24924. 8009cd8: bfc4 itt gt
  24925. 8009cda: 1a9b subgt r3, r3, r2
  24926. 8009cdc: 18ed addgt r5, r5, r3
  24927. 8009cde: 2600 movs r6, #0
  24928. 8009ce0: 341a adds r4, #26
  24929. 8009ce2: 42b5 cmp r5, r6
  24930. 8009ce4: d11a bne.n 8009d1c <_printf_common+0xc8>
  24931. 8009ce6: 2000 movs r0, #0
  24932. 8009ce8: e008 b.n 8009cfc <_printf_common+0xa8>
  24933. 8009cea: 2301 movs r3, #1
  24934. 8009cec: 4652 mov r2, sl
  24935. 8009cee: 4649 mov r1, r9
  24936. 8009cf0: 4638 mov r0, r7
  24937. 8009cf2: 47c0 blx r8
  24938. 8009cf4: 3001 adds r0, #1
  24939. 8009cf6: d103 bne.n 8009d00 <_printf_common+0xac>
  24940. 8009cf8: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
  24941. 8009cfc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  24942. 8009d00: 3501 adds r5, #1
  24943. 8009d02: e7c6 b.n 8009c92 <_printf_common+0x3e>
  24944. 8009d04: 18e1 adds r1, r4, r3
  24945. 8009d06: 1c5a adds r2, r3, #1
  24946. 8009d08: 2030 movs r0, #48 ; 0x30
  24947. 8009d0a: f881 0043 strb.w r0, [r1, #67] ; 0x43
  24948. 8009d0e: 4422 add r2, r4
  24949. 8009d10: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
  24950. 8009d14: f882 1043 strb.w r1, [r2, #67] ; 0x43
  24951. 8009d18: 3302 adds r3, #2
  24952. 8009d1a: e7c7 b.n 8009cac <_printf_common+0x58>
  24953. 8009d1c: 2301 movs r3, #1
  24954. 8009d1e: 4622 mov r2, r4
  24955. 8009d20: 4649 mov r1, r9
  24956. 8009d22: 4638 mov r0, r7
  24957. 8009d24: 47c0 blx r8
  24958. 8009d26: 3001 adds r0, #1
  24959. 8009d28: d0e6 beq.n 8009cf8 <_printf_common+0xa4>
  24960. 8009d2a: 3601 adds r6, #1
  24961. 8009d2c: e7d9 b.n 8009ce2 <_printf_common+0x8e>
  24962. ...
  24963. 08009d30 <_printf_i>:
  24964. 8009d30: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
  24965. 8009d34: 460c mov r4, r1
  24966. 8009d36: 4691 mov r9, r2
  24967. 8009d38: 7e27 ldrb r7, [r4, #24]
  24968. 8009d3a: 990c ldr r1, [sp, #48] ; 0x30
  24969. 8009d3c: 2f78 cmp r7, #120 ; 0x78
  24970. 8009d3e: 4680 mov r8, r0
  24971. 8009d40: 469a mov sl, r3
  24972. 8009d42: f104 0243 add.w r2, r4, #67 ; 0x43
  24973. 8009d46: d807 bhi.n 8009d58 <_printf_i+0x28>
  24974. 8009d48: 2f62 cmp r7, #98 ; 0x62
  24975. 8009d4a: d80a bhi.n 8009d62 <_printf_i+0x32>
  24976. 8009d4c: 2f00 cmp r7, #0
  24977. 8009d4e: f000 80d8 beq.w 8009f02 <_printf_i+0x1d2>
  24978. 8009d52: 2f58 cmp r7, #88 ; 0x58
  24979. 8009d54: f000 80a3 beq.w 8009e9e <_printf_i+0x16e>
  24980. 8009d58: f104 0642 add.w r6, r4, #66 ; 0x42
  24981. 8009d5c: f884 7042 strb.w r7, [r4, #66] ; 0x42
  24982. 8009d60: e03a b.n 8009dd8 <_printf_i+0xa8>
  24983. 8009d62: f1a7 0363 sub.w r3, r7, #99 ; 0x63
  24984. 8009d66: 2b15 cmp r3, #21
  24985. 8009d68: d8f6 bhi.n 8009d58 <_printf_i+0x28>
  24986. 8009d6a: a001 add r0, pc, #4 ; (adr r0, 8009d70 <_printf_i+0x40>)
  24987. 8009d6c: f850 f023 ldr.w pc, [r0, r3, lsl #2]
  24988. 8009d70: 08009dc9 .word 0x08009dc9
  24989. 8009d74: 08009ddd .word 0x08009ddd
  24990. 8009d78: 08009d59 .word 0x08009d59
  24991. 8009d7c: 08009d59 .word 0x08009d59
  24992. 8009d80: 08009d59 .word 0x08009d59
  24993. 8009d84: 08009d59 .word 0x08009d59
  24994. 8009d88: 08009ddd .word 0x08009ddd
  24995. 8009d8c: 08009d59 .word 0x08009d59
  24996. 8009d90: 08009d59 .word 0x08009d59
  24997. 8009d94: 08009d59 .word 0x08009d59
  24998. 8009d98: 08009d59 .word 0x08009d59
  24999. 8009d9c: 08009ee9 .word 0x08009ee9
  25000. 8009da0: 08009e0d .word 0x08009e0d
  25001. 8009da4: 08009ecb .word 0x08009ecb
  25002. 8009da8: 08009d59 .word 0x08009d59
  25003. 8009dac: 08009d59 .word 0x08009d59
  25004. 8009db0: 08009f0b .word 0x08009f0b
  25005. 8009db4: 08009d59 .word 0x08009d59
  25006. 8009db8: 08009e0d .word 0x08009e0d
  25007. 8009dbc: 08009d59 .word 0x08009d59
  25008. 8009dc0: 08009d59 .word 0x08009d59
  25009. 8009dc4: 08009ed3 .word 0x08009ed3
  25010. 8009dc8: 680b ldr r3, [r1, #0]
  25011. 8009dca: 1d1a adds r2, r3, #4
  25012. 8009dcc: 681b ldr r3, [r3, #0]
  25013. 8009dce: 600a str r2, [r1, #0]
  25014. 8009dd0: f104 0642 add.w r6, r4, #66 ; 0x42
  25015. 8009dd4: f884 3042 strb.w r3, [r4, #66] ; 0x42
  25016. 8009dd8: 2301 movs r3, #1
  25017. 8009dda: e0a3 b.n 8009f24 <_printf_i+0x1f4>
  25018. 8009ddc: 6825 ldr r5, [r4, #0]
  25019. 8009dde: 6808 ldr r0, [r1, #0]
  25020. 8009de0: 062e lsls r6, r5, #24
  25021. 8009de2: f100 0304 add.w r3, r0, #4
  25022. 8009de6: d50a bpl.n 8009dfe <_printf_i+0xce>
  25023. 8009de8: 6805 ldr r5, [r0, #0]
  25024. 8009dea: 600b str r3, [r1, #0]
  25025. 8009dec: 2d00 cmp r5, #0
  25026. 8009dee: da03 bge.n 8009df8 <_printf_i+0xc8>
  25027. 8009df0: 232d movs r3, #45 ; 0x2d
  25028. 8009df2: 426d negs r5, r5
  25029. 8009df4: f884 3043 strb.w r3, [r4, #67] ; 0x43
  25030. 8009df8: 485e ldr r0, [pc, #376] ; (8009f74 <_printf_i+0x244>)
  25031. 8009dfa: 230a movs r3, #10
  25032. 8009dfc: e019 b.n 8009e32 <_printf_i+0x102>
  25033. 8009dfe: f015 0f40 tst.w r5, #64 ; 0x40
  25034. 8009e02: 6805 ldr r5, [r0, #0]
  25035. 8009e04: 600b str r3, [r1, #0]
  25036. 8009e06: bf18 it ne
  25037. 8009e08: b22d sxthne r5, r5
  25038. 8009e0a: e7ef b.n 8009dec <_printf_i+0xbc>
  25039. 8009e0c: 680b ldr r3, [r1, #0]
  25040. 8009e0e: 6825 ldr r5, [r4, #0]
  25041. 8009e10: 1d18 adds r0, r3, #4
  25042. 8009e12: 6008 str r0, [r1, #0]
  25043. 8009e14: 0628 lsls r0, r5, #24
  25044. 8009e16: d501 bpl.n 8009e1c <_printf_i+0xec>
  25045. 8009e18: 681d ldr r5, [r3, #0]
  25046. 8009e1a: e002 b.n 8009e22 <_printf_i+0xf2>
  25047. 8009e1c: 0669 lsls r1, r5, #25
  25048. 8009e1e: d5fb bpl.n 8009e18 <_printf_i+0xe8>
  25049. 8009e20: 881d ldrh r5, [r3, #0]
  25050. 8009e22: 4854 ldr r0, [pc, #336] ; (8009f74 <_printf_i+0x244>)
  25051. 8009e24: 2f6f cmp r7, #111 ; 0x6f
  25052. 8009e26: bf0c ite eq
  25053. 8009e28: 2308 moveq r3, #8
  25054. 8009e2a: 230a movne r3, #10
  25055. 8009e2c: 2100 movs r1, #0
  25056. 8009e2e: f884 1043 strb.w r1, [r4, #67] ; 0x43
  25057. 8009e32: 6866 ldr r6, [r4, #4]
  25058. 8009e34: 60a6 str r6, [r4, #8]
  25059. 8009e36: 2e00 cmp r6, #0
  25060. 8009e38: bfa2 ittt ge
  25061. 8009e3a: 6821 ldrge r1, [r4, #0]
  25062. 8009e3c: f021 0104 bicge.w r1, r1, #4
  25063. 8009e40: 6021 strge r1, [r4, #0]
  25064. 8009e42: b90d cbnz r5, 8009e48 <_printf_i+0x118>
  25065. 8009e44: 2e00 cmp r6, #0
  25066. 8009e46: d04d beq.n 8009ee4 <_printf_i+0x1b4>
  25067. 8009e48: 4616 mov r6, r2
  25068. 8009e4a: fbb5 f1f3 udiv r1, r5, r3
  25069. 8009e4e: fb03 5711 mls r7, r3, r1, r5
  25070. 8009e52: 5dc7 ldrb r7, [r0, r7]
  25071. 8009e54: f806 7d01 strb.w r7, [r6, #-1]!
  25072. 8009e58: 462f mov r7, r5
  25073. 8009e5a: 42bb cmp r3, r7
  25074. 8009e5c: 460d mov r5, r1
  25075. 8009e5e: d9f4 bls.n 8009e4a <_printf_i+0x11a>
  25076. 8009e60: 2b08 cmp r3, #8
  25077. 8009e62: d10b bne.n 8009e7c <_printf_i+0x14c>
  25078. 8009e64: 6823 ldr r3, [r4, #0]
  25079. 8009e66: 07df lsls r7, r3, #31
  25080. 8009e68: d508 bpl.n 8009e7c <_printf_i+0x14c>
  25081. 8009e6a: 6923 ldr r3, [r4, #16]
  25082. 8009e6c: 6861 ldr r1, [r4, #4]
  25083. 8009e6e: 4299 cmp r1, r3
  25084. 8009e70: bfde ittt le
  25085. 8009e72: 2330 movle r3, #48 ; 0x30
  25086. 8009e74: f806 3c01 strble.w r3, [r6, #-1]
  25087. 8009e78: f106 36ff addle.w r6, r6, #4294967295 ; 0xffffffff
  25088. 8009e7c: 1b92 subs r2, r2, r6
  25089. 8009e7e: 6122 str r2, [r4, #16]
  25090. 8009e80: f8cd a000 str.w sl, [sp]
  25091. 8009e84: 464b mov r3, r9
  25092. 8009e86: aa03 add r2, sp, #12
  25093. 8009e88: 4621 mov r1, r4
  25094. 8009e8a: 4640 mov r0, r8
  25095. 8009e8c: f7ff fee2 bl 8009c54 <_printf_common>
  25096. 8009e90: 3001 adds r0, #1
  25097. 8009e92: d14c bne.n 8009f2e <_printf_i+0x1fe>
  25098. 8009e94: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
  25099. 8009e98: b004 add sp, #16
  25100. 8009e9a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  25101. 8009e9e: 4835 ldr r0, [pc, #212] ; (8009f74 <_printf_i+0x244>)
  25102. 8009ea0: f884 7045 strb.w r7, [r4, #69] ; 0x45
  25103. 8009ea4: 6823 ldr r3, [r4, #0]
  25104. 8009ea6: 680e ldr r6, [r1, #0]
  25105. 8009ea8: 061f lsls r7, r3, #24
  25106. 8009eaa: f856 5b04 ldr.w r5, [r6], #4
  25107. 8009eae: 600e str r6, [r1, #0]
  25108. 8009eb0: d514 bpl.n 8009edc <_printf_i+0x1ac>
  25109. 8009eb2: 07d9 lsls r1, r3, #31
  25110. 8009eb4: bf44 itt mi
  25111. 8009eb6: f043 0320 orrmi.w r3, r3, #32
  25112. 8009eba: 6023 strmi r3, [r4, #0]
  25113. 8009ebc: b91d cbnz r5, 8009ec6 <_printf_i+0x196>
  25114. 8009ebe: 6823 ldr r3, [r4, #0]
  25115. 8009ec0: f023 0320 bic.w r3, r3, #32
  25116. 8009ec4: 6023 str r3, [r4, #0]
  25117. 8009ec6: 2310 movs r3, #16
  25118. 8009ec8: e7b0 b.n 8009e2c <_printf_i+0xfc>
  25119. 8009eca: 6823 ldr r3, [r4, #0]
  25120. 8009ecc: f043 0320 orr.w r3, r3, #32
  25121. 8009ed0: 6023 str r3, [r4, #0]
  25122. 8009ed2: 2378 movs r3, #120 ; 0x78
  25123. 8009ed4: 4828 ldr r0, [pc, #160] ; (8009f78 <_printf_i+0x248>)
  25124. 8009ed6: f884 3045 strb.w r3, [r4, #69] ; 0x45
  25125. 8009eda: e7e3 b.n 8009ea4 <_printf_i+0x174>
  25126. 8009edc: 065e lsls r6, r3, #25
  25127. 8009ede: bf48 it mi
  25128. 8009ee0: b2ad uxthmi r5, r5
  25129. 8009ee2: e7e6 b.n 8009eb2 <_printf_i+0x182>
  25130. 8009ee4: 4616 mov r6, r2
  25131. 8009ee6: e7bb b.n 8009e60 <_printf_i+0x130>
  25132. 8009ee8: 680b ldr r3, [r1, #0]
  25133. 8009eea: 6826 ldr r6, [r4, #0]
  25134. 8009eec: 6960 ldr r0, [r4, #20]
  25135. 8009eee: 1d1d adds r5, r3, #4
  25136. 8009ef0: 600d str r5, [r1, #0]
  25137. 8009ef2: 0635 lsls r5, r6, #24
  25138. 8009ef4: 681b ldr r3, [r3, #0]
  25139. 8009ef6: d501 bpl.n 8009efc <_printf_i+0x1cc>
  25140. 8009ef8: 6018 str r0, [r3, #0]
  25141. 8009efa: e002 b.n 8009f02 <_printf_i+0x1d2>
  25142. 8009efc: 0671 lsls r1, r6, #25
  25143. 8009efe: d5fb bpl.n 8009ef8 <_printf_i+0x1c8>
  25144. 8009f00: 8018 strh r0, [r3, #0]
  25145. 8009f02: 2300 movs r3, #0
  25146. 8009f04: 6123 str r3, [r4, #16]
  25147. 8009f06: 4616 mov r6, r2
  25148. 8009f08: e7ba b.n 8009e80 <_printf_i+0x150>
  25149. 8009f0a: 680b ldr r3, [r1, #0]
  25150. 8009f0c: 1d1a adds r2, r3, #4
  25151. 8009f0e: 600a str r2, [r1, #0]
  25152. 8009f10: 681e ldr r6, [r3, #0]
  25153. 8009f12: 6862 ldr r2, [r4, #4]
  25154. 8009f14: 2100 movs r1, #0
  25155. 8009f16: 4630 mov r0, r6
  25156. 8009f18: f7f6 f9fa bl 8000310 <memchr>
  25157. 8009f1c: b108 cbz r0, 8009f22 <_printf_i+0x1f2>
  25158. 8009f1e: 1b80 subs r0, r0, r6
  25159. 8009f20: 6060 str r0, [r4, #4]
  25160. 8009f22: 6863 ldr r3, [r4, #4]
  25161. 8009f24: 6123 str r3, [r4, #16]
  25162. 8009f26: 2300 movs r3, #0
  25163. 8009f28: f884 3043 strb.w r3, [r4, #67] ; 0x43
  25164. 8009f2c: e7a8 b.n 8009e80 <_printf_i+0x150>
  25165. 8009f2e: 6923 ldr r3, [r4, #16]
  25166. 8009f30: 4632 mov r2, r6
  25167. 8009f32: 4649 mov r1, r9
  25168. 8009f34: 4640 mov r0, r8
  25169. 8009f36: 47d0 blx sl
  25170. 8009f38: 3001 adds r0, #1
  25171. 8009f3a: d0ab beq.n 8009e94 <_printf_i+0x164>
  25172. 8009f3c: 6823 ldr r3, [r4, #0]
  25173. 8009f3e: 079b lsls r3, r3, #30
  25174. 8009f40: d413 bmi.n 8009f6a <_printf_i+0x23a>
  25175. 8009f42: 68e0 ldr r0, [r4, #12]
  25176. 8009f44: 9b03 ldr r3, [sp, #12]
  25177. 8009f46: 4298 cmp r0, r3
  25178. 8009f48: bfb8 it lt
  25179. 8009f4a: 4618 movlt r0, r3
  25180. 8009f4c: e7a4 b.n 8009e98 <_printf_i+0x168>
  25181. 8009f4e: 2301 movs r3, #1
  25182. 8009f50: 4632 mov r2, r6
  25183. 8009f52: 4649 mov r1, r9
  25184. 8009f54: 4640 mov r0, r8
  25185. 8009f56: 47d0 blx sl
  25186. 8009f58: 3001 adds r0, #1
  25187. 8009f5a: d09b beq.n 8009e94 <_printf_i+0x164>
  25188. 8009f5c: 3501 adds r5, #1
  25189. 8009f5e: 68e3 ldr r3, [r4, #12]
  25190. 8009f60: 9903 ldr r1, [sp, #12]
  25191. 8009f62: 1a5b subs r3, r3, r1
  25192. 8009f64: 42ab cmp r3, r5
  25193. 8009f66: dcf2 bgt.n 8009f4e <_printf_i+0x21e>
  25194. 8009f68: e7eb b.n 8009f42 <_printf_i+0x212>
  25195. 8009f6a: 2500 movs r5, #0
  25196. 8009f6c: f104 0619 add.w r6, r4, #25
  25197. 8009f70: e7f5 b.n 8009f5e <_printf_i+0x22e>
  25198. 8009f72: bf00 nop
  25199. 8009f74: 0800aa71 .word 0x0800aa71
  25200. 8009f78: 0800aa82 .word 0x0800aa82
  25201. 08009f7c <__swbuf_r>:
  25202. 8009f7c: b5f8 push {r3, r4, r5, r6, r7, lr}
  25203. 8009f7e: 460e mov r6, r1
  25204. 8009f80: 4614 mov r4, r2
  25205. 8009f82: 4605 mov r5, r0
  25206. 8009f84: b118 cbz r0, 8009f8e <__swbuf_r+0x12>
  25207. 8009f86: 6983 ldr r3, [r0, #24]
  25208. 8009f88: b90b cbnz r3, 8009f8e <__swbuf_r+0x12>
  25209. 8009f8a: f000 f9d9 bl 800a340 <__sinit>
  25210. 8009f8e: 4b21 ldr r3, [pc, #132] ; (800a014 <__swbuf_r+0x98>)
  25211. 8009f90: 429c cmp r4, r3
  25212. 8009f92: d12b bne.n 8009fec <__swbuf_r+0x70>
  25213. 8009f94: 686c ldr r4, [r5, #4]
  25214. 8009f96: 69a3 ldr r3, [r4, #24]
  25215. 8009f98: 60a3 str r3, [r4, #8]
  25216. 8009f9a: 89a3 ldrh r3, [r4, #12]
  25217. 8009f9c: 071a lsls r2, r3, #28
  25218. 8009f9e: d52f bpl.n 800a000 <__swbuf_r+0x84>
  25219. 8009fa0: 6923 ldr r3, [r4, #16]
  25220. 8009fa2: b36b cbz r3, 800a000 <__swbuf_r+0x84>
  25221. 8009fa4: 6923 ldr r3, [r4, #16]
  25222. 8009fa6: 6820 ldr r0, [r4, #0]
  25223. 8009fa8: 1ac0 subs r0, r0, r3
  25224. 8009faa: 6963 ldr r3, [r4, #20]
  25225. 8009fac: b2f6 uxtb r6, r6
  25226. 8009fae: 4283 cmp r3, r0
  25227. 8009fb0: 4637 mov r7, r6
  25228. 8009fb2: dc04 bgt.n 8009fbe <__swbuf_r+0x42>
  25229. 8009fb4: 4621 mov r1, r4
  25230. 8009fb6: 4628 mov r0, r5
  25231. 8009fb8: f000 f92e bl 800a218 <_fflush_r>
  25232. 8009fbc: bb30 cbnz r0, 800a00c <__swbuf_r+0x90>
  25233. 8009fbe: 68a3 ldr r3, [r4, #8]
  25234. 8009fc0: 3b01 subs r3, #1
  25235. 8009fc2: 60a3 str r3, [r4, #8]
  25236. 8009fc4: 6823 ldr r3, [r4, #0]
  25237. 8009fc6: 1c5a adds r2, r3, #1
  25238. 8009fc8: 6022 str r2, [r4, #0]
  25239. 8009fca: 701e strb r6, [r3, #0]
  25240. 8009fcc: 6963 ldr r3, [r4, #20]
  25241. 8009fce: 3001 adds r0, #1
  25242. 8009fd0: 4283 cmp r3, r0
  25243. 8009fd2: d004 beq.n 8009fde <__swbuf_r+0x62>
  25244. 8009fd4: 89a3 ldrh r3, [r4, #12]
  25245. 8009fd6: 07db lsls r3, r3, #31
  25246. 8009fd8: d506 bpl.n 8009fe8 <__swbuf_r+0x6c>
  25247. 8009fda: 2e0a cmp r6, #10
  25248. 8009fdc: d104 bne.n 8009fe8 <__swbuf_r+0x6c>
  25249. 8009fde: 4621 mov r1, r4
  25250. 8009fe0: 4628 mov r0, r5
  25251. 8009fe2: f000 f919 bl 800a218 <_fflush_r>
  25252. 8009fe6: b988 cbnz r0, 800a00c <__swbuf_r+0x90>
  25253. 8009fe8: 4638 mov r0, r7
  25254. 8009fea: bdf8 pop {r3, r4, r5, r6, r7, pc}
  25255. 8009fec: 4b0a ldr r3, [pc, #40] ; (800a018 <__swbuf_r+0x9c>)
  25256. 8009fee: 429c cmp r4, r3
  25257. 8009ff0: d101 bne.n 8009ff6 <__swbuf_r+0x7a>
  25258. 8009ff2: 68ac ldr r4, [r5, #8]
  25259. 8009ff4: e7cf b.n 8009f96 <__swbuf_r+0x1a>
  25260. 8009ff6: 4b09 ldr r3, [pc, #36] ; (800a01c <__swbuf_r+0xa0>)
  25261. 8009ff8: 429c cmp r4, r3
  25262. 8009ffa: bf08 it eq
  25263. 8009ffc: 68ec ldreq r4, [r5, #12]
  25264. 8009ffe: e7ca b.n 8009f96 <__swbuf_r+0x1a>
  25265. 800a000: 4621 mov r1, r4
  25266. 800a002: 4628 mov r0, r5
  25267. 800a004: f000 f80c bl 800a020 <__swsetup_r>
  25268. 800a008: 2800 cmp r0, #0
  25269. 800a00a: d0cb beq.n 8009fa4 <__swbuf_r+0x28>
  25270. 800a00c: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff
  25271. 800a010: e7ea b.n 8009fe8 <__swbuf_r+0x6c>
  25272. 800a012: bf00 nop
  25273. 800a014: 0800aab4 .word 0x0800aab4
  25274. 800a018: 0800aad4 .word 0x0800aad4
  25275. 800a01c: 0800aa94 .word 0x0800aa94
  25276. 0800a020 <__swsetup_r>:
  25277. 800a020: 4b32 ldr r3, [pc, #200] ; (800a0ec <__swsetup_r+0xcc>)
  25278. 800a022: b570 push {r4, r5, r6, lr}
  25279. 800a024: 681d ldr r5, [r3, #0]
  25280. 800a026: 4606 mov r6, r0
  25281. 800a028: 460c mov r4, r1
  25282. 800a02a: b125 cbz r5, 800a036 <__swsetup_r+0x16>
  25283. 800a02c: 69ab ldr r3, [r5, #24]
  25284. 800a02e: b913 cbnz r3, 800a036 <__swsetup_r+0x16>
  25285. 800a030: 4628 mov r0, r5
  25286. 800a032: f000 f985 bl 800a340 <__sinit>
  25287. 800a036: 4b2e ldr r3, [pc, #184] ; (800a0f0 <__swsetup_r+0xd0>)
  25288. 800a038: 429c cmp r4, r3
  25289. 800a03a: d10f bne.n 800a05c <__swsetup_r+0x3c>
  25290. 800a03c: 686c ldr r4, [r5, #4]
  25291. 800a03e: 89a3 ldrh r3, [r4, #12]
  25292. 800a040: f9b4 200c ldrsh.w r2, [r4, #12]
  25293. 800a044: 0719 lsls r1, r3, #28
  25294. 800a046: d42c bmi.n 800a0a2 <__swsetup_r+0x82>
  25295. 800a048: 06dd lsls r5, r3, #27
  25296. 800a04a: d411 bmi.n 800a070 <__swsetup_r+0x50>
  25297. 800a04c: 2309 movs r3, #9
  25298. 800a04e: 6033 str r3, [r6, #0]
  25299. 800a050: f042 0340 orr.w r3, r2, #64 ; 0x40
  25300. 800a054: 81a3 strh r3, [r4, #12]
  25301. 800a056: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
  25302. 800a05a: e03e b.n 800a0da <__swsetup_r+0xba>
  25303. 800a05c: 4b25 ldr r3, [pc, #148] ; (800a0f4 <__swsetup_r+0xd4>)
  25304. 800a05e: 429c cmp r4, r3
  25305. 800a060: d101 bne.n 800a066 <__swsetup_r+0x46>
  25306. 800a062: 68ac ldr r4, [r5, #8]
  25307. 800a064: e7eb b.n 800a03e <__swsetup_r+0x1e>
  25308. 800a066: 4b24 ldr r3, [pc, #144] ; (800a0f8 <__swsetup_r+0xd8>)
  25309. 800a068: 429c cmp r4, r3
  25310. 800a06a: bf08 it eq
  25311. 800a06c: 68ec ldreq r4, [r5, #12]
  25312. 800a06e: e7e6 b.n 800a03e <__swsetup_r+0x1e>
  25313. 800a070: 0758 lsls r0, r3, #29
  25314. 800a072: d512 bpl.n 800a09a <__swsetup_r+0x7a>
  25315. 800a074: 6b61 ldr r1, [r4, #52] ; 0x34
  25316. 800a076: b141 cbz r1, 800a08a <__swsetup_r+0x6a>
  25317. 800a078: f104 0344 add.w r3, r4, #68 ; 0x44
  25318. 800a07c: 4299 cmp r1, r3
  25319. 800a07e: d002 beq.n 800a086 <__swsetup_r+0x66>
  25320. 800a080: 4630 mov r0, r6
  25321. 800a082: f000 fa61 bl 800a548 <_free_r>
  25322. 800a086: 2300 movs r3, #0
  25323. 800a088: 6363 str r3, [r4, #52] ; 0x34
  25324. 800a08a: 89a3 ldrh r3, [r4, #12]
  25325. 800a08c: f023 0324 bic.w r3, r3, #36 ; 0x24
  25326. 800a090: 81a3 strh r3, [r4, #12]
  25327. 800a092: 2300 movs r3, #0
  25328. 800a094: 6063 str r3, [r4, #4]
  25329. 800a096: 6923 ldr r3, [r4, #16]
  25330. 800a098: 6023 str r3, [r4, #0]
  25331. 800a09a: 89a3 ldrh r3, [r4, #12]
  25332. 800a09c: f043 0308 orr.w r3, r3, #8
  25333. 800a0a0: 81a3 strh r3, [r4, #12]
  25334. 800a0a2: 6923 ldr r3, [r4, #16]
  25335. 800a0a4: b94b cbnz r3, 800a0ba <__swsetup_r+0x9a>
  25336. 800a0a6: 89a3 ldrh r3, [r4, #12]
  25337. 800a0a8: f403 7320 and.w r3, r3, #640 ; 0x280
  25338. 800a0ac: f5b3 7f00 cmp.w r3, #512 ; 0x200
  25339. 800a0b0: d003 beq.n 800a0ba <__swsetup_r+0x9a>
  25340. 800a0b2: 4621 mov r1, r4
  25341. 800a0b4: 4630 mov r0, r6
  25342. 800a0b6: f000 fa07 bl 800a4c8 <__smakebuf_r>
  25343. 800a0ba: 89a0 ldrh r0, [r4, #12]
  25344. 800a0bc: f9b4 200c ldrsh.w r2, [r4, #12]
  25345. 800a0c0: f010 0301 ands.w r3, r0, #1
  25346. 800a0c4: d00a beq.n 800a0dc <__swsetup_r+0xbc>
  25347. 800a0c6: 2300 movs r3, #0
  25348. 800a0c8: 60a3 str r3, [r4, #8]
  25349. 800a0ca: 6963 ldr r3, [r4, #20]
  25350. 800a0cc: 425b negs r3, r3
  25351. 800a0ce: 61a3 str r3, [r4, #24]
  25352. 800a0d0: 6923 ldr r3, [r4, #16]
  25353. 800a0d2: b943 cbnz r3, 800a0e6 <__swsetup_r+0xc6>
  25354. 800a0d4: f010 0080 ands.w r0, r0, #128 ; 0x80
  25355. 800a0d8: d1ba bne.n 800a050 <__swsetup_r+0x30>
  25356. 800a0da: bd70 pop {r4, r5, r6, pc}
  25357. 800a0dc: 0781 lsls r1, r0, #30
  25358. 800a0de: bf58 it pl
  25359. 800a0e0: 6963 ldrpl r3, [r4, #20]
  25360. 800a0e2: 60a3 str r3, [r4, #8]
  25361. 800a0e4: e7f4 b.n 800a0d0 <__swsetup_r+0xb0>
  25362. 800a0e6: 2000 movs r0, #0
  25363. 800a0e8: e7f7 b.n 800a0da <__swsetup_r+0xba>
  25364. 800a0ea: bf00 nop
  25365. 800a0ec: 24000184 .word 0x24000184
  25366. 800a0f0: 0800aab4 .word 0x0800aab4
  25367. 800a0f4: 0800aad4 .word 0x0800aad4
  25368. 800a0f8: 0800aa94 .word 0x0800aa94
  25369. 0800a0fc <abort>:
  25370. 800a0fc: b508 push {r3, lr}
  25371. 800a0fe: 2006 movs r0, #6
  25372. 800a100: f000 fb04 bl 800a70c <raise>
  25373. 800a104: 2001 movs r0, #1
  25374. 800a106: f7f7 f8d1 bl 80012ac <_exit>
  25375. ...
  25376. 0800a10c <__sflush_r>:
  25377. 800a10c: 898a ldrh r2, [r1, #12]
  25378. 800a10e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  25379. 800a112: 4605 mov r5, r0
  25380. 800a114: 0710 lsls r0, r2, #28
  25381. 800a116: 460c mov r4, r1
  25382. 800a118: d458 bmi.n 800a1cc <__sflush_r+0xc0>
  25383. 800a11a: 684b ldr r3, [r1, #4]
  25384. 800a11c: 2b00 cmp r3, #0
  25385. 800a11e: dc05 bgt.n 800a12c <__sflush_r+0x20>
  25386. 800a120: 6c0b ldr r3, [r1, #64] ; 0x40
  25387. 800a122: 2b00 cmp r3, #0
  25388. 800a124: dc02 bgt.n 800a12c <__sflush_r+0x20>
  25389. 800a126: 2000 movs r0, #0
  25390. 800a128: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  25391. 800a12c: 6ae6 ldr r6, [r4, #44] ; 0x2c
  25392. 800a12e: 2e00 cmp r6, #0
  25393. 800a130: d0f9 beq.n 800a126 <__sflush_r+0x1a>
  25394. 800a132: 2300 movs r3, #0
  25395. 800a134: f412 5280 ands.w r2, r2, #4096 ; 0x1000
  25396. 800a138: 682f ldr r7, [r5, #0]
  25397. 800a13a: 602b str r3, [r5, #0]
  25398. 800a13c: d032 beq.n 800a1a4 <__sflush_r+0x98>
  25399. 800a13e: 6d60 ldr r0, [r4, #84] ; 0x54
  25400. 800a140: 89a3 ldrh r3, [r4, #12]
  25401. 800a142: 075a lsls r2, r3, #29
  25402. 800a144: d505 bpl.n 800a152 <__sflush_r+0x46>
  25403. 800a146: 6863 ldr r3, [r4, #4]
  25404. 800a148: 1ac0 subs r0, r0, r3
  25405. 800a14a: 6b63 ldr r3, [r4, #52] ; 0x34
  25406. 800a14c: b10b cbz r3, 800a152 <__sflush_r+0x46>
  25407. 800a14e: 6c23 ldr r3, [r4, #64] ; 0x40
  25408. 800a150: 1ac0 subs r0, r0, r3
  25409. 800a152: 2300 movs r3, #0
  25410. 800a154: 4602 mov r2, r0
  25411. 800a156: 6ae6 ldr r6, [r4, #44] ; 0x2c
  25412. 800a158: 6a21 ldr r1, [r4, #32]
  25413. 800a15a: 4628 mov r0, r5
  25414. 800a15c: 47b0 blx r6
  25415. 800a15e: 1c43 adds r3, r0, #1
  25416. 800a160: 89a3 ldrh r3, [r4, #12]
  25417. 800a162: d106 bne.n 800a172 <__sflush_r+0x66>
  25418. 800a164: 6829 ldr r1, [r5, #0]
  25419. 800a166: 291d cmp r1, #29
  25420. 800a168: d82c bhi.n 800a1c4 <__sflush_r+0xb8>
  25421. 800a16a: 4a2a ldr r2, [pc, #168] ; (800a214 <__sflush_r+0x108>)
  25422. 800a16c: 40ca lsrs r2, r1
  25423. 800a16e: 07d6 lsls r6, r2, #31
  25424. 800a170: d528 bpl.n 800a1c4 <__sflush_r+0xb8>
  25425. 800a172: 2200 movs r2, #0
  25426. 800a174: 6062 str r2, [r4, #4]
  25427. 800a176: 04d9 lsls r1, r3, #19
  25428. 800a178: 6922 ldr r2, [r4, #16]
  25429. 800a17a: 6022 str r2, [r4, #0]
  25430. 800a17c: d504 bpl.n 800a188 <__sflush_r+0x7c>
  25431. 800a17e: 1c42 adds r2, r0, #1
  25432. 800a180: d101 bne.n 800a186 <__sflush_r+0x7a>
  25433. 800a182: 682b ldr r3, [r5, #0]
  25434. 800a184: b903 cbnz r3, 800a188 <__sflush_r+0x7c>
  25435. 800a186: 6560 str r0, [r4, #84] ; 0x54
  25436. 800a188: 6b61 ldr r1, [r4, #52] ; 0x34
  25437. 800a18a: 602f str r7, [r5, #0]
  25438. 800a18c: 2900 cmp r1, #0
  25439. 800a18e: d0ca beq.n 800a126 <__sflush_r+0x1a>
  25440. 800a190: f104 0344 add.w r3, r4, #68 ; 0x44
  25441. 800a194: 4299 cmp r1, r3
  25442. 800a196: d002 beq.n 800a19e <__sflush_r+0x92>
  25443. 800a198: 4628 mov r0, r5
  25444. 800a19a: f000 f9d5 bl 800a548 <_free_r>
  25445. 800a19e: 2000 movs r0, #0
  25446. 800a1a0: 6360 str r0, [r4, #52] ; 0x34
  25447. 800a1a2: e7c1 b.n 800a128 <__sflush_r+0x1c>
  25448. 800a1a4: 6a21 ldr r1, [r4, #32]
  25449. 800a1a6: 2301 movs r3, #1
  25450. 800a1a8: 4628 mov r0, r5
  25451. 800a1aa: 47b0 blx r6
  25452. 800a1ac: 1c41 adds r1, r0, #1
  25453. 800a1ae: d1c7 bne.n 800a140 <__sflush_r+0x34>
  25454. 800a1b0: 682b ldr r3, [r5, #0]
  25455. 800a1b2: 2b00 cmp r3, #0
  25456. 800a1b4: d0c4 beq.n 800a140 <__sflush_r+0x34>
  25457. 800a1b6: 2b1d cmp r3, #29
  25458. 800a1b8: d001 beq.n 800a1be <__sflush_r+0xb2>
  25459. 800a1ba: 2b16 cmp r3, #22
  25460. 800a1bc: d101 bne.n 800a1c2 <__sflush_r+0xb6>
  25461. 800a1be: 602f str r7, [r5, #0]
  25462. 800a1c0: e7b1 b.n 800a126 <__sflush_r+0x1a>
  25463. 800a1c2: 89a3 ldrh r3, [r4, #12]
  25464. 800a1c4: f043 0340 orr.w r3, r3, #64 ; 0x40
  25465. 800a1c8: 81a3 strh r3, [r4, #12]
  25466. 800a1ca: e7ad b.n 800a128 <__sflush_r+0x1c>
  25467. 800a1cc: 690f ldr r7, [r1, #16]
  25468. 800a1ce: 2f00 cmp r7, #0
  25469. 800a1d0: d0a9 beq.n 800a126 <__sflush_r+0x1a>
  25470. 800a1d2: 0793 lsls r3, r2, #30
  25471. 800a1d4: 680e ldr r6, [r1, #0]
  25472. 800a1d6: bf08 it eq
  25473. 800a1d8: 694b ldreq r3, [r1, #20]
  25474. 800a1da: 600f str r7, [r1, #0]
  25475. 800a1dc: bf18 it ne
  25476. 800a1de: 2300 movne r3, #0
  25477. 800a1e0: eba6 0807 sub.w r8, r6, r7
  25478. 800a1e4: 608b str r3, [r1, #8]
  25479. 800a1e6: f1b8 0f00 cmp.w r8, #0
  25480. 800a1ea: dd9c ble.n 800a126 <__sflush_r+0x1a>
  25481. 800a1ec: 6a21 ldr r1, [r4, #32]
  25482. 800a1ee: 6aa6 ldr r6, [r4, #40] ; 0x28
  25483. 800a1f0: 4643 mov r3, r8
  25484. 800a1f2: 463a mov r2, r7
  25485. 800a1f4: 4628 mov r0, r5
  25486. 800a1f6: 47b0 blx r6
  25487. 800a1f8: 2800 cmp r0, #0
  25488. 800a1fa: dc06 bgt.n 800a20a <__sflush_r+0xfe>
  25489. 800a1fc: 89a3 ldrh r3, [r4, #12]
  25490. 800a1fe: f043 0340 orr.w r3, r3, #64 ; 0x40
  25491. 800a202: 81a3 strh r3, [r4, #12]
  25492. 800a204: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
  25493. 800a208: e78e b.n 800a128 <__sflush_r+0x1c>
  25494. 800a20a: 4407 add r7, r0
  25495. 800a20c: eba8 0800 sub.w r8, r8, r0
  25496. 800a210: e7e9 b.n 800a1e6 <__sflush_r+0xda>
  25497. 800a212: bf00 nop
  25498. 800a214: 20400001 .word 0x20400001
  25499. 0800a218 <_fflush_r>:
  25500. 800a218: b538 push {r3, r4, r5, lr}
  25501. 800a21a: 690b ldr r3, [r1, #16]
  25502. 800a21c: 4605 mov r5, r0
  25503. 800a21e: 460c mov r4, r1
  25504. 800a220: b913 cbnz r3, 800a228 <_fflush_r+0x10>
  25505. 800a222: 2500 movs r5, #0
  25506. 800a224: 4628 mov r0, r5
  25507. 800a226: bd38 pop {r3, r4, r5, pc}
  25508. 800a228: b118 cbz r0, 800a232 <_fflush_r+0x1a>
  25509. 800a22a: 6983 ldr r3, [r0, #24]
  25510. 800a22c: b90b cbnz r3, 800a232 <_fflush_r+0x1a>
  25511. 800a22e: f000 f887 bl 800a340 <__sinit>
  25512. 800a232: 4b14 ldr r3, [pc, #80] ; (800a284 <_fflush_r+0x6c>)
  25513. 800a234: 429c cmp r4, r3
  25514. 800a236: d11b bne.n 800a270 <_fflush_r+0x58>
  25515. 800a238: 686c ldr r4, [r5, #4]
  25516. 800a23a: f9b4 300c ldrsh.w r3, [r4, #12]
  25517. 800a23e: 2b00 cmp r3, #0
  25518. 800a240: d0ef beq.n 800a222 <_fflush_r+0xa>
  25519. 800a242: 6e62 ldr r2, [r4, #100] ; 0x64
  25520. 800a244: 07d0 lsls r0, r2, #31
  25521. 800a246: d404 bmi.n 800a252 <_fflush_r+0x3a>
  25522. 800a248: 0599 lsls r1, r3, #22
  25523. 800a24a: d402 bmi.n 800a252 <_fflush_r+0x3a>
  25524. 800a24c: 6da0 ldr r0, [r4, #88] ; 0x58
  25525. 800a24e: f000 f915 bl 800a47c <__retarget_lock_acquire_recursive>
  25526. 800a252: 4628 mov r0, r5
  25527. 800a254: 4621 mov r1, r4
  25528. 800a256: f7ff ff59 bl 800a10c <__sflush_r>
  25529. 800a25a: 6e63 ldr r3, [r4, #100] ; 0x64
  25530. 800a25c: 07da lsls r2, r3, #31
  25531. 800a25e: 4605 mov r5, r0
  25532. 800a260: d4e0 bmi.n 800a224 <_fflush_r+0xc>
  25533. 800a262: 89a3 ldrh r3, [r4, #12]
  25534. 800a264: 059b lsls r3, r3, #22
  25535. 800a266: d4dd bmi.n 800a224 <_fflush_r+0xc>
  25536. 800a268: 6da0 ldr r0, [r4, #88] ; 0x58
  25537. 800a26a: f000 f908 bl 800a47e <__retarget_lock_release_recursive>
  25538. 800a26e: e7d9 b.n 800a224 <_fflush_r+0xc>
  25539. 800a270: 4b05 ldr r3, [pc, #20] ; (800a288 <_fflush_r+0x70>)
  25540. 800a272: 429c cmp r4, r3
  25541. 800a274: d101 bne.n 800a27a <_fflush_r+0x62>
  25542. 800a276: 68ac ldr r4, [r5, #8]
  25543. 800a278: e7df b.n 800a23a <_fflush_r+0x22>
  25544. 800a27a: 4b04 ldr r3, [pc, #16] ; (800a28c <_fflush_r+0x74>)
  25545. 800a27c: 429c cmp r4, r3
  25546. 800a27e: bf08 it eq
  25547. 800a280: 68ec ldreq r4, [r5, #12]
  25548. 800a282: e7da b.n 800a23a <_fflush_r+0x22>
  25549. 800a284: 0800aab4 .word 0x0800aab4
  25550. 800a288: 0800aad4 .word 0x0800aad4
  25551. 800a28c: 0800aa94 .word 0x0800aa94
  25552. 0800a290 <std>:
  25553. 800a290: 2300 movs r3, #0
  25554. 800a292: b510 push {r4, lr}
  25555. 800a294: 4604 mov r4, r0
  25556. 800a296: e9c0 3300 strd r3, r3, [r0]
  25557. 800a29a: e9c0 3304 strd r3, r3, [r0, #16]
  25558. 800a29e: 6083 str r3, [r0, #8]
  25559. 800a2a0: 8181 strh r1, [r0, #12]
  25560. 800a2a2: 6643 str r3, [r0, #100] ; 0x64
  25561. 800a2a4: 81c2 strh r2, [r0, #14]
  25562. 800a2a6: 6183 str r3, [r0, #24]
  25563. 800a2a8: 4619 mov r1, r3
  25564. 800a2aa: 2208 movs r2, #8
  25565. 800a2ac: 305c adds r0, #92 ; 0x5c
  25566. 800a2ae: f7ff fb6f bl 8009990 <memset>
  25567. 800a2b2: 4b05 ldr r3, [pc, #20] ; (800a2c8 <std+0x38>)
  25568. 800a2b4: 6263 str r3, [r4, #36] ; 0x24
  25569. 800a2b6: 4b05 ldr r3, [pc, #20] ; (800a2cc <std+0x3c>)
  25570. 800a2b8: 62a3 str r3, [r4, #40] ; 0x28
  25571. 800a2ba: 4b05 ldr r3, [pc, #20] ; (800a2d0 <std+0x40>)
  25572. 800a2bc: 62e3 str r3, [r4, #44] ; 0x2c
  25573. 800a2be: 4b05 ldr r3, [pc, #20] ; (800a2d4 <std+0x44>)
  25574. 800a2c0: 6224 str r4, [r4, #32]
  25575. 800a2c2: 6323 str r3, [r4, #48] ; 0x30
  25576. 800a2c4: bd10 pop {r4, pc}
  25577. 800a2c6: bf00 nop
  25578. 800a2c8: 0800a745 .word 0x0800a745
  25579. 800a2cc: 0800a767 .word 0x0800a767
  25580. 800a2d0: 0800a79f .word 0x0800a79f
  25581. 800a2d4: 0800a7c3 .word 0x0800a7c3
  25582. 0800a2d8 <_cleanup_r>:
  25583. 800a2d8: 4901 ldr r1, [pc, #4] ; (800a2e0 <_cleanup_r+0x8>)
  25584. 800a2da: f000 b8af b.w 800a43c <_fwalk_reent>
  25585. 800a2de: bf00 nop
  25586. 800a2e0: 0800a219 .word 0x0800a219
  25587. 0800a2e4 <__sfmoreglue>:
  25588. 800a2e4: b570 push {r4, r5, r6, lr}
  25589. 800a2e6: 1e4a subs r2, r1, #1
  25590. 800a2e8: 2568 movs r5, #104 ; 0x68
  25591. 800a2ea: 4355 muls r5, r2
  25592. 800a2ec: 460e mov r6, r1
  25593. 800a2ee: f105 0174 add.w r1, r5, #116 ; 0x74
  25594. 800a2f2: f000 f979 bl 800a5e8 <_malloc_r>
  25595. 800a2f6: 4604 mov r4, r0
  25596. 800a2f8: b140 cbz r0, 800a30c <__sfmoreglue+0x28>
  25597. 800a2fa: 2100 movs r1, #0
  25598. 800a2fc: e9c0 1600 strd r1, r6, [r0]
  25599. 800a300: 300c adds r0, #12
  25600. 800a302: 60a0 str r0, [r4, #8]
  25601. 800a304: f105 0268 add.w r2, r5, #104 ; 0x68
  25602. 800a308: f7ff fb42 bl 8009990 <memset>
  25603. 800a30c: 4620 mov r0, r4
  25604. 800a30e: bd70 pop {r4, r5, r6, pc}
  25605. 0800a310 <__sfp_lock_acquire>:
  25606. 800a310: 4801 ldr r0, [pc, #4] ; (800a318 <__sfp_lock_acquire+0x8>)
  25607. 800a312: f000 b8b3 b.w 800a47c <__retarget_lock_acquire_recursive>
  25608. 800a316: bf00 nop
  25609. 800a318: 24002d10 .word 0x24002d10
  25610. 0800a31c <__sfp_lock_release>:
  25611. 800a31c: 4801 ldr r0, [pc, #4] ; (800a324 <__sfp_lock_release+0x8>)
  25612. 800a31e: f000 b8ae b.w 800a47e <__retarget_lock_release_recursive>
  25613. 800a322: bf00 nop
  25614. 800a324: 24002d10 .word 0x24002d10
  25615. 0800a328 <__sinit_lock_acquire>:
  25616. 800a328: 4801 ldr r0, [pc, #4] ; (800a330 <__sinit_lock_acquire+0x8>)
  25617. 800a32a: f000 b8a7 b.w 800a47c <__retarget_lock_acquire_recursive>
  25618. 800a32e: bf00 nop
  25619. 800a330: 24002d0b .word 0x24002d0b
  25620. 0800a334 <__sinit_lock_release>:
  25621. 800a334: 4801 ldr r0, [pc, #4] ; (800a33c <__sinit_lock_release+0x8>)
  25622. 800a336: f000 b8a2 b.w 800a47e <__retarget_lock_release_recursive>
  25623. 800a33a: bf00 nop
  25624. 800a33c: 24002d0b .word 0x24002d0b
  25625. 0800a340 <__sinit>:
  25626. 800a340: b510 push {r4, lr}
  25627. 800a342: 4604 mov r4, r0
  25628. 800a344: f7ff fff0 bl 800a328 <__sinit_lock_acquire>
  25629. 800a348: 69a3 ldr r3, [r4, #24]
  25630. 800a34a: b11b cbz r3, 800a354 <__sinit+0x14>
  25631. 800a34c: e8bd 4010 ldmia.w sp!, {r4, lr}
  25632. 800a350: f7ff bff0 b.w 800a334 <__sinit_lock_release>
  25633. 800a354: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48
  25634. 800a358: 6523 str r3, [r4, #80] ; 0x50
  25635. 800a35a: 4b13 ldr r3, [pc, #76] ; (800a3a8 <__sinit+0x68>)
  25636. 800a35c: 4a13 ldr r2, [pc, #76] ; (800a3ac <__sinit+0x6c>)
  25637. 800a35e: 681b ldr r3, [r3, #0]
  25638. 800a360: 62a2 str r2, [r4, #40] ; 0x28
  25639. 800a362: 42a3 cmp r3, r4
  25640. 800a364: bf04 itt eq
  25641. 800a366: 2301 moveq r3, #1
  25642. 800a368: 61a3 streq r3, [r4, #24]
  25643. 800a36a: 4620 mov r0, r4
  25644. 800a36c: f000 f820 bl 800a3b0 <__sfp>
  25645. 800a370: 6060 str r0, [r4, #4]
  25646. 800a372: 4620 mov r0, r4
  25647. 800a374: f000 f81c bl 800a3b0 <__sfp>
  25648. 800a378: 60a0 str r0, [r4, #8]
  25649. 800a37a: 4620 mov r0, r4
  25650. 800a37c: f000 f818 bl 800a3b0 <__sfp>
  25651. 800a380: 2200 movs r2, #0
  25652. 800a382: 60e0 str r0, [r4, #12]
  25653. 800a384: 2104 movs r1, #4
  25654. 800a386: 6860 ldr r0, [r4, #4]
  25655. 800a388: f7ff ff82 bl 800a290 <std>
  25656. 800a38c: 68a0 ldr r0, [r4, #8]
  25657. 800a38e: 2201 movs r2, #1
  25658. 800a390: 2109 movs r1, #9
  25659. 800a392: f7ff ff7d bl 800a290 <std>
  25660. 800a396: 68e0 ldr r0, [r4, #12]
  25661. 800a398: 2202 movs r2, #2
  25662. 800a39a: 2112 movs r1, #18
  25663. 800a39c: f7ff ff78 bl 800a290 <std>
  25664. 800a3a0: 2301 movs r3, #1
  25665. 800a3a2: 61a3 str r3, [r4, #24]
  25666. 800a3a4: e7d2 b.n 800a34c <__sinit+0xc>
  25667. 800a3a6: bf00 nop
  25668. 800a3a8: 0800aa5c .word 0x0800aa5c
  25669. 800a3ac: 0800a2d9 .word 0x0800a2d9
  25670. 0800a3b0 <__sfp>:
  25671. 800a3b0: b5f8 push {r3, r4, r5, r6, r7, lr}
  25672. 800a3b2: 4607 mov r7, r0
  25673. 800a3b4: f7ff ffac bl 800a310 <__sfp_lock_acquire>
  25674. 800a3b8: 4b1e ldr r3, [pc, #120] ; (800a434 <__sfp+0x84>)
  25675. 800a3ba: 681e ldr r6, [r3, #0]
  25676. 800a3bc: 69b3 ldr r3, [r6, #24]
  25677. 800a3be: b913 cbnz r3, 800a3c6 <__sfp+0x16>
  25678. 800a3c0: 4630 mov r0, r6
  25679. 800a3c2: f7ff ffbd bl 800a340 <__sinit>
  25680. 800a3c6: 3648 adds r6, #72 ; 0x48
  25681. 800a3c8: e9d6 3401 ldrd r3, r4, [r6, #4]
  25682. 800a3cc: 3b01 subs r3, #1
  25683. 800a3ce: d503 bpl.n 800a3d8 <__sfp+0x28>
  25684. 800a3d0: 6833 ldr r3, [r6, #0]
  25685. 800a3d2: b30b cbz r3, 800a418 <__sfp+0x68>
  25686. 800a3d4: 6836 ldr r6, [r6, #0]
  25687. 800a3d6: e7f7 b.n 800a3c8 <__sfp+0x18>
  25688. 800a3d8: f9b4 500c ldrsh.w r5, [r4, #12]
  25689. 800a3dc: b9d5 cbnz r5, 800a414 <__sfp+0x64>
  25690. 800a3de: 4b16 ldr r3, [pc, #88] ; (800a438 <__sfp+0x88>)
  25691. 800a3e0: 60e3 str r3, [r4, #12]
  25692. 800a3e2: f104 0058 add.w r0, r4, #88 ; 0x58
  25693. 800a3e6: 6665 str r5, [r4, #100] ; 0x64
  25694. 800a3e8: f000 f847 bl 800a47a <__retarget_lock_init_recursive>
  25695. 800a3ec: f7ff ff96 bl 800a31c <__sfp_lock_release>
  25696. 800a3f0: e9c4 5501 strd r5, r5, [r4, #4]
  25697. 800a3f4: e9c4 5504 strd r5, r5, [r4, #16]
  25698. 800a3f8: 6025 str r5, [r4, #0]
  25699. 800a3fa: 61a5 str r5, [r4, #24]
  25700. 800a3fc: 2208 movs r2, #8
  25701. 800a3fe: 4629 mov r1, r5
  25702. 800a400: f104 005c add.w r0, r4, #92 ; 0x5c
  25703. 800a404: f7ff fac4 bl 8009990 <memset>
  25704. 800a408: e9c4 550d strd r5, r5, [r4, #52] ; 0x34
  25705. 800a40c: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48
  25706. 800a410: 4620 mov r0, r4
  25707. 800a412: bdf8 pop {r3, r4, r5, r6, r7, pc}
  25708. 800a414: 3468 adds r4, #104 ; 0x68
  25709. 800a416: e7d9 b.n 800a3cc <__sfp+0x1c>
  25710. 800a418: 2104 movs r1, #4
  25711. 800a41a: 4638 mov r0, r7
  25712. 800a41c: f7ff ff62 bl 800a2e4 <__sfmoreglue>
  25713. 800a420: 4604 mov r4, r0
  25714. 800a422: 6030 str r0, [r6, #0]
  25715. 800a424: 2800 cmp r0, #0
  25716. 800a426: d1d5 bne.n 800a3d4 <__sfp+0x24>
  25717. 800a428: f7ff ff78 bl 800a31c <__sfp_lock_release>
  25718. 800a42c: 230c movs r3, #12
  25719. 800a42e: 603b str r3, [r7, #0]
  25720. 800a430: e7ee b.n 800a410 <__sfp+0x60>
  25721. 800a432: bf00 nop
  25722. 800a434: 0800aa5c .word 0x0800aa5c
  25723. 800a438: ffff0001 .word 0xffff0001
  25724. 0800a43c <_fwalk_reent>:
  25725. 800a43c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  25726. 800a440: 4606 mov r6, r0
  25727. 800a442: 4688 mov r8, r1
  25728. 800a444: f100 0448 add.w r4, r0, #72 ; 0x48
  25729. 800a448: 2700 movs r7, #0
  25730. 800a44a: e9d4 9501 ldrd r9, r5, [r4, #4]
  25731. 800a44e: f1b9 0901 subs.w r9, r9, #1
  25732. 800a452: d505 bpl.n 800a460 <_fwalk_reent+0x24>
  25733. 800a454: 6824 ldr r4, [r4, #0]
  25734. 800a456: 2c00 cmp r4, #0
  25735. 800a458: d1f7 bne.n 800a44a <_fwalk_reent+0xe>
  25736. 800a45a: 4638 mov r0, r7
  25737. 800a45c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  25738. 800a460: 89ab ldrh r3, [r5, #12]
  25739. 800a462: 2b01 cmp r3, #1
  25740. 800a464: d907 bls.n 800a476 <_fwalk_reent+0x3a>
  25741. 800a466: f9b5 300e ldrsh.w r3, [r5, #14]
  25742. 800a46a: 3301 adds r3, #1
  25743. 800a46c: d003 beq.n 800a476 <_fwalk_reent+0x3a>
  25744. 800a46e: 4629 mov r1, r5
  25745. 800a470: 4630 mov r0, r6
  25746. 800a472: 47c0 blx r8
  25747. 800a474: 4307 orrs r7, r0
  25748. 800a476: 3568 adds r5, #104 ; 0x68
  25749. 800a478: e7e9 b.n 800a44e <_fwalk_reent+0x12>
  25750. 0800a47a <__retarget_lock_init_recursive>:
  25751. 800a47a: 4770 bx lr
  25752. 0800a47c <__retarget_lock_acquire_recursive>:
  25753. 800a47c: 4770 bx lr
  25754. 0800a47e <__retarget_lock_release_recursive>:
  25755. 800a47e: 4770 bx lr
  25756. 0800a480 <__swhatbuf_r>:
  25757. 800a480: b570 push {r4, r5, r6, lr}
  25758. 800a482: 460e mov r6, r1
  25759. 800a484: f9b1 100e ldrsh.w r1, [r1, #14]
  25760. 800a488: 2900 cmp r1, #0
  25761. 800a48a: b096 sub sp, #88 ; 0x58
  25762. 800a48c: 4614 mov r4, r2
  25763. 800a48e: 461d mov r5, r3
  25764. 800a490: da07 bge.n 800a4a2 <__swhatbuf_r+0x22>
  25765. 800a492: 2300 movs r3, #0
  25766. 800a494: 602b str r3, [r5, #0]
  25767. 800a496: 89b3 ldrh r3, [r6, #12]
  25768. 800a498: 061a lsls r2, r3, #24
  25769. 800a49a: d410 bmi.n 800a4be <__swhatbuf_r+0x3e>
  25770. 800a49c: f44f 6380 mov.w r3, #1024 ; 0x400
  25771. 800a4a0: e00e b.n 800a4c0 <__swhatbuf_r+0x40>
  25772. 800a4a2: 466a mov r2, sp
  25773. 800a4a4: f000 f9b4 bl 800a810 <_fstat_r>
  25774. 800a4a8: 2800 cmp r0, #0
  25775. 800a4aa: dbf2 blt.n 800a492 <__swhatbuf_r+0x12>
  25776. 800a4ac: 9a01 ldr r2, [sp, #4]
  25777. 800a4ae: f402 4270 and.w r2, r2, #61440 ; 0xf000
  25778. 800a4b2: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000
  25779. 800a4b6: 425a negs r2, r3
  25780. 800a4b8: 415a adcs r2, r3
  25781. 800a4ba: 602a str r2, [r5, #0]
  25782. 800a4bc: e7ee b.n 800a49c <__swhatbuf_r+0x1c>
  25783. 800a4be: 2340 movs r3, #64 ; 0x40
  25784. 800a4c0: 2000 movs r0, #0
  25785. 800a4c2: 6023 str r3, [r4, #0]
  25786. 800a4c4: b016 add sp, #88 ; 0x58
  25787. 800a4c6: bd70 pop {r4, r5, r6, pc}
  25788. 0800a4c8 <__smakebuf_r>:
  25789. 800a4c8: 898b ldrh r3, [r1, #12]
  25790. 800a4ca: b573 push {r0, r1, r4, r5, r6, lr}
  25791. 800a4cc: 079d lsls r5, r3, #30
  25792. 800a4ce: 4606 mov r6, r0
  25793. 800a4d0: 460c mov r4, r1
  25794. 800a4d2: d507 bpl.n 800a4e4 <__smakebuf_r+0x1c>
  25795. 800a4d4: f104 0347 add.w r3, r4, #71 ; 0x47
  25796. 800a4d8: 6023 str r3, [r4, #0]
  25797. 800a4da: 6123 str r3, [r4, #16]
  25798. 800a4dc: 2301 movs r3, #1
  25799. 800a4de: 6163 str r3, [r4, #20]
  25800. 800a4e0: b002 add sp, #8
  25801. 800a4e2: bd70 pop {r4, r5, r6, pc}
  25802. 800a4e4: ab01 add r3, sp, #4
  25803. 800a4e6: 466a mov r2, sp
  25804. 800a4e8: f7ff ffca bl 800a480 <__swhatbuf_r>
  25805. 800a4ec: 9900 ldr r1, [sp, #0]
  25806. 800a4ee: 4605 mov r5, r0
  25807. 800a4f0: 4630 mov r0, r6
  25808. 800a4f2: f000 f879 bl 800a5e8 <_malloc_r>
  25809. 800a4f6: b948 cbnz r0, 800a50c <__smakebuf_r+0x44>
  25810. 800a4f8: f9b4 300c ldrsh.w r3, [r4, #12]
  25811. 800a4fc: 059a lsls r2, r3, #22
  25812. 800a4fe: d4ef bmi.n 800a4e0 <__smakebuf_r+0x18>
  25813. 800a500: f023 0303 bic.w r3, r3, #3
  25814. 800a504: f043 0302 orr.w r3, r3, #2
  25815. 800a508: 81a3 strh r3, [r4, #12]
  25816. 800a50a: e7e3 b.n 800a4d4 <__smakebuf_r+0xc>
  25817. 800a50c: 4b0d ldr r3, [pc, #52] ; (800a544 <__smakebuf_r+0x7c>)
  25818. 800a50e: 62b3 str r3, [r6, #40] ; 0x28
  25819. 800a510: 89a3 ldrh r3, [r4, #12]
  25820. 800a512: 6020 str r0, [r4, #0]
  25821. 800a514: f043 0380 orr.w r3, r3, #128 ; 0x80
  25822. 800a518: 81a3 strh r3, [r4, #12]
  25823. 800a51a: 9b00 ldr r3, [sp, #0]
  25824. 800a51c: 6163 str r3, [r4, #20]
  25825. 800a51e: 9b01 ldr r3, [sp, #4]
  25826. 800a520: 6120 str r0, [r4, #16]
  25827. 800a522: b15b cbz r3, 800a53c <__smakebuf_r+0x74>
  25828. 800a524: f9b4 100e ldrsh.w r1, [r4, #14]
  25829. 800a528: 4630 mov r0, r6
  25830. 800a52a: f000 f983 bl 800a834 <_isatty_r>
  25831. 800a52e: b128 cbz r0, 800a53c <__smakebuf_r+0x74>
  25832. 800a530: 89a3 ldrh r3, [r4, #12]
  25833. 800a532: f023 0303 bic.w r3, r3, #3
  25834. 800a536: f043 0301 orr.w r3, r3, #1
  25835. 800a53a: 81a3 strh r3, [r4, #12]
  25836. 800a53c: 89a0 ldrh r0, [r4, #12]
  25837. 800a53e: 4305 orrs r5, r0
  25838. 800a540: 81a5 strh r5, [r4, #12]
  25839. 800a542: e7cd b.n 800a4e0 <__smakebuf_r+0x18>
  25840. 800a544: 0800a2d9 .word 0x0800a2d9
  25841. 0800a548 <_free_r>:
  25842. 800a548: b537 push {r0, r1, r2, r4, r5, lr}
  25843. 800a54a: 2900 cmp r1, #0
  25844. 800a54c: d048 beq.n 800a5e0 <_free_r+0x98>
  25845. 800a54e: f851 3c04 ldr.w r3, [r1, #-4]
  25846. 800a552: 9001 str r0, [sp, #4]
  25847. 800a554: 2b00 cmp r3, #0
  25848. 800a556: f1a1 0404 sub.w r4, r1, #4
  25849. 800a55a: bfb8 it lt
  25850. 800a55c: 18e4 addlt r4, r4, r3
  25851. 800a55e: f000 f98b bl 800a878 <__malloc_lock>
  25852. 800a562: 4a20 ldr r2, [pc, #128] ; (800a5e4 <_free_r+0x9c>)
  25853. 800a564: 9801 ldr r0, [sp, #4]
  25854. 800a566: 6813 ldr r3, [r2, #0]
  25855. 800a568: 4615 mov r5, r2
  25856. 800a56a: b933 cbnz r3, 800a57a <_free_r+0x32>
  25857. 800a56c: 6063 str r3, [r4, #4]
  25858. 800a56e: 6014 str r4, [r2, #0]
  25859. 800a570: b003 add sp, #12
  25860. 800a572: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
  25861. 800a576: f000 b985 b.w 800a884 <__malloc_unlock>
  25862. 800a57a: 42a3 cmp r3, r4
  25863. 800a57c: d90b bls.n 800a596 <_free_r+0x4e>
  25864. 800a57e: 6821 ldr r1, [r4, #0]
  25865. 800a580: 1862 adds r2, r4, r1
  25866. 800a582: 4293 cmp r3, r2
  25867. 800a584: bf04 itt eq
  25868. 800a586: 681a ldreq r2, [r3, #0]
  25869. 800a588: 685b ldreq r3, [r3, #4]
  25870. 800a58a: 6063 str r3, [r4, #4]
  25871. 800a58c: bf04 itt eq
  25872. 800a58e: 1852 addeq r2, r2, r1
  25873. 800a590: 6022 streq r2, [r4, #0]
  25874. 800a592: 602c str r4, [r5, #0]
  25875. 800a594: e7ec b.n 800a570 <_free_r+0x28>
  25876. 800a596: 461a mov r2, r3
  25877. 800a598: 685b ldr r3, [r3, #4]
  25878. 800a59a: b10b cbz r3, 800a5a0 <_free_r+0x58>
  25879. 800a59c: 42a3 cmp r3, r4
  25880. 800a59e: d9fa bls.n 800a596 <_free_r+0x4e>
  25881. 800a5a0: 6811 ldr r1, [r2, #0]
  25882. 800a5a2: 1855 adds r5, r2, r1
  25883. 800a5a4: 42a5 cmp r5, r4
  25884. 800a5a6: d10b bne.n 800a5c0 <_free_r+0x78>
  25885. 800a5a8: 6824 ldr r4, [r4, #0]
  25886. 800a5aa: 4421 add r1, r4
  25887. 800a5ac: 1854 adds r4, r2, r1
  25888. 800a5ae: 42a3 cmp r3, r4
  25889. 800a5b0: 6011 str r1, [r2, #0]
  25890. 800a5b2: d1dd bne.n 800a570 <_free_r+0x28>
  25891. 800a5b4: 681c ldr r4, [r3, #0]
  25892. 800a5b6: 685b ldr r3, [r3, #4]
  25893. 800a5b8: 6053 str r3, [r2, #4]
  25894. 800a5ba: 4421 add r1, r4
  25895. 800a5bc: 6011 str r1, [r2, #0]
  25896. 800a5be: e7d7 b.n 800a570 <_free_r+0x28>
  25897. 800a5c0: d902 bls.n 800a5c8 <_free_r+0x80>
  25898. 800a5c2: 230c movs r3, #12
  25899. 800a5c4: 6003 str r3, [r0, #0]
  25900. 800a5c6: e7d3 b.n 800a570 <_free_r+0x28>
  25901. 800a5c8: 6825 ldr r5, [r4, #0]
  25902. 800a5ca: 1961 adds r1, r4, r5
  25903. 800a5cc: 428b cmp r3, r1
  25904. 800a5ce: bf04 itt eq
  25905. 800a5d0: 6819 ldreq r1, [r3, #0]
  25906. 800a5d2: 685b ldreq r3, [r3, #4]
  25907. 800a5d4: 6063 str r3, [r4, #4]
  25908. 800a5d6: bf04 itt eq
  25909. 800a5d8: 1949 addeq r1, r1, r5
  25910. 800a5da: 6021 streq r1, [r4, #0]
  25911. 800a5dc: 6054 str r4, [r2, #4]
  25912. 800a5de: e7c7 b.n 800a570 <_free_r+0x28>
  25913. 800a5e0: b003 add sp, #12
  25914. 800a5e2: bd30 pop {r4, r5, pc}
  25915. 800a5e4: 240013d8 .word 0x240013d8
  25916. 0800a5e8 <_malloc_r>:
  25917. 800a5e8: b5f8 push {r3, r4, r5, r6, r7, lr}
  25918. 800a5ea: 1ccd adds r5, r1, #3
  25919. 800a5ec: f025 0503 bic.w r5, r5, #3
  25920. 800a5f0: 3508 adds r5, #8
  25921. 800a5f2: 2d0c cmp r5, #12
  25922. 800a5f4: bf38 it cc
  25923. 800a5f6: 250c movcc r5, #12
  25924. 800a5f8: 2d00 cmp r5, #0
  25925. 800a5fa: 4606 mov r6, r0
  25926. 800a5fc: db01 blt.n 800a602 <_malloc_r+0x1a>
  25927. 800a5fe: 42a9 cmp r1, r5
  25928. 800a600: d903 bls.n 800a60a <_malloc_r+0x22>
  25929. 800a602: 230c movs r3, #12
  25930. 800a604: 6033 str r3, [r6, #0]
  25931. 800a606: 2000 movs r0, #0
  25932. 800a608: bdf8 pop {r3, r4, r5, r6, r7, pc}
  25933. 800a60a: f000 f935 bl 800a878 <__malloc_lock>
  25934. 800a60e: 4921 ldr r1, [pc, #132] ; (800a694 <_malloc_r+0xac>)
  25935. 800a610: 680a ldr r2, [r1, #0]
  25936. 800a612: 4614 mov r4, r2
  25937. 800a614: b99c cbnz r4, 800a63e <_malloc_r+0x56>
  25938. 800a616: 4f20 ldr r7, [pc, #128] ; (800a698 <_malloc_r+0xb0>)
  25939. 800a618: 683b ldr r3, [r7, #0]
  25940. 800a61a: b923 cbnz r3, 800a626 <_malloc_r+0x3e>
  25941. 800a61c: 4621 mov r1, r4
  25942. 800a61e: 4630 mov r0, r6
  25943. 800a620: f000 f83c bl 800a69c <_sbrk_r>
  25944. 800a624: 6038 str r0, [r7, #0]
  25945. 800a626: 4629 mov r1, r5
  25946. 800a628: 4630 mov r0, r6
  25947. 800a62a: f000 f837 bl 800a69c <_sbrk_r>
  25948. 800a62e: 1c43 adds r3, r0, #1
  25949. 800a630: d123 bne.n 800a67a <_malloc_r+0x92>
  25950. 800a632: 230c movs r3, #12
  25951. 800a634: 6033 str r3, [r6, #0]
  25952. 800a636: 4630 mov r0, r6
  25953. 800a638: f000 f924 bl 800a884 <__malloc_unlock>
  25954. 800a63c: e7e3 b.n 800a606 <_malloc_r+0x1e>
  25955. 800a63e: 6823 ldr r3, [r4, #0]
  25956. 800a640: 1b5b subs r3, r3, r5
  25957. 800a642: d417 bmi.n 800a674 <_malloc_r+0x8c>
  25958. 800a644: 2b0b cmp r3, #11
  25959. 800a646: d903 bls.n 800a650 <_malloc_r+0x68>
  25960. 800a648: 6023 str r3, [r4, #0]
  25961. 800a64a: 441c add r4, r3
  25962. 800a64c: 6025 str r5, [r4, #0]
  25963. 800a64e: e004 b.n 800a65a <_malloc_r+0x72>
  25964. 800a650: 6863 ldr r3, [r4, #4]
  25965. 800a652: 42a2 cmp r2, r4
  25966. 800a654: bf0c ite eq
  25967. 800a656: 600b streq r3, [r1, #0]
  25968. 800a658: 6053 strne r3, [r2, #4]
  25969. 800a65a: 4630 mov r0, r6
  25970. 800a65c: f000 f912 bl 800a884 <__malloc_unlock>
  25971. 800a660: f104 000b add.w r0, r4, #11
  25972. 800a664: 1d23 adds r3, r4, #4
  25973. 800a666: f020 0007 bic.w r0, r0, #7
  25974. 800a66a: 1ac2 subs r2, r0, r3
  25975. 800a66c: d0cc beq.n 800a608 <_malloc_r+0x20>
  25976. 800a66e: 1a1b subs r3, r3, r0
  25977. 800a670: 50a3 str r3, [r4, r2]
  25978. 800a672: e7c9 b.n 800a608 <_malloc_r+0x20>
  25979. 800a674: 4622 mov r2, r4
  25980. 800a676: 6864 ldr r4, [r4, #4]
  25981. 800a678: e7cc b.n 800a614 <_malloc_r+0x2c>
  25982. 800a67a: 1cc4 adds r4, r0, #3
  25983. 800a67c: f024 0403 bic.w r4, r4, #3
  25984. 800a680: 42a0 cmp r0, r4
  25985. 800a682: d0e3 beq.n 800a64c <_malloc_r+0x64>
  25986. 800a684: 1a21 subs r1, r4, r0
  25987. 800a686: 4630 mov r0, r6
  25988. 800a688: f000 f808 bl 800a69c <_sbrk_r>
  25989. 800a68c: 3001 adds r0, #1
  25990. 800a68e: d1dd bne.n 800a64c <_malloc_r+0x64>
  25991. 800a690: e7cf b.n 800a632 <_malloc_r+0x4a>
  25992. 800a692: bf00 nop
  25993. 800a694: 240013d8 .word 0x240013d8
  25994. 800a698: 240013dc .word 0x240013dc
  25995. 0800a69c <_sbrk_r>:
  25996. 800a69c: b538 push {r3, r4, r5, lr}
  25997. 800a69e: 4d06 ldr r5, [pc, #24] ; (800a6b8 <_sbrk_r+0x1c>)
  25998. 800a6a0: 2300 movs r3, #0
  25999. 800a6a2: 4604 mov r4, r0
  26000. 800a6a4: 4608 mov r0, r1
  26001. 800a6a6: 602b str r3, [r5, #0]
  26002. 800a6a8: f7f6 fe78 bl 800139c <_sbrk>
  26003. 800a6ac: 1c43 adds r3, r0, #1
  26004. 800a6ae: d102 bne.n 800a6b6 <_sbrk_r+0x1a>
  26005. 800a6b0: 682b ldr r3, [r5, #0]
  26006. 800a6b2: b103 cbz r3, 800a6b6 <_sbrk_r+0x1a>
  26007. 800a6b4: 6023 str r3, [r4, #0]
  26008. 800a6b6: bd38 pop {r3, r4, r5, pc}
  26009. 800a6b8: 24002d14 .word 0x24002d14
  26010. 0800a6bc <_raise_r>:
  26011. 800a6bc: 291f cmp r1, #31
  26012. 800a6be: b538 push {r3, r4, r5, lr}
  26013. 800a6c0: 4604 mov r4, r0
  26014. 800a6c2: 460d mov r5, r1
  26015. 800a6c4: d904 bls.n 800a6d0 <_raise_r+0x14>
  26016. 800a6c6: 2316 movs r3, #22
  26017. 800a6c8: 6003 str r3, [r0, #0]
  26018. 800a6ca: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
  26019. 800a6ce: bd38 pop {r3, r4, r5, pc}
  26020. 800a6d0: 6c42 ldr r2, [r0, #68] ; 0x44
  26021. 800a6d2: b112 cbz r2, 800a6da <_raise_r+0x1e>
  26022. 800a6d4: f852 3021 ldr.w r3, [r2, r1, lsl #2]
  26023. 800a6d8: b94b cbnz r3, 800a6ee <_raise_r+0x32>
  26024. 800a6da: 4620 mov r0, r4
  26025. 800a6dc: f000 f830 bl 800a740 <_getpid_r>
  26026. 800a6e0: 462a mov r2, r5
  26027. 800a6e2: 4601 mov r1, r0
  26028. 800a6e4: 4620 mov r0, r4
  26029. 800a6e6: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
  26030. 800a6ea: f000 b817 b.w 800a71c <_kill_r>
  26031. 800a6ee: 2b01 cmp r3, #1
  26032. 800a6f0: d00a beq.n 800a708 <_raise_r+0x4c>
  26033. 800a6f2: 1c59 adds r1, r3, #1
  26034. 800a6f4: d103 bne.n 800a6fe <_raise_r+0x42>
  26035. 800a6f6: 2316 movs r3, #22
  26036. 800a6f8: 6003 str r3, [r0, #0]
  26037. 800a6fa: 2001 movs r0, #1
  26038. 800a6fc: e7e7 b.n 800a6ce <_raise_r+0x12>
  26039. 800a6fe: 2400 movs r4, #0
  26040. 800a700: f842 4025 str.w r4, [r2, r5, lsl #2]
  26041. 800a704: 4628 mov r0, r5
  26042. 800a706: 4798 blx r3
  26043. 800a708: 2000 movs r0, #0
  26044. 800a70a: e7e0 b.n 800a6ce <_raise_r+0x12>
  26045. 0800a70c <raise>:
  26046. 800a70c: 4b02 ldr r3, [pc, #8] ; (800a718 <raise+0xc>)
  26047. 800a70e: 4601 mov r1, r0
  26048. 800a710: 6818 ldr r0, [r3, #0]
  26049. 800a712: f7ff bfd3 b.w 800a6bc <_raise_r>
  26050. 800a716: bf00 nop
  26051. 800a718: 24000184 .word 0x24000184
  26052. 0800a71c <_kill_r>:
  26053. 800a71c: b538 push {r3, r4, r5, lr}
  26054. 800a71e: 4d07 ldr r5, [pc, #28] ; (800a73c <_kill_r+0x20>)
  26055. 800a720: 2300 movs r3, #0
  26056. 800a722: 4604 mov r4, r0
  26057. 800a724: 4608 mov r0, r1
  26058. 800a726: 4611 mov r1, r2
  26059. 800a728: 602b str r3, [r5, #0]
  26060. 800a72a: f7f6 fdaf bl 800128c <_kill>
  26061. 800a72e: 1c43 adds r3, r0, #1
  26062. 800a730: d102 bne.n 800a738 <_kill_r+0x1c>
  26063. 800a732: 682b ldr r3, [r5, #0]
  26064. 800a734: b103 cbz r3, 800a738 <_kill_r+0x1c>
  26065. 800a736: 6023 str r3, [r4, #0]
  26066. 800a738: bd38 pop {r3, r4, r5, pc}
  26067. 800a73a: bf00 nop
  26068. 800a73c: 24002d14 .word 0x24002d14
  26069. 0800a740 <_getpid_r>:
  26070. 800a740: f7f6 bd9c b.w 800127c <_getpid>
  26071. 0800a744 <__sread>:
  26072. 800a744: b510 push {r4, lr}
  26073. 800a746: 460c mov r4, r1
  26074. 800a748: f9b1 100e ldrsh.w r1, [r1, #14]
  26075. 800a74c: f000 f8a0 bl 800a890 <_read_r>
  26076. 800a750: 2800 cmp r0, #0
  26077. 800a752: bfab itete ge
  26078. 800a754: 6d63 ldrge r3, [r4, #84] ; 0x54
  26079. 800a756: 89a3 ldrhlt r3, [r4, #12]
  26080. 800a758: 181b addge r3, r3, r0
  26081. 800a75a: f423 5380 biclt.w r3, r3, #4096 ; 0x1000
  26082. 800a75e: bfac ite ge
  26083. 800a760: 6563 strge r3, [r4, #84] ; 0x54
  26084. 800a762: 81a3 strhlt r3, [r4, #12]
  26085. 800a764: bd10 pop {r4, pc}
  26086. 0800a766 <__swrite>:
  26087. 800a766: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  26088. 800a76a: 461f mov r7, r3
  26089. 800a76c: 898b ldrh r3, [r1, #12]
  26090. 800a76e: 05db lsls r3, r3, #23
  26091. 800a770: 4605 mov r5, r0
  26092. 800a772: 460c mov r4, r1
  26093. 800a774: 4616 mov r6, r2
  26094. 800a776: d505 bpl.n 800a784 <__swrite+0x1e>
  26095. 800a778: f9b1 100e ldrsh.w r1, [r1, #14]
  26096. 800a77c: 2302 movs r3, #2
  26097. 800a77e: 2200 movs r2, #0
  26098. 800a780: f000 f868 bl 800a854 <_lseek_r>
  26099. 800a784: 89a3 ldrh r3, [r4, #12]
  26100. 800a786: f9b4 100e ldrsh.w r1, [r4, #14]
  26101. 800a78a: f423 5380 bic.w r3, r3, #4096 ; 0x1000
  26102. 800a78e: 81a3 strh r3, [r4, #12]
  26103. 800a790: 4632 mov r2, r6
  26104. 800a792: 463b mov r3, r7
  26105. 800a794: 4628 mov r0, r5
  26106. 800a796: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
  26107. 800a79a: f000 b817 b.w 800a7cc <_write_r>
  26108. 0800a79e <__sseek>:
  26109. 800a79e: b510 push {r4, lr}
  26110. 800a7a0: 460c mov r4, r1
  26111. 800a7a2: f9b1 100e ldrsh.w r1, [r1, #14]
  26112. 800a7a6: f000 f855 bl 800a854 <_lseek_r>
  26113. 800a7aa: 1c43 adds r3, r0, #1
  26114. 800a7ac: 89a3 ldrh r3, [r4, #12]
  26115. 800a7ae: bf15 itete ne
  26116. 800a7b0: 6560 strne r0, [r4, #84] ; 0x54
  26117. 800a7b2: f423 5380 biceq.w r3, r3, #4096 ; 0x1000
  26118. 800a7b6: f443 5380 orrne.w r3, r3, #4096 ; 0x1000
  26119. 800a7ba: 81a3 strheq r3, [r4, #12]
  26120. 800a7bc: bf18 it ne
  26121. 800a7be: 81a3 strhne r3, [r4, #12]
  26122. 800a7c0: bd10 pop {r4, pc}
  26123. 0800a7c2 <__sclose>:
  26124. 800a7c2: f9b1 100e ldrsh.w r1, [r1, #14]
  26125. 800a7c6: f000 b813 b.w 800a7f0 <_close_r>
  26126. ...
  26127. 0800a7cc <_write_r>:
  26128. 800a7cc: b538 push {r3, r4, r5, lr}
  26129. 800a7ce: 4d07 ldr r5, [pc, #28] ; (800a7ec <_write_r+0x20>)
  26130. 800a7d0: 4604 mov r4, r0
  26131. 800a7d2: 4608 mov r0, r1
  26132. 800a7d4: 4611 mov r1, r2
  26133. 800a7d6: 2200 movs r2, #0
  26134. 800a7d8: 602a str r2, [r5, #0]
  26135. 800a7da: 461a mov r2, r3
  26136. 800a7dc: f7f6 fd8d bl 80012fa <_write>
  26137. 800a7e0: 1c43 adds r3, r0, #1
  26138. 800a7e2: d102 bne.n 800a7ea <_write_r+0x1e>
  26139. 800a7e4: 682b ldr r3, [r5, #0]
  26140. 800a7e6: b103 cbz r3, 800a7ea <_write_r+0x1e>
  26141. 800a7e8: 6023 str r3, [r4, #0]
  26142. 800a7ea: bd38 pop {r3, r4, r5, pc}
  26143. 800a7ec: 24002d14 .word 0x24002d14
  26144. 0800a7f0 <_close_r>:
  26145. 800a7f0: b538 push {r3, r4, r5, lr}
  26146. 800a7f2: 4d06 ldr r5, [pc, #24] ; (800a80c <_close_r+0x1c>)
  26147. 800a7f4: 2300 movs r3, #0
  26148. 800a7f6: 4604 mov r4, r0
  26149. 800a7f8: 4608 mov r0, r1
  26150. 800a7fa: 602b str r3, [r5, #0]
  26151. 800a7fc: f7f6 fd99 bl 8001332 <_close>
  26152. 800a800: 1c43 adds r3, r0, #1
  26153. 800a802: d102 bne.n 800a80a <_close_r+0x1a>
  26154. 800a804: 682b ldr r3, [r5, #0]
  26155. 800a806: b103 cbz r3, 800a80a <_close_r+0x1a>
  26156. 800a808: 6023 str r3, [r4, #0]
  26157. 800a80a: bd38 pop {r3, r4, r5, pc}
  26158. 800a80c: 24002d14 .word 0x24002d14
  26159. 0800a810 <_fstat_r>:
  26160. 800a810: b538 push {r3, r4, r5, lr}
  26161. 800a812: 4d07 ldr r5, [pc, #28] ; (800a830 <_fstat_r+0x20>)
  26162. 800a814: 2300 movs r3, #0
  26163. 800a816: 4604 mov r4, r0
  26164. 800a818: 4608 mov r0, r1
  26165. 800a81a: 4611 mov r1, r2
  26166. 800a81c: 602b str r3, [r5, #0]
  26167. 800a81e: f7f6 fd94 bl 800134a <_fstat>
  26168. 800a822: 1c43 adds r3, r0, #1
  26169. 800a824: d102 bne.n 800a82c <_fstat_r+0x1c>
  26170. 800a826: 682b ldr r3, [r5, #0]
  26171. 800a828: b103 cbz r3, 800a82c <_fstat_r+0x1c>
  26172. 800a82a: 6023 str r3, [r4, #0]
  26173. 800a82c: bd38 pop {r3, r4, r5, pc}
  26174. 800a82e: bf00 nop
  26175. 800a830: 24002d14 .word 0x24002d14
  26176. 0800a834 <_isatty_r>:
  26177. 800a834: b538 push {r3, r4, r5, lr}
  26178. 800a836: 4d06 ldr r5, [pc, #24] ; (800a850 <_isatty_r+0x1c>)
  26179. 800a838: 2300 movs r3, #0
  26180. 800a83a: 4604 mov r4, r0
  26181. 800a83c: 4608 mov r0, r1
  26182. 800a83e: 602b str r3, [r5, #0]
  26183. 800a840: f7f6 fd93 bl 800136a <_isatty>
  26184. 800a844: 1c43 adds r3, r0, #1
  26185. 800a846: d102 bne.n 800a84e <_isatty_r+0x1a>
  26186. 800a848: 682b ldr r3, [r5, #0]
  26187. 800a84a: b103 cbz r3, 800a84e <_isatty_r+0x1a>
  26188. 800a84c: 6023 str r3, [r4, #0]
  26189. 800a84e: bd38 pop {r3, r4, r5, pc}
  26190. 800a850: 24002d14 .word 0x24002d14
  26191. 0800a854 <_lseek_r>:
  26192. 800a854: b538 push {r3, r4, r5, lr}
  26193. 800a856: 4d07 ldr r5, [pc, #28] ; (800a874 <_lseek_r+0x20>)
  26194. 800a858: 4604 mov r4, r0
  26195. 800a85a: 4608 mov r0, r1
  26196. 800a85c: 4611 mov r1, r2
  26197. 800a85e: 2200 movs r2, #0
  26198. 800a860: 602a str r2, [r5, #0]
  26199. 800a862: 461a mov r2, r3
  26200. 800a864: f7f6 fd8c bl 8001380 <_lseek>
  26201. 800a868: 1c43 adds r3, r0, #1
  26202. 800a86a: d102 bne.n 800a872 <_lseek_r+0x1e>
  26203. 800a86c: 682b ldr r3, [r5, #0]
  26204. 800a86e: b103 cbz r3, 800a872 <_lseek_r+0x1e>
  26205. 800a870: 6023 str r3, [r4, #0]
  26206. 800a872: bd38 pop {r3, r4, r5, pc}
  26207. 800a874: 24002d14 .word 0x24002d14
  26208. 0800a878 <__malloc_lock>:
  26209. 800a878: 4801 ldr r0, [pc, #4] ; (800a880 <__malloc_lock+0x8>)
  26210. 800a87a: f7ff bdff b.w 800a47c <__retarget_lock_acquire_recursive>
  26211. 800a87e: bf00 nop
  26212. 800a880: 24002d0c .word 0x24002d0c
  26213. 0800a884 <__malloc_unlock>:
  26214. 800a884: 4801 ldr r0, [pc, #4] ; (800a88c <__malloc_unlock+0x8>)
  26215. 800a886: f7ff bdfa b.w 800a47e <__retarget_lock_release_recursive>
  26216. 800a88a: bf00 nop
  26217. 800a88c: 24002d0c .word 0x24002d0c
  26218. 0800a890 <_read_r>:
  26219. 800a890: b538 push {r3, r4, r5, lr}
  26220. 800a892: 4d07 ldr r5, [pc, #28] ; (800a8b0 <_read_r+0x20>)
  26221. 800a894: 4604 mov r4, r0
  26222. 800a896: 4608 mov r0, r1
  26223. 800a898: 4611 mov r1, r2
  26224. 800a89a: 2200 movs r2, #0
  26225. 800a89c: 602a str r2, [r5, #0]
  26226. 800a89e: 461a mov r2, r3
  26227. 800a8a0: f7f6 fd0e bl 80012c0 <_read>
  26228. 800a8a4: 1c43 adds r3, r0, #1
  26229. 800a8a6: d102 bne.n 800a8ae <_read_r+0x1e>
  26230. 800a8a8: 682b ldr r3, [r5, #0]
  26231. 800a8aa: b103 cbz r3, 800a8ae <_read_r+0x1e>
  26232. 800a8ac: 6023 str r3, [r4, #0]
  26233. 800a8ae: bd38 pop {r3, r4, r5, pc}
  26234. 800a8b0: 24002d14 .word 0x24002d14
  26235. 0800a8b4 <_init>:
  26236. 800a8b4: b5f8 push {r3, r4, r5, r6, r7, lr}
  26237. 800a8b6: bf00 nop
  26238. 800a8b8: bcf8 pop {r3, r4, r5, r6, r7}
  26239. 800a8ba: bc08 pop {r3}
  26240. 800a8bc: 469e mov lr, r3
  26241. 800a8be: 4770 bx lr
  26242. 0800a8c0 <_fini>:
  26243. 800a8c0: b5f8 push {r3, r4, r5, r6, r7, lr}
  26244. 800a8c2: bf00 nop
  26245. 800a8c4: bcf8 pop {r3, r4, r5, r6, r7}
  26246. 800a8c6: bc08 pop {r3}
  26247. 800a8c8: 469e mov lr, r3
  26248. 800a8ca: 4770 bx lr