stm32h7xx_ll_exti.c 16 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32h7xx_ll_exti.c
  4. * @author MCD Application Team
  5. * @brief EXTI LL module driver.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * Copyright (c) 2017 STMicroelectronics.
  10. * All rights reserved.
  11. *
  12. * This software is licensed under terms that can be found in the LICENSE file
  13. * in the root directory of this software component.
  14. * If no LICENSE file comes with this software, it is provided AS-IS.
  15. *
  16. ******************************************************************************
  17. */
  18. #if defined(USE_FULL_LL_DRIVER)
  19. /* Includes ------------------------------------------------------------------*/
  20. #include "stm32h7xx_ll_exti.h"
  21. #ifdef USE_FULL_ASSERT
  22. #include "stm32_assert.h"
  23. #else
  24. #define assert_param(expr) ((void)0U)
  25. #endif
  26. /** @addtogroup STM32H7xx_LL_Driver
  27. * @{
  28. */
  29. #if defined (EXTI)
  30. /** @defgroup EXTI_LL EXTI
  31. * @{
  32. */
  33. /* Private types -------------------------------------------------------------*/
  34. /* Private variables ---------------------------------------------------------*/
  35. /* Private constants ---------------------------------------------------------*/
  36. /* Private macros ------------------------------------------------------------*/
  37. /** @addtogroup EXTI_LL_Private_Macros
  38. * @{
  39. */
  40. #define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
  41. #define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
  42. #define IS_LL_EXTI_LINE_64_95(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U)
  43. #define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
  44. || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
  45. || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
  46. #define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
  47. || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
  48. || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
  49. || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
  50. /**
  51. * @}
  52. */
  53. /* Private function prototypes -----------------------------------------------*/
  54. /* Exported functions --------------------------------------------------------*/
  55. /** @addtogroup EXTI_LL_Exported_Functions
  56. * @{
  57. */
  58. /** @addtogroup EXTI_LL_EF_Init
  59. * @{
  60. */
  61. /**
  62. * @brief De-initialize the EXTI registers to their default reset values.
  63. * @retval An ErrorStatus enumeration value:
  64. * - SUCCESS: EXTI registers are de-initialized
  65. * - ERROR: not applicable
  66. */
  67. ErrorStatus LL_EXTI_DeInit(void)
  68. {
  69. /* Rising Trigger selection register set to default reset values */
  70. LL_EXTI_WriteReg(RTSR1, 0x00000000U);
  71. LL_EXTI_WriteReg(RTSR2, 0x00000000U);
  72. LL_EXTI_WriteReg(RTSR3, 0x00000000U);
  73. /* Falling Trigger selection register set to default reset values */
  74. LL_EXTI_WriteReg(FTSR1, 0x00000000U);
  75. LL_EXTI_WriteReg(FTSR2, 0x00000000U);
  76. LL_EXTI_WriteReg(FTSR3, 0x00000000U);
  77. /* Software interrupt event register set to default reset values */
  78. LL_EXTI_WriteReg(SWIER1, 0x00000000U);
  79. LL_EXTI_WriteReg(SWIER2, 0x00000000U);
  80. LL_EXTI_WriteReg(SWIER3, 0x00000000U);
  81. /* D3 Pending register set to default reset values */
  82. LL_EXTI_WriteReg(D3PMR1, 0x00000000U);
  83. LL_EXTI_WriteReg(D3PMR2, 0x00000000U);
  84. LL_EXTI_WriteReg(D3PMR3, 0x00000000U);
  85. /* D3 Pending clear selection register low to default reset values */
  86. LL_EXTI_WriteReg(D3PCR1L, 0x00000000U);
  87. LL_EXTI_WriteReg(D3PCR2L, 0x00000000U);
  88. LL_EXTI_WriteReg(D3PCR3L, 0x00000000U);
  89. /* D3 Pending clear selection register high to default reset values */
  90. LL_EXTI_WriteReg(D3PCR1H, 0x00000000U);
  91. LL_EXTI_WriteReg(D3PCR2H, 0x00000000U);
  92. LL_EXTI_WriteReg(D3PCR3H, 0x00000000U);
  93. /* Interrupt mask register reset */
  94. LL_EXTI_WriteReg(IMR1, 0x00000000U);
  95. LL_EXTI_WriteReg(IMR2, 0x00000000U);
  96. LL_EXTI_WriteReg(IMR3, 0x00000000U);
  97. /* Event mask register reset */
  98. LL_EXTI_WriteReg(EMR1, 0x00000000U);
  99. LL_EXTI_WriteReg(EMR2, 0x00000000U);
  100. LL_EXTI_WriteReg(EMR3, 0x00000000U);
  101. /* Clear Pending requests */
  102. LL_EXTI_WriteReg(PR1, EXTI_PR1_PR_Msk);
  103. LL_EXTI_WriteReg(PR2, EXTI_PR2_PR_Msk);
  104. LL_EXTI_WriteReg(PR3, EXTI_PR3_PR_Msk);
  105. #if defined(DUAL_CORE)
  106. /* Interrupt mask register set to default reset values for Core 2 (Coretx-M4)*/
  107. LL_EXTI_WriteReg(C2IMR1, 0x00000000U);
  108. LL_EXTI_WriteReg(C2IMR2, 0x00000000U);
  109. LL_EXTI_WriteReg(C2IMR3, 0x00000000U);
  110. /* Event mask register set to default reset values */
  111. LL_EXTI_WriteReg(C2EMR1, 0x00000000U);
  112. LL_EXTI_WriteReg(C2EMR2, 0x00000000U);
  113. LL_EXTI_WriteReg(C2EMR3, 0x00000000U);
  114. /* Clear Pending requests */
  115. LL_EXTI_WriteReg(C2PR1, EXTI_PR1_PR_Msk);
  116. LL_EXTI_WriteReg(C2PR2, EXTI_PR2_PR_Msk);
  117. LL_EXTI_WriteReg(C2PR3, EXTI_PR3_PR_Msk);
  118. #endif /* DUAL_CORE*/
  119. return SUCCESS;
  120. }
  121. /**
  122. * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
  123. * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
  124. * @retval An ErrorStatus enumeration value:
  125. * - SUCCESS: EXTI registers are initialized
  126. * - ERROR: not applicable
  127. */
  128. ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
  129. {
  130. ErrorStatus status = SUCCESS;
  131. /* Check the parameters */
  132. assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
  133. assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
  134. assert_param(IS_LL_EXTI_LINE_64_95(EXTI_InitStruct->Line_64_95));
  135. assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
  136. assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
  137. /* ENABLE LineCommand */
  138. if (EXTI_InitStruct->LineCommand != DISABLE)
  139. {
  140. assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
  141. /* Configure EXTI Lines in range from 0 to 31 */
  142. if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
  143. {
  144. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
  145. {
  146. /* Enable IT on provided Lines for Cortex-M7*/
  147. LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
  148. }
  149. else
  150. {
  151. /* Disable IT on provided Lines for Cortex-M7*/
  152. LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
  153. }
  154. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
  155. {
  156. /* Enable event on provided Lines for Cortex-M7 */
  157. LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
  158. }
  159. else
  160. {
  161. /* Disable event on provided Lines for Cortex-M7 */
  162. LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
  163. }
  164. #if defined(DUAL_CORE)
  165. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
  166. {
  167. /* Enable IT on provided Lines for Cortex-M4 */
  168. LL_C2_EXTI_EnableIT_0_31 (EXTI_InitStruct->Line_0_31);
  169. }
  170. else
  171. {
  172. /* Disable IT on provided Lines for Cortex-M4*/
  173. LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
  174. }
  175. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
  176. {
  177. /* Enable event on provided Lines for Cortex-M4 */
  178. LL_C2_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
  179. }
  180. else
  181. {
  182. /* Disable event on provided Lines for Cortex-M4*/
  183. LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
  184. }
  185. #endif /* DUAL_CORE */
  186. if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
  187. {
  188. switch (EXTI_InitStruct->Trigger)
  189. {
  190. case LL_EXTI_TRIGGER_RISING:
  191. /* First Disable Falling Trigger on provided Lines */
  192. LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
  193. /* Then Enable Rising Trigger on provided Lines */
  194. LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
  195. break;
  196. case LL_EXTI_TRIGGER_FALLING:
  197. /* First Disable Rising Trigger on provided Lines */
  198. LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
  199. /* Then Enable Falling Trigger on provided Lines */
  200. LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
  201. break;
  202. case LL_EXTI_TRIGGER_RISING_FALLING:
  203. LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
  204. LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
  205. break;
  206. default:
  207. status = ERROR;
  208. break;
  209. }
  210. }
  211. }
  212. /* Configure EXTI Lines in range from 32 to 63 */
  213. if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
  214. {
  215. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
  216. {
  217. /* Enable IT on provided Lines for Cortex-M7*/
  218. LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
  219. }
  220. else
  221. {
  222. /* Disable IT on provided Lines for Cortex-M7*/
  223. LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
  224. }
  225. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
  226. {
  227. /* Enable event on provided Lines for Cortex-M7 */
  228. LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
  229. }
  230. else
  231. {
  232. /* Disable event on provided Lines for Cortex-M7 */
  233. LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
  234. }
  235. #if defined(DUAL_CORE)
  236. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
  237. {
  238. /* Enable IT on provided Lines for Cortex-M4 */
  239. LL_C2_EXTI_EnableIT_32_63 (EXTI_InitStruct->Line_32_63);
  240. }
  241. else
  242. {
  243. /* Disable IT on provided Lines for Cortex-M4 */
  244. LL_C2_EXTI_DisableIT_32_63 (EXTI_InitStruct->Line_32_63);
  245. }
  246. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
  247. {
  248. /* Enable event on provided Lines for Cortex-M4 */
  249. LL_C2_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
  250. }
  251. else
  252. {
  253. /* Disable event on provided Lines for Cortex-M4 */
  254. LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
  255. }
  256. #endif /* DUAL_CORE */
  257. if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
  258. {
  259. switch (EXTI_InitStruct->Trigger)
  260. {
  261. case LL_EXTI_TRIGGER_RISING:
  262. /* First Disable Falling Trigger on provided Lines */
  263. LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
  264. /* Then Enable IT on provided Lines */
  265. LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
  266. break;
  267. case LL_EXTI_TRIGGER_FALLING:
  268. /* First Disable Rising Trigger on provided Lines */
  269. LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
  270. /* Then Enable Falling Trigger on provided Lines */
  271. LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
  272. break;
  273. case LL_EXTI_TRIGGER_RISING_FALLING:
  274. LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
  275. LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
  276. break;
  277. default:
  278. status = ERROR;
  279. break;
  280. }
  281. }
  282. }
  283. /* Configure EXTI Lines in range from 64 to 95 */
  284. if (EXTI_InitStruct->Line_64_95 != LL_EXTI_LINE_NONE)
  285. {
  286. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
  287. {
  288. /* Enable IT on provided Lines for Cortex-M7*/
  289. LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95);
  290. }
  291. else
  292. {
  293. /* Disable IT on provided Lines for Cortex-M7*/
  294. LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
  295. }
  296. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
  297. {
  298. /* Enable event on provided Lines for Cortex-M7 */
  299. LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
  300. }
  301. else
  302. {
  303. /* Disable event on provided Lines for Cortex-M7 */
  304. LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
  305. }
  306. #if defined(DUAL_CORE)
  307. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
  308. {
  309. /* Enable IT on provided Lines for Cortex-M4 */
  310. LL_C2_EXTI_EnableIT_64_95 (EXTI_InitStruct->Line_64_95);
  311. }
  312. else
  313. {
  314. /* Disable IT on provided Lines for Cortex-M4 */
  315. LL_C2_EXTI_DisableIT_64_95 (EXTI_InitStruct->Line_64_95);
  316. }
  317. if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
  318. {
  319. /* Enable event on provided Lines for Cortex-M4 */
  320. LL_C2_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
  321. }
  322. else
  323. {
  324. /* Disable event on provided Lines for Cortex-M4 */
  325. LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
  326. }
  327. #endif /* DUAL_CORE */
  328. if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
  329. {
  330. switch (EXTI_InitStruct->Trigger)
  331. {
  332. case LL_EXTI_TRIGGER_RISING:
  333. /* First Disable Falling Trigger on provided Lines */
  334. LL_EXTI_DisableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
  335. /* Then Enable IT on provided Lines */
  336. LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
  337. break;
  338. case LL_EXTI_TRIGGER_FALLING:
  339. /* First Disable Rising Trigger on provided Lines */
  340. LL_EXTI_DisableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
  341. /* Then Enable Falling Trigger on provided Lines */
  342. LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
  343. break;
  344. case LL_EXTI_TRIGGER_RISING_FALLING:
  345. LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
  346. LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
  347. break;
  348. default:
  349. status = ERROR;
  350. break;
  351. }
  352. }
  353. }
  354. }
  355. else /* DISABLE LineCommand */
  356. {
  357. /* Disable IT on provided Lines for Cortex-M7*/
  358. LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
  359. LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
  360. LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
  361. /* Disable event on provided Lines for Cortex-M7 */
  362. LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
  363. LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
  364. LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
  365. #if defined(DUAL_CORE)
  366. /* Disable IT on provided Lines for Cortex-M4*/
  367. LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
  368. LL_C2_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
  369. LL_C2_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
  370. /* Disable event on provided Lines for Cortex-M4 */
  371. LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
  372. LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
  373. LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
  374. #endif /* DUAL_CORE */
  375. }
  376. return status;
  377. }
  378. /**
  379. * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
  380. * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
  381. * @retval None
  382. */
  383. void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
  384. {
  385. EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
  386. EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE;
  387. EXTI_InitStruct->Line_64_95 = LL_EXTI_LINE_NONE;
  388. EXTI_InitStruct->LineCommand = DISABLE;
  389. EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
  390. EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
  391. }
  392. /**
  393. * @}
  394. */
  395. /**
  396. * @}
  397. */
  398. /**
  399. * @}
  400. */
  401. #endif /* defined (EXTI) */
  402. /**
  403. * @}
  404. */
  405. #endif /* USE_FULL_LL_DRIVER */